system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <stdio.h>
#include <time.h>
#include <stdlib.h>
#include <sys/time.h>
#define N 8388608
#define BLOCK_DIM 256
//Kernel
__global__ void reduction(int * in, int * out){
int globalid = blockIdx.x*blockDim.x + threadIdx.x;
__shared__ int s_array[BLOCK_DIM];
s_array[threadIdx.x] = in[globalid];
__syncthreads();
for (int i = 1; i < blockDim.x; i *= 2){
if (threadIdx.x % (2*i) == 0){
s_array[threadIdx.x] += s_array[threadIdx.x+i];
}
__syncthreads();
}
if (threadIdx.x == 0)
out[blockIdx.x] = s_array[0];
}
int main(){
struct timeval t1, t2;
int *hArray;
int hReduction;
int *dIn, *dOut; //Device Arrays
//Reserva de memoria Host
hArray = (int*)malloc(N*sizeof(int));
//Inicialización del vector
srand(time(NULL));
for (int i = 0; i < N; i++){
hArray[i] = ((float)rand()/RAND_MAX)*200 - 100;
}
//Reserva de memoria Device
cudaMalloc((void **)&dIn, N*sizeof(int));
cudaMalloc((void **)&dOut, (N/BLOCK_DIM)*sizeof(int));
//Copia de memoria Host->Device
cudaMemcpy(dIn, hArray, N*sizeof(int), cudaMemcpyHostToDevice);
int *aux;
int block_dim_stage = BLOCK_DIM;
int blocks;
gettimeofday(&t1, 0);
//Reducción por etapas
for(int left = N; left > 1; left /= block_dim_stage){
if(left < block_dim_stage)
block_dim_stage = left;
blocks = left / block_dim_stage;
cudaDeviceSynchronize();
reduction<<<blocks, block_dim_stage>>>(dIn, dOut);
aux = dIn;
dIn = dOut;
dOut = aux;
}
cudaDeviceSynchronize();
gettimeofday(&t2, 0);
//Copia de memoria Device->Host
cudaMemcpy(&hReduction, dIn, sizeof(int), cudaMemcpyDeviceToHost);
//Comprobación de errores
int hReduction2 = 0;
for(int i = 0; i < N; i++){
hReduction2 += hArray[i];
}
if(hReduction != hReduction2)
printf("Error\n");
else
printf("Correcto\n");
double time = (1000000.0*(t2.tv_sec-t1.tv_sec) + t2.tv_usec-t1.tv_usec)/1000.0;
printf("Tiempo: %f ms\n", time);
printf("Reducción = %d\n", hReduction);
//Liberar memoria Host y Device
free(hArray);
cudaFree(dIn);
cudaFree(dOut);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
#include <stdlib.h>
#include <sys/time.h>
#define N 8388608
#define BLOCK_DIM 256
//Kernel
__global__ void reduction(int * in, int * out){
int globalid = blockIdx.x*blockDim.x + threadIdx.x;
__shared__ int s_array[BLOCK_DIM];
s_array[threadIdx.x] = in[globalid];
__syncthreads();
for (int i = 1; i < blockDim.x; i *= 2){
if (threadIdx.x % (2*i) == 0){
s_array[threadIdx.x] += s_array[threadIdx.x+i];
}
__syncthreads();
}
if (threadIdx.x == 0)
out[blockIdx.x] = s_array[0];
}
int main(){
struct timeval t1, t2;
int *hArray;
int hReduction;
int *dIn, *dOut; //Device Arrays
//Reserva de memoria Host
hArray = (int*)malloc(N*sizeof(int));
//Inicialización del vector
srand(time(NULL));
for (int i = 0; i < N; i++){
hArray[i] = ((float)rand()/RAND_MAX)*200 - 100;
}
//Reserva de memoria Device
hipMalloc((void **)&dIn, N*sizeof(int));
hipMalloc((void **)&dOut, (N/BLOCK_DIM)*sizeof(int));
//Copia de memoria Host->Device
hipMemcpy(dIn, hArray, N*sizeof(int), hipMemcpyHostToDevice);
int *aux;
int block_dim_stage = BLOCK_DIM;
int blocks;
gettimeofday(&t1, 0);
//Reducción por etapas
for(int left = N; left > 1; left /= block_dim_stage){
if(left < block_dim_stage)
block_dim_stage = left;
blocks = left / block_dim_stage;
hipDeviceSynchronize();
reduction<<<blocks, block_dim_stage>>>(dIn, dOut);
aux = dIn;
dIn = dOut;
dOut = aux;
}
hipDeviceSynchronize();
gettimeofday(&t2, 0);
//Copia de memoria Device->Host
hipMemcpy(&hReduction, dIn, sizeof(int), hipMemcpyDeviceToHost);
//Comprobación de errores
int hReduction2 = 0;
for(int i = 0; i < N; i++){
hReduction2 += hArray[i];
}
if(hReduction != hReduction2)
printf("Error\n");
else
printf("Correcto\n");
double time = (1000000.0*(t2.tv_sec-t1.tv_sec) + t2.tv_usec-t1.tv_usec)/1000.0;
printf("Tiempo: %f ms\n", time);
printf("Reducción = %d\n", hReduction);
//Liberar memoria Host y Device
free(hArray);
hipFree(dIn);
hipFree(dOut);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
#include <stdlib.h>
#include <sys/time.h>
#define N 8388608
#define BLOCK_DIM 256
//Kernel
__global__ void reduction(int * in, int * out){
int globalid = blockIdx.x*blockDim.x + threadIdx.x;
__shared__ int s_array[BLOCK_DIM];
s_array[threadIdx.x] = in[globalid];
__syncthreads();
for (int i = 1; i < blockDim.x; i *= 2){
if (threadIdx.x % (2*i) == 0){
s_array[threadIdx.x] += s_array[threadIdx.x+i];
}
__syncthreads();
}
if (threadIdx.x == 0)
out[blockIdx.x] = s_array[0];
}
int main(){
struct timeval t1, t2;
int *hArray;
int hReduction;
int *dIn, *dOut; //Device Arrays
//Reserva de memoria Host
hArray = (int*)malloc(N*sizeof(int));
//Inicialización del vector
srand(time(NULL));
for (int i = 0; i < N; i++){
hArray[i] = ((float)rand()/RAND_MAX)*200 - 100;
}
//Reserva de memoria Device
hipMalloc((void **)&dIn, N*sizeof(int));
hipMalloc((void **)&dOut, (N/BLOCK_DIM)*sizeof(int));
//Copia de memoria Host->Device
hipMemcpy(dIn, hArray, N*sizeof(int), hipMemcpyHostToDevice);
int *aux;
int block_dim_stage = BLOCK_DIM;
int blocks;
gettimeofday(&t1, 0);
//Reducción por etapas
for(int left = N; left > 1; left /= block_dim_stage){
if(left < block_dim_stage)
block_dim_stage = left;
blocks = left / block_dim_stage;
hipDeviceSynchronize();
reduction<<<blocks, block_dim_stage>>>(dIn, dOut);
aux = dIn;
dIn = dOut;
dOut = aux;
}
hipDeviceSynchronize();
gettimeofday(&t2, 0);
//Copia de memoria Device->Host
hipMemcpy(&hReduction, dIn, sizeof(int), hipMemcpyDeviceToHost);
//Comprobación de errores
int hReduction2 = 0;
for(int i = 0; i < N; i++){
hReduction2 += hArray[i];
}
if(hReduction != hReduction2)
printf("Error\n");
else
printf("Correcto\n");
double time = (1000000.0*(t2.tv_sec-t1.tv_sec) + t2.tv_usec-t1.tv_usec)/1000.0;
printf("Tiempo: %f ms\n", time);
printf("Reducción = %d\n", hReduction);
//Liberar memoria Host y Device
free(hArray);
hipFree(dIn);
hipFree(dOut);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9reductionPiS_
.globl _Z9reductionPiS_
.p2align 8
.type _Z9reductionPiS_,@function
_Z9reductionPiS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_cmp_lt_u32 s3, 2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
s_mov_b32 s5, 1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s6
s_cmp_ge_u32 s4, s3
s_mov_b32 s5, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
.LBB0_3:
s_lshl_b32 s4, s5, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s4, -1
v_and_b32_e32 v2, s6, v0
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_2
v_add_lshl_u32 v2, s5, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB0_2
.LBB0_5:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9reductionPiS_
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9reductionPiS_, .Lfunc_end0-_Z9reductionPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9reductionPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9reductionPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
#include <stdlib.h>
#include <sys/time.h>
#define N 8388608
#define BLOCK_DIM 256
//Kernel
__global__ void reduction(int * in, int * out){
int globalid = blockIdx.x*blockDim.x + threadIdx.x;
__shared__ int s_array[BLOCK_DIM];
s_array[threadIdx.x] = in[globalid];
__syncthreads();
for (int i = 1; i < blockDim.x; i *= 2){
if (threadIdx.x % (2*i) == 0){
s_array[threadIdx.x] += s_array[threadIdx.x+i];
}
__syncthreads();
}
if (threadIdx.x == 0)
out[blockIdx.x] = s_array[0];
}
int main(){
struct timeval t1, t2;
int *hArray;
int hReduction;
int *dIn, *dOut; //Device Arrays
//Reserva de memoria Host
hArray = (int*)malloc(N*sizeof(int));
//Inicialización del vector
srand(time(NULL));
for (int i = 0; i < N; i++){
hArray[i] = ((float)rand()/RAND_MAX)*200 - 100;
}
//Reserva de memoria Device
hipMalloc((void **)&dIn, N*sizeof(int));
hipMalloc((void **)&dOut, (N/BLOCK_DIM)*sizeof(int));
//Copia de memoria Host->Device
hipMemcpy(dIn, hArray, N*sizeof(int), hipMemcpyHostToDevice);
int *aux;
int block_dim_stage = BLOCK_DIM;
int blocks;
gettimeofday(&t1, 0);
//Reducción por etapas
for(int left = N; left > 1; left /= block_dim_stage){
if(left < block_dim_stage)
block_dim_stage = left;
blocks = left / block_dim_stage;
hipDeviceSynchronize();
reduction<<<blocks, block_dim_stage>>>(dIn, dOut);
aux = dIn;
dIn = dOut;
dOut = aux;
}
hipDeviceSynchronize();
gettimeofday(&t2, 0);
//Copia de memoria Device->Host
hipMemcpy(&hReduction, dIn, sizeof(int), hipMemcpyDeviceToHost);
//Comprobación de errores
int hReduction2 = 0;
for(int i = 0; i < N; i++){
hReduction2 += hArray[i];
}
if(hReduction != hReduction2)
printf("Error\n");
else
printf("Correcto\n");
double time = (1000000.0*(t2.tv_sec-t1.tv_sec) + t2.tv_usec-t1.tv_usec)/1000.0;
printf("Tiempo: %f ms\n", time);
printf("Reducción = %d\n", hReduction);
//Liberar memoria Host y Device
free(hArray);
hipFree(dIn);
hipFree(dOut);
} | .text
.file "reduction_with_BC.hip"
.globl _Z24__device_stub__reductionPiS_ # -- Begin function _Z24__device_stub__reductionPiS_
.p2align 4, 0x90
.type _Z24__device_stub__reductionPiS_,@function
_Z24__device_stub__reductionPiS_: # @_Z24__device_stub__reductionPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9reductionPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__reductionPiS_, .Lfunc_end0-_Z24__device_stub__reductionPiS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI1_1:
.long 0x43480000 # float 200
.LCPI1_2:
.long 0xc2c80000 # float -100
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_3:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI1_4:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $33554432, %edi # imm = 0x2000000
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
mulss .LCPI1_1(%rip), %xmm0
addss .LCPI1_2(%rip), %xmm0
cvttss2si %xmm0, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $8388608, %r14 # imm = 0x800000
jne .LBB1_1
# %bb.2:
movabsq $4294967296, %r12 # imm = 0x100000000
movq %rsp, %rdi
movl $33554432, %esi # imm = 0x2000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $131072, %esi # imm = 0x20000
callq hipMalloc
movq (%rsp), %rdi
movl $33554432, %edx # imm = 0x2000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 104(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl $8388608, %r14d # imm = 0x800000
movl $256, %r13d # imm = 0x100
leaq 56(%rsp), %rbp
leaq 32(%rsp), %r15
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_3 Depth=1
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rcx, (%rsp)
movq %rax, 8(%rsp)
cmpl $1, %r14d
jbe .LBB1_6
.LBB1_3: # =>This Inner Loop Header: Depth=1
cmpl %r13d, %r14d
cmovll %r14d, %r13d
movl %r14d, %eax
xorl %edx, %edx
divl %r13d
movl %eax, %r14d
callq hipDeviceSynchronize
movq %r14, %rdi
orq %r12, %rdi
movq %r13, %rdx
orq %r12, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_3 Depth=1
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
leaq 96(%rsp), %rax
movq %rax, 32(%rsp)
leaq 88(%rsp), %rax
movq %rax, 40(%rsp)
leaq 16(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
movl $_Z9reductionPiS_, %edi
movq %r15, %r9
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_5
.LBB1_6:
callq hipDeviceSynchronize
xorl %r14d, %r14d
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rsi
leaq 16(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
addl (%rbx,%r14,4), %eax
incq %r14
cmpq $8388608, %r14 # imm = 0x800000
jne .LBB1_7
# %bb.8:
cmpl %eax, 16(%rsp)
movl $.Lstr, %eax
movl $.Lstr.1, %edi
cmoveq %rax, %rdi
callq puts@PLT
movq 32(%rsp), %rax
subq 104(%rsp), %rax
cvtsi2sd %rax, %xmm1
mulsd .LCPI1_3(%rip), %xmm1
cvtsi2sdq 40(%rsp), %xmm0
cvtsi2sdq 112(%rsp), %xmm2
addsd %xmm1, %xmm0
subsd %xmm2, %xmm0
divsd .LCPI1_4(%rip), %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movl 16(%rsp), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9reductionPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9reductionPiS_,@object # @_Z9reductionPiS_
.section .rodata,"a",@progbits
.globl _Z9reductionPiS_
.p2align 3, 0x0
_Z9reductionPiS_:
.quad _Z24__device_stub__reductionPiS_
.size _Z9reductionPiS_, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Tiempo: %f ms\n"
.size .L.str.2, 15
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Reducci\303\263n = %d\n"
.size .L.str.3, 17
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9reductionPiS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Correcto"
.size .Lstr, 9
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Error"
.size .Lstr.1, 6
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__reductionPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9reductionPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9reductionPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R6, c[0x0][0x0], R7 ; /* 0x0000000006027a24 */
/* 0x001fca00078e0207 */
/*0060*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0203 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0090*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc80003f05270 */
/*00a0*/ ISETP.GE.U32.AND P1, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f26070 */
/*00b0*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */
/* 0x0041e80000004800 */
/*00c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*00d0*/ @!P1 BRA 0x2c0 ; /* 0x000001e000009947 */
/* 0x000fea0003800000 */
/*00e0*/ SHF.L.U32 R0, R7, 0x2, RZ ; /* 0x0000000207007819 */
/* 0x001fe200000006ff */
/*00f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fca00078e00ff */
/*0100*/ SHF.L.U32 R10, R5, 0x1, RZ ; /* 0x00000001050a7819 */
/* 0x000fc800000006ff */
/*0110*/ I2F.U32.RP R4, R10 ; /* 0x0000000a00047306 */
/* 0x000e220000209000 */
/*0120*/ IMAD.MOV R9, RZ, RZ, -R10 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a0a */
/*0130*/ ISETP.NE.U32.AND P2, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fcc0003f45070 */
/*0140*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0150*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0160*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0170*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*0180*/ IMAD R9, R9, R3, RZ ; /* 0x0000000309097224 */
/* 0x002fd200078e02ff */
/*0190*/ IMAD.HI.U32 R3, R3, R9, R2 ; /* 0x0000000903037227 */
/* 0x000fcc00078e0002 */
/*01a0*/ IMAD.HI.U32 R3, R3, R7, RZ ; /* 0x0000000703037227 */
/* 0x000fc800078e00ff */
/*01b0*/ IMAD.MOV R8, RZ, RZ, -R3 ; /* 0x000000ffff087224 */
/* 0x000fc800078e0a03 */
/*01c0*/ IMAD R3, R10, R8, R7 ; /* 0x000000080a037224 */
/* 0x000fca00078e0207 */
/*01d0*/ ISETP.GE.U32.AND P1, PT, R3, R10, PT ; /* 0x0000000a0300720c */
/* 0x000fda0003f26070 */
/*01e0*/ @P1 IADD3 R3, -R10, R3, RZ ; /* 0x000000030a031210 */
/* 0x000fc80007ffe1ff */
/*01f0*/ ISETP.GE.U32.AND P1, PT, R3, R10, PT ; /* 0x0000000a0300720c */
/* 0x000fda0003f26070 */
/*0200*/ @P1 IMAD.IADD R3, R3, 0x1, -R10 ; /* 0x0000000103031824 */
/* 0x000fe200078e0a0a */
/*0210*/ @!P2 LOP3.LUT R3, RZ, R10, RZ, 0x33, !PT ; /* 0x0000000aff03a212 */
/* 0x000fc800078e33ff */
/*0220*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*0230*/ @!P1 LEA R2, R5, R0, 0x2 ; /* 0x0000000005029211 */
/* 0x000fe200078e10ff */
/*0240*/ @!P1 LDS R3, [R7.X4] ; /* 0x0000000007039984 */
/* 0x000fe20000004800 */
/*0250*/ MOV R5, R10 ; /* 0x0000000a00057202 */
/* 0x000fc80000000f00 */
/*0260*/ @!P1 LDS R2, [R2] ; /* 0x0000000002029984 */
/* 0x000e240000000800 */
/*0270*/ @!P1 IMAD.IADD R3, R3, 0x1, R2 ; /* 0x0000000103039824 */
/* 0x001fca00078e0202 */
/*0280*/ @!P1 STS [R7.X4], R3 ; /* 0x0000000307009388 */
/* 0x0001e80000004800 */
/*0290*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02a0*/ ISETP.GE.U32.AND P1, PT, R10, c[0x0][0x0], PT ; /* 0x000000000a007a0c */
/* 0x000fda0003f26070 */
/*02b0*/ @!P1 BRA 0x100 ; /* 0xfffffe4000009947 */
/* 0x001fea000383ffff */
/*02c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*02d0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*02e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*02f0*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fca00078e0003 */
/*0300*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0310*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0320*/ BRA 0x320; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9reductionPiS_
.globl _Z9reductionPiS_
.p2align 8
.type _Z9reductionPiS_,@function
_Z9reductionPiS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_cmp_lt_u32 s3, 2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
s_mov_b32 s5, 1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s6
s_cmp_ge_u32 s4, s3
s_mov_b32 s5, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
.LBB0_3:
s_lshl_b32 s4, s5, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s4, -1
v_and_b32_e32 v2, s6, v0
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_2
v_add_lshl_u32 v2, s5, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB0_2
.LBB0_5:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9reductionPiS_
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9reductionPiS_, .Lfunc_end0-_Z9reductionPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9reductionPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9reductionPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000cc948_00000000-6_reduction_with_BC.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9reductionPiS_PiS_
.type _Z30__device_stub__Z9reductionPiS_PiS_, @function
_Z30__device_stub__Z9reductionPiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9reductionPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z9reductionPiS_PiS_, .-_Z30__device_stub__Z9reductionPiS_PiS_
.globl _Z9reductionPiS_
.type _Z9reductionPiS_, @function
_Z9reductionPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9reductionPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9reductionPiS_, .-_Z9reductionPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Error\n"
.LC4:
.string "Correcto\n"
.LC7:
.string "Tiempo: %f ms\n"
.LC8:
.string "Reducci\303\263n = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $33554432, %edi
call malloc@PLT
movq %rax, %r13
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %r13, %rbx
leaq 33554432(%r13), %r12
movq %r13, %rbp
.L12:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
mulss .LC1(%rip), %xmm0
subss .LC2(%rip), %xmm0
cvttss2sil %xmm0, %eax
movl %eax, 0(%rbp)
addq $4, %rbp
cmpq %r12, %rbp
jne .L12
movq %rsp, %rdi
movl $33554432, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $131072, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $33554432, %edx
movq %r13, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $8388608, %r14d
movl $256, %ebp
jmp .L14
.L13:
movq (%rsp), %rax
movq 8(%rsp), %rdx
movq %rdx, (%rsp)
movq %rax, 8(%rsp)
cmpl $1, %r15d
jle .L23
.L14:
cmpl %r14d, %ebp
cmovg %r14d, %ebp
movl %r14d, %eax
cltd
idivl %ebp
movl %eax, %r15d
movl %eax, %r14d
call cudaDeviceSynchronize@PLT
movl %ebp, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl %r15d, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z30__device_stub__Z9reductionPiS_PiS_
jmp .L13
.L23:
call cudaDeviceSynchronize@PLT
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
leaq 20(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %edx
.L15:
movl %edx, %eax
addl (%rbx), %eax
movl %eax, %edx
addq $4, %rbx
cmpq %r12, %rbx
jne .L15
cmpl %eax, 20(%rsp)
je .L16
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L17:
movq 48(%rsp), %rax
subq 32(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC5(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 56(%rsp), %xmm1
addsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 40(%rsp), %xmm1
subsd %xmm1, %xmm0
divsd .LC6(%rip), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 20(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L17
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z9reductionPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z9reductionPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.align 4
.LC1:
.long 1128792064
.align 4
.LC2:
.long 1120403456
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1093567616
.align 8
.LC6:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "reduction_with_BC.hip"
.globl _Z24__device_stub__reductionPiS_ # -- Begin function _Z24__device_stub__reductionPiS_
.p2align 4, 0x90
.type _Z24__device_stub__reductionPiS_,@function
_Z24__device_stub__reductionPiS_: # @_Z24__device_stub__reductionPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9reductionPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__reductionPiS_, .Lfunc_end0-_Z24__device_stub__reductionPiS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI1_1:
.long 0x43480000 # float 200
.LCPI1_2:
.long 0xc2c80000 # float -100
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_3:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI1_4:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $33554432, %edi # imm = 0x2000000
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
mulss .LCPI1_1(%rip), %xmm0
addss .LCPI1_2(%rip), %xmm0
cvttss2si %xmm0, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $8388608, %r14 # imm = 0x800000
jne .LBB1_1
# %bb.2:
movabsq $4294967296, %r12 # imm = 0x100000000
movq %rsp, %rdi
movl $33554432, %esi # imm = 0x2000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $131072, %esi # imm = 0x20000
callq hipMalloc
movq (%rsp), %rdi
movl $33554432, %edx # imm = 0x2000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 104(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl $8388608, %r14d # imm = 0x800000
movl $256, %r13d # imm = 0x100
leaq 56(%rsp), %rbp
leaq 32(%rsp), %r15
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_3 Depth=1
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rcx, (%rsp)
movq %rax, 8(%rsp)
cmpl $1, %r14d
jbe .LBB1_6
.LBB1_3: # =>This Inner Loop Header: Depth=1
cmpl %r13d, %r14d
cmovll %r14d, %r13d
movl %r14d, %eax
xorl %edx, %edx
divl %r13d
movl %eax, %r14d
callq hipDeviceSynchronize
movq %r14, %rdi
orq %r12, %rdi
movq %r13, %rdx
orq %r12, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_3 Depth=1
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
leaq 96(%rsp), %rax
movq %rax, 32(%rsp)
leaq 88(%rsp), %rax
movq %rax, 40(%rsp)
leaq 16(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
movl $_Z9reductionPiS_, %edi
movq %r15, %r9
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_5
.LBB1_6:
callq hipDeviceSynchronize
xorl %r14d, %r14d
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rsi
leaq 16(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
addl (%rbx,%r14,4), %eax
incq %r14
cmpq $8388608, %r14 # imm = 0x800000
jne .LBB1_7
# %bb.8:
cmpl %eax, 16(%rsp)
movl $.Lstr, %eax
movl $.Lstr.1, %edi
cmoveq %rax, %rdi
callq puts@PLT
movq 32(%rsp), %rax
subq 104(%rsp), %rax
cvtsi2sd %rax, %xmm1
mulsd .LCPI1_3(%rip), %xmm1
cvtsi2sdq 40(%rsp), %xmm0
cvtsi2sdq 112(%rsp), %xmm2
addsd %xmm1, %xmm0
subsd %xmm2, %xmm0
divsd .LCPI1_4(%rip), %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movl 16(%rsp), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9reductionPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9reductionPiS_,@object # @_Z9reductionPiS_
.section .rodata,"a",@progbits
.globl _Z9reductionPiS_
.p2align 3, 0x0
_Z9reductionPiS_:
.quad _Z24__device_stub__reductionPiS_
.size _Z9reductionPiS_, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Tiempo: %f ms\n"
.size .L.str.2, 15
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Reducci\303\263n = %d\n"
.size .L.str.3, 17
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9reductionPiS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Correcto"
.size .Lstr, 9
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Error"
.size .Lstr.1, 6
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__reductionPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9reductionPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#define N 64
#define TPB 32
// A scaling function to convert integers 0,1,...,N-1 to evenly spaced floats
__device__ float scale(int i, int n)
{
return ((float)i) / (n - 1);
}
// Compute the distance between 2 points on a line.
__device__ float distance(float x1, float x2)
{
return sqrt((x2 - x1) * (x2 - x1));
}
__global__ void distanceKernel(float* d_out, float ref, int len)
{
const int i = blockIdx.x * blockDim.x + threadIdx.x;
const float x = scale(i, len);
d_out[i] = distance(x, ref);
printf("i = %2d: dist from %f to %f is %f.\n", i, ref, x, d_out[i]);
}
int main()
{
// Choose a reference value from which distances are measured.
const float ref = 0.5;
// Declare a pointer for an array of floats
float* d_out = 0;
// Allocate device memory for d_out
cudaMalloc(&d_out, N * sizeof(float));
// Launch kernel to compute, NOTE: it is advicable to replace N/TPB with
// (N+TPB-1)/TPB to make sure the number of blocks needed is rounded up.
distanceKernel<<<N/TPB, TPB>>>(d_out, ref, N);
// Wait for device to finish before exiting
cudaDeviceSynchronize();
// Free the memory (Don't forget!!)
cudaFree(d_out);
return 0;
} | code for sm_80
Function : _Z14distanceKernelPffi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x16c] ; /* 0x00005b0000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ BSSY B0, 0x150 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*0040*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ IADD3 R1, R1, -0x20, RZ ; /* 0xffffffe001017810 */
/* 0x000fce0007ffe0ff */
/*0070*/ I2F R4, UR4 ; /* 0x0000000400047d06 */
/* 0x000e620008201400 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fce00078e0203 */
/*0090*/ MUFU.RCP R5, R4 ; /* 0x0000000400057308 */
/* 0x002e300000001000 */
/*00a0*/ I2F R3, R0 ; /* 0x0000000000037306 */
/* 0x000e620000201400 */
/*00b0*/ FFMA R2, -R4, R5, 1 ; /* 0x3f80000004027423 */
/* 0x001fc80000000105 */
/*00c0*/ FFMA R2, R5, R2, R5 ; /* 0x0000000205027223 */
/* 0x000fc60000000005 */
/*00d0*/ FCHK P0, R3, R4 ; /* 0x0000000403007302 */
/* 0x002e220000000000 */
/*00e0*/ FFMA R5, R3, R2, RZ ; /* 0x0000000203057223 */
/* 0x000fc800000000ff */
/*00f0*/ FFMA R6, -R4, R5, R3 ; /* 0x0000000504067223 */
/* 0x000fc80000000103 */
/*0100*/ FFMA R5, R2, R6, R5 ; /* 0x0000000602057223 */
/* 0x000fe20000000005 */
/*0110*/ @!P0 BRA 0x140 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*0120*/ MOV R2, 0x140 ; /* 0x0000014000027802 */
/* 0x000fe40000000f00 */
/*0130*/ CALL.REL.NOINC 0x570 ; /* 0x0000043000007944 */
/* 0x000fea0003c00000 */
/*0140*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0150*/ FADD R2, -R5, c[0x0][0x168] ; /* 0x00005a0005027621 */
/* 0x000fe20000000100 */
/*0160*/ IADD3 R6, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f3e0ff */
/*0170*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0180*/ BSSY B0, 0x2a0 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*0190*/ FMUL R3, R2, R2 ; /* 0x0000000202037220 */
/* 0x000fe40000400000 */
/*01a0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff077624 */
/* 0x000fe400008e06ff */
/*01b0*/ MUFU.RSQ R4, R3 ; /* 0x0000000300047308 */
/* 0x0000620000001400 */
/*01c0*/ IADD3 R2, R3, -0xd000000, RZ ; /* 0xf300000003027810 */
/* 0x000fc80007ffe0ff */
/*01d0*/ ISETP.GT.U32.AND P0, PT, R2, 0x727fffff, PT ; /* 0x727fffff0200780c */
/* 0x000fda0003f04070 */
/*01e0*/ @!P0 BRA 0x250 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*01f0*/ BSSY B1, 0x230 ; /* 0x0000003000017945 */
/* 0x003fe20003800000 */
/*0200*/ MOV R11, 0x220 ; /* 0x00000220000b7802 */
/* 0x000fe40000000f00 */
/*0210*/ CALL.REL.NOINC 0x400 ; /* 0x000001e000007944 */
/* 0x000fea0003c00000 */
/*0220*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0230*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0004 */
/*0240*/ BRA 0x290 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0250*/ FMUL.FTZ R2, R3, R4 ; /* 0x0000000403027220 */
/* 0x003fe40000410000 */
/*0260*/ FMUL.FTZ R4, R4, 0.5 ; /* 0x3f00000004047820 */
/* 0x000fe40000410000 */
/*0270*/ FFMA R3, -R2, R2, R3 ; /* 0x0000000202037223 */
/* 0x000fc80000000103 */
/*0280*/ FFMA R2, R3, R4, R2 ; /* 0x0000000403027223 */
/* 0x000fe40000000002 */
/*0290*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02a0*/ F2F.F64.F32 R8, R5 ; /* 0x0000000500087310 */
/* 0x0001e20000201800 */
/*02b0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe200078e00ff */
/*02c0*/ MOV R3, 0x0 ; /* 0x0000000000037802 */
/* 0x000fe20000000f00 */
/*02d0*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0003e20000100800 */
/*02e0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*02f0*/ IMAD.WIDE R12, R0, R13, c[0x0][0x160] ; /* 0x00005800000c7625 */
/* 0x000fe200078e020d */
/*0300*/ LDC.64 R16, c[0x4][R3] ; /* 0x0100000003107b82 */
/* 0x0002a20000000a00 */
/*0310*/ F2F.F64.F32 R10, R2 ; /* 0x00000002000a7310 */
/* 0x000ee40000201800 */
/*0320*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x001fe200078e00ff */
/*0330*/ STG.E [R12.64], R2 ; /* 0x000000020c007986 */
/* 0x0003ea000c101904 */
/*0340*/ F2F.F64.F32 R14, c[0x0][0x168] ; /* 0x00005a00000e7b10 */
/* 0x000e220000201800 */
/*0350*/ STL.128 [R1+0x10], R8 ; /* 0x0000100801007387 */
/* 0x0083e80000100c00 */
/*0360*/ STL.64 [R1+0x8], R14 ; /* 0x0000080e01007387 */
/* 0x0013e40000100a00 */
/*0370*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x006fe20000000000 */
/*0380*/ MOV R9, 0x3f0 ; /* 0x000003f000097802 */
/* 0x000fc40000000f00 */
/*0390*/ MOV R20, 0x370 ; /* 0x0000037000147802 */
/* 0x000fe40000000f00 */
/*03a0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*03b0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*03c0*/ IADD3 R20, P0, P1, -R20, R9, R2 ; /* 0x0000000914147210 */
/* 0x000fc8000791e102 */
/*03d0*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*03e0*/ CALL.ABS.NOINC R16 ; /* 0x0000000010007343 */
/* 0x000fea0003c00000 */
/*03f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0400*/ LOP3.LUT P0, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03ff7812 */
/* 0x000fda000780c0ff */
/*0410*/ @!P0 BRA 0x530 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0420*/ FSETP.GEU.FTZ.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720b */
/* 0x000fe20003f1e000 */
/*0430*/ IMAD.MOV.U32 R2, RZ, RZ, R3 ; /* 0x000000ffff027224 */
/* 0x000fd800078e0003 */
/*0440*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, 0x7fffffff ; /* 0x7fffffffff038424 */
/* 0x000fe200078e00ff */
/*0450*/ @!P0 BRA 0x530 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0460*/ FSETP.GTU.FTZ.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fda0003f1c200 */
/*0470*/ @P0 FADD.FTZ R3, R2, 1 ; /* 0x3f80000002030421 */
/* 0x000fe20000010000 */
/*0480*/ @P0 BRA 0x530 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0490*/ FSETP.NEU.FTZ.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fda0003f1d200 */
/*04a0*/ @P0 FFMA R4, R2, 1.84467440737095516160e+19, RZ ; /* 0x5f80000002040823 */
/* 0x000fc800000000ff */
/*04b0*/ @P0 MUFU.RSQ R3, R4 ; /* 0x0000000400030308 */
/* 0x000e240000001400 */
/*04c0*/ @P0 FMUL.FTZ R9, R4, R3 ; /* 0x0000000304090220 */
/* 0x001fe40000410000 */
/*04d0*/ @P0 FMUL.FTZ R10, R3, 0.5 ; /* 0x3f000000030a0820 */
/* 0x000fe40000410000 */
/*04e0*/ @P0 FADD.FTZ R8, -R9.reuse, -RZ ; /* 0x800000ff09080221 */
/* 0x040fe40000010100 */
/*04f0*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, R2 ; /* 0x000000ffff038224 */
/* 0x000fe400078e0002 */
/*0500*/ @P0 FFMA R8, R9, R8, R4 ; /* 0x0000000809080223 */
/* 0x000fc80000000004 */
/*0510*/ @P0 FFMA R8, R8, R10, R9 ; /* 0x0000000a08080223 */
/* 0x000fc80000000009 */
/*0520*/ @P0 FMUL.FTZ R3, R8, 2.3283064365386962891e-10 ; /* 0x2f80000008030820 */
/* 0x000fc80000410000 */
/*0530*/ IMAD.MOV.U32 R4, RZ, RZ, R3 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0003 */
/*0540*/ IMAD.MOV.U32 R2, RZ, RZ, R11 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000b */
/*0550*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0560*/ RET.REL.NODEC R2 0x0 ; /* 0xfffffa9002007950 */
/* 0x000fea0003c3ffff */
/*0570*/ SHF.R.U32.HI R6, RZ, 0x17, R4.reuse ; /* 0x00000017ff067819 */
/* 0x100fe20000011604 */
/*0580*/ BSSY B1, 0xbd0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0590*/ SHF.R.U32.HI R5, RZ, 0x17, R3.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011603 */
/*05a0*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0003 */
/*05b0*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fe200078ec0ff */
/*05c0*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*05d0*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe400078ec0ff */
/*05e0*/ IADD3 R11, R6, -0x1, RZ ; /* 0xffffffff060b7810 */
/* 0x000fe40007ffe0ff */
/*05f0*/ IADD3 R10, R5, -0x1, RZ ; /* 0xffffffff050a7810 */
/* 0x000fc40007ffe0ff */
/*0600*/ ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; /* 0x000000fd0b00780c */
/* 0x000fc80003f04070 */
/*0610*/ ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; /* 0x000000fd0a00780c */
/* 0x000fda0000704470 */
/*0620*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*0630*/ @!P0 BRA 0x7b0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0640*/ FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fe40003f1c200 */
/*0650*/ FSETP.GTU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fc80003f3c200 */
/*0660*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0670*/ @P0 BRA 0xbb0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0680*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c807 */
/*0690*/ @!P0 BRA 0xb90 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*06a0*/ FSETP.NEU.FTZ.AND P2, PT, |R3|.reuse, +INF , PT ; /* 0x7f8000000300780b */
/* 0x040fe40003f5d200 */
/*06b0*/ FSETP.NEU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f3d200 */
/*06c0*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fd60003f1d200 */
/*06d0*/ @!P1 BRA !P2, 0xb90 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*06e0*/ LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000784c0ff */
/*06f0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0700*/ @P1 BRA 0xb70 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0710*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*0720*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0730*/ @P0 BRA 0xb40 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0740*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f06270 */
/*0750*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f26270 */
/*0760*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*0770*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*0780*/ @!P0 FFMA R7, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003078823 */
/* 0x000fe400000000ff */
/*0790*/ @!P1 FFMA R8, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004089823 */
/* 0x000fe200000000ff */
/*07a0*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*07b0*/ LEA R3, R6, 0xc0800000, 0x17 ; /* 0xc080000006037811 */
/* 0x000fe200078eb8ff */
/*07c0*/ BSSY B2, 0xb30 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*07d0*/ IADD3 R5, R5, -0x7f, RZ ; /* 0xffffff8105057810 */
/* 0x000fc60007ffe0ff */
/*07e0*/ IMAD.IADD R8, R8, 0x1, -R3 ; /* 0x0000000108087824 */
/* 0x000fe200078e0a03 */
/*07f0*/ IADD3 R6, R5.reuse, 0x7f, -R6 ; /* 0x0000007f05067810 */
/* 0x040fe20007ffe806 */
/*0800*/ IMAD R7, R5, -0x800000, R7 ; /* 0xff80000005077824 */
/* 0x000fe400078e0207 */
/*0810*/ MUFU.RCP R3, R8 ; /* 0x0000000800037308 */
/* 0x000e220000001000 */
/*0820*/ FADD.FTZ R4, -R8, -RZ ; /* 0x800000ff08047221 */
/* 0x000fe40000010100 */
/*0830*/ IMAD.IADD R6, R6, 0x1, R9 ; /* 0x0000000106067824 */
/* 0x000fe400078e0209 */
/*0840*/ FFMA R10, R3, R4, 1 ; /* 0x3f800000030a7423 */
/* 0x001fc80000000004 */
/*0850*/ FFMA R12, R3, R10, R3 ; /* 0x0000000a030c7223 */
/* 0x000fc80000000003 */
/*0860*/ FFMA R3, R7, R12, RZ ; /* 0x0000000c07037223 */
/* 0x000fc800000000ff */
/*0870*/ FFMA R10, R4, R3, R7 ; /* 0x00000003040a7223 */
/* 0x000fc80000000007 */
/*0880*/ FFMA R11, R12, R10, R3 ; /* 0x0000000a0c0b7223 */
/* 0x000fc80000000003 */
/*0890*/ FFMA R7, R4, R11, R7 ; /* 0x0000000b04077223 */
/* 0x000fc80000000007 */
/*08a0*/ FFMA R3, R12, R7, R11 ; /* 0x000000070c037223 */
/* 0x000fca000000000b */
/*08b0*/ SHF.R.U32.HI R4, RZ, 0x17, R3 ; /* 0x00000017ff047819 */
/* 0x000fc80000011603 */
/*08c0*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fca00078ec0ff */
/*08d0*/ IMAD.IADD R8, R4, 0x1, R6 ; /* 0x0000000104087824 */
/* 0x000fca00078e0206 */
/*08e0*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fc80007ffe0ff */
/*08f0*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*0900*/ @!P0 BRA 0xb10 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0910*/ ISETP.GT.AND P0, PT, R8, 0xfe, PT ; /* 0x000000fe0800780c */
/* 0x000fda0003f04270 */
/*0920*/ @P0 BRA 0xae0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0930*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*0940*/ @P0 BRA 0xb20 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0950*/ ISETP.GE.AND P0, PT, R8, -0x18, PT ; /* 0xffffffe80800780c */
/* 0x000fe40003f06270 */
/*0960*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*0970*/ @!P0 BRA 0xb20 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0980*/ FFMA.RZ R4, R12, R7.reuse, R11.reuse ; /* 0x000000070c047223 */
/* 0x180fe2000000c00b */
/*0990*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f45270 */
/*09a0*/ FFMA.RM R5, R12, R7.reuse, R11.reuse ; /* 0x000000070c057223 */
/* 0x180fe2000000400b */
/*09b0*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f25270 */
/*09c0*/ LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04067812 */
/* 0x000fe200078ec0ff */
/*09d0*/ FFMA.RP R4, R12, R7, R11 ; /* 0x000000070c047223 */
/* 0x000fe2000000800b */
/*09e0*/ IADD3 R7, R8, 0x20, RZ ; /* 0x0000002008077810 */
/* 0x000fe20007ffe0ff */
/*09f0*/ IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0a08 */
/*0a00*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe400078efcff */
/*0a10*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fc40003f1d000 */
/*0a20*/ SHF.L.U32 R7, R6, R7, RZ ; /* 0x0000000706077219 */
/* 0x000fe400000006ff */
/*0a30*/ SEL R5, R8, RZ, P2 ; /* 0x000000ff08057207 */
/* 0x000fe40001000000 */
/*0a40*/ ISETP.NE.AND P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f25270 */
/*0a50*/ SHF.R.U32.HI R5, RZ, R5, R6 ; /* 0x00000005ff057219 */
/* 0x000fe40000011606 */
/*0a60*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0a70*/ SHF.R.U32.HI R7, RZ, 0x1, R5 ; /* 0x00000001ff077819 */
/* 0x000fc40000011605 */
/*0a80*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0a90*/ LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef807 */
/*0aa0*/ LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ; /* 0x0000000504047212 */
/* 0x000fca00078ec0ff */
/*0ab0*/ IMAD.IADD R4, R7, 0x1, R4 ; /* 0x0000000107047824 */
/* 0x000fca00078e0204 */
/*0ac0*/ LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ; /* 0x0000000304037212 */
/* 0x000fe200078efcff */
/*0ad0*/ BRA 0xb20 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0ae0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0af0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0b00*/ BRA 0xb20 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0b10*/ IMAD R3, R6, 0x800000, R3 ; /* 0x0080000006037824 */
/* 0x000fe400078e0203 */
/*0b20*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0b30*/ BRA 0xbc0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0b40*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fc800078e4807 */
/*0b50*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0b60*/ BRA 0xbc0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0b70*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fe200078e4807 */
/*0b80*/ BRA 0xbc0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0b90*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*0ba0*/ BRA 0xbc0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0bb0*/ FADD.FTZ R3, R3, R4 ; /* 0x0000000403037221 */
/* 0x000fe40000010000 */
/*0bc0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0bd0*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x001fe400078e0003 */
/*0be0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0bf0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff40002007950 */
/* 0x000fea0003c3ffff */
/*0c00*/ BRA 0xc00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define N 64
#define TPB 32
// A scaling function to convert integers 0,1,...,N-1 to evenly spaced floats
__device__ float scale(int i, int n)
{
return ((float)i) / (n - 1);
}
// Compute the distance between 2 points on a line.
__device__ float distance(float x1, float x2)
{
return sqrt((x2 - x1) * (x2 - x1));
}
__global__ void distanceKernel(float* d_out, float ref, int len)
{
const int i = blockIdx.x * blockDim.x + threadIdx.x;
const float x = scale(i, len);
d_out[i] = distance(x, ref);
printf("i = %2d: dist from %f to %f is %f.\n", i, ref, x, d_out[i]);
}
int main()
{
// Choose a reference value from which distances are measured.
const float ref = 0.5;
// Declare a pointer for an array of floats
float* d_out = 0;
// Allocate device memory for d_out
cudaMalloc(&d_out, N * sizeof(float));
// Launch kernel to compute, NOTE: it is advicable to replace N/TPB with
// (N+TPB-1)/TPB to make sure the number of blocks needed is rounded up.
distanceKernel<<<N/TPB, TPB>>>(d_out, ref, N);
// Wait for device to finish before exiting
cudaDeviceSynchronize();
// Free the memory (Don't forget!!)
cudaFree(d_out);
return 0;
} | .file "tmpxft_0004119d_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5scaleii
.type _Z5scaleii, @function
_Z5scaleii:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z5scaleii, .-_Z5scaleii
.globl _Z8distanceff
.type _Z8distanceff, @function
_Z8distanceff:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z8distanceff, .-_Z8distanceff
.globl _Z36__device_stub__Z14distanceKernelPffiPffi
.type _Z36__device_stub__Z14distanceKernelPffiPffi, @function
_Z36__device_stub__Z14distanceKernelPffiPffi:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14distanceKernelPffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z36__device_stub__Z14distanceKernelPffiPffi, .-_Z36__device_stub__Z14distanceKernelPffiPffi
.globl _Z14distanceKernelPffi
.type _Z14distanceKernelPffi, @function
_Z14distanceKernelPffi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z14distanceKernelPffiPffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z14distanceKernelPffi, .-_Z14distanceKernelPffi
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L16:
call cudaDeviceSynchronize@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $64, %esi
movss .LC0(%rip), %xmm0
movq 8(%rsp), %rdi
call _Z36__device_stub__Z14distanceKernelPffiPffi
jmp .L16
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z14distanceKernelPffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14distanceKernelPffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1056964608
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define N 64
#define TPB 32
// A scaling function to convert integers 0,1,...,N-1 to evenly spaced floats
__device__ float scale(int i, int n)
{
return ((float)i) / (n - 1);
}
// Compute the distance between 2 points on a line.
__device__ float distance(float x1, float x2)
{
return sqrt((x2 - x1) * (x2 - x1));
}
__global__ void distanceKernel(float* d_out, float ref, int len)
{
const int i = blockIdx.x * blockDim.x + threadIdx.x;
const float x = scale(i, len);
d_out[i] = distance(x, ref);
printf("i = %2d: dist from %f to %f is %f.\n", i, ref, x, d_out[i]);
}
int main()
{
// Choose a reference value from which distances are measured.
const float ref = 0.5;
// Declare a pointer for an array of floats
float* d_out = 0;
// Allocate device memory for d_out
cudaMalloc(&d_out, N * sizeof(float));
// Launch kernel to compute, NOTE: it is advicable to replace N/TPB with
// (N+TPB-1)/TPB to make sure the number of blocks needed is rounded up.
distanceKernel<<<N/TPB, TPB>>>(d_out, ref, N);
// Wait for device to finish before exiting
cudaDeviceSynchronize();
// Free the memory (Don't forget!!)
cudaFree(d_out);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define N 64
#define TPB 32
// A scaling function to convert integers 0,1,...,N-1 to evenly spaced floats
__device__ float scale(int i, int n)
{
return ((float)i) / (n - 1);
}
// Compute the distance between 2 points on a line.
__device__ float distance(float x1, float x2)
{
return sqrt((x2 - x1) * (x2 - x1));
}
__global__ void distanceKernel(float* d_out, float ref, int len)
{
const int i = blockIdx.x * blockDim.x + threadIdx.x;
const float x = scale(i, len);
d_out[i] = distance(x, ref);
printf("i = %2d: dist from %f to %f is %f.\n", i, ref, x, d_out[i]);
}
int main()
{
// Choose a reference value from which distances are measured.
const float ref = 0.5;
// Declare a pointer for an array of floats
float* d_out = 0;
// Allocate device memory for d_out
hipMalloc(&d_out, N * sizeof(float));
// Launch kernel to compute, NOTE: it is advicable to replace N/TPB with
// (N+TPB-1)/TPB to make sure the number of blocks needed is rounded up.
distanceKernel<<<N/TPB, TPB>>>(d_out, ref, N);
// Wait for device to finish before exiting
hipDeviceSynchronize();
// Free the memory (Don't forget!!)
hipFree(d_out);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define N 64
#define TPB 32
// A scaling function to convert integers 0,1,...,N-1 to evenly spaced floats
__device__ float scale(int i, int n)
{
return ((float)i) / (n - 1);
}
// Compute the distance between 2 points on a line.
__device__ float distance(float x1, float x2)
{
return sqrt((x2 - x1) * (x2 - x1));
}
__global__ void distanceKernel(float* d_out, float ref, int len)
{
const int i = blockIdx.x * blockDim.x + threadIdx.x;
const float x = scale(i, len);
d_out[i] = distance(x, ref);
printf("i = %2d: dist from %f to %f is %f.\n", i, ref, x, d_out[i]);
}
int main()
{
// Choose a reference value from which distances are measured.
const float ref = 0.5;
// Declare a pointer for an array of floats
float* d_out = 0;
// Allocate device memory for d_out
hipMalloc(&d_out, N * sizeof(float));
// Launch kernel to compute, NOTE: it is advicable to replace N/TPB with
// (N+TPB-1)/TPB to make sure the number of blocks needed is rounded up.
distanceKernel<<<N/TPB, TPB>>>(d_out, ref, N);
// Wait for device to finish before exiting
hipDeviceSynchronize();
// Free the memory (Don't forget!!)
hipFree(d_out);
return 0;
} | .text
.file "kernel.hip"
.globl _Z29__device_stub__distanceKernelPffi # -- Begin function _Z29__device_stub__distanceKernelPffi
.p2align 4, 0x90
.type _Z29__device_stub__distanceKernelPffi,@function
_Z29__device_stub__distanceKernelPffi: # @_Z29__device_stub__distanceKernelPffi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14distanceKernelPffi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z29__device_stub__distanceKernelPffi, .Lfunc_end0-_Z29__device_stub__distanceKernelPffi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 30(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $1056964608, 20(%rsp) # imm = 0x3F000000
movl $64, 16(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14distanceKernelPffi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14distanceKernelPffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14distanceKernelPffi,@object # @_Z14distanceKernelPffi
.section .rodata,"a",@progbits
.globl _Z14distanceKernelPffi
.p2align 3, 0x0
_Z14distanceKernelPffi:
.quad _Z29__device_stub__distanceKernelPffi
.size _Z14distanceKernelPffi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14distanceKernelPffi"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__distanceKernelPffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14distanceKernelPffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004119d_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5scaleii
.type _Z5scaleii, @function
_Z5scaleii:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z5scaleii, .-_Z5scaleii
.globl _Z8distanceff
.type _Z8distanceff, @function
_Z8distanceff:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z8distanceff, .-_Z8distanceff
.globl _Z36__device_stub__Z14distanceKernelPffiPffi
.type _Z36__device_stub__Z14distanceKernelPffiPffi, @function
_Z36__device_stub__Z14distanceKernelPffiPffi:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14distanceKernelPffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z36__device_stub__Z14distanceKernelPffiPffi, .-_Z36__device_stub__Z14distanceKernelPffiPffi
.globl _Z14distanceKernelPffi
.type _Z14distanceKernelPffi, @function
_Z14distanceKernelPffi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z14distanceKernelPffiPffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z14distanceKernelPffi, .-_Z14distanceKernelPffi
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L16:
call cudaDeviceSynchronize@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $64, %esi
movss .LC0(%rip), %xmm0
movq 8(%rsp), %rdi
call _Z36__device_stub__Z14distanceKernelPffiPffi
jmp .L16
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z14distanceKernelPffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14distanceKernelPffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1056964608
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z29__device_stub__distanceKernelPffi # -- Begin function _Z29__device_stub__distanceKernelPffi
.p2align 4, 0x90
.type _Z29__device_stub__distanceKernelPffi,@function
_Z29__device_stub__distanceKernelPffi: # @_Z29__device_stub__distanceKernelPffi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14distanceKernelPffi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z29__device_stub__distanceKernelPffi, .Lfunc_end0-_Z29__device_stub__distanceKernelPffi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 30(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $1056964608, 20(%rsp) # imm = 0x3F000000
movl $64, 16(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14distanceKernelPffi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14distanceKernelPffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14distanceKernelPffi,@object # @_Z14distanceKernelPffi
.section .rodata,"a",@progbits
.globl _Z14distanceKernelPffi
.p2align 3, 0x0
_Z14distanceKernelPffi:
.quad _Z29__device_stub__distanceKernelPffi
.size _Z14distanceKernelPffi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14distanceKernelPffi"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__distanceKernelPffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14distanceKernelPffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void set_array_double(double *a, double value, size_t len)
{
size_t idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < len) {
a[idx] = value;
idx += blockDim.x * gridDim.x;
}
} | code for sm_80
Function : _Z16set_array_doublePddm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x174], PT, P0 ; /* 0x00005d00ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0080*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*0090*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff067624 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe400078e00ff */
/*00c0*/ LEA R2, P0, R0, c[0x0][0x160], 0x3 ; /* 0x0000580000027a11 */
/* 0x000fe200078018ff */
/*00d0*/ IMAD R9, R6, c[0x0][0xc], RZ ; /* 0x0000030006097a24 */
/* 0x000fc600078e02ff */
/*00e0*/ LEA.HI.X R3, R0, c[0x0][0x164], R7, 0x3, P0 ; /* 0x0000590000037a11 */
/* 0x000fe400000f1c07 */
/*00f0*/ IADD3 R0, P0, R9, R0, RZ ; /* 0x0000000009007210 */
/* 0x000fc60007f1e0ff */
/*0100*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x0001e2000c101b04 */
/*0110*/ IADD3.X R7, RZ, R7, RZ, P0, !PT ; /* 0x00000007ff077210 */
/* 0x000fe400007fe4ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fc80003f06070 */
/*0130*/ ISETP.GE.U32.AND.EX P0, PT, R7, c[0x0][0x174], PT, P0 ; /* 0x00005d0007007a0c */
/* 0x000fda0003f06100 */
/*0140*/ @!P0 BRA 0xc0 ; /* 0xffffff7000008947 */
/* 0x001fea000383ffff */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void set_array_double(double *a, double value, size_t len)
{
size_t idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < len) {
a[idx] = value;
idx += blockDim.x * gridDim.x;
}
} | .file "tmpxft_000de411_00000000-6_set_array_double.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z16set_array_doublePddmPddm
.type _Z38__device_stub__Z16set_array_doublePddmPddm, @function
_Z38__device_stub__Z16set_array_doublePddmPddm:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movsd %xmm0, 16(%rsp)
movq %rsi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16set_array_doublePddm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z16set_array_doublePddmPddm, .-_Z38__device_stub__Z16set_array_doublePddmPddm
.globl _Z16set_array_doublePddm
.type _Z16set_array_doublePddm, @function
_Z16set_array_doublePddm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z16set_array_doublePddmPddm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16set_array_doublePddm, .-_Z16set_array_doublePddm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16set_array_doublePddm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16set_array_doublePddm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void set_array_double(double *a, double value, size_t len)
{
size_t idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < len) {
a[idx] = value;
idx += blockDim.x * gridDim.x;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void set_array_double(double *a, double value, size_t len)
{
size_t idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < len) {
a[idx] = value;
idx += blockDim.x * gridDim.x;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void set_array_double(double *a, double value, size_t len)
{
size_t idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < len) {
a[idx] = value;
idx += blockDim.x * gridDim.x;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16set_array_doublePddm
.globl _Z16set_array_doublePddm
.p2align 8
.type _Z16set_array_doublePddm,@function
_Z16set_array_doublePddm:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
v_mov_b32_e32 v2, 0
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b32 s4, s[4:5], 0x0
s_load_b128 s[8:11], s[0:1], 0x0
v_lshlrev_b64 v[3:4], 3, v[1:2]
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s1, s5
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s4, s6
v_add_co_u32 v3, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
v_dual_mov_b32 v5, s10 :: v_dual_mov_b32 v6, s11
s_lshl_b64 s[6:7], s[4:5], 3
.LBB0_2:
v_add_co_u32 v1, vcc_lo, v1, s4
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_store_b64 v[3:4], v[5:6], off
v_add_co_u32 v3, s0, v3, s6
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
v_add_co_ci_u32_e64 v4, s0, s7, v4, s0
s_or_b32 s1, vcc_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16set_array_doublePddm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16set_array_doublePddm, .Lfunc_end0-_Z16set_array_doublePddm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16set_array_doublePddm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16set_array_doublePddm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void set_array_double(double *a, double value, size_t len)
{
size_t idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < len) {
a[idx] = value;
idx += blockDim.x * gridDim.x;
}
} | .text
.file "set_array_double.hip"
.globl _Z31__device_stub__set_array_doublePddm # -- Begin function _Z31__device_stub__set_array_doublePddm
.p2align 4, 0x90
.type _Z31__device_stub__set_array_doublePddm,@function
_Z31__device_stub__set_array_doublePddm: # @_Z31__device_stub__set_array_doublePddm
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movsd %xmm0, 64(%rsp)
movq %rsi, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16set_array_doublePddm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z31__device_stub__set_array_doublePddm, .Lfunc_end0-_Z31__device_stub__set_array_doublePddm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16set_array_doublePddm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16set_array_doublePddm,@object # @_Z16set_array_doublePddm
.section .rodata,"a",@progbits
.globl _Z16set_array_doublePddm
.p2align 3, 0x0
_Z16set_array_doublePddm:
.quad _Z31__device_stub__set_array_doublePddm
.size _Z16set_array_doublePddm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16set_array_doublePddm"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__set_array_doublePddm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16set_array_doublePddm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16set_array_doublePddm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x174], PT, P0 ; /* 0x00005d00ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0080*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*0090*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff067624 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe400078e00ff */
/*00c0*/ LEA R2, P0, R0, c[0x0][0x160], 0x3 ; /* 0x0000580000027a11 */
/* 0x000fe200078018ff */
/*00d0*/ IMAD R9, R6, c[0x0][0xc], RZ ; /* 0x0000030006097a24 */
/* 0x000fc600078e02ff */
/*00e0*/ LEA.HI.X R3, R0, c[0x0][0x164], R7, 0x3, P0 ; /* 0x0000590000037a11 */
/* 0x000fe400000f1c07 */
/*00f0*/ IADD3 R0, P0, R9, R0, RZ ; /* 0x0000000009007210 */
/* 0x000fc60007f1e0ff */
/*0100*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x0001e2000c101b04 */
/*0110*/ IADD3.X R7, RZ, R7, RZ, P0, !PT ; /* 0x00000007ff077210 */
/* 0x000fe400007fe4ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fc80003f06070 */
/*0130*/ ISETP.GE.U32.AND.EX P0, PT, R7, c[0x0][0x174], PT, P0 ; /* 0x00005d0007007a0c */
/* 0x000fda0003f06100 */
/*0140*/ @!P0 BRA 0xc0 ; /* 0xffffff7000008947 */
/* 0x001fea000383ffff */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16set_array_doublePddm
.globl _Z16set_array_doublePddm
.p2align 8
.type _Z16set_array_doublePddm,@function
_Z16set_array_doublePddm:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
v_mov_b32_e32 v2, 0
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b32 s4, s[4:5], 0x0
s_load_b128 s[8:11], s[0:1], 0x0
v_lshlrev_b64 v[3:4], 3, v[1:2]
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s1, s5
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s4, s6
v_add_co_u32 v3, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
v_dual_mov_b32 v5, s10 :: v_dual_mov_b32 v6, s11
s_lshl_b64 s[6:7], s[4:5], 3
.LBB0_2:
v_add_co_u32 v1, vcc_lo, v1, s4
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_store_b64 v[3:4], v[5:6], off
v_add_co_u32 v3, s0, v3, s6
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
v_add_co_ci_u32_e64 v4, s0, s7, v4, s0
s_or_b32 s1, vcc_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16set_array_doublePddm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16set_array_doublePddm, .Lfunc_end0-_Z16set_array_doublePddm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16set_array_doublePddm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16set_array_doublePddm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000de411_00000000-6_set_array_double.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z16set_array_doublePddmPddm
.type _Z38__device_stub__Z16set_array_doublePddmPddm, @function
_Z38__device_stub__Z16set_array_doublePddmPddm:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movsd %xmm0, 16(%rsp)
movq %rsi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16set_array_doublePddm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z16set_array_doublePddmPddm, .-_Z38__device_stub__Z16set_array_doublePddmPddm
.globl _Z16set_array_doublePddm
.type _Z16set_array_doublePddm, @function
_Z16set_array_doublePddm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z16set_array_doublePddmPddm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16set_array_doublePddm, .-_Z16set_array_doublePddm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16set_array_doublePddm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16set_array_doublePddm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "set_array_double.hip"
.globl _Z31__device_stub__set_array_doublePddm # -- Begin function _Z31__device_stub__set_array_doublePddm
.p2align 4, 0x90
.type _Z31__device_stub__set_array_doublePddm,@function
_Z31__device_stub__set_array_doublePddm: # @_Z31__device_stub__set_array_doublePddm
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movsd %xmm0, 64(%rsp)
movq %rsi, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16set_array_doublePddm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z31__device_stub__set_array_doublePddm, .Lfunc_end0-_Z31__device_stub__set_array_doublePddm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16set_array_doublePddm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16set_array_doublePddm,@object # @_Z16set_array_doublePddm
.section .rodata,"a",@progbits
.globl _Z16set_array_doublePddm
.p2align 3, 0x0
_Z16set_array_doublePddm:
.quad _Z31__device_stub__set_array_doublePddm
.size _Z16set_array_doublePddm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16set_array_doublePddm"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__set_array_doublePddm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16set_array_doublePddm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
#include <math.h>
#include <sys/types.h>
#include <sys/time.h>
#include <sys/stat.h>
#define BLOCK_DIM 1024
#define SEED 26
__global__ void data(double *a, double *b, double *c, int count) {
int t_id = blockDim.x * blockIdx.x + threadIdx.x;
if (t_id < count)
c[t_id] = a[t_id] + b[t_id];
}
int main (int argc, char *argv[]) {
if (argc != 2) {
printf("Usage: %s number\n", argv[0]);
exit(1);
}
// Initialize host variables
int i = 0;
double *hA, *hB, *hC, *refC;
int num = atoi(argv[1]);
long size = num*sizeof(double);
hA = (double *)malloc(size);
hB = (double *)malloc(size);
hC = (double *)malloc(size);
refC = (double *)malloc(size);
// Timing variables;
cudaEvent_t incl_start, incl_end;
cudaEvent_t excl_start, excl_end;
float time_incl, time_excl;
cudaEventCreate(&incl_start);
cudaEventCreate(&incl_end);
cudaEventCreate(&excl_start);
cudaEventCreate(&excl_end);
// Populate hA, hB, refC
srand(SEED);
for (i=0; i<num; i++) {
hA[i] = -10 + rand() % 20;
hB[i] = -10 + rand() % 20;
refC[i] = hA[i] + hB[i];
}
// Device memory allocation
double *dA, *dB, *dC;
cudaMalloc((void **)&dA, size);
cudaMalloc((void **)&dB, size);
cudaMalloc((void **)&dC, size);
cudaEventRecord(incl_start, 0);
cudaMemcpy(dA, hA, size, cudaMemcpyHostToDevice);
cudaMemcpy(dB, hB, size, cudaMemcpyHostToDevice);
// Launch kernel
int GRID_DIM = (num % BLOCK_DIM == 0)
? num / BLOCK_DIM
: (int)(num / BLOCK_DIM) + 1;
dim3 dimGrid(GRID_DIM, 1, 1);
dim3 dimBlock(BLOCK_DIM, 1, 1);
cudaEventRecord(excl_start, 0);
data<<<dimGrid, dimBlock>>>(dA, dB, dC, num);
cudaEventRecord(excl_end, 0);
cudaEventSynchronize(excl_end);
cudaMemcpy(hC, dC, size, cudaMemcpyDeviceToHost);
cudaEventRecord(incl_end, 0);
cudaEventSynchronize(incl_end);
// Verify results
for (i=0; i<num; i++) {
if (fabs(refC[i] - hC[i]) > 1e-12) {
printf("FAIL\n");
exit(1);
}
}
// Print metrics
cudaEventElapsedTime(&time_incl, incl_start, incl_end);
cudaEventElapsedTime(&time_excl, excl_start, excl_end);
//time_incl *= 1000;
//time_excl *= 1000;
//printf("Inclusive: %f\n", incl_diff);
//printf("Exclusive: %f\n", excl_diff);
//printf("Size = %d\n Inclusive Time = %f\n Exclusive Time = %f\n", num, time_incl, time_excl);
printf("%d\t%f\t%f\n", num, time_incl, time_excl);
// Cleanup
cudaFree(dA);
cudaFree(dB);
cudaFree(dC);
free(hA);
free(hB);
free(hC);
free(refC);
return 0;
} | code for sm_80
Function : _Z4dataPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R8, R9, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R2, R8.reuse, R9.reuse, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0209 */
/*00d0*/ DADD R6, R4, R2 ; /* 0x0000000004067229 */
/* 0x004e0e0000000002 */
/*00e0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#include <math.h>
#include <sys/types.h>
#include <sys/time.h>
#include <sys/stat.h>
#define BLOCK_DIM 1024
#define SEED 26
__global__ void data(double *a, double *b, double *c, int count) {
int t_id = blockDim.x * blockIdx.x + threadIdx.x;
if (t_id < count)
c[t_id] = a[t_id] + b[t_id];
}
int main (int argc, char *argv[]) {
if (argc != 2) {
printf("Usage: %s number\n", argv[0]);
exit(1);
}
// Initialize host variables
int i = 0;
double *hA, *hB, *hC, *refC;
int num = atoi(argv[1]);
long size = num*sizeof(double);
hA = (double *)malloc(size);
hB = (double *)malloc(size);
hC = (double *)malloc(size);
refC = (double *)malloc(size);
// Timing variables;
cudaEvent_t incl_start, incl_end;
cudaEvent_t excl_start, excl_end;
float time_incl, time_excl;
cudaEventCreate(&incl_start);
cudaEventCreate(&incl_end);
cudaEventCreate(&excl_start);
cudaEventCreate(&excl_end);
// Populate hA, hB, refC
srand(SEED);
for (i=0; i<num; i++) {
hA[i] = -10 + rand() % 20;
hB[i] = -10 + rand() % 20;
refC[i] = hA[i] + hB[i];
}
// Device memory allocation
double *dA, *dB, *dC;
cudaMalloc((void **)&dA, size);
cudaMalloc((void **)&dB, size);
cudaMalloc((void **)&dC, size);
cudaEventRecord(incl_start, 0);
cudaMemcpy(dA, hA, size, cudaMemcpyHostToDevice);
cudaMemcpy(dB, hB, size, cudaMemcpyHostToDevice);
// Launch kernel
int GRID_DIM = (num % BLOCK_DIM == 0)
? num / BLOCK_DIM
: (int)(num / BLOCK_DIM) + 1;
dim3 dimGrid(GRID_DIM, 1, 1);
dim3 dimBlock(BLOCK_DIM, 1, 1);
cudaEventRecord(excl_start, 0);
data<<<dimGrid, dimBlock>>>(dA, dB, dC, num);
cudaEventRecord(excl_end, 0);
cudaEventSynchronize(excl_end);
cudaMemcpy(hC, dC, size, cudaMemcpyDeviceToHost);
cudaEventRecord(incl_end, 0);
cudaEventSynchronize(incl_end);
// Verify results
for (i=0; i<num; i++) {
if (fabs(refC[i] - hC[i]) > 1e-12) {
printf("FAIL\n");
exit(1);
}
}
// Print metrics
cudaEventElapsedTime(&time_incl, incl_start, incl_end);
cudaEventElapsedTime(&time_excl, excl_start, excl_end);
//time_incl *= 1000;
//time_excl *= 1000;
//printf("Inclusive: %f\n", incl_diff);
//printf("Exclusive: %f\n", excl_diff);
//printf("Size = %d\n Inclusive Time = %f\n Exclusive Time = %f\n", num, time_incl, time_excl);
printf("%d\t%f\t%f\n", num, time_incl, time_excl);
// Cleanup
cudaFree(dA);
cudaFree(dB);
cudaFree(dC);
free(hA);
free(hB);
free(hC);
free(refC);
return 0;
} | .file "tmpxft_001a171a_00000000-6_q2_1024.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z4dataPdS_S_iPdS_S_i
.type _Z28__device_stub__Z4dataPdS_S_iPdS_S_i, @function
_Z28__device_stub__Z4dataPdS_S_iPdS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4dataPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z4dataPdS_S_iPdS_S_i, .-_Z28__device_stub__Z4dataPdS_S_iPdS_S_i
.globl _Z4dataPdS_S_i
.type _Z4dataPdS_S_i, @function
_Z4dataPdS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z4dataPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4dataPdS_S_i, .-_Z4dataPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Usage: %s number\n"
.LC3:
.string "FAIL\n"
.LC4:
.string "%d\t%f\t%f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jne .L28
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movq %rax, 24(%rsp)
movl %eax, 12(%rsp)
cltq
leaq 0(,%rax,8), %rbx
movq %rbx, 16(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
movl $26, %edi
call srand@PLT
testl %r15d, %r15d
jle .L13
leal -1(%r15), %r15d
movl $0, %ebx
.L14:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $35, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
sall $2, %edx
subl %edx, %eax
subl $10, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, 0(%r13,%rbx,8)
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $35, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
sall $2, %edx
subl %edx, %eax
subl $10, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%r14,%rbx,8)
addsd 0(%r13,%rbx,8), %xmm0
movsd %xmm0, 0(%rbp,%rbx,8)
movq %rbx, %rax
addq $1, %rbx
cmpq %r15, %rax
jne .L14
.L13:
leaq 72(%rsp), %rdi
movq 16(%rsp), %rbx
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
testq $1023, 24(%rsp)
jne .L15
movl $1024, %ecx
movl 12(%rsp), %eax
cltd
idivl %ecx
.L16:
movl %eax, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1024, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movl 116(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movq 96(%rsp), %rdi
movl 104(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L17:
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $2, %ecx
movq 16(%rsp), %rdx
movq 88(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 24(%rsp), %rax
testl %eax, %eax
jle .L18
movl %eax, %edx
movl $0, %eax
movq .LC1(%rip), %xmm2
movsd .LC2(%rip), %xmm1
.L21:
movsd 0(%rbp,%rax,8), %xmm0
subsd (%r12,%rax,8), %xmm0
andpd %xmm2, %xmm0
comisd %xmm1, %xmm0
ja .L30
addq $1, %rax
cmpq %rdx, %rax
jne .L21
.L18:
leaq 32(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 36(%rsp), %rdi
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 32(%rsp), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 36(%rsp), %xmm1
movl 12(%rsp), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movq (%rsi), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L15:
movl $1024, %ecx
movl 12(%rsp), %eax
cltd
idivl %ecx
addl $1, %eax
jmp .L16
.L29:
movl 12(%rsp), %ecx
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z28__device_stub__Z4dataPdS_S_iPdS_S_i
jmp .L17
.L30:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z4dataPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z4dataPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC1:
.long -1
.long 2147483647
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long -2127697391
.long 1030854553
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#include <math.h>
#include <sys/types.h>
#include <sys/time.h>
#include <sys/stat.h>
#define BLOCK_DIM 1024
#define SEED 26
__global__ void data(double *a, double *b, double *c, int count) {
int t_id = blockDim.x * blockIdx.x + threadIdx.x;
if (t_id < count)
c[t_id] = a[t_id] + b[t_id];
}
int main (int argc, char *argv[]) {
if (argc != 2) {
printf("Usage: %s number\n", argv[0]);
exit(1);
}
// Initialize host variables
int i = 0;
double *hA, *hB, *hC, *refC;
int num = atoi(argv[1]);
long size = num*sizeof(double);
hA = (double *)malloc(size);
hB = (double *)malloc(size);
hC = (double *)malloc(size);
refC = (double *)malloc(size);
// Timing variables;
cudaEvent_t incl_start, incl_end;
cudaEvent_t excl_start, excl_end;
float time_incl, time_excl;
cudaEventCreate(&incl_start);
cudaEventCreate(&incl_end);
cudaEventCreate(&excl_start);
cudaEventCreate(&excl_end);
// Populate hA, hB, refC
srand(SEED);
for (i=0; i<num; i++) {
hA[i] = -10 + rand() % 20;
hB[i] = -10 + rand() % 20;
refC[i] = hA[i] + hB[i];
}
// Device memory allocation
double *dA, *dB, *dC;
cudaMalloc((void **)&dA, size);
cudaMalloc((void **)&dB, size);
cudaMalloc((void **)&dC, size);
cudaEventRecord(incl_start, 0);
cudaMemcpy(dA, hA, size, cudaMemcpyHostToDevice);
cudaMemcpy(dB, hB, size, cudaMemcpyHostToDevice);
// Launch kernel
int GRID_DIM = (num % BLOCK_DIM == 0)
? num / BLOCK_DIM
: (int)(num / BLOCK_DIM) + 1;
dim3 dimGrid(GRID_DIM, 1, 1);
dim3 dimBlock(BLOCK_DIM, 1, 1);
cudaEventRecord(excl_start, 0);
data<<<dimGrid, dimBlock>>>(dA, dB, dC, num);
cudaEventRecord(excl_end, 0);
cudaEventSynchronize(excl_end);
cudaMemcpy(hC, dC, size, cudaMemcpyDeviceToHost);
cudaEventRecord(incl_end, 0);
cudaEventSynchronize(incl_end);
// Verify results
for (i=0; i<num; i++) {
if (fabs(refC[i] - hC[i]) > 1e-12) {
printf("FAIL\n");
exit(1);
}
}
// Print metrics
cudaEventElapsedTime(&time_incl, incl_start, incl_end);
cudaEventElapsedTime(&time_excl, excl_start, excl_end);
//time_incl *= 1000;
//time_excl *= 1000;
//printf("Inclusive: %f\n", incl_diff);
//printf("Exclusive: %f\n", excl_diff);
//printf("Size = %d\n Inclusive Time = %f\n Exclusive Time = %f\n", num, time_incl, time_excl);
printf("%d\t%f\t%f\n", num, time_incl, time_excl);
// Cleanup
cudaFree(dA);
cudaFree(dB);
cudaFree(dC);
free(hA);
free(hB);
free(hC);
free(refC);
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <math.h>
#include <sys/types.h>
#include <sys/time.h>
#include <sys/stat.h>
#define BLOCK_DIM 1024
#define SEED 26
__global__ void data(double *a, double *b, double *c, int count) {
int t_id = blockDim.x * blockIdx.x + threadIdx.x;
if (t_id < count)
c[t_id] = a[t_id] + b[t_id];
}
int main (int argc, char *argv[]) {
if (argc != 2) {
printf("Usage: %s number\n", argv[0]);
exit(1);
}
// Initialize host variables
int i = 0;
double *hA, *hB, *hC, *refC;
int num = atoi(argv[1]);
long size = num*sizeof(double);
hA = (double *)malloc(size);
hB = (double *)malloc(size);
hC = (double *)malloc(size);
refC = (double *)malloc(size);
// Timing variables;
hipEvent_t incl_start, incl_end;
hipEvent_t excl_start, excl_end;
float time_incl, time_excl;
hipEventCreate(&incl_start);
hipEventCreate(&incl_end);
hipEventCreate(&excl_start);
hipEventCreate(&excl_end);
// Populate hA, hB, refC
srand(SEED);
for (i=0; i<num; i++) {
hA[i] = -10 + rand() % 20;
hB[i] = -10 + rand() % 20;
refC[i] = hA[i] + hB[i];
}
// Device memory allocation
double *dA, *dB, *dC;
hipMalloc((void **)&dA, size);
hipMalloc((void **)&dB, size);
hipMalloc((void **)&dC, size);
hipEventRecord(incl_start, 0);
hipMemcpy(dA, hA, size, hipMemcpyHostToDevice);
hipMemcpy(dB, hB, size, hipMemcpyHostToDevice);
// Launch kernel
int GRID_DIM = (num % BLOCK_DIM == 0)
? num / BLOCK_DIM
: (int)(num / BLOCK_DIM) + 1;
dim3 dimGrid(GRID_DIM, 1, 1);
dim3 dimBlock(BLOCK_DIM, 1, 1);
hipEventRecord(excl_start, 0);
data<<<dimGrid, dimBlock>>>(dA, dB, dC, num);
hipEventRecord(excl_end, 0);
hipEventSynchronize(excl_end);
hipMemcpy(hC, dC, size, hipMemcpyDeviceToHost);
hipEventRecord(incl_end, 0);
hipEventSynchronize(incl_end);
// Verify results
for (i=0; i<num; i++) {
if (fabs(refC[i] - hC[i]) > 1e-12) {
printf("FAIL\n");
exit(1);
}
}
// Print metrics
hipEventElapsedTime(&time_incl, incl_start, incl_end);
hipEventElapsedTime(&time_excl, excl_start, excl_end);
//time_incl *= 1000;
//time_excl *= 1000;
//printf("Inclusive: %f\n", incl_diff);
//printf("Exclusive: %f\n", excl_diff);
//printf("Size = %d\n Inclusive Time = %f\n Exclusive Time = %f\n", num, time_incl, time_excl);
printf("%d\t%f\t%f\n", num, time_incl, time_excl);
// Cleanup
hipFree(dA);
hipFree(dB);
hipFree(dC);
free(hA);
free(hB);
free(hC);
free(refC);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <math.h>
#include <sys/types.h>
#include <sys/time.h>
#include <sys/stat.h>
#define BLOCK_DIM 1024
#define SEED 26
__global__ void data(double *a, double *b, double *c, int count) {
int t_id = blockDim.x * blockIdx.x + threadIdx.x;
if (t_id < count)
c[t_id] = a[t_id] + b[t_id];
}
int main (int argc, char *argv[]) {
if (argc != 2) {
printf("Usage: %s number\n", argv[0]);
exit(1);
}
// Initialize host variables
int i = 0;
double *hA, *hB, *hC, *refC;
int num = atoi(argv[1]);
long size = num*sizeof(double);
hA = (double *)malloc(size);
hB = (double *)malloc(size);
hC = (double *)malloc(size);
refC = (double *)malloc(size);
// Timing variables;
hipEvent_t incl_start, incl_end;
hipEvent_t excl_start, excl_end;
float time_incl, time_excl;
hipEventCreate(&incl_start);
hipEventCreate(&incl_end);
hipEventCreate(&excl_start);
hipEventCreate(&excl_end);
// Populate hA, hB, refC
srand(SEED);
for (i=0; i<num; i++) {
hA[i] = -10 + rand() % 20;
hB[i] = -10 + rand() % 20;
refC[i] = hA[i] + hB[i];
}
// Device memory allocation
double *dA, *dB, *dC;
hipMalloc((void **)&dA, size);
hipMalloc((void **)&dB, size);
hipMalloc((void **)&dC, size);
hipEventRecord(incl_start, 0);
hipMemcpy(dA, hA, size, hipMemcpyHostToDevice);
hipMemcpy(dB, hB, size, hipMemcpyHostToDevice);
// Launch kernel
int GRID_DIM = (num % BLOCK_DIM == 0)
? num / BLOCK_DIM
: (int)(num / BLOCK_DIM) + 1;
dim3 dimGrid(GRID_DIM, 1, 1);
dim3 dimBlock(BLOCK_DIM, 1, 1);
hipEventRecord(excl_start, 0);
data<<<dimGrid, dimBlock>>>(dA, dB, dC, num);
hipEventRecord(excl_end, 0);
hipEventSynchronize(excl_end);
hipMemcpy(hC, dC, size, hipMemcpyDeviceToHost);
hipEventRecord(incl_end, 0);
hipEventSynchronize(incl_end);
// Verify results
for (i=0; i<num; i++) {
if (fabs(refC[i] - hC[i]) > 1e-12) {
printf("FAIL\n");
exit(1);
}
}
// Print metrics
hipEventElapsedTime(&time_incl, incl_start, incl_end);
hipEventElapsedTime(&time_excl, excl_start, excl_end);
//time_incl *= 1000;
//time_excl *= 1000;
//printf("Inclusive: %f\n", incl_diff);
//printf("Exclusive: %f\n", excl_diff);
//printf("Size = %d\n Inclusive Time = %f\n Exclusive Time = %f\n", num, time_incl, time_excl);
printf("%d\t%f\t%f\n", num, time_incl, time_excl);
// Cleanup
hipFree(dA);
hipFree(dB);
hipFree(dC);
free(hA);
free(hB);
free(hC);
free(refC);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4dataPdS_S_i
.globl _Z4dataPdS_S_i
.p2align 8
.type _Z4dataPdS_S_i,@function
_Z4dataPdS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4dataPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4dataPdS_S_i, .Lfunc_end0-_Z4dataPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4dataPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4dataPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <math.h>
#include <sys/types.h>
#include <sys/time.h>
#include <sys/stat.h>
#define BLOCK_DIM 1024
#define SEED 26
__global__ void data(double *a, double *b, double *c, int count) {
int t_id = blockDim.x * blockIdx.x + threadIdx.x;
if (t_id < count)
c[t_id] = a[t_id] + b[t_id];
}
int main (int argc, char *argv[]) {
if (argc != 2) {
printf("Usage: %s number\n", argv[0]);
exit(1);
}
// Initialize host variables
int i = 0;
double *hA, *hB, *hC, *refC;
int num = atoi(argv[1]);
long size = num*sizeof(double);
hA = (double *)malloc(size);
hB = (double *)malloc(size);
hC = (double *)malloc(size);
refC = (double *)malloc(size);
// Timing variables;
hipEvent_t incl_start, incl_end;
hipEvent_t excl_start, excl_end;
float time_incl, time_excl;
hipEventCreate(&incl_start);
hipEventCreate(&incl_end);
hipEventCreate(&excl_start);
hipEventCreate(&excl_end);
// Populate hA, hB, refC
srand(SEED);
for (i=0; i<num; i++) {
hA[i] = -10 + rand() % 20;
hB[i] = -10 + rand() % 20;
refC[i] = hA[i] + hB[i];
}
// Device memory allocation
double *dA, *dB, *dC;
hipMalloc((void **)&dA, size);
hipMalloc((void **)&dB, size);
hipMalloc((void **)&dC, size);
hipEventRecord(incl_start, 0);
hipMemcpy(dA, hA, size, hipMemcpyHostToDevice);
hipMemcpy(dB, hB, size, hipMemcpyHostToDevice);
// Launch kernel
int GRID_DIM = (num % BLOCK_DIM == 0)
? num / BLOCK_DIM
: (int)(num / BLOCK_DIM) + 1;
dim3 dimGrid(GRID_DIM, 1, 1);
dim3 dimBlock(BLOCK_DIM, 1, 1);
hipEventRecord(excl_start, 0);
data<<<dimGrid, dimBlock>>>(dA, dB, dC, num);
hipEventRecord(excl_end, 0);
hipEventSynchronize(excl_end);
hipMemcpy(hC, dC, size, hipMemcpyDeviceToHost);
hipEventRecord(incl_end, 0);
hipEventSynchronize(incl_end);
// Verify results
for (i=0; i<num; i++) {
if (fabs(refC[i] - hC[i]) > 1e-12) {
printf("FAIL\n");
exit(1);
}
}
// Print metrics
hipEventElapsedTime(&time_incl, incl_start, incl_end);
hipEventElapsedTime(&time_excl, excl_start, excl_end);
//time_incl *= 1000;
//time_excl *= 1000;
//printf("Inclusive: %f\n", incl_diff);
//printf("Exclusive: %f\n", excl_diff);
//printf("Size = %d\n Inclusive Time = %f\n Exclusive Time = %f\n", num, time_incl, time_excl);
printf("%d\t%f\t%f\n", num, time_incl, time_excl);
// Cleanup
hipFree(dA);
hipFree(dB);
hipFree(dC);
free(hA);
free(hB);
free(hC);
free(refC);
return 0;
} | .text
.file "q2_1024.hip"
.globl _Z19__device_stub__dataPdS_S_i # -- Begin function _Z19__device_stub__dataPdS_S_i
.p2align 4, 0x90
.type _Z19__device_stub__dataPdS_S_i,@function
_Z19__device_stub__dataPdS_S_i: # @_Z19__device_stub__dataPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4dataPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__dataPdS_S_i, .Lfunc_end0-_Z19__device_stub__dataPdS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0x3d719799812dea11 # double 9.9999999999999998E-13
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB1_15
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 8(%rsp) # 8-byte Spill
movslq %eax, %r13
leaq (,%r13,8), %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, %r15
movq %r12, 80(%rsp) # 8-byte Spill
movq %r12, %rdi
callq malloc
movq %rax, %r12
leaq 96(%rsp), %rdi
callq hipEventCreate
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 88(%rsp), %rdi
callq hipEventCreate
leaq 40(%rsp), %rdi
callq hipEventCreate
movl $26, %edi
callq srand
testl %r13d, %r13d
jle .LBB1_4
# %bb.2: # %.lr.ph.preheader
movl 8(%rsp), %r13d # 4-byte Reload
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
shll $2, %ecx
leal (%rcx,%rcx,4), %ecx
negl %ecx
addl %ecx, %eax
addl $-10, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%rbx,%rbp,8)
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
shll $2, %ecx
leal (%rcx,%rcx,4), %ecx
negl %ecx
addl %ecx, %eax
addl $-10, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%r14,%rbp,8)
addsd (%rbx,%rbp,8), %xmm0
movsd %xmm0, (%r12,%rbp,8)
incq %rbp
cmpq %rbp, %r13
jne .LBB1_3
.LBB1_4: # %._crit_edge
leaq 32(%rsp), %rdi
movq 80(%rsp), %r13 # 8-byte Reload
movq %r13, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
movq %rbx, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %r14, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rcx # 8-byte Reload
testl $1023, %ecx # imm = 0x3FF
je .LBB1_5
# %bb.6:
leal 1023(%rcx), %eax
testl %ecx, %ecx
cmovnsl %ecx, %eax
sarl $10, %eax
incl %eax
jmp .LBB1_7
.LBB1_5:
movl %ecx, %eax
sarl $10, %eax
.LBB1_7:
movl %eax, %r13d
movabsq $4294967296, %rbp # imm = 0x100000000
orq %rbp, %r13
movq 88(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
orq $1024, %rbp # imm = 0x400
movq %r13, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq 8(%rsp), %r13 # 8-byte Reload
jne .LBB1_9
# %bb.8:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movl %r13d, 60(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 60(%rsp), %rax
movq %rax, 184(%rsp)
leaq 64(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z4dataPdS_S_i, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_9:
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq %r15, %rdi
movq 80(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 48(%rsp), %rdi
callq hipEventSynchronize
testl %r13d, %r13d
jle .LBB1_14
# %bb.10: # %.lr.ph59.preheader
movl %r13d, %eax
xorl %ecx, %ecx
movapd .LCPI1_0(%rip), %xmm0 # xmm0 = [NaN,NaN]
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB1_12: # %.lr.ph59
# =>This Inner Loop Header: Depth=1
movsd (%r12,%rcx,8), %xmm2 # xmm2 = mem[0],zero
subsd (%r15,%rcx,8), %xmm2
andpd %xmm0, %xmm2
ucomisd %xmm1, %xmm2
ja .LBB1_13
# %bb.11: # in Loop: Header=BB1_12 Depth=1
incq %rcx
cmpq %rcx, %rax
jne .LBB1_12
.LBB1_14: # %._crit_edge60
movq 96(%rsp), %rsi
movq 48(%rsp), %rdx
leaq 160(%rsp), %rdi
callq hipEventElapsedTime
movq 88(%rsp), %rsi
movq 40(%rsp), %rdx
leaq 64(%rsp), %rdi
callq hipEventElapsedTime
movss 160(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss 64(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str.2, %edi
movl %r13d, %esi
movb $2, %al
callq printf
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_13:
.cfi_def_cfa_offset 256
movl $.Lstr, %edi
callq puts@PLT
movl $1, %edi
callq exit
.LBB1_15:
movq (%rsi), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4dataPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4dataPdS_S_i,@object # @_Z4dataPdS_S_i
.section .rodata,"a",@progbits
.globl _Z4dataPdS_S_i
.p2align 3, 0x0
_Z4dataPdS_S_i:
.quad _Z19__device_stub__dataPdS_S_i
.size _Z4dataPdS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Usage: %s number\n"
.size .L.str, 18
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d\t%f\t%f\n"
.size .L.str.2, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4dataPdS_S_i"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "FAIL"
.size .Lstr, 5
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__dataPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4dataPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4dataPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R8, R9, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R2, R8.reuse, R9.reuse, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0209 */
/*00d0*/ DADD R6, R4, R2 ; /* 0x0000000004067229 */
/* 0x004e0e0000000002 */
/*00e0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4dataPdS_S_i
.globl _Z4dataPdS_S_i
.p2align 8
.type _Z4dataPdS_S_i,@function
_Z4dataPdS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4dataPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4dataPdS_S_i, .Lfunc_end0-_Z4dataPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4dataPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4dataPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a171a_00000000-6_q2_1024.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z4dataPdS_S_iPdS_S_i
.type _Z28__device_stub__Z4dataPdS_S_iPdS_S_i, @function
_Z28__device_stub__Z4dataPdS_S_iPdS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4dataPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z4dataPdS_S_iPdS_S_i, .-_Z28__device_stub__Z4dataPdS_S_iPdS_S_i
.globl _Z4dataPdS_S_i
.type _Z4dataPdS_S_i, @function
_Z4dataPdS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z4dataPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4dataPdS_S_i, .-_Z4dataPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Usage: %s number\n"
.LC3:
.string "FAIL\n"
.LC4:
.string "%d\t%f\t%f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jne .L28
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movq %rax, 24(%rsp)
movl %eax, 12(%rsp)
cltq
leaq 0(,%rax,8), %rbx
movq %rbx, 16(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
movl $26, %edi
call srand@PLT
testl %r15d, %r15d
jle .L13
leal -1(%r15), %r15d
movl $0, %ebx
.L14:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $35, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
sall $2, %edx
subl %edx, %eax
subl $10, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, 0(%r13,%rbx,8)
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $35, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
sall $2, %edx
subl %edx, %eax
subl $10, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%r14,%rbx,8)
addsd 0(%r13,%rbx,8), %xmm0
movsd %xmm0, 0(%rbp,%rbx,8)
movq %rbx, %rax
addq $1, %rbx
cmpq %r15, %rax
jne .L14
.L13:
leaq 72(%rsp), %rdi
movq 16(%rsp), %rbx
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
testq $1023, 24(%rsp)
jne .L15
movl $1024, %ecx
movl 12(%rsp), %eax
cltd
idivl %ecx
.L16:
movl %eax, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1024, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movl 116(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movq 96(%rsp), %rdi
movl 104(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L17:
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $2, %ecx
movq 16(%rsp), %rdx
movq 88(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 24(%rsp), %rax
testl %eax, %eax
jle .L18
movl %eax, %edx
movl $0, %eax
movq .LC1(%rip), %xmm2
movsd .LC2(%rip), %xmm1
.L21:
movsd 0(%rbp,%rax,8), %xmm0
subsd (%r12,%rax,8), %xmm0
andpd %xmm2, %xmm0
comisd %xmm1, %xmm0
ja .L30
addq $1, %rax
cmpq %rdx, %rax
jne .L21
.L18:
leaq 32(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 36(%rsp), %rdi
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 32(%rsp), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 36(%rsp), %xmm1
movl 12(%rsp), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movq (%rsi), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L15:
movl $1024, %ecx
movl 12(%rsp), %eax
cltd
idivl %ecx
addl $1, %eax
jmp .L16
.L29:
movl 12(%rsp), %ecx
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z28__device_stub__Z4dataPdS_S_iPdS_S_i
jmp .L17
.L30:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z4dataPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z4dataPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC1:
.long -1
.long 2147483647
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long -2127697391
.long 1030854553
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "q2_1024.hip"
.globl _Z19__device_stub__dataPdS_S_i # -- Begin function _Z19__device_stub__dataPdS_S_i
.p2align 4, 0x90
.type _Z19__device_stub__dataPdS_S_i,@function
_Z19__device_stub__dataPdS_S_i: # @_Z19__device_stub__dataPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4dataPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__dataPdS_S_i, .Lfunc_end0-_Z19__device_stub__dataPdS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0x3d719799812dea11 # double 9.9999999999999998E-13
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB1_15
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 8(%rsp) # 8-byte Spill
movslq %eax, %r13
leaq (,%r13,8), %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, %r15
movq %r12, 80(%rsp) # 8-byte Spill
movq %r12, %rdi
callq malloc
movq %rax, %r12
leaq 96(%rsp), %rdi
callq hipEventCreate
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 88(%rsp), %rdi
callq hipEventCreate
leaq 40(%rsp), %rdi
callq hipEventCreate
movl $26, %edi
callq srand
testl %r13d, %r13d
jle .LBB1_4
# %bb.2: # %.lr.ph.preheader
movl 8(%rsp), %r13d # 4-byte Reload
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
shll $2, %ecx
leal (%rcx,%rcx,4), %ecx
negl %ecx
addl %ecx, %eax
addl $-10, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%rbx,%rbp,8)
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
shll $2, %ecx
leal (%rcx,%rcx,4), %ecx
negl %ecx
addl %ecx, %eax
addl $-10, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%r14,%rbp,8)
addsd (%rbx,%rbp,8), %xmm0
movsd %xmm0, (%r12,%rbp,8)
incq %rbp
cmpq %rbp, %r13
jne .LBB1_3
.LBB1_4: # %._crit_edge
leaq 32(%rsp), %rdi
movq 80(%rsp), %r13 # 8-byte Reload
movq %r13, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
movq %rbx, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %r14, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rcx # 8-byte Reload
testl $1023, %ecx # imm = 0x3FF
je .LBB1_5
# %bb.6:
leal 1023(%rcx), %eax
testl %ecx, %ecx
cmovnsl %ecx, %eax
sarl $10, %eax
incl %eax
jmp .LBB1_7
.LBB1_5:
movl %ecx, %eax
sarl $10, %eax
.LBB1_7:
movl %eax, %r13d
movabsq $4294967296, %rbp # imm = 0x100000000
orq %rbp, %r13
movq 88(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
orq $1024, %rbp # imm = 0x400
movq %r13, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq 8(%rsp), %r13 # 8-byte Reload
jne .LBB1_9
# %bb.8:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movl %r13d, 60(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 60(%rsp), %rax
movq %rax, 184(%rsp)
leaq 64(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z4dataPdS_S_i, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_9:
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq %r15, %rdi
movq 80(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 48(%rsp), %rdi
callq hipEventSynchronize
testl %r13d, %r13d
jle .LBB1_14
# %bb.10: # %.lr.ph59.preheader
movl %r13d, %eax
xorl %ecx, %ecx
movapd .LCPI1_0(%rip), %xmm0 # xmm0 = [NaN,NaN]
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB1_12: # %.lr.ph59
# =>This Inner Loop Header: Depth=1
movsd (%r12,%rcx,8), %xmm2 # xmm2 = mem[0],zero
subsd (%r15,%rcx,8), %xmm2
andpd %xmm0, %xmm2
ucomisd %xmm1, %xmm2
ja .LBB1_13
# %bb.11: # in Loop: Header=BB1_12 Depth=1
incq %rcx
cmpq %rcx, %rax
jne .LBB1_12
.LBB1_14: # %._crit_edge60
movq 96(%rsp), %rsi
movq 48(%rsp), %rdx
leaq 160(%rsp), %rdi
callq hipEventElapsedTime
movq 88(%rsp), %rsi
movq 40(%rsp), %rdx
leaq 64(%rsp), %rdi
callq hipEventElapsedTime
movss 160(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss 64(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str.2, %edi
movl %r13d, %esi
movb $2, %al
callq printf
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_13:
.cfi_def_cfa_offset 256
movl $.Lstr, %edi
callq puts@PLT
movl $1, %edi
callq exit
.LBB1_15:
movq (%rsi), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4dataPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4dataPdS_S_i,@object # @_Z4dataPdS_S_i
.section .rodata,"a",@progbits
.globl _Z4dataPdS_S_i
.p2align 3, 0x0
_Z4dataPdS_S_i:
.quad _Z19__device_stub__dataPdS_S_i
.size _Z4dataPdS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Usage: %s number\n"
.size .L.str, 18
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d\t%f\t%f\n"
.size .L.str.2, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4dataPdS_S_i"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "FAIL"
.size .Lstr, 5
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__dataPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4dataPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void non_max_supp_kernel(unsigned char *data, unsigned char *out, unsigned char *theta, int rows, int cols) {
extern __shared__ int l_mem[];
int* l_data = l_mem;
// These variables are offset by one to avoid seg. fault errors
// As such, this kernel ignores the outside ring of pixels
const int L_SIZE = blockDim.x;
const int g_row = blockIdx.y * blockDim.y + threadIdx.y + 1;
const int g_col = blockIdx.x * blockDim.x + threadIdx.x + 1;
const int l_row = threadIdx.y + 1;
const int l_col = threadIdx.x + 1;
const int pos = g_row * cols + g_col;
// copy to l_data
l_data[l_row * (L_SIZE + 2) + l_col] = data[pos];
// top most row
if(l_row == 1) {
l_data[0 * (L_SIZE + 2) + l_col] = data[pos - cols];
// top left
if(l_col == 1)
l_data[0 * (L_SIZE + 2) + 0] = data[pos - cols - 1];
// top right
else if(l_col == L_SIZE)
l_data[0 * (L_SIZE + 2) + (L_SIZE + 1)] = data[pos - cols + 1];
}
// bottom most row
else if(l_row == L_SIZE) {
l_data[(L_SIZE + 1) * (L_SIZE + 2) + l_col] = data[pos + cols];
// bottom left
if(l_col == 1)
l_data[(L_SIZE + 1) * (L_SIZE + 2) + 0] = data[pos + cols - 1];
// bottom right
else if(l_col == L_SIZE)
l_data[(L_SIZE + 1) * (L_SIZE + 2) + (L_SIZE + 1)] = data[pos + cols + 1];
}
if(l_col == 1)
l_data[l_row * (L_SIZE + 2) + 0] = data[pos - 1];
else if(l_col == L_SIZE)
l_data[l_row * (L_SIZE + 2) + (L_SIZE + 1)] = data[pos + 1];
__syncthreads();
unsigned char my_magnitude = l_data[l_row * (L_SIZE + 2) + l_col];
// The following variables are used to address the matrices more easily
switch(theta[pos]) {
// A gradient angle of 0 degrees = an edge that is North/South
// Check neighbors to the East and West
case 0:
// supress me if my neighbor has larger magnitude
if(my_magnitude <= l_data[l_row * (L_SIZE + 2) + l_col + 1] || // east
my_magnitude <= l_data[l_row * (L_SIZE + 2) + l_col - 1]) // west
{
out[pos] = 0;
}
// otherwise, copy my value to the output buffer
else {
out[pos] = my_magnitude;
}
break;
// A gradient angle of 45 degrees = an edge that is NW/SE
// Check neighbors to the NE and SW
case 45:
// supress me if my neighbor has larger magnitude
if(my_magnitude <= l_data[(l_row - 1) * (L_SIZE + 2) + l_col + 1] || // north east
my_magnitude <= l_data[(l_row + 1) * (L_SIZE + 2) + l_col - 1]) // south west
{
out[pos] = 0;
}
// otherwise, copy my value to the output buffer
else {
out[pos] = my_magnitude;
}
break;
// A gradient angle of 90 degrees = an edge that is E/W
// Check neighbors to the North and South
case 90:
// supress me if my neighbor has larger magnitude
if(my_magnitude <= l_data[(l_row - 1) * (L_SIZE + 2) + l_col] || // north
my_magnitude <= l_data[(l_row + 1) * (L_SIZE + 2) + l_col]) // south
{
out[pos] = 0;
}
// otherwise, copy my value to the output buffer
else {
out[pos] = my_magnitude;
}
break;
// A gradient angle of 135 degrees = an edge that is NE/SW
// Check neighbors to the NW and SE
case 135:
// supress me if my neighbor has larger magnitude
if(my_magnitude <= l_data[(l_row - 1) * (L_SIZE + 2) + l_col - 1] || // north west
my_magnitude <= l_data[(l_row + 1) * (L_SIZE + 2) + l_col + 1]) // south east
{
out[pos] = 0;
}
// otherwise, copy my value to the output buffer
else {
out[pos] = my_magnitude;
}
break;
default: out[pos] = my_magnitude; break;
}
} | code for sm_80
Function : _Z19non_max_supp_kernelPhS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e680000002100 */
/*0050*/ S2R R13, SR_CTAID.Y ; /* 0x00000000000d7919 */
/* 0x000ea20000002600 */
/*0060*/ IADD3 R6, R0, 0x1, RZ ; /* 0x0000000100067810 */
/* 0x001fe20007ffe0ff */
/*0070*/ IMAD R9, R2, c[0x0][0x0], R5 ; /* 0x0000000002097a24 */
/* 0x002fc800078e0205 */
/*0080*/ IMAD R2, R13, c[0x0][0x4], R6 ; /* 0x000001000d027a24 */
/* 0x004fc800078e0206 */
/*0090*/ IMAD R8, R2, c[0x0][0x17c], R9 ; /* 0x00005f0002087a24 */
/* 0x000fca00078e0209 */
/*00a0*/ IADD3 R2, P0, R8, c[0x0][0x160], RZ ; /* 0x0000580008027a10 */
/* 0x000fc80007f1e0ff */
/*00b0*/ LEA.HI.X.SX32 R3, R8, c[0x0][0x164], 0x1, P0 ; /* 0x0000590008037a11 */
/* 0x000fca00000f0eff */
/*00c0*/ LDG.E.U8 R11, [R2.64+0x1] ; /* 0x00000106020b7981 */
/* 0x000ea2000c1e1100 */
/*00d0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x2 ; /* 0x00000002ff077424 */
/* 0x000fe200078e00ff */
/*00e0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*00f0*/ BSSY B0, 0x4b0 ; /* 0x000003b000007945 */
/* 0x000fe20003800000 */
/*0100*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe40007ffe0ff */
/*0110*/ IADD3 R7, R7, c[0x0][0x0], RZ ; /* 0x0000000007077a10 */
/* 0x000fca0007ffe0ff */
/*0120*/ IMAD R4, R6, R7, R5 ; /* 0x0000000706047224 */
/* 0x000fca00078e0205 */
/*0130*/ STS [R4.X4+0x4], R11 ; /* 0x0000040b04007388 */
/* 0x0041e20000004800 */
/*0140*/ @!P0 BRA 0x300 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0150*/ ISETP.NE.AND P0, PT, R6, c[0x0][0x0], PT ; /* 0x0000000006007a0c */
/* 0x000fda0003f05270 */
/*0160*/ @P0 BRA 0x4a0 ; /* 0x0000033000000947 */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff0b7624 */
/* 0x001fe200078e00ff */
/*0180*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff097819 */
/* 0x000fc80000011408 */
/*0190*/ SHF.R.S32.HI R12, RZ, 0x1f, R11 ; /* 0x0000001fff0c7819 */
/* 0x000fe4000001140b */
/*01a0*/ IADD3 R10, P0, P1, R11, c[0x0][0x160], R8 ; /* 0x000058000b0a7a10 */
/* 0x000fc8000791e008 */
/*01b0*/ IADD3.X R11, R12, c[0x0][0x164], R9, P0, P1 ; /* 0x000059000c0b7a10 */
/* 0x000fca00007e2409 */
/*01c0*/ LDG.E.U8 R9, [R10.64] ; /* 0x000000060a097981 */
/* 0x000ea2000c1e1100 */
/*01d0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*01e0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*01f0*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fcc000fffe03f */
/*0200*/ IMAD R12, R7, UR4, RZ ; /* 0x00000004070c7c24 */
/* 0x000fc8000f8e02ff */
/*0210*/ IMAD.IADD R14, R12, 0x1, R5 ; /* 0x000000010c0e7824 */
/* 0x000fca00078e0205 */
/*0220*/ STS [R14.X4+0x4], R9 ; /* 0x000004090e007388 */
/* 0x0041e20000004800 */
/*0230*/ @!P0 BRA 0x2c0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0240*/ IADD3 R9, R5, 0x1, RZ ; /* 0x0000000105097810 */
/* 0x001fc80007ffe0ff */
/*0250*/ ISETP.NE.AND P0, PT, R9, c[0x0][0x0], PT ; /* 0x0000000009007a0c */
/* 0x000fda0003f05270 */
/*0260*/ @P0 BRA 0x4a0 ; /* 0x0000023000000947 */
/* 0x000fea0003800000 */
/*0270*/ LDG.E.U8 R10, [R10.64+0x1] ; /* 0x000001060a0a7981 */
/* 0x000ea2000c1e1100 */
/*0280*/ IADD3 R12, R12, c[0x0][0x0], RZ ; /* 0x000000000c0c7a10 */
/* 0x000fca0007ffe0ff */
/*0290*/ IMAD.SHL.U32 R9, R12, 0x4, RZ ; /* 0x000000040c097824 */
/* 0x000fca00078e00ff */
/*02a0*/ STS [R9+0x4], R10 ; /* 0x0000040a09007388 */
/* 0x0041e20000000800 */
/*02b0*/ BRA 0x4a0 ; /* 0x000001e000007947 */
/* 0x000fea0003800000 */
/*02c0*/ LDG.E.U8 R10, [R10.64+-0x1] ; /* 0xffffff060a0a7981 */
/* 0x000ea2000c1e1100 */
/*02d0*/ IMAD.SHL.U32 R9, R12, 0x4, RZ ; /* 0x000000040c097824 */
/* 0x001fca00078e00ff */
/*02e0*/ STS [R9], R10 ; /* 0x0000000a09007388 */
/* 0x0041e20000000800 */
/*02f0*/ BRA 0x4a0 ; /* 0x000001a000007947 */
/* 0x000fea0003800000 */
/*0300*/ IMAD R10, R13, c[0x0][0x4], R0 ; /* 0x000001000d0a7a24 */
/* 0x000fca00078e0200 */
/*0310*/ IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a7810 */
/* 0x000fca0007ffe0ff */
/*0320*/ IMAD R10, R10, c[0x0][0x17c], R9 ; /* 0x00005f000a0a7a24 */
/* 0x000fca00078e0209 */
/*0330*/ IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a7810 */
/* 0x000fc80007ffe0ff */
/*0340*/ IADD3 R9, R10, -c[0x0][0x17c], RZ ; /* 0x80005f000a097a10 */
/* 0x000fc80007ffe0ff */
/*0350*/ IADD3 R12, P0, R9, c[0x0][0x160], RZ ; /* 0x00005800090c7a10 */
/* 0x000fc80007f1e0ff */
/*0360*/ LEA.HI.X.SX32 R13, R9, c[0x0][0x164], 0x1, P0 ; /* 0x00005900090d7a11 */
/* 0x000fca00000f0eff */
/*0370*/ LDG.E.U8 R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000ea2000c1e1100 */
/*0380*/ ULDC UR4, c[0x0][0x17c] ; /* 0x00005f0000047ab9 */
/* 0x000fe20000000800 */
/*0390*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f25270 */
/*03a0*/ ULOP3.LUT UR4, URZ, UR4, URZ, 0x33, !UPT ; /* 0x000000043f047292 */
/* 0x000fcc000f8e333f */
/*03b0*/ IADD3 R9, R10, UR4, RZ ; /* 0x000000040a097c10 */
/* 0x000fc8000fffe0ff */
/*03c0*/ IADD3 R10, P0, R9, c[0x0][0x160], RZ ; /* 0x00005800090a7a10 */
/* 0x000fc80007f1e0ff */
/*03d0*/ LEA.HI.X.SX32 R11, R9, c[0x0][0x164], 0x1, P0 ; /* 0x00005900090b7a11 */
/* 0x001fe200000f0eff */
/*03e0*/ STS [R5.X4+0x4], R12 ; /* 0x0000040c05007388 */
/* 0x0041e20000004800 */
/*03f0*/ @!P1 BRA 0x480 ; /* 0x0000008000009947 */
/* 0x000fea0003800000 */
/*0400*/ IADD3 R9, R5, 0x1, RZ ; /* 0x0000000105097810 */
/* 0x000fc80007ffe0ff */
/*0410*/ ISETP.NE.AND P0, PT, R9, c[0x0][0x0], PT ; /* 0x0000000009007a0c */
/* 0x000fda0003f05270 */
/*0420*/ @P0 BRA 0x4a0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0430*/ LDG.E.U8 R10, [R10.64+0x2] ; /* 0x000002060a0a7981 */
/* 0x000ea2000c1e1100 */
/*0440*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0450*/ ULEA UR4, UR4, 0x4, 0x2 ; /* 0x0000000404047891 */
/* 0x000fd2000f8e103f */
/*0460*/ STS [UR4], R10 ; /* 0x0000000aff007988 */
/* 0x0043e20008000804 */
/*0470*/ BRA 0x4a0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0480*/ LDG.E.U8 R10, [R10.64] ; /* 0x000000060a0a7981 */
/* 0x000ea8000c1e1100 */
/*0490*/ STS [RZ], R10 ; /* 0x0000000aff007388 */
/* 0x0043e40000000800 */
/*04a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04b0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*04c0*/ BSSY B0, 0x590 ; /* 0x000000c000007945 */
/* 0x000fd80003800000 */
/*04d0*/ @!P0 BRA 0x550 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*04e0*/ IADD3 R9, R5, 0x1, RZ ; /* 0x0000000105097810 */
/* 0x001fc80007ffe0ff */
/*04f0*/ ISETP.NE.AND P0, PT, R9, c[0x0][0x0], PT ; /* 0x0000000009007a0c */
/* 0x000fda0003f05270 */
/*0500*/ @P0 BRA 0x580 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0510*/ LDG.E.U8 R2, [R2.64+0x2] ; /* 0x0000020602027981 */
/* 0x000ea2000c1e1100 */
/*0520*/ IMAD R9, R6, R7, c[0x0][0x0] ; /* 0x0000000006097624 */
/* 0x000fca00078e0207 */
/*0530*/ STS [R9.X4+0x4], R2 ; /* 0x0000040209007388 */
/* 0x0041e20000004800 */
/*0540*/ BRA 0x580 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0550*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1100 */
/*0560*/ IMAD R9, R6, R7, RZ ; /* 0x0000000706097224 */
/* 0x001fca00078e02ff */
/*0570*/ STS [R9.X4], R2 ; /* 0x0000000209007388 */
/* 0x0041e40000004800 */
/*0580*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0590*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*05a0*/ SHF.R.S32.HI R2, RZ, 0x1f, R8 ; /* 0x0000001fff027819 */
/* 0x001fe40000011408 */
/*05b0*/ IADD3 R10, P0, R8, c[0x0][0x170], RZ ; /* 0x00005c00080a7a10 */
/* 0x002fc80007f1e0ff */
/*05c0*/ IADD3.X R11, R2, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d00020b7a10 */
/* 0x000fca00007fe4ff */
/*05d0*/ LDG.E.U8 R10, [R10.64] ; /* 0x000000060a0a7981 */
/* 0x000ea2000c1e1100 */
/*05e0*/ IADD3 R8, P1, R8, c[0x0][0x168], RZ ; /* 0x00005a0008087a10 */
/* 0x000fe20007f3e0ff */
/*05f0*/ BSSY B0, 0x8d0 ; /* 0x000002d000007945 */
/* 0x000fe40003800000 */
/*0600*/ LDS.U8 R3, [R4.X4+0x4] ; /* 0x0000040004037984 */
/* 0x0000620000004000 */
/*0610*/ IADD3.X R9, R2, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0002097a10 */
/* 0x000fe40000ffe4ff */
/*0620*/ ISETP.GT.AND P0, PT, R10, 0x59, PT ; /* 0x000000590a00780c */
/* 0x004fda0003f04270 */
/*0630*/ @P0 BRA 0x7c0 ; /* 0x0000018000000947 */
/* 0x000fea0003800000 */
/*0640*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x003fda0003f05270 */
/*0650*/ @!P0 BRA 0x740 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0660*/ ISETP.NE.AND P0, PT, R10, 0x2d, PT ; /* 0x0000002d0a00780c */
/* 0x000fda0003f05270 */
/*0670*/ @P0 BRA 0x8c0 ; /* 0x0000024000000947 */
/* 0x000fea0003800000 */
/*0680*/ IMAD R2, R7, R0, R5 ; /* 0x0000000007027224 */
/* 0x000fcc00078e0205 */
/*0690*/ LDS R2, [R2.X4+0x8] ; /* 0x0000080002027984 */
/* 0x000e240000004800 */
/*06a0*/ ISETP.GT.AND P0, PT, R3, R2, PT ; /* 0x000000020300720c */
/* 0x001fda0003f04270 */
/*06b0*/ @P0 IMAD.SHL.U32 R4, R7, 0x2, RZ ; /* 0x0000000207040824 */
/* 0x000fc800078e00ff */
/*06c0*/ @P0 IMAD R4, R7, R0, R4 ; /* 0x0000000007040224 */
/* 0x000fc800078e0204 */
/*06d0*/ @P0 IMAD.IADD R4, R4, 0x1, R5 ; /* 0x0000000104040824 */
/* 0x000fcc00078e0205 */
/*06e0*/ @P0 LDS R4, [R4.X4] ; /* 0x0000000004040984 */
/* 0x000e240000004800 */
/*06f0*/ ISETP.LE.OR P0, PT, R3, R4, !P0 ; /* 0x000000040300720c */
/* 0x001fda0004703670 */
/*0700*/ @!P0 STG.E.U8 [R8.64], R3 ; /* 0x0000000308008986 */
/* 0x0001e2000c101106 */
/*0710*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0720*/ STG.E.U8 [R8.64], RZ ; /* 0x000000ff08007986 */
/* 0x000fe2000c101106 */
/*0730*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0740*/ LDS R0, [R4.X4+0x8] ; /* 0x0000080004007984 */
/* 0x000e240000004800 */
/*0750*/ ISETP.GT.AND P0, PT, R3, R0, PT ; /* 0x000000000300720c */
/* 0x001fda0003f04270 */
/*0760*/ @P0 LDS R0, [R4.X4] ; /* 0x0000000004000984 */
/* 0x000e240000004800 */
/*0770*/ ISETP.LE.OR P0, PT, R3, R0, !P0 ; /* 0x000000000300720c */
/* 0x001fda0004703670 */
/*0780*/ @!P0 STG.E.U8 [R8.64], R3 ; /* 0x0000000308008986 */
/* 0x0001e2000c101106 */
/*0790*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*07a0*/ STG.E.U8 [R8.64], RZ ; /* 0x000000ff08007986 */
/* 0x000fe2000c101106 */
/*07b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07c0*/ ISETP.NE.AND P0, PT, R10, 0x5a, PT ; /* 0x0000005a0a00780c */
/* 0x003fda0003f05270 */
/*07d0*/ @!P0 BRA 0x8f0 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*07e0*/ ISETP.NE.AND P0, PT, R10, 0x87, PT ; /* 0x000000870a00780c */
/* 0x000fda0003f05270 */
/*07f0*/ @P0 BRA 0x8c0 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*0800*/ IMAD R2, R7, R0, R5 ; /* 0x0000000007027224 */
/* 0x000fcc00078e0205 */
/*0810*/ LDS R2, [R2.X4] ; /* 0x0000000002027984 */
/* 0x000e240000004800 */
/*0820*/ ISETP.GT.AND P0, PT, R3, R2, PT ; /* 0x000000020300720c */
/* 0x001fda0003f04270 */
/*0830*/ @P0 IMAD.SHL.U32 R4, R7, 0x2, RZ ; /* 0x0000000207040824 */
/* 0x000fc800078e00ff */
/*0840*/ @P0 IMAD R4, R7, R0, R4 ; /* 0x0000000007040224 */
/* 0x000fc800078e0204 */
/*0850*/ @P0 IMAD.IADD R0, R4, 0x1, R5 ; /* 0x0000000104000824 */
/* 0x000fcc00078e0205 */
/*0860*/ @P0 LDS R0, [R0.X4+0x8] ; /* 0x0000080000000984 */
/* 0x000e240000004800 */
/*0870*/ ISETP.LE.OR P0, PT, R3, R0, !P0 ; /* 0x000000000300720c */
/* 0x001fda0004703670 */
/*0880*/ @!P0 STG.E.U8 [R8.64], R3 ; /* 0x0000000308008986 */
/* 0x0001e2000c101106 */
/*0890*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*08a0*/ STG.E.U8 [R8.64], RZ ; /* 0x000000ff08007986 */
/* 0x000fe2000c101106 */
/*08b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08d0*/ STG.E.U8 [R8.64], R3 ; /* 0x0000000308007986 */
/* 0x000fe2000c101106 */
/*08e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08f0*/ IMAD R2, R7, R0, R5 ; /* 0x0000000007027224 */
/* 0x000fcc00078e0205 */
/*0900*/ LDS R2, [R2.X4+0x4] ; /* 0x0000040002027984 */
/* 0x000e240000004800 */
/*0910*/ ISETP.GT.AND P0, PT, R3, R2, PT ; /* 0x000000020300720c */
/* 0x001fda0003f04270 */
/*0920*/ @P0 IMAD.SHL.U32 R4, R7, 0x2, RZ ; /* 0x0000000207040824 */
/* 0x000fc800078e00ff */
/*0930*/ @P0 IMAD R4, R7, R0, R4 ; /* 0x0000000007040224 */
/* 0x000fc800078e0204 */
/*0940*/ @P0 IMAD.IADD R0, R4, 0x1, R5 ; /* 0x0000000104000824 */
/* 0x000fcc00078e0205 */
/*0950*/ @P0 LDS R0, [R0.X4+0x4] ; /* 0x0000040000000984 */
/* 0x000e240000004800 */
/*0960*/ ISETP.LE.OR P0, PT, R3, R0, !P0 ; /* 0x000000000300720c */
/* 0x001fda0004703670 */
/*0970*/ @!P0 STG.E.U8 [R8.64], R3 ; /* 0x0000000308008986 */
/* 0x0001e2000c101106 */
/*0980*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0990*/ STG.E.U8 [R8.64], RZ ; /* 0x000000ff08007986 */
/* 0x000fe2000c101106 */
/*09a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09b0*/ BRA 0x9b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void non_max_supp_kernel(unsigned char *data, unsigned char *out, unsigned char *theta, int rows, int cols) {
extern __shared__ int l_mem[];
int* l_data = l_mem;
// These variables are offset by one to avoid seg. fault errors
// As such, this kernel ignores the outside ring of pixels
const int L_SIZE = blockDim.x;
const int g_row = blockIdx.y * blockDim.y + threadIdx.y + 1;
const int g_col = blockIdx.x * blockDim.x + threadIdx.x + 1;
const int l_row = threadIdx.y + 1;
const int l_col = threadIdx.x + 1;
const int pos = g_row * cols + g_col;
// copy to l_data
l_data[l_row * (L_SIZE + 2) + l_col] = data[pos];
// top most row
if(l_row == 1) {
l_data[0 * (L_SIZE + 2) + l_col] = data[pos - cols];
// top left
if(l_col == 1)
l_data[0 * (L_SIZE + 2) + 0] = data[pos - cols - 1];
// top right
else if(l_col == L_SIZE)
l_data[0 * (L_SIZE + 2) + (L_SIZE + 1)] = data[pos - cols + 1];
}
// bottom most row
else if(l_row == L_SIZE) {
l_data[(L_SIZE + 1) * (L_SIZE + 2) + l_col] = data[pos + cols];
// bottom left
if(l_col == 1)
l_data[(L_SIZE + 1) * (L_SIZE + 2) + 0] = data[pos + cols - 1];
// bottom right
else if(l_col == L_SIZE)
l_data[(L_SIZE + 1) * (L_SIZE + 2) + (L_SIZE + 1)] = data[pos + cols + 1];
}
if(l_col == 1)
l_data[l_row * (L_SIZE + 2) + 0] = data[pos - 1];
else if(l_col == L_SIZE)
l_data[l_row * (L_SIZE + 2) + (L_SIZE + 1)] = data[pos + 1];
__syncthreads();
unsigned char my_magnitude = l_data[l_row * (L_SIZE + 2) + l_col];
// The following variables are used to address the matrices more easily
switch(theta[pos]) {
// A gradient angle of 0 degrees = an edge that is North/South
// Check neighbors to the East and West
case 0:
// supress me if my neighbor has larger magnitude
if(my_magnitude <= l_data[l_row * (L_SIZE + 2) + l_col + 1] || // east
my_magnitude <= l_data[l_row * (L_SIZE + 2) + l_col - 1]) // west
{
out[pos] = 0;
}
// otherwise, copy my value to the output buffer
else {
out[pos] = my_magnitude;
}
break;
// A gradient angle of 45 degrees = an edge that is NW/SE
// Check neighbors to the NE and SW
case 45:
// supress me if my neighbor has larger magnitude
if(my_magnitude <= l_data[(l_row - 1) * (L_SIZE + 2) + l_col + 1] || // north east
my_magnitude <= l_data[(l_row + 1) * (L_SIZE + 2) + l_col - 1]) // south west
{
out[pos] = 0;
}
// otherwise, copy my value to the output buffer
else {
out[pos] = my_magnitude;
}
break;
// A gradient angle of 90 degrees = an edge that is E/W
// Check neighbors to the North and South
case 90:
// supress me if my neighbor has larger magnitude
if(my_magnitude <= l_data[(l_row - 1) * (L_SIZE + 2) + l_col] || // north
my_magnitude <= l_data[(l_row + 1) * (L_SIZE + 2) + l_col]) // south
{
out[pos] = 0;
}
// otherwise, copy my value to the output buffer
else {
out[pos] = my_magnitude;
}
break;
// A gradient angle of 135 degrees = an edge that is NE/SW
// Check neighbors to the NW and SE
case 135:
// supress me if my neighbor has larger magnitude
if(my_magnitude <= l_data[(l_row - 1) * (L_SIZE + 2) + l_col - 1] || // north west
my_magnitude <= l_data[(l_row + 1) * (L_SIZE + 2) + l_col + 1]) // south east
{
out[pos] = 0;
}
// otherwise, copy my value to the output buffer
else {
out[pos] = my_magnitude;
}
break;
default: out[pos] = my_magnitude; break;
}
} | .file "tmpxft_0008e6ca_00000000-6_non_max_supp_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z19non_max_supp_kernelPhS_S_iiPhS_S_ii
.type _Z45__device_stub__Z19non_max_supp_kernelPhS_S_iiPhS_S_ii, @function
_Z45__device_stub__Z19non_max_supp_kernelPhS_S_iiPhS_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19non_max_supp_kernelPhS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z19non_max_supp_kernelPhS_S_iiPhS_S_ii, .-_Z45__device_stub__Z19non_max_supp_kernelPhS_S_iiPhS_S_ii
.globl _Z19non_max_supp_kernelPhS_S_ii
.type _Z19non_max_supp_kernelPhS_S_ii, @function
_Z19non_max_supp_kernelPhS_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z19non_max_supp_kernelPhS_S_iiPhS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19non_max_supp_kernelPhS_S_ii, .-_Z19non_max_supp_kernelPhS_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19non_max_supp_kernelPhS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19non_max_supp_kernelPhS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void non_max_supp_kernel(unsigned char *data, unsigned char *out, unsigned char *theta, int rows, int cols) {
extern __shared__ int l_mem[];
int* l_data = l_mem;
// These variables are offset by one to avoid seg. fault errors
// As such, this kernel ignores the outside ring of pixels
const int L_SIZE = blockDim.x;
const int g_row = blockIdx.y * blockDim.y + threadIdx.y + 1;
const int g_col = blockIdx.x * blockDim.x + threadIdx.x + 1;
const int l_row = threadIdx.y + 1;
const int l_col = threadIdx.x + 1;
const int pos = g_row * cols + g_col;
// copy to l_data
l_data[l_row * (L_SIZE + 2) + l_col] = data[pos];
// top most row
if(l_row == 1) {
l_data[0 * (L_SIZE + 2) + l_col] = data[pos - cols];
// top left
if(l_col == 1)
l_data[0 * (L_SIZE + 2) + 0] = data[pos - cols - 1];
// top right
else if(l_col == L_SIZE)
l_data[0 * (L_SIZE + 2) + (L_SIZE + 1)] = data[pos - cols + 1];
}
// bottom most row
else if(l_row == L_SIZE) {
l_data[(L_SIZE + 1) * (L_SIZE + 2) + l_col] = data[pos + cols];
// bottom left
if(l_col == 1)
l_data[(L_SIZE + 1) * (L_SIZE + 2) + 0] = data[pos + cols - 1];
// bottom right
else if(l_col == L_SIZE)
l_data[(L_SIZE + 1) * (L_SIZE + 2) + (L_SIZE + 1)] = data[pos + cols + 1];
}
if(l_col == 1)
l_data[l_row * (L_SIZE + 2) + 0] = data[pos - 1];
else if(l_col == L_SIZE)
l_data[l_row * (L_SIZE + 2) + (L_SIZE + 1)] = data[pos + 1];
__syncthreads();
unsigned char my_magnitude = l_data[l_row * (L_SIZE + 2) + l_col];
// The following variables are used to address the matrices more easily
switch(theta[pos]) {
// A gradient angle of 0 degrees = an edge that is North/South
// Check neighbors to the East and West
case 0:
// supress me if my neighbor has larger magnitude
if(my_magnitude <= l_data[l_row * (L_SIZE + 2) + l_col + 1] || // east
my_magnitude <= l_data[l_row * (L_SIZE + 2) + l_col - 1]) // west
{
out[pos] = 0;
}
// otherwise, copy my value to the output buffer
else {
out[pos] = my_magnitude;
}
break;
// A gradient angle of 45 degrees = an edge that is NW/SE
// Check neighbors to the NE and SW
case 45:
// supress me if my neighbor has larger magnitude
if(my_magnitude <= l_data[(l_row - 1) * (L_SIZE + 2) + l_col + 1] || // north east
my_magnitude <= l_data[(l_row + 1) * (L_SIZE + 2) + l_col - 1]) // south west
{
out[pos] = 0;
}
// otherwise, copy my value to the output buffer
else {
out[pos] = my_magnitude;
}
break;
// A gradient angle of 90 degrees = an edge that is E/W
// Check neighbors to the North and South
case 90:
// supress me if my neighbor has larger magnitude
if(my_magnitude <= l_data[(l_row - 1) * (L_SIZE + 2) + l_col] || // north
my_magnitude <= l_data[(l_row + 1) * (L_SIZE + 2) + l_col]) // south
{
out[pos] = 0;
}
// otherwise, copy my value to the output buffer
else {
out[pos] = my_magnitude;
}
break;
// A gradient angle of 135 degrees = an edge that is NE/SW
// Check neighbors to the NW and SE
case 135:
// supress me if my neighbor has larger magnitude
if(my_magnitude <= l_data[(l_row - 1) * (L_SIZE + 2) + l_col - 1] || // north west
my_magnitude <= l_data[(l_row + 1) * (L_SIZE + 2) + l_col + 1]) // south east
{
out[pos] = 0;
}
// otherwise, copy my value to the output buffer
else {
out[pos] = my_magnitude;
}
break;
default: out[pos] = my_magnitude; break;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void non_max_supp_kernel(unsigned char *data, unsigned char *out, unsigned char *theta, int rows, int cols) {
extern __shared__ int l_mem[];
int* l_data = l_mem;
// These variables are offset by one to avoid seg. fault errors
// As such, this kernel ignores the outside ring of pixels
const int L_SIZE = blockDim.x;
const int g_row = blockIdx.y * blockDim.y + threadIdx.y + 1;
const int g_col = blockIdx.x * blockDim.x + threadIdx.x + 1;
const int l_row = threadIdx.y + 1;
const int l_col = threadIdx.x + 1;
const int pos = g_row * cols + g_col;
// copy to l_data
l_data[l_row * (L_SIZE + 2) + l_col] = data[pos];
// top most row
if(l_row == 1) {
l_data[0 * (L_SIZE + 2) + l_col] = data[pos - cols];
// top left
if(l_col == 1)
l_data[0 * (L_SIZE + 2) + 0] = data[pos - cols - 1];
// top right
else if(l_col == L_SIZE)
l_data[0 * (L_SIZE + 2) + (L_SIZE + 1)] = data[pos - cols + 1];
}
// bottom most row
else if(l_row == L_SIZE) {
l_data[(L_SIZE + 1) * (L_SIZE + 2) + l_col] = data[pos + cols];
// bottom left
if(l_col == 1)
l_data[(L_SIZE + 1) * (L_SIZE + 2) + 0] = data[pos + cols - 1];
// bottom right
else if(l_col == L_SIZE)
l_data[(L_SIZE + 1) * (L_SIZE + 2) + (L_SIZE + 1)] = data[pos + cols + 1];
}
if(l_col == 1)
l_data[l_row * (L_SIZE + 2) + 0] = data[pos - 1];
else if(l_col == L_SIZE)
l_data[l_row * (L_SIZE + 2) + (L_SIZE + 1)] = data[pos + 1];
__syncthreads();
unsigned char my_magnitude = l_data[l_row * (L_SIZE + 2) + l_col];
// The following variables are used to address the matrices more easily
switch(theta[pos]) {
// A gradient angle of 0 degrees = an edge that is North/South
// Check neighbors to the East and West
case 0:
// supress me if my neighbor has larger magnitude
if(my_magnitude <= l_data[l_row * (L_SIZE + 2) + l_col + 1] || // east
my_magnitude <= l_data[l_row * (L_SIZE + 2) + l_col - 1]) // west
{
out[pos] = 0;
}
// otherwise, copy my value to the output buffer
else {
out[pos] = my_magnitude;
}
break;
// A gradient angle of 45 degrees = an edge that is NW/SE
// Check neighbors to the NE and SW
case 45:
// supress me if my neighbor has larger magnitude
if(my_magnitude <= l_data[(l_row - 1) * (L_SIZE + 2) + l_col + 1] || // north east
my_magnitude <= l_data[(l_row + 1) * (L_SIZE + 2) + l_col - 1]) // south west
{
out[pos] = 0;
}
// otherwise, copy my value to the output buffer
else {
out[pos] = my_magnitude;
}
break;
// A gradient angle of 90 degrees = an edge that is E/W
// Check neighbors to the North and South
case 90:
// supress me if my neighbor has larger magnitude
if(my_magnitude <= l_data[(l_row - 1) * (L_SIZE + 2) + l_col] || // north
my_magnitude <= l_data[(l_row + 1) * (L_SIZE + 2) + l_col]) // south
{
out[pos] = 0;
}
// otherwise, copy my value to the output buffer
else {
out[pos] = my_magnitude;
}
break;
// A gradient angle of 135 degrees = an edge that is NE/SW
// Check neighbors to the NW and SE
case 135:
// supress me if my neighbor has larger magnitude
if(my_magnitude <= l_data[(l_row - 1) * (L_SIZE + 2) + l_col - 1] || // north west
my_magnitude <= l_data[(l_row + 1) * (L_SIZE + 2) + l_col + 1]) // south east
{
out[pos] = 0;
}
// otherwise, copy my value to the output buffer
else {
out[pos] = my_magnitude;
}
break;
default: out[pos] = my_magnitude; break;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void non_max_supp_kernel(unsigned char *data, unsigned char *out, unsigned char *theta, int rows, int cols) {
extern __shared__ int l_mem[];
int* l_data = l_mem;
// These variables are offset by one to avoid seg. fault errors
// As such, this kernel ignores the outside ring of pixels
const int L_SIZE = blockDim.x;
const int g_row = blockIdx.y * blockDim.y + threadIdx.y + 1;
const int g_col = blockIdx.x * blockDim.x + threadIdx.x + 1;
const int l_row = threadIdx.y + 1;
const int l_col = threadIdx.x + 1;
const int pos = g_row * cols + g_col;
// copy to l_data
l_data[l_row * (L_SIZE + 2) + l_col] = data[pos];
// top most row
if(l_row == 1) {
l_data[0 * (L_SIZE + 2) + l_col] = data[pos - cols];
// top left
if(l_col == 1)
l_data[0 * (L_SIZE + 2) + 0] = data[pos - cols - 1];
// top right
else if(l_col == L_SIZE)
l_data[0 * (L_SIZE + 2) + (L_SIZE + 1)] = data[pos - cols + 1];
}
// bottom most row
else if(l_row == L_SIZE) {
l_data[(L_SIZE + 1) * (L_SIZE + 2) + l_col] = data[pos + cols];
// bottom left
if(l_col == 1)
l_data[(L_SIZE + 1) * (L_SIZE + 2) + 0] = data[pos + cols - 1];
// bottom right
else if(l_col == L_SIZE)
l_data[(L_SIZE + 1) * (L_SIZE + 2) + (L_SIZE + 1)] = data[pos + cols + 1];
}
if(l_col == 1)
l_data[l_row * (L_SIZE + 2) + 0] = data[pos - 1];
else if(l_col == L_SIZE)
l_data[l_row * (L_SIZE + 2) + (L_SIZE + 1)] = data[pos + 1];
__syncthreads();
unsigned char my_magnitude = l_data[l_row * (L_SIZE + 2) + l_col];
// The following variables are used to address the matrices more easily
switch(theta[pos]) {
// A gradient angle of 0 degrees = an edge that is North/South
// Check neighbors to the East and West
case 0:
// supress me if my neighbor has larger magnitude
if(my_magnitude <= l_data[l_row * (L_SIZE + 2) + l_col + 1] || // east
my_magnitude <= l_data[l_row * (L_SIZE + 2) + l_col - 1]) // west
{
out[pos] = 0;
}
// otherwise, copy my value to the output buffer
else {
out[pos] = my_magnitude;
}
break;
// A gradient angle of 45 degrees = an edge that is NW/SE
// Check neighbors to the NE and SW
case 45:
// supress me if my neighbor has larger magnitude
if(my_magnitude <= l_data[(l_row - 1) * (L_SIZE + 2) + l_col + 1] || // north east
my_magnitude <= l_data[(l_row + 1) * (L_SIZE + 2) + l_col - 1]) // south west
{
out[pos] = 0;
}
// otherwise, copy my value to the output buffer
else {
out[pos] = my_magnitude;
}
break;
// A gradient angle of 90 degrees = an edge that is E/W
// Check neighbors to the North and South
case 90:
// supress me if my neighbor has larger magnitude
if(my_magnitude <= l_data[(l_row - 1) * (L_SIZE + 2) + l_col] || // north
my_magnitude <= l_data[(l_row + 1) * (L_SIZE + 2) + l_col]) // south
{
out[pos] = 0;
}
// otherwise, copy my value to the output buffer
else {
out[pos] = my_magnitude;
}
break;
// A gradient angle of 135 degrees = an edge that is NE/SW
// Check neighbors to the NW and SE
case 135:
// supress me if my neighbor has larger magnitude
if(my_magnitude <= l_data[(l_row - 1) * (L_SIZE + 2) + l_col - 1] || // north west
my_magnitude <= l_data[(l_row + 1) * (L_SIZE + 2) + l_col + 1]) // south east
{
out[pos] = 0;
}
// otherwise, copy my value to the output buffer
else {
out[pos] = my_magnitude;
}
break;
default: out[pos] = my_magnitude; break;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19non_max_supp_kernelPhS_S_ii
.globl _Z19non_max_supp_kernelPhS_S_ii
.p2align 8
.type _Z19non_max_supp_kernelPhS_S_ii,@function
_Z19non_max_supp_kernelPhS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s6, s[0:1], 0x1c
v_bfe_u32 v8, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 1, v8
v_add_nc_u32_e32 v9, 1, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v13, 2, v9
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s4, 16
s_and_b32 s5, s4, 0xffff
v_mad_u64_u32 v[5:6], null, s15, s2, v[4:5]
s_load_b64 s[2:3], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s14, s5, v[0:1]
s_add_i32 s4, s5, 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_u32_u24_e32 v10, s4, v4
v_mul_lo_u32 v12, v5, s6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v11, 2, v10
v_add3_u32 v6, v12, v1, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v11, 0, v11, v13
v_ashrrev_i32_e32 v7, 31, v6
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v7, vcc_lo
global_load_u8 v5, v[2:3], off
s_waitcnt vmcnt(0)
ds_store_b32 v11, v5
v_cmpx_ne_u32_e32 0, v8
s_xor_b32 s7, exec_lo, s7
s_cbranch_execz .LBB0_9
s_mov_b32 s8, exec_lo
v_cmpx_eq_u32_e64 s5, v4
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v4, s6, v6
s_add_i32 s10, s5, 1
v_lshlrev_b32_e32 v14, 2, v9
s_mul_i32 s9, s10, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
s_lshl_b32 s11, s9, 2
v_ashrrev_i32_e32 v5, 31, v4
v_add_co_u32 v4, vcc_lo, s2, v4
v_add3_u32 v14, 0, s11, v14
s_mov_b32 s11, exec_lo
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_u8 v13, v[4:5], off
s_waitcnt vmcnt(0)
ds_store_b32 v14, v13
v_cmpx_ne_u32_e32 0, v0
s_xor_b32 s11, exec_lo, s11
s_cbranch_execz .LBB0_6
s_mov_b32 s12, exec_lo
v_cmpx_eq_u32_e64 s5, v9
s_cbranch_execz .LBB0_5
global_load_u8 v4, v[4:5], off offset:1
s_lshl_b32 s13, s9, 2
s_lshl_b32 s10, s10, 2
s_add_i32 s13, s13, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s10, s13, s10
v_mov_b32_e32 v5, s10
s_waitcnt vmcnt(0)
ds_store_b32 v5, v4
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s12
.LBB0_6:
s_and_not1_saveexec_b32 s10, s11
s_cbranch_execz .LBB0_8
global_load_u8 v4, v[4:5], off offset:-1
s_lshl_b32 s9, s9, 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s9, s9, 0
v_mov_b32_e32 v5, s9
s_waitcnt vmcnt(0)
ds_store_b32 v5, v4
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s8
.LBB0_9:
s_and_not1_saveexec_b32 s7, s7
s_cbranch_execz .LBB0_17
v_subrev_nc_u32_e32 v4, s6, v6
v_lshl_add_u32 v14, v9, 2, 0
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_u8 v13, v[4:5], off
s_waitcnt vmcnt(0)
ds_store_b32 v14, v13
v_cmpx_ne_u32_e32 0, v0
s_xor_b32 s6, exec_lo, s6
s_cbranch_execz .LBB0_14
s_mov_b32 s8, exec_lo
v_cmpx_eq_u32_e64 s5, v9
s_cbranch_execz .LBB0_13
global_load_u8 v4, v[4:5], off offset:1
s_lshl_b32 s9, s5, 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s9, s9, 0
v_mov_b32_e32 v5, s9
s_waitcnt vmcnt(0)
ds_store_b32 v5, v4 offset:4
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s8
.LBB0_14:
s_and_not1_saveexec_b32 s6, s6
s_cbranch_execz .LBB0_16
global_load_u8 v4, v[4:5], off offset:-1
v_mov_b32_e32 v5, 0
s_waitcnt vmcnt(0)
ds_store_b32 v5, v4
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s6
.LBB0_17:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s7
s_mov_b32 s6, exec_lo
v_cmpx_ne_u32_e32 0, v0
s_xor_b32 s6, exec_lo, s6
s_cbranch_execz .LBB0_21
s_mov_b32 s7, exec_lo
v_cmpx_eq_u32_e64 s5, v9
s_cbranch_execz .LBB0_20
global_load_u8 v1, v[2:3], off offset:1
v_lshlrev_b32_e32 v2, 2, v10
s_lshl_b32 s5, s5, 2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add3_u32 v2, s5, 0, v2
s_waitcnt vmcnt(0)
ds_store_b32 v2, v1 offset:4
.LBB0_20:
s_or_b32 exec_lo, exec_lo, s7
.LBB0_21:
s_and_not1_saveexec_b32 s5, s6
s_cbranch_execz .LBB0_23
v_add_nc_u32_e32 v1, v12, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_u8 v1, v[1:2], off
v_lshl_add_u32 v2, v10, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v2, v1
.LBB0_23:
s_or_b32 exec_lo, exec_lo, s5
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_add_co_u32 v1, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v7, vcc_lo
s_mov_b32 s2, 0
s_mov_b32 s3, exec_lo
global_load_u8 v4, v[1:2], off
ds_load_b32 v1, v11
s_waitcnt lgkmcnt(0)
v_and_b32_e32 v1, 0xff, v1
s_waitcnt vmcnt(0)
v_cmpx_lt_i16_e32 0x59, v4
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_37
s_mov_b32 s5, exec_lo
v_cmpx_lt_i16_e32 0x86, v4
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB0_30
v_mov_b32_e32 v3, v1
s_mov_b32 s6, 0
s_mov_b32 s2, exec_lo
v_cmpx_eq_u16_e32 0x87, v4
s_cbranch_execz .LBB0_29
v_mul_u32_u24_e32 v2, s4, v8
v_lshlrev_b32_e32 v0, 2, v0
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v2, 2, v2
v_add3_u32 v0, 0, v2, v0
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 v1, v0
s_xor_b32 s7, exec_lo, s7
v_add_nc_u32_e32 v0, 2, v8
v_lshlrev_b32_e32 v2, 2, v9
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_u32_u24_e32 v0, s4, v0
v_lshl_add_u32 v0, v0, 2, 0
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v2, v0, v2, 4
s_or_b32 exec_lo, exec_lo, s7
v_mov_b32_e32 v3, 0
s_and_b32 s6, s6, exec_lo
.LBB0_29:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s2, s6, exec_lo
.LBB0_30:
s_and_not1_saveexec_b32 s5, s5
s_cbranch_execz .LBB0_36
v_mov_b32_e32 v3, v1
s_mov_b32 s7, s2
s_mov_b32 s6, exec_lo
v_cmpx_eq_u16_e32 0x5a, v4
s_cbranch_execz .LBB0_35
v_mul_u32_u24_e32 v0, s4, v8
s_mov_b32 s7, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v2, 2, v0
v_lshlrev_b32_e32 v0, 2, v9
v_add3_u32 v2, 0, v2, v0
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v1, v2
s_and_saveexec_b32 s8, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s8, exec_lo, s8
v_add_nc_u32_e32 v2, 2, v8
s_or_b32 s7, s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_u32_u24_e32 v2, s4, v2
v_lshlrev_b32_e32 v2, 2, v2
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v2, 0, v2, v0
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v3, 0
s_and_not1_b32 s8, s2, exec_lo
s_and_b32 s7, s7, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s7, s8, s7
.LBB0_35:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s2, exec_lo
s_and_b32 s6, s7, exec_lo
s_or_b32 s2, s2, s6
.LBB0_36:
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s2, s2, exec_lo
.LBB0_37:
s_and_not1_saveexec_b32 s3, s3
s_cbranch_execz .LBB0_51
s_mov_b32 s5, s2
s_mov_b32 s6, exec_lo
v_cmpx_lt_i16_e32 44, v4
s_xor_b32 s6, exec_lo, s6
s_cbranch_execz .LBB0_44
v_mov_b32_e32 v3, v1
s_mov_b32 s7, s2
s_mov_b32 s5, exec_lo
v_cmpx_eq_u16_e32 45, v4
s_cbranch_execz .LBB0_43
v_mul_u32_u24_e32 v2, s4, v8
v_lshlrev_b32_e32 v3, 2, v9
s_mov_b32 s7, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v2, 2, v2
v_add3_u32 v2, 0, v2, v3
ds_load_b32 v2, v2 offset:4
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v1, v2
s_and_saveexec_b32 s8, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s8, exec_lo, s8
v_add_nc_u32_e32 v2, 2, v8
v_lshlrev_b32_e32 v0, 2, v0
s_or_b32 s7, s2, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_u32_u24_e32 v2, s4, v2
v_lshlrev_b32_e32 v2, 2, v2
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v2, 0, v2, v0
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v3, 0
s_and_not1_b32 s4, s2, exec_lo
s_and_b32 s7, s7, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s7, s4, s7
.LBB0_43:
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s4, s2, exec_lo
s_and_b32 s5, s7, exec_lo
s_or_b32 s5, s4, s5
.LBB0_44:
s_and_not1_saveexec_b32 s4, s6
s_cbranch_execz .LBB0_50
v_mov_b32_e32 v3, v1
s_mov_b32 s7, s5
s_mov_b32 s6, exec_lo
v_cmpx_eq_u16_e32 0, v4
s_cbranch_execz .LBB0_49
ds_load_b32 v2, v11 offset:4
s_mov_b32 s7, s5
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v1, v2
s_and_saveexec_b32 s8, vcc_lo
v_lshlrev_b32_e32 v2, 2, v10
v_lshlrev_b32_e32 v0, 2, v0
s_or_b32 s7, s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v2, 0, v2, v0
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v3, 0
s_and_not1_b32 s8, s5, exec_lo
s_and_b32 s7, s7, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s7, s8, s7
.LBB0_49:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s5, s5, exec_lo
s_and_b32 s6, s7, exec_lo
s_or_b32 s5, s5, s6
.LBB0_50:
s_or_b32 exec_lo, exec_lo, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s2, exec_lo
s_and_b32 s4, s5, exec_lo
s_or_b32 s2, s2, s4
.LBB0_51:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_53
ds_load_b32 v0, v2
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v1, v0
v_cndmask_b32_e32 v3, 0, v1, vcc_lo
.LBB0_53:
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v7, vcc_lo
global_store_b8 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19non_max_supp_kernelPhS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19non_max_supp_kernelPhS_S_ii, .Lfunc_end0-_Z19non_max_supp_kernelPhS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19non_max_supp_kernelPhS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19non_max_supp_kernelPhS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void non_max_supp_kernel(unsigned char *data, unsigned char *out, unsigned char *theta, int rows, int cols) {
extern __shared__ int l_mem[];
int* l_data = l_mem;
// These variables are offset by one to avoid seg. fault errors
// As such, this kernel ignores the outside ring of pixels
const int L_SIZE = blockDim.x;
const int g_row = blockIdx.y * blockDim.y + threadIdx.y + 1;
const int g_col = blockIdx.x * blockDim.x + threadIdx.x + 1;
const int l_row = threadIdx.y + 1;
const int l_col = threadIdx.x + 1;
const int pos = g_row * cols + g_col;
// copy to l_data
l_data[l_row * (L_SIZE + 2) + l_col] = data[pos];
// top most row
if(l_row == 1) {
l_data[0 * (L_SIZE + 2) + l_col] = data[pos - cols];
// top left
if(l_col == 1)
l_data[0 * (L_SIZE + 2) + 0] = data[pos - cols - 1];
// top right
else if(l_col == L_SIZE)
l_data[0 * (L_SIZE + 2) + (L_SIZE + 1)] = data[pos - cols + 1];
}
// bottom most row
else if(l_row == L_SIZE) {
l_data[(L_SIZE + 1) * (L_SIZE + 2) + l_col] = data[pos + cols];
// bottom left
if(l_col == 1)
l_data[(L_SIZE + 1) * (L_SIZE + 2) + 0] = data[pos + cols - 1];
// bottom right
else if(l_col == L_SIZE)
l_data[(L_SIZE + 1) * (L_SIZE + 2) + (L_SIZE + 1)] = data[pos + cols + 1];
}
if(l_col == 1)
l_data[l_row * (L_SIZE + 2) + 0] = data[pos - 1];
else if(l_col == L_SIZE)
l_data[l_row * (L_SIZE + 2) + (L_SIZE + 1)] = data[pos + 1];
__syncthreads();
unsigned char my_magnitude = l_data[l_row * (L_SIZE + 2) + l_col];
// The following variables are used to address the matrices more easily
switch(theta[pos]) {
// A gradient angle of 0 degrees = an edge that is North/South
// Check neighbors to the East and West
case 0:
// supress me if my neighbor has larger magnitude
if(my_magnitude <= l_data[l_row * (L_SIZE + 2) + l_col + 1] || // east
my_magnitude <= l_data[l_row * (L_SIZE + 2) + l_col - 1]) // west
{
out[pos] = 0;
}
// otherwise, copy my value to the output buffer
else {
out[pos] = my_magnitude;
}
break;
// A gradient angle of 45 degrees = an edge that is NW/SE
// Check neighbors to the NE and SW
case 45:
// supress me if my neighbor has larger magnitude
if(my_magnitude <= l_data[(l_row - 1) * (L_SIZE + 2) + l_col + 1] || // north east
my_magnitude <= l_data[(l_row + 1) * (L_SIZE + 2) + l_col - 1]) // south west
{
out[pos] = 0;
}
// otherwise, copy my value to the output buffer
else {
out[pos] = my_magnitude;
}
break;
// A gradient angle of 90 degrees = an edge that is E/W
// Check neighbors to the North and South
case 90:
// supress me if my neighbor has larger magnitude
if(my_magnitude <= l_data[(l_row - 1) * (L_SIZE + 2) + l_col] || // north
my_magnitude <= l_data[(l_row + 1) * (L_SIZE + 2) + l_col]) // south
{
out[pos] = 0;
}
// otherwise, copy my value to the output buffer
else {
out[pos] = my_magnitude;
}
break;
// A gradient angle of 135 degrees = an edge that is NE/SW
// Check neighbors to the NW and SE
case 135:
// supress me if my neighbor has larger magnitude
if(my_magnitude <= l_data[(l_row - 1) * (L_SIZE + 2) + l_col - 1] || // north west
my_magnitude <= l_data[(l_row + 1) * (L_SIZE + 2) + l_col + 1]) // south east
{
out[pos] = 0;
}
// otherwise, copy my value to the output buffer
else {
out[pos] = my_magnitude;
}
break;
default: out[pos] = my_magnitude; break;
}
} | .text
.file "non_max_supp_kernel.hip"
.globl _Z34__device_stub__non_max_supp_kernelPhS_S_ii # -- Begin function _Z34__device_stub__non_max_supp_kernelPhS_S_ii
.p2align 4, 0x90
.type _Z34__device_stub__non_max_supp_kernelPhS_S_ii,@function
_Z34__device_stub__non_max_supp_kernelPhS_S_ii: # @_Z34__device_stub__non_max_supp_kernelPhS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19non_max_supp_kernelPhS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z34__device_stub__non_max_supp_kernelPhS_S_ii, .Lfunc_end0-_Z34__device_stub__non_max_supp_kernelPhS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19non_max_supp_kernelPhS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19non_max_supp_kernelPhS_S_ii,@object # @_Z19non_max_supp_kernelPhS_S_ii
.section .rodata,"a",@progbits
.globl _Z19non_max_supp_kernelPhS_S_ii
.p2align 3, 0x0
_Z19non_max_supp_kernelPhS_S_ii:
.quad _Z34__device_stub__non_max_supp_kernelPhS_S_ii
.size _Z19non_max_supp_kernelPhS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19non_max_supp_kernelPhS_S_ii"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__non_max_supp_kernelPhS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19non_max_supp_kernelPhS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19non_max_supp_kernelPhS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e680000002100 */
/*0050*/ S2R R13, SR_CTAID.Y ; /* 0x00000000000d7919 */
/* 0x000ea20000002600 */
/*0060*/ IADD3 R6, R0, 0x1, RZ ; /* 0x0000000100067810 */
/* 0x001fe20007ffe0ff */
/*0070*/ IMAD R9, R2, c[0x0][0x0], R5 ; /* 0x0000000002097a24 */
/* 0x002fc800078e0205 */
/*0080*/ IMAD R2, R13, c[0x0][0x4], R6 ; /* 0x000001000d027a24 */
/* 0x004fc800078e0206 */
/*0090*/ IMAD R8, R2, c[0x0][0x17c], R9 ; /* 0x00005f0002087a24 */
/* 0x000fca00078e0209 */
/*00a0*/ IADD3 R2, P0, R8, c[0x0][0x160], RZ ; /* 0x0000580008027a10 */
/* 0x000fc80007f1e0ff */
/*00b0*/ LEA.HI.X.SX32 R3, R8, c[0x0][0x164], 0x1, P0 ; /* 0x0000590008037a11 */
/* 0x000fca00000f0eff */
/*00c0*/ LDG.E.U8 R11, [R2.64+0x1] ; /* 0x00000106020b7981 */
/* 0x000ea2000c1e1100 */
/*00d0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x2 ; /* 0x00000002ff077424 */
/* 0x000fe200078e00ff */
/*00e0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*00f0*/ BSSY B0, 0x4b0 ; /* 0x000003b000007945 */
/* 0x000fe20003800000 */
/*0100*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe40007ffe0ff */
/*0110*/ IADD3 R7, R7, c[0x0][0x0], RZ ; /* 0x0000000007077a10 */
/* 0x000fca0007ffe0ff */
/*0120*/ IMAD R4, R6, R7, R5 ; /* 0x0000000706047224 */
/* 0x000fca00078e0205 */
/*0130*/ STS [R4.X4+0x4], R11 ; /* 0x0000040b04007388 */
/* 0x0041e20000004800 */
/*0140*/ @!P0 BRA 0x300 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0150*/ ISETP.NE.AND P0, PT, R6, c[0x0][0x0], PT ; /* 0x0000000006007a0c */
/* 0x000fda0003f05270 */
/*0160*/ @P0 BRA 0x4a0 ; /* 0x0000033000000947 */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff0b7624 */
/* 0x001fe200078e00ff */
/*0180*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff097819 */
/* 0x000fc80000011408 */
/*0190*/ SHF.R.S32.HI R12, RZ, 0x1f, R11 ; /* 0x0000001fff0c7819 */
/* 0x000fe4000001140b */
/*01a0*/ IADD3 R10, P0, P1, R11, c[0x0][0x160], R8 ; /* 0x000058000b0a7a10 */
/* 0x000fc8000791e008 */
/*01b0*/ IADD3.X R11, R12, c[0x0][0x164], R9, P0, P1 ; /* 0x000059000c0b7a10 */
/* 0x000fca00007e2409 */
/*01c0*/ LDG.E.U8 R9, [R10.64] ; /* 0x000000060a097981 */
/* 0x000ea2000c1e1100 */
/*01d0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*01e0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*01f0*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fcc000fffe03f */
/*0200*/ IMAD R12, R7, UR4, RZ ; /* 0x00000004070c7c24 */
/* 0x000fc8000f8e02ff */
/*0210*/ IMAD.IADD R14, R12, 0x1, R5 ; /* 0x000000010c0e7824 */
/* 0x000fca00078e0205 */
/*0220*/ STS [R14.X4+0x4], R9 ; /* 0x000004090e007388 */
/* 0x0041e20000004800 */
/*0230*/ @!P0 BRA 0x2c0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0240*/ IADD3 R9, R5, 0x1, RZ ; /* 0x0000000105097810 */
/* 0x001fc80007ffe0ff */
/*0250*/ ISETP.NE.AND P0, PT, R9, c[0x0][0x0], PT ; /* 0x0000000009007a0c */
/* 0x000fda0003f05270 */
/*0260*/ @P0 BRA 0x4a0 ; /* 0x0000023000000947 */
/* 0x000fea0003800000 */
/*0270*/ LDG.E.U8 R10, [R10.64+0x1] ; /* 0x000001060a0a7981 */
/* 0x000ea2000c1e1100 */
/*0280*/ IADD3 R12, R12, c[0x0][0x0], RZ ; /* 0x000000000c0c7a10 */
/* 0x000fca0007ffe0ff */
/*0290*/ IMAD.SHL.U32 R9, R12, 0x4, RZ ; /* 0x000000040c097824 */
/* 0x000fca00078e00ff */
/*02a0*/ STS [R9+0x4], R10 ; /* 0x0000040a09007388 */
/* 0x0041e20000000800 */
/*02b0*/ BRA 0x4a0 ; /* 0x000001e000007947 */
/* 0x000fea0003800000 */
/*02c0*/ LDG.E.U8 R10, [R10.64+-0x1] ; /* 0xffffff060a0a7981 */
/* 0x000ea2000c1e1100 */
/*02d0*/ IMAD.SHL.U32 R9, R12, 0x4, RZ ; /* 0x000000040c097824 */
/* 0x001fca00078e00ff */
/*02e0*/ STS [R9], R10 ; /* 0x0000000a09007388 */
/* 0x0041e20000000800 */
/*02f0*/ BRA 0x4a0 ; /* 0x000001a000007947 */
/* 0x000fea0003800000 */
/*0300*/ IMAD R10, R13, c[0x0][0x4], R0 ; /* 0x000001000d0a7a24 */
/* 0x000fca00078e0200 */
/*0310*/ IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a7810 */
/* 0x000fca0007ffe0ff */
/*0320*/ IMAD R10, R10, c[0x0][0x17c], R9 ; /* 0x00005f000a0a7a24 */
/* 0x000fca00078e0209 */
/*0330*/ IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a7810 */
/* 0x000fc80007ffe0ff */
/*0340*/ IADD3 R9, R10, -c[0x0][0x17c], RZ ; /* 0x80005f000a097a10 */
/* 0x000fc80007ffe0ff */
/*0350*/ IADD3 R12, P0, R9, c[0x0][0x160], RZ ; /* 0x00005800090c7a10 */
/* 0x000fc80007f1e0ff */
/*0360*/ LEA.HI.X.SX32 R13, R9, c[0x0][0x164], 0x1, P0 ; /* 0x00005900090d7a11 */
/* 0x000fca00000f0eff */
/*0370*/ LDG.E.U8 R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000ea2000c1e1100 */
/*0380*/ ULDC UR4, c[0x0][0x17c] ; /* 0x00005f0000047ab9 */
/* 0x000fe20000000800 */
/*0390*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f25270 */
/*03a0*/ ULOP3.LUT UR4, URZ, UR4, URZ, 0x33, !UPT ; /* 0x000000043f047292 */
/* 0x000fcc000f8e333f */
/*03b0*/ IADD3 R9, R10, UR4, RZ ; /* 0x000000040a097c10 */
/* 0x000fc8000fffe0ff */
/*03c0*/ IADD3 R10, P0, R9, c[0x0][0x160], RZ ; /* 0x00005800090a7a10 */
/* 0x000fc80007f1e0ff */
/*03d0*/ LEA.HI.X.SX32 R11, R9, c[0x0][0x164], 0x1, P0 ; /* 0x00005900090b7a11 */
/* 0x001fe200000f0eff */
/*03e0*/ STS [R5.X4+0x4], R12 ; /* 0x0000040c05007388 */
/* 0x0041e20000004800 */
/*03f0*/ @!P1 BRA 0x480 ; /* 0x0000008000009947 */
/* 0x000fea0003800000 */
/*0400*/ IADD3 R9, R5, 0x1, RZ ; /* 0x0000000105097810 */
/* 0x000fc80007ffe0ff */
/*0410*/ ISETP.NE.AND P0, PT, R9, c[0x0][0x0], PT ; /* 0x0000000009007a0c */
/* 0x000fda0003f05270 */
/*0420*/ @P0 BRA 0x4a0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0430*/ LDG.E.U8 R10, [R10.64+0x2] ; /* 0x000002060a0a7981 */
/* 0x000ea2000c1e1100 */
/*0440*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0450*/ ULEA UR4, UR4, 0x4, 0x2 ; /* 0x0000000404047891 */
/* 0x000fd2000f8e103f */
/*0460*/ STS [UR4], R10 ; /* 0x0000000aff007988 */
/* 0x0043e20008000804 */
/*0470*/ BRA 0x4a0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0480*/ LDG.E.U8 R10, [R10.64] ; /* 0x000000060a0a7981 */
/* 0x000ea8000c1e1100 */
/*0490*/ STS [RZ], R10 ; /* 0x0000000aff007388 */
/* 0x0043e40000000800 */
/*04a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04b0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*04c0*/ BSSY B0, 0x590 ; /* 0x000000c000007945 */
/* 0x000fd80003800000 */
/*04d0*/ @!P0 BRA 0x550 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*04e0*/ IADD3 R9, R5, 0x1, RZ ; /* 0x0000000105097810 */
/* 0x001fc80007ffe0ff */
/*04f0*/ ISETP.NE.AND P0, PT, R9, c[0x0][0x0], PT ; /* 0x0000000009007a0c */
/* 0x000fda0003f05270 */
/*0500*/ @P0 BRA 0x580 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0510*/ LDG.E.U8 R2, [R2.64+0x2] ; /* 0x0000020602027981 */
/* 0x000ea2000c1e1100 */
/*0520*/ IMAD R9, R6, R7, c[0x0][0x0] ; /* 0x0000000006097624 */
/* 0x000fca00078e0207 */
/*0530*/ STS [R9.X4+0x4], R2 ; /* 0x0000040209007388 */
/* 0x0041e20000004800 */
/*0540*/ BRA 0x580 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0550*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1100 */
/*0560*/ IMAD R9, R6, R7, RZ ; /* 0x0000000706097224 */
/* 0x001fca00078e02ff */
/*0570*/ STS [R9.X4], R2 ; /* 0x0000000209007388 */
/* 0x0041e40000004800 */
/*0580*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0590*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*05a0*/ SHF.R.S32.HI R2, RZ, 0x1f, R8 ; /* 0x0000001fff027819 */
/* 0x001fe40000011408 */
/*05b0*/ IADD3 R10, P0, R8, c[0x0][0x170], RZ ; /* 0x00005c00080a7a10 */
/* 0x002fc80007f1e0ff */
/*05c0*/ IADD3.X R11, R2, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d00020b7a10 */
/* 0x000fca00007fe4ff */
/*05d0*/ LDG.E.U8 R10, [R10.64] ; /* 0x000000060a0a7981 */
/* 0x000ea2000c1e1100 */
/*05e0*/ IADD3 R8, P1, R8, c[0x0][0x168], RZ ; /* 0x00005a0008087a10 */
/* 0x000fe20007f3e0ff */
/*05f0*/ BSSY B0, 0x8d0 ; /* 0x000002d000007945 */
/* 0x000fe40003800000 */
/*0600*/ LDS.U8 R3, [R4.X4+0x4] ; /* 0x0000040004037984 */
/* 0x0000620000004000 */
/*0610*/ IADD3.X R9, R2, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0002097a10 */
/* 0x000fe40000ffe4ff */
/*0620*/ ISETP.GT.AND P0, PT, R10, 0x59, PT ; /* 0x000000590a00780c */
/* 0x004fda0003f04270 */
/*0630*/ @P0 BRA 0x7c0 ; /* 0x0000018000000947 */
/* 0x000fea0003800000 */
/*0640*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x003fda0003f05270 */
/*0650*/ @!P0 BRA 0x740 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0660*/ ISETP.NE.AND P0, PT, R10, 0x2d, PT ; /* 0x0000002d0a00780c */
/* 0x000fda0003f05270 */
/*0670*/ @P0 BRA 0x8c0 ; /* 0x0000024000000947 */
/* 0x000fea0003800000 */
/*0680*/ IMAD R2, R7, R0, R5 ; /* 0x0000000007027224 */
/* 0x000fcc00078e0205 */
/*0690*/ LDS R2, [R2.X4+0x8] ; /* 0x0000080002027984 */
/* 0x000e240000004800 */
/*06a0*/ ISETP.GT.AND P0, PT, R3, R2, PT ; /* 0x000000020300720c */
/* 0x001fda0003f04270 */
/*06b0*/ @P0 IMAD.SHL.U32 R4, R7, 0x2, RZ ; /* 0x0000000207040824 */
/* 0x000fc800078e00ff */
/*06c0*/ @P0 IMAD R4, R7, R0, R4 ; /* 0x0000000007040224 */
/* 0x000fc800078e0204 */
/*06d0*/ @P0 IMAD.IADD R4, R4, 0x1, R5 ; /* 0x0000000104040824 */
/* 0x000fcc00078e0205 */
/*06e0*/ @P0 LDS R4, [R4.X4] ; /* 0x0000000004040984 */
/* 0x000e240000004800 */
/*06f0*/ ISETP.LE.OR P0, PT, R3, R4, !P0 ; /* 0x000000040300720c */
/* 0x001fda0004703670 */
/*0700*/ @!P0 STG.E.U8 [R8.64], R3 ; /* 0x0000000308008986 */
/* 0x0001e2000c101106 */
/*0710*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0720*/ STG.E.U8 [R8.64], RZ ; /* 0x000000ff08007986 */
/* 0x000fe2000c101106 */
/*0730*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0740*/ LDS R0, [R4.X4+0x8] ; /* 0x0000080004007984 */
/* 0x000e240000004800 */
/*0750*/ ISETP.GT.AND P0, PT, R3, R0, PT ; /* 0x000000000300720c */
/* 0x001fda0003f04270 */
/*0760*/ @P0 LDS R0, [R4.X4] ; /* 0x0000000004000984 */
/* 0x000e240000004800 */
/*0770*/ ISETP.LE.OR P0, PT, R3, R0, !P0 ; /* 0x000000000300720c */
/* 0x001fda0004703670 */
/*0780*/ @!P0 STG.E.U8 [R8.64], R3 ; /* 0x0000000308008986 */
/* 0x0001e2000c101106 */
/*0790*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*07a0*/ STG.E.U8 [R8.64], RZ ; /* 0x000000ff08007986 */
/* 0x000fe2000c101106 */
/*07b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07c0*/ ISETP.NE.AND P0, PT, R10, 0x5a, PT ; /* 0x0000005a0a00780c */
/* 0x003fda0003f05270 */
/*07d0*/ @!P0 BRA 0x8f0 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*07e0*/ ISETP.NE.AND P0, PT, R10, 0x87, PT ; /* 0x000000870a00780c */
/* 0x000fda0003f05270 */
/*07f0*/ @P0 BRA 0x8c0 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*0800*/ IMAD R2, R7, R0, R5 ; /* 0x0000000007027224 */
/* 0x000fcc00078e0205 */
/*0810*/ LDS R2, [R2.X4] ; /* 0x0000000002027984 */
/* 0x000e240000004800 */
/*0820*/ ISETP.GT.AND P0, PT, R3, R2, PT ; /* 0x000000020300720c */
/* 0x001fda0003f04270 */
/*0830*/ @P0 IMAD.SHL.U32 R4, R7, 0x2, RZ ; /* 0x0000000207040824 */
/* 0x000fc800078e00ff */
/*0840*/ @P0 IMAD R4, R7, R0, R4 ; /* 0x0000000007040224 */
/* 0x000fc800078e0204 */
/*0850*/ @P0 IMAD.IADD R0, R4, 0x1, R5 ; /* 0x0000000104000824 */
/* 0x000fcc00078e0205 */
/*0860*/ @P0 LDS R0, [R0.X4+0x8] ; /* 0x0000080000000984 */
/* 0x000e240000004800 */
/*0870*/ ISETP.LE.OR P0, PT, R3, R0, !P0 ; /* 0x000000000300720c */
/* 0x001fda0004703670 */
/*0880*/ @!P0 STG.E.U8 [R8.64], R3 ; /* 0x0000000308008986 */
/* 0x0001e2000c101106 */
/*0890*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*08a0*/ STG.E.U8 [R8.64], RZ ; /* 0x000000ff08007986 */
/* 0x000fe2000c101106 */
/*08b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08d0*/ STG.E.U8 [R8.64], R3 ; /* 0x0000000308007986 */
/* 0x000fe2000c101106 */
/*08e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08f0*/ IMAD R2, R7, R0, R5 ; /* 0x0000000007027224 */
/* 0x000fcc00078e0205 */
/*0900*/ LDS R2, [R2.X4+0x4] ; /* 0x0000040002027984 */
/* 0x000e240000004800 */
/*0910*/ ISETP.GT.AND P0, PT, R3, R2, PT ; /* 0x000000020300720c */
/* 0x001fda0003f04270 */
/*0920*/ @P0 IMAD.SHL.U32 R4, R7, 0x2, RZ ; /* 0x0000000207040824 */
/* 0x000fc800078e00ff */
/*0930*/ @P0 IMAD R4, R7, R0, R4 ; /* 0x0000000007040224 */
/* 0x000fc800078e0204 */
/*0940*/ @P0 IMAD.IADD R0, R4, 0x1, R5 ; /* 0x0000000104000824 */
/* 0x000fcc00078e0205 */
/*0950*/ @P0 LDS R0, [R0.X4+0x4] ; /* 0x0000040000000984 */
/* 0x000e240000004800 */
/*0960*/ ISETP.LE.OR P0, PT, R3, R0, !P0 ; /* 0x000000000300720c */
/* 0x001fda0004703670 */
/*0970*/ @!P0 STG.E.U8 [R8.64], R3 ; /* 0x0000000308008986 */
/* 0x0001e2000c101106 */
/*0980*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0990*/ STG.E.U8 [R8.64], RZ ; /* 0x000000ff08007986 */
/* 0x000fe2000c101106 */
/*09a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09b0*/ BRA 0x9b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19non_max_supp_kernelPhS_S_ii
.globl _Z19non_max_supp_kernelPhS_S_ii
.p2align 8
.type _Z19non_max_supp_kernelPhS_S_ii,@function
_Z19non_max_supp_kernelPhS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s6, s[0:1], 0x1c
v_bfe_u32 v8, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 1, v8
v_add_nc_u32_e32 v9, 1, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v13, 2, v9
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s4, 16
s_and_b32 s5, s4, 0xffff
v_mad_u64_u32 v[5:6], null, s15, s2, v[4:5]
s_load_b64 s[2:3], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s14, s5, v[0:1]
s_add_i32 s4, s5, 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_u32_u24_e32 v10, s4, v4
v_mul_lo_u32 v12, v5, s6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v11, 2, v10
v_add3_u32 v6, v12, v1, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v11, 0, v11, v13
v_ashrrev_i32_e32 v7, 31, v6
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v7, vcc_lo
global_load_u8 v5, v[2:3], off
s_waitcnt vmcnt(0)
ds_store_b32 v11, v5
v_cmpx_ne_u32_e32 0, v8
s_xor_b32 s7, exec_lo, s7
s_cbranch_execz .LBB0_9
s_mov_b32 s8, exec_lo
v_cmpx_eq_u32_e64 s5, v4
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v4, s6, v6
s_add_i32 s10, s5, 1
v_lshlrev_b32_e32 v14, 2, v9
s_mul_i32 s9, s10, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
s_lshl_b32 s11, s9, 2
v_ashrrev_i32_e32 v5, 31, v4
v_add_co_u32 v4, vcc_lo, s2, v4
v_add3_u32 v14, 0, s11, v14
s_mov_b32 s11, exec_lo
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_u8 v13, v[4:5], off
s_waitcnt vmcnt(0)
ds_store_b32 v14, v13
v_cmpx_ne_u32_e32 0, v0
s_xor_b32 s11, exec_lo, s11
s_cbranch_execz .LBB0_6
s_mov_b32 s12, exec_lo
v_cmpx_eq_u32_e64 s5, v9
s_cbranch_execz .LBB0_5
global_load_u8 v4, v[4:5], off offset:1
s_lshl_b32 s13, s9, 2
s_lshl_b32 s10, s10, 2
s_add_i32 s13, s13, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s10, s13, s10
v_mov_b32_e32 v5, s10
s_waitcnt vmcnt(0)
ds_store_b32 v5, v4
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s12
.LBB0_6:
s_and_not1_saveexec_b32 s10, s11
s_cbranch_execz .LBB0_8
global_load_u8 v4, v[4:5], off offset:-1
s_lshl_b32 s9, s9, 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s9, s9, 0
v_mov_b32_e32 v5, s9
s_waitcnt vmcnt(0)
ds_store_b32 v5, v4
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s8
.LBB0_9:
s_and_not1_saveexec_b32 s7, s7
s_cbranch_execz .LBB0_17
v_subrev_nc_u32_e32 v4, s6, v6
v_lshl_add_u32 v14, v9, 2, 0
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_u8 v13, v[4:5], off
s_waitcnt vmcnt(0)
ds_store_b32 v14, v13
v_cmpx_ne_u32_e32 0, v0
s_xor_b32 s6, exec_lo, s6
s_cbranch_execz .LBB0_14
s_mov_b32 s8, exec_lo
v_cmpx_eq_u32_e64 s5, v9
s_cbranch_execz .LBB0_13
global_load_u8 v4, v[4:5], off offset:1
s_lshl_b32 s9, s5, 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s9, s9, 0
v_mov_b32_e32 v5, s9
s_waitcnt vmcnt(0)
ds_store_b32 v5, v4 offset:4
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s8
.LBB0_14:
s_and_not1_saveexec_b32 s6, s6
s_cbranch_execz .LBB0_16
global_load_u8 v4, v[4:5], off offset:-1
v_mov_b32_e32 v5, 0
s_waitcnt vmcnt(0)
ds_store_b32 v5, v4
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s6
.LBB0_17:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s7
s_mov_b32 s6, exec_lo
v_cmpx_ne_u32_e32 0, v0
s_xor_b32 s6, exec_lo, s6
s_cbranch_execz .LBB0_21
s_mov_b32 s7, exec_lo
v_cmpx_eq_u32_e64 s5, v9
s_cbranch_execz .LBB0_20
global_load_u8 v1, v[2:3], off offset:1
v_lshlrev_b32_e32 v2, 2, v10
s_lshl_b32 s5, s5, 2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add3_u32 v2, s5, 0, v2
s_waitcnt vmcnt(0)
ds_store_b32 v2, v1 offset:4
.LBB0_20:
s_or_b32 exec_lo, exec_lo, s7
.LBB0_21:
s_and_not1_saveexec_b32 s5, s6
s_cbranch_execz .LBB0_23
v_add_nc_u32_e32 v1, v12, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_u8 v1, v[1:2], off
v_lshl_add_u32 v2, v10, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v2, v1
.LBB0_23:
s_or_b32 exec_lo, exec_lo, s5
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_add_co_u32 v1, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v7, vcc_lo
s_mov_b32 s2, 0
s_mov_b32 s3, exec_lo
global_load_u8 v4, v[1:2], off
ds_load_b32 v1, v11
s_waitcnt lgkmcnt(0)
v_and_b32_e32 v1, 0xff, v1
s_waitcnt vmcnt(0)
v_cmpx_lt_i16_e32 0x59, v4
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_37
s_mov_b32 s5, exec_lo
v_cmpx_lt_i16_e32 0x86, v4
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB0_30
v_mov_b32_e32 v3, v1
s_mov_b32 s6, 0
s_mov_b32 s2, exec_lo
v_cmpx_eq_u16_e32 0x87, v4
s_cbranch_execz .LBB0_29
v_mul_u32_u24_e32 v2, s4, v8
v_lshlrev_b32_e32 v0, 2, v0
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v2, 2, v2
v_add3_u32 v0, 0, v2, v0
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 v1, v0
s_xor_b32 s7, exec_lo, s7
v_add_nc_u32_e32 v0, 2, v8
v_lshlrev_b32_e32 v2, 2, v9
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_u32_u24_e32 v0, s4, v0
v_lshl_add_u32 v0, v0, 2, 0
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v2, v0, v2, 4
s_or_b32 exec_lo, exec_lo, s7
v_mov_b32_e32 v3, 0
s_and_b32 s6, s6, exec_lo
.LBB0_29:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s2, s6, exec_lo
.LBB0_30:
s_and_not1_saveexec_b32 s5, s5
s_cbranch_execz .LBB0_36
v_mov_b32_e32 v3, v1
s_mov_b32 s7, s2
s_mov_b32 s6, exec_lo
v_cmpx_eq_u16_e32 0x5a, v4
s_cbranch_execz .LBB0_35
v_mul_u32_u24_e32 v0, s4, v8
s_mov_b32 s7, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v2, 2, v0
v_lshlrev_b32_e32 v0, 2, v9
v_add3_u32 v2, 0, v2, v0
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v1, v2
s_and_saveexec_b32 s8, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s8, exec_lo, s8
v_add_nc_u32_e32 v2, 2, v8
s_or_b32 s7, s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_u32_u24_e32 v2, s4, v2
v_lshlrev_b32_e32 v2, 2, v2
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v2, 0, v2, v0
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v3, 0
s_and_not1_b32 s8, s2, exec_lo
s_and_b32 s7, s7, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s7, s8, s7
.LBB0_35:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s2, exec_lo
s_and_b32 s6, s7, exec_lo
s_or_b32 s2, s2, s6
.LBB0_36:
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s2, s2, exec_lo
.LBB0_37:
s_and_not1_saveexec_b32 s3, s3
s_cbranch_execz .LBB0_51
s_mov_b32 s5, s2
s_mov_b32 s6, exec_lo
v_cmpx_lt_i16_e32 44, v4
s_xor_b32 s6, exec_lo, s6
s_cbranch_execz .LBB0_44
v_mov_b32_e32 v3, v1
s_mov_b32 s7, s2
s_mov_b32 s5, exec_lo
v_cmpx_eq_u16_e32 45, v4
s_cbranch_execz .LBB0_43
v_mul_u32_u24_e32 v2, s4, v8
v_lshlrev_b32_e32 v3, 2, v9
s_mov_b32 s7, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v2, 2, v2
v_add3_u32 v2, 0, v2, v3
ds_load_b32 v2, v2 offset:4
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v1, v2
s_and_saveexec_b32 s8, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s8, exec_lo, s8
v_add_nc_u32_e32 v2, 2, v8
v_lshlrev_b32_e32 v0, 2, v0
s_or_b32 s7, s2, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_u32_u24_e32 v2, s4, v2
v_lshlrev_b32_e32 v2, 2, v2
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v2, 0, v2, v0
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v3, 0
s_and_not1_b32 s4, s2, exec_lo
s_and_b32 s7, s7, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s7, s4, s7
.LBB0_43:
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s4, s2, exec_lo
s_and_b32 s5, s7, exec_lo
s_or_b32 s5, s4, s5
.LBB0_44:
s_and_not1_saveexec_b32 s4, s6
s_cbranch_execz .LBB0_50
v_mov_b32_e32 v3, v1
s_mov_b32 s7, s5
s_mov_b32 s6, exec_lo
v_cmpx_eq_u16_e32 0, v4
s_cbranch_execz .LBB0_49
ds_load_b32 v2, v11 offset:4
s_mov_b32 s7, s5
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v1, v2
s_and_saveexec_b32 s8, vcc_lo
v_lshlrev_b32_e32 v2, 2, v10
v_lshlrev_b32_e32 v0, 2, v0
s_or_b32 s7, s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v2, 0, v2, v0
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v3, 0
s_and_not1_b32 s8, s5, exec_lo
s_and_b32 s7, s7, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s7, s8, s7
.LBB0_49:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s5, s5, exec_lo
s_and_b32 s6, s7, exec_lo
s_or_b32 s5, s5, s6
.LBB0_50:
s_or_b32 exec_lo, exec_lo, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s2, exec_lo
s_and_b32 s4, s5, exec_lo
s_or_b32 s2, s2, s4
.LBB0_51:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_53
ds_load_b32 v0, v2
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v1, v0
v_cndmask_b32_e32 v3, 0, v1, vcc_lo
.LBB0_53:
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v7, vcc_lo
global_store_b8 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19non_max_supp_kernelPhS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19non_max_supp_kernelPhS_S_ii, .Lfunc_end0-_Z19non_max_supp_kernelPhS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19non_max_supp_kernelPhS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19non_max_supp_kernelPhS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008e6ca_00000000-6_non_max_supp_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z19non_max_supp_kernelPhS_S_iiPhS_S_ii
.type _Z45__device_stub__Z19non_max_supp_kernelPhS_S_iiPhS_S_ii, @function
_Z45__device_stub__Z19non_max_supp_kernelPhS_S_iiPhS_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19non_max_supp_kernelPhS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z19non_max_supp_kernelPhS_S_iiPhS_S_ii, .-_Z45__device_stub__Z19non_max_supp_kernelPhS_S_iiPhS_S_ii
.globl _Z19non_max_supp_kernelPhS_S_ii
.type _Z19non_max_supp_kernelPhS_S_ii, @function
_Z19non_max_supp_kernelPhS_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z19non_max_supp_kernelPhS_S_iiPhS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19non_max_supp_kernelPhS_S_ii, .-_Z19non_max_supp_kernelPhS_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19non_max_supp_kernelPhS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19non_max_supp_kernelPhS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "non_max_supp_kernel.hip"
.globl _Z34__device_stub__non_max_supp_kernelPhS_S_ii # -- Begin function _Z34__device_stub__non_max_supp_kernelPhS_S_ii
.p2align 4, 0x90
.type _Z34__device_stub__non_max_supp_kernelPhS_S_ii,@function
_Z34__device_stub__non_max_supp_kernelPhS_S_ii: # @_Z34__device_stub__non_max_supp_kernelPhS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19non_max_supp_kernelPhS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z34__device_stub__non_max_supp_kernelPhS_S_ii, .Lfunc_end0-_Z34__device_stub__non_max_supp_kernelPhS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19non_max_supp_kernelPhS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19non_max_supp_kernelPhS_S_ii,@object # @_Z19non_max_supp_kernelPhS_S_ii
.section .rodata,"a",@progbits
.globl _Z19non_max_supp_kernelPhS_S_ii
.p2align 3, 0x0
_Z19non_max_supp_kernelPhS_S_ii:
.quad _Z34__device_stub__non_max_supp_kernelPhS_S_ii
.size _Z19non_max_supp_kernelPhS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19non_max_supp_kernelPhS_S_ii"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__non_max_supp_kernelPhS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19non_max_supp_kernelPhS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
//#include "helper_cuda.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#define SIZE_M (512 * 2)
#define SIZE_N (512 * 4)
#define SIZE_K (512 * 2)
#define BLOCK_SIZE 16
#define ID2INDX(_row, _col, _width) (((_row)*(_width))+(_col))
void generateValues(float** p, int size) {
for (int i = 0; i < size; i++) {
*((*p) + i) = rand() % 10 + rand() % 100 / 100.0;
}
}
__global__ void MatMul(float* matA, float* matB, float* matC, int m, int n, int k) {
int row = blockDim.x * blockIdx.x + threadIdx.x;
int col = blockDim.y * blockIdx.y + threadIdx.y;
if (row >= m || col >= n) return;
float val = 0;
for (int i = 0; i < k; i++) {
val += matA[ID2INDX(row, i, k)] * matB[ID2INDX(i, col, n)];
}
matC[ID2INDX(row, col, n)] = val;
}
void compareMatrix(float* a, float* b, int size) {
bool isPass = true;
for (int i = 0; i < size; i++) {
if (a[i] != b[i]) {
isPass = false;
//break;
//printf("%d != %d\n", a[i], b[i]);
}
}
if (isPass) printf("CPU and GPU result are same.\n");
else printf("The results are not matched!!!!\n");
}
int main(int argc, char* argv[]) {
// Matrix size
int m, n, k;
m = SIZE_M; n = SIZE_N; k = SIZE_K;
printf("Matrix A = [%d by %d]\nMatrix B = [%d by %d]\nMatrix C = [%d by %d]\n",
m, k, k, n, m, n);
int sizeA, sizeB, sizeC;
sizeA = m * k; sizeB = n * k; sizeC = m * n;
// initialize matrix A and B
float* A = NULL, * B = NULL;
A = new float[sizeA];
B = new float[sizeB];
memset(A, 0, sizeof(float) * sizeA);
memset(B, 0, sizeof(float) * sizeB);
// initialize matrix cpuC and gpuC
float* cpuC = NULL, * gpuC = NULL;
cpuC = new float[sizeC];
gpuC = new float[sizeC];
memset(cpuC, 0, sizeof(float) * sizeC);
memset(gpuC, 0, sizeof(float) * sizeC);
// input values matrix A and B
generateValues(&A, sizeA);
generateValues(&B, sizeB);
printf("CPU val: %f %f\n", A[0], B[0]);
// CPU running
for (int row = 0; row < m; row++) {
for (int col = 0; col < n; col++) {
int index = ID2INDX(row, col, n);
for (int i = 0; i < k; i++) {
cpuC[index] += A[ID2INDX(row, i, k)] * B[ID2INDX(i, col, n)];
}
}
}
printf("CPU result %f\n", cpuC[0]);
printf("CPU is finished\n");
// GPU
printf("GPU start\n");
float* dA, * dB, * dC;
cudaMalloc(&dA, sizeA * sizeof(float));
cudaMalloc(&dB, sizeB * sizeof(float));
cudaMalloc(&dC, sizeC * sizeof(float));
cudaMemset(&dA, 0, sizeA * sizeof(float));
cudaMemset(&dB, 0, sizeB * sizeof(float));
cudaMemset(&dC, 0, sizeC * sizeof(float));
cudaMemcpy(dA, A, sizeA * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(dB, B, sizeB * sizeof(float), cudaMemcpyHostToDevice);
printf("finished copy data from host to device\n");
dim3 gridDim(ceil((float)m / BLOCK_SIZE), ceil((float)n / BLOCK_SIZE));
dim3 blockDim(BLOCK_SIZE, BLOCK_SIZE);
printf("Grid(%d, %d), Block(%d, %d)\n", gridDim.x, gridDim.y, blockDim.x, blockDim.y);
MatMul << <gridDim, blockDim >> > (dA, dB, dC, m, n, k);
cudaDeviceSynchronize();
cudaMemcpy(gpuC, dC, sizeC * sizeof(float), cudaMemcpyDeviceToHost);
printf("GPU result %f\n", gpuC[0]);
compareMatrix(cpuC, gpuC, sizeC);
// 1. GPU global memory
return 0;
}
*/ | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
//#include "helper_cuda.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#define SIZE_M (512 * 2)
#define SIZE_N (512 * 4)
#define SIZE_K (512 * 2)
#define BLOCK_SIZE 16
#define ID2INDX(_row, _col, _width) (((_row)*(_width))+(_col))
void generateValues(float** p, int size) {
for (int i = 0; i < size; i++) {
*((*p) + i) = rand() % 10 + rand() % 100 / 100.0;
}
}
__global__ void MatMul(float* matA, float* matB, float* matC, int m, int n, int k) {
int row = blockDim.x * blockIdx.x + threadIdx.x;
int col = blockDim.y * blockIdx.y + threadIdx.y;
if (row >= m || col >= n) return;
float val = 0;
for (int i = 0; i < k; i++) {
val += matA[ID2INDX(row, i, k)] * matB[ID2INDX(i, col, n)];
}
matC[ID2INDX(row, col, n)] = val;
}
void compareMatrix(float* a, float* b, int size) {
bool isPass = true;
for (int i = 0; i < size; i++) {
if (a[i] != b[i]) {
isPass = false;
//break;
//printf("%d != %d\n", a[i], b[i]);
}
}
if (isPass) printf("CPU and GPU result are same.\n");
else printf("The results are not matched!!!!\n");
}
int main(int argc, char* argv[]) {
// Matrix size
int m, n, k;
m = SIZE_M; n = SIZE_N; k = SIZE_K;
printf("Matrix A = [%d by %d]\nMatrix B = [%d by %d]\nMatrix C = [%d by %d]\n",
m, k, k, n, m, n);
int sizeA, sizeB, sizeC;
sizeA = m * k; sizeB = n * k; sizeC = m * n;
// initialize matrix A and B
float* A = NULL, * B = NULL;
A = new float[sizeA];
B = new float[sizeB];
memset(A, 0, sizeof(float) * sizeA);
memset(B, 0, sizeof(float) * sizeB);
// initialize matrix cpuC and gpuC
float* cpuC = NULL, * gpuC = NULL;
cpuC = new float[sizeC];
gpuC = new float[sizeC];
memset(cpuC, 0, sizeof(float) * sizeC);
memset(gpuC, 0, sizeof(float) * sizeC);
// input values matrix A and B
generateValues(&A, sizeA);
generateValues(&B, sizeB);
printf("CPU val: %f %f\n", A[0], B[0]);
// CPU running
for (int row = 0; row < m; row++) {
for (int col = 0; col < n; col++) {
int index = ID2INDX(row, col, n);
for (int i = 0; i < k; i++) {
cpuC[index] += A[ID2INDX(row, i, k)] * B[ID2INDX(i, col, n)];
}
}
}
printf("CPU result %f\n", cpuC[0]);
printf("CPU is finished\n");
// GPU
printf("GPU start\n");
float* dA, * dB, * dC;
cudaMalloc(&dA, sizeA * sizeof(float));
cudaMalloc(&dB, sizeB * sizeof(float));
cudaMalloc(&dC, sizeC * sizeof(float));
cudaMemset(&dA, 0, sizeA * sizeof(float));
cudaMemset(&dB, 0, sizeB * sizeof(float));
cudaMemset(&dC, 0, sizeC * sizeof(float));
cudaMemcpy(dA, A, sizeA * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(dB, B, sizeB * sizeof(float), cudaMemcpyHostToDevice);
printf("finished copy data from host to device\n");
dim3 gridDim(ceil((float)m / BLOCK_SIZE), ceil((float)n / BLOCK_SIZE));
dim3 blockDim(BLOCK_SIZE, BLOCK_SIZE);
printf("Grid(%d, %d), Block(%d, %d)\n", gridDim.x, gridDim.y, blockDim.x, blockDim.y);
MatMul << <gridDim, blockDim >> > (dA, dB, dC, m, n, k);
cudaDeviceSynchronize();
cudaMemcpy(gpuC, dC, sizeC * sizeof(float), cudaMemcpyDeviceToHost);
printf("GPU result %f\n", gpuC[0]);
compareMatrix(cpuC, gpuC, sizeC);
// 1. GPU global memory
return 0;
}
*/ | .file "tmpxft_0004fd9d_00000000-6_MatMul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
//#include "helper_cuda.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#define SIZE_M (512 * 2)
#define SIZE_N (512 * 4)
#define SIZE_K (512 * 2)
#define BLOCK_SIZE 16
#define ID2INDX(_row, _col, _width) (((_row)*(_width))+(_col))
void generateValues(float** p, int size) {
for (int i = 0; i < size; i++) {
*((*p) + i) = rand() % 10 + rand() % 100 / 100.0;
}
}
__global__ void MatMul(float* matA, float* matB, float* matC, int m, int n, int k) {
int row = blockDim.x * blockIdx.x + threadIdx.x;
int col = blockDim.y * blockIdx.y + threadIdx.y;
if (row >= m || col >= n) return;
float val = 0;
for (int i = 0; i < k; i++) {
val += matA[ID2INDX(row, i, k)] * matB[ID2INDX(i, col, n)];
}
matC[ID2INDX(row, col, n)] = val;
}
void compareMatrix(float* a, float* b, int size) {
bool isPass = true;
for (int i = 0; i < size; i++) {
if (a[i] != b[i]) {
isPass = false;
//break;
//printf("%d != %d\n", a[i], b[i]);
}
}
if (isPass) printf("CPU and GPU result are same.\n");
else printf("The results are not matched!!!!\n");
}
int main(int argc, char* argv[]) {
// Matrix size
int m, n, k;
m = SIZE_M; n = SIZE_N; k = SIZE_K;
printf("Matrix A = [%d by %d]\nMatrix B = [%d by %d]\nMatrix C = [%d by %d]\n",
m, k, k, n, m, n);
int sizeA, sizeB, sizeC;
sizeA = m * k; sizeB = n * k; sizeC = m * n;
// initialize matrix A and B
float* A = NULL, * B = NULL;
A = new float[sizeA];
B = new float[sizeB];
memset(A, 0, sizeof(float) * sizeA);
memset(B, 0, sizeof(float) * sizeB);
// initialize matrix cpuC and gpuC
float* cpuC = NULL, * gpuC = NULL;
cpuC = new float[sizeC];
gpuC = new float[sizeC];
memset(cpuC, 0, sizeof(float) * sizeC);
memset(gpuC, 0, sizeof(float) * sizeC);
// input values matrix A and B
generateValues(&A, sizeA);
generateValues(&B, sizeB);
printf("CPU val: %f %f\n", A[0], B[0]);
// CPU running
for (int row = 0; row < m; row++) {
for (int col = 0; col < n; col++) {
int index = ID2INDX(row, col, n);
for (int i = 0; i < k; i++) {
cpuC[index] += A[ID2INDX(row, i, k)] * B[ID2INDX(i, col, n)];
}
}
}
printf("CPU result %f\n", cpuC[0]);
printf("CPU is finished\n");
// GPU
printf("GPU start\n");
float* dA, * dB, * dC;
cudaMalloc(&dA, sizeA * sizeof(float));
cudaMalloc(&dB, sizeB * sizeof(float));
cudaMalloc(&dC, sizeC * sizeof(float));
cudaMemset(&dA, 0, sizeA * sizeof(float));
cudaMemset(&dB, 0, sizeB * sizeof(float));
cudaMemset(&dC, 0, sizeC * sizeof(float));
cudaMemcpy(dA, A, sizeA * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(dB, B, sizeB * sizeof(float), cudaMemcpyHostToDevice);
printf("finished copy data from host to device\n");
dim3 gridDim(ceil((float)m / BLOCK_SIZE), ceil((float)n / BLOCK_SIZE));
dim3 blockDim(BLOCK_SIZE, BLOCK_SIZE);
printf("Grid(%d, %d), Block(%d, %d)\n", gridDim.x, gridDim.y, blockDim.x, blockDim.y);
MatMul << <gridDim, blockDim >> > (dA, dB, dC, m, n, k);
cudaDeviceSynchronize();
cudaMemcpy(gpuC, dC, sizeC * sizeof(float), cudaMemcpyDeviceToHost);
printf("GPU result %f\n", gpuC[0]);
compareMatrix(cpuC, gpuC, sizeC);
// 1. GPU global memory
return 0;
}
*/ | #include <hip/hip_runtime.h>
/*
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
//#include "helper_cuda.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#define SIZE_M (512 * 2)
#define SIZE_N (512 * 4)
#define SIZE_K (512 * 2)
#define BLOCK_SIZE 16
#define ID2INDX(_row, _col, _width) (((_row)*(_width))+(_col))
void generateValues(float** p, int size) {
for (int i = 0; i < size; i++) {
*((*p) + i) = rand() % 10 + rand() % 100 / 100.0;
}
}
__global__ void MatMul(float* matA, float* matB, float* matC, int m, int n, int k) {
int row = blockDim.x * blockIdx.x + threadIdx.x;
int col = blockDim.y * blockIdx.y + threadIdx.y;
if (row >= m || col >= n) return;
float val = 0;
for (int i = 0; i < k; i++) {
val += matA[ID2INDX(row, i, k)] * matB[ID2INDX(i, col, n)];
}
matC[ID2INDX(row, col, n)] = val;
}
void compareMatrix(float* a, float* b, int size) {
bool isPass = true;
for (int i = 0; i < size; i++) {
if (a[i] != b[i]) {
isPass = false;
//break;
//printf("%d != %d\n", a[i], b[i]);
}
}
if (isPass) printf("CPU and GPU result are same.\n");
else printf("The results are not matched!!!!\n");
}
int main(int argc, char* argv[]) {
// Matrix size
int m, n, k;
m = SIZE_M; n = SIZE_N; k = SIZE_K;
printf("Matrix A = [%d by %d]\nMatrix B = [%d by %d]\nMatrix C = [%d by %d]\n",
m, k, k, n, m, n);
int sizeA, sizeB, sizeC;
sizeA = m * k; sizeB = n * k; sizeC = m * n;
// initialize matrix A and B
float* A = NULL, * B = NULL;
A = new float[sizeA];
B = new float[sizeB];
memset(A, 0, sizeof(float) * sizeA);
memset(B, 0, sizeof(float) * sizeB);
// initialize matrix cpuC and gpuC
float* cpuC = NULL, * gpuC = NULL;
cpuC = new float[sizeC];
gpuC = new float[sizeC];
memset(cpuC, 0, sizeof(float) * sizeC);
memset(gpuC, 0, sizeof(float) * sizeC);
// input values matrix A and B
generateValues(&A, sizeA);
generateValues(&B, sizeB);
printf("CPU val: %f %f\n", A[0], B[0]);
// CPU running
for (int row = 0; row < m; row++) {
for (int col = 0; col < n; col++) {
int index = ID2INDX(row, col, n);
for (int i = 0; i < k; i++) {
cpuC[index] += A[ID2INDX(row, i, k)] * B[ID2INDX(i, col, n)];
}
}
}
printf("CPU result %f\n", cpuC[0]);
printf("CPU is finished\n");
// GPU
printf("GPU start\n");
float* dA, * dB, * dC;
cudaMalloc(&dA, sizeA * sizeof(float));
cudaMalloc(&dB, sizeB * sizeof(float));
cudaMalloc(&dC, sizeC * sizeof(float));
cudaMemset(&dA, 0, sizeA * sizeof(float));
cudaMemset(&dB, 0, sizeB * sizeof(float));
cudaMemset(&dC, 0, sizeC * sizeof(float));
cudaMemcpy(dA, A, sizeA * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(dB, B, sizeB * sizeof(float), cudaMemcpyHostToDevice);
printf("finished copy data from host to device\n");
dim3 gridDim(ceil((float)m / BLOCK_SIZE), ceil((float)n / BLOCK_SIZE));
dim3 blockDim(BLOCK_SIZE, BLOCK_SIZE);
printf("Grid(%d, %d), Block(%d, %d)\n", gridDim.x, gridDim.y, blockDim.x, blockDim.y);
MatMul << <gridDim, blockDim >> > (dA, dB, dC, m, n, k);
cudaDeviceSynchronize();
cudaMemcpy(gpuC, dC, sizeC * sizeof(float), cudaMemcpyDeviceToHost);
printf("GPU result %f\n", gpuC[0]);
compareMatrix(cpuC, gpuC, sizeC);
// 1. GPU global memory
return 0;
}
*/ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
//#include "helper_cuda.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#define SIZE_M (512 * 2)
#define SIZE_N (512 * 4)
#define SIZE_K (512 * 2)
#define BLOCK_SIZE 16
#define ID2INDX(_row, _col, _width) (((_row)*(_width))+(_col))
void generateValues(float** p, int size) {
for (int i = 0; i < size; i++) {
*((*p) + i) = rand() % 10 + rand() % 100 / 100.0;
}
}
__global__ void MatMul(float* matA, float* matB, float* matC, int m, int n, int k) {
int row = blockDim.x * blockIdx.x + threadIdx.x;
int col = blockDim.y * blockIdx.y + threadIdx.y;
if (row >= m || col >= n) return;
float val = 0;
for (int i = 0; i < k; i++) {
val += matA[ID2INDX(row, i, k)] * matB[ID2INDX(i, col, n)];
}
matC[ID2INDX(row, col, n)] = val;
}
void compareMatrix(float* a, float* b, int size) {
bool isPass = true;
for (int i = 0; i < size; i++) {
if (a[i] != b[i]) {
isPass = false;
//break;
//printf("%d != %d\n", a[i], b[i]);
}
}
if (isPass) printf("CPU and GPU result are same.\n");
else printf("The results are not matched!!!!\n");
}
int main(int argc, char* argv[]) {
// Matrix size
int m, n, k;
m = SIZE_M; n = SIZE_N; k = SIZE_K;
printf("Matrix A = [%d by %d]\nMatrix B = [%d by %d]\nMatrix C = [%d by %d]\n",
m, k, k, n, m, n);
int sizeA, sizeB, sizeC;
sizeA = m * k; sizeB = n * k; sizeC = m * n;
// initialize matrix A and B
float* A = NULL, * B = NULL;
A = new float[sizeA];
B = new float[sizeB];
memset(A, 0, sizeof(float) * sizeA);
memset(B, 0, sizeof(float) * sizeB);
// initialize matrix cpuC and gpuC
float* cpuC = NULL, * gpuC = NULL;
cpuC = new float[sizeC];
gpuC = new float[sizeC];
memset(cpuC, 0, sizeof(float) * sizeC);
memset(gpuC, 0, sizeof(float) * sizeC);
// input values matrix A and B
generateValues(&A, sizeA);
generateValues(&B, sizeB);
printf("CPU val: %f %f\n", A[0], B[0]);
// CPU running
for (int row = 0; row < m; row++) {
for (int col = 0; col < n; col++) {
int index = ID2INDX(row, col, n);
for (int i = 0; i < k; i++) {
cpuC[index] += A[ID2INDX(row, i, k)] * B[ID2INDX(i, col, n)];
}
}
}
printf("CPU result %f\n", cpuC[0]);
printf("CPU is finished\n");
// GPU
printf("GPU start\n");
float* dA, * dB, * dC;
cudaMalloc(&dA, sizeA * sizeof(float));
cudaMalloc(&dB, sizeB * sizeof(float));
cudaMalloc(&dC, sizeC * sizeof(float));
cudaMemset(&dA, 0, sizeA * sizeof(float));
cudaMemset(&dB, 0, sizeB * sizeof(float));
cudaMemset(&dC, 0, sizeC * sizeof(float));
cudaMemcpy(dA, A, sizeA * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(dB, B, sizeB * sizeof(float), cudaMemcpyHostToDevice);
printf("finished copy data from host to device\n");
dim3 gridDim(ceil((float)m / BLOCK_SIZE), ceil((float)n / BLOCK_SIZE));
dim3 blockDim(BLOCK_SIZE, BLOCK_SIZE);
printf("Grid(%d, %d), Block(%d, %d)\n", gridDim.x, gridDim.y, blockDim.x, blockDim.y);
MatMul << <gridDim, blockDim >> > (dA, dB, dC, m, n, k);
cudaDeviceSynchronize();
cudaMemcpy(gpuC, dC, sizeC * sizeof(float), cudaMemcpyDeviceToHost);
printf("GPU result %f\n", gpuC[0]);
compareMatrix(cpuC, gpuC, sizeC);
// 1. GPU global memory
return 0;
}
*/ | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
//#include "helper_cuda.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#define SIZE_M (512 * 2)
#define SIZE_N (512 * 4)
#define SIZE_K (512 * 2)
#define BLOCK_SIZE 16
#define ID2INDX(_row, _col, _width) (((_row)*(_width))+(_col))
void generateValues(float** p, int size) {
for (int i = 0; i < size; i++) {
*((*p) + i) = rand() % 10 + rand() % 100 / 100.0;
}
}
__global__ void MatMul(float* matA, float* matB, float* matC, int m, int n, int k) {
int row = blockDim.x * blockIdx.x + threadIdx.x;
int col = blockDim.y * blockIdx.y + threadIdx.y;
if (row >= m || col >= n) return;
float val = 0;
for (int i = 0; i < k; i++) {
val += matA[ID2INDX(row, i, k)] * matB[ID2INDX(i, col, n)];
}
matC[ID2INDX(row, col, n)] = val;
}
void compareMatrix(float* a, float* b, int size) {
bool isPass = true;
for (int i = 0; i < size; i++) {
if (a[i] != b[i]) {
isPass = false;
//break;
//printf("%d != %d\n", a[i], b[i]);
}
}
if (isPass) printf("CPU and GPU result are same.\n");
else printf("The results are not matched!!!!\n");
}
int main(int argc, char* argv[]) {
// Matrix size
int m, n, k;
m = SIZE_M; n = SIZE_N; k = SIZE_K;
printf("Matrix A = [%d by %d]\nMatrix B = [%d by %d]\nMatrix C = [%d by %d]\n",
m, k, k, n, m, n);
int sizeA, sizeB, sizeC;
sizeA = m * k; sizeB = n * k; sizeC = m * n;
// initialize matrix A and B
float* A = NULL, * B = NULL;
A = new float[sizeA];
B = new float[sizeB];
memset(A, 0, sizeof(float) * sizeA);
memset(B, 0, sizeof(float) * sizeB);
// initialize matrix cpuC and gpuC
float* cpuC = NULL, * gpuC = NULL;
cpuC = new float[sizeC];
gpuC = new float[sizeC];
memset(cpuC, 0, sizeof(float) * sizeC);
memset(gpuC, 0, sizeof(float) * sizeC);
// input values matrix A and B
generateValues(&A, sizeA);
generateValues(&B, sizeB);
printf("CPU val: %f %f\n", A[0], B[0]);
// CPU running
for (int row = 0; row < m; row++) {
for (int col = 0; col < n; col++) {
int index = ID2INDX(row, col, n);
for (int i = 0; i < k; i++) {
cpuC[index] += A[ID2INDX(row, i, k)] * B[ID2INDX(i, col, n)];
}
}
}
printf("CPU result %f\n", cpuC[0]);
printf("CPU is finished\n");
// GPU
printf("GPU start\n");
float* dA, * dB, * dC;
cudaMalloc(&dA, sizeA * sizeof(float));
cudaMalloc(&dB, sizeB * sizeof(float));
cudaMalloc(&dC, sizeC * sizeof(float));
cudaMemset(&dA, 0, sizeA * sizeof(float));
cudaMemset(&dB, 0, sizeB * sizeof(float));
cudaMemset(&dC, 0, sizeC * sizeof(float));
cudaMemcpy(dA, A, sizeA * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(dB, B, sizeB * sizeof(float), cudaMemcpyHostToDevice);
printf("finished copy data from host to device\n");
dim3 gridDim(ceil((float)m / BLOCK_SIZE), ceil((float)n / BLOCK_SIZE));
dim3 blockDim(BLOCK_SIZE, BLOCK_SIZE);
printf("Grid(%d, %d), Block(%d, %d)\n", gridDim.x, gridDim.y, blockDim.x, blockDim.y);
MatMul << <gridDim, blockDim >> > (dA, dB, dC, m, n, k);
cudaDeviceSynchronize();
cudaMemcpy(gpuC, dC, sizeC * sizeof(float), cudaMemcpyDeviceToHost);
printf("GPU result %f\n", gpuC[0]);
compareMatrix(cpuC, gpuC, sizeC);
// 1. GPU global memory
return 0;
}
*/ | .text
.file "MatMul.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004fd9d_00000000-6_MatMul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "MatMul.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C" {
/*
* Kernel for mirroring the image parallely usng CUDA
*/
__global__
void mirror(const uchar4* const inputChannel, uchar4* outputChannel, int numRows, int numCols, bool vertical)
{
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if ( col >= numCols || row >= numRows )
{
return;
}
if(!vertical)
{
int thread_x = blockDim.x * blockIdx.x + threadIdx.x;
int thread_y = blockDim.y * blockIdx.y + threadIdx.y;
int thread_x_new = thread_x;
int thread_y_new = numRows-thread_y;
long myId = thread_y * numCols + thread_x;
long myId_new = thread_y_new * numCols + thread_x_new;
outputChannel[myId_new] = inputChannel[myId];
}
else
{
unsigned int thread_x = blockDim.x * blockIdx.x + threadIdx.x;
unsigned int thread_y = blockDim.y * blockIdx.y + threadIdx.y;
unsigned int thread_x_new = numCols-thread_x;
unsigned int thread_y_new = thread_y;
unsigned long int myId = thread_y * numCols + thread_x;
unsigned long int myId_new = thread_y_new * numCols + thread_x_new;
//printf("Id : %lu\t NewId : %lu\n", myId, myId_new);
outputChannel[myId_new] = inputChannel[myId]; // linear data store in global memory
}
}
} | code for sm_80
Function : mirror
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x170], P0 ; /* 0x00005c0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ULDC.S8 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000200 */
/*00b0*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf05270 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd80000000a00 */
/*00d0*/ @!P0 BRA 0x170 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*00e0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*00f0*/ IMAD R4, R3, c[0x0][0x174], R0 ; /* 0x00005d0003047a24 */
/* 0x000fd200078e0200 */
/*0100*/ IMAD.WIDE.U32 R4, R4, R2, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0002 */
/*0110*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IADD3 R0, -R0, c[0x0][0x174], RZ ; /* 0x00005d0000007a10 */
/* 0x000fca0007ffe1ff */
/*0130*/ IMAD R3, R3, c[0x0][0x174], R0 ; /* 0x00005d0003037a24 */
/* 0x000fc800078e0200 */
/*0140*/ IMAD.WIDE.U32 R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fca00078e0002 */
/*0150*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0180*/ IMAD R4, R3, c[0x0][0x174], R0 ; /* 0x00005d0003047a24 */
/* 0x000fc800078e0200 */
/*0190*/ IMAD.WIDE R4, R4, R2, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0202 */
/*01a0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*01b0*/ IADD3 R3, -R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fca0007ffe1ff */
/*01c0*/ IMAD R3, R3, c[0x0][0x174], R0 ; /* 0x00005d0003037a24 */
/* 0x000fc800078e0200 */
/*01d0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fca00078e0202 */
/*01e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C" {
/*
* Kernel for mirroring the image parallely usng CUDA
*/
__global__
void mirror(const uchar4* const inputChannel, uchar4* outputChannel, int numRows, int numCols, bool vertical)
{
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if ( col >= numCols || row >= numRows )
{
return;
}
if(!vertical)
{
int thread_x = blockDim.x * blockIdx.x + threadIdx.x;
int thread_y = blockDim.y * blockIdx.y + threadIdx.y;
int thread_x_new = thread_x;
int thread_y_new = numRows-thread_y;
long myId = thread_y * numCols + thread_x;
long myId_new = thread_y_new * numCols + thread_x_new;
outputChannel[myId_new] = inputChannel[myId];
}
else
{
unsigned int thread_x = blockDim.x * blockIdx.x + threadIdx.x;
unsigned int thread_y = blockDim.y * blockIdx.y + threadIdx.y;
unsigned int thread_x_new = numCols-thread_x;
unsigned int thread_y_new = thread_y;
unsigned long int myId = thread_y * numCols + thread_x;
unsigned long int myId_new = thread_y_new * numCols + thread_x_new;
//printf("Id : %lu\t NewId : %lu\n", myId, myId_new);
outputChannel[myId_new] = inputChannel[myId]; // linear data store in global memory
}
}
} | .file "tmpxft_000aa141_00000000-6_38-mirror_ops.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z6mirrorPK6uchar4PS_iibPK6uchar4PS_iib
.type _Z38__device_stub__Z6mirrorPK6uchar4PS_iibPK6uchar4PS_iib, @function
_Z38__device_stub__Z6mirrorPK6uchar4PS_iibPK6uchar4PS_iib:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movb %r8b, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq mirror(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z6mirrorPK6uchar4PS_iibPK6uchar4PS_iib, .-_Z38__device_stub__Z6mirrorPK6uchar4PS_iibPK6uchar4PS_iib
.globl mirror
.type mirror, @function
mirror:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl %r8b, %r8d
call _Z38__device_stub__Z6mirrorPK6uchar4PS_iibPK6uchar4PS_iib
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size mirror, .-mirror
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "mirror"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq mirror(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C" {
/*
* Kernel for mirroring the image parallely usng CUDA
*/
__global__
void mirror(const uchar4* const inputChannel, uchar4* outputChannel, int numRows, int numCols, bool vertical)
{
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if ( col >= numCols || row >= numRows )
{
return;
}
if(!vertical)
{
int thread_x = blockDim.x * blockIdx.x + threadIdx.x;
int thread_y = blockDim.y * blockIdx.y + threadIdx.y;
int thread_x_new = thread_x;
int thread_y_new = numRows-thread_y;
long myId = thread_y * numCols + thread_x;
long myId_new = thread_y_new * numCols + thread_x_new;
outputChannel[myId_new] = inputChannel[myId];
}
else
{
unsigned int thread_x = blockDim.x * blockIdx.x + threadIdx.x;
unsigned int thread_y = blockDim.y * blockIdx.y + threadIdx.y;
unsigned int thread_x_new = numCols-thread_x;
unsigned int thread_y_new = thread_y;
unsigned long int myId = thread_y * numCols + thread_x;
unsigned long int myId_new = thread_y_new * numCols + thread_x_new;
//printf("Id : %lu\t NewId : %lu\n", myId, myId_new);
outputChannel[myId_new] = inputChannel[myId]; // linear data store in global memory
}
}
} | #include <hip/hip_runtime.h>
extern "C" {
/*
* Kernel for mirroring the image parallely usng CUDA
*/
__global__
void mirror(const uchar4* const inputChannel, uchar4* outputChannel, int numRows, int numCols, bool vertical)
{
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if ( col >= numCols || row >= numRows )
{
return;
}
if(!vertical)
{
int thread_x = blockDim.x * blockIdx.x + threadIdx.x;
int thread_y = blockDim.y * blockIdx.y + threadIdx.y;
int thread_x_new = thread_x;
int thread_y_new = numRows-thread_y;
long myId = thread_y * numCols + thread_x;
long myId_new = thread_y_new * numCols + thread_x_new;
outputChannel[myId_new] = inputChannel[myId];
}
else
{
unsigned int thread_x = blockDim.x * blockIdx.x + threadIdx.x;
unsigned int thread_y = blockDim.y * blockIdx.y + threadIdx.y;
unsigned int thread_x_new = numCols-thread_x;
unsigned int thread_y_new = thread_y;
unsigned long int myId = thread_y * numCols + thread_x;
unsigned long int myId_new = thread_y_new * numCols + thread_x_new;
//printf("Id : %lu\t NewId : %lu\n", myId, myId_new);
outputChannel[myId_new] = inputChannel[myId]; // linear data store in global memory
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C" {
/*
* Kernel for mirroring the image parallely usng CUDA
*/
__global__
void mirror(const uchar4* const inputChannel, uchar4* outputChannel, int numRows, int numCols, bool vertical)
{
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if ( col >= numCols || row >= numRows )
{
return;
}
if(!vertical)
{
int thread_x = blockDim.x * blockIdx.x + threadIdx.x;
int thread_y = blockDim.y * blockIdx.y + threadIdx.y;
int thread_x_new = thread_x;
int thread_y_new = numRows-thread_y;
long myId = thread_y * numCols + thread_x;
long myId_new = thread_y_new * numCols + thread_x_new;
outputChannel[myId_new] = inputChannel[myId];
}
else
{
unsigned int thread_x = blockDim.x * blockIdx.x + threadIdx.x;
unsigned int thread_y = blockDim.y * blockIdx.y + threadIdx.y;
unsigned int thread_x_new = numCols-thread_x;
unsigned int thread_y_new = thread_y;
unsigned long int myId = thread_y * numCols + thread_x;
unsigned long int myId_new = thread_y_new * numCols + thread_x_new;
//printf("Id : %lu\t NewId : %lu\n", myId, myId_new);
outputChannel[myId_new] = inputChannel[myId]; // linear data store in global memory
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected mirror
.globl mirror
.p2align 8
.type mirror,@function
mirror:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x14
v_and_b32_e32 v3, 0x3ff, v0
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s5, v[3:4]
s_mov_b32 s5, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_7
s_load_b32 s3, s[2:3], 0xc
s_load_b32 s2, s[0:1], 0x10
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s15, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
s_load_b32 s3, s[0:1], 0x18
v_mul_lo_u32 v0, v3, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v2, v0, v1
s_waitcnt lgkmcnt(0)
s_bitcmp1_b32 s3, 0
s_cselect_b32 s3, -1, 0
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB0_4
v_sub_nc_u32_e32 v3, s2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[4:5], null, v3, s4, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_cbranch_execz .LBB0_5
s_branch .LBB0_6
.LBB0_4:
.LBB0_5:
v_sub_nc_u32_e32 v1, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v4, v1, v0
v_mov_b32_e32 v5, v3
.LBB0_6:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
v_lshlrev_b64 v[0:1], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel mirror
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size mirror, .Lfunc_end0-mirror
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 1
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: mirror
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: mirror.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C" {
/*
* Kernel for mirroring the image parallely usng CUDA
*/
__global__
void mirror(const uchar4* const inputChannel, uchar4* outputChannel, int numRows, int numCols, bool vertical)
{
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if ( col >= numCols || row >= numRows )
{
return;
}
if(!vertical)
{
int thread_x = blockDim.x * blockIdx.x + threadIdx.x;
int thread_y = blockDim.y * blockIdx.y + threadIdx.y;
int thread_x_new = thread_x;
int thread_y_new = numRows-thread_y;
long myId = thread_y * numCols + thread_x;
long myId_new = thread_y_new * numCols + thread_x_new;
outputChannel[myId_new] = inputChannel[myId];
}
else
{
unsigned int thread_x = blockDim.x * blockIdx.x + threadIdx.x;
unsigned int thread_y = blockDim.y * blockIdx.y + threadIdx.y;
unsigned int thread_x_new = numCols-thread_x;
unsigned int thread_y_new = thread_y;
unsigned long int myId = thread_y * numCols + thread_x;
unsigned long int myId_new = thread_y_new * numCols + thread_x_new;
//printf("Id : %lu\t NewId : %lu\n", myId, myId_new);
outputChannel[myId_new] = inputChannel[myId]; // linear data store in global memory
}
}
} | .text
.file "38-mirror_ops.hip"
.globl __device_stub__mirror # -- Begin function __device_stub__mirror
.p2align 4, 0x90
.type __device_stub__mirror,@function
__device_stub__mirror: # @__device_stub__mirror
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movb %r8b, 7(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 7(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $mirror, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__mirror, .Lfunc_end0-__device_stub__mirror
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $mirror, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type mirror,@object # @mirror
.section .rodata,"a",@progbits
.globl mirror
.p2align 3, 0x0
mirror:
.quad __device_stub__mirror
.size mirror, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "mirror"
.size .L__unnamed_1, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__mirror
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym mirror
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : mirror
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x170], P0 ; /* 0x00005c0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ULDC.S8 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000200 */
/*00b0*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf05270 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd80000000a00 */
/*00d0*/ @!P0 BRA 0x170 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*00e0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*00f0*/ IMAD R4, R3, c[0x0][0x174], R0 ; /* 0x00005d0003047a24 */
/* 0x000fd200078e0200 */
/*0100*/ IMAD.WIDE.U32 R4, R4, R2, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0002 */
/*0110*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IADD3 R0, -R0, c[0x0][0x174], RZ ; /* 0x00005d0000007a10 */
/* 0x000fca0007ffe1ff */
/*0130*/ IMAD R3, R3, c[0x0][0x174], R0 ; /* 0x00005d0003037a24 */
/* 0x000fc800078e0200 */
/*0140*/ IMAD.WIDE.U32 R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fca00078e0002 */
/*0150*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0180*/ IMAD R4, R3, c[0x0][0x174], R0 ; /* 0x00005d0003047a24 */
/* 0x000fc800078e0200 */
/*0190*/ IMAD.WIDE R4, R4, R2, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0202 */
/*01a0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*01b0*/ IADD3 R3, -R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fca0007ffe1ff */
/*01c0*/ IMAD R3, R3, c[0x0][0x174], R0 ; /* 0x00005d0003037a24 */
/* 0x000fc800078e0200 */
/*01d0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fca00078e0202 */
/*01e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected mirror
.globl mirror
.p2align 8
.type mirror,@function
mirror:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x14
v_and_b32_e32 v3, 0x3ff, v0
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s5, v[3:4]
s_mov_b32 s5, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_7
s_load_b32 s3, s[2:3], 0xc
s_load_b32 s2, s[0:1], 0x10
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s15, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
s_load_b32 s3, s[0:1], 0x18
v_mul_lo_u32 v0, v3, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v2, v0, v1
s_waitcnt lgkmcnt(0)
s_bitcmp1_b32 s3, 0
s_cselect_b32 s3, -1, 0
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB0_4
v_sub_nc_u32_e32 v3, s2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[4:5], null, v3, s4, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_cbranch_execz .LBB0_5
s_branch .LBB0_6
.LBB0_4:
.LBB0_5:
v_sub_nc_u32_e32 v1, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v4, v1, v0
v_mov_b32_e32 v5, v3
.LBB0_6:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
v_lshlrev_b64 v[0:1], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel mirror
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size mirror, .Lfunc_end0-mirror
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 1
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: mirror
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: mirror.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000aa141_00000000-6_38-mirror_ops.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z6mirrorPK6uchar4PS_iibPK6uchar4PS_iib
.type _Z38__device_stub__Z6mirrorPK6uchar4PS_iibPK6uchar4PS_iib, @function
_Z38__device_stub__Z6mirrorPK6uchar4PS_iibPK6uchar4PS_iib:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movb %r8b, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq mirror(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z6mirrorPK6uchar4PS_iibPK6uchar4PS_iib, .-_Z38__device_stub__Z6mirrorPK6uchar4PS_iibPK6uchar4PS_iib
.globl mirror
.type mirror, @function
mirror:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl %r8b, %r8d
call _Z38__device_stub__Z6mirrorPK6uchar4PS_iibPK6uchar4PS_iib
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size mirror, .-mirror
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "mirror"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq mirror(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "38-mirror_ops.hip"
.globl __device_stub__mirror # -- Begin function __device_stub__mirror
.p2align 4, 0x90
.type __device_stub__mirror,@function
__device_stub__mirror: # @__device_stub__mirror
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movb %r8b, 7(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 7(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $mirror, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__mirror, .Lfunc_end0-__device_stub__mirror
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $mirror, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type mirror,@object # @mirror
.section .rodata,"a",@progbits
.globl mirror
.p2align 3, 0x0
mirror:
.quad __device_stub__mirror
.size mirror, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "mirror"
.size .L__unnamed_1, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__mirror
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym mirror
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //
// Sample Program to test cmake build system
// settings for CUDA
//
// Author : Siddhant Wadhwa
// Creation Date : Thursday, April 21st, 2016
// Modification history : <none>
//
#include <iostream>
#include <stdio.h>
#define N 10
__global__ void add( int *a, int *b, int *c ) {
int tid = blockIdx.x; // handle the data at this index
if (tid < N)
c[tid] = a[tid] + b[tid];
}
int main (void) {
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
// allocate the memory on the GPU
cudaMalloc( (void**)&dev_a, N * sizeof(int) );
cudaMalloc( (void**)&dev_b, N * sizeof(int) );
cudaMalloc( (void**)&dev_c, N * sizeof(int) );
// fill the arrays 'a' and 'b' on the CPU
for (int i=0; i<N; i++) {
a[i] = -i;
b[i] = i * i;
}
// copy the arrays 'a' and 'b' to the GPU
cudaMemcpy( dev_a, a, N * sizeof(int), cudaMemcpyHostToDevice );
cudaMemcpy( dev_b, b, N * sizeof(int), cudaMemcpyHostToDevice );
// Execute cuda kernel
add<<<N,1>>>( dev_a, dev_b, dev_c );
// copy the array 'c' back from the GPU to the CPU
cudaMemcpy( c, dev_c, N * sizeof(int), cudaMemcpyDeviceToHost );
// display the results
for (int i=0; i<N; i++) {
printf( "%d + %d = %d\n", a[i], b[i], c[i] );
}
// free the memory allocated on the GPU
cudaFree( dev_a );
cudaFree( dev_b );
cudaFree( dev_c );
return 0;
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0x9, PT ; /* 0x000000090600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //
// Sample Program to test cmake build system
// settings for CUDA
//
// Author : Siddhant Wadhwa
// Creation Date : Thursday, April 21st, 2016
// Modification history : <none>
//
#include <iostream>
#include <stdio.h>
#define N 10
__global__ void add( int *a, int *b, int *c ) {
int tid = blockIdx.x; // handle the data at this index
if (tid < N)
c[tid] = a[tid] + b[tid];
}
int main (void) {
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
// allocate the memory on the GPU
cudaMalloc( (void**)&dev_a, N * sizeof(int) );
cudaMalloc( (void**)&dev_b, N * sizeof(int) );
cudaMalloc( (void**)&dev_c, N * sizeof(int) );
// fill the arrays 'a' and 'b' on the CPU
for (int i=0; i<N; i++) {
a[i] = -i;
b[i] = i * i;
}
// copy the arrays 'a' and 'b' to the GPU
cudaMemcpy( dev_a, a, N * sizeof(int), cudaMemcpyHostToDevice );
cudaMemcpy( dev_b, b, N * sizeof(int), cudaMemcpyHostToDevice );
// Execute cuda kernel
add<<<N,1>>>( dev_a, dev_b, dev_c );
// copy the array 'c' back from the GPU to the CPU
cudaMemcpy( c, dev_c, N * sizeof(int), cudaMemcpyDeviceToHost );
// display the results
for (int i=0; i<N; i++) {
printf( "%d + %d = %d\n", a[i], b[i], c[i] );
}
// free the memory allocated on the GPU
cudaFree( dev_a );
cudaFree( dev_b );
cudaFree( dev_c );
return 0;
} | .file "tmpxft_00006891_00000000-6_sample_cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d + %d = %d\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $200, %rsp
.cfi_def_cfa_offset 224
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
movl %eax, %edx
negl %edx
movl %edx, 48(%rsp,%rax,4)
movl %eax, %edx
imull %eax, %edx
movl %edx, 96(%rsp,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L12
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 96(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $10, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 144(%rsp), %rdi
movl $2, %ecx
movl $40, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L14:
movl 96(%rsp,%rbx), %ecx
movl 48(%rsp,%rbx), %edx
movl 144(%rsp,%rbx), %r8d
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $40, %rbx
jne .L14
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //
// Sample Program to test cmake build system
// settings for CUDA
//
// Author : Siddhant Wadhwa
// Creation Date : Thursday, April 21st, 2016
// Modification history : <none>
//
#include <iostream>
#include <stdio.h>
#define N 10
__global__ void add( int *a, int *b, int *c ) {
int tid = blockIdx.x; // handle the data at this index
if (tid < N)
c[tid] = a[tid] + b[tid];
}
int main (void) {
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
// allocate the memory on the GPU
cudaMalloc( (void**)&dev_a, N * sizeof(int) );
cudaMalloc( (void**)&dev_b, N * sizeof(int) );
cudaMalloc( (void**)&dev_c, N * sizeof(int) );
// fill the arrays 'a' and 'b' on the CPU
for (int i=0; i<N; i++) {
a[i] = -i;
b[i] = i * i;
}
// copy the arrays 'a' and 'b' to the GPU
cudaMemcpy( dev_a, a, N * sizeof(int), cudaMemcpyHostToDevice );
cudaMemcpy( dev_b, b, N * sizeof(int), cudaMemcpyHostToDevice );
// Execute cuda kernel
add<<<N,1>>>( dev_a, dev_b, dev_c );
// copy the array 'c' back from the GPU to the CPU
cudaMemcpy( c, dev_c, N * sizeof(int), cudaMemcpyDeviceToHost );
// display the results
for (int i=0; i<N; i++) {
printf( "%d + %d = %d\n", a[i], b[i], c[i] );
}
// free the memory allocated on the GPU
cudaFree( dev_a );
cudaFree( dev_b );
cudaFree( dev_c );
return 0;
} | //
// Sample Program to test cmake build system
// settings for CUDA
//
// Author : Siddhant Wadhwa
// Creation Date : Thursday, April 21st, 2016
// Modification history : <none>
//
#include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#define N 10
__global__ void add( int *a, int *b, int *c ) {
int tid = blockIdx.x; // handle the data at this index
if (tid < N)
c[tid] = a[tid] + b[tid];
}
int main (void) {
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
// allocate the memory on the GPU
hipMalloc( (void**)&dev_a, N * sizeof(int) );
hipMalloc( (void**)&dev_b, N * sizeof(int) );
hipMalloc( (void**)&dev_c, N * sizeof(int) );
// fill the arrays 'a' and 'b' on the CPU
for (int i=0; i<N; i++) {
a[i] = -i;
b[i] = i * i;
}
// copy the arrays 'a' and 'b' to the GPU
hipMemcpy( dev_a, a, N * sizeof(int), hipMemcpyHostToDevice );
hipMemcpy( dev_b, b, N * sizeof(int), hipMemcpyHostToDevice );
// Execute cuda kernel
add<<<N,1>>>( dev_a, dev_b, dev_c );
// copy the array 'c' back from the GPU to the CPU
hipMemcpy( c, dev_c, N * sizeof(int), hipMemcpyDeviceToHost );
// display the results
for (int i=0; i<N; i++) {
printf( "%d + %d = %d\n", a[i], b[i], c[i] );
}
// free the memory allocated on the GPU
hipFree( dev_a );
hipFree( dev_b );
hipFree( dev_c );
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //
// Sample Program to test cmake build system
// settings for CUDA
//
// Author : Siddhant Wadhwa
// Creation Date : Thursday, April 21st, 2016
// Modification history : <none>
//
#include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#define N 10
__global__ void add( int *a, int *b, int *c ) {
int tid = blockIdx.x; // handle the data at this index
if (tid < N)
c[tid] = a[tid] + b[tid];
}
int main (void) {
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
// allocate the memory on the GPU
hipMalloc( (void**)&dev_a, N * sizeof(int) );
hipMalloc( (void**)&dev_b, N * sizeof(int) );
hipMalloc( (void**)&dev_c, N * sizeof(int) );
// fill the arrays 'a' and 'b' on the CPU
for (int i=0; i<N; i++) {
a[i] = -i;
b[i] = i * i;
}
// copy the arrays 'a' and 'b' to the GPU
hipMemcpy( dev_a, a, N * sizeof(int), hipMemcpyHostToDevice );
hipMemcpy( dev_b, b, N * sizeof(int), hipMemcpyHostToDevice );
// Execute cuda kernel
add<<<N,1>>>( dev_a, dev_b, dev_c );
// copy the array 'c' back from the GPU to the CPU
hipMemcpy( c, dev_c, N * sizeof(int), hipMemcpyDeviceToHost );
// display the results
for (int i=0; i<N; i++) {
printf( "%d + %d = %d\n", a[i], b[i], c[i] );
}
// free the memory allocated on the GPU
hipFree( dev_a );
hipFree( dev_b );
hipFree( dev_c );
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_cmp_gt_i32 s15, 9
s_cbranch_scc1 .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //
// Sample Program to test cmake build system
// settings for CUDA
//
// Author : Siddhant Wadhwa
// Creation Date : Thursday, April 21st, 2016
// Modification history : <none>
//
#include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#define N 10
__global__ void add( int *a, int *b, int *c ) {
int tid = blockIdx.x; // handle the data at this index
if (tid < N)
c[tid] = a[tid] + b[tid];
}
int main (void) {
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
// allocate the memory on the GPU
hipMalloc( (void**)&dev_a, N * sizeof(int) );
hipMalloc( (void**)&dev_b, N * sizeof(int) );
hipMalloc( (void**)&dev_c, N * sizeof(int) );
// fill the arrays 'a' and 'b' on the CPU
for (int i=0; i<N; i++) {
a[i] = -i;
b[i] = i * i;
}
// copy the arrays 'a' and 'b' to the GPU
hipMemcpy( dev_a, a, N * sizeof(int), hipMemcpyHostToDevice );
hipMemcpy( dev_b, b, N * sizeof(int), hipMemcpyHostToDevice );
// Execute cuda kernel
add<<<N,1>>>( dev_a, dev_b, dev_c );
// copy the array 'c' back from the GPU to the CPU
hipMemcpy( c, dev_c, N * sizeof(int), hipMemcpyDeviceToHost );
// display the results
for (int i=0; i<N; i++) {
printf( "%d + %d = %d\n", a[i], b[i], c[i] );
}
// free the memory allocated on the GPU
hipFree( dev_a );
hipFree( dev_b );
hipFree( dev_c );
return 0;
} | .text
.file "sample_cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $240, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -16
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq %rsp, %rdi
movl $40, %esi
callq hipMalloc
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, 192(%rsp,%rcx,4)
movl %ecx, %edx
imull %ecx, %edx
movl %edx, 144(%rsp,%rcx,4)
incq %rcx
decl %eax
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
movq 16(%rsp), %rdi
leaq 192(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 144(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 9(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 192(%rsp,%rbx,4), %esi
movl 144(%rsp,%rbx,4), %edx
movl 96(%rsp,%rbx,4), %ecx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB1_5
# %bb.6:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $240, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d + %d = %d\n"
.size .L.str, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0x9, PT ; /* 0x000000090600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_cmp_gt_i32 s15, 9
s_cbranch_scc1 .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00006891_00000000-6_sample_cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d + %d = %d\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $200, %rsp
.cfi_def_cfa_offset 224
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
movl %eax, %edx
negl %edx
movl %edx, 48(%rsp,%rax,4)
movl %eax, %edx
imull %eax, %edx
movl %edx, 96(%rsp,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L12
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 96(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $10, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 144(%rsp), %rdi
movl $2, %ecx
movl $40, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L14:
movl 96(%rsp,%rbx), %ecx
movl 48(%rsp,%rbx), %edx
movl 144(%rsp,%rbx), %r8d
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $40, %rbx
jne .L14
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sample_cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $240, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -16
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq %rsp, %rdi
movl $40, %esi
callq hipMalloc
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, 192(%rsp,%rcx,4)
movl %ecx, %edx
imull %ecx, %edx
movl %edx, 144(%rsp,%rcx,4)
incq %rcx
decl %eax
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
movq 16(%rsp), %rdi
leaq 192(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 144(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 9(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 192(%rsp,%rbx,4), %esi
movl 144(%rsp,%rbx,4), %edx
movl 96(%rsp,%rbx,4), %ecx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB1_5
# %bb.6:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $240, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d + %d = %d\n"
.size .L.str, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void addtoall(int* a, int b)
{
int i = threadIdx.x;
atomicAdd(&(a[i]), b);
}
int main(void)
{
int N = 32;
int *A = new int[N];
int *d_A;
cudaMalloc((void**)&d_A, N*sizeof(int));
cudaMemcpy(d_A, A, N*sizeof(int), cudaMemcpyHostToDevice);
addtoall<<<1,N>>>(d_A, 7);
addtoall<<<1,N>>>(d_A, 3);
addtoall<<<1,N>>>(d_A, 3);
addtoall<<<1,N>>>(d_A, 3);
addtoall<<<1,N>>>(d_A, 3);
addtoall<<<1,N>>>(d_A, 3);
addtoall<<<1,N>>>(d_A, 3);
cudaMemcpy(A, d_A, N*sizeof(int), cudaMemcpyDeviceToHost);
for(int i =0; i<N; i++)
{
printf("%d ", A[i]);
}
} | code for sm_80
Function : _Z8addtoallPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R5, c[0x0][0x168] ; /* 0x00005a0000057a02 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0050*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fca00078e0203 */
/*0060*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x000fe2000c10e184 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void addtoall(int* a, int b)
{
int i = threadIdx.x;
atomicAdd(&(a[i]), b);
}
int main(void)
{
int N = 32;
int *A = new int[N];
int *d_A;
cudaMalloc((void**)&d_A, N*sizeof(int));
cudaMemcpy(d_A, A, N*sizeof(int), cudaMemcpyHostToDevice);
addtoall<<<1,N>>>(d_A, 7);
addtoall<<<1,N>>>(d_A, 3);
addtoall<<<1,N>>>(d_A, 3);
addtoall<<<1,N>>>(d_A, 3);
addtoall<<<1,N>>>(d_A, 3);
addtoall<<<1,N>>>(d_A, 3);
addtoall<<<1,N>>>(d_A, 3);
cudaMemcpy(A, d_A, N*sizeof(int), cudaMemcpyDeviceToHost);
for(int i =0; i<N; i++)
{
printf("%d ", A[i]);
}
} | .file "tmpxft_0002283b_00000000-6_atomic_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z8addtoallPiiPii
.type _Z28__device_stub__Z8addtoallPiiPii, @function
_Z28__device_stub__Z8addtoallPiiPii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8addtoallPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z8addtoallPiiPii, .-_Z28__device_stub__Z8addtoallPiiPii
.globl _Z8addtoallPii
.type _Z8addtoallPii, @function
_Z8addtoallPii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z8addtoallPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8addtoallPii, .-_Z8addtoallPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $128, %edi
call _Znam@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $128, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L12:
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L13:
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L14:
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L15:
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L16:
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L17:
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L18:
movl $2, %ecx
movl $128, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq %rbp, %rbx
subq $-128, %rbp
leaq .LC0(%rip), %r12
.L19:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L19
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl $7, %esi
movq 8(%rsp), %rdi
call _Z28__device_stub__Z8addtoallPiiPii
jmp .L12
.L24:
movl $3, %esi
movq 8(%rsp), %rdi
call _Z28__device_stub__Z8addtoallPiiPii
jmp .L13
.L25:
movl $3, %esi
movq 8(%rsp), %rdi
call _Z28__device_stub__Z8addtoallPiiPii
jmp .L14
.L26:
movl $3, %esi
movq 8(%rsp), %rdi
call _Z28__device_stub__Z8addtoallPiiPii
jmp .L15
.L27:
movl $3, %esi
movq 8(%rsp), %rdi
call _Z28__device_stub__Z8addtoallPiiPii
jmp .L16
.L28:
movl $3, %esi
movq 8(%rsp), %rdi
call _Z28__device_stub__Z8addtoallPiiPii
jmp .L17
.L29:
movl $3, %esi
movq 8(%rsp), %rdi
call _Z28__device_stub__Z8addtoallPiiPii
jmp .L18
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z8addtoallPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8addtoallPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void addtoall(int* a, int b)
{
int i = threadIdx.x;
atomicAdd(&(a[i]), b);
}
int main(void)
{
int N = 32;
int *A = new int[N];
int *d_A;
cudaMalloc((void**)&d_A, N*sizeof(int));
cudaMemcpy(d_A, A, N*sizeof(int), cudaMemcpyHostToDevice);
addtoall<<<1,N>>>(d_A, 7);
addtoall<<<1,N>>>(d_A, 3);
addtoall<<<1,N>>>(d_A, 3);
addtoall<<<1,N>>>(d_A, 3);
addtoall<<<1,N>>>(d_A, 3);
addtoall<<<1,N>>>(d_A, 3);
addtoall<<<1,N>>>(d_A, 3);
cudaMemcpy(A, d_A, N*sizeof(int), cudaMemcpyDeviceToHost);
for(int i =0; i<N; i++)
{
printf("%d ", A[i]);
}
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void addtoall(int* a, int b)
{
int i = threadIdx.x;
atomicAdd(&(a[i]), b);
}
int main(void)
{
int N = 32;
int *A = new int[N];
int *d_A;
hipMalloc((void**)&d_A, N*sizeof(int));
hipMemcpy(d_A, A, N*sizeof(int), hipMemcpyHostToDevice);
addtoall<<<1,N>>>(d_A, 7);
addtoall<<<1,N>>>(d_A, 3);
addtoall<<<1,N>>>(d_A, 3);
addtoall<<<1,N>>>(d_A, 3);
addtoall<<<1,N>>>(d_A, 3);
addtoall<<<1,N>>>(d_A, 3);
addtoall<<<1,N>>>(d_A, 3);
hipMemcpy(A, d_A, N*sizeof(int), hipMemcpyDeviceToHost);
for(int i =0; i<N; i++)
{
printf("%d ", A[i]);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void addtoall(int* a, int b)
{
int i = threadIdx.x;
atomicAdd(&(a[i]), b);
}
int main(void)
{
int N = 32;
int *A = new int[N];
int *d_A;
hipMalloc((void**)&d_A, N*sizeof(int));
hipMemcpy(d_A, A, N*sizeof(int), hipMemcpyHostToDevice);
addtoall<<<1,N>>>(d_A, 7);
addtoall<<<1,N>>>(d_A, 3);
addtoall<<<1,N>>>(d_A, 3);
addtoall<<<1,N>>>(d_A, 3);
addtoall<<<1,N>>>(d_A, 3);
addtoall<<<1,N>>>(d_A, 3);
addtoall<<<1,N>>>(d_A, 3);
hipMemcpy(A, d_A, N*sizeof(int), hipMemcpyDeviceToHost);
for(int i =0; i<N; i++)
{
printf("%d ", A[i]);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8addtoallPii
.globl _Z8addtoallPii
.p2align 8
.type _Z8addtoallPii,@function
_Z8addtoallPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v1, s2 :: v_dual_lshlrev_b32 v0, 2, v0
global_atomic_add_u32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8addtoallPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 3
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8addtoallPii, .Lfunc_end0-_Z8addtoallPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8addtoallPii
.private_segment_fixed_size: 0
.sgpr_count: 3
.sgpr_spill_count: 0
.symbol: _Z8addtoallPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void addtoall(int* a, int b)
{
int i = threadIdx.x;
atomicAdd(&(a[i]), b);
}
int main(void)
{
int N = 32;
int *A = new int[N];
int *d_A;
hipMalloc((void**)&d_A, N*sizeof(int));
hipMemcpy(d_A, A, N*sizeof(int), hipMemcpyHostToDevice);
addtoall<<<1,N>>>(d_A, 7);
addtoall<<<1,N>>>(d_A, 3);
addtoall<<<1,N>>>(d_A, 3);
addtoall<<<1,N>>>(d_A, 3);
addtoall<<<1,N>>>(d_A, 3);
addtoall<<<1,N>>>(d_A, 3);
addtoall<<<1,N>>>(d_A, 3);
hipMemcpy(A, d_A, N*sizeof(int), hipMemcpyDeviceToHost);
for(int i =0; i<N; i++)
{
printf("%d ", A[i]);
}
} | .text
.file "atomic_test.hip"
.globl _Z23__device_stub__addtoallPii # -- Begin function _Z23__device_stub__addtoallPii
.p2align 4, 0x90
.type _Z23__device_stub__addtoallPii,@function
_Z23__device_stub__addtoallPii: # @_Z23__device_stub__addtoallPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8addtoallPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__addtoallPii, .Lfunc_end0-_Z23__device_stub__addtoallPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movabsq $4294967297, %r14 # imm = 0x100000001
movl $128, %edi
callq _Znam
movq %rax, %rbx
leaq 88(%rsp), %rdi
movl $128, %esi
callq hipMalloc
movq 88(%rsp), %rdi
movl $128, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 31(%r14), %r15
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 88(%rsp), %rax
movq %rax, 56(%rsp)
movl $7, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8addtoallPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 88(%rsp), %rax
movq %rax, 56(%rsp)
movl $3, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8addtoallPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 88(%rsp), %rax
movq %rax, 56(%rsp)
movl $3, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8addtoallPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 88(%rsp), %rax
movq %rax, 56(%rsp)
movl $3, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8addtoallPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9:
movq 88(%rsp), %rax
movq %rax, 56(%rsp)
movl $3, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8addtoallPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_10:
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_12
# %bb.11:
movq 88(%rsp), %rax
movq %rax, 56(%rsp)
movl $3, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8addtoallPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_12:
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_14
# %bb.13:
movq 88(%rsp), %rax
movq %rax, 56(%rsp)
movl $3, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8addtoallPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_14:
movq 88(%rsp), %rsi
movl $128, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_15: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $32, %r14
jne .LBB1_15
# %bb.16:
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8addtoallPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8addtoallPii,@object # @_Z8addtoallPii
.section .rodata,"a",@progbits
.globl _Z8addtoallPii
.p2align 3, 0x0
_Z8addtoallPii:
.quad _Z23__device_stub__addtoallPii
.size _Z8addtoallPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8addtoallPii"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__addtoallPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8addtoallPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8addtoallPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R5, c[0x0][0x168] ; /* 0x00005a0000057a02 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0050*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fca00078e0203 */
/*0060*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x000fe2000c10e184 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8addtoallPii
.globl _Z8addtoallPii
.p2align 8
.type _Z8addtoallPii,@function
_Z8addtoallPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v1, s2 :: v_dual_lshlrev_b32 v0, 2, v0
global_atomic_add_u32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8addtoallPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 3
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8addtoallPii, .Lfunc_end0-_Z8addtoallPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8addtoallPii
.private_segment_fixed_size: 0
.sgpr_count: 3
.sgpr_spill_count: 0
.symbol: _Z8addtoallPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002283b_00000000-6_atomic_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z8addtoallPiiPii
.type _Z28__device_stub__Z8addtoallPiiPii, @function
_Z28__device_stub__Z8addtoallPiiPii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8addtoallPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z8addtoallPiiPii, .-_Z28__device_stub__Z8addtoallPiiPii
.globl _Z8addtoallPii
.type _Z8addtoallPii, @function
_Z8addtoallPii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z8addtoallPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8addtoallPii, .-_Z8addtoallPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $128, %edi
call _Znam@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $128, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L12:
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L13:
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L14:
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L15:
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L16:
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L17:
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L18:
movl $2, %ecx
movl $128, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq %rbp, %rbx
subq $-128, %rbp
leaq .LC0(%rip), %r12
.L19:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L19
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl $7, %esi
movq 8(%rsp), %rdi
call _Z28__device_stub__Z8addtoallPiiPii
jmp .L12
.L24:
movl $3, %esi
movq 8(%rsp), %rdi
call _Z28__device_stub__Z8addtoallPiiPii
jmp .L13
.L25:
movl $3, %esi
movq 8(%rsp), %rdi
call _Z28__device_stub__Z8addtoallPiiPii
jmp .L14
.L26:
movl $3, %esi
movq 8(%rsp), %rdi
call _Z28__device_stub__Z8addtoallPiiPii
jmp .L15
.L27:
movl $3, %esi
movq 8(%rsp), %rdi
call _Z28__device_stub__Z8addtoallPiiPii
jmp .L16
.L28:
movl $3, %esi
movq 8(%rsp), %rdi
call _Z28__device_stub__Z8addtoallPiiPii
jmp .L17
.L29:
movl $3, %esi
movq 8(%rsp), %rdi
call _Z28__device_stub__Z8addtoallPiiPii
jmp .L18
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z8addtoallPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8addtoallPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "atomic_test.hip"
.globl _Z23__device_stub__addtoallPii # -- Begin function _Z23__device_stub__addtoallPii
.p2align 4, 0x90
.type _Z23__device_stub__addtoallPii,@function
_Z23__device_stub__addtoallPii: # @_Z23__device_stub__addtoallPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8addtoallPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__addtoallPii, .Lfunc_end0-_Z23__device_stub__addtoallPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movabsq $4294967297, %r14 # imm = 0x100000001
movl $128, %edi
callq _Znam
movq %rax, %rbx
leaq 88(%rsp), %rdi
movl $128, %esi
callq hipMalloc
movq 88(%rsp), %rdi
movl $128, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 31(%r14), %r15
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 88(%rsp), %rax
movq %rax, 56(%rsp)
movl $7, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8addtoallPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 88(%rsp), %rax
movq %rax, 56(%rsp)
movl $3, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8addtoallPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 88(%rsp), %rax
movq %rax, 56(%rsp)
movl $3, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8addtoallPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 88(%rsp), %rax
movq %rax, 56(%rsp)
movl $3, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8addtoallPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9:
movq 88(%rsp), %rax
movq %rax, 56(%rsp)
movl $3, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8addtoallPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_10:
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_12
# %bb.11:
movq 88(%rsp), %rax
movq %rax, 56(%rsp)
movl $3, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8addtoallPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_12:
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_14
# %bb.13:
movq 88(%rsp), %rax
movq %rax, 56(%rsp)
movl $3, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8addtoallPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_14:
movq 88(%rsp), %rsi
movl $128, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_15: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $32, %r14
jne .LBB1_15
# %bb.16:
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8addtoallPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8addtoallPii,@object # @_Z8addtoallPii
.section .rodata,"a",@progbits
.globl _Z8addtoallPii
.p2align 3, 0x0
_Z8addtoallPii:
.quad _Z23__device_stub__addtoallPii
.size _Z8addtoallPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8addtoallPii"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__addtoallPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8addtoallPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <iostream>
#include <map>
#include <string>
#include <fstream>
#include <vector>
using namespace std;
#define ll long long
const int GRID_SIZE = 1;
// Use naive method
__device__ bool isPrime(ll n)
{
if(n<2)
return false;
for(ll i=2;i*i<=n;i++)
if(n%i==0)
return false;
return true;
}
// Read numbers from file and add to vector
std::vector<ll> readFile(char* arg){
vector<ll> numbersFromFile;
std::ifstream infile(arg);
ll number;
if(!infile.is_open()) {
throw std::invalid_argument("Problem with file");
}
while (infile >> number) {
numbersFromFile.push_back(number);
}
return numbersFromFile;
}
__global__ void calculate(ll *Arr, bool *results, int sizeOfArray, int amountOfBlocks){
int x = (blockIdx.x * blockDim.x) + threadIdx.x;
if (amountOfBlocks >= sizeOfArray){
results[x] += isPrime(Arr[x]);
} else{
int sizeOfPart = sizeOfArray / amountOfBlocks;
int restOfDivide = sizeOfArray%amountOfBlocks;
int startPart = sizeOfPart * x;
int endPart = sizeOfPart * (x + 1);
if (endPart <= sizeOfArray)
{
int restStart = sizeOfPart * amountOfBlocks;
for (int i = startPart; i < endPart; i++){
results[i] += isPrime(Arr[i]);
}
if (x < restOfDivide){
results[restStart + x] += isPrime(Arr[restStart + x]);
}
}
}
}
int main(int argc, char** argv )
{
float time;
if ( argc < 2 )
{
printf("Pass file path\n");
return -1;
}
vector<ll> numbersFromFile;
try {
numbersFromFile = readFile(argv[1]);
} catch ( const std::invalid_argument& ex ) {
cout << ex.what() << endl;
return -1;
}
int sizeOfArray = numbersFromFile.size();
int sizeToAllocateLongLong = sizeOfArray * sizeof(ll);
int sizeToAllocateBool = sizeOfArray * sizeof(bool);
ll numbersFromFileArr[sizeOfArray];
std::copy(numbersFromFile.begin(), numbersFromFile.end(), numbersFromFileArr);
bool* results = (bool *) malloc (sizeToAllocateBool);
ll* c_arr;
bool* c_results;
cudaMalloc((void**) &c_arr, sizeToAllocateLongLong);
cudaMalloc((void**) &c_results, sizeToAllocateBool);
cudaMemcpy((void *)c_arr, (void *)numbersFromFileArr, sizeToAllocateLongLong, cudaMemcpyHostToDevice);
//Start timer
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
int amountOfBlocks = sizeOfArray;
calculate<<<amountOfBlocks, GRID_SIZE>>>(c_arr, c_results, sizeOfArray, amountOfBlocks);
//End timer and put result into time variable
cudaDeviceSynchronize();
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
printf("Czas: %.4fms\n", time);
if (cudaMemcpy((void *)results, (void *)c_results , sizeToAllocateBool, cudaMemcpyDeviceToHost) != cudaSuccess) {
cout<<"GPU to CPU copy error\n";
}
cudaFree(c_arr);
cudaFree(c_results);
for(int j = 0; j < sizeOfArray ; j++)
{
if (results[j]){
cout << numbersFromFileArr[j] << " prime" << endl;
} else {
cout << numbersFromFileArr[j] << " composite" << endl;
}
}
free(results);
return 0;
} | .file "tmpxft_000f73f8_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4591:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4591:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7isPrimex
.type _Z7isPrimex, @function
_Z7isPrimex:
.LFB4567:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4567:
.size _Z7isPrimex, .-_Z7isPrimex
.globl _Z32__device_stub__Z9calculatePxPbiiPxPbii
.type _Z32__device_stub__Z9calculatePxPbiiPxPbii, @function
_Z32__device_stub__Z9calculatePxPbiiPxPbii:
.LFB4613:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9calculatePxPbii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4613:
.size _Z32__device_stub__Z9calculatePxPbiiPxPbii, .-_Z32__device_stub__Z9calculatePxPbiiPxPbii
.globl _Z9calculatePxPbii
.type _Z9calculatePxPbii, @function
_Z9calculatePxPbii:
.LFB4614:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9calculatePxPbiiPxPbii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4614:
.size _Z9calculatePxPbii, .-_Z9calculatePxPbii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9calculatePxPbii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4616:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9calculatePxPbii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4616:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIxSaIxEED2Ev,"axG",@progbits,_ZNSt6vectorIxSaIxEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIxSaIxEED2Ev
.type _ZNSt6vectorIxSaIxEED2Ev, @function
_ZNSt6vectorIxSaIxEED2Ev:
.LFB4942:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L18
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L18:
ret
.cfi_endproc
.LFE4942:
.size _ZNSt6vectorIxSaIxEED2Ev, .-_ZNSt6vectorIxSaIxEED2Ev
.weak _ZNSt6vectorIxSaIxEED1Ev
.set _ZNSt6vectorIxSaIxEED1Ev,_ZNSt6vectorIxSaIxEED2Ev
.section .rodata._ZNSt6vectorIxSaIxEE17_M_realloc_insertIJRKxEEEvN9__gnu_cxx17__normal_iteratorIPxS1_EEDpOT_.str1.1,"aMS",@progbits,1
.LC1:
.string "vector::_M_realloc_insert"
.section .text._ZNSt6vectorIxSaIxEE17_M_realloc_insertIJRKxEEEvN9__gnu_cxx17__normal_iteratorIPxS1_EEDpOT_,"axG",@progbits,_ZNSt6vectorIxSaIxEE17_M_realloc_insertIJRKxEEEvN9__gnu_cxx17__normal_iteratorIPxS1_EEDpOT_,comdat
.align 2
.weak _ZNSt6vectorIxSaIxEE17_M_realloc_insertIJRKxEEEvN9__gnu_cxx17__normal_iteratorIPxS1_EEDpOT_
.type _ZNSt6vectorIxSaIxEE17_M_realloc_insertIJRKxEEEvN9__gnu_cxx17__normal_iteratorIPxS1_EEDpOT_, @function
_ZNSt6vectorIxSaIxEE17_M_realloc_insertIJRKxEEEvN9__gnu_cxx17__normal_iteratorIPxS1_EEDpOT_:
.LFB5144:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movq 8(%rdi), %rbp
movq (%rdi), %r13
movq %rbp, %rax
subq %r13, %rax
sarq $3, %rax
movabsq $1152921504606846975, %rdx
cmpq %rdx, %rax
je .L38
movq %rdi, %rbx
cmpq %r13, %rbp
movl $1, %edx
cmovne %rax, %rdx
addq %rdx, %rax
jc .L24
movabsq $1152921504606846975, %r14
cmpq %r14, %rax
cmovbe %rax, %r14
movq (%rsp), %r15
subq %r13, %r15
movl $0, %r12d
testq %rax, %rax
je .L25
jmp .L32
.L38:
leaq .LC1(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L39:
movq %r15, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memmove@PLT
leaq 8(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jg .L27
addq %rbp, %r15
movq 16(%rbx), %rsi
subq %r13, %rsi
jmp .L31
.L24:
movq (%rsp), %r15
subq %r13, %r15
movabsq $1152921504606846975, %r14
.L32:
leaq 0(,%r14,8), %rdi
call _Znwm@PLT
movq %rax, %r12
.L25:
movq 8(%rsp), %rax
movq (%rax), %rax
movq %rax, (%r12,%r15)
testq %r15, %r15
jg .L39
leaq 8(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jle .L29
.L27:
movq %rbp, %rdx
movq (%rsp), %rsi
movq %r15, %rdi
call memcpy@PLT
.L29:
addq %rbp, %r15
testq %r13, %r13
je .L30
movq 16(%rbx), %rsi
subq %r13, %rsi
.L31:
movq %r13, %rdi
call _ZdlPvm@PLT
.L30:
movq %r12, (%rbx)
movq %r15, 8(%rbx)
leaq (%r12,%r14,8), %rax
movq %rax, 16(%rbx)
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5144:
.size _ZNSt6vectorIxSaIxEE17_M_realloc_insertIJRKxEEEvN9__gnu_cxx17__normal_iteratorIPxS1_EEDpOT_, .-_ZNSt6vectorIxSaIxEE17_M_realloc_insertIJRKxEEEvN9__gnu_cxx17__normal_iteratorIPxS1_EEDpOT_
.section .rodata.str1.1
.LC2:
.string "Problem with file"
.text
.globl _Z8readFilePc
.type _Z8readFilePc, @function
_Z8readFilePc:
.LFB4568:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4568
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $544, %rsp
.cfi_def_cfa_offset 592
movq %rdi, %rbx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 536(%rsp)
xorl %eax, %eax
movq $0, (%rdi)
movq $0, 8(%rdi)
movq $0, 16(%rdi)
leaq 16(%rsp), %r14
leaq 272(%rsp), %rdi
call _ZNSt8ios_baseC2Ev@PLT
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 272(%rsp)
movq $0, 488(%rsp)
movb $0, 496(%rsp)
movb $0, 497(%rsp)
movq $0, 504(%rsp)
movq $0, 512(%rsp)
movq $0, 520(%rsp)
movq $0, 528(%rsp)
movq 8+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %r12
movq %r12, 16(%rsp)
movq 16+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %r13
movq -24(%r12), %rax
movq %r13, 16(%rsp,%rax)
movq $0, 24(%rsp)
movq 16(%rsp), %rax
movq %r14, %rdi
addq -24(%rax), %rdi
movl $0, %esi
.LEHB0:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE0:
leaq 24+_ZTVSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 16(%rsp)
leaq 40(%rax), %rax
movq %rax, 272(%rsp)
leaq 32(%rsp), %rdi
.LEHB1:
call _ZNSt13basic_filebufIcSt11char_traitsIcEEC1Ev@PLT
.LEHE1:
leaq 32(%rsp), %rsi
leaq 272(%rsp), %rdi
.LEHB2:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
leaq 32(%rsp), %rdi
movl $8, %edx
movq %rbp, %rsi
call _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
testq %rax, %rax
je .L69
movq 16(%rsp), %rax
movq -24(%rax), %rax
leaq 16(%rsp,%rax), %rdi
movl $0, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L42
.L69:
movq 16(%rsp), %rax
movq -24(%rax), %rax
leaq 16(%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $4, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.LEHE2:
.L42:
leaq 136(%rsp), %rdi
call _ZNKSt12__basic_fileIcE7is_openEv@PLT
testb %al, %al
je .L66
leaq 8(%rsp), %rbp
jmp .L43
.L63:
endbr64
movq %rax, %rbp
leaq 32(%rsp), %rdi
call _ZNSt13basic_filebufIcSt11char_traitsIcEED1Ev@PLT
.L46:
movq %r12, 16(%rsp)
movq -24(%r12), %rax
movq %r13, 16(%rsp,%rax)
movq $0, 24(%rsp)
.L47:
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 272(%rsp)
leaq 272(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
.L48:
movq %rbx, %rdi
call _ZNSt6vectorIxSaIxEED1Ev
movq 536(%rsp), %rax
subq %fs:40, %rax
je .L57
call __stack_chk_fail@PLT
.L62:
endbr64
movq %rax, %rbp
jmp .L46
.L61:
endbr64
movq %rax, %rbp
jmp .L47
.L66:
movl $16, %edi
call __cxa_allocate_exception@PLT
movq %rax, %r12
leaq .LC2(%rip), %rsi
movq %rax, %rdi
.LEHB3:
call _ZNSt16invalid_argumentC1EPKc@PLT
.LEHE3:
movq 536(%rsp), %rax
subq %fs:40, %rax
je .L49
call __stack_chk_fail@PLT
.L49:
movq _ZNSt16invalid_argumentD1Ev@GOTPCREL(%rip), %rdx
leaq _ZTISt16invalid_argument(%rip), %rsi
movq %r12, %rdi
.LEHB4:
call __cxa_throw@PLT
.L60:
endbr64
movq %rax, %rbp
jmp .L56
.L50:
movq %rbp, %rdx
movq %rbx, %rdi
call _ZNSt6vectorIxSaIxEE17_M_realloc_insertIJRKxEEEvN9__gnu_cxx17__normal_iteratorIPxS1_EEDpOT_
jmp .L43
.L71:
movq (%rax), %rdx
movq -24(%rdx), %rdx
testb $5, 32(%rax,%rdx)
jne .L70
movq 8(%rbx), %rsi
cmpq 16(%rbx), %rsi
je .L50
movq 8(%rsp), %rax
movq %rax, (%rsi)
addq $8, 8(%rbx)
.L43:
leaq 16(%rsp), %rdi
movq %rbp, %rsi
call _ZNSi10_M_extractIxEERSiRT_@PLT
.LEHE4:
jmp .L71
.L70:
leaq 24+_ZTVSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 16(%rsp)
leaq 40(%rax), %rax
movq %rax, 272(%rsp)
leaq 16+_ZTVSt13basic_filebufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 32(%rsp)
leaq 32(%rsp), %rdi
.LEHB5:
call _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv@PLT
.LEHE5:
jmp .L54
.L64:
endbr64
movq %rax, %rdi
call __cxa_begin_catch@PLT
call __cxa_end_catch@PLT
.L54:
leaq 136(%rsp), %rdi
call _ZNSt12__basic_fileIcED1Ev@PLT
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 32(%rsp)
leaq 88(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
movq %r12, 16(%rsp)
movq -24(%r12), %rax
movq %r13, 16(%rsp,%rax)
movq $0, 24(%rsp)
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 272(%rsp)
leaq 272(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 536(%rsp), %rax
subq %fs:40, %rax
jne .L72
movq %rbx, %rax
addq $544, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L59:
.cfi_restore_state
endbr64
movq %rax, %rbp
movq %r12, %rdi
call __cxa_free_exception@PLT
.L56:
leaq 16(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
jmp .L48
.L57:
movq %rbp, %rdi
.LEHB6:
call _Unwind_Resume@PLT
.LEHE6:
.L72:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4568:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.align 4
.LLSDA4568:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT4568-.LLSDATTD4568
.LLSDATTD4568:
.byte 0x1
.uleb128 .LLSDACSE4568-.LLSDACSB4568
.LLSDACSB4568:
.uleb128 .LEHB0-.LFB4568
.uleb128 .LEHE0-.LEHB0
.uleb128 .L61-.LFB4568
.uleb128 0
.uleb128 .LEHB1-.LFB4568
.uleb128 .LEHE1-.LEHB1
.uleb128 .L62-.LFB4568
.uleb128 0
.uleb128 .LEHB2-.LFB4568
.uleb128 .LEHE2-.LEHB2
.uleb128 .L63-.LFB4568
.uleb128 0
.uleb128 .LEHB3-.LFB4568
.uleb128 .LEHE3-.LEHB3
.uleb128 .L59-.LFB4568
.uleb128 0
.uleb128 .LEHB4-.LFB4568
.uleb128 .LEHE4-.LEHB4
.uleb128 .L60-.LFB4568
.uleb128 0
.uleb128 .LEHB5-.LFB4568
.uleb128 .LEHE5-.LEHB5
.uleb128 .L64-.LFB4568
.uleb128 0x1
.uleb128 .LEHB6-.LFB4568
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.LLSDACSE4568:
.byte 0x1
.byte 0
.align 4
.long 0
.LLSDATT4568:
.text
.size _Z8readFilePc, .-_Z8readFilePc
.section .rodata.str1.1
.LC3:
.string "Pass file path\n"
.LC4:
.string "Czas: %.4fms\n"
.LC5:
.string "GPU to CPU copy error\n"
.LC6:
.string " prime"
.LC7:
.string " composite"
.text
.globl main
.type main, @function
main:
.LFB4585:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4585
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $136, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
cmpl $1, %edi
jle .L107
movq $0, -112(%rbp)
movq $0, -104(%rbp)
movq $0, -96(%rbp)
leaq -80(%rbp), %rdi
movq 8(%rsi), %rsi
.LEHB7:
call _Z8readFilePc
.LEHE7:
jmp .L108
.L107:
leaq .LC3(%rip), %rsi
movl $2, %edi
.LEHB8:
call __printf_chk@PLT
.LEHE8:
movl $-1, %ebx
jmp .L73
.L108:
movq -80(%rbp), %r15
movq %r15, -112(%rbp)
movq -72(%rbp), %rbx
movq %rbx, -104(%rbp)
movq -64(%rbp), %rax
movq %rax, -96(%rbp)
movq $0, -80(%rbp)
movq $0, -72(%rbp)
movq $0, -64(%rbp)
leaq -80(%rbp), %rdi
call _ZNSt6vectorIxSaIxEED1Ev
movq %rbx, %rdx
subq %r15, %rdx
movq %rdx, %r14
sarq $3, %r14
movl %r14d, -172(%rbp)
movslq %r14d, %rbx
leal 0(,%r14,8), %r13d
leaq 15(,%rbx,8), %rax
movq %rax, %rsi
andq $-16, %rsi
andq $-4096, %rax
movq %rsp, %rcx
subq %rax, %rcx
.L76:
cmpq %rcx, %rsp
je .L77
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L76
.L77:
movq %rsi, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L78
orq $0, -8(%rsp,%rax)
.L78:
leaq 7(%rsp), %r12
movq %r12, %rax
shrq $3, %rax
andq $-8, %r12
cmpq $8, %rdx
jle .L79
movq %r15, %rsi
movq %r12, %rdi
call memmove@PLT
.L80:
movq %rbx, %rdi
call malloc@PLT
movq %rax, -168(%rbp)
movslq %r13d, %r13
leaq -160(%rbp), %rdi
movq %r13, %rsi
.LEHB9:
call cudaMalloc@PLT
jmp .L109
.L79:
jne .L80
movq (%r15), %rdx
movq %rdx, 0(,%rax,8)
jmp .L80
.L109:
leaq -152(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq -160(%rbp), %rdi
call cudaMemcpy@PLT
leaq -144(%rbp), %rdi
call cudaEventCreate@PLT
leaq -136(%rbp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq -144(%rbp), %rdi
call cudaEventRecord@PLT
movl $1, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl %r14d, -124(%rbp)
movl $1, -120(%rbp)
movl $1, -116(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -80(%rbp), %rdx
movl $1, %ecx
movq -124(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L81
movl -172(%rbp), %ecx
movl %ecx, %edx
movq -152(%rbp), %rsi
movq -160(%rbp), %rdi
call _Z32__device_stub__Z9calculatePxPbiiPxPbii
.L81:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq -136(%rbp), %rdi
call cudaEventRecord@PLT
movq -136(%rbp), %rdi
call cudaEventSynchronize@PLT
leaq -80(%rbp), %rdi
movq -136(%rbp), %rdx
movq -144(%rbp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd -80(%rbp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %rbx, %rdx
movq -152(%rbp), %rsi
movq -168(%rbp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
je .L82
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.L82:
movq -160(%rbp), %rdi
call cudaFree@PLT
movq -152(%rbp), %rdi
call cudaFree@PLT
testl %r14d, %r14d
jle .L83
movq -168(%rbp), %rax
movq %rax, %rbx
movl %r14d, %r14d
addq %rax, %r14
jmp .L94
.L116:
movq %rax, %r13
movl $6, %edx
leaq .LC6(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 0(%r13), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %r15
testq %r15, %r15
je .L110
cmpb $0, 56(%r15)
je .L87
movzbl 67(%r15), %esi
.L88:
movsbl %sil, %esi
movq %r13, %rdi
call _ZNSo3putEc@PLT
jmp .L111
.L110:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L112
call _ZSt16__throw_bad_castv@PLT
.L103:
endbr64
movq %rax, %rbx
jmp .L97
.L112:
call __stack_chk_fail@PLT
.L87:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L88
.L111:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L89
.L84:
movq (%r12), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIxEERSoT_@PLT
movq %rax, %r13
movl $10, %edx
leaq .LC7(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 0(%r13), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %r15
testq %r15, %r15
je .L113
cmpb $0, 56(%r15)
je .L92
movzbl 67(%r15), %esi
.L93:
movsbl %sil, %esi
movq %r13, %rdi
call _ZNSo3putEc@PLT
jmp .L114
.L113:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L115
call _ZSt16__throw_bad_castv@PLT
.L115:
call __stack_chk_fail@PLT
.L92:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L93
.L114:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.L89:
addq $1, %rbx
addq $8, %r12
cmpq %rbx, %r14
je .L83
.L94:
cmpb $0, (%rbx)
je .L84
movq (%r12), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIxEERSoT_@PLT
.LEHE9:
jmp .L116
.L83:
movq -168(%rbp), %rdi
call free@PLT
movl $0, %ebx
.L98:
leaq -112(%rbp), %rdi
call _ZNSt6vectorIxSaIxEED1Ev
.L73:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L117
movl %ebx, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L102:
.cfi_restore_state
endbr64
movq %rax, %rdi
movq %rax, %rbx
cmpq $1, %rdx
jne .L97
call __cxa_begin_catch@PLT
movq %rax, %rdi
movq (%rax), %rax
call *16(%rax)
movq %rax, %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB10:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE10:
call __cxa_end_catch@PLT
movl $-1, %ebx
jmp .L98
.L104:
endbr64
movq %rax, %rbx
call __cxa_end_catch@PLT
.L97:
leaq -112(%rbp), %rdi
call _ZNSt6vectorIxSaIxEED1Ev
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L100
call __stack_chk_fail@PLT
.L100:
movq %rbx, %rdi
.LEHB11:
call _Unwind_Resume@PLT
.LEHE11:
.L117:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4585:
.section .gcc_except_table
.align 4
.LLSDA4585:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT4585-.LLSDATTD4585
.LLSDATTD4585:
.byte 0x1
.uleb128 .LLSDACSE4585-.LLSDACSB4585
.LLSDACSB4585:
.uleb128 .LEHB7-.LFB4585
.uleb128 .LEHE7-.LEHB7
.uleb128 .L102-.LFB4585
.uleb128 0x3
.uleb128 .LEHB8-.LFB4585
.uleb128 .LEHE8-.LEHB8
.uleb128 0
.uleb128 0
.uleb128 .LEHB9-.LFB4585
.uleb128 .LEHE9-.LEHB9
.uleb128 .L103-.LFB4585
.uleb128 0
.uleb128 .LEHB10-.LFB4585
.uleb128 .LEHE10-.LEHB10
.uleb128 .L104-.LFB4585
.uleb128 0
.uleb128 .LEHB11-.LFB4585
.uleb128 .LEHE11-.LEHB11
.uleb128 0
.uleb128 0
.LLSDACSE4585:
.byte 0
.byte 0
.byte 0x1
.byte 0x7d
.align 4
.long DW.ref._ZTISt16invalid_argument-.
.LLSDATT4585:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref._ZTISt16invalid_argument
.weak DW.ref._ZTISt16invalid_argument
.section .data.rel.local.DW.ref._ZTISt16invalid_argument,"awG",@progbits,DW.ref._ZTISt16invalid_argument,comdat
.align 8
.type DW.ref._ZTISt16invalid_argument, @object
.size DW.ref._ZTISt16invalid_argument, 8
DW.ref._ZTISt16invalid_argument:
.quad _ZTISt16invalid_argument
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <iostream>
#include <map>
#include <string>
#include <fstream>
#include <vector>
using namespace std;
#define ll long long
const int GRID_SIZE = 1;
// Use naive method
__device__ bool isPrime(ll n)
{
if(n<2)
return false;
for(ll i=2;i*i<=n;i++)
if(n%i==0)
return false;
return true;
}
// Read numbers from file and add to vector
std::vector<ll> readFile(char* arg){
vector<ll> numbersFromFile;
std::ifstream infile(arg);
ll number;
if(!infile.is_open()) {
throw std::invalid_argument("Problem with file");
}
while (infile >> number) {
numbersFromFile.push_back(number);
}
return numbersFromFile;
}
__global__ void calculate(ll *Arr, bool *results, int sizeOfArray, int amountOfBlocks){
int x = (blockIdx.x * blockDim.x) + threadIdx.x;
if (amountOfBlocks >= sizeOfArray){
results[x] += isPrime(Arr[x]);
} else{
int sizeOfPart = sizeOfArray / amountOfBlocks;
int restOfDivide = sizeOfArray%amountOfBlocks;
int startPart = sizeOfPart * x;
int endPart = sizeOfPart * (x + 1);
if (endPart <= sizeOfArray)
{
int restStart = sizeOfPart * amountOfBlocks;
for (int i = startPart; i < endPart; i++){
results[i] += isPrime(Arr[i]);
}
if (x < restOfDivide){
results[restStart + x] += isPrime(Arr[restStart + x]);
}
}
}
}
int main(int argc, char** argv )
{
float time;
if ( argc < 2 )
{
printf("Pass file path\n");
return -1;
}
vector<ll> numbersFromFile;
try {
numbersFromFile = readFile(argv[1]);
} catch ( const std::invalid_argument& ex ) {
cout << ex.what() << endl;
return -1;
}
int sizeOfArray = numbersFromFile.size();
int sizeToAllocateLongLong = sizeOfArray * sizeof(ll);
int sizeToAllocateBool = sizeOfArray * sizeof(bool);
ll numbersFromFileArr[sizeOfArray];
std::copy(numbersFromFile.begin(), numbersFromFile.end(), numbersFromFileArr);
bool* results = (bool *) malloc (sizeToAllocateBool);
ll* c_arr;
bool* c_results;
cudaMalloc((void**) &c_arr, sizeToAllocateLongLong);
cudaMalloc((void**) &c_results, sizeToAllocateBool);
cudaMemcpy((void *)c_arr, (void *)numbersFromFileArr, sizeToAllocateLongLong, cudaMemcpyHostToDevice);
//Start timer
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
int amountOfBlocks = sizeOfArray;
calculate<<<amountOfBlocks, GRID_SIZE>>>(c_arr, c_results, sizeOfArray, amountOfBlocks);
//End timer and put result into time variable
cudaDeviceSynchronize();
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
printf("Czas: %.4fms\n", time);
if (cudaMemcpy((void *)results, (void *)c_results , sizeToAllocateBool, cudaMemcpyDeviceToHost) != cudaSuccess) {
cout<<"GPU to CPU copy error\n";
}
cudaFree(c_arr);
cudaFree(c_results);
for(int j = 0; j < sizeOfArray ; j++)
{
if (results[j]){
cout << numbersFromFileArr[j] << " prime" << endl;
} else {
cout << numbersFromFileArr[j] << " composite" << endl;
}
}
free(results);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <map>
#include <string>
#include <fstream>
#include <vector>
using namespace std;
#define ll long long
const int GRID_SIZE = 1;
// Use naive method
__device__ bool isPrime(ll n)
{
if(n<2)
return false;
for(ll i=2;i*i<=n;i++)
if(n%i==0)
return false;
return true;
}
// Read numbers from file and add to vector
std::vector<ll> readFile(char* arg){
vector<ll> numbersFromFile;
std::ifstream infile(arg);
ll number;
if(!infile.is_open()) {
throw std::invalid_argument("Problem with file");
}
while (infile >> number) {
numbersFromFile.push_back(number);
}
return numbersFromFile;
}
__global__ void calculate(ll *Arr, bool *results, int sizeOfArray, int amountOfBlocks){
int x = (blockIdx.x * blockDim.x) + threadIdx.x;
if (amountOfBlocks >= sizeOfArray){
results[x] += isPrime(Arr[x]);
} else{
int sizeOfPart = sizeOfArray / amountOfBlocks;
int restOfDivide = sizeOfArray%amountOfBlocks;
int startPart = sizeOfPart * x;
int endPart = sizeOfPart * (x + 1);
if (endPart <= sizeOfArray)
{
int restStart = sizeOfPart * amountOfBlocks;
for (int i = startPart; i < endPart; i++){
results[i] += isPrime(Arr[i]);
}
if (x < restOfDivide){
results[restStart + x] += isPrime(Arr[restStart + x]);
}
}
}
}
int main(int argc, char** argv )
{
float time;
if ( argc < 2 )
{
printf("Pass file path\n");
return -1;
}
vector<ll> numbersFromFile;
try {
numbersFromFile = readFile(argv[1]);
} catch ( const std::invalid_argument& ex ) {
cout << ex.what() << endl;
return -1;
}
int sizeOfArray = numbersFromFile.size();
int sizeToAllocateLongLong = sizeOfArray * sizeof(ll);
int sizeToAllocateBool = sizeOfArray * sizeof(bool);
ll numbersFromFileArr[sizeOfArray];
std::copy(numbersFromFile.begin(), numbersFromFile.end(), numbersFromFileArr);
bool* results = (bool *) malloc (sizeToAllocateBool);
ll* c_arr;
bool* c_results;
hipMalloc((void**) &c_arr, sizeToAllocateLongLong);
hipMalloc((void**) &c_results, sizeToAllocateBool);
hipMemcpy((void *)c_arr, (void *)numbersFromFileArr, sizeToAllocateLongLong, hipMemcpyHostToDevice);
//Start timer
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
int amountOfBlocks = sizeOfArray;
calculate<<<amountOfBlocks, GRID_SIZE>>>(c_arr, c_results, sizeOfArray, amountOfBlocks);
//End timer and put result into time variable
hipDeviceSynchronize();
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("Czas: %.4fms\n", time);
if (hipMemcpy((void *)results, (void *)c_results , sizeToAllocateBool, hipMemcpyDeviceToHost) != hipSuccess) {
cout<<"GPU to CPU copy error\n";
}
hipFree(c_arr);
hipFree(c_results);
for(int j = 0; j < sizeOfArray ; j++)
{
if (results[j]){
cout << numbersFromFileArr[j] << " prime" << endl;
} else {
cout << numbersFromFileArr[j] << " composite" << endl;
}
}
free(results);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <map>
#include <string>
#include <fstream>
#include <vector>
using namespace std;
#define ll long long
const int GRID_SIZE = 1;
// Use naive method
__device__ bool isPrime(ll n)
{
if(n<2)
return false;
for(ll i=2;i*i<=n;i++)
if(n%i==0)
return false;
return true;
}
// Read numbers from file and add to vector
std::vector<ll> readFile(char* arg){
vector<ll> numbersFromFile;
std::ifstream infile(arg);
ll number;
if(!infile.is_open()) {
throw std::invalid_argument("Problem with file");
}
while (infile >> number) {
numbersFromFile.push_back(number);
}
return numbersFromFile;
}
__global__ void calculate(ll *Arr, bool *results, int sizeOfArray, int amountOfBlocks){
int x = (blockIdx.x * blockDim.x) + threadIdx.x;
if (amountOfBlocks >= sizeOfArray){
results[x] += isPrime(Arr[x]);
} else{
int sizeOfPart = sizeOfArray / amountOfBlocks;
int restOfDivide = sizeOfArray%amountOfBlocks;
int startPart = sizeOfPart * x;
int endPart = sizeOfPart * (x + 1);
if (endPart <= sizeOfArray)
{
int restStart = sizeOfPart * amountOfBlocks;
for (int i = startPart; i < endPart; i++){
results[i] += isPrime(Arr[i]);
}
if (x < restOfDivide){
results[restStart + x] += isPrime(Arr[restStart + x]);
}
}
}
}
int main(int argc, char** argv )
{
float time;
if ( argc < 2 )
{
printf("Pass file path\n");
return -1;
}
vector<ll> numbersFromFile;
try {
numbersFromFile = readFile(argv[1]);
} catch ( const std::invalid_argument& ex ) {
cout << ex.what() << endl;
return -1;
}
int sizeOfArray = numbersFromFile.size();
int sizeToAllocateLongLong = sizeOfArray * sizeof(ll);
int sizeToAllocateBool = sizeOfArray * sizeof(bool);
ll numbersFromFileArr[sizeOfArray];
std::copy(numbersFromFile.begin(), numbersFromFile.end(), numbersFromFileArr);
bool* results = (bool *) malloc (sizeToAllocateBool);
ll* c_arr;
bool* c_results;
hipMalloc((void**) &c_arr, sizeToAllocateLongLong);
hipMalloc((void**) &c_results, sizeToAllocateBool);
hipMemcpy((void *)c_arr, (void *)numbersFromFileArr, sizeToAllocateLongLong, hipMemcpyHostToDevice);
//Start timer
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
int amountOfBlocks = sizeOfArray;
calculate<<<amountOfBlocks, GRID_SIZE>>>(c_arr, c_results, sizeOfArray, amountOfBlocks);
//End timer and put result into time variable
hipDeviceSynchronize();
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("Czas: %.4fms\n", time);
if (hipMemcpy((void *)results, (void *)c_results , sizeToAllocateBool, hipMemcpyDeviceToHost) != hipSuccess) {
cout<<"GPU to CPU copy error\n";
}
hipFree(c_arr);
hipFree(c_results);
for(int j = 0; j < sizeOfArray ; j++)
{
if (results[j]){
cout << numbersFromFileArr[j] << " prime" << endl;
} else {
cout << numbersFromFileArr[j] << " composite" << endl;
}
}
free(results);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9calculatePxPbii
.globl _Z9calculatePxPbii
.p2align 8
.type _Z9calculatePxPbii,@function
_Z9calculatePxPbii:
s_clause 0x2
s_load_b32 s8, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s8, 0xffff
s_cmp_lt_i32 s3, s2
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
s_cbranch_scc1 .LBB0_9
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s0, 0
s_mov_b64 s[8:9], 2
s_mov_b32 s1, 0
s_mov_b32 s10, exec_lo
v_lshlrev_b64 v[3:4], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b64 v[3:4], v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i64_e32 1, v[3:4]
s_cbranch_execnz .LBB0_4
s_branch .LBB0_11
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[5:6]
s_add_u32 s8, s8, 1
s_addc_u32 s9, s9, 0
s_and_not1_b32 s0, s12, exec_lo
s_and_not1_b32 s13, s13, exec_lo
s_and_b32 s12, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s12, s0, s12
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, exec_lo, s12
s_or_b32 s1, s0, s1
s_and_not1_b32 s0, s11, exec_lo
s_and_b32 s11, s13, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s11, s0, s11
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_10
.LBB0_4:
s_mul_i32 s0, s8, s9
s_mul_hi_u32 s14, s8, s8
s_and_not1_b32 s13, s13, exec_lo
s_add_i32 s15, s14, s0
s_mul_i32 s14, s8, s8
s_add_i32 s15, s15, s0
s_or_b32 s12, s12, exec_lo
v_cmp_gt_i64_e32 vcc_lo, s[14:15], v[3:4]
v_cmp_le_i64_e64 s0, s[14:15], v[3:4]
s_and_b32 s14, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_or_b32 s13, s13, s14
s_and_saveexec_b32 s14, s0
s_cbranch_execz .LBB0_3
v_or_b32_e32 v6, s9, v4
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ne_u64_e32 vcc_lo, 0, v[5:6]
s_and_saveexec_b32 s0, vcc_lo
s_xor_b32 s15, exec_lo, s0
s_cbranch_execz .LBB0_7
v_cvt_f32_u32_e32 v0, s8
v_cvt_f32_u32_e32 v5, s9
s_sub_u32 s0, 0, s8
s_subb_u32 s16, 0, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v0, v5, 0x4f800000, v0
v_rcp_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x5f7ffffc, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, 0x2f800000, v0
v_trunc_f32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmamk_f32 v0, v5, 0xcf800000, v0
v_cvt_u32_f32_e32 v5, v5
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v6, s0, v5
v_mul_hi_u32 v7, s0, v0
v_mul_lo_u32 v8, s16, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, v7, v6
v_mul_lo_u32 v7, s0, v0
v_add_nc_u32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v8, v0, v7
v_mul_lo_u32 v9, v0, v6
v_mul_hi_u32 v10, v0, v6
v_mul_hi_u32 v11, v5, v7
v_mul_lo_u32 v7, v5, v7
v_mul_hi_u32 v12, v5, v6
v_mul_lo_u32 v6, v5, v6
v_add_co_u32 v8, vcc_lo, v8, v9
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v8, v7
v_add_co_ci_u32_e32 v7, vcc_lo, v9, v11, vcc_lo
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, v7, v6
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v6
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v6, s0, v0
v_mul_lo_u32 v8, s16, v0
v_mul_lo_u32 v7, s0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, v6, v7
v_mul_lo_u32 v7, s0, v0
v_add_nc_u32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v8, v0, v7
v_mul_lo_u32 v9, v0, v6
v_mul_hi_u32 v10, v0, v6
v_mul_hi_u32 v11, v5, v7
v_mul_lo_u32 v7, v5, v7
v_mul_hi_u32 v12, v5, v6
v_mul_lo_u32 v6, v5, v6
v_add_co_u32 v8, vcc_lo, v8, v9
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v8, v7
v_add_co_ci_u32_e32 v7, vcc_lo, v9, v11, vcc_lo
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, v7, v6
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v6
v_add_co_ci_u32_e32 v11, vcc_lo, v5, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v12, v3, v0
v_mad_u64_u32 v[7:8], null, v4, v0, 0
v_mad_u64_u32 v[5:6], null, v3, v11, 0
v_mad_u64_u32 v[9:10], null, v4, v11, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, v12, v5
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v7
v_add_co_ci_u32_e32 v0, vcc_lo, v5, v8, vcc_lo
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v9
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v8, s9, v0
v_mad_u64_u32 v[5:6], null, s8, v0, 0
v_mul_lo_u32 v0, s8, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v5, vcc_lo, v3, v5
v_add3_u32 v0, v6, v0, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v6, v4, v0
v_subrev_co_ci_u32_e64 v6, s0, s9, v6, vcc_lo
v_sub_co_ci_u32_e32 v0, vcc_lo, v4, v0, vcc_lo
v_sub_co_u32 v7, vcc_lo, v5, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_subrev_co_ci_u32_e64 v8, s0, 0, v6, vcc_lo
v_cmp_le_u32_e64 s0, s8, v5
v_subrev_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s9, v0
v_cndmask_b32_e64 v9, 0, -1, s0
v_cmp_le_u32_e64 s0, s8, v7
v_cndmask_b32_e64 v12, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, s9, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v10, 0, -1, s0
v_cmp_le_u32_e64 s0, s9, v8
v_cndmask_b32_e64 v11, 0, -1, s0
v_cmp_eq_u32_e64 s0, s9, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v10, v11, v10, vcc_lo
v_sub_co_u32 v11, vcc_lo, v7, s8
v_subrev_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v10
v_cndmask_b32_e64 v9, v12, v9, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v6, v8, v6 :: v_dual_cndmask_b32 v7, v7, v11
v_cmp_ne_u32_e32 vcc_lo, 0, v9
s_delay_alu instid0(VALU_DEP_2)
v_dual_cndmask_b32 v6, v0, v6 :: v_dual_cndmask_b32 v5, v5, v7
.LBB0_7:
s_and_not1_saveexec_b32 s0, s15
s_cbranch_execz .LBB0_2
v_cvt_f32_u32_e32 v0, s8
s_sub_i32 s15, 0, s8
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, s15, v0
v_mul_hi_u32 v5, v0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v5
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s8
v_sub_nc_u32_e32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s8, v0
v_cmp_le_u32_e32 vcc_lo, s8, v0
v_cndmask_b32_e32 v0, v0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s8, v0
v_cmp_le_u32_e32 vcc_lo, s8, v0
v_cndmask_b32_e32 v5, v0, v5, vcc_lo
s_branch .LBB0_2
.LBB0_9:
s_mov_b32 s1, 0
s_branch .LBB0_12
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s0, s11, exec_lo
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s10
s_mov_b32 s1, -1
s_cbranch_execnz .LBB0_38
.LBB0_12:
s_ashr_i32 s0, s3, 31
s_ashr_i32 s11, s2, 31
s_add_i32 s8, s3, s0
s_add_i32 s12, s2, s11
s_xor_b32 s8, s8, s0
s_xor_b32 s12, s12, s11
v_cvt_f32_u32_e32 v0, s8
s_sub_i32 s10, 0, s8
s_xor_b32 s0, s11, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s9, v0
s_mul_i32 s10, s10, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s10, s9, s10
s_add_i32 s9, s9, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s9, s12, s9
s_mul_i32 s10, s9, s8
s_add_i32 s11, s9, 1
s_sub_i32 s10, s12, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s12, s10, s8
s_cmp_ge_u32 s10, s8
s_cselect_b32 s9, s11, s9
s_cselect_b32 s10, s12, s10
s_add_i32 s11, s9, 1
s_cmp_ge_u32 s10, s8
s_cselect_b32 s8, s11, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s8, s8, s0
s_sub_i32 s8, s8, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s8, v1, s[8:9]
s_mov_b32 s9, exec_lo
v_cmpx_ge_i32_e64 s2, v2
s_cbranch_execz .LBB0_37
v_mul_lo_u32 v3, s8, v1
s_mov_b32 s12, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 v3, v2
s_cbranch_execz .LBB0_25
v_mov_b32_e32 v5, 0
s_mov_b32 s13, 0
s_branch .LBB0_17
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s0, s14, exec_lo
s_and_b32 s10, s17, exec_lo
s_or_b32 s14, s0, s10
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s15
v_add_co_u32 v6, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v4, vcc_lo
v_cndmask_b32_e64 v4, 0, -1, s14
v_add_nc_u32_e32 v3, 1, v3
global_load_u8 v0, v[6:7], off
v_and_b32_e32 v4, 0xff, v4
v_cmp_eq_u32_e32 vcc_lo, v3, v2
s_or_b32 s13, vcc_lo, s13
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ne_u16_e64 s0, v0, v4
v_cndmask_b32_e64 v0, 0, 1, s0
global_store_b8 v[6:7], v0, off
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execz .LBB0_25
.LBB0_17:
v_ashrrev_i32_e32 v4, 31, v3
s_mov_b64 s[10:11], 2
s_and_not1_b32 s14, s14, exec_lo
s_mov_b32 s16, 0
s_mov_b32 s15, exec_lo
v_lshlrev_b64 v[6:7], 3, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b64 v[7:8], v[6:7], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i64_e32 1, v[7:8]
s_cbranch_execnz .LBB0_20
s_branch .LBB0_16
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
s_add_u32 s10, s10, 1
s_addc_u32 s11, s11, 0
s_and_not1_b32 s0, s18, exec_lo
s_and_not1_b32 s19, s19, exec_lo
s_and_b32 s18, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s18, s0, s18
.LBB0_19:
s_or_b32 exec_lo, exec_lo, s20
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, exec_lo, s18
s_or_b32 s16, s0, s16
s_and_not1_b32 s0, s17, exec_lo
s_and_b32 s17, s19, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s17, s0, s17
s_and_not1_b32 exec_lo, exec_lo, s16
s_cbranch_execz .LBB0_15
.LBB0_20:
s_mul_i32 s0, s10, s11
s_mul_hi_u32 s20, s10, s10
s_and_not1_b32 s19, s19, exec_lo
s_add_i32 s21, s20, s0
s_mul_i32 s20, s10, s10
s_add_i32 s21, s21, s0
s_or_b32 s18, s18, exec_lo
v_cmp_gt_i64_e32 vcc_lo, s[20:21], v[7:8]
v_cmp_le_i64_e64 s0, s[20:21], v[7:8]
s_and_b32 s20, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_or_b32 s19, s19, s20
s_and_saveexec_b32 s20, s0
s_cbranch_execz .LBB0_19
v_or_b32_e32 v6, s11, v8
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ne_u64_e32 0, v[5:6]
s_xor_b32 s21, exec_lo, s0
s_cbranch_execz .LBB0_23
v_cvt_f32_u32_e32 v0, s10
v_cvt_f32_u32_e32 v6, s11
s_sub_u32 s0, 0, s10
s_subb_u32 s22, 0, s11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v0, 0x4f800000, v6
v_rcp_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x5f7ffffc, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, 0x2f800000, v0
v_trunc_f32_e32 v6, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v0, 0xcf800000, v6
v_cvt_u32_f32_e32 v6, v6
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v9, s0, v6
v_mul_hi_u32 v10, s0, v0
v_mul_lo_u32 v11, s22, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v9, v10, v9
v_mul_lo_u32 v10, s0, v0
v_add_nc_u32_e32 v9, v9, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v11, v0, v10
v_mul_lo_u32 v12, v0, v9
v_mul_hi_u32 v13, v0, v9
v_mul_hi_u32 v14, v6, v10
v_mul_lo_u32 v10, v6, v10
v_mul_hi_u32 v15, v6, v9
v_mul_lo_u32 v9, v6, v9
v_add_co_u32 v11, vcc_lo, v11, v12
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, v11, v10
v_add_co_ci_u32_e32 v10, vcc_lo, v12, v14, vcc_lo
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v15, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, v10, v9
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v9
v_add_co_ci_u32_e32 v6, vcc_lo, v6, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v9, s0, v0
v_mul_lo_u32 v11, s22, v0
v_mul_lo_u32 v10, s0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v9, v9, v10
v_mul_lo_u32 v10, s0, v0
v_add_nc_u32_e32 v9, v9, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v11, v0, v10
v_mul_lo_u32 v12, v0, v9
v_mul_hi_u32 v13, v0, v9
v_mul_hi_u32 v14, v6, v10
v_mul_lo_u32 v10, v6, v10
v_mul_hi_u32 v15, v6, v9
v_mul_lo_u32 v9, v6, v9
v_add_co_u32 v11, vcc_lo, v11, v12
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, v11, v10
v_add_co_ci_u32_e32 v10, vcc_lo, v12, v14, vcc_lo
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v15, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, v10, v9
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v9
v_add_co_ci_u32_e32 v6, vcc_lo, v6, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v15, v7, v0
v_mad_u64_u32 v[11:12], null, v8, v0, 0
v_mad_u64_u32 v[9:10], null, v7, v6, 0
v_mad_u64_u32 v[13:14], null, v8, v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, v15, v9
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v11
v_add_co_ci_u32_e32 v0, vcc_lo, v6, v12, vcc_lo
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v13
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v11, s11, v0
v_mad_u64_u32 v[9:10], null, s10, v0, 0
v_mul_lo_u32 v0, s10, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v9, vcc_lo, v7, v9
v_add3_u32 v0, v10, v0, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v6, v8, v0
v_subrev_co_ci_u32_e64 v6, s0, s11, v6, vcc_lo
v_sub_co_ci_u32_e32 v0, vcc_lo, v8, v0, vcc_lo
v_sub_co_u32 v10, vcc_lo, v9, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_subrev_co_ci_u32_e64 v11, s0, 0, v6, vcc_lo
v_cmp_le_u32_e64 s0, s10, v9
v_subrev_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s11, v0
v_cndmask_b32_e64 v12, 0, -1, s0
v_cmp_le_u32_e64 s0, s10, v10
v_cndmask_b32_e64 v15, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, s11, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v13, 0, -1, s0
v_cmp_le_u32_e64 s0, s11, v11
v_cndmask_b32_e64 v14, 0, -1, s0
v_cmp_eq_u32_e64 s0, s11, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v13, v14, v13, vcc_lo
v_sub_co_u32 v14, vcc_lo, v10, s10
v_subrev_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v13
v_cndmask_b32_e64 v12, v15, v12, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v6, v11, v6, vcc_lo
v_cndmask_b32_e32 v11, v10, v14, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v12
s_delay_alu instid0(VALU_DEP_2)
v_dual_cndmask_b32 v10, v0, v6 :: v_dual_cndmask_b32 v9, v9, v11
.LBB0_23:
s_and_not1_saveexec_b32 s0, s21
s_cbranch_execz .LBB0_18
v_cvt_f32_u32_e32 v0, s10
s_sub_i32 s21, 0, s10
v_mov_b32_e32 v10, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v6, s21, v0
v_mul_hi_u32 v6, v0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v6
v_mul_hi_u32 v0, v7, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s10
v_sub_nc_u32_e32 v0, v7, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s10, v0
v_cmp_le_u32_e32 vcc_lo, s10, v0
v_cndmask_b32_e32 v0, v0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s10, v0
v_cmp_le_u32_e32 vcc_lo, s10, v0
v_cndmask_b32_e32 v9, v0, v6, vcc_lo
s_branch .LBB0_18
.LBB0_25:
s_or_b32 exec_lo, exec_lo, s12
s_mul_i32 s0, s8, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s0, s2, s0
s_mov_b32 s2, s1
v_cmp_gt_i32_e32 vcc_lo, s0, v1
s_and_saveexec_b32 s10, vcc_lo
s_cbranch_execz .LBB0_36
v_mad_u64_u32 v[2:3], null, s8, s3, v[1:2]
s_mov_b32 s0, 0
s_mov_b64 s[2:3], 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 3, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_mov_b32 s4, 0
s_mov_b32 s5, exec_lo
global_load_b64 v[0:1], v[0:1], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i64_e32 1, v[0:1]
s_cbranch_execnz .LBB0_29
s_branch .LBB0_35
.LBB0_27:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
s_and_not1_b32 s0, s11, exec_lo
s_and_not1_b32 s12, s12, exec_lo
s_and_b32 s11, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s11, s0, s11
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, exec_lo, s11
s_or_b32 s4, s0, s4
s_and_not1_b32 s0, s8, exec_lo
s_and_b32 s8, s12, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s8, s0, s8
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB0_34
.LBB0_29:
s_mul_i32 s0, s2, s3
s_mul_hi_u32 s13, s2, s2
s_mul_i32 s14, s2, s2
s_add_i32 s13, s13, s0
s_and_not1_b32 s12, s12, exec_lo
s_add_i32 s15, s13, s0
s_or_b32 s11, s11, exec_lo
v_cmp_gt_i64_e32 vcc_lo, s[14:15], v[0:1]
s_and_b32 s13, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s12, s12, s13
s_mov_b32 s13, exec_lo
v_cmpx_le_i64_e64 s[14:15], v[0:1]
s_cbranch_execz .LBB0_28
v_or_b32_e32 v5, s3, v1
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
s_and_saveexec_b32 s0, vcc_lo
s_xor_b32 s14, exec_lo, s0
s_cbranch_execz .LBB0_32
v_cvt_f32_u32_e32 v4, s2
v_cvt_f32_u32_e32 v5, s3
s_sub_u32 s0, 0, s2
s_subb_u32 s15, 0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v4, v5, 0x4f800000, v4
v_rcp_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x5f7ffffc, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, 0x2f800000, v4
v_trunc_f32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmamk_f32 v4, v5, 0xcf800000, v4
v_cvt_u32_f32_e32 v5, v5
v_cvt_u32_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v6, s0, v5
v_mul_hi_u32 v7, s0, v4
v_mul_lo_u32 v8, s15, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, v7, v6
v_mul_lo_u32 v7, s0, v4
v_add_nc_u32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v8, v4, v7
v_mul_lo_u32 v9, v4, v6
v_mul_hi_u32 v10, v4, v6
v_mul_hi_u32 v11, v5, v7
v_mul_lo_u32 v7, v5, v7
v_mul_hi_u32 v12, v5, v6
v_mul_lo_u32 v6, v5, v6
v_add_co_u32 v8, vcc_lo, v8, v9
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v8, v7
v_add_co_ci_u32_e32 v7, vcc_lo, v9, v11, vcc_lo
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, v7, v6
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, v4, v6
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v6, s0, v4
v_mul_lo_u32 v8, s15, v4
v_mul_lo_u32 v7, s0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, v6, v7
v_mul_lo_u32 v7, s0, v4
v_add_nc_u32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v8, v4, v7
v_mul_lo_u32 v9, v4, v6
v_mul_hi_u32 v10, v4, v6
v_mul_hi_u32 v11, v5, v7
v_mul_lo_u32 v7, v5, v7
v_mul_hi_u32 v12, v5, v6
v_mul_lo_u32 v6, v5, v6
v_add_co_u32 v8, vcc_lo, v8, v9
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v8, v7
v_add_co_ci_u32_e32 v7, vcc_lo, v9, v11, vcc_lo
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, v7, v6
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, v4, v6
v_add_co_ci_u32_e32 v10, vcc_lo, v5, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v11, v0, v8
v_mad_u64_u32 v[6:7], null, v1, v8, 0
v_mad_u64_u32 v[4:5], null, v0, v10, 0
v_mad_u64_u32 v[8:9], null, v1, v10, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v11, v4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, v4, v6
v_add_co_ci_u32_e32 v4, vcc_lo, v5, v7, vcc_lo
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, v4, v8
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v8, s3, v6
v_mad_u64_u32 v[4:5], null, s2, v6, 0
v_mul_lo_u32 v6, s2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v4, vcc_lo, v0, v4
v_add3_u32 v5, v5, v6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v6, v1, v5
v_subrev_co_ci_u32_e64 v6, s0, s3, v6, vcc_lo
v_sub_co_ci_u32_e32 v5, vcc_lo, v1, v5, vcc_lo
v_sub_co_u32 v7, vcc_lo, v4, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_subrev_co_ci_u32_e64 v8, s0, 0, v6, vcc_lo
v_cmp_le_u32_e64 s0, s2, v4
v_subrev_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s3, v5
v_cndmask_b32_e64 v9, 0, -1, s0
v_cmp_le_u32_e64 s0, s2, v7
v_cndmask_b32_e64 v12, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, s3, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v10, 0, -1, s0
v_cmp_le_u32_e64 s0, s3, v8
v_cndmask_b32_e64 v11, 0, -1, s0
v_cmp_eq_u32_e64 s0, s3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v10, v11, v10, vcc_lo
v_sub_co_u32 v11, vcc_lo, v7, s2
v_subrev_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v10
v_cndmask_b32_e64 v9, v12, v9, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v6, v8, v6 :: v_dual_cndmask_b32 v7, v7, v11
v_cmp_ne_u32_e32 vcc_lo, 0, v9
s_delay_alu instid0(VALU_DEP_2)
v_dual_cndmask_b32 v5, v5, v6 :: v_dual_cndmask_b32 v4, v4, v7
.LBB0_32:
s_and_not1_saveexec_b32 s0, s14
s_cbranch_execz .LBB0_27
v_cvt_f32_u32_e32 v4, s2
s_sub_i32 s14, 0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
v_cvt_u32_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, s14, v4
v_mul_hi_u32 v5, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v4, v5
v_mul_hi_u32 v4, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v4, s2
v_sub_nc_u32_e32 v4, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s2, v4
v_cmp_le_u32_e32 vcc_lo, s2, v4
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s2, v4
v_cmp_le_u32_e32 vcc_lo, s2, v4
v_dual_cndmask_b32 v4, v4, v5 :: v_dual_mov_b32 v5, 0
s_branch .LBB0_27
.LBB0_34:
s_or_b32 exec_lo, exec_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s0, s8, exec_lo
.LBB0_35:
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s0, s0, exec_lo
s_or_b32 s2, s1, exec_lo
.LBB0_36:
s_or_b32 exec_lo, exec_lo, s10
v_mov_b32_e32 v1, v2
v_mov_b32_e32 v2, v3
s_and_not1_b32 s1, s1, exec_lo
s_and_b32 s2, s2, exec_lo
s_and_b32 s0, s0, exec_lo
s_or_b32 s1, s1, s2
.LBB0_37:
s_or_b32 exec_lo, exec_lo, s9
.LBB0_38:
s_and_saveexec_b32 s2, s1
s_cbranch_execnz .LBB0_40
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_40:
v_add_co_u32 v0, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v2, vcc_lo
v_cndmask_b32_e64 v3, 0, -1, s0
global_load_u8 v2, v[0:1], off
v_and_b32_e32 v3, 0xff, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u16_e32 vcc_lo, v2, v3
v_cndmask_b32_e64 v2, 0, 1, vcc_lo
global_store_b8 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9calculatePxPbii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 23
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9calculatePxPbii, .Lfunc_end0-_Z9calculatePxPbii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9calculatePxPbii
.private_segment_fixed_size: 0
.sgpr_count: 25
.sgpr_spill_count: 0
.symbol: _Z9calculatePxPbii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <map>
#include <string>
#include <fstream>
#include <vector>
using namespace std;
#define ll long long
const int GRID_SIZE = 1;
// Use naive method
__device__ bool isPrime(ll n)
{
if(n<2)
return false;
for(ll i=2;i*i<=n;i++)
if(n%i==0)
return false;
return true;
}
// Read numbers from file and add to vector
std::vector<ll> readFile(char* arg){
vector<ll> numbersFromFile;
std::ifstream infile(arg);
ll number;
if(!infile.is_open()) {
throw std::invalid_argument("Problem with file");
}
while (infile >> number) {
numbersFromFile.push_back(number);
}
return numbersFromFile;
}
__global__ void calculate(ll *Arr, bool *results, int sizeOfArray, int amountOfBlocks){
int x = (blockIdx.x * blockDim.x) + threadIdx.x;
if (amountOfBlocks >= sizeOfArray){
results[x] += isPrime(Arr[x]);
} else{
int sizeOfPart = sizeOfArray / amountOfBlocks;
int restOfDivide = sizeOfArray%amountOfBlocks;
int startPart = sizeOfPart * x;
int endPart = sizeOfPart * (x + 1);
if (endPart <= sizeOfArray)
{
int restStart = sizeOfPart * amountOfBlocks;
for (int i = startPart; i < endPart; i++){
results[i] += isPrime(Arr[i]);
}
if (x < restOfDivide){
results[restStart + x] += isPrime(Arr[restStart + x]);
}
}
}
}
int main(int argc, char** argv )
{
float time;
if ( argc < 2 )
{
printf("Pass file path\n");
return -1;
}
vector<ll> numbersFromFile;
try {
numbersFromFile = readFile(argv[1]);
} catch ( const std::invalid_argument& ex ) {
cout << ex.what() << endl;
return -1;
}
int sizeOfArray = numbersFromFile.size();
int sizeToAllocateLongLong = sizeOfArray * sizeof(ll);
int sizeToAllocateBool = sizeOfArray * sizeof(bool);
ll numbersFromFileArr[sizeOfArray];
std::copy(numbersFromFile.begin(), numbersFromFile.end(), numbersFromFileArr);
bool* results = (bool *) malloc (sizeToAllocateBool);
ll* c_arr;
bool* c_results;
hipMalloc((void**) &c_arr, sizeToAllocateLongLong);
hipMalloc((void**) &c_results, sizeToAllocateBool);
hipMemcpy((void *)c_arr, (void *)numbersFromFileArr, sizeToAllocateLongLong, hipMemcpyHostToDevice);
//Start timer
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
int amountOfBlocks = sizeOfArray;
calculate<<<amountOfBlocks, GRID_SIZE>>>(c_arr, c_results, sizeOfArray, amountOfBlocks);
//End timer and put result into time variable
hipDeviceSynchronize();
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("Czas: %.4fms\n", time);
if (hipMemcpy((void *)results, (void *)c_results , sizeToAllocateBool, hipMemcpyDeviceToHost) != hipSuccess) {
cout<<"GPU to CPU copy error\n";
}
hipFree(c_arr);
hipFree(c_results);
for(int j = 0; j < sizeOfArray ; j++)
{
if (results[j]){
cout << numbersFromFileArr[j] << " prime" << endl;
} else {
cout << numbersFromFileArr[j] << " composite" << endl;
}
}
free(results);
return 0;
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z8readFilePc # -- Begin function _Z8readFilePc
.p2align 4, 0x90
.type _Z8readFilePc,@function
_Z8readFilePc: # @_Z8readFilePc
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $552, %rsp # imm = 0x228
.cfi_def_cfa_offset 608
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbp
xorps %xmm0, %xmm0
movups %xmm0, (%rdi)
movq $0, 16(%rdi)
.Ltmp0:
leaq 32(%rsp), %rdi
movl $8, %edx
movq %rbp, 8(%rsp) # 8-byte Spill
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
.Ltmp1:
# %bb.1:
leaq 152(%rsp), %rdi
callq _ZNKSt12__basic_fileIcE7is_openEv
testb %al, %al
je .LBB0_8
# %bb.2: # %.preheader
movq (%rbp), %r14
leaq 32(%rsp), %r15
leaq 16(%rsp), %r12
.LBB0_3: # %_ZNSt6vectorIxSaIxEE9push_backERKx.exit.outer
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
movq 8(%rbp), %rbx
movq 16(%rbp), %r13
movq %r14, (%rsp) # 8-byte Spill
subq %rbx, %r14
.p2align 4, 0x90
.LBB0_4: # %_ZNSt6vectorIxSaIxEE9push_backERKx.exit
# Parent Loop BB0_3 Depth=1
# => This Inner Loop Header: Depth=2
.Ltmp8:
movq %r15, %rdi
movq %r12, %rsi
callq _ZNSi10_M_extractIxEERSiRT_
.Ltmp9:
# %bb.5: # %_ZNSirsERx.exit
# in Loop: Header=BB0_4 Depth=2
movq (%rax), %rcx
movq -24(%rcx), %rcx
testb $5, 32(%rax,%rcx)
jne .LBB0_26
# %bb.6: # in Loop: Header=BB0_4 Depth=2
cmpq %r13, %rbx
je .LBB0_14
# %bb.7: # in Loop: Header=BB0_4 Depth=2
movq 16(%rsp), %rax
movq %rax, (%rbx)
addq $8, %rbx
addq $-8, %r14
jmp .LBB0_4
.p2align 4, 0x90
.LBB0_14: # in Loop: Header=BB0_3 Depth=1
movq %rbx, 8(%rbp)
movabsq $-9223372036854775800, %rax # imm = 0x8000000000000008
cmpq %rax, %r14
je .LBB0_15
# %bb.17: # %_ZNKSt6vectorIxSaIxEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB0_3 Depth=1
movq %r14, %rdx
negq %rdx
movq %rdx, %r13
sarq $3, %r13
cmpq $1, %r13
movq %r13, %rax
adcq $0, %rax
leaq (%rax,%r13), %rbx
movabsq $1152921504606846975, %rcx # imm = 0xFFFFFFFFFFFFFFF
cmpq %rcx, %rbx
cmovaeq %rcx, %rbx
addq %r13, %rax
cmovbq %rcx, %rbx
testq %rbx, %rbx
je .LBB0_18
# %bb.19: # in Loop: Header=BB0_3 Depth=1
movq %rdx, 24(%rsp) # 8-byte Spill
leaq (,%rbx,8), %rdi
.Ltmp11:
callq _Znwm
.Ltmp12:
# %bb.20: # in Loop: Header=BB0_3 Depth=1
movq %rax, %rbp
movq 24(%rsp), %rdx # 8-byte Reload
jmp .LBB0_21
.LBB0_18: # in Loop: Header=BB0_3 Depth=1
xorl %ebp, %ebp
.LBB0_21: # %_ZNSt12_Vector_baseIxSaIxEE11_M_allocateEm.exit.i.i
# in Loop: Header=BB0_3 Depth=1
movq 16(%rsp), %rax
movq %rax, (%rbp,%r13,8)
testq %rdx, %rdx
movq (%rsp), %r13 # 8-byte Reload
jle .LBB0_23
# %bb.22: # in Loop: Header=BB0_3 Depth=1
movq %rbp, %rdi
movq %r13, %rsi
callq memmove@PLT
.LBB0_23: # %_ZNSt6vectorIxSaIxEE11_S_relocateEPxS2_S2_RS0_.exit.i.i
# in Loop: Header=BB0_3 Depth=1
testq %r13, %r13
je .LBB0_25
# %bb.24: # in Loop: Header=BB0_3 Depth=1
movq %r13, %rdi
callq _ZdlPv
.LBB0_25: # %_ZNSt6vectorIxSaIxEE17_M_realloc_insertIJRKxEEEvN9__gnu_cxx17__normal_iteratorIPxS1_EEDpOT_.exit.i
# in Loop: Header=BB0_3 Depth=1
movq %rbp, %rax
subq %r14, %rax
addq $8, %rax
movq 8(%rsp), %rcx # 8-byte Reload
movq %rax, 8(%rcx)
leaq (,%rbx,8), %rax
addq %rbp, %rax
movq %rax, 16(%rcx)
movq %rbp, %r14
movq %rcx, %rbp
jmp .LBB0_3
.LBB0_26:
movq %rbx, 8(%rbp)
movq (%rsp), %rax # 8-byte Reload
movq %rax, (%rbp)
leaq 32(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 288(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
movq %rbp, %rax
addq $552, %rsp # imm = 0x228
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_8:
.cfi_def_cfa_offset 608
movl $16, %edi
callq __cxa_allocate_exception
movq %rax, %r14
.Ltmp3:
movl $.L.str, %esi
movq %rax, %rdi
callq _ZNSt16invalid_argumentC1EPKc
.Ltmp4:
# %bb.9:
.Ltmp6:
movl $_ZTISt16invalid_argument, %esi
movl $_ZNSt16invalid_argumentD1Ev, %edx
movq %r14, %rdi
callq __cxa_throw
.Ltmp7:
# %bb.32:
.LBB0_15:
movq (%rsp), %rax # 8-byte Reload
movq %rax, (%rbp)
.Ltmp14:
movl $.L.str.6, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp15:
# %bb.16: # %.noexc
.LBB0_13:
.Ltmp5:
movq %rax, %r15
movq %r14, %rdi
callq __cxa_free_exception
jmp .LBB0_28
.LBB0_11: # %.loopexit.loopexit.split-lp
.Ltmp13:
movq %rax, %r15
movq 8(%rsp), %rax # 8-byte Reload
movq (%rsp), %rcx # 8-byte Reload
movq %rcx, (%rax)
jmp .LBB0_28
.LBB0_10:
.Ltmp2:
movq %rax, %r15
jmp .LBB0_29
.LBB0_12: # %.loopexit.split-lp
.Ltmp16:
movq %rax, %r15
jmp .LBB0_28
.LBB0_27: # %.loopexit.loopexit
.Ltmp10:
movq %rax, %r15
movq %rbx, 8(%rbp)
movq (%rsp), %rax # 8-byte Reload
movq %rax, (%rbp)
.LBB0_28:
leaq 32(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 288(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
.LBB0_29:
movq 8(%rsp), %rax # 8-byte Reload
movq (%rax), %rdi
testq %rdi, %rdi
je .LBB0_31
# %bb.30:
callq _ZdlPv
.LBB0_31: # %_ZNSt6vectorIxSaIxEED2Ev.exit
movq %r15, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size _Z8readFilePc, .Lfunc_end0-_Z8readFilePc
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp8-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp9-.Ltmp8 # Call between .Ltmp8 and .Ltmp9
.uleb128 .Ltmp10-.Lfunc_begin0 # jumps to .Ltmp10
.byte 0 # On action: cleanup
.uleb128 .Ltmp11-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp12-.Ltmp11 # Call between .Ltmp11 and .Ltmp12
.uleb128 .Ltmp13-.Lfunc_begin0 # jumps to .Ltmp13
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp3-.Ltmp12 # Call between .Ltmp12 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp15-.Ltmp6 # Call between .Ltmp6 and .Ltmp15
.uleb128 .Ltmp16-.Lfunc_begin0 # jumps to .Ltmp16
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Lfunc_end0-.Ltmp15 # Call between .Ltmp15 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.globl _Z24__device_stub__calculatePxPbii # -- Begin function _Z24__device_stub__calculatePxPbii
.p2align 4, 0x90
.type _Z24__device_stub__calculatePxPbii,@function
_Z24__device_stub__calculatePxPbii: # @_Z24__device_stub__calculatePxPbii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9calculatePxPbii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z24__device_stub__calculatePxPbii, .Lfunc_end1-_Z24__device_stub__calculatePxPbii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $184, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
cmpl $1, %edi
jg .LBB2_2
# %bb.1:
.cfi_escape 0x2e, 0x00
movl $.Lstr, %edi
callq puts@PLT
movl $-1, %eax
jmp .LBB2_54
.LBB2_2:
movq 8(%rsi), %rsi
.Ltmp17:
.cfi_escape 0x2e, 0x00
leaq -144(%rbp), %rdi
callq _Z8readFilePc
.Ltmp18:
# %bb.3: # %_ZNSt6vectorIxSaIxEEaSEOS1_.exit
movq %rsp, %r15
movq -144(%rbp), %rbx
movq -136(%rbp), %r12
subq %rbx, %r12
movq %r12, %rax
shrq $3, %rax
movslq %eax, %r13
movabsq $34359738360, %rax # imm = 0x7FFFFFFF8
andq %r12, %rax
addq $15, %rax
andq $-16, %rax
.cfi_escape 0x2e, 0x00
movq %rsp, %r14
subq %rax, %r14
movq %r14, %rsp
cmpq $9, %r12
jl .LBB2_5
# %bb.4:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movq %rbx, %rsi
movq %r12, %rdx
callq memmove@PLT
.LBB2_7: # %_ZSt4copyIN9__gnu_cxx17__normal_iteratorIPxSt6vectorIxSaIxEEEES2_ET0_T_S8_S7_.exit
movq %rbx, -48(%rbp) # 8-byte Spill
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq malloc
movq %rax, -56(%rbp) # 8-byte Spill
movslq %r12d, %rbx
.Ltmp31:
.cfi_escape 0x2e, 0x00
leaq -80(%rbp), %rdi
movq %rbx, %rsi
callq hipMalloc
.Ltmp32:
# %bb.8:
.Ltmp33:
.cfi_escape 0x2e, 0x00
leaq -72(%rbp), %rdi
movq %r13, %rsi
callq hipMalloc
.Ltmp34:
# %bb.9:
movq -80(%rbp), %rdi
.Ltmp35:
.cfi_escape 0x2e, 0x00
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
.Ltmp36:
# %bb.10:
.Ltmp38:
movq %r15, -152(%rbp) # 8-byte Spill
.cfi_escape 0x2e, 0x00
leaq -104(%rbp), %rdi
callq hipEventCreate
.Ltmp39:
# %bb.11:
.Ltmp40:
.cfi_escape 0x2e, 0x00
leaq -64(%rbp), %rdi
callq hipEventCreate
.Ltmp41:
# %bb.12:
movq -104(%rbp), %rdi
.Ltmp42:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp43:
# %bb.13:
sarq $3, %r12
movl %r12d, %eax
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rax, %rdi
.Ltmp45:
.cfi_escape 0x2e, 0x00
movabsq $4294967297, %rdx # imm = 0x100000001
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp46:
# %bb.14:
testl %eax, %eax
jne .LBB2_17
# %bb.15:
movq -80(%rbp), %rax
movq -72(%rbp), %rcx
movq %rax, -216(%rbp)
movq %rcx, -208(%rbp)
movl %r12d, -92(%rbp)
movl %r12d, -88(%rbp)
leaq -216(%rbp), %rax
movq %rax, -144(%rbp)
leaq -208(%rbp), %rax
movq %rax, -136(%rbp)
leaq -92(%rbp), %rax
movq %rax, -128(%rbp)
leaq -88(%rbp), %rax
movq %rax, -120(%rbp)
.Ltmp47:
.cfi_escape 0x2e, 0x00
leaq -200(%rbp), %rdi
leaq -184(%rbp), %rsi
leaq -168(%rbp), %rdx
leaq -160(%rbp), %rcx
callq __hipPopCallConfiguration
.Ltmp48:
# %bb.16: # %.noexc
movq -200(%rbp), %rsi
movl -192(%rbp), %edx
movq -184(%rbp), %rcx
movl -176(%rbp), %r8d
.Ltmp49:
.cfi_escape 0x2e, 0x10
leaq -144(%rbp), %r9
movl $_Z9calculatePxPbii, %edi
pushq -160(%rbp)
pushq -168(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.Ltmp50:
.LBB2_17:
.Ltmp51:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp52:
# %bb.18:
movq -64(%rbp), %rdi
.Ltmp53:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp54:
# %bb.19:
movq -64(%rbp), %rdi
.Ltmp55:
.cfi_escape 0x2e, 0x00
callq hipEventSynchronize
.Ltmp56:
# %bb.20:
movq -104(%rbp), %rsi
movq -64(%rbp), %rdx
.Ltmp57:
.cfi_escape 0x2e, 0x00
leaq -84(%rbp), %rdi
callq hipEventElapsedTime
.Ltmp58:
# %bb.21:
movss -84(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq -72(%rbp), %rsi
.Ltmp59:
.cfi_escape 0x2e, 0x00
movq -56(%rbp), %rdi # 8-byte Reload
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
.Ltmp60:
# %bb.22:
testl %eax, %eax
je .LBB2_24
# %bb.23:
.Ltmp61:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp62:
.LBB2_24: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq -80(%rbp), %rdi
.Ltmp63:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp64:
# %bb.25:
movq -72(%rbp), %rdi
.Ltmp65:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp66:
# %bb.26: # %.preheader
testl %r12d, %r12d
jle .LBB2_51
# %bb.27: # %.lr.ph.preheader
movl %r12d, %ebx
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_28: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq -56(%rbp), %rax # 8-byte Reload
cmpb $0, (%rax,%r15)
movq (%r14,%r15,8), %rsi
je .LBB2_57
# %bb.29: # in Loop: Header=BB2_28 Depth=1
.Ltmp68:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIxEERSoT_
.Ltmp69:
# %bb.30: # %_ZNSolsEx.exit
# in Loop: Header=BB2_28 Depth=1
.Ltmp70:
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movl $.L.str.4, %esi
movl $6, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp71:
# %bb.31: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit56
# in Loop: Header=BB2_28 Depth=1
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB2_32
# %bb.44: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB2_28 Depth=1
cmpb $0, 56(%r13)
jne .LBB2_47
# %bb.45: # in Loop: Header=BB2_28 Depth=1
.Ltmp72:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp73:
# %bb.46: # %.noexc71
# in Loop: Header=BB2_28 Depth=1
movq (%r13), %rax
.Ltmp74:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp75:
jmp .LBB2_48
.p2align 4, 0x90
.LBB2_57: # in Loop: Header=BB2_28 Depth=1
.Ltmp76:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIxEERSoT_
.Ltmp77:
# %bb.58: # %_ZNSolsEx.exit60
# in Loop: Header=BB2_28 Depth=1
.Ltmp78:
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movl $.L.str.5, %esi
movl $10, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp79:
# %bb.59: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit62
# in Loop: Header=BB2_28 Depth=1
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB2_32
# %bb.60: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i76
# in Loop: Header=BB2_28 Depth=1
cmpb $0, 56(%r13)
je .LBB2_61
.LBB2_47: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i.invoke.sink.split
# in Loop: Header=BB2_28 Depth=1
movzbl 67(%r13), %eax
.LBB2_48: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i.invoke
# in Loop: Header=BB2_28 Depth=1
.Ltmp84:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
.Ltmp85:
# %bb.49: # %.noexc73.invoke
# in Loop: Header=BB2_28 Depth=1
.Ltmp86:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp87:
# %bb.50: # %_ZNSolsEPFRSoS_E.exit58
# in Loop: Header=BB2_28 Depth=1
incq %r15
cmpq %r15, %rbx
jne .LBB2_28
jmp .LBB2_51
.LBB2_61: # in Loop: Header=BB2_28 Depth=1
.Ltmp80:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp81:
# %bb.62: # %.noexc81
# in Loop: Header=BB2_28 Depth=1
movq (%r13), %rax
.Ltmp82:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp83:
jmp .LBB2_48
.LBB2_51: # %._crit_edge
.cfi_escape 0x2e, 0x00
movq -56(%rbp), %rdi # 8-byte Reload
callq free
xorl %eax, %eax
movq -152(%rbp), %rsp # 8-byte Reload
.LBB2_52:
movq -48(%rbp), %rdi # 8-byte Reload
testq %rdi, %rdi
je .LBB2_54
# %bb.53:
.cfi_escape 0x2e, 0x00
movl %eax, %ebx
callq _ZdlPv
movl %ebx, %eax
.LBB2_54: # %_ZNSt6vectorIxSaIxEED2Ev.exit66
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB2_5:
.cfi_def_cfa %rbp, 16
cmpq $8, %r12
jne .LBB2_7
# %bb.6:
movq (%rbx), %rax
movq %rax, (%r14)
jmp .LBB2_7
.LBB2_32: # %.invoke
.Ltmp89:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp90:
# %bb.43: # %.cont
.LBB2_33:
.Ltmp19:
movq %rax, %r14
cmpl $1, %edx
jne .LBB2_34
# %bb.35:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq __cxa_begin_catch
movq (%rax), %rcx
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq *16(%rcx)
.Ltmp20:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
.Ltmp21:
# %bb.36:
.Ltmp22:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
.Ltmp23:
# %bb.37: # %_ZNSolsEPFRSoS_E.exit
.Ltmp28:
.cfi_escape 0x2e, 0x00
callq __cxa_end_catch
.Ltmp29:
# %bb.38:
movl $-1, %eax
xorl %ecx, %ecx
movq %rcx, -48(%rbp) # 8-byte Spill
jmp .LBB2_52
.LBB2_40:
.Ltmp30:
movq %rax, %r14
jmp .LBB2_34
.LBB2_39:
.Ltmp24:
movq %rax, %r14
.Ltmp25:
.cfi_escape 0x2e, 0x00
callq __cxa_end_catch
.Ltmp26:
.LBB2_34:
xorl %eax, %eax
movq %rax, -48(%rbp) # 8-byte Spill
jmp .LBB2_65
.LBB2_68:
.Ltmp27:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq __clang_call_terminate
.LBB2_41:
.Ltmp44:
jmp .LBB2_64
.LBB2_63:
.Ltmp37:
jmp .LBB2_64
.LBB2_42:
.Ltmp67:
jmp .LBB2_64
.LBB2_56: # %.loopexit.split-lp
.Ltmp91:
jmp .LBB2_64
.LBB2_55: # %.loopexit
.Ltmp88:
.LBB2_64:
movq %rax, %r14
.LBB2_65:
cmpq $0, -48(%rbp) # 8-byte Folded Reload
je .LBB2_67
# %bb.66:
.cfi_escape 0x2e, 0x00
movq -48(%rbp), %rdi # 8-byte Reload
callq _ZdlPv
.LBB2_67: # %_ZNSt6vectorIxSaIxEED2Ev.exit68
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Ltmp17-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp18-.Ltmp17 # Call between .Ltmp17 and .Ltmp18
.uleb128 .Ltmp19-.Lfunc_begin1 # jumps to .Ltmp19
.byte 3 # On action: 2
.uleb128 .Ltmp18-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Ltmp31-.Ltmp18 # Call between .Ltmp18 and .Ltmp31
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp31-.Lfunc_begin1 # >> Call Site 3 <<
.uleb128 .Ltmp36-.Ltmp31 # Call between .Ltmp31 and .Ltmp36
.uleb128 .Ltmp37-.Lfunc_begin1 # jumps to .Ltmp37
.byte 0 # On action: cleanup
.uleb128 .Ltmp38-.Lfunc_begin1 # >> Call Site 4 <<
.uleb128 .Ltmp43-.Ltmp38 # Call between .Ltmp38 and .Ltmp43
.uleb128 .Ltmp44-.Lfunc_begin1 # jumps to .Ltmp44
.byte 0 # On action: cleanup
.uleb128 .Ltmp45-.Lfunc_begin1 # >> Call Site 5 <<
.uleb128 .Ltmp66-.Ltmp45 # Call between .Ltmp45 and .Ltmp66
.uleb128 .Ltmp67-.Lfunc_begin1 # jumps to .Ltmp67
.byte 0 # On action: cleanup
.uleb128 .Ltmp68-.Lfunc_begin1 # >> Call Site 6 <<
.uleb128 .Ltmp83-.Ltmp68 # Call between .Ltmp68 and .Ltmp83
.uleb128 .Ltmp88-.Lfunc_begin1 # jumps to .Ltmp88
.byte 0 # On action: cleanup
.uleb128 .Ltmp89-.Lfunc_begin1 # >> Call Site 7 <<
.uleb128 .Ltmp90-.Ltmp89 # Call between .Ltmp89 and .Ltmp90
.uleb128 .Ltmp91-.Lfunc_begin1 # jumps to .Ltmp91
.byte 0 # On action: cleanup
.uleb128 .Ltmp90-.Lfunc_begin1 # >> Call Site 8 <<
.uleb128 .Ltmp20-.Ltmp90 # Call between .Ltmp90 and .Ltmp20
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp20-.Lfunc_begin1 # >> Call Site 9 <<
.uleb128 .Ltmp23-.Ltmp20 # Call between .Ltmp20 and .Ltmp23
.uleb128 .Ltmp24-.Lfunc_begin1 # jumps to .Ltmp24
.byte 0 # On action: cleanup
.uleb128 .Ltmp28-.Lfunc_begin1 # >> Call Site 10 <<
.uleb128 .Ltmp29-.Ltmp28 # Call between .Ltmp28 and .Ltmp29
.uleb128 .Ltmp30-.Lfunc_begin1 # jumps to .Ltmp30
.byte 0 # On action: cleanup
.uleb128 .Ltmp25-.Lfunc_begin1 # >> Call Site 11 <<
.uleb128 .Ltmp26-.Ltmp25 # Call between .Ltmp25 and .Ltmp26
.uleb128 .Ltmp27-.Lfunc_begin1 # jumps to .Ltmp27
.byte 5 # On action: 3
.uleb128 .Ltmp26-.Lfunc_begin1 # >> Call Site 12 <<
.uleb128 .Lfunc_end2-.Ltmp26 # Call between .Ltmp26 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.byte 0 # >> Action Record 1 <<
# Cleanup
.byte 0 # No further actions
.byte 1 # >> Action Record 2 <<
# Catch TypeInfo 1
.byte 125 # Continue to action 1
.byte 2 # >> Action Record 3 <<
# Catch TypeInfo 2
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 2
.long _ZTISt16invalid_argument # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.section .text.__clang_call_terminate,"axG",@progbits,__clang_call_terminate,comdat
.hidden __clang_call_terminate # -- Begin function __clang_call_terminate
.weak __clang_call_terminate
.p2align 4, 0x90
.type __clang_call_terminate,@function
__clang_call_terminate: # @__clang_call_terminate
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq __cxa_begin_catch
callq _ZSt9terminatev
.Lfunc_end3:
.size __clang_call_terminate, .Lfunc_end3-__clang_call_terminate
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9calculatePxPbii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Problem with file"
.size .L.str, 18
.type _Z9calculatePxPbii,@object # @_Z9calculatePxPbii
.section .rodata,"a",@progbits
.globl _Z9calculatePxPbii
.p2align 3, 0x0
_Z9calculatePxPbii:
.quad _Z24__device_stub__calculatePxPbii
.size _Z9calculatePxPbii, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Czas: %.4fms\n"
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "GPU to CPU copy error\n"
.size .L.str.3, 23
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " prime"
.size .L.str.4, 7
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " composite"
.size .L.str.5, 11
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "vector::_M_realloc_insert"
.size .L.str.6, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9calculatePxPbii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Pass file path"
.size .Lstr, 15
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Z24__device_stub__calculatePxPbii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZTISt16invalid_argument
.addrsig_sym _Z9calculatePxPbii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
//CUDA RunTime API
#include <cuda_runtime.h>
//1M
#define DATA_SIZE 1048576
#define THREAD_NUM 256
#define BLOCK_NUM 32
#define NUM_THREADS 256
__global__ static void matMultCUDA(const float* a, size_t lda,
const float* b, size_t ldb, float* c, size_t ldc, int n)
{
extern __shared__ float data[];
const int tid = threadIdx.x;
const int row = blockIdx.x;
int i, j;
for(i = tid; i < n; i += blockDim.x) {
data[i] = a[row * lda + i];
}
__syncthreads();
for(j = tid; j < n; j += blockDim.x) {
float t = 0;
float y = 0;
for(i = 0; i < n; i++) {
float r;
y -= data[i] * b[i * ldb + j];
r = t - y;
y = (r - t) + y;
t = r;
}
c[row * ldc + j] = t;
}
}
clock_t matmultCUDA(const float* a, int lda,
const float* b, int ldb, float* c, int ldc, int n)
{
float *ac, *bc, *cc;
clock_t start, end;
start = clock();
cudaMalloc((void**) &ac, sizeof(float) * n * n);
cudaMalloc((void**) &bc, sizeof(float) * n * n);
cudaMalloc((void**) &cc, sizeof(float) * n * n);
cudaMemcpy(ac, a,
sizeof(float) * n * n, cudaMemcpyHostToDevice);
cudaMemcpy(bc, b,
sizeof(float) * n * n, cudaMemcpyHostToDevice);
int blocks = (n + NUM_THREADS - 1) / NUM_THREADS;
matMultCUDA<<< n, NUM_THREADS, sizeof(float) * n>>>
(ac, n, bc, n, cc, n, n);
cudaMemcpy(c, cc,
sizeof(float) * n * n, cudaMemcpyDeviceToHost);
cudaFree(ac);
cudaFree(bc);
cudaFree(cc);
end = clock();
return end - start;
}
void compare_mat(const float* a, int lda,
const float* b, int ldb, int n)
{
float max_err = 0;
float average_err = 0;
int i, j;
for(i = 0; i < n; i++) {
for(j = 0; j < n; j++) {
if(b[i * ldb + j] != 0) {
float err = fabs((a[i * lda + j] -
b[i * ldb + j]) / b[i * ldb + j]);
if(max_err < err) max_err = err;
average_err += err;
} }
}
printf("Max error: %g Average error: %g\n",
max_err, average_err / (n * n));
}
void matmult(const float* a, int lda, const float* b, int ldb,
float* c, int ldc, int n)
{
int i, j, k;
for(i = 0; i < n; i++) {
for(j = 0; j < n; j++) {
double t = 0;
for(k = 0; k < n; k++) {
t += a[i * lda + k] * b[k * ldb + j];
}
c[i * ldc + j] = t;
}
} }
void matgen(float* a, int lda, int n)
{
int i, j;
for(i = 0; i < n; i++) {
for(j = 0; j < n; j++) {
a[i * lda + j] = (float) rand() / RAND_MAX +
(float) rand() / (RAND_MAX * RAND_MAX);
} }
}
int main() {
float *a, *b, *c, *d;
int n = 1000;
a = (float*) malloc(sizeof(float) * n * n);
b = (float*) malloc(sizeof(float) * n * n);
c = (float*) malloc(sizeof(float) * n * n);
d = (float*) malloc(sizeof(float) * n * n);
srand(0);
matgen(a, n, n);
matgen(b, n, n);
clock_t time = matmultCUDA(a, n, b, n, c, n, n);
matmult(a, n, b, n, d, n, n);
compare_mat(c, n, d, n, n);
double sec = (double) time / CLOCKS_PER_SEC;
printf("Time used: %.2f (%.2lf GFLOPS)\n", sec,
2.0 * n * n * n / (sec * 1E9));
return 0;
} | .file "tmpxft_000462d4_00000000-6_cudasucess.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL41__device_stub__Z11matMultCUDAPKfmS0_mPfmiPKfmS0_mPfmi, @function
_ZL41__device_stub__Z11matMultCUDAPKfmS0_mPfmiPKfmS0_mPfmi:
.LFB2086:
.cfi_startproc
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _ZL11matMultCUDAPKfmS0_mPfmi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _ZL41__device_stub__Z11matMultCUDAPKfmS0_mPfmiPKfmS0_mPfmi, .-_ZL41__device_stub__Z11matMultCUDAPKfmS0_mPfmiPKfmS0_mPfmi
.type _ZL11matMultCUDAPKfmS0_mPfmi, @function
_ZL11matMultCUDAPKfmS0_mPfmi:
.LFB2087:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _ZL41__device_stub__Z11matMultCUDAPKfmS0_mPfmiPKfmS0_mPfmi
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL11matMultCUDAPKfmS0_mPfmi, .-_ZL11matMultCUDAPKfmS0_mPfmi
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11matmultCUDAPKfiS0_iPfii
.type _Z11matmultCUDAPKfiS0_iPfii, @function
_Z11matmultCUDAPKfiS0_iPfii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %r14
movq %rdx, %r13
movq %r8, 8(%rsp)
movl 144(%rsp), %r15d
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
call clock@PLT
movq %rax, %r12
movslq %r15d, %rbp
movq %rbp, %rbx
imulq %rbp, %rbx
salq $2, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl %r15d, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
leaq 0(,%rbp,4), %r8
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
call clock@PLT
subq %r12, %rax
movq 72(%rsp), %rdx
subq %fs:40, %rdx
jne .L16
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 152
pushq %r15
.cfi_def_cfa_offset 160
movq %rbp, %r9
movq 56(%rsp), %r8
movq %rbp, %rcx
movq 48(%rsp), %rdx
movq %rbp, %rsi
movq 40(%rsp), %rdi
call _ZL41__device_stub__Z11matMultCUDAPKfmS0_mPfmiPKfmS0_mPfmi
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z11matmultCUDAPKfiS0_iPfii, .-_Z11matmultCUDAPKfiS0_iPfii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Max error: %g Average error: %g\n"
.text
.globl _Z11compare_matPKfiS0_ii
.type _Z11compare_matPKfiS0_ii, @function
_Z11compare_matPKfiS0_ii:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
testl %r8d, %r8d
jle .L24
movq %rdi, %r9
movl %esi, %r10d
movl %r8d, %esi
movslq %ecx, %rcx
leaq 0(,%rcx,4), %rbx
movl $0, %ebp
movl $0, %r11d
pxor %xmm1, %xmm1
movaps %xmm1, %xmm4
movaps %xmm1, %xmm3
movss .LC1(%rip), %xmm5
jmp .L19
.L26:
movslq %eax, %rdi
movss (%r9,%rdi,4), %xmm0
subss %xmm2, %xmm0
divss %xmm2, %xmm0
andps %xmm5, %xmm0
movaps %xmm0, %xmm6
maxss %xmm4, %xmm6
movaps %xmm6, %xmm4
addss %xmm0, %xmm1
.L20:
addq $4, %rcx
addl $1, %eax
cmpl %eax, %esi
je .L29
.L23:
movss (%rcx), %xmm2
ucomiss %xmm3, %xmm2
jp .L26
je .L20
jmp .L26
.L29:
addl $1, %r11d
addl %r10d, %esi
addq %rbx, %rdx
addl %r10d, %ebp
cmpl %r11d, %r8d
je .L18
.L19:
movl %ebp, %eax
movq %rdx, %rcx
jmp .L23
.L24:
pxor %xmm1, %xmm1
movaps %xmm1, %xmm4
.L18:
imull %r8d, %r8d
pxor %xmm0, %xmm0
cvtsi2ssl %r8d, %xmm0
divss %xmm0, %xmm1
pxor %xmm0, %xmm0
cvtss2sd %xmm4, %xmm0
cvtss2sd %xmm1, %xmm1
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z11compare_matPKfiS0_ii, .-_Z11compare_matPKfiS0_ii
.globl _Z7matmultPKfiS0_iPfii
.type _Z7matmultPKfiS0_iPfii, @function
_Z7matmultPKfiS0_iPfii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl 48(%rsp), %r12d
testl %r12d, %r12d
jle .L30
movq %rdx, %r11
movl %ecx, %eax
movslq %r9d, %rbp
salq $2, %rbp
movslq %esi, %rsi
leaq 0(,%rsi,4), %rbx
movq %rdi, %r9
movslq %r12d, %r10
leaq (%rdi,%r10,4), %rcx
cltq
leaq 0(,%rax,4), %rsi
movl $0, %r14d
.L32:
movq %r11, %r13
movl $0, %edi
.L35:
movq %r13, %rdx
movq %r9, %rax
pxor %xmm1, %xmm1
.L33:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
cvtss2sd %xmm0, %xmm0
addsd %xmm0, %xmm1
addq $4, %rax
addq %rsi, %rdx
cmpq %rcx, %rax
jne .L33
cvtsd2ss %xmm1, %xmm1
movss %xmm1, (%r8,%rdi,4)
addq $1, %rdi
addq $4, %r13
cmpq %r10, %rdi
jne .L35
addl $1, %r14d
addq %rbp, %r8
addq %rbx, %r9
addq %rbx, %rcx
cmpl %r14d, %r12d
jne .L32
.L30:
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z7matmultPKfiS0_iPfii, .-_Z7matmultPKfiS0_iPfii
.globl _Z6matgenPfii
.type _Z6matgenPfii, @function
_Z6matgenPfii:
.LFB2060:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L44
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %edx, %r15d
movslq %esi, %rsi
leaq 0(,%rsi,4), %r13
movslq %edx, %r14
leaq (%rdi,%r14,4), %rbp
negq %r14
salq $2, %r14
movl $0, %r12d
.L40:
leaq 0(%rbp,%r14), %rbx
.L41:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC4(%rip), %xmm0
movss %xmm0, 12(%rsp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
addss 12(%rsp), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L41
addl $1, %r12d
addq %r13, %rbp
cmpl %r12d, %r15d
jne .L40
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2060:
.size _Z6matgenPfii, .-_Z6matgenPfii
.section .rodata.str1.8
.align 8
.LC8:
.string "Time used: %.2f (%.2lf GFLOPS)\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl $4000000, %edi
call malloc@PLT
movq %rax, %rbx
movl $4000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $4000000, %edi
call malloc@PLT
movq %rax, %r12
movl $4000000, %edi
call malloc@PLT
movq %rax, %r13
movl $0, %edi
call srand@PLT
movl $1000, %edx
movl $1000, %esi
movq %rbx, %rdi
call _Z6matgenPfii
movl $1000, %edx
movl $1000, %esi
movq %rbp, %rdi
call _Z6matgenPfii
subq $8, %rsp
.cfi_def_cfa_offset 56
pushq $1000
.cfi_def_cfa_offset 64
movl $1000, %r9d
movq %r12, %r8
movl $1000, %ecx
movq %rbp, %rdx
movl $1000, %esi
movq %rbx, %rdi
call _Z11matmultCUDAPKfiS0_iPfii
movq %rax, %r14
movl $1000, (%rsp)
movl $1000, %r9d
movq %r13, %r8
movl $1000, %ecx
movq %rbp, %rdx
movl $1000, %esi
movq %rbx, %rdi
call _Z7matmultPKfiS0_iPfii
addq $16, %rsp
.cfi_def_cfa_offset 48
movl $1000, %r8d
movl $1000, %ecx
movq %r13, %rdx
movl $1000, %esi
movq %r12, %rdi
call _Z11compare_matPKfiS0_ii
pxor %xmm0, %xmm0
cvtsi2sdq %r14, %xmm0
divsd .LC5(%rip), %xmm0
movapd %xmm0, %xmm2
mulsd .LC6(%rip), %xmm2
movsd .LC7(%rip), %xmm1
divsd %xmm2, %xmm1
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC9:
.string "_Z11matMultCUDAPKfmS0_mPfmi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL11matMultCUDAPKfmS0_mPfmi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC1:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 805306368
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1093567616
.align 8
.LC6:
.long 0
.long 1104006501
.align 8
.LC7:
.long 0
.long 1105055077
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
//CUDA RunTime API
#include <cuda_runtime.h>
//1M
#define DATA_SIZE 1048576
#define THREAD_NUM 256
#define BLOCK_NUM 32
#define NUM_THREADS 256
__global__ static void matMultCUDA(const float* a, size_t lda,
const float* b, size_t ldb, float* c, size_t ldc, int n)
{
extern __shared__ float data[];
const int tid = threadIdx.x;
const int row = blockIdx.x;
int i, j;
for(i = tid; i < n; i += blockDim.x) {
data[i] = a[row * lda + i];
}
__syncthreads();
for(j = tid; j < n; j += blockDim.x) {
float t = 0;
float y = 0;
for(i = 0; i < n; i++) {
float r;
y -= data[i] * b[i * ldb + j];
r = t - y;
y = (r - t) + y;
t = r;
}
c[row * ldc + j] = t;
}
}
clock_t matmultCUDA(const float* a, int lda,
const float* b, int ldb, float* c, int ldc, int n)
{
float *ac, *bc, *cc;
clock_t start, end;
start = clock();
cudaMalloc((void**) &ac, sizeof(float) * n * n);
cudaMalloc((void**) &bc, sizeof(float) * n * n);
cudaMalloc((void**) &cc, sizeof(float) * n * n);
cudaMemcpy(ac, a,
sizeof(float) * n * n, cudaMemcpyHostToDevice);
cudaMemcpy(bc, b,
sizeof(float) * n * n, cudaMemcpyHostToDevice);
int blocks = (n + NUM_THREADS - 1) / NUM_THREADS;
matMultCUDA<<< n, NUM_THREADS, sizeof(float) * n>>>
(ac, n, bc, n, cc, n, n);
cudaMemcpy(c, cc,
sizeof(float) * n * n, cudaMemcpyDeviceToHost);
cudaFree(ac);
cudaFree(bc);
cudaFree(cc);
end = clock();
return end - start;
}
void compare_mat(const float* a, int lda,
const float* b, int ldb, int n)
{
float max_err = 0;
float average_err = 0;
int i, j;
for(i = 0; i < n; i++) {
for(j = 0; j < n; j++) {
if(b[i * ldb + j] != 0) {
float err = fabs((a[i * lda + j] -
b[i * ldb + j]) / b[i * ldb + j]);
if(max_err < err) max_err = err;
average_err += err;
} }
}
printf("Max error: %g Average error: %g\n",
max_err, average_err / (n * n));
}
void matmult(const float* a, int lda, const float* b, int ldb,
float* c, int ldc, int n)
{
int i, j, k;
for(i = 0; i < n; i++) {
for(j = 0; j < n; j++) {
double t = 0;
for(k = 0; k < n; k++) {
t += a[i * lda + k] * b[k * ldb + j];
}
c[i * ldc + j] = t;
}
} }
void matgen(float* a, int lda, int n)
{
int i, j;
for(i = 0; i < n; i++) {
for(j = 0; j < n; j++) {
a[i * lda + j] = (float) rand() / RAND_MAX +
(float) rand() / (RAND_MAX * RAND_MAX);
} }
}
int main() {
float *a, *b, *c, *d;
int n = 1000;
a = (float*) malloc(sizeof(float) * n * n);
b = (float*) malloc(sizeof(float) * n * n);
c = (float*) malloc(sizeof(float) * n * n);
d = (float*) malloc(sizeof(float) * n * n);
srand(0);
matgen(a, n, n);
matgen(b, n, n);
clock_t time = matmultCUDA(a, n, b, n, c, n, n);
matmult(a, n, b, n, d, n, n);
compare_mat(c, n, d, n, n);
double sec = (double) time / CLOCKS_PER_SEC;
printf("Time used: %.2f (%.2lf GFLOPS)\n", sec,
2.0 * n * n * n / (sec * 1E9));
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
//CUDA RunTime API
#include <hip/hip_runtime.h>
//1M
#define DATA_SIZE 1048576
#define THREAD_NUM 256
#define BLOCK_NUM 32
#define NUM_THREADS 256
__global__ static void matMultCUDA(const float* a, size_t lda,
const float* b, size_t ldb, float* c, size_t ldc, int n)
{
extern __shared__ float data[];
const int tid = threadIdx.x;
const int row = blockIdx.x;
int i, j;
for(i = tid; i < n; i += blockDim.x) {
data[i] = a[row * lda + i];
}
__syncthreads();
for(j = tid; j < n; j += blockDim.x) {
float t = 0;
float y = 0;
for(i = 0; i < n; i++) {
float r;
y -= data[i] * b[i * ldb + j];
r = t - y;
y = (r - t) + y;
t = r;
}
c[row * ldc + j] = t;
}
}
clock_t matmultCUDA(const float* a, int lda,
const float* b, int ldb, float* c, int ldc, int n)
{
float *ac, *bc, *cc;
clock_t start, end;
start = clock();
hipMalloc((void**) &ac, sizeof(float) * n * n);
hipMalloc((void**) &bc, sizeof(float) * n * n);
hipMalloc((void**) &cc, sizeof(float) * n * n);
hipMemcpy(ac, a,
sizeof(float) * n * n, hipMemcpyHostToDevice);
hipMemcpy(bc, b,
sizeof(float) * n * n, hipMemcpyHostToDevice);
int blocks = (n + NUM_THREADS - 1) / NUM_THREADS;
matMultCUDA<<< n, NUM_THREADS, sizeof(float) * n>>>
(ac, n, bc, n, cc, n, n);
hipMemcpy(c, cc,
sizeof(float) * n * n, hipMemcpyDeviceToHost);
hipFree(ac);
hipFree(bc);
hipFree(cc);
end = clock();
return end - start;
}
void compare_mat(const float* a, int lda,
const float* b, int ldb, int n)
{
float max_err = 0;
float average_err = 0;
int i, j;
for(i = 0; i < n; i++) {
for(j = 0; j < n; j++) {
if(b[i * ldb + j] != 0) {
float err = fabs((a[i * lda + j] -
b[i * ldb + j]) / b[i * ldb + j]);
if(max_err < err) max_err = err;
average_err += err;
} }
}
printf("Max error: %g Average error: %g\n",
max_err, average_err / (n * n));
}
void matmult(const float* a, int lda, const float* b, int ldb,
float* c, int ldc, int n)
{
int i, j, k;
for(i = 0; i < n; i++) {
for(j = 0; j < n; j++) {
double t = 0;
for(k = 0; k < n; k++) {
t += a[i * lda + k] * b[k * ldb + j];
}
c[i * ldc + j] = t;
}
} }
void matgen(float* a, int lda, int n)
{
int i, j;
for(i = 0; i < n; i++) {
for(j = 0; j < n; j++) {
a[i * lda + j] = (float) rand() / RAND_MAX +
(float) rand() / (RAND_MAX * RAND_MAX);
} }
}
int main() {
float *a, *b, *c, *d;
int n = 1000;
a = (float*) malloc(sizeof(float) * n * n);
b = (float*) malloc(sizeof(float) * n * n);
c = (float*) malloc(sizeof(float) * n * n);
d = (float*) malloc(sizeof(float) * n * n);
srand(0);
matgen(a, n, n);
matgen(b, n, n);
clock_t time = matmultCUDA(a, n, b, n, c, n, n);
matmult(a, n, b, n, d, n, n);
compare_mat(c, n, d, n, n);
double sec = (double) time / CLOCKS_PER_SEC;
printf("Time used: %.2f (%.2lf GFLOPS)\n", sec,
2.0 * n * n * n / (sec * 1E9));
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
//CUDA RunTime API
#include <hip/hip_runtime.h>
//1M
#define DATA_SIZE 1048576
#define THREAD_NUM 256
#define BLOCK_NUM 32
#define NUM_THREADS 256
__global__ static void matMultCUDA(const float* a, size_t lda,
const float* b, size_t ldb, float* c, size_t ldc, int n)
{
extern __shared__ float data[];
const int tid = threadIdx.x;
const int row = blockIdx.x;
int i, j;
for(i = tid; i < n; i += blockDim.x) {
data[i] = a[row * lda + i];
}
__syncthreads();
for(j = tid; j < n; j += blockDim.x) {
float t = 0;
float y = 0;
for(i = 0; i < n; i++) {
float r;
y -= data[i] * b[i * ldb + j];
r = t - y;
y = (r - t) + y;
t = r;
}
c[row * ldc + j] = t;
}
}
clock_t matmultCUDA(const float* a, int lda,
const float* b, int ldb, float* c, int ldc, int n)
{
float *ac, *bc, *cc;
clock_t start, end;
start = clock();
hipMalloc((void**) &ac, sizeof(float) * n * n);
hipMalloc((void**) &bc, sizeof(float) * n * n);
hipMalloc((void**) &cc, sizeof(float) * n * n);
hipMemcpy(ac, a,
sizeof(float) * n * n, hipMemcpyHostToDevice);
hipMemcpy(bc, b,
sizeof(float) * n * n, hipMemcpyHostToDevice);
int blocks = (n + NUM_THREADS - 1) / NUM_THREADS;
matMultCUDA<<< n, NUM_THREADS, sizeof(float) * n>>>
(ac, n, bc, n, cc, n, n);
hipMemcpy(c, cc,
sizeof(float) * n * n, hipMemcpyDeviceToHost);
hipFree(ac);
hipFree(bc);
hipFree(cc);
end = clock();
return end - start;
}
void compare_mat(const float* a, int lda,
const float* b, int ldb, int n)
{
float max_err = 0;
float average_err = 0;
int i, j;
for(i = 0; i < n; i++) {
for(j = 0; j < n; j++) {
if(b[i * ldb + j] != 0) {
float err = fabs((a[i * lda + j] -
b[i * ldb + j]) / b[i * ldb + j]);
if(max_err < err) max_err = err;
average_err += err;
} }
}
printf("Max error: %g Average error: %g\n",
max_err, average_err / (n * n));
}
void matmult(const float* a, int lda, const float* b, int ldb,
float* c, int ldc, int n)
{
int i, j, k;
for(i = 0; i < n; i++) {
for(j = 0; j < n; j++) {
double t = 0;
for(k = 0; k < n; k++) {
t += a[i * lda + k] * b[k * ldb + j];
}
c[i * ldc + j] = t;
}
} }
void matgen(float* a, int lda, int n)
{
int i, j;
for(i = 0; i < n; i++) {
for(j = 0; j < n; j++) {
a[i * lda + j] = (float) rand() / RAND_MAX +
(float) rand() / (RAND_MAX * RAND_MAX);
} }
}
int main() {
float *a, *b, *c, *d;
int n = 1000;
a = (float*) malloc(sizeof(float) * n * n);
b = (float*) malloc(sizeof(float) * n * n);
c = (float*) malloc(sizeof(float) * n * n);
d = (float*) malloc(sizeof(float) * n * n);
srand(0);
matgen(a, n, n);
matgen(b, n, n);
clock_t time = matmultCUDA(a, n, b, n, c, n, n);
matmult(a, n, b, n, d, n, n);
compare_mat(c, n, d, n, n);
double sec = (double) time / CLOCKS_PER_SEC;
printf("Time used: %.2f (%.2lf GFLOPS)\n", sec,
2.0 * n * n * n / (sec * 1E9));
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL11matMultCUDAPKfmS0_mPfmi,"axG",@progbits,_ZL11matMultCUDAPKfmS0_mPfmi,comdat
.globl _ZL11matMultCUDAPKfmS0_mPfmi
.p2align 8
.type _ZL11matMultCUDAPKfmS0_mPfmi,@function
_ZL11matMultCUDAPKfmS0_mPfmi:
s_load_b32 s12, s[0:1], 0x30
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s12, v0
s_cbranch_execz .LBB0_3
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s8, s[0:1], 0x44
s_ashr_i32 s3, s15, 31
v_lshl_add_u32 v3, v0, 2, 0
v_mov_b32_e32 v1, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s7, s15, s7
s_mul_hi_u32 s9, s15, s6
s_mul_i32 s3, s3, s6
s_add_i32 s7, s9, s7
s_mul_i32 s6, s15, s6
s_add_i32 s7, s7, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[6:7], s[6:7], 2
s_add_u32 s3, s4, s6
s_addc_u32 s4, s5, s7
s_and_b32 s5, s8, 0xffff
s_mov_b32 s6, 0
s_lshl_b32 s7, s5, 2
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
v_add_co_u32 v4, vcc_lo, s3, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s4, v5, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s12, v1
global_load_b32 v2, v[4:5], off
s_or_b32 s6, vcc_lo, s6
s_waitcnt vmcnt(0)
ds_store_b32 v3, v2
v_add_nc_u32_e32 v3, s7, v3
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s12, v0
s_cbranch_execz .LBB0_10
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x10
s_load_b32 s0, s[0:1], 0x44
s_cmp_gt_i32 s12, 0
s_cselect_b32 s1, -1, 0
s_ashr_i32 s2, s15, 31
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s15, s11
s_mul_hi_u32 s11, s15, s10
s_mul_i32 s13, s2, s10
s_add_i32 s3, s11, s3
s_mul_i32 s2, s15, s10
s_add_i32 s3, s3, s13
s_mov_b32 s10, 0
s_lshl_b64 s[2:3], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s8, s8, s2
s_addc_u32 s9, s9, s3
s_and_b32 s11, s0, 0xffff
s_lshl_b64 s[2:3], s[6:7], 2
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_7
.p2align 6
.LBB0_5:
v_mov_b32_e32 v4, 0
.LBB0_6:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_add_nc_u32_e32 v0, s11, v0
v_cmp_le_i32_e32 vcc_lo, s12, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s0, s8, v1
v_add_co_ci_u32_e64 v2, s0, s9, v2, s0
s_or_b32 s10, vcc_lo, s10
global_store_b32 v[1:2], v4, off
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execz .LBB0_10
.LBB0_7:
v_ashrrev_i32_e32 v1, 31, v0
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[0:1]
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, 0
s_mov_b32 s0, 0
s_mov_b32 s6, s12
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_9:
global_load_b32 v6, v[2:3], off
v_dual_mov_b32 v7, s0 :: v_dual_mov_b32 v8, v4
v_add_co_u32 v2, vcc_lo, v2, s2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
ds_load_b32 v7, v7
s_add_i32 s6, s6, -1
s_add_i32 s0, s0, 4
s_cmp_lg_u32 s6, 0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f32 v5, -v7, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v4, v8, v5
v_sub_f32_e32 v6, v4, v8
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v5, v5, v6
s_cbranch_scc1 .LBB0_9
s_branch .LBB0_6
.LBB0_10:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL11matMultCUDAPKfmS0_mPfmi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL11matMultCUDAPKfmS0_mPfmi,"axG",@progbits,_ZL11matMultCUDAPKfmS0_mPfmi,comdat
.Lfunc_end0:
.size _ZL11matMultCUDAPKfmS0_mPfmi, .Lfunc_end0-_ZL11matMultCUDAPKfmS0_mPfmi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
- .offset: 176
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL11matMultCUDAPKfmS0_mPfmi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL11matMultCUDAPKfmS0_mPfmi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
//CUDA RunTime API
#include <hip/hip_runtime.h>
//1M
#define DATA_SIZE 1048576
#define THREAD_NUM 256
#define BLOCK_NUM 32
#define NUM_THREADS 256
__global__ static void matMultCUDA(const float* a, size_t lda,
const float* b, size_t ldb, float* c, size_t ldc, int n)
{
extern __shared__ float data[];
const int tid = threadIdx.x;
const int row = blockIdx.x;
int i, j;
for(i = tid; i < n; i += blockDim.x) {
data[i] = a[row * lda + i];
}
__syncthreads();
for(j = tid; j < n; j += blockDim.x) {
float t = 0;
float y = 0;
for(i = 0; i < n; i++) {
float r;
y -= data[i] * b[i * ldb + j];
r = t - y;
y = (r - t) + y;
t = r;
}
c[row * ldc + j] = t;
}
}
clock_t matmultCUDA(const float* a, int lda,
const float* b, int ldb, float* c, int ldc, int n)
{
float *ac, *bc, *cc;
clock_t start, end;
start = clock();
hipMalloc((void**) &ac, sizeof(float) * n * n);
hipMalloc((void**) &bc, sizeof(float) * n * n);
hipMalloc((void**) &cc, sizeof(float) * n * n);
hipMemcpy(ac, a,
sizeof(float) * n * n, hipMemcpyHostToDevice);
hipMemcpy(bc, b,
sizeof(float) * n * n, hipMemcpyHostToDevice);
int blocks = (n + NUM_THREADS - 1) / NUM_THREADS;
matMultCUDA<<< n, NUM_THREADS, sizeof(float) * n>>>
(ac, n, bc, n, cc, n, n);
hipMemcpy(c, cc,
sizeof(float) * n * n, hipMemcpyDeviceToHost);
hipFree(ac);
hipFree(bc);
hipFree(cc);
end = clock();
return end - start;
}
void compare_mat(const float* a, int lda,
const float* b, int ldb, int n)
{
float max_err = 0;
float average_err = 0;
int i, j;
for(i = 0; i < n; i++) {
for(j = 0; j < n; j++) {
if(b[i * ldb + j] != 0) {
float err = fabs((a[i * lda + j] -
b[i * ldb + j]) / b[i * ldb + j]);
if(max_err < err) max_err = err;
average_err += err;
} }
}
printf("Max error: %g Average error: %g\n",
max_err, average_err / (n * n));
}
void matmult(const float* a, int lda, const float* b, int ldb,
float* c, int ldc, int n)
{
int i, j, k;
for(i = 0; i < n; i++) {
for(j = 0; j < n; j++) {
double t = 0;
for(k = 0; k < n; k++) {
t += a[i * lda + k] * b[k * ldb + j];
}
c[i * ldc + j] = t;
}
} }
void matgen(float* a, int lda, int n)
{
int i, j;
for(i = 0; i < n; i++) {
for(j = 0; j < n; j++) {
a[i * lda + j] = (float) rand() / RAND_MAX +
(float) rand() / (RAND_MAX * RAND_MAX);
} }
}
int main() {
float *a, *b, *c, *d;
int n = 1000;
a = (float*) malloc(sizeof(float) * n * n);
b = (float*) malloc(sizeof(float) * n * n);
c = (float*) malloc(sizeof(float) * n * n);
d = (float*) malloc(sizeof(float) * n * n);
srand(0);
matgen(a, n, n);
matgen(b, n, n);
clock_t time = matmultCUDA(a, n, b, n, c, n, n);
matmult(a, n, b, n, d, n, n);
compare_mat(c, n, d, n, n);
double sec = (double) time / CLOCKS_PER_SEC;
printf("Time used: %.2f (%.2lf GFLOPS)\n", sec,
2.0 * n * n * n / (sec * 1E9));
return 0;
} | .text
.file "cudasucess.hip"
.globl _Z11matmultCUDAPKfiS0_iPfii # -- Begin function _Z11matmultCUDAPKfiS0_iPfii
.p2align 4, 0x90
.type _Z11matmultCUDAPKfiS0_iPfii,@function
_Z11matmultCUDAPKfiS0_iPfii: # @_Z11matmultCUDAPKfiS0_iPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, 32(%rsp) # 8-byte Spill
movq %rdx, %rbp
movq %rdi, %rbx
movl 256(%rsp), %r12d
callq clock
movq %rax, 40(%rsp) # 8-byte Spill
movslq %r12d, %r14
leaq (,%r14,4), %r13
movq %r13, %r15
imulq %r14, %r15
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %r15, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %rbp, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %r12
orq $256, %rdx # imm = 0x100
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
movq %r13, %r8
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 136(%rsp)
movq %r14, 128(%rsp)
movq %rcx, 120(%rsp)
movq %r14, 112(%rsp)
movq %rdx, 104(%rsp)
movq %r14, 96(%rsp)
movl %r14d, 28(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 112(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 96(%rsp), %rax
movq %rax, 184(%rsp)
leaq 28(%rsp), %rax
movq %rax, 192(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_ZL11matMultCUDAPKfmS0_mPfmi, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
movq (%rsp), %rsi
movq 32(%rsp), %rdi # 8-byte Reload
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
callq clock
subq 40(%rsp), %rax # 8-byte Folded Reload
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z11matmultCUDAPKfiS0_iPfii, .Lfunc_end0-_Z11matmultCUDAPKfiS0_iPfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL26__device_stub__matMultCUDAPKfmS0_mPfmi
.type _ZL26__device_stub__matMultCUDAPKfmS0_mPfmi,@function
_ZL26__device_stub__matMultCUDAPKfmS0_mPfmi: # @_ZL26__device_stub__matMultCUDAPKfmS0_mPfmi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_ZL11matMultCUDAPKfmS0_mPfmi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _ZL26__device_stub__matMultCUDAPKfmS0_mPfmi, .Lfunc_end1-_ZL26__device_stub__matMultCUDAPKfmS0_mPfmi
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z11compare_matPKfiS0_ii
.LCPI2_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl _Z11compare_matPKfiS0_ii
.p2align 4, 0x90
.type _Z11compare_matPKfiS0_ii,@function
_Z11compare_matPKfiS0_ii: # @_Z11compare_matPKfiS0_ii
.cfi_startproc
# %bb.0:
testl %r8d, %r8d
jle .LBB2_1
# %bb.2: # %.preheader.lr.ph
movslq %ecx, %rax
movslq %esi, %rcx
movl %r8d, %esi
shlq $2, %rcx
shlq $2, %rax
xorps %xmm0, %xmm0
xorl %r9d, %r9d
movaps .LCPI2_0(%rip), %xmm2 # xmm2 = [NaN,NaN,NaN,NaN]
xorps %xmm3, %xmm3
xorps %xmm1, %xmm1
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_7: # %._crit_edge
# in Loop: Header=BB2_3 Depth=1
incq %r9
addq %rcx, %rdi
addq %rax, %rdx
cmpq %rsi, %r9
je .LBB2_8
.LBB2_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
xorl %r10d, %r10d
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_6: # in Loop: Header=BB2_4 Depth=2
incq %r10
cmpq %r10, %rsi
je .LBB2_7
.LBB2_4: # Parent Loop BB2_3 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdx,%r10,4), %xmm4 # xmm4 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm4
jne .LBB2_5
jnp .LBB2_6
.LBB2_5: # in Loop: Header=BB2_4 Depth=2
movss (%rdi,%r10,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
subss %xmm4, %xmm5
divss %xmm4, %xmm5
andps %xmm2, %xmm5
addss %xmm5, %xmm1
maxss %xmm3, %xmm5
movaps %xmm5, %xmm3
jmp .LBB2_6
.LBB2_8: # %._crit_edge46.loopexit
xorps %xmm0, %xmm0
cvtss2sd %xmm3, %xmm0
jmp .LBB2_9
.LBB2_1:
xorps %xmm0, %xmm0
xorps %xmm1, %xmm1
.LBB2_9: # %._crit_edge46
imull %r8d, %r8d
xorps %xmm2, %xmm2
cvtsi2ss %r8d, %xmm2
divss %xmm2, %xmm1
cvtss2sd %xmm1, %xmm1
movl $.L.str, %edi
movb $2, %al
jmp printf # TAILCALL
.Lfunc_end2:
.size _Z11compare_matPKfiS0_ii, .Lfunc_end2-_Z11compare_matPKfiS0_ii
.cfi_endproc
# -- End function
.globl _Z7matmultPKfiS0_iPfii # -- Begin function _Z7matmultPKfiS0_iPfii
.p2align 4, 0x90
.type _Z7matmultPKfiS0_iPfii,@function
_Z7matmultPKfiS0_iPfii: # @_Z7matmultPKfiS0_iPfii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl 40(%rsp), %r10d
testl %r10d, %r10d
jle .LBB3_7
# %bb.1: # %.preheader26.lr.ph
movslq %ecx, %rax
movslq %esi, %rcx
movslq %r9d, %rsi
movl %r10d, %r9d
shlq $2, %rcx
shlq $2, %rax
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB3_2: # %.preheader26
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
# Child Loop BB3_4 Depth 3
movq %r10, %r11
imulq %rsi, %r11
leaq (%r8,%r11,4), %r11
movq %rdx, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_3: # %.preheader
# Parent Loop BB3_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_4 Depth 3
xorpd %xmm0, %xmm0
movq %rbx, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_2 Depth=1
# Parent Loop BB3_3 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rdi,%r12,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r15), %xmm1
cvtss2sd %xmm1, %xmm1
addsd %xmm1, %xmm0
incq %r12
addq %rax, %r15
cmpq %r12, %r9
jne .LBB3_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB3_3 Depth=2
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r11,%r14,4)
incq %r14
addq $4, %rbx
cmpq %r9, %r14
jne .LBB3_3
# %bb.6: # %._crit_edge30
# in Loop: Header=BB3_2 Depth=1
incq %r10
addq %rcx, %rdi
cmpq %r9, %r10
jne .LBB3_2
.LBB3_7: # %._crit_edge32
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z7matmultPKfiS0_iPfii, .Lfunc_end3-_Z7matmultPKfiS0_iPfii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z6matgenPfii
.LCPI4_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z6matgenPfii
.p2align 4, 0x90
.type _Z6matgenPfii,@function
_Z6matgenPfii: # @_Z6matgenPfii
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB4_6
# %bb.1: # %.preheader.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movslq %esi, %r14
movl %edx, %r15d
shlq $2, %r14
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_3 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_3: # Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI4_0(%rip), %xmm0
movss %xmm0, 12(%rsp) # 4-byte Spill
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
addss 12(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, (%rbx,%r13,4)
incq %r13
cmpq %r13, %r15
jne .LBB4_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
incq %r12
addq %r14, %rbx
cmpq %r15, %r12
jne .LBB4_2
# %bb.5:
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.LBB4_6: # %._crit_edge13
retq
.Lfunc_end4:
.size _Z6matgenPfii, .Lfunc_end4-_Z6matgenPfii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI5_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI5_2:
.long 0x49742400 # float 1.0E+6
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI5_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI5_3:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI5_4:
.quad 0x41cdcd6500000000 # double 1.0E+9
.LCPI5_5:
.quad 0x41ddcd6500000000 # double 2.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %r15
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %rbx
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %r14
xorl %r13d, %r13d
xorl %edi, %edi
callq srand
movq %r15, %rbp
.p2align 4, 0x90
.LBB5_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB5_2 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_2: # Parent Loop BB5_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI5_0(%rip), %xmm0
movss %xmm0, 12(%rsp) # 4-byte Spill
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
addss 12(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, (%rbp,%r12,4)
incq %r12
cmpq $1000, %r12 # imm = 0x3E8
jne .LBB5_2
# %bb.3: # %._crit_edge.i
# in Loop: Header=BB5_1 Depth=1
incq %r13
addq $4000, %rbp # imm = 0xFA0
cmpq $1000, %r13 # imm = 0x3E8
jne .LBB5_1
# %bb.4: # %.preheader.i38.preheader
xorl %r13d, %r13d
movq 16(%rsp), %rbp # 8-byte Reload
.p2align 4, 0x90
.LBB5_5: # %.preheader.i38
# =>This Loop Header: Depth=1
# Child Loop BB5_6 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_6: # Parent Loop BB5_5 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI5_0(%rip), %xmm0
movss %xmm0, 12(%rsp) # 4-byte Spill
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
addss 12(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, (%rbp,%r12,4)
incq %r12
cmpq $1000, %r12 # imm = 0x3E8
jne .LBB5_6
# %bb.7: # %._crit_edge.i43
# in Loop: Header=BB5_5 Depth=1
incq %r13
addq $4000, %rbp # imm = 0xFA0
cmpq $1000, %r13 # imm = 0x3E8
jne .LBB5_5
# %bb.8: # %_Z6matgenPfii.exit46
movl $1000, (%rsp) # imm = 0x3E8
movq %r15, %rdi
movq 16(%rsp), %r12 # 8-byte Reload
movq %r12, %rdx
movq %rbx, %r8
callq _Z11matmultCUDAPKfiS0_iPfii
movq %rax, %r13
xorl %eax, %eax
.p2align 4, 0x90
.LBB5_9: # %.preheader26.i
# =>This Loop Header: Depth=1
# Child Loop BB5_10 Depth 2
# Child Loop BB5_11 Depth 3
imulq $4000, %rax, %rcx # imm = 0xFA0
addq %r14, %rcx
movq %r12, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB5_10: # %.preheader.i47
# Parent Loop BB5_9 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB5_11 Depth 3
xorps %xmm0, %xmm0
movq %rdx, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB5_11: # Parent Loop BB5_9 Depth=1
# Parent Loop BB5_10 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r15,%r8,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rdi), %xmm1
cvtss2sd %xmm1, %xmm1
addsd %xmm1, %xmm0
incq %r8
addq $4000, %rdi # imm = 0xFA0
cmpq $1000, %r8 # imm = 0x3E8
jne .LBB5_11
# %bb.12: # %._crit_edge.i51
# in Loop: Header=BB5_10 Depth=2
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rcx,%rsi,4)
incq %rsi
addq $4, %rdx
cmpq $1000, %rsi # imm = 0x3E8
jne .LBB5_10
# %bb.13: # %._crit_edge30.i
# in Loop: Header=BB5_9 Depth=1
incq %rax
addq $4000, %r15 # imm = 0xFA0
cmpq $1000, %rax # imm = 0x3E8
jne .LBB5_9
# %bb.14: # %.preheader.i52.preheader
xorps %xmm0, %xmm0
xorl %eax, %eax
movaps .LCPI5_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
xorps %xmm3, %xmm3
xorps %xmm2, %xmm2
jmp .LBB5_15
.p2align 4, 0x90
.LBB5_19: # %._crit_edge.i56
# in Loop: Header=BB5_15 Depth=1
incq %rax
addq $4000, %rbx # imm = 0xFA0
addq $4000, %r14 # imm = 0xFA0
cmpq $1000, %rax # imm = 0x3E8
je .LBB5_20
.LBB5_15: # %.preheader.i52
# =>This Loop Header: Depth=1
# Child Loop BB5_16 Depth 2
xorl %ecx, %ecx
jmp .LBB5_16
.p2align 4, 0x90
.LBB5_18: # in Loop: Header=BB5_16 Depth=2
incq %rcx
cmpq $1000, %rcx # imm = 0x3E8
je .LBB5_19
.LBB5_16: # Parent Loop BB5_15 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%rcx,4), %xmm4 # xmm4 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm4
jne .LBB5_17
jnp .LBB5_18
.LBB5_17: # in Loop: Header=BB5_16 Depth=2
movss (%rbx,%rcx,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
subss %xmm4, %xmm5
divss %xmm4, %xmm5
andps %xmm1, %xmm5
addss %xmm5, %xmm2
maxss %xmm3, %xmm5
movaps %xmm5, %xmm3
jmp .LBB5_18
.LBB5_20: # %_Z11compare_matPKfiS0_ii.exit
xorps %xmm0, %xmm0
cvtss2sd %xmm3, %xmm0
divss .LCPI5_2(%rip), %xmm2
xorps %xmm1, %xmm1
cvtss2sd %xmm2, %xmm1
movl $.L.str, %edi
movb $2, %al
callq printf
xorps %xmm0, %xmm0
cvtsi2sd %r13, %xmm0
divsd .LCPI5_3(%rip), %xmm0
movsd .LCPI5_4(%rip), %xmm2 # xmm2 = mem[0],zero
mulsd %xmm0, %xmm2
movsd .LCPI5_5(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm2, %xmm1
movl $.L.str.1, %edi
movb $2, %al
callq printf
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL11matMultCUDAPKfmS0_mPfmi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _ZL11matMultCUDAPKfmS0_mPfmi,@object # @_ZL11matMultCUDAPKfmS0_mPfmi
.section .rodata,"a",@progbits
.p2align 3, 0x0
_ZL11matMultCUDAPKfmS0_mPfmi:
.quad _ZL26__device_stub__matMultCUDAPKfmS0_mPfmi
.size _ZL11matMultCUDAPKfmS0_mPfmi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Max error: %g Average error: %g\n"
.size .L.str, 33
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Time used: %.2f (%.2lf GFLOPS)\n"
.size .L.str.1, 32
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_ZL11matMultCUDAPKfmS0_mPfmi"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZL26__device_stub__matMultCUDAPKfmS0_mPfmi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZL11matMultCUDAPKfmS0_mPfmi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000462d4_00000000-6_cudasucess.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL41__device_stub__Z11matMultCUDAPKfmS0_mPfmiPKfmS0_mPfmi, @function
_ZL41__device_stub__Z11matMultCUDAPKfmS0_mPfmiPKfmS0_mPfmi:
.LFB2086:
.cfi_startproc
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _ZL11matMultCUDAPKfmS0_mPfmi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _ZL41__device_stub__Z11matMultCUDAPKfmS0_mPfmiPKfmS0_mPfmi, .-_ZL41__device_stub__Z11matMultCUDAPKfmS0_mPfmiPKfmS0_mPfmi
.type _ZL11matMultCUDAPKfmS0_mPfmi, @function
_ZL11matMultCUDAPKfmS0_mPfmi:
.LFB2087:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _ZL41__device_stub__Z11matMultCUDAPKfmS0_mPfmiPKfmS0_mPfmi
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL11matMultCUDAPKfmS0_mPfmi, .-_ZL11matMultCUDAPKfmS0_mPfmi
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11matmultCUDAPKfiS0_iPfii
.type _Z11matmultCUDAPKfiS0_iPfii, @function
_Z11matmultCUDAPKfiS0_iPfii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %r14
movq %rdx, %r13
movq %r8, 8(%rsp)
movl 144(%rsp), %r15d
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
call clock@PLT
movq %rax, %r12
movslq %r15d, %rbp
movq %rbp, %rbx
imulq %rbp, %rbx
salq $2, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl %r15d, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
leaq 0(,%rbp,4), %r8
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
call clock@PLT
subq %r12, %rax
movq 72(%rsp), %rdx
subq %fs:40, %rdx
jne .L16
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 152
pushq %r15
.cfi_def_cfa_offset 160
movq %rbp, %r9
movq 56(%rsp), %r8
movq %rbp, %rcx
movq 48(%rsp), %rdx
movq %rbp, %rsi
movq 40(%rsp), %rdi
call _ZL41__device_stub__Z11matMultCUDAPKfmS0_mPfmiPKfmS0_mPfmi
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z11matmultCUDAPKfiS0_iPfii, .-_Z11matmultCUDAPKfiS0_iPfii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Max error: %g Average error: %g\n"
.text
.globl _Z11compare_matPKfiS0_ii
.type _Z11compare_matPKfiS0_ii, @function
_Z11compare_matPKfiS0_ii:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
testl %r8d, %r8d
jle .L24
movq %rdi, %r9
movl %esi, %r10d
movl %r8d, %esi
movslq %ecx, %rcx
leaq 0(,%rcx,4), %rbx
movl $0, %ebp
movl $0, %r11d
pxor %xmm1, %xmm1
movaps %xmm1, %xmm4
movaps %xmm1, %xmm3
movss .LC1(%rip), %xmm5
jmp .L19
.L26:
movslq %eax, %rdi
movss (%r9,%rdi,4), %xmm0
subss %xmm2, %xmm0
divss %xmm2, %xmm0
andps %xmm5, %xmm0
movaps %xmm0, %xmm6
maxss %xmm4, %xmm6
movaps %xmm6, %xmm4
addss %xmm0, %xmm1
.L20:
addq $4, %rcx
addl $1, %eax
cmpl %eax, %esi
je .L29
.L23:
movss (%rcx), %xmm2
ucomiss %xmm3, %xmm2
jp .L26
je .L20
jmp .L26
.L29:
addl $1, %r11d
addl %r10d, %esi
addq %rbx, %rdx
addl %r10d, %ebp
cmpl %r11d, %r8d
je .L18
.L19:
movl %ebp, %eax
movq %rdx, %rcx
jmp .L23
.L24:
pxor %xmm1, %xmm1
movaps %xmm1, %xmm4
.L18:
imull %r8d, %r8d
pxor %xmm0, %xmm0
cvtsi2ssl %r8d, %xmm0
divss %xmm0, %xmm1
pxor %xmm0, %xmm0
cvtss2sd %xmm4, %xmm0
cvtss2sd %xmm1, %xmm1
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z11compare_matPKfiS0_ii, .-_Z11compare_matPKfiS0_ii
.globl _Z7matmultPKfiS0_iPfii
.type _Z7matmultPKfiS0_iPfii, @function
_Z7matmultPKfiS0_iPfii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl 48(%rsp), %r12d
testl %r12d, %r12d
jle .L30
movq %rdx, %r11
movl %ecx, %eax
movslq %r9d, %rbp
salq $2, %rbp
movslq %esi, %rsi
leaq 0(,%rsi,4), %rbx
movq %rdi, %r9
movslq %r12d, %r10
leaq (%rdi,%r10,4), %rcx
cltq
leaq 0(,%rax,4), %rsi
movl $0, %r14d
.L32:
movq %r11, %r13
movl $0, %edi
.L35:
movq %r13, %rdx
movq %r9, %rax
pxor %xmm1, %xmm1
.L33:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
cvtss2sd %xmm0, %xmm0
addsd %xmm0, %xmm1
addq $4, %rax
addq %rsi, %rdx
cmpq %rcx, %rax
jne .L33
cvtsd2ss %xmm1, %xmm1
movss %xmm1, (%r8,%rdi,4)
addq $1, %rdi
addq $4, %r13
cmpq %r10, %rdi
jne .L35
addl $1, %r14d
addq %rbp, %r8
addq %rbx, %r9
addq %rbx, %rcx
cmpl %r14d, %r12d
jne .L32
.L30:
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z7matmultPKfiS0_iPfii, .-_Z7matmultPKfiS0_iPfii
.globl _Z6matgenPfii
.type _Z6matgenPfii, @function
_Z6matgenPfii:
.LFB2060:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L44
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %edx, %r15d
movslq %esi, %rsi
leaq 0(,%rsi,4), %r13
movslq %edx, %r14
leaq (%rdi,%r14,4), %rbp
negq %r14
salq $2, %r14
movl $0, %r12d
.L40:
leaq 0(%rbp,%r14), %rbx
.L41:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC4(%rip), %xmm0
movss %xmm0, 12(%rsp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
addss 12(%rsp), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L41
addl $1, %r12d
addq %r13, %rbp
cmpl %r12d, %r15d
jne .L40
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2060:
.size _Z6matgenPfii, .-_Z6matgenPfii
.section .rodata.str1.8
.align 8
.LC8:
.string "Time used: %.2f (%.2lf GFLOPS)\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl $4000000, %edi
call malloc@PLT
movq %rax, %rbx
movl $4000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $4000000, %edi
call malloc@PLT
movq %rax, %r12
movl $4000000, %edi
call malloc@PLT
movq %rax, %r13
movl $0, %edi
call srand@PLT
movl $1000, %edx
movl $1000, %esi
movq %rbx, %rdi
call _Z6matgenPfii
movl $1000, %edx
movl $1000, %esi
movq %rbp, %rdi
call _Z6matgenPfii
subq $8, %rsp
.cfi_def_cfa_offset 56
pushq $1000
.cfi_def_cfa_offset 64
movl $1000, %r9d
movq %r12, %r8
movl $1000, %ecx
movq %rbp, %rdx
movl $1000, %esi
movq %rbx, %rdi
call _Z11matmultCUDAPKfiS0_iPfii
movq %rax, %r14
movl $1000, (%rsp)
movl $1000, %r9d
movq %r13, %r8
movl $1000, %ecx
movq %rbp, %rdx
movl $1000, %esi
movq %rbx, %rdi
call _Z7matmultPKfiS0_iPfii
addq $16, %rsp
.cfi_def_cfa_offset 48
movl $1000, %r8d
movl $1000, %ecx
movq %r13, %rdx
movl $1000, %esi
movq %r12, %rdi
call _Z11compare_matPKfiS0_ii
pxor %xmm0, %xmm0
cvtsi2sdq %r14, %xmm0
divsd .LC5(%rip), %xmm0
movapd %xmm0, %xmm2
mulsd .LC6(%rip), %xmm2
movsd .LC7(%rip), %xmm1
divsd %xmm2, %xmm1
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC9:
.string "_Z11matMultCUDAPKfmS0_mPfmi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL11matMultCUDAPKfmS0_mPfmi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC1:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 805306368
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1093567616
.align 8
.LC6:
.long 0
.long 1104006501
.align 8
.LC7:
.long 0
.long 1105055077
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cudasucess.hip"
.globl _Z11matmultCUDAPKfiS0_iPfii # -- Begin function _Z11matmultCUDAPKfiS0_iPfii
.p2align 4, 0x90
.type _Z11matmultCUDAPKfiS0_iPfii,@function
_Z11matmultCUDAPKfiS0_iPfii: # @_Z11matmultCUDAPKfiS0_iPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, 32(%rsp) # 8-byte Spill
movq %rdx, %rbp
movq %rdi, %rbx
movl 256(%rsp), %r12d
callq clock
movq %rax, 40(%rsp) # 8-byte Spill
movslq %r12d, %r14
leaq (,%r14,4), %r13
movq %r13, %r15
imulq %r14, %r15
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %r15, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %rbp, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %r12
orq $256, %rdx # imm = 0x100
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
movq %r13, %r8
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 136(%rsp)
movq %r14, 128(%rsp)
movq %rcx, 120(%rsp)
movq %r14, 112(%rsp)
movq %rdx, 104(%rsp)
movq %r14, 96(%rsp)
movl %r14d, 28(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 112(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 96(%rsp), %rax
movq %rax, 184(%rsp)
leaq 28(%rsp), %rax
movq %rax, 192(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_ZL11matMultCUDAPKfmS0_mPfmi, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
movq (%rsp), %rsi
movq 32(%rsp), %rdi # 8-byte Reload
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
callq clock
subq 40(%rsp), %rax # 8-byte Folded Reload
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z11matmultCUDAPKfiS0_iPfii, .Lfunc_end0-_Z11matmultCUDAPKfiS0_iPfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL26__device_stub__matMultCUDAPKfmS0_mPfmi
.type _ZL26__device_stub__matMultCUDAPKfmS0_mPfmi,@function
_ZL26__device_stub__matMultCUDAPKfmS0_mPfmi: # @_ZL26__device_stub__matMultCUDAPKfmS0_mPfmi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_ZL11matMultCUDAPKfmS0_mPfmi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _ZL26__device_stub__matMultCUDAPKfmS0_mPfmi, .Lfunc_end1-_ZL26__device_stub__matMultCUDAPKfmS0_mPfmi
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z11compare_matPKfiS0_ii
.LCPI2_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl _Z11compare_matPKfiS0_ii
.p2align 4, 0x90
.type _Z11compare_matPKfiS0_ii,@function
_Z11compare_matPKfiS0_ii: # @_Z11compare_matPKfiS0_ii
.cfi_startproc
# %bb.0:
testl %r8d, %r8d
jle .LBB2_1
# %bb.2: # %.preheader.lr.ph
movslq %ecx, %rax
movslq %esi, %rcx
movl %r8d, %esi
shlq $2, %rcx
shlq $2, %rax
xorps %xmm0, %xmm0
xorl %r9d, %r9d
movaps .LCPI2_0(%rip), %xmm2 # xmm2 = [NaN,NaN,NaN,NaN]
xorps %xmm3, %xmm3
xorps %xmm1, %xmm1
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_7: # %._crit_edge
# in Loop: Header=BB2_3 Depth=1
incq %r9
addq %rcx, %rdi
addq %rax, %rdx
cmpq %rsi, %r9
je .LBB2_8
.LBB2_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
xorl %r10d, %r10d
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_6: # in Loop: Header=BB2_4 Depth=2
incq %r10
cmpq %r10, %rsi
je .LBB2_7
.LBB2_4: # Parent Loop BB2_3 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdx,%r10,4), %xmm4 # xmm4 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm4
jne .LBB2_5
jnp .LBB2_6
.LBB2_5: # in Loop: Header=BB2_4 Depth=2
movss (%rdi,%r10,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
subss %xmm4, %xmm5
divss %xmm4, %xmm5
andps %xmm2, %xmm5
addss %xmm5, %xmm1
maxss %xmm3, %xmm5
movaps %xmm5, %xmm3
jmp .LBB2_6
.LBB2_8: # %._crit_edge46.loopexit
xorps %xmm0, %xmm0
cvtss2sd %xmm3, %xmm0
jmp .LBB2_9
.LBB2_1:
xorps %xmm0, %xmm0
xorps %xmm1, %xmm1
.LBB2_9: # %._crit_edge46
imull %r8d, %r8d
xorps %xmm2, %xmm2
cvtsi2ss %r8d, %xmm2
divss %xmm2, %xmm1
cvtss2sd %xmm1, %xmm1
movl $.L.str, %edi
movb $2, %al
jmp printf # TAILCALL
.Lfunc_end2:
.size _Z11compare_matPKfiS0_ii, .Lfunc_end2-_Z11compare_matPKfiS0_ii
.cfi_endproc
# -- End function
.globl _Z7matmultPKfiS0_iPfii # -- Begin function _Z7matmultPKfiS0_iPfii
.p2align 4, 0x90
.type _Z7matmultPKfiS0_iPfii,@function
_Z7matmultPKfiS0_iPfii: # @_Z7matmultPKfiS0_iPfii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl 40(%rsp), %r10d
testl %r10d, %r10d
jle .LBB3_7
# %bb.1: # %.preheader26.lr.ph
movslq %ecx, %rax
movslq %esi, %rcx
movslq %r9d, %rsi
movl %r10d, %r9d
shlq $2, %rcx
shlq $2, %rax
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB3_2: # %.preheader26
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
# Child Loop BB3_4 Depth 3
movq %r10, %r11
imulq %rsi, %r11
leaq (%r8,%r11,4), %r11
movq %rdx, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_3: # %.preheader
# Parent Loop BB3_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_4 Depth 3
xorpd %xmm0, %xmm0
movq %rbx, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_2 Depth=1
# Parent Loop BB3_3 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rdi,%r12,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r15), %xmm1
cvtss2sd %xmm1, %xmm1
addsd %xmm1, %xmm0
incq %r12
addq %rax, %r15
cmpq %r12, %r9
jne .LBB3_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB3_3 Depth=2
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r11,%r14,4)
incq %r14
addq $4, %rbx
cmpq %r9, %r14
jne .LBB3_3
# %bb.6: # %._crit_edge30
# in Loop: Header=BB3_2 Depth=1
incq %r10
addq %rcx, %rdi
cmpq %r9, %r10
jne .LBB3_2
.LBB3_7: # %._crit_edge32
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z7matmultPKfiS0_iPfii, .Lfunc_end3-_Z7matmultPKfiS0_iPfii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z6matgenPfii
.LCPI4_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z6matgenPfii
.p2align 4, 0x90
.type _Z6matgenPfii,@function
_Z6matgenPfii: # @_Z6matgenPfii
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB4_6
# %bb.1: # %.preheader.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movslq %esi, %r14
movl %edx, %r15d
shlq $2, %r14
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_3 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_3: # Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI4_0(%rip), %xmm0
movss %xmm0, 12(%rsp) # 4-byte Spill
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
addss 12(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, (%rbx,%r13,4)
incq %r13
cmpq %r13, %r15
jne .LBB4_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
incq %r12
addq %r14, %rbx
cmpq %r15, %r12
jne .LBB4_2
# %bb.5:
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.LBB4_6: # %._crit_edge13
retq
.Lfunc_end4:
.size _Z6matgenPfii, .Lfunc_end4-_Z6matgenPfii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI5_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI5_2:
.long 0x49742400 # float 1.0E+6
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI5_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI5_3:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI5_4:
.quad 0x41cdcd6500000000 # double 1.0E+9
.LCPI5_5:
.quad 0x41ddcd6500000000 # double 2.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %r15
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %rbx
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %r14
xorl %r13d, %r13d
xorl %edi, %edi
callq srand
movq %r15, %rbp
.p2align 4, 0x90
.LBB5_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB5_2 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_2: # Parent Loop BB5_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI5_0(%rip), %xmm0
movss %xmm0, 12(%rsp) # 4-byte Spill
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
addss 12(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, (%rbp,%r12,4)
incq %r12
cmpq $1000, %r12 # imm = 0x3E8
jne .LBB5_2
# %bb.3: # %._crit_edge.i
# in Loop: Header=BB5_1 Depth=1
incq %r13
addq $4000, %rbp # imm = 0xFA0
cmpq $1000, %r13 # imm = 0x3E8
jne .LBB5_1
# %bb.4: # %.preheader.i38.preheader
xorl %r13d, %r13d
movq 16(%rsp), %rbp # 8-byte Reload
.p2align 4, 0x90
.LBB5_5: # %.preheader.i38
# =>This Loop Header: Depth=1
# Child Loop BB5_6 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_6: # Parent Loop BB5_5 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI5_0(%rip), %xmm0
movss %xmm0, 12(%rsp) # 4-byte Spill
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
addss 12(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, (%rbp,%r12,4)
incq %r12
cmpq $1000, %r12 # imm = 0x3E8
jne .LBB5_6
# %bb.7: # %._crit_edge.i43
# in Loop: Header=BB5_5 Depth=1
incq %r13
addq $4000, %rbp # imm = 0xFA0
cmpq $1000, %r13 # imm = 0x3E8
jne .LBB5_5
# %bb.8: # %_Z6matgenPfii.exit46
movl $1000, (%rsp) # imm = 0x3E8
movq %r15, %rdi
movq 16(%rsp), %r12 # 8-byte Reload
movq %r12, %rdx
movq %rbx, %r8
callq _Z11matmultCUDAPKfiS0_iPfii
movq %rax, %r13
xorl %eax, %eax
.p2align 4, 0x90
.LBB5_9: # %.preheader26.i
# =>This Loop Header: Depth=1
# Child Loop BB5_10 Depth 2
# Child Loop BB5_11 Depth 3
imulq $4000, %rax, %rcx # imm = 0xFA0
addq %r14, %rcx
movq %r12, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB5_10: # %.preheader.i47
# Parent Loop BB5_9 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB5_11 Depth 3
xorps %xmm0, %xmm0
movq %rdx, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB5_11: # Parent Loop BB5_9 Depth=1
# Parent Loop BB5_10 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r15,%r8,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rdi), %xmm1
cvtss2sd %xmm1, %xmm1
addsd %xmm1, %xmm0
incq %r8
addq $4000, %rdi # imm = 0xFA0
cmpq $1000, %r8 # imm = 0x3E8
jne .LBB5_11
# %bb.12: # %._crit_edge.i51
# in Loop: Header=BB5_10 Depth=2
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rcx,%rsi,4)
incq %rsi
addq $4, %rdx
cmpq $1000, %rsi # imm = 0x3E8
jne .LBB5_10
# %bb.13: # %._crit_edge30.i
# in Loop: Header=BB5_9 Depth=1
incq %rax
addq $4000, %r15 # imm = 0xFA0
cmpq $1000, %rax # imm = 0x3E8
jne .LBB5_9
# %bb.14: # %.preheader.i52.preheader
xorps %xmm0, %xmm0
xorl %eax, %eax
movaps .LCPI5_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
xorps %xmm3, %xmm3
xorps %xmm2, %xmm2
jmp .LBB5_15
.p2align 4, 0x90
.LBB5_19: # %._crit_edge.i56
# in Loop: Header=BB5_15 Depth=1
incq %rax
addq $4000, %rbx # imm = 0xFA0
addq $4000, %r14 # imm = 0xFA0
cmpq $1000, %rax # imm = 0x3E8
je .LBB5_20
.LBB5_15: # %.preheader.i52
# =>This Loop Header: Depth=1
# Child Loop BB5_16 Depth 2
xorl %ecx, %ecx
jmp .LBB5_16
.p2align 4, 0x90
.LBB5_18: # in Loop: Header=BB5_16 Depth=2
incq %rcx
cmpq $1000, %rcx # imm = 0x3E8
je .LBB5_19
.LBB5_16: # Parent Loop BB5_15 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%rcx,4), %xmm4 # xmm4 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm4
jne .LBB5_17
jnp .LBB5_18
.LBB5_17: # in Loop: Header=BB5_16 Depth=2
movss (%rbx,%rcx,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
subss %xmm4, %xmm5
divss %xmm4, %xmm5
andps %xmm1, %xmm5
addss %xmm5, %xmm2
maxss %xmm3, %xmm5
movaps %xmm5, %xmm3
jmp .LBB5_18
.LBB5_20: # %_Z11compare_matPKfiS0_ii.exit
xorps %xmm0, %xmm0
cvtss2sd %xmm3, %xmm0
divss .LCPI5_2(%rip), %xmm2
xorps %xmm1, %xmm1
cvtss2sd %xmm2, %xmm1
movl $.L.str, %edi
movb $2, %al
callq printf
xorps %xmm0, %xmm0
cvtsi2sd %r13, %xmm0
divsd .LCPI5_3(%rip), %xmm0
movsd .LCPI5_4(%rip), %xmm2 # xmm2 = mem[0],zero
mulsd %xmm0, %xmm2
movsd .LCPI5_5(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm2, %xmm1
movl $.L.str.1, %edi
movb $2, %al
callq printf
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL11matMultCUDAPKfmS0_mPfmi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _ZL11matMultCUDAPKfmS0_mPfmi,@object # @_ZL11matMultCUDAPKfmS0_mPfmi
.section .rodata,"a",@progbits
.p2align 3, 0x0
_ZL11matMultCUDAPKfmS0_mPfmi:
.quad _ZL26__device_stub__matMultCUDAPKfmS0_mPfmi
.size _ZL11matMultCUDAPKfmS0_mPfmi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Max error: %g Average error: %g\n"
.size .L.str, 33
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Time used: %.2f (%.2lf GFLOPS)\n"
.size .L.str.1, 32
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_ZL11matMultCUDAPKfmS0_mPfmi"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZL26__device_stub__matMultCUDAPKfmS0_mPfmi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZL11matMultCUDAPKfmS0_mPfmi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
void fill_matrix(double *mat, unsigned numRows, unsigned numCols)
{
for(unsigned i=0; i < numRows; i++)
for(unsigned j=0; j < numCols; j++)
{
mat[i*numCols + j] = i*2.1f + j*3.2f;
}
}
void print_matrix_to_file(double *mat, unsigned numRows, unsigned numCols)
{
const char *fname = "assignment2_3_out";
FILE *f = fopen(fname, "w");
for(unsigned i=0; i < numRows; i++)
{
for(unsigned j=0; j < numCols; j++)
fprintf(f,"%4.4f ", mat[i*numCols + j]);
fprintf(f,"\n");
}
fclose(f); }
template<int TILE_WIDTH>
__global__ void MatrixMulKernel_col_maj(double* M, double* N, double* P, int Width) {
extern __shared__ double buffer[];
double *ds_M = &buffer[0]; // TILE_WIDTH WIDTH
double *ds_N = &buffer[TILE_WIDTH*Width]; // WIDTH TILE_WIDTH
//__shared__ float ds_M[Width][Width];
//__shared__ float ds_N[Width][Width];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
int Row = by * blockDim.y + ty;
int Col = bx * blockDim.x + tx;
// Loop over the M and N tiles required to compute the P element
for (int p = 0; p < Width/TILE_WIDTH; ++p) {
// Collaborative loading of M and N tiles into shared memory
ds_M[ty*Width + tx + p*blockDim.x ] = M[Row*Width + p*TILE_WIDTH+tx];
ds_N[ty*TILE_WIDTH + blockDim.y*TILE_WIDTH*p + tx] = N[(p*TILE_WIDTH+ty)*Width + Col];
__syncthreads();
}
double Pvalue = 0;
for (int i = 0; i < TILE_WIDTH; ++i){
Pvalue += ds_M[ty*Width + i] * ds_N[i*Width + tx];
}
__syncthreads();
P[Row*Width+Col] = Pvalue;
}
int main(int argc,char **argv) {
int N_ll[2]; int N;
int loop, loop1, loop2; // loop variables
float time_spent;
N_ll[0]=16; N_ll[1]=8192;
for (loop=0;loop<2;loop++){
N=N_ll[loop];
size_t size = N *N* sizeof(double);
double*h_matA = (double*)malloc(size);
double*h_matB = (double*)malloc(size);
double*h_matC = (double*)malloc(size); // result
fill_matrix(h_matA,N,N);
fill_matrix(h_matB,N,N);
printf("\nMatrix A (first 10*10 inputs)\n");
for(loop1 = 0; loop1 < 10; loop1++){
for (loop2=0;loop2 < 10; loop2++)
printf("%f ", *(h_matA + N*loop1 + loop2));
printf("\n");
}
printf("\n\nMatrix B (first 10*10 inputs)\n");
for(loop1 = 0; loop1 < 10; loop1++){
for (loop2=0;loop2 < 10; loop2++)
printf("%f ", *(h_matB + N*loop1 + loop2));
printf("\n");
}
double* d_matA; cudaMalloc(&d_matA, size);
double* d_matB; cudaMalloc(&d_matB, size);
double* d_matC; cudaMalloc(&d_matC, size);
//GPU timing
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// Copy vectors from host memory to device memory
cudaMemcpy(d_matA, h_matA, size,cudaMemcpyHostToDevice);
cudaMemcpy(d_matB, h_matB, size,cudaMemcpyHostToDevice);
// Invoke kernel
dim3 threadsPerBlock (16,16);
dim3 blocksPerGrid ((N + threadsPerBlock.x - 1) /threadsPerBlock.x,(N + threadsPerBlock.y - 1) /threadsPerBlock.y);
cudaEventRecord(start, 0);
size_t blocksize = 2 * N * 16;
(MatrixMulKernel_col_maj<16>)<<<blocksPerGrid, threadsPerBlock, sizeof(double)*blocksize>>>(d_matA,d_matB, d_matC, N);
cudaError_t err1 = cudaPeekAtLastError();
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time_spent, start, stop);
printf("\nTime spent in col maj %f\n",time_spent);
// h_C contains the result in host memory
cudaMemcpy(h_matC, d_matC, size,cudaMemcpyDeviceToHost);
printf("\n\nMatrix C (first 10*10 outputs)\n");
for(loop1 = 0; loop1 < 10; loop1++){
for (loop2=0;loop2 < 10; loop2++)
printf("%f ", *(h_matC + N*loop1 + loop2));
printf("\n");
}
// Log outputs
printf("\nWritting to file assignment_2_1_out as Mat C");
print_matrix_to_file(h_matC,N,N);
// Free device memory
cudaFree(d_matA);
cudaFree(d_matB);
cudaFree(d_matC);
// Free host memory
free(h_matA);
free(h_matB);
free(h_matC);
}
return 0;
} | code for sm_80
Function : _Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e240000002200 */
/*0050*/ ISETP.GE.AND P0, PT, R2, 0x10, PT ; /* 0x000000100200780c */
/* 0x000fe40003f06270 */
/*0060*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e620000002500 */
/*0070*/ SHF.R.S32.HI R7, RZ, 0x1f, R2 ; /* 0x0000001fff077819 */
/* 0x000fc60000011402 */
/*0080*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0090*/ LEA.HI R7, R7, c[0x0][0x178], RZ, 0x4 ; /* 0x00005e0007077a11 */
/* 0x000fe200078f20ff */
/*00a0*/ IMAD R4, R5, c[0x0][0x4], R0 ; /* 0x0000010005047a24 */
/* 0x001fe400078e0200 */
/*00b0*/ IMAD R5, R6, c[0x0][0x0], R3 ; /* 0x0000000006057a24 */
/* 0x002fe200078e0203 */
/*00c0*/ SHF.L.U32 R6, R2, 0x4, RZ ; /* 0x0000000402067819 */
/* 0x000fe400000006ff */
/*00d0*/ @!P0 BRA 0x6a0 ; /* 0x000005c000008947 */
/* 0x000fea0003800000 */
/*00e0*/ SHF.R.S32.HI R8, RZ, 0x4, R7 ; /* 0x00000004ff087819 */
/* 0x000fe20000011407 */
/*00f0*/ IMAD.MOV.U32 R27, RZ, RZ, RZ ; /* 0x000000ffff1b7224 */
/* 0x000fc600078e00ff */
/*0100*/ IADD3 R9, R8.reuse, -0x1, RZ ; /* 0xffffffff08097810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R7, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308077812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P1, PT, R9, 0x3, PT ; /* 0x000000030900780c */
/* 0x000fe40003f26070 */
/*0130*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fd60003f05270 */
/*0140*/ @!P1 BRA 0x490 ; /* 0x0000034000009947 */
/* 0x000fea0003800000 */
/*0150*/ IMAD R13, R0, 0x10, R3.reuse ; /* 0x00000010000d7824 */
/* 0x100fe200078e0203 */
/*0160*/ IADD3 R8, -R8, R7, RZ ; /* 0x0000000708087210 */
/* 0x000fe20007ffe1ff */
/*0170*/ IMAD R9, R4, c[0x0][0x178], R3.reuse ; /* 0x00005e0004097a24 */
/* 0x100fe400078e0203 */
/*0180*/ IMAD R12, R0, c[0x0][0x178], R3 ; /* 0x00005e00000c7a24 */
/* 0x000fe200078e0203 */
/*0190*/ IADD3 R13, R6, R13, RZ ; /* 0x0000000d060d7210 */
/* 0x000fe20007ffe0ff */
/*01a0*/ IMAD R11, R0, c[0x0][0x178], R5 ; /* 0x00005e00000b7a24 */
/* 0x000fe200078e0205 */
/*01b0*/ IADD3 R9, R9, 0x30, RZ ; /* 0x0000003009097810 */
/* 0x000fe20007ffe0ff */
/*01c0*/ IMAD.MOV.U32 R27, RZ, RZ, RZ ; /* 0x000000ffff1b7224 */
/* 0x000fe200078e00ff */
/*01d0*/ SHF.L.U32 R12, R12, 0x3, RZ ; /* 0x000000030c0c7819 */
/* 0x000fe200000006ff */
/*01e0*/ IMAD.SHL.U32 R13, R13, 0x8, RZ ; /* 0x000000080d0d7824 */
/* 0x000fc400078e00ff */
/*01f0*/ HFMA2.MMA R10, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0a7435 */
/* 0x000fe200000001ff */
/*0200*/ IADD3 R15, R9, -0x30, RZ ; /* 0xffffffd0090f7810 */
/* 0x000fd20007ffe0ff */
/*0210*/ IMAD.WIDE R14, R15, R10, c[0x0][0x160] ; /* 0x000058000f0e7625 */
/* 0x000fc800078e020a */
/*0220*/ IMAD.WIDE R28, R11, R10, c[0x0][0x168] ; /* 0x00005a000b1c7625 */
/* 0x001fe200078e020a */
/*0230*/ LDG.E.64 R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x000ea8000c1e1b00 */
/*0240*/ LDG.E.64 R20, [R28.64] ; /* 0x000000041c147981 */
/* 0x000ee2000c1e1b00 */
/*0250*/ IMAD.WIDE R24, R6, 0x8, R28 ; /* 0x0000000806187825 */
/* 0x000fc600078e021c */
/*0260*/ STS.64 [R12], R22 ; /* 0x000000160c007388 */
/* 0x004fe80000000a00 */
/*0270*/ STS.64 [R13], R20 ; /* 0x000000140d007388 */
/* 0x0081e80000000a00 */
/*0280*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0290*/ LDG.E.64 R16, [R14.64+0x80] ; /* 0x000080040e107981 */
/* 0x000ea8000c1e1b00 */
/*02a0*/ LDG.E.64 R18, [R24.64] ; /* 0x0000000418127981 */
/* 0x000ee2000c1e1b00 */
/*02b0*/ IMAD.MOV.U32 R26, RZ, RZ, c[0x0][0x4] ; /* 0x00000100ff1a7624 */
/* 0x000fc400078e00ff */
/*02c0*/ IMAD R29, R10, c[0x0][0x0], R12 ; /* 0x000000000a1d7a24 */
/* 0x000fc600078e020c */
/*02d0*/ LEA R28, R26, R13, 0x7 ; /* 0x0000000d1a1c7211 */
/* 0x000fe200078e38ff */
/*02e0*/ IMAD.WIDE R12, R6, 0x8, R24 ; /* 0x00000008060c7825 */
/* 0x001fe200078e0218 */
/*02f0*/ STS.64 [R29], R16 ; /* 0x000000101d007388 */
/* 0x0041e80000000a00 */
/*0300*/ STS.64 [R28], R18 ; /* 0x000000121c007388 */
/* 0x0083e80000000a00 */
/*0310*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0320*/ LDG.E.64 R22, [R14.64+0x100] ; /* 0x000100040e167981 */
/* 0x000ea8000c1e1b00 */
/*0330*/ LDG.E.64 R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000ee2000c1e1b00 */
/*0340*/ IMAD R29, R10, c[0x0][0x0], R29 ; /* 0x000000000a1d7a24 */
/* 0x001fc400078e021d */
/*0350*/ IMAD R19, R26, 0x80, R28 ; /* 0x000000801a137824 */
/* 0x002fe400078e021c */
/*0360*/ IMAD.WIDE R24, R6, 0x8, R12 ; /* 0x0000000806187825 */
/* 0x000fe200078e020c */
/*0370*/ STS.64 [R29], R22 ; /* 0x000000161d007388 */
/* 0x0041e80000000a00 */
/*0380*/ STS.64 [R19], R20 ; /* 0x0000001413007388 */
/* 0x0081e80000000a00 */
/*0390*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03a0*/ LDG.E.64 R16, [R14.64+0x180] ; /* 0x000180040e107981 */
/* 0x000ea8000c1e1b00 */
/*03b0*/ LDG.E.64 R24, [R24.64] ; /* 0x0000000418187981 */
/* 0x000ee2000c1e1b00 */
/*03c0*/ IADD3 R27, R27, 0x4, RZ ; /* 0x000000041b1b7810 */
/* 0x000fe20007ffe0ff */
/*03d0*/ IMAD R18, R10, c[0x0][0x0], R29 ; /* 0x000000000a127a24 */
/* 0x000fe200078e021d */
/*03e0*/ LEA R28, R26, R19, 0x7 ; /* 0x000000131a1c7211 */
/* 0x000fe200078e38ff */
/*03f0*/ IMAD R11, R2, 0x40, R11 ; /* 0x00000040020b7824 */
/* 0x000fe200078e020b */
/*0400*/ IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009097810 */
/* 0x000fe20007ffe0ff */
/*0410*/ IMAD.IADD R12, R8, 0x1, R27 ; /* 0x00000001080c7824 */
/* 0x000fe200078e021b */
/*0420*/ LEA R13, R26, R28, 0x7 ; /* 0x0000001c1a0d7211 */
/* 0x000fc800078e38ff */
/*0430*/ ISETP.NE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f25270 */
/*0440*/ IMAD R12, R10, c[0x0][0x0], R18 ; /* 0x000000000a0c7a24 */
/* 0x000fe200078e0212 */
/*0450*/ STS.64 [R18], R16 ; /* 0x0000001012007388 */
/* 0x0041e80000000a00 */
/*0460*/ STS.64 [R28], R24 ; /* 0x000000181c007388 */
/* 0x0081e80000000a00 */
/*0470*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0480*/ @P1 BRA 0x1f0 ; /* 0xfffffd6000001947 */
/* 0x000fea000383ffff */
/*0490*/ @!P0 BRA 0x6a0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*04a0*/ IMAD R8, R4, c[0x0][0x178], R3 ; /* 0x00005e0004087a24 */
/* 0x000fe200078e0203 */
/*04b0*/ MOV R10, 0x8 ; /* 0x00000008000a7802 */
/* 0x000fe20000000f00 */
/*04c0*/ IMAD R12, R27.reuse, c[0x0][0x4], R0 ; /* 0x000001001b0c7a24 */
/* 0x040fe200078e0200 */
/*04d0*/ IADD3 R11, R6, R3, RZ ; /* 0x00000003060b7210 */
/* 0x000fe20007ffe0ff */
/*04e0*/ IMAD R9, R27, 0x10, R8 ; /* 0x000000101b097824 */
/* 0x000fc400078e0208 */
/*04f0*/ IMAD R13, R27.reuse, c[0x0][0x0], R3 ; /* 0x000000001b0d7a24 */
/* 0x040fe200078e0203 */
/*0500*/ LEA R11, R12, R11, 0x4 ; /* 0x0000000b0c0b7211 */
/* 0x000fe200078e20ff */
/*0510*/ IMAD R14, R27, 0x10, R0 ; /* 0x000000101b0e7824 */
/* 0x000fe400078e0200 */
/*0520*/ IMAD.WIDE R8, R9, R10, c[0x0][0x160] ; /* 0x0000580009087625 */
/* 0x000fe200078e020a */
/*0530*/ SHF.L.U32 R11, R11, 0x3, RZ ; /* 0x000000030b0b7819 */
/* 0x000fc600000006ff */
/*0540*/ IMAD R13, R0, c[0x0][0x178], R13 ; /* 0x00005e00000d7a24 */
/* 0x000fe200078e020d */
/*0550*/ MOV R19, R9 ; /* 0x0000000900137202 */
/* 0x001fe20000000f00 */
/*0560*/ IMAD R15, R14, c[0x0][0x178], R5 ; /* 0x00005e000e0f7a24 */
/* 0x000fe400078e0205 */
/*0570*/ IMAD.MOV.U32 R16, RZ, RZ, R8 ; /* 0x000000ffff107224 */
/* 0x000fe400078e0008 */
/*0580*/ IMAD.SHL.U32 R17, R13, 0x8, RZ ; /* 0x000000080d117824 */
/* 0x000fe400078e00ff */
/*0590*/ IMAD.WIDE R8, R15, R10, c[0x0][0x168] ; /* 0x00005a000f087625 */
/* 0x000fc800078e020a */
/*05a0*/ MOV R12, R16 ; /* 0x00000010000c7202 */
/* 0x000fe20000000f00 */
/*05b0*/ LDG.E.64 R14, [R8.64] ; /* 0x00000004080e7981 */
/* 0x0000a2000c1e1b00 */
/*05c0*/ MOV R13, R19 ; /* 0x00000013000d7202 */
/* 0x000fcc0000000f00 */
/*05d0*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee2000c1e1b00 */
/*05e0*/ IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07077810 */
/* 0x000fc80007ffe0ff */
/*05f0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*0600*/ IMAD.MOV.U32 R18, RZ, RZ, c[0x0][0x4] ; /* 0x00000100ff127624 */
/* 0x000fe200078e00ff */
/*0610*/ IADD3 R16, P1, R16, 0x80, RZ ; /* 0x0000008010107810 */
/* 0x000fe20007f3e0ff */
/*0620*/ IMAD.WIDE R8, R6, 0x8, R8 ; /* 0x0000000806087825 */
/* 0x001fc600078e0208 */
/*0630*/ IADD3.X R19, RZ, R19, RZ, P1, !PT ; /* 0x00000013ff137210 */
/* 0x000fe20000ffe4ff */
/*0640*/ STS.64 [R17], R12 ; /* 0x0000000c11007388 */
/* 0x0081e80000000a00 */
/*0650*/ STS.64 [R11], R14 ; /* 0x0000000e0b007388 */
/* 0x0043e20000000a00 */
/*0660*/ IMAD R17, R10, c[0x0][0x0], R17 ; /* 0x000000000a117a24 */
/* 0x001fe200078e0211 */
/*0670*/ LEA R11, R18, R11, 0x7 ; /* 0x0000000b120b7211 */
/* 0x002fe400078e38ff */
/*0680*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0690*/ @P0 BRA 0x5a0 ; /* 0xffffff0000000947 */
/* 0x000fea000383ffff */
/*06a0*/ IMAD.IADD R6, R6, 0x1, R3 ; /* 0x0000000106067824 */
/* 0x000fe400078e0203 */
/*06b0*/ IMAD R0, R0, c[0x0][0x178], RZ ; /* 0x00005e0000007a24 */
/* 0x000fc400078e02ff */
/*06c0*/ IMAD R4, R4, c[0x0][0x178], R5 ; /* 0x00005e0004047a24 */
/* 0x000fe200078e0205 */
/*06d0*/ SHF.L.U32 R3, R6, 0x3, RZ ; /* 0x0000000306037819 */
/* 0x000fe400000006ff */
/*06e0*/ LDS.64 R6, [R6.X8] ; /* 0x0000000006067984 */
/* 0x000fe40000008a00 */
/*06f0*/ LEA R3, R2.reuse, R3, 0x3 ; /* 0x0000000302037211 */
/* 0x040fe400078e18ff */
/*0700*/ LDS.64 R8, [R0.X8] ; /* 0x0000000000087984 */
/* 0x000e660000008a00 */
/*0710*/ IMAD R25, R2.reuse, 0x8, R3 ; /* 0x0000000802197824 */
/* 0x041fe200078e0203 */
/*0720*/ LDS.64 R10, [R0.X8+0x8] ; /* 0x00000800000a7984 */
/* 0x000fe80000008a00 */
/*0730*/ LDS.64 R12, [R3] ; /* 0x00000000030c7984 */
/* 0x0000a20000000a00 */
/*0740*/ LEA R27, R2, R25, 0x3 ; /* 0x00000019021b7211 */
/* 0x000fc600078e18ff */
/*0750*/ LDS.64 R18, [R0.X8+0x10] ; /* 0x0000100000127984 */
/* 0x000fe20000008a00 */
/*0760*/ LEA R29, R2, R27, 0x3 ; /* 0x0000001b021d7211 */
/* 0x000fc600078e18ff */
/*0770*/ LDS.64 R20, [R25] ; /* 0x0000000019147984 */
/* 0x0007240000000a00 */
/*0780*/ IMAD R3, R2.reuse, 0x8, R29 ; /* 0x0000000802037824 */
/* 0x041fe400078e021d */
/*0790*/ LDS.64 R14, [R0.X8+0x18] ; /* 0x00001800000e7984 */
/* 0x000fe80000008a00 */
/*07a0*/ LDS.64 R16, [R27] ; /* 0x000000001b107984 */
/* 0x0001620000000a00 */
/*07b0*/ LEA R25, R2, R3, 0x3 ; /* 0x0000000302197211 */
/* 0x008fc800078e18ff */
/*07c0*/ LEA R27, R2, R25, 0x3 ; /* 0x00000019021b7211 */
/* 0x001fe200078e18ff */
/*07d0*/ DFMA R22, R6, R8, RZ ; /* 0x000000080616722b */
/* 0x0020a400000000ff */
/*07e0*/ LDS.64 R6, [R0.X8+0x20] ; /* 0x0000200000067984 */
/* 0x001fe80000008a00 */
/*07f0*/ LDS.64 R8, [R29] ; /* 0x000000001d087984 */
/* 0x0000620000000a00 */
/*0800*/ DFMA R22, R12, R10, R22 ; /* 0x0000000a0c16722b */
/* 0x0045060000000016 */
/*0810*/ LDS.64 R10, [R0.X8+0x28] ; /* 0x00002800000a7984 */
/* 0x004fe80000008a00 */
/*0820*/ LDS.64 R12, [R3] ; /* 0x00000000030c7984 */
/* 0x0004e20000000a00 */
/*0830*/ IMAD R29, R2.reuse, 0x8, R27 ; /* 0x00000008021d7824 */
/* 0x041fe200078e021b */
/*0840*/ DFMA R22, R20, R18, R22 ; /* 0x000000121416722b */
/* 0x0101640000000016 */
/*0850*/ LDS.64 R18, [R0.X8+0x30] ; /* 0x0000300000127984 */
/* 0x001fe80000008a00 */
/*0860*/ LDS.64 R20, [R25] ; /* 0x0000000019147984 */
/* 0x0001220000000a00 */
/*0870*/ LEA R3, R2, R29, 0x3 ; /* 0x0000001d02037211 */
/* 0x004fe200078e18ff */
/*0880*/ DFMA R22, R16, R14, R22 ; /* 0x0000000e1016722b */
/* 0x0204440000000016 */
/*0890*/ LDS.64 R14, [R0.X8+0x38] ; /* 0x00003800000e7984 */
/* 0x004fe80000008a00 */
/*08a0*/ LDS.64 R16, [R27] ; /* 0x000000001b107984 */
/* 0x0005620000000a00 */
/*08b0*/ LEA R25, R2, R3, 0x3 ; /* 0x0000000302197211 */
/* 0x001fca00078e18ff */
/*08c0*/ IMAD R27, R2, 0x8, R25 ; /* 0x00000008021b7824 */
/* 0x004fe200078e0219 */
/*08d0*/ DFMA R22, R8, R6, R22 ; /* 0x000000060816722b */
/* 0x0020e40000000016 */
/*08e0*/ LDS.64 R6, [R0.X8+0x40] ; /* 0x0000400000067984 */
/* 0x001fe80000008a00 */
/*08f0*/ LDS.64 R8, [R29] ; /* 0x000000001d087984 */
/* 0x0000620000000a00 */
/*0900*/ DFMA R22, R12, R10, R22 ; /* 0x0000000a0c16722b */
/* 0x0085060000000016 */
/*0910*/ LDS.64 R10, [R0.X8+0x48] ; /* 0x00004800000a7984 */
/* 0x004fe80000008a00 */
/*0920*/ LDS.64 R12, [R3] ; /* 0x00000000030c7984 */
/* 0x000ea20000000a00 */
/*0930*/ LEA R29, R2.reuse, R27, 0x3 ; /* 0x0000001b021d7211 */
/* 0x041fe200078e18ff */
/*0940*/ DFMA R22, R20, R18, R22 ; /* 0x000000121416722b */
/* 0x0101640000000016 */
/*0950*/ LDS.64 R20, [R0.X8+0x50] ; /* 0x0000500000147984 */
/* 0x001fe20000008a00 */
/*0960*/ LEA R26, R2, R29, 0x3 ; /* 0x0000001d021a7211 */
/* 0x000fc600078e18ff */
/*0970*/ LDS.64 R18, [R25] ; /* 0x0000000019127984 */
/* 0x000e220000000a00 */
/*0980*/ DFMA R22, R16, R14, R22 ; /* 0x0000000e1016722b */
/* 0x0206620000000016 */
/*0990*/ IMAD R28, R2.reuse, 0x8, R26 ; /* 0x00000008021c7824 */
/* 0x040fe400078e021a */
/*09a0*/ LDS.64 R14, [R0.X8+0x58] ; /* 0x00005800000e7984 */
/* 0x008fe80000008a00 */
/*09b0*/ LDS.64 R16, [R27] ; /* 0x000000001b107984 */
/* 0x0007280000000a00 */
/*09c0*/ LDS.64 R24, [R0.X8+0x78] ; /* 0x0000780000187984 */
/* 0x000fe20000008a00 */
/*09d0*/ LEA R27, R2, R28, 0x3 ; /* 0x0000001c021b7211 */
/* 0x008fca00078e18ff */
/*09e0*/ LDS.64 R2, [R27] ; /* 0x000000001b027984 */
/* 0x000fe20000000a00 */
/*09f0*/ DFMA R22, R8, R6, R22 ; /* 0x000000060816722b */
/* 0x0022860000000016 */
/*0a00*/ LDS.64 R8, [R0.X8+0x60] ; /* 0x0000600000087984 */
/* 0x002fe80000008a00 */
/*0a10*/ LDS.64 R6, [R29] ; /* 0x000000001d067984 */
/* 0x000e620000000a00 */
/*0a20*/ DFMA R22, R12, R10, R22 ; /* 0x0000000a0c16722b */
/* 0x0044060000000016 */
/*0a30*/ LDS.64 R12, [R0.X8+0x68] ; /* 0x00006800000c7984 */
/* 0x004fe80000008a00 */
/*0a40*/ LDS.64 R10, [R26] ; /* 0x000000001a0a7984 */
/* 0x000ea20000000a00 */
/*0a50*/ DFMA R18, R18, R20, R22 ; /* 0x000000141212722b */
/* 0x0011060000000016 */
/*0a60*/ LDS.64 R22, [R0.X8+0x70] ; /* 0x0000700000167984 */
/* 0x001fe80000008a00 */
/*0a70*/ LDS.64 R20, [R28] ; /* 0x000000001c147984 */
/* 0x000e220000000a00 */
/*0a80*/ DFMA R14, R16, R14, R18 ; /* 0x0000000e100e722b */
/* 0x010e4c0000000012 */
/*0a90*/ DFMA R6, R6, R8, R14 ; /* 0x000000080606722b */
/* 0x0022a4000000000e */
/*0aa0*/ MOV R9, 0x8 ; /* 0x0000000800097802 */
/* 0x002fca0000000f00 */
/*0ab0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe200078e0209 */
/*0ac0*/ DFMA R6, R10, R12, R6 ; /* 0x0000000c0a06722b */
/* 0x004e0c0000000006 */
/*0ad0*/ DFMA R6, R20, R22, R6 ; /* 0x000000161406722b */
/* 0x001e0c0000000006 */
/*0ae0*/ DFMA R2, R2, R24, R6 ; /* 0x000000180202722b */
/* 0x001e220000000006 */
/*0af0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0b00*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x001fe2000c101b04 */
/*0b10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b20*/ BRA 0xb20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
void fill_matrix(double *mat, unsigned numRows, unsigned numCols)
{
for(unsigned i=0; i < numRows; i++)
for(unsigned j=0; j < numCols; j++)
{
mat[i*numCols + j] = i*2.1f + j*3.2f;
}
}
void print_matrix_to_file(double *mat, unsigned numRows, unsigned numCols)
{
const char *fname = "assignment2_3_out";
FILE *f = fopen(fname, "w");
for(unsigned i=0; i < numRows; i++)
{
for(unsigned j=0; j < numCols; j++)
fprintf(f,"%4.4f ", mat[i*numCols + j]);
fprintf(f,"\n");
}
fclose(f); }
template<int TILE_WIDTH>
__global__ void MatrixMulKernel_col_maj(double* M, double* N, double* P, int Width) {
extern __shared__ double buffer[];
double *ds_M = &buffer[0]; // TILE_WIDTH WIDTH
double *ds_N = &buffer[TILE_WIDTH*Width]; // WIDTH TILE_WIDTH
//__shared__ float ds_M[Width][Width];
//__shared__ float ds_N[Width][Width];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
int Row = by * blockDim.y + ty;
int Col = bx * blockDim.x + tx;
// Loop over the M and N tiles required to compute the P element
for (int p = 0; p < Width/TILE_WIDTH; ++p) {
// Collaborative loading of M and N tiles into shared memory
ds_M[ty*Width + tx + p*blockDim.x ] = M[Row*Width + p*TILE_WIDTH+tx];
ds_N[ty*TILE_WIDTH + blockDim.y*TILE_WIDTH*p + tx] = N[(p*TILE_WIDTH+ty)*Width + Col];
__syncthreads();
}
double Pvalue = 0;
for (int i = 0; i < TILE_WIDTH; ++i){
Pvalue += ds_M[ty*Width + i] * ds_N[i*Width + tx];
}
__syncthreads();
P[Row*Width+Col] = Pvalue;
}
int main(int argc,char **argv) {
int N_ll[2]; int N;
int loop, loop1, loop2; // loop variables
float time_spent;
N_ll[0]=16; N_ll[1]=8192;
for (loop=0;loop<2;loop++){
N=N_ll[loop];
size_t size = N *N* sizeof(double);
double*h_matA = (double*)malloc(size);
double*h_matB = (double*)malloc(size);
double*h_matC = (double*)malloc(size); // result
fill_matrix(h_matA,N,N);
fill_matrix(h_matB,N,N);
printf("\nMatrix A (first 10*10 inputs)\n");
for(loop1 = 0; loop1 < 10; loop1++){
for (loop2=0;loop2 < 10; loop2++)
printf("%f ", *(h_matA + N*loop1 + loop2));
printf("\n");
}
printf("\n\nMatrix B (first 10*10 inputs)\n");
for(loop1 = 0; loop1 < 10; loop1++){
for (loop2=0;loop2 < 10; loop2++)
printf("%f ", *(h_matB + N*loop1 + loop2));
printf("\n");
}
double* d_matA; cudaMalloc(&d_matA, size);
double* d_matB; cudaMalloc(&d_matB, size);
double* d_matC; cudaMalloc(&d_matC, size);
//GPU timing
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// Copy vectors from host memory to device memory
cudaMemcpy(d_matA, h_matA, size,cudaMemcpyHostToDevice);
cudaMemcpy(d_matB, h_matB, size,cudaMemcpyHostToDevice);
// Invoke kernel
dim3 threadsPerBlock (16,16);
dim3 blocksPerGrid ((N + threadsPerBlock.x - 1) /threadsPerBlock.x,(N + threadsPerBlock.y - 1) /threadsPerBlock.y);
cudaEventRecord(start, 0);
size_t blocksize = 2 * N * 16;
(MatrixMulKernel_col_maj<16>)<<<blocksPerGrid, threadsPerBlock, sizeof(double)*blocksize>>>(d_matA,d_matB, d_matC, N);
cudaError_t err1 = cudaPeekAtLastError();
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time_spent, start, stop);
printf("\nTime spent in col maj %f\n",time_spent);
// h_C contains the result in host memory
cudaMemcpy(h_matC, d_matC, size,cudaMemcpyDeviceToHost);
printf("\n\nMatrix C (first 10*10 outputs)\n");
for(loop1 = 0; loop1 < 10; loop1++){
for (loop2=0;loop2 < 10; loop2++)
printf("%f ", *(h_matC + N*loop1 + loop2));
printf("\n");
}
// Log outputs
printf("\nWritting to file assignment_2_1_out as Mat C");
print_matrix_to_file(h_matC,N,N);
// Free device memory
cudaFree(d_matA);
cudaFree(d_matB);
cudaFree(d_matC);
// Free host memory
free(h_matA);
free(h_matB);
free(h_matC);
}
return 0;
} | .file "tmpxft_000f1b00_00000000-6_ee16b068_3.cudafe1.cpp"
.text
#APP
#NO_APP
.section .text._Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i,"axG",@progbits,_Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i,comdat
.weak _Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i
.type _Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i, @function
_Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i:
.LFB2136:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 4(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2136:
.size _Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i, .-_Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11fill_matrixPdjj
.type _Z11fill_matrixPdjj, @function
_Z11fill_matrixPdjj:
.LFB2057:
.cfi_startproc
endbr64
movq %rdi, %r9
movl $0, %r8d
movl $0, %r10d
movss .LC0(%rip), %xmm3
movss .LC1(%rip), %xmm2
testl %esi, %esi
jne .L10
ret
.L17:
movl %r10d, %eax
pxor %xmm1, %xmm1
cvtsi2ssq %rax, %xmm1
mulss %xmm3, %xmm1
movl $0, %eax
.L16:
leal (%r8,%rax), %ecx
movl %eax, %edi
pxor %xmm0, %xmm0
cvtsi2ssq %rdi, %xmm0
mulss %xmm2, %xmm0
addss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movsd %xmm0, (%r9,%rcx,8)
addl $1, %eax
cmpl %eax, %edx
jne .L16
.L18:
addl $1, %r10d
addl %edx, %r8d
cmpl %r10d, %esi
je .L9
.L10:
testl %edx, %edx
jne .L17
jmp .L18
.L9:
ret
.cfi_endproc
.LFE2057:
.size _Z11fill_matrixPdjj, .-_Z11fill_matrixPdjj
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "w"
.LC3:
.string "assignment2_3_out"
.LC4:
.string "%4.4f "
.LC5:
.string "\n"
.text
.globl _Z20print_matrix_to_filePdjj
.type _Z20print_matrix_to_filePdjj, @function
_Z20print_matrix_to_filePdjj:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r13
movl %esi, %ebx
movl %esi, 12(%rsp)
movl %edx, %r15d
leaq .LC2(%rip), %rsi
leaq .LC3(%rip), %rdi
call fopen@PLT
movq %rax, %r12
movl %r15d, %ebp
movl $0, 8(%rsp)
leaq .LC4(%rip), %r14
testl %ebx, %ebx
jne .L23
.L24:
movq %r12, %rdi
call fclose@PLT
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movl %ebx, %eax
movsd 0(%r13,%rax,8), %xmm0
movq %r14, %rdx
movl $2, %esi
movq %r12, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addl $1, %ebx
cmpl %ebp, %ebx
jne .L25
.L27:
leaq .LC5(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, 8(%rsp)
movl 8(%rsp), %eax
addl %r15d, %ebp
cmpl %eax, 12(%rsp)
je .L24
.L23:
movl %ebp, %ebx
subl %r15d, %ebx
testl %r15d, %r15d
jne .L25
jmp .L27
.cfi_endproc
.LFE2058:
.size _Z20print_matrix_to_filePdjj, .-_Z20print_matrix_to_filePdjj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "\nMatrix A (first 10*10 inputs)\n"
.section .rodata.str1.1
.LC7:
.string "%f "
.section .rodata.str1.8
.align 8
.LC8:
.string "\n\nMatrix B (first 10*10 inputs)\n"
.section .rodata.str1.1
.LC9:
.string "\nTime spent in col maj %f\n"
.section .rodata.str1.8
.align 8
.LC10:
.string "\n\nMatrix C (first 10*10 outputs)\n"
.align 8
.LC11:
.string "\nWritting to file assignment_2_1_out as Mat C"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $16, 128(%rsp)
movl $8192, 132(%rsp)
leaq 128(%rsp), %rax
movq %rax, (%rsp)
leaq 136(%rsp), %rax
movq %rax, 40(%rsp)
leaq .LC7(%rip), %r14
.L44:
movq (%rsp), %rax
movl (%rax), %r13d
movl %r13d, %eax
imull %r13d, %eax
cltq
leaq 0(,%rax,8), %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r15
movq %rax, 16(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rax, 8(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, 24(%rsp)
movl %r13d, %edx
movl %r13d, %esi
movq %r15, %rdi
call _Z11fill_matrixPdjj
movl %r13d, %edx
movl %r13d, %esi
movq %rbp, %rdi
call _Z11fill_matrixPdjj
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %r13d, %r12
salq $3, %r12
leaq 80(%r15), %rbp
movl $10, %r15d
movl %r13d, 36(%rsp)
.L34:
leaq -80(%rbp), %r13
.L35:
movsd 0(%r13), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %r13
cmpq %rbp, %r13
jne .L35
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq %r12, %rbp
subl $1, %r15d
jne .L34
movl 36(%rsp), %r13d
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
leaq 80(%rax), %rbp
movl $10, %r15d
movl %r13d, 36(%rsp)
.L37:
leaq -80(%rbp), %r13
.L38:
movsd 0(%r13), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %r13
cmpq %rbp, %r13
jne .L38
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq %r12, %rbp
subl $1, %r15d
jne .L37
movl 36(%rsp), %r13d
leaq 64(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
call cudaEventCreate@PLT
leaq 96(%rsp), %rdi
call cudaEventCreate@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 112(%rsp)
leal 15(%r13), %eax
shrl $4, %eax
movl %eax, 116(%rsp)
movl %eax, 120(%rsp)
movl $1, 124(%rsp)
movl $0, %esi
movq 88(%rsp), %rdi
call cudaEventRecord@PLT
movl $16, 104(%rsp)
movl $16, 108(%rsp)
movl %r13d, %eax
sall $5, %eax
cltq
movl 112(%rsp), %ecx
movl $0, %r9d
leaq 0(,%rax,8), %r8
movq 104(%rsp), %rdx
movq 116(%rsp), %rdi
movl 124(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L40:
call cudaPeekAtLastError@PLT
movl $0, %esi
movq 96(%rsp), %rdi
call cudaEventRecord@PLT
movq 96(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 60(%rsp), %rdi
movq 96(%rsp), %rdx
movq 88(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 60(%rsp), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 80(%rsp), %rsi
movq 24(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 80(%rbx), %rbp
movl $10, %r15d
.L41:
leaq -80(%rbp), %rbx
.L42:
movsd (%rbx), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L42
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq %r12, %rbp
subl $1, %r15d
jne .L41
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %edx
movl %r13d, %esi
movq 24(%rsp), %rbx
movq %rbx, %rdi
call _Z20print_matrix_to_filePdjj
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
addq $4, (%rsp)
movq (%rsp), %rax
movq 40(%rsp), %rcx
cmpq %rcx, %rax
jne .L44
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L52
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
movl %r13d, %ecx
movq 80(%rsp), %rdx
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i
jmp .L40
.L52:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC12:
.string "_Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1074161254
.align 4
.LC1:
.long 1078774989
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
void fill_matrix(double *mat, unsigned numRows, unsigned numCols)
{
for(unsigned i=0; i < numRows; i++)
for(unsigned j=0; j < numCols; j++)
{
mat[i*numCols + j] = i*2.1f + j*3.2f;
}
}
void print_matrix_to_file(double *mat, unsigned numRows, unsigned numCols)
{
const char *fname = "assignment2_3_out";
FILE *f = fopen(fname, "w");
for(unsigned i=0; i < numRows; i++)
{
for(unsigned j=0; j < numCols; j++)
fprintf(f,"%4.4f ", mat[i*numCols + j]);
fprintf(f,"\n");
}
fclose(f); }
template<int TILE_WIDTH>
__global__ void MatrixMulKernel_col_maj(double* M, double* N, double* P, int Width) {
extern __shared__ double buffer[];
double *ds_M = &buffer[0]; // TILE_WIDTH WIDTH
double *ds_N = &buffer[TILE_WIDTH*Width]; // WIDTH TILE_WIDTH
//__shared__ float ds_M[Width][Width];
//__shared__ float ds_N[Width][Width];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
int Row = by * blockDim.y + ty;
int Col = bx * blockDim.x + tx;
// Loop over the M and N tiles required to compute the P element
for (int p = 0; p < Width/TILE_WIDTH; ++p) {
// Collaborative loading of M and N tiles into shared memory
ds_M[ty*Width + tx + p*blockDim.x ] = M[Row*Width + p*TILE_WIDTH+tx];
ds_N[ty*TILE_WIDTH + blockDim.y*TILE_WIDTH*p + tx] = N[(p*TILE_WIDTH+ty)*Width + Col];
__syncthreads();
}
double Pvalue = 0;
for (int i = 0; i < TILE_WIDTH; ++i){
Pvalue += ds_M[ty*Width + i] * ds_N[i*Width + tx];
}
__syncthreads();
P[Row*Width+Col] = Pvalue;
}
int main(int argc,char **argv) {
int N_ll[2]; int N;
int loop, loop1, loop2; // loop variables
float time_spent;
N_ll[0]=16; N_ll[1]=8192;
for (loop=0;loop<2;loop++){
N=N_ll[loop];
size_t size = N *N* sizeof(double);
double*h_matA = (double*)malloc(size);
double*h_matB = (double*)malloc(size);
double*h_matC = (double*)malloc(size); // result
fill_matrix(h_matA,N,N);
fill_matrix(h_matB,N,N);
printf("\nMatrix A (first 10*10 inputs)\n");
for(loop1 = 0; loop1 < 10; loop1++){
for (loop2=0;loop2 < 10; loop2++)
printf("%f ", *(h_matA + N*loop1 + loop2));
printf("\n");
}
printf("\n\nMatrix B (first 10*10 inputs)\n");
for(loop1 = 0; loop1 < 10; loop1++){
for (loop2=0;loop2 < 10; loop2++)
printf("%f ", *(h_matB + N*loop1 + loop2));
printf("\n");
}
double* d_matA; cudaMalloc(&d_matA, size);
double* d_matB; cudaMalloc(&d_matB, size);
double* d_matC; cudaMalloc(&d_matC, size);
//GPU timing
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// Copy vectors from host memory to device memory
cudaMemcpy(d_matA, h_matA, size,cudaMemcpyHostToDevice);
cudaMemcpy(d_matB, h_matB, size,cudaMemcpyHostToDevice);
// Invoke kernel
dim3 threadsPerBlock (16,16);
dim3 blocksPerGrid ((N + threadsPerBlock.x - 1) /threadsPerBlock.x,(N + threadsPerBlock.y - 1) /threadsPerBlock.y);
cudaEventRecord(start, 0);
size_t blocksize = 2 * N * 16;
(MatrixMulKernel_col_maj<16>)<<<blocksPerGrid, threadsPerBlock, sizeof(double)*blocksize>>>(d_matA,d_matB, d_matC, N);
cudaError_t err1 = cudaPeekAtLastError();
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time_spent, start, stop);
printf("\nTime spent in col maj %f\n",time_spent);
// h_C contains the result in host memory
cudaMemcpy(h_matC, d_matC, size,cudaMemcpyDeviceToHost);
printf("\n\nMatrix C (first 10*10 outputs)\n");
for(loop1 = 0; loop1 < 10; loop1++){
for (loop2=0;loop2 < 10; loop2++)
printf("%f ", *(h_matC + N*loop1 + loop2));
printf("\n");
}
// Log outputs
printf("\nWritting to file assignment_2_1_out as Mat C");
print_matrix_to_file(h_matC,N,N);
// Free device memory
cudaFree(d_matA);
cudaFree(d_matB);
cudaFree(d_matC);
// Free host memory
free(h_matA);
free(h_matB);
free(h_matC);
}
return 0;
} | #include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
void fill_matrix(double *mat, unsigned numRows, unsigned numCols)
{
for(unsigned i=0; i < numRows; i++)
for(unsigned j=0; j < numCols; j++)
{
mat[i*numCols + j] = i*2.1f + j*3.2f;
}
}
void print_matrix_to_file(double *mat, unsigned numRows, unsigned numCols)
{
const char *fname = "assignment2_3_out";
FILE *f = fopen(fname, "w");
for(unsigned i=0; i < numRows; i++)
{
for(unsigned j=0; j < numCols; j++)
fprintf(f,"%4.4f ", mat[i*numCols + j]);
fprintf(f,"\n");
}
fclose(f); }
template<int TILE_WIDTH>
__global__ void MatrixMulKernel_col_maj(double* M, double* N, double* P, int Width) {
extern __shared__ double buffer[];
double *ds_M = &buffer[0]; // TILE_WIDTH WIDTH
double *ds_N = &buffer[TILE_WIDTH*Width]; // WIDTH TILE_WIDTH
//__shared__ float ds_M[Width][Width];
//__shared__ float ds_N[Width][Width];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
int Row = by * blockDim.y + ty;
int Col = bx * blockDim.x + tx;
// Loop over the M and N tiles required to compute the P element
for (int p = 0; p < Width/TILE_WIDTH; ++p) {
// Collaborative loading of M and N tiles into shared memory
ds_M[ty*Width + tx + p*blockDim.x ] = M[Row*Width + p*TILE_WIDTH+tx];
ds_N[ty*TILE_WIDTH + blockDim.y*TILE_WIDTH*p + tx] = N[(p*TILE_WIDTH+ty)*Width + Col];
__syncthreads();
}
double Pvalue = 0;
for (int i = 0; i < TILE_WIDTH; ++i){
Pvalue += ds_M[ty*Width + i] * ds_N[i*Width + tx];
}
__syncthreads();
P[Row*Width+Col] = Pvalue;
}
int main(int argc,char **argv) {
int N_ll[2]; int N;
int loop, loop1, loop2; // loop variables
float time_spent;
N_ll[0]=16; N_ll[1]=8192;
for (loop=0;loop<2;loop++){
N=N_ll[loop];
size_t size = N *N* sizeof(double);
double*h_matA = (double*)malloc(size);
double*h_matB = (double*)malloc(size);
double*h_matC = (double*)malloc(size); // result
fill_matrix(h_matA,N,N);
fill_matrix(h_matB,N,N);
printf("\nMatrix A (first 10*10 inputs)\n");
for(loop1 = 0; loop1 < 10; loop1++){
for (loop2=0;loop2 < 10; loop2++)
printf("%f ", *(h_matA + N*loop1 + loop2));
printf("\n");
}
printf("\n\nMatrix B (first 10*10 inputs)\n");
for(loop1 = 0; loop1 < 10; loop1++){
for (loop2=0;loop2 < 10; loop2++)
printf("%f ", *(h_matB + N*loop1 + loop2));
printf("\n");
}
double* d_matA; hipMalloc(&d_matA, size);
double* d_matB; hipMalloc(&d_matB, size);
double* d_matC; hipMalloc(&d_matC, size);
//GPU timing
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// Copy vectors from host memory to device memory
hipMemcpy(d_matA, h_matA, size,hipMemcpyHostToDevice);
hipMemcpy(d_matB, h_matB, size,hipMemcpyHostToDevice);
// Invoke kernel
dim3 threadsPerBlock (16,16);
dim3 blocksPerGrid ((N + threadsPerBlock.x - 1) /threadsPerBlock.x,(N + threadsPerBlock.y - 1) /threadsPerBlock.y);
hipEventRecord(start, 0);
size_t blocksize = 2 * N * 16;
(MatrixMulKernel_col_maj<16>)<<<blocksPerGrid, threadsPerBlock, sizeof(double)*blocksize>>>(d_matA,d_matB, d_matC, N);
hipError_t err1 = hipPeekAtLastError();
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time_spent, start, stop);
printf("\nTime spent in col maj %f\n",time_spent);
// h_C contains the result in host memory
hipMemcpy(h_matC, d_matC, size,hipMemcpyDeviceToHost);
printf("\n\nMatrix C (first 10*10 outputs)\n");
for(loop1 = 0; loop1 < 10; loop1++){
for (loop2=0;loop2 < 10; loop2++)
printf("%f ", *(h_matC + N*loop1 + loop2));
printf("\n");
}
// Log outputs
printf("\nWritting to file assignment_2_1_out as Mat C");
print_matrix_to_file(h_matC,N,N);
// Free device memory
hipFree(d_matA);
hipFree(d_matB);
hipFree(d_matC);
// Free host memory
free(h_matA);
free(h_matB);
free(h_matC);
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
void fill_matrix(double *mat, unsigned numRows, unsigned numCols)
{
for(unsigned i=0; i < numRows; i++)
for(unsigned j=0; j < numCols; j++)
{
mat[i*numCols + j] = i*2.1f + j*3.2f;
}
}
void print_matrix_to_file(double *mat, unsigned numRows, unsigned numCols)
{
const char *fname = "assignment2_3_out";
FILE *f = fopen(fname, "w");
for(unsigned i=0; i < numRows; i++)
{
for(unsigned j=0; j < numCols; j++)
fprintf(f,"%4.4f ", mat[i*numCols + j]);
fprintf(f,"\n");
}
fclose(f); }
template<int TILE_WIDTH>
__global__ void MatrixMulKernel_col_maj(double* M, double* N, double* P, int Width) {
extern __shared__ double buffer[];
double *ds_M = &buffer[0]; // TILE_WIDTH WIDTH
double *ds_N = &buffer[TILE_WIDTH*Width]; // WIDTH TILE_WIDTH
//__shared__ float ds_M[Width][Width];
//__shared__ float ds_N[Width][Width];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
int Row = by * blockDim.y + ty;
int Col = bx * blockDim.x + tx;
// Loop over the M and N tiles required to compute the P element
for (int p = 0; p < Width/TILE_WIDTH; ++p) {
// Collaborative loading of M and N tiles into shared memory
ds_M[ty*Width + tx + p*blockDim.x ] = M[Row*Width + p*TILE_WIDTH+tx];
ds_N[ty*TILE_WIDTH + blockDim.y*TILE_WIDTH*p + tx] = N[(p*TILE_WIDTH+ty)*Width + Col];
__syncthreads();
}
double Pvalue = 0;
for (int i = 0; i < TILE_WIDTH; ++i){
Pvalue += ds_M[ty*Width + i] * ds_N[i*Width + tx];
}
__syncthreads();
P[Row*Width+Col] = Pvalue;
}
int main(int argc,char **argv) {
int N_ll[2]; int N;
int loop, loop1, loop2; // loop variables
float time_spent;
N_ll[0]=16; N_ll[1]=8192;
for (loop=0;loop<2;loop++){
N=N_ll[loop];
size_t size = N *N* sizeof(double);
double*h_matA = (double*)malloc(size);
double*h_matB = (double*)malloc(size);
double*h_matC = (double*)malloc(size); // result
fill_matrix(h_matA,N,N);
fill_matrix(h_matB,N,N);
printf("\nMatrix A (first 10*10 inputs)\n");
for(loop1 = 0; loop1 < 10; loop1++){
for (loop2=0;loop2 < 10; loop2++)
printf("%f ", *(h_matA + N*loop1 + loop2));
printf("\n");
}
printf("\n\nMatrix B (first 10*10 inputs)\n");
for(loop1 = 0; loop1 < 10; loop1++){
for (loop2=0;loop2 < 10; loop2++)
printf("%f ", *(h_matB + N*loop1 + loop2));
printf("\n");
}
double* d_matA; hipMalloc(&d_matA, size);
double* d_matB; hipMalloc(&d_matB, size);
double* d_matC; hipMalloc(&d_matC, size);
//GPU timing
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// Copy vectors from host memory to device memory
hipMemcpy(d_matA, h_matA, size,hipMemcpyHostToDevice);
hipMemcpy(d_matB, h_matB, size,hipMemcpyHostToDevice);
// Invoke kernel
dim3 threadsPerBlock (16,16);
dim3 blocksPerGrid ((N + threadsPerBlock.x - 1) /threadsPerBlock.x,(N + threadsPerBlock.y - 1) /threadsPerBlock.y);
hipEventRecord(start, 0);
size_t blocksize = 2 * N * 16;
(MatrixMulKernel_col_maj<16>)<<<blocksPerGrid, threadsPerBlock, sizeof(double)*blocksize>>>(d_matA,d_matB, d_matC, N);
hipError_t err1 = hipPeekAtLastError();
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time_spent, start, stop);
printf("\nTime spent in col maj %f\n",time_spent);
// h_C contains the result in host memory
hipMemcpy(h_matC, d_matC, size,hipMemcpyDeviceToHost);
printf("\n\nMatrix C (first 10*10 outputs)\n");
for(loop1 = 0; loop1 < 10; loop1++){
for (loop2=0;loop2 < 10; loop2++)
printf("%f ", *(h_matC + N*loop1 + loop2));
printf("\n");
}
// Log outputs
printf("\nWritting to file assignment_2_1_out as Mat C");
print_matrix_to_file(h_matC,N,N);
// Free device memory
hipFree(d_matA);
hipFree(d_matB);
hipFree(d_matC);
// Free host memory
free(h_matA);
free(h_matB);
free(h_matC);
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i,"axG",@progbits,_Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i,comdat
.protected _Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i
.globl _Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i
.p2align 8
.type _Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i,@function
_Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x18
s_load_b32 s4, s[0:1], 0x2c
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v6, v3, s2
s_lshr_b32 s11, s4, 16
s_lshl_b32 s5, s2, 7
v_mad_u64_u32 v[1:2], null, s15, s11, v[3:4]
s_and_b32 s12, s4, 0xffff
s_add_i32 s8, s5, 0
s_cmp_lt_i32 s2, 16
s_mul_i32 s14, s14, s12
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v4, 3, v0
v_lshlrev_b32_e32 v5, 3, v6
v_lshlrev_b32_e32 v8, 7, v3
s_ashr_i32 s10, s2, 31
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
s_lshr_b32 s10, s10, 28
v_add3_u32 v7, 0, v4, v5
v_add3_u32 v8, s8, v8, v4
v_add3_u32 v4, v0, v6, s14
s_add_i32 s10, s2, s10
s_lshl_b32 s9, s2, 4
s_ashr_i32 s10, s10, 4
s_lshl_b32 s11, s11, 7
s_lshl_b32 s12, s12, 3
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s10, s10, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s10, 0
v_lshlrev_b64 v[9:10], 3, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[11:12], 3, v[4:5]
v_add_nc_u32_e32 v2, 16, v2
v_add_nc_u32_e32 v4, s9, v4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_b64 v[9:10], v[9:10], off
global_load_b64 v[11:12], v[11:12], off
s_waitcnt vmcnt(1)
ds_store_b64 v7, v[9:10]
s_waitcnt vmcnt(0)
ds_store_b64 v8, v[11:12]
v_add_nc_u32_e32 v8, s11, v8
v_add_nc_u32_e32 v7, s12, v7
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_3:
v_mov_b32_e32 v2, 0
v_lshl_add_u32 v4, v6, 3, 0
v_mov_b32_e32 v3, 0
v_lshl_add_u32 v5, v0, 3, s8
s_lshl_b32 s4, s2, 3
.LBB0_4:
s_delay_alu instid0(VALU_DEP_3)
v_add_nc_u32_e32 v8, s3, v4
s_add_i32 s3, s3, 8
ds_load_b64 v[6:7], v5
ds_load_b64 v[8:9], v8
v_add_nc_u32_e32 v5, s4, v5
s_cmpk_eq_i32 s3, 0x80
s_waitcnt lgkmcnt(0)
v_fma_f64 v[2:3], v[8:9], v[6:7], v[2:3]
s_cbranch_scc0 .LBB0_4
v_mul_lo_u32 v1, v1, s2
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_add3_u32 v0, s14, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i,"axG",@progbits,_Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i,comdat
.Lfunc_end0:
.size _Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i, .Lfunc_end0-_Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
void fill_matrix(double *mat, unsigned numRows, unsigned numCols)
{
for(unsigned i=0; i < numRows; i++)
for(unsigned j=0; j < numCols; j++)
{
mat[i*numCols + j] = i*2.1f + j*3.2f;
}
}
void print_matrix_to_file(double *mat, unsigned numRows, unsigned numCols)
{
const char *fname = "assignment2_3_out";
FILE *f = fopen(fname, "w");
for(unsigned i=0; i < numRows; i++)
{
for(unsigned j=0; j < numCols; j++)
fprintf(f,"%4.4f ", mat[i*numCols + j]);
fprintf(f,"\n");
}
fclose(f); }
template<int TILE_WIDTH>
__global__ void MatrixMulKernel_col_maj(double* M, double* N, double* P, int Width) {
extern __shared__ double buffer[];
double *ds_M = &buffer[0]; // TILE_WIDTH WIDTH
double *ds_N = &buffer[TILE_WIDTH*Width]; // WIDTH TILE_WIDTH
//__shared__ float ds_M[Width][Width];
//__shared__ float ds_N[Width][Width];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
int Row = by * blockDim.y + ty;
int Col = bx * blockDim.x + tx;
// Loop over the M and N tiles required to compute the P element
for (int p = 0; p < Width/TILE_WIDTH; ++p) {
// Collaborative loading of M and N tiles into shared memory
ds_M[ty*Width + tx + p*blockDim.x ] = M[Row*Width + p*TILE_WIDTH+tx];
ds_N[ty*TILE_WIDTH + blockDim.y*TILE_WIDTH*p + tx] = N[(p*TILE_WIDTH+ty)*Width + Col];
__syncthreads();
}
double Pvalue = 0;
for (int i = 0; i < TILE_WIDTH; ++i){
Pvalue += ds_M[ty*Width + i] * ds_N[i*Width + tx];
}
__syncthreads();
P[Row*Width+Col] = Pvalue;
}
int main(int argc,char **argv) {
int N_ll[2]; int N;
int loop, loop1, loop2; // loop variables
float time_spent;
N_ll[0]=16; N_ll[1]=8192;
for (loop=0;loop<2;loop++){
N=N_ll[loop];
size_t size = N *N* sizeof(double);
double*h_matA = (double*)malloc(size);
double*h_matB = (double*)malloc(size);
double*h_matC = (double*)malloc(size); // result
fill_matrix(h_matA,N,N);
fill_matrix(h_matB,N,N);
printf("\nMatrix A (first 10*10 inputs)\n");
for(loop1 = 0; loop1 < 10; loop1++){
for (loop2=0;loop2 < 10; loop2++)
printf("%f ", *(h_matA + N*loop1 + loop2));
printf("\n");
}
printf("\n\nMatrix B (first 10*10 inputs)\n");
for(loop1 = 0; loop1 < 10; loop1++){
for (loop2=0;loop2 < 10; loop2++)
printf("%f ", *(h_matB + N*loop1 + loop2));
printf("\n");
}
double* d_matA; hipMalloc(&d_matA, size);
double* d_matB; hipMalloc(&d_matB, size);
double* d_matC; hipMalloc(&d_matC, size);
//GPU timing
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// Copy vectors from host memory to device memory
hipMemcpy(d_matA, h_matA, size,hipMemcpyHostToDevice);
hipMemcpy(d_matB, h_matB, size,hipMemcpyHostToDevice);
// Invoke kernel
dim3 threadsPerBlock (16,16);
dim3 blocksPerGrid ((N + threadsPerBlock.x - 1) /threadsPerBlock.x,(N + threadsPerBlock.y - 1) /threadsPerBlock.y);
hipEventRecord(start, 0);
size_t blocksize = 2 * N * 16;
(MatrixMulKernel_col_maj<16>)<<<blocksPerGrid, threadsPerBlock, sizeof(double)*blocksize>>>(d_matA,d_matB, d_matC, N);
hipError_t err1 = hipPeekAtLastError();
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time_spent, start, stop);
printf("\nTime spent in col maj %f\n",time_spent);
// h_C contains the result in host memory
hipMemcpy(h_matC, d_matC, size,hipMemcpyDeviceToHost);
printf("\n\nMatrix C (first 10*10 outputs)\n");
for(loop1 = 0; loop1 < 10; loop1++){
for (loop2=0;loop2 < 10; loop2++)
printf("%f ", *(h_matC + N*loop1 + loop2));
printf("\n");
}
// Log outputs
printf("\nWritting to file assignment_2_1_out as Mat C");
print_matrix_to_file(h_matC,N,N);
// Free device memory
hipFree(d_matA);
hipFree(d_matB);
hipFree(d_matC);
// Free host memory
free(h_matA);
free(h_matB);
free(h_matC);
}
return 0;
} | .text
.file "ee16b068_3.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11fill_matrixPdjj
.LCPI0_0:
.long 0x40066666 # float 2.0999999
.LCPI0_1:
.long 0x404ccccd # float 3.20000005
.text
.globl _Z11fill_matrixPdjj
.p2align 4, 0x90
.type _Z11fill_matrixPdjj,@function
_Z11fill_matrixPdjj: # @_Z11fill_matrixPdjj
.cfi_startproc
# %bb.0:
testl %esi, %esi
je .LBB0_6
# %bb.1: # %.preheader.lr.ph
movl %edx, %eax
xorl %ecx, %ecx
movss .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorl %r8d, %r8d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
incl %r8d
addq %rax, %rcx
cmpl %esi, %r8d
je .LBB0_6
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
testl %edx, %edx
je .LBB0_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
movl %r8d, %r9d
xorps %xmm2, %xmm2
cvtsi2ss %r9, %xmm2
mulss %xmm0, %xmm2
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movl %r9d, %r10d
xorps %xmm3, %xmm3
cvtsi2ss %r10, %xmm3
mulss %xmm1, %xmm3
addss %xmm2, %xmm3
cvtss2sd %xmm3, %xmm3
leal (%rcx,%r9), %r10d
movsd %xmm3, (%rdi,%r10,8)
incq %r9
cmpq %r9, %rax
jne .LBB0_4
jmp .LBB0_5
.LBB0_6: # %._crit_edge15
retq
.Lfunc_end0:
.size _Z11fill_matrixPdjj, .Lfunc_end0-_Z11fill_matrixPdjj
.cfi_endproc
# -- End function
.globl _Z20print_matrix_to_filePdjj # -- Begin function _Z20print_matrix_to_filePdjj
.p2align 4, 0x90
.type _Z20print_matrix_to_filePdjj,@function
_Z20print_matrix_to_filePdjj: # @_Z20print_matrix_to_filePdjj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movl %esi, %ebp
movq %rdi, %r14
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r15
movl %ebp, 12(%rsp) # 4-byte Spill
testl %ebp, %ebp
je .LBB1_4
# %bb.1: # %.preheader.lr.ph
movl %ebx, %ecx
movl %ebx, %eax
movq %rax, 16(%rsp) # 8-byte Spill
xorl %ebx, %ebx
xorl %ebp, %ebp
movl %ecx, 8(%rsp) # 4-byte Spill
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_3: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movl $10, %edi
movq %r15, %rsi
callq fputc@PLT
incl %ebp
movl 8(%rsp), %ecx # 4-byte Reload
addl %ecx, %ebx
cmpl 12(%rsp), %ebp # 4-byte Folded Reload
je .LBB1_4
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_5 Depth 2
movq 16(%rsp), %r12 # 8-byte Reload
movl %ebx, %r13d
testl %ecx, %ecx
je .LBB1_3
.p2align 4, 0x90
.LBB1_5: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl %r13d, %eax
movsd (%r14,%rax,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.2, %esi
movq %r15, %rdi
movb $1, %al
callq fprintf
incl %r13d
decq %r12
jne .LBB1_5
jmp .LBB1_3
.LBB1_4: # %._crit_edge17
movq %r15, %rdi
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end1:
.size _Z20print_matrix_to_filePdjj, .Lfunc_end1-_Z20print_matrix_to_filePdjj
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x40066666 # float 2.0999999
.LCPI2_1:
.long 0x404ccccd # float 3.20000005
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $35184372088848, %rax # imm = 0x200000000010
movq %rax, 168(%rsp)
xorl %eax, %eax
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_30: # %_Z20print_matrix_to_filePdjj.exit
# in Loop: Header=BB2_1 Depth=1
movq %r13, %rdi
callq fclose
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi # 8-byte Reload
callq free
movq 16(%rsp), %rdi # 8-byte Reload
callq free
movq %r12, %rdi
callq free
movq 88(%rsp), %rcx # 8-byte Reload
leaq 1(%rcx), %rax
testq %rcx, %rcx
jne .LBB2_31
.LBB2_1: # =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
# Child Loop BB2_4 Depth 3
# Child Loop BB2_8 Depth 2
# Child Loop BB2_9 Depth 3
# Child Loop BB2_12 Depth 2
# Child Loop BB2_13 Depth 3
# Child Loop BB2_16 Depth 2
# Child Loop BB2_17 Depth 3
# Child Loop BB2_22 Depth 2
# Child Loop BB2_23 Depth 3
# Child Loop BB2_27 Depth 2
# Child Loop BB2_28 Depth 3
movq %rax, 88(%rsp) # 8-byte Spill
movslq 168(%rsp,%rax,4), %r13
movl %r13d, %ebx
imull %ebx, %ebx
shlq $3, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r14
movq %rbx, %rdi
callq malloc
movq %rax, %r15
movq %rbx, 80(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq malloc
movq %rax, %r12
movl %r13d, %ebx
testq %r13, %r13
movss .LCPI2_0(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss .LCPI2_1(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
je .LBB2_11
# %bb.2: # %.preheader.i.preheader
# in Loop: Header=BB2_1 Depth=1
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_3: # %.preheader.i
# Parent Loop BB2_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_4 Depth 3
movl %ecx, %edx
xorps %xmm0, %xmm0
cvtsi2ss %rdx, %xmm0
mulss %xmm2, %xmm0
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_1 Depth=1
# Parent Loop BB2_3 Depth=2
# => This Inner Loop Header: Depth=3
movl %edx, %esi
xorps %xmm1, %xmm1
cvtsi2ss %rsi, %xmm1
mulss %xmm3, %xmm1
addss %xmm0, %xmm1
cvtss2sd %xmm1, %xmm1
leal (%rax,%rdx), %esi
movsd %xmm1, (%r14,%rsi,8)
incq %rdx
cmpq %rdx, %rbx
jne .LBB2_4
# %bb.5: # %._crit_edge.i
# in Loop: Header=BB2_3 Depth=2
incl %ecx
addq %rbx, %rax
cmpl %r13d, %ecx
jne .LBB2_3
# %bb.6: # %_Z11fill_matrixPdjj.exit
# in Loop: Header=BB2_1 Depth=1
testl %r13d, %r13d
je .LBB2_11
# %bb.7: # %.preheader.i73.preheader
# in Loop: Header=BB2_1 Depth=1
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_8: # %.preheader.i73
# Parent Loop BB2_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_9 Depth 3
movl %ecx, %edx
xorps %xmm0, %xmm0
cvtsi2ss %rdx, %xmm0
mulss %xmm2, %xmm0
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_9: # Parent Loop BB2_1 Depth=1
# Parent Loop BB2_8 Depth=2
# => This Inner Loop Header: Depth=3
movl %edx, %esi
xorps %xmm1, %xmm1
cvtsi2ss %rsi, %xmm1
mulss %xmm3, %xmm1
addss %xmm0, %xmm1
cvtss2sd %xmm1, %xmm1
leal (%rax,%rdx), %esi
movsd %xmm1, (%r15,%rsi,8)
incq %rdx
cmpq %rdx, %rbx
jne .LBB2_9
# %bb.10: # %._crit_edge.i79
# in Loop: Header=BB2_8 Depth=2
incl %ecx
addq %rbx, %rax
cmpl %ebx, %ecx
jne .LBB2_8
.LBB2_11: # %_Z11fill_matrixPdjj.exit81
# in Loop: Header=BB2_1 Depth=1
movq %r15, 16(%rsp) # 8-byte Spill
movl $.Lstr, %edi
callq puts@PLT
movq %r13, 8(%rsp) # 8-byte Spill
leaq (,%r13,8), %r13
movq %r14, 64(%rsp) # 8-byte Spill
movq %r14, %r15
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_12: # %.preheader93
# Parent Loop BB2_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_13 Depth 3
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_13: # Parent Loop BB2_1 Depth=1
# Parent Loop BB2_12 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%r15,%r14,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.5, %edi
movb $1, %al
callq printf
incq %r14
cmpq $10, %r14
jne .LBB2_13
# %bb.14: # in Loop: Header=BB2_12 Depth=2
movl $10, %edi
callq putchar@PLT
incq %rbp
addq %r13, %r15
cmpq $10, %rbp
jne .LBB2_12
# %bb.15: # in Loop: Header=BB2_1 Depth=1
movl $.Lstr.1, %edi
callq puts@PLT
movq 16(%rsp), %r15 # 8-byte Reload
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_16: # %.preheader92
# Parent Loop BB2_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_17 Depth 3
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_17: # Parent Loop BB2_1 Depth=1
# Parent Loop BB2_16 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%r15,%r14,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.5, %edi
movb $1, %al
callq printf
incq %r14
cmpq $10, %r14
jne .LBB2_17
# %bb.18: # in Loop: Header=BB2_16 Depth=2
movl $10, %edi
callq putchar@PLT
incq %rbp
addq %r13, %r15
cmpq $10, %rbp
jne .LBB2_16
# %bb.19: # in Loop: Header=BB2_1 Depth=1
leaq 48(%rsp), %rdi
movq 80(%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 72(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
movq 64(%rsp), %rsi # 8-byte Reload
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq 16(%rsp), %rsi # 8-byte Reload
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %r14 # 8-byte Reload
leal 15(%r14), %eax
shrl $4, %eax
movq %rax, %rbp
shlq $32, %rbp
orq %rax, %rbp
movq 72(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r14, %r8
shlq $8, %r8
movq %rbp, %rdi
movl $1, %esi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_21
# %bb.20: # in Loop: Header=BB2_1 Depth=1
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 160(%rsp)
movq %rcx, 152(%rsp)
movq %rdx, 144(%rsp)
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, 60(%rsp)
leaq 160(%rsp), %rax
movq %rax, 176(%rsp)
leaq 152(%rsp), %rax
movq %rax, 184(%rsp)
leaq 144(%rsp), %rax
movq %rax, 192(%rsp)
leaq 60(%rsp), %rax
movq %rax, 200(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
movl $_Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i, %edi
leaq 176(%rsp), %r9
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_21: # in Loop: Header=BB2_1 Depth=1
callq hipPeekAtLastError
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 72(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 56(%rsp), %rdi
callq hipEventElapsedTime
movss 56(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rsi
movq %r12, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.2, %edi
callq puts@PLT
movq %r12, %r15
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_22: # %.preheader
# Parent Loop BB2_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_23 Depth 3
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_23: # Parent Loop BB2_1 Depth=1
# Parent Loop BB2_22 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%r15,%r14,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.5, %edi
movb $1, %al
callq printf
incq %r14
cmpq $10, %r14
jne .LBB2_23
# %bb.24: # in Loop: Header=BB2_22 Depth=2
movl $10, %edi
callq putchar@PLT
incq %rbp
addq %r13, %r15
cmpq $10, %rbp
jne .LBB2_22
# %bb.25: # in Loop: Header=BB2_1 Depth=1
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r13
cmpl $0, 8(%rsp) # 4-byte Folded Reload
je .LBB2_30
# %bb.26: # %.preheader.i84.preheader
# in Loop: Header=BB2_1 Depth=1
xorl %ebp, %ebp
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_27: # %.preheader.i84
# Parent Loop BB2_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_28 Depth 3
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_28: # Parent Loop BB2_1 Depth=1
# Parent Loop BB2_27 Depth=2
# => This Inner Loop Header: Depth=3
leal (%r14,%rbp), %eax
movsd (%r12,%rax,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.2, %esi
movq %r13, %rdi
movb $1, %al
callq fprintf
incq %r14
cmpq %r14, %rbx
jne .LBB2_28
# %bb.29: # %._crit_edge.i89
# in Loop: Header=BB2_27 Depth=2
movl $10, %edi
movq %r13, %rsi
callq fputc@PLT
incl %r15d
addq %rbx, %rbp
cmpl %ebx, %r15d
jne .LBB2_27
jmp .LBB2_30
.LBB2_31:
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.section .text._Z38__device_stub__MatrixMulKernel_col_majILi16EEvPdS0_S0_i,"axG",@progbits,_Z38__device_stub__MatrixMulKernel_col_majILi16EEvPdS0_S0_i,comdat
.weak _Z38__device_stub__MatrixMulKernel_col_majILi16EEvPdS0_S0_i # -- Begin function _Z38__device_stub__MatrixMulKernel_col_majILi16EEvPdS0_S0_i
.p2align 4, 0x90
.type _Z38__device_stub__MatrixMulKernel_col_majILi16EEvPdS0_S0_i,@function
_Z38__device_stub__MatrixMulKernel_col_majILi16EEvPdS0_S0_i: # @_Z38__device_stub__MatrixMulKernel_col_majILi16EEvPdS0_S0_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z38__device_stub__MatrixMulKernel_col_majILi16EEvPdS0_S0_i, .Lfunc_end3-_Z38__device_stub__MatrixMulKernel_col_majILi16EEvPdS0_S0_i
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "assignment2_3_out"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "w"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%4.4f "
.size .L.str.2, 7
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%f "
.size .L.str.5, 4
.type _Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i,@object # @_Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i
.section .rodata._Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i,"aG",@progbits,_Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i,comdat
.weak _Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i
.p2align 3, 0x0
_Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i:
.quad _Z38__device_stub__MatrixMulKernel_col_majILi16EEvPdS0_S0_i
.size _Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i, 8
.type .L.str.7,@object # @.str.7
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.7:
.asciz "\nTime spent in col maj %f\n"
.size .L.str.7, 27
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "\nWritting to file assignment_2_1_out as Mat C"
.size .L.str.9, 46
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i"
.size .L__unnamed_1, 45
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nMatrix A (first 10*10 inputs)"
.size .Lstr, 31
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n\nMatrix B (first 10*10 inputs)"
.size .Lstr.1, 32
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\n\nMatrix C (first 10*10 outputs)"
.size .Lstr.2, 33
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__MatrixMulKernel_col_majILi16EEvPdS0_S0_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e240000002200 */
/*0050*/ ISETP.GE.AND P0, PT, R2, 0x10, PT ; /* 0x000000100200780c */
/* 0x000fe40003f06270 */
/*0060*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e620000002500 */
/*0070*/ SHF.R.S32.HI R7, RZ, 0x1f, R2 ; /* 0x0000001fff077819 */
/* 0x000fc60000011402 */
/*0080*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0090*/ LEA.HI R7, R7, c[0x0][0x178], RZ, 0x4 ; /* 0x00005e0007077a11 */
/* 0x000fe200078f20ff */
/*00a0*/ IMAD R4, R5, c[0x0][0x4], R0 ; /* 0x0000010005047a24 */
/* 0x001fe400078e0200 */
/*00b0*/ IMAD R5, R6, c[0x0][0x0], R3 ; /* 0x0000000006057a24 */
/* 0x002fe200078e0203 */
/*00c0*/ SHF.L.U32 R6, R2, 0x4, RZ ; /* 0x0000000402067819 */
/* 0x000fe400000006ff */
/*00d0*/ @!P0 BRA 0x6a0 ; /* 0x000005c000008947 */
/* 0x000fea0003800000 */
/*00e0*/ SHF.R.S32.HI R8, RZ, 0x4, R7 ; /* 0x00000004ff087819 */
/* 0x000fe20000011407 */
/*00f0*/ IMAD.MOV.U32 R27, RZ, RZ, RZ ; /* 0x000000ffff1b7224 */
/* 0x000fc600078e00ff */
/*0100*/ IADD3 R9, R8.reuse, -0x1, RZ ; /* 0xffffffff08097810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R7, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308077812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P1, PT, R9, 0x3, PT ; /* 0x000000030900780c */
/* 0x000fe40003f26070 */
/*0130*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fd60003f05270 */
/*0140*/ @!P1 BRA 0x490 ; /* 0x0000034000009947 */
/* 0x000fea0003800000 */
/*0150*/ IMAD R13, R0, 0x10, R3.reuse ; /* 0x00000010000d7824 */
/* 0x100fe200078e0203 */
/*0160*/ IADD3 R8, -R8, R7, RZ ; /* 0x0000000708087210 */
/* 0x000fe20007ffe1ff */
/*0170*/ IMAD R9, R4, c[0x0][0x178], R3.reuse ; /* 0x00005e0004097a24 */
/* 0x100fe400078e0203 */
/*0180*/ IMAD R12, R0, c[0x0][0x178], R3 ; /* 0x00005e00000c7a24 */
/* 0x000fe200078e0203 */
/*0190*/ IADD3 R13, R6, R13, RZ ; /* 0x0000000d060d7210 */
/* 0x000fe20007ffe0ff */
/*01a0*/ IMAD R11, R0, c[0x0][0x178], R5 ; /* 0x00005e00000b7a24 */
/* 0x000fe200078e0205 */
/*01b0*/ IADD3 R9, R9, 0x30, RZ ; /* 0x0000003009097810 */
/* 0x000fe20007ffe0ff */
/*01c0*/ IMAD.MOV.U32 R27, RZ, RZ, RZ ; /* 0x000000ffff1b7224 */
/* 0x000fe200078e00ff */
/*01d0*/ SHF.L.U32 R12, R12, 0x3, RZ ; /* 0x000000030c0c7819 */
/* 0x000fe200000006ff */
/*01e0*/ IMAD.SHL.U32 R13, R13, 0x8, RZ ; /* 0x000000080d0d7824 */
/* 0x000fc400078e00ff */
/*01f0*/ HFMA2.MMA R10, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0a7435 */
/* 0x000fe200000001ff */
/*0200*/ IADD3 R15, R9, -0x30, RZ ; /* 0xffffffd0090f7810 */
/* 0x000fd20007ffe0ff */
/*0210*/ IMAD.WIDE R14, R15, R10, c[0x0][0x160] ; /* 0x000058000f0e7625 */
/* 0x000fc800078e020a */
/*0220*/ IMAD.WIDE R28, R11, R10, c[0x0][0x168] ; /* 0x00005a000b1c7625 */
/* 0x001fe200078e020a */
/*0230*/ LDG.E.64 R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x000ea8000c1e1b00 */
/*0240*/ LDG.E.64 R20, [R28.64] ; /* 0x000000041c147981 */
/* 0x000ee2000c1e1b00 */
/*0250*/ IMAD.WIDE R24, R6, 0x8, R28 ; /* 0x0000000806187825 */
/* 0x000fc600078e021c */
/*0260*/ STS.64 [R12], R22 ; /* 0x000000160c007388 */
/* 0x004fe80000000a00 */
/*0270*/ STS.64 [R13], R20 ; /* 0x000000140d007388 */
/* 0x0081e80000000a00 */
/*0280*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0290*/ LDG.E.64 R16, [R14.64+0x80] ; /* 0x000080040e107981 */
/* 0x000ea8000c1e1b00 */
/*02a0*/ LDG.E.64 R18, [R24.64] ; /* 0x0000000418127981 */
/* 0x000ee2000c1e1b00 */
/*02b0*/ IMAD.MOV.U32 R26, RZ, RZ, c[0x0][0x4] ; /* 0x00000100ff1a7624 */
/* 0x000fc400078e00ff */
/*02c0*/ IMAD R29, R10, c[0x0][0x0], R12 ; /* 0x000000000a1d7a24 */
/* 0x000fc600078e020c */
/*02d0*/ LEA R28, R26, R13, 0x7 ; /* 0x0000000d1a1c7211 */
/* 0x000fe200078e38ff */
/*02e0*/ IMAD.WIDE R12, R6, 0x8, R24 ; /* 0x00000008060c7825 */
/* 0x001fe200078e0218 */
/*02f0*/ STS.64 [R29], R16 ; /* 0x000000101d007388 */
/* 0x0041e80000000a00 */
/*0300*/ STS.64 [R28], R18 ; /* 0x000000121c007388 */
/* 0x0083e80000000a00 */
/*0310*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0320*/ LDG.E.64 R22, [R14.64+0x100] ; /* 0x000100040e167981 */
/* 0x000ea8000c1e1b00 */
/*0330*/ LDG.E.64 R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000ee2000c1e1b00 */
/*0340*/ IMAD R29, R10, c[0x0][0x0], R29 ; /* 0x000000000a1d7a24 */
/* 0x001fc400078e021d */
/*0350*/ IMAD R19, R26, 0x80, R28 ; /* 0x000000801a137824 */
/* 0x002fe400078e021c */
/*0360*/ IMAD.WIDE R24, R6, 0x8, R12 ; /* 0x0000000806187825 */
/* 0x000fe200078e020c */
/*0370*/ STS.64 [R29], R22 ; /* 0x000000161d007388 */
/* 0x0041e80000000a00 */
/*0380*/ STS.64 [R19], R20 ; /* 0x0000001413007388 */
/* 0x0081e80000000a00 */
/*0390*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03a0*/ LDG.E.64 R16, [R14.64+0x180] ; /* 0x000180040e107981 */
/* 0x000ea8000c1e1b00 */
/*03b0*/ LDG.E.64 R24, [R24.64] ; /* 0x0000000418187981 */
/* 0x000ee2000c1e1b00 */
/*03c0*/ IADD3 R27, R27, 0x4, RZ ; /* 0x000000041b1b7810 */
/* 0x000fe20007ffe0ff */
/*03d0*/ IMAD R18, R10, c[0x0][0x0], R29 ; /* 0x000000000a127a24 */
/* 0x000fe200078e021d */
/*03e0*/ LEA R28, R26, R19, 0x7 ; /* 0x000000131a1c7211 */
/* 0x000fe200078e38ff */
/*03f0*/ IMAD R11, R2, 0x40, R11 ; /* 0x00000040020b7824 */
/* 0x000fe200078e020b */
/*0400*/ IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009097810 */
/* 0x000fe20007ffe0ff */
/*0410*/ IMAD.IADD R12, R8, 0x1, R27 ; /* 0x00000001080c7824 */
/* 0x000fe200078e021b */
/*0420*/ LEA R13, R26, R28, 0x7 ; /* 0x0000001c1a0d7211 */
/* 0x000fc800078e38ff */
/*0430*/ ISETP.NE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f25270 */
/*0440*/ IMAD R12, R10, c[0x0][0x0], R18 ; /* 0x000000000a0c7a24 */
/* 0x000fe200078e0212 */
/*0450*/ STS.64 [R18], R16 ; /* 0x0000001012007388 */
/* 0x0041e80000000a00 */
/*0460*/ STS.64 [R28], R24 ; /* 0x000000181c007388 */
/* 0x0081e80000000a00 */
/*0470*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0480*/ @P1 BRA 0x1f0 ; /* 0xfffffd6000001947 */
/* 0x000fea000383ffff */
/*0490*/ @!P0 BRA 0x6a0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*04a0*/ IMAD R8, R4, c[0x0][0x178], R3 ; /* 0x00005e0004087a24 */
/* 0x000fe200078e0203 */
/*04b0*/ MOV R10, 0x8 ; /* 0x00000008000a7802 */
/* 0x000fe20000000f00 */
/*04c0*/ IMAD R12, R27.reuse, c[0x0][0x4], R0 ; /* 0x000001001b0c7a24 */
/* 0x040fe200078e0200 */
/*04d0*/ IADD3 R11, R6, R3, RZ ; /* 0x00000003060b7210 */
/* 0x000fe20007ffe0ff */
/*04e0*/ IMAD R9, R27, 0x10, R8 ; /* 0x000000101b097824 */
/* 0x000fc400078e0208 */
/*04f0*/ IMAD R13, R27.reuse, c[0x0][0x0], R3 ; /* 0x000000001b0d7a24 */
/* 0x040fe200078e0203 */
/*0500*/ LEA R11, R12, R11, 0x4 ; /* 0x0000000b0c0b7211 */
/* 0x000fe200078e20ff */
/*0510*/ IMAD R14, R27, 0x10, R0 ; /* 0x000000101b0e7824 */
/* 0x000fe400078e0200 */
/*0520*/ IMAD.WIDE R8, R9, R10, c[0x0][0x160] ; /* 0x0000580009087625 */
/* 0x000fe200078e020a */
/*0530*/ SHF.L.U32 R11, R11, 0x3, RZ ; /* 0x000000030b0b7819 */
/* 0x000fc600000006ff */
/*0540*/ IMAD R13, R0, c[0x0][0x178], R13 ; /* 0x00005e00000d7a24 */
/* 0x000fe200078e020d */
/*0550*/ MOV R19, R9 ; /* 0x0000000900137202 */
/* 0x001fe20000000f00 */
/*0560*/ IMAD R15, R14, c[0x0][0x178], R5 ; /* 0x00005e000e0f7a24 */
/* 0x000fe400078e0205 */
/*0570*/ IMAD.MOV.U32 R16, RZ, RZ, R8 ; /* 0x000000ffff107224 */
/* 0x000fe400078e0008 */
/*0580*/ IMAD.SHL.U32 R17, R13, 0x8, RZ ; /* 0x000000080d117824 */
/* 0x000fe400078e00ff */
/*0590*/ IMAD.WIDE R8, R15, R10, c[0x0][0x168] ; /* 0x00005a000f087625 */
/* 0x000fc800078e020a */
/*05a0*/ MOV R12, R16 ; /* 0x00000010000c7202 */
/* 0x000fe20000000f00 */
/*05b0*/ LDG.E.64 R14, [R8.64] ; /* 0x00000004080e7981 */
/* 0x0000a2000c1e1b00 */
/*05c0*/ MOV R13, R19 ; /* 0x00000013000d7202 */
/* 0x000fcc0000000f00 */
/*05d0*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee2000c1e1b00 */
/*05e0*/ IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07077810 */
/* 0x000fc80007ffe0ff */
/*05f0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*0600*/ IMAD.MOV.U32 R18, RZ, RZ, c[0x0][0x4] ; /* 0x00000100ff127624 */
/* 0x000fe200078e00ff */
/*0610*/ IADD3 R16, P1, R16, 0x80, RZ ; /* 0x0000008010107810 */
/* 0x000fe20007f3e0ff */
/*0620*/ IMAD.WIDE R8, R6, 0x8, R8 ; /* 0x0000000806087825 */
/* 0x001fc600078e0208 */
/*0630*/ IADD3.X R19, RZ, R19, RZ, P1, !PT ; /* 0x00000013ff137210 */
/* 0x000fe20000ffe4ff */
/*0640*/ STS.64 [R17], R12 ; /* 0x0000000c11007388 */
/* 0x0081e80000000a00 */
/*0650*/ STS.64 [R11], R14 ; /* 0x0000000e0b007388 */
/* 0x0043e20000000a00 */
/*0660*/ IMAD R17, R10, c[0x0][0x0], R17 ; /* 0x000000000a117a24 */
/* 0x001fe200078e0211 */
/*0670*/ LEA R11, R18, R11, 0x7 ; /* 0x0000000b120b7211 */
/* 0x002fe400078e38ff */
/*0680*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0690*/ @P0 BRA 0x5a0 ; /* 0xffffff0000000947 */
/* 0x000fea000383ffff */
/*06a0*/ IMAD.IADD R6, R6, 0x1, R3 ; /* 0x0000000106067824 */
/* 0x000fe400078e0203 */
/*06b0*/ IMAD R0, R0, c[0x0][0x178], RZ ; /* 0x00005e0000007a24 */
/* 0x000fc400078e02ff */
/*06c0*/ IMAD R4, R4, c[0x0][0x178], R5 ; /* 0x00005e0004047a24 */
/* 0x000fe200078e0205 */
/*06d0*/ SHF.L.U32 R3, R6, 0x3, RZ ; /* 0x0000000306037819 */
/* 0x000fe400000006ff */
/*06e0*/ LDS.64 R6, [R6.X8] ; /* 0x0000000006067984 */
/* 0x000fe40000008a00 */
/*06f0*/ LEA R3, R2.reuse, R3, 0x3 ; /* 0x0000000302037211 */
/* 0x040fe400078e18ff */
/*0700*/ LDS.64 R8, [R0.X8] ; /* 0x0000000000087984 */
/* 0x000e660000008a00 */
/*0710*/ IMAD R25, R2.reuse, 0x8, R3 ; /* 0x0000000802197824 */
/* 0x041fe200078e0203 */
/*0720*/ LDS.64 R10, [R0.X8+0x8] ; /* 0x00000800000a7984 */
/* 0x000fe80000008a00 */
/*0730*/ LDS.64 R12, [R3] ; /* 0x00000000030c7984 */
/* 0x0000a20000000a00 */
/*0740*/ LEA R27, R2, R25, 0x3 ; /* 0x00000019021b7211 */
/* 0x000fc600078e18ff */
/*0750*/ LDS.64 R18, [R0.X8+0x10] ; /* 0x0000100000127984 */
/* 0x000fe20000008a00 */
/*0760*/ LEA R29, R2, R27, 0x3 ; /* 0x0000001b021d7211 */
/* 0x000fc600078e18ff */
/*0770*/ LDS.64 R20, [R25] ; /* 0x0000000019147984 */
/* 0x0007240000000a00 */
/*0780*/ IMAD R3, R2.reuse, 0x8, R29 ; /* 0x0000000802037824 */
/* 0x041fe400078e021d */
/*0790*/ LDS.64 R14, [R0.X8+0x18] ; /* 0x00001800000e7984 */
/* 0x000fe80000008a00 */
/*07a0*/ LDS.64 R16, [R27] ; /* 0x000000001b107984 */
/* 0x0001620000000a00 */
/*07b0*/ LEA R25, R2, R3, 0x3 ; /* 0x0000000302197211 */
/* 0x008fc800078e18ff */
/*07c0*/ LEA R27, R2, R25, 0x3 ; /* 0x00000019021b7211 */
/* 0x001fe200078e18ff */
/*07d0*/ DFMA R22, R6, R8, RZ ; /* 0x000000080616722b */
/* 0x0020a400000000ff */
/*07e0*/ LDS.64 R6, [R0.X8+0x20] ; /* 0x0000200000067984 */
/* 0x001fe80000008a00 */
/*07f0*/ LDS.64 R8, [R29] ; /* 0x000000001d087984 */
/* 0x0000620000000a00 */
/*0800*/ DFMA R22, R12, R10, R22 ; /* 0x0000000a0c16722b */
/* 0x0045060000000016 */
/*0810*/ LDS.64 R10, [R0.X8+0x28] ; /* 0x00002800000a7984 */
/* 0x004fe80000008a00 */
/*0820*/ LDS.64 R12, [R3] ; /* 0x00000000030c7984 */
/* 0x0004e20000000a00 */
/*0830*/ IMAD R29, R2.reuse, 0x8, R27 ; /* 0x00000008021d7824 */
/* 0x041fe200078e021b */
/*0840*/ DFMA R22, R20, R18, R22 ; /* 0x000000121416722b */
/* 0x0101640000000016 */
/*0850*/ LDS.64 R18, [R0.X8+0x30] ; /* 0x0000300000127984 */
/* 0x001fe80000008a00 */
/*0860*/ LDS.64 R20, [R25] ; /* 0x0000000019147984 */
/* 0x0001220000000a00 */
/*0870*/ LEA R3, R2, R29, 0x3 ; /* 0x0000001d02037211 */
/* 0x004fe200078e18ff */
/*0880*/ DFMA R22, R16, R14, R22 ; /* 0x0000000e1016722b */
/* 0x0204440000000016 */
/*0890*/ LDS.64 R14, [R0.X8+0x38] ; /* 0x00003800000e7984 */
/* 0x004fe80000008a00 */
/*08a0*/ LDS.64 R16, [R27] ; /* 0x000000001b107984 */
/* 0x0005620000000a00 */
/*08b0*/ LEA R25, R2, R3, 0x3 ; /* 0x0000000302197211 */
/* 0x001fca00078e18ff */
/*08c0*/ IMAD R27, R2, 0x8, R25 ; /* 0x00000008021b7824 */
/* 0x004fe200078e0219 */
/*08d0*/ DFMA R22, R8, R6, R22 ; /* 0x000000060816722b */
/* 0x0020e40000000016 */
/*08e0*/ LDS.64 R6, [R0.X8+0x40] ; /* 0x0000400000067984 */
/* 0x001fe80000008a00 */
/*08f0*/ LDS.64 R8, [R29] ; /* 0x000000001d087984 */
/* 0x0000620000000a00 */
/*0900*/ DFMA R22, R12, R10, R22 ; /* 0x0000000a0c16722b */
/* 0x0085060000000016 */
/*0910*/ LDS.64 R10, [R0.X8+0x48] ; /* 0x00004800000a7984 */
/* 0x004fe80000008a00 */
/*0920*/ LDS.64 R12, [R3] ; /* 0x00000000030c7984 */
/* 0x000ea20000000a00 */
/*0930*/ LEA R29, R2.reuse, R27, 0x3 ; /* 0x0000001b021d7211 */
/* 0x041fe200078e18ff */
/*0940*/ DFMA R22, R20, R18, R22 ; /* 0x000000121416722b */
/* 0x0101640000000016 */
/*0950*/ LDS.64 R20, [R0.X8+0x50] ; /* 0x0000500000147984 */
/* 0x001fe20000008a00 */
/*0960*/ LEA R26, R2, R29, 0x3 ; /* 0x0000001d021a7211 */
/* 0x000fc600078e18ff */
/*0970*/ LDS.64 R18, [R25] ; /* 0x0000000019127984 */
/* 0x000e220000000a00 */
/*0980*/ DFMA R22, R16, R14, R22 ; /* 0x0000000e1016722b */
/* 0x0206620000000016 */
/*0990*/ IMAD R28, R2.reuse, 0x8, R26 ; /* 0x00000008021c7824 */
/* 0x040fe400078e021a */
/*09a0*/ LDS.64 R14, [R0.X8+0x58] ; /* 0x00005800000e7984 */
/* 0x008fe80000008a00 */
/*09b0*/ LDS.64 R16, [R27] ; /* 0x000000001b107984 */
/* 0x0007280000000a00 */
/*09c0*/ LDS.64 R24, [R0.X8+0x78] ; /* 0x0000780000187984 */
/* 0x000fe20000008a00 */
/*09d0*/ LEA R27, R2, R28, 0x3 ; /* 0x0000001c021b7211 */
/* 0x008fca00078e18ff */
/*09e0*/ LDS.64 R2, [R27] ; /* 0x000000001b027984 */
/* 0x000fe20000000a00 */
/*09f0*/ DFMA R22, R8, R6, R22 ; /* 0x000000060816722b */
/* 0x0022860000000016 */
/*0a00*/ LDS.64 R8, [R0.X8+0x60] ; /* 0x0000600000087984 */
/* 0x002fe80000008a00 */
/*0a10*/ LDS.64 R6, [R29] ; /* 0x000000001d067984 */
/* 0x000e620000000a00 */
/*0a20*/ DFMA R22, R12, R10, R22 ; /* 0x0000000a0c16722b */
/* 0x0044060000000016 */
/*0a30*/ LDS.64 R12, [R0.X8+0x68] ; /* 0x00006800000c7984 */
/* 0x004fe80000008a00 */
/*0a40*/ LDS.64 R10, [R26] ; /* 0x000000001a0a7984 */
/* 0x000ea20000000a00 */
/*0a50*/ DFMA R18, R18, R20, R22 ; /* 0x000000141212722b */
/* 0x0011060000000016 */
/*0a60*/ LDS.64 R22, [R0.X8+0x70] ; /* 0x0000700000167984 */
/* 0x001fe80000008a00 */
/*0a70*/ LDS.64 R20, [R28] ; /* 0x000000001c147984 */
/* 0x000e220000000a00 */
/*0a80*/ DFMA R14, R16, R14, R18 ; /* 0x0000000e100e722b */
/* 0x010e4c0000000012 */
/*0a90*/ DFMA R6, R6, R8, R14 ; /* 0x000000080606722b */
/* 0x0022a4000000000e */
/*0aa0*/ MOV R9, 0x8 ; /* 0x0000000800097802 */
/* 0x002fca0000000f00 */
/*0ab0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe200078e0209 */
/*0ac0*/ DFMA R6, R10, R12, R6 ; /* 0x0000000c0a06722b */
/* 0x004e0c0000000006 */
/*0ad0*/ DFMA R6, R20, R22, R6 ; /* 0x000000161406722b */
/* 0x001e0c0000000006 */
/*0ae0*/ DFMA R2, R2, R24, R6 ; /* 0x000000180202722b */
/* 0x001e220000000006 */
/*0af0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0b00*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x001fe2000c101b04 */
/*0b10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b20*/ BRA 0xb20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i,"axG",@progbits,_Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i,comdat
.protected _Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i
.globl _Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i
.p2align 8
.type _Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i,@function
_Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x18
s_load_b32 s4, s[0:1], 0x2c
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v6, v3, s2
s_lshr_b32 s11, s4, 16
s_lshl_b32 s5, s2, 7
v_mad_u64_u32 v[1:2], null, s15, s11, v[3:4]
s_and_b32 s12, s4, 0xffff
s_add_i32 s8, s5, 0
s_cmp_lt_i32 s2, 16
s_mul_i32 s14, s14, s12
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v4, 3, v0
v_lshlrev_b32_e32 v5, 3, v6
v_lshlrev_b32_e32 v8, 7, v3
s_ashr_i32 s10, s2, 31
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
s_lshr_b32 s10, s10, 28
v_add3_u32 v7, 0, v4, v5
v_add3_u32 v8, s8, v8, v4
v_add3_u32 v4, v0, v6, s14
s_add_i32 s10, s2, s10
s_lshl_b32 s9, s2, 4
s_ashr_i32 s10, s10, 4
s_lshl_b32 s11, s11, 7
s_lshl_b32 s12, s12, 3
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s10, s10, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s10, 0
v_lshlrev_b64 v[9:10], 3, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[11:12], 3, v[4:5]
v_add_nc_u32_e32 v2, 16, v2
v_add_nc_u32_e32 v4, s9, v4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_b64 v[9:10], v[9:10], off
global_load_b64 v[11:12], v[11:12], off
s_waitcnt vmcnt(1)
ds_store_b64 v7, v[9:10]
s_waitcnt vmcnt(0)
ds_store_b64 v8, v[11:12]
v_add_nc_u32_e32 v8, s11, v8
v_add_nc_u32_e32 v7, s12, v7
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_3:
v_mov_b32_e32 v2, 0
v_lshl_add_u32 v4, v6, 3, 0
v_mov_b32_e32 v3, 0
v_lshl_add_u32 v5, v0, 3, s8
s_lshl_b32 s4, s2, 3
.LBB0_4:
s_delay_alu instid0(VALU_DEP_3)
v_add_nc_u32_e32 v8, s3, v4
s_add_i32 s3, s3, 8
ds_load_b64 v[6:7], v5
ds_load_b64 v[8:9], v8
v_add_nc_u32_e32 v5, s4, v5
s_cmpk_eq_i32 s3, 0x80
s_waitcnt lgkmcnt(0)
v_fma_f64 v[2:3], v[8:9], v[6:7], v[2:3]
s_cbranch_scc0 .LBB0_4
v_mul_lo_u32 v1, v1, s2
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_add3_u32 v0, s14, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i,"axG",@progbits,_Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i,comdat
.Lfunc_end0:
.size _Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i, .Lfunc_end0-_Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f1b00_00000000-6_ee16b068_3.cudafe1.cpp"
.text
#APP
#NO_APP
.section .text._Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i,"axG",@progbits,_Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i,comdat
.weak _Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i
.type _Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i, @function
_Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i:
.LFB2136:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 4(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2136:
.size _Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i, .-_Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11fill_matrixPdjj
.type _Z11fill_matrixPdjj, @function
_Z11fill_matrixPdjj:
.LFB2057:
.cfi_startproc
endbr64
movq %rdi, %r9
movl $0, %r8d
movl $0, %r10d
movss .LC0(%rip), %xmm3
movss .LC1(%rip), %xmm2
testl %esi, %esi
jne .L10
ret
.L17:
movl %r10d, %eax
pxor %xmm1, %xmm1
cvtsi2ssq %rax, %xmm1
mulss %xmm3, %xmm1
movl $0, %eax
.L16:
leal (%r8,%rax), %ecx
movl %eax, %edi
pxor %xmm0, %xmm0
cvtsi2ssq %rdi, %xmm0
mulss %xmm2, %xmm0
addss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movsd %xmm0, (%r9,%rcx,8)
addl $1, %eax
cmpl %eax, %edx
jne .L16
.L18:
addl $1, %r10d
addl %edx, %r8d
cmpl %r10d, %esi
je .L9
.L10:
testl %edx, %edx
jne .L17
jmp .L18
.L9:
ret
.cfi_endproc
.LFE2057:
.size _Z11fill_matrixPdjj, .-_Z11fill_matrixPdjj
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "w"
.LC3:
.string "assignment2_3_out"
.LC4:
.string "%4.4f "
.LC5:
.string "\n"
.text
.globl _Z20print_matrix_to_filePdjj
.type _Z20print_matrix_to_filePdjj, @function
_Z20print_matrix_to_filePdjj:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r13
movl %esi, %ebx
movl %esi, 12(%rsp)
movl %edx, %r15d
leaq .LC2(%rip), %rsi
leaq .LC3(%rip), %rdi
call fopen@PLT
movq %rax, %r12
movl %r15d, %ebp
movl $0, 8(%rsp)
leaq .LC4(%rip), %r14
testl %ebx, %ebx
jne .L23
.L24:
movq %r12, %rdi
call fclose@PLT
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movl %ebx, %eax
movsd 0(%r13,%rax,8), %xmm0
movq %r14, %rdx
movl $2, %esi
movq %r12, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addl $1, %ebx
cmpl %ebp, %ebx
jne .L25
.L27:
leaq .LC5(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, 8(%rsp)
movl 8(%rsp), %eax
addl %r15d, %ebp
cmpl %eax, 12(%rsp)
je .L24
.L23:
movl %ebp, %ebx
subl %r15d, %ebx
testl %r15d, %r15d
jne .L25
jmp .L27
.cfi_endproc
.LFE2058:
.size _Z20print_matrix_to_filePdjj, .-_Z20print_matrix_to_filePdjj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "\nMatrix A (first 10*10 inputs)\n"
.section .rodata.str1.1
.LC7:
.string "%f "
.section .rodata.str1.8
.align 8
.LC8:
.string "\n\nMatrix B (first 10*10 inputs)\n"
.section .rodata.str1.1
.LC9:
.string "\nTime spent in col maj %f\n"
.section .rodata.str1.8
.align 8
.LC10:
.string "\n\nMatrix C (first 10*10 outputs)\n"
.align 8
.LC11:
.string "\nWritting to file assignment_2_1_out as Mat C"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $16, 128(%rsp)
movl $8192, 132(%rsp)
leaq 128(%rsp), %rax
movq %rax, (%rsp)
leaq 136(%rsp), %rax
movq %rax, 40(%rsp)
leaq .LC7(%rip), %r14
.L44:
movq (%rsp), %rax
movl (%rax), %r13d
movl %r13d, %eax
imull %r13d, %eax
cltq
leaq 0(,%rax,8), %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r15
movq %rax, 16(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rax, 8(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, 24(%rsp)
movl %r13d, %edx
movl %r13d, %esi
movq %r15, %rdi
call _Z11fill_matrixPdjj
movl %r13d, %edx
movl %r13d, %esi
movq %rbp, %rdi
call _Z11fill_matrixPdjj
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %r13d, %r12
salq $3, %r12
leaq 80(%r15), %rbp
movl $10, %r15d
movl %r13d, 36(%rsp)
.L34:
leaq -80(%rbp), %r13
.L35:
movsd 0(%r13), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %r13
cmpq %rbp, %r13
jne .L35
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq %r12, %rbp
subl $1, %r15d
jne .L34
movl 36(%rsp), %r13d
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
leaq 80(%rax), %rbp
movl $10, %r15d
movl %r13d, 36(%rsp)
.L37:
leaq -80(%rbp), %r13
.L38:
movsd 0(%r13), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %r13
cmpq %rbp, %r13
jne .L38
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq %r12, %rbp
subl $1, %r15d
jne .L37
movl 36(%rsp), %r13d
leaq 64(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
call cudaEventCreate@PLT
leaq 96(%rsp), %rdi
call cudaEventCreate@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 112(%rsp)
leal 15(%r13), %eax
shrl $4, %eax
movl %eax, 116(%rsp)
movl %eax, 120(%rsp)
movl $1, 124(%rsp)
movl $0, %esi
movq 88(%rsp), %rdi
call cudaEventRecord@PLT
movl $16, 104(%rsp)
movl $16, 108(%rsp)
movl %r13d, %eax
sall $5, %eax
cltq
movl 112(%rsp), %ecx
movl $0, %r9d
leaq 0(,%rax,8), %r8
movq 104(%rsp), %rdx
movq 116(%rsp), %rdi
movl 124(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L40:
call cudaPeekAtLastError@PLT
movl $0, %esi
movq 96(%rsp), %rdi
call cudaEventRecord@PLT
movq 96(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 60(%rsp), %rdi
movq 96(%rsp), %rdx
movq 88(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 60(%rsp), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 80(%rsp), %rsi
movq 24(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 80(%rbx), %rbp
movl $10, %r15d
.L41:
leaq -80(%rbp), %rbx
.L42:
movsd (%rbx), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L42
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq %r12, %rbp
subl $1, %r15d
jne .L41
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %edx
movl %r13d, %esi
movq 24(%rsp), %rbx
movq %rbx, %rdi
call _Z20print_matrix_to_filePdjj
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
addq $4, (%rsp)
movq (%rsp), %rax
movq 40(%rsp), %rcx
cmpq %rcx, %rax
jne .L44
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L52
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
movl %r13d, %ecx
movq 80(%rsp), %rdx
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i
jmp .L40
.L52:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC12:
.string "_Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1074161254
.align 4
.LC1:
.long 1078774989
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ee16b068_3.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11fill_matrixPdjj
.LCPI0_0:
.long 0x40066666 # float 2.0999999
.LCPI0_1:
.long 0x404ccccd # float 3.20000005
.text
.globl _Z11fill_matrixPdjj
.p2align 4, 0x90
.type _Z11fill_matrixPdjj,@function
_Z11fill_matrixPdjj: # @_Z11fill_matrixPdjj
.cfi_startproc
# %bb.0:
testl %esi, %esi
je .LBB0_6
# %bb.1: # %.preheader.lr.ph
movl %edx, %eax
xorl %ecx, %ecx
movss .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorl %r8d, %r8d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
incl %r8d
addq %rax, %rcx
cmpl %esi, %r8d
je .LBB0_6
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
testl %edx, %edx
je .LBB0_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
movl %r8d, %r9d
xorps %xmm2, %xmm2
cvtsi2ss %r9, %xmm2
mulss %xmm0, %xmm2
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movl %r9d, %r10d
xorps %xmm3, %xmm3
cvtsi2ss %r10, %xmm3
mulss %xmm1, %xmm3
addss %xmm2, %xmm3
cvtss2sd %xmm3, %xmm3
leal (%rcx,%r9), %r10d
movsd %xmm3, (%rdi,%r10,8)
incq %r9
cmpq %r9, %rax
jne .LBB0_4
jmp .LBB0_5
.LBB0_6: # %._crit_edge15
retq
.Lfunc_end0:
.size _Z11fill_matrixPdjj, .Lfunc_end0-_Z11fill_matrixPdjj
.cfi_endproc
# -- End function
.globl _Z20print_matrix_to_filePdjj # -- Begin function _Z20print_matrix_to_filePdjj
.p2align 4, 0x90
.type _Z20print_matrix_to_filePdjj,@function
_Z20print_matrix_to_filePdjj: # @_Z20print_matrix_to_filePdjj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movl %esi, %ebp
movq %rdi, %r14
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r15
movl %ebp, 12(%rsp) # 4-byte Spill
testl %ebp, %ebp
je .LBB1_4
# %bb.1: # %.preheader.lr.ph
movl %ebx, %ecx
movl %ebx, %eax
movq %rax, 16(%rsp) # 8-byte Spill
xorl %ebx, %ebx
xorl %ebp, %ebp
movl %ecx, 8(%rsp) # 4-byte Spill
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_3: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movl $10, %edi
movq %r15, %rsi
callq fputc@PLT
incl %ebp
movl 8(%rsp), %ecx # 4-byte Reload
addl %ecx, %ebx
cmpl 12(%rsp), %ebp # 4-byte Folded Reload
je .LBB1_4
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_5 Depth 2
movq 16(%rsp), %r12 # 8-byte Reload
movl %ebx, %r13d
testl %ecx, %ecx
je .LBB1_3
.p2align 4, 0x90
.LBB1_5: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl %r13d, %eax
movsd (%r14,%rax,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.2, %esi
movq %r15, %rdi
movb $1, %al
callq fprintf
incl %r13d
decq %r12
jne .LBB1_5
jmp .LBB1_3
.LBB1_4: # %._crit_edge17
movq %r15, %rdi
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end1:
.size _Z20print_matrix_to_filePdjj, .Lfunc_end1-_Z20print_matrix_to_filePdjj
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x40066666 # float 2.0999999
.LCPI2_1:
.long 0x404ccccd # float 3.20000005
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $35184372088848, %rax # imm = 0x200000000010
movq %rax, 168(%rsp)
xorl %eax, %eax
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_30: # %_Z20print_matrix_to_filePdjj.exit
# in Loop: Header=BB2_1 Depth=1
movq %r13, %rdi
callq fclose
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi # 8-byte Reload
callq free
movq 16(%rsp), %rdi # 8-byte Reload
callq free
movq %r12, %rdi
callq free
movq 88(%rsp), %rcx # 8-byte Reload
leaq 1(%rcx), %rax
testq %rcx, %rcx
jne .LBB2_31
.LBB2_1: # =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
# Child Loop BB2_4 Depth 3
# Child Loop BB2_8 Depth 2
# Child Loop BB2_9 Depth 3
# Child Loop BB2_12 Depth 2
# Child Loop BB2_13 Depth 3
# Child Loop BB2_16 Depth 2
# Child Loop BB2_17 Depth 3
# Child Loop BB2_22 Depth 2
# Child Loop BB2_23 Depth 3
# Child Loop BB2_27 Depth 2
# Child Loop BB2_28 Depth 3
movq %rax, 88(%rsp) # 8-byte Spill
movslq 168(%rsp,%rax,4), %r13
movl %r13d, %ebx
imull %ebx, %ebx
shlq $3, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r14
movq %rbx, %rdi
callq malloc
movq %rax, %r15
movq %rbx, 80(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq malloc
movq %rax, %r12
movl %r13d, %ebx
testq %r13, %r13
movss .LCPI2_0(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss .LCPI2_1(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
je .LBB2_11
# %bb.2: # %.preheader.i.preheader
# in Loop: Header=BB2_1 Depth=1
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_3: # %.preheader.i
# Parent Loop BB2_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_4 Depth 3
movl %ecx, %edx
xorps %xmm0, %xmm0
cvtsi2ss %rdx, %xmm0
mulss %xmm2, %xmm0
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_1 Depth=1
# Parent Loop BB2_3 Depth=2
# => This Inner Loop Header: Depth=3
movl %edx, %esi
xorps %xmm1, %xmm1
cvtsi2ss %rsi, %xmm1
mulss %xmm3, %xmm1
addss %xmm0, %xmm1
cvtss2sd %xmm1, %xmm1
leal (%rax,%rdx), %esi
movsd %xmm1, (%r14,%rsi,8)
incq %rdx
cmpq %rdx, %rbx
jne .LBB2_4
# %bb.5: # %._crit_edge.i
# in Loop: Header=BB2_3 Depth=2
incl %ecx
addq %rbx, %rax
cmpl %r13d, %ecx
jne .LBB2_3
# %bb.6: # %_Z11fill_matrixPdjj.exit
# in Loop: Header=BB2_1 Depth=1
testl %r13d, %r13d
je .LBB2_11
# %bb.7: # %.preheader.i73.preheader
# in Loop: Header=BB2_1 Depth=1
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_8: # %.preheader.i73
# Parent Loop BB2_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_9 Depth 3
movl %ecx, %edx
xorps %xmm0, %xmm0
cvtsi2ss %rdx, %xmm0
mulss %xmm2, %xmm0
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_9: # Parent Loop BB2_1 Depth=1
# Parent Loop BB2_8 Depth=2
# => This Inner Loop Header: Depth=3
movl %edx, %esi
xorps %xmm1, %xmm1
cvtsi2ss %rsi, %xmm1
mulss %xmm3, %xmm1
addss %xmm0, %xmm1
cvtss2sd %xmm1, %xmm1
leal (%rax,%rdx), %esi
movsd %xmm1, (%r15,%rsi,8)
incq %rdx
cmpq %rdx, %rbx
jne .LBB2_9
# %bb.10: # %._crit_edge.i79
# in Loop: Header=BB2_8 Depth=2
incl %ecx
addq %rbx, %rax
cmpl %ebx, %ecx
jne .LBB2_8
.LBB2_11: # %_Z11fill_matrixPdjj.exit81
# in Loop: Header=BB2_1 Depth=1
movq %r15, 16(%rsp) # 8-byte Spill
movl $.Lstr, %edi
callq puts@PLT
movq %r13, 8(%rsp) # 8-byte Spill
leaq (,%r13,8), %r13
movq %r14, 64(%rsp) # 8-byte Spill
movq %r14, %r15
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_12: # %.preheader93
# Parent Loop BB2_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_13 Depth 3
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_13: # Parent Loop BB2_1 Depth=1
# Parent Loop BB2_12 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%r15,%r14,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.5, %edi
movb $1, %al
callq printf
incq %r14
cmpq $10, %r14
jne .LBB2_13
# %bb.14: # in Loop: Header=BB2_12 Depth=2
movl $10, %edi
callq putchar@PLT
incq %rbp
addq %r13, %r15
cmpq $10, %rbp
jne .LBB2_12
# %bb.15: # in Loop: Header=BB2_1 Depth=1
movl $.Lstr.1, %edi
callq puts@PLT
movq 16(%rsp), %r15 # 8-byte Reload
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_16: # %.preheader92
# Parent Loop BB2_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_17 Depth 3
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_17: # Parent Loop BB2_1 Depth=1
# Parent Loop BB2_16 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%r15,%r14,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.5, %edi
movb $1, %al
callq printf
incq %r14
cmpq $10, %r14
jne .LBB2_17
# %bb.18: # in Loop: Header=BB2_16 Depth=2
movl $10, %edi
callq putchar@PLT
incq %rbp
addq %r13, %r15
cmpq $10, %rbp
jne .LBB2_16
# %bb.19: # in Loop: Header=BB2_1 Depth=1
leaq 48(%rsp), %rdi
movq 80(%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 72(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
movq 64(%rsp), %rsi # 8-byte Reload
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq 16(%rsp), %rsi # 8-byte Reload
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %r14 # 8-byte Reload
leal 15(%r14), %eax
shrl $4, %eax
movq %rax, %rbp
shlq $32, %rbp
orq %rax, %rbp
movq 72(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r14, %r8
shlq $8, %r8
movq %rbp, %rdi
movl $1, %esi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_21
# %bb.20: # in Loop: Header=BB2_1 Depth=1
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 160(%rsp)
movq %rcx, 152(%rsp)
movq %rdx, 144(%rsp)
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, 60(%rsp)
leaq 160(%rsp), %rax
movq %rax, 176(%rsp)
leaq 152(%rsp), %rax
movq %rax, 184(%rsp)
leaq 144(%rsp), %rax
movq %rax, 192(%rsp)
leaq 60(%rsp), %rax
movq %rax, 200(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
movl $_Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i, %edi
leaq 176(%rsp), %r9
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_21: # in Loop: Header=BB2_1 Depth=1
callq hipPeekAtLastError
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 72(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 56(%rsp), %rdi
callq hipEventElapsedTime
movss 56(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rsi
movq %r12, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.2, %edi
callq puts@PLT
movq %r12, %r15
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_22: # %.preheader
# Parent Loop BB2_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_23 Depth 3
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_23: # Parent Loop BB2_1 Depth=1
# Parent Loop BB2_22 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%r15,%r14,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.5, %edi
movb $1, %al
callq printf
incq %r14
cmpq $10, %r14
jne .LBB2_23
# %bb.24: # in Loop: Header=BB2_22 Depth=2
movl $10, %edi
callq putchar@PLT
incq %rbp
addq %r13, %r15
cmpq $10, %rbp
jne .LBB2_22
# %bb.25: # in Loop: Header=BB2_1 Depth=1
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r13
cmpl $0, 8(%rsp) # 4-byte Folded Reload
je .LBB2_30
# %bb.26: # %.preheader.i84.preheader
# in Loop: Header=BB2_1 Depth=1
xorl %ebp, %ebp
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_27: # %.preheader.i84
# Parent Loop BB2_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_28 Depth 3
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_28: # Parent Loop BB2_1 Depth=1
# Parent Loop BB2_27 Depth=2
# => This Inner Loop Header: Depth=3
leal (%r14,%rbp), %eax
movsd (%r12,%rax,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.2, %esi
movq %r13, %rdi
movb $1, %al
callq fprintf
incq %r14
cmpq %r14, %rbx
jne .LBB2_28
# %bb.29: # %._crit_edge.i89
# in Loop: Header=BB2_27 Depth=2
movl $10, %edi
movq %r13, %rsi
callq fputc@PLT
incl %r15d
addq %rbx, %rbp
cmpl %ebx, %r15d
jne .LBB2_27
jmp .LBB2_30
.LBB2_31:
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.section .text._Z38__device_stub__MatrixMulKernel_col_majILi16EEvPdS0_S0_i,"axG",@progbits,_Z38__device_stub__MatrixMulKernel_col_majILi16EEvPdS0_S0_i,comdat
.weak _Z38__device_stub__MatrixMulKernel_col_majILi16EEvPdS0_S0_i # -- Begin function _Z38__device_stub__MatrixMulKernel_col_majILi16EEvPdS0_S0_i
.p2align 4, 0x90
.type _Z38__device_stub__MatrixMulKernel_col_majILi16EEvPdS0_S0_i,@function
_Z38__device_stub__MatrixMulKernel_col_majILi16EEvPdS0_S0_i: # @_Z38__device_stub__MatrixMulKernel_col_majILi16EEvPdS0_S0_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z38__device_stub__MatrixMulKernel_col_majILi16EEvPdS0_S0_i, .Lfunc_end3-_Z38__device_stub__MatrixMulKernel_col_majILi16EEvPdS0_S0_i
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "assignment2_3_out"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "w"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%4.4f "
.size .L.str.2, 7
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%f "
.size .L.str.5, 4
.type _Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i,@object # @_Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i
.section .rodata._Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i,"aG",@progbits,_Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i,comdat
.weak _Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i
.p2align 3, 0x0
_Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i:
.quad _Z38__device_stub__MatrixMulKernel_col_majILi16EEvPdS0_S0_i
.size _Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i, 8
.type .L.str.7,@object # @.str.7
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.7:
.asciz "\nTime spent in col maj %f\n"
.size .L.str.7, 27
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "\nWritting to file assignment_2_1_out as Mat C"
.size .L.str.9, 46
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i"
.size .L__unnamed_1, 45
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nMatrix A (first 10*10 inputs)"
.size .Lstr, 31
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n\nMatrix B (first 10*10 inputs)"
.size .Lstr.1, 32
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\n\nMatrix C (first 10*10 outputs)"
.size .Lstr.2, 33
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__MatrixMulKernel_col_majILi16EEvPdS0_S0_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23MatrixMulKernel_col_majILi16EEvPdS0_S0_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void kernel( void ){
}
int main(void) {
int count;
cudaGetDeviceCount(&count);
printf( "%d\n",count );
return 0;
} | code for sm_80
Function : _Z6kernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void kernel( void ){
}
int main(void) {
int count;
cudaGetDeviceCount(&count);
printf( "%d\n",count );
return 0;
} | .file "tmpxft_00062763_00000000-6_count.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 4(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z24__device_stub__Z6kernelvv
.type _Z24__device_stub__Z6kernelvv, @function
_Z24__device_stub__Z6kernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z6kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z6kernelvv, .-_Z24__device_stub__Z6kernelvv
.globl _Z6kernelv
.type _Z6kernelv, @function
_Z6kernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z6kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelv, .-_Z6kernelv
.section .rodata.str1.1
.LC1:
.string "_Z6kernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void kernel( void ){
}
int main(void) {
int count;
cudaGetDeviceCount(&count);
printf( "%d\n",count );
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void kernel( void ){
}
int main(void) {
int count;
hipGetDeviceCount(&count);
printf( "%d\n",count );
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void kernel( void ){
}
int main(void) {
int count;
hipGetDeviceCount(&count);
printf( "%d\n",count );
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelv
.globl _Z6kernelv
.p2align 8
.type _Z6kernelv,@function
_Z6kernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelv, .Lfunc_end0-_Z6kernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z6kernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void kernel( void ){
}
int main(void) {
int count;
hipGetDeviceCount(&count);
printf( "%d\n",count );
return 0;
} | .text
.file "count.hip"
.globl _Z21__device_stub__kernelv # -- Begin function _Z21__device_stub__kernelv
.p2align 4, 0x90
.type _Z21__device_stub__kernelv,@function
_Z21__device_stub__kernelv: # @_Z21__device_stub__kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelv, .Lfunc_end0-_Z21__device_stub__kernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
movl 4(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelv,@object # @_Z6kernelv
.section .rodata,"a",@progbits
.globl _Z6kernelv
.p2align 3, 0x0
_Z6kernelv:
.quad _Z21__device_stub__kernelv
.size _Z6kernelv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\n"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelv"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelv
.globl _Z6kernelv
.p2align 8
.type _Z6kernelv,@function
_Z6kernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelv, .Lfunc_end0-_Z6kernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z6kernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00062763_00000000-6_count.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 4(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z24__device_stub__Z6kernelvv
.type _Z24__device_stub__Z6kernelvv, @function
_Z24__device_stub__Z6kernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z6kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z6kernelvv, .-_Z24__device_stub__Z6kernelvv
.globl _Z6kernelv
.type _Z6kernelv, @function
_Z6kernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z6kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelv, .-_Z6kernelv
.section .rodata.str1.1
.LC1:
.string "_Z6kernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "count.hip"
.globl _Z21__device_stub__kernelv # -- Begin function _Z21__device_stub__kernelv
.p2align 4, 0x90
.type _Z21__device_stub__kernelv,@function
_Z21__device_stub__kernelv: # @_Z21__device_stub__kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelv, .Lfunc_end0-_Z21__device_stub__kernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
movl 4(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelv,@object # @_Z6kernelv
.section .rodata,"a",@progbits
.globl _Z6kernelv
.p2align 3, 0x0
_Z6kernelv:
.quad _Z21__device_stub__kernelv
.size _Z6kernelv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\n"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelv"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<iostream>
#include<cstdio>
using namespace std;
__global__ void sum(int *a,int *b,int n)
{
int block=256*blockIdx.x;
int sum=0;
for(int i=block;i<min(block+256,n);i++)
{
sum=sum+a[i];
}
b[blockIdx.x]=sum;
}
int main()
{
cout<<"Enter the no of elements"<<endl;
int n;
cin>>n;
int a[n];
for(int i=0;i<n;i++)
{
a[i]=i+1;
}
int *ad,*bd;
int size=n*sizeof(int);
cudaMalloc(&ad,size);
cudaMemcpy(ad,a,size,cudaMemcpyHostToDevice);
int grids=ceil(n*1.0f/256.0f);
cudaMalloc(&bd,grids*sizeof(int));
dim3 grid(grids,1);
dim3 block(1,1);
int p=n;
while(n>1)
{
sum<<<grid,block>>>(ad,bd,n);
n=ceil(n*1.0f/256.0f);
cudaMemcpy(ad,bd,n*sizeof(int),cudaMemcpyDeviceToDevice);
}
int add[2];
n=p;
cudaMemcpy(add,ad,4,cudaMemcpyDeviceToHost);
cout<<"The sum is "<<add[0]<<endl;
float mean=0.0f;
mean=add[0]/(n*1.0f);
cout<<"The mean is "<<mean<<endl;
} | code for sm_80
Function : _Z3sumPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*0040*/ IMAD.SHL.U32 R5, R0, 0x100, RZ ; /* 0x0000010000057824 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R2, R5, 0x100, RZ ; /* 0x0000010005027810 */
/* 0x000fc80007ffe0ff */
/*0060*/ IMNMX R2, R2, c[0x0][0x170], PT ; /* 0x00005c0002027a17 */
/* 0x000fc80003800200 */
/*0070*/ ISETP.GE.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x000fda0003f06270 */
/*0080*/ @P0 BRA 0x730 ; /* 0x000006a000000947 */
/* 0x000fea0003800000 */
/*0090*/ LOP3.LUT R2, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff027a12 */
/* 0x000fe200078e33ff */
/*00a0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*00b0*/ IADD3 R3, -R5, -0x101, RZ ; /* 0xfffffeff05037810 */
/* 0x000fc80007ffe1ff */
/*00c0*/ IMNMX R8, R2, R3, !PT ; /* 0x0000000302087217 */
/* 0x000fc80007800200 */
/*00d0*/ IADD3 R3, -R5, -0x2, -R8 ; /* 0xfffffffe05037810 */
/* 0x000fe40007ffe908 */
/*00e0*/ LOP3.LUT R2, RZ, R8, RZ, 0x33, !PT ; /* 0x00000008ff027212 */
/* 0x000fe400078e33ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fc60003f06070 */
/*0100*/ IMAD.IADD R2, R2, 0x1, -R5 ; /* 0x0000000102027824 */
/* 0x000fca00078e0a05 */
/*0110*/ LOP3.LUT R4, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302047812 */
/* 0x000fca00078ec0ff */
/*0120*/ @!P0 BRA 0x660 ; /* 0x0000053000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R7, R4, R8, R5 ; /* 0x0000000804077210 */
/* 0x000fe20007ffe005 */
/*0140*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe400078e00ff */
/*0150*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*0160*/ IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0a07 */
/*0170*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fc600078e0202 */
/*0180*/ ISETP.GT.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe40003f04270 */
/*0190*/ IADD3 R2, P1, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fca0007f3e0ff */
/*01a0*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fcc00008e0603 */
/*01b0*/ @!P0 BRA 0x580 ; /* 0x000003c000008947 */
/* 0x000fea0003800000 */
/*01c0*/ IADD3 R8, R7, -0x1, RZ ; /* 0xffffffff07087810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*01e0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fda0003f24270 */
/*01f0*/ @!P1 BRA 0x400 ; /* 0x0000020000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ LDG.E R13, [R2.64+-0x8] ; /* 0xfffff804020d7981 */
/* 0x000ea8000c1e1900 */
/*0220*/ LDG.E R12, [R2.64+-0x4] ; /* 0xfffffc04020c7981 */
/* 0x000ea8000c1e1900 */
/*0230*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x0000e8000c1e1900 */
/*0240*/ LDG.E R14, [R2.64+0x4] ; /* 0x00000404020e7981 */
/* 0x0000e8000c1e1900 */
/*0250*/ LDG.E R17, [R2.64+0x8] ; /* 0x0000080402117981 */
/* 0x000128000c1e1900 */
/*0260*/ LDG.E R16, [R2.64+0xc] ; /* 0x00000c0402107981 */
/* 0x000128000c1e1900 */
/*0270*/ LDG.E R19, [R2.64+0x10] ; /* 0x0000100402137981 */
/* 0x000168000c1e1900 */
/*0280*/ LDG.E R18, [R2.64+0x14] ; /* 0x0000140402127981 */
/* 0x000168000c1e1900 */
/*0290*/ LDG.E R21, [R2.64+0x18] ; /* 0x0000180402157981 */
/* 0x000168000c1e1900 */
/*02a0*/ LDG.E R20, [R2.64+0x1c] ; /* 0x00001c0402147981 */
/* 0x000168000c1e1900 */
/*02b0*/ LDG.E R23, [R2.64+0x20] ; /* 0x0000200402177981 */
/* 0x000168000c1e1900 */
/*02c0*/ LDG.E R22, [R2.64+0x24] ; /* 0x0000240402167981 */
/* 0x000168000c1e1900 */
/*02d0*/ LDG.E R11, [R2.64+0x28] ; /* 0x00002804020b7981 */
/* 0x000168000c1e1900 */
/*02e0*/ LDG.E R10, [R2.64+0x2c] ; /* 0x00002c04020a7981 */
/* 0x000168000c1e1900 */
/*02f0*/ LDG.E R9, [R2.64+0x30] ; /* 0x0000300402097981 */
/* 0x000168000c1e1900 */
/*0300*/ LDG.E R8, [R2.64+0x34] ; /* 0x0000340402087981 */
/* 0x000162000c1e1900 */
/*0310*/ IADD3 R7, R7, -0x10, RZ ; /* 0xfffffff007077810 */
/* 0x000fc40007ffe0ff */
/*0320*/ IADD3 R5, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x000fe40007ffe0ff */
/*0330*/ ISETP.GT.AND P1, PT, R7, 0xd, PT ; /* 0x0000000d0700780c */
/* 0x000fe40003f24270 */
/*0340*/ IADD3 R12, R12, R13, R6 ; /* 0x0000000d0c0c7210 */
/* 0x004fe40007ffe006 */
/*0350*/ IADD3 R13, P2, R2, 0x40, RZ ; /* 0x00000040020d7810 */
/* 0x000fca0007f5e0ff */
/*0360*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x001fe200010e0603 */
/*0370*/ IADD3 R12, R14, R15, R12 ; /* 0x0000000f0e0c7210 */
/* 0x008fe20007ffe00c */
/*0380*/ IMAD.MOV.U32 R2, RZ, RZ, R13 ; /* 0x000000ffff027224 */
/* 0x000fc600078e000d */
/*0390*/ IADD3 R12, R16, R17, R12 ; /* 0x00000011100c7210 */
/* 0x010fc80007ffe00c */
/*03a0*/ IADD3 R12, R18, R19, R12 ; /* 0x00000013120c7210 */
/* 0x020fc80007ffe00c */
/*03b0*/ IADD3 R12, R20, R21, R12 ; /* 0x00000015140c7210 */
/* 0x000fc80007ffe00c */
/*03c0*/ IADD3 R12, R22, R23, R12 ; /* 0x00000017160c7210 */
/* 0x000fc80007ffe00c */
/*03d0*/ IADD3 R10, R10, R11, R12 ; /* 0x0000000b0a0a7210 */
/* 0x000fc80007ffe00c */
/*03e0*/ IADD3 R6, R8, R9, R10 ; /* 0x0000000908067210 */
/* 0x000fe20007ffe00a */
/*03f0*/ @P1 BRA 0x210 ; /* 0xfffffe1000001947 */
/* 0x000fea000383ffff */
/*0400*/ IADD3 R8, R7, -0x1, RZ ; /* 0xffffffff07087810 */
/* 0x000fc80007ffe0ff */
/*0410*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0420*/ @!P1 BRA 0x560 ; /* 0x0000013000009947 */
/* 0x000fea0003800000 */
/*0430*/ LDG.E R9, [R2.64+-0x8] ; /* 0xfffff80402097981 */
/* 0x000ea8000c1e1900 */
/*0440*/ LDG.E R8, [R2.64+-0x4] ; /* 0xfffffc0402087981 */
/* 0x000ea8000c1e1900 */
/*0450*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x0000e8000c1e1900 */
/*0460*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000404020a7981 */
/* 0x0000e8000c1e1900 */
/*0470*/ LDG.E R13, [R2.64+0x8] ; /* 0x00000804020d7981 */
/* 0x000128000c1e1900 */
/*0480*/ LDG.E R12, [R2.64+0xc] ; /* 0x00000c04020c7981 */
/* 0x000128000c1e1900 */
/*0490*/ LDG.E R15, [R2.64+0x10] ; /* 0x00001004020f7981 */
/* 0x000168000c1e1900 */
/*04a0*/ LDG.E R14, [R2.64+0x14] ; /* 0x00001404020e7981 */
/* 0x000162000c1e1900 */
/*04b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*04c0*/ IADD3 R5, R5, 0x8, RZ ; /* 0x0000000805057810 */
/* 0x000fe40007ffe0ff */
/*04d0*/ IADD3 R7, R7, -0x8, RZ ; /* 0xfffffff807077810 */
/* 0x000fe40007ffe0ff */
/*04e0*/ IADD3 R8, R8, R9, R6 ; /* 0x0000000908087210 */
/* 0x004fe40007ffe006 */
/*04f0*/ IADD3 R9, P1, R2, 0x20, RZ ; /* 0x0000002002097810 */
/* 0x000fca0007f3e0ff */
/*0500*/ IMAD.MOV.U32 R2, RZ, RZ, R9 ; /* 0x000000ffff027224 */
/* 0x001fe200078e0009 */
/*0510*/ IADD3 R8, R10, R11, R8 ; /* 0x0000000b0a087210 */
/* 0x008fe20007ffe008 */
/*0520*/ IMAD.X R10, RZ, RZ, R3, P1 ; /* 0x000000ffff0a7224 */
/* 0x000fc800008e0603 */
/*0530*/ IMAD.MOV.U32 R3, RZ, RZ, R10 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000a */
/*0540*/ IADD3 R8, R12, R13, R8 ; /* 0x0000000d0c087210 */
/* 0x010fc80007ffe008 */
/*0550*/ IADD3 R6, R14, R15, R8 ; /* 0x0000000f0e067210 */
/* 0x020fe40007ffe008 */
/*0560*/ ISETP.NE.OR P0, PT, R7, 0x1, P0 ; /* 0x000000010700780c */
/* 0x000fda0000705670 */
/*0570*/ @!P0 BRA 0x660 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0580*/ LDG.E R9, [R2.64+-0x8] ; /* 0xfffff80402097981 */
/* 0x0000a8000c1e1900 */
/*0590*/ LDG.E R8, [R2.64+-0x4] ; /* 0xfffffc0402087981 */
/* 0x0000a8000c1e1900 */
/*05a0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x0000e8000c1e1900 */
/*05b0*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000404020a7981 */
/* 0x0000e2000c1e1900 */
/*05c0*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fc40007ffe0ff */
/*05d0*/ IADD3 R12, P1, R2, 0x10, RZ ; /* 0x00000010020c7810 */
/* 0x000fe40007f3e0ff */
/*05e0*/ ISETP.NE.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe40003f05270 */
/*05f0*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fe20007ffe0ff */
/*0600*/ IMAD.X R13, RZ, RZ, R3, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe400008e0603 */
/*0610*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x001fe400078e000c */
/*0620*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000d */
/*0630*/ IADD3 R6, R8, R9, R6 ; /* 0x0000000908067210 */
/* 0x004fc80007ffe006 */
/*0640*/ IADD3 R6, R10, R11, R6 ; /* 0x0000000b0a067210 */
/* 0x008fe20007ffe006 */
/*0650*/ @P0 BRA 0x580 ; /* 0xffffff2000000947 */
/* 0x000fea000383ffff */
/*0660*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0670*/ @!P0 BRA 0x730 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0680*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc800078e00ff */
/*0690*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fc800078e0202 */
/*06a0*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0003 */
/*06b0*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */
/* 0x000fcc00078e0005 */
/*06c0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x0000a2000c1e1900 */
/*06d0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fc80007ffe0ff */
/*06e0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*06f0*/ IADD3 R2, P1, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fca0007f3e0ff */
/*0700*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fe400008e0605 */
/*0710*/ IMAD.IADD R6, R3, 0x1, R6 ; /* 0x0000000103067824 */
/* 0x004fc800078e0206 */
/*0720*/ @P0 BRA 0x6b0 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*0730*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0740*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0003 */
/*0750*/ STG.E [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x000fe2000c101904 */
/*0760*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0770*/ BRA 0x770; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<iostream>
#include<cstdio>
using namespace std;
__global__ void sum(int *a,int *b,int n)
{
int block=256*blockIdx.x;
int sum=0;
for(int i=block;i<min(block+256,n);i++)
{
sum=sum+a[i];
}
b[blockIdx.x]=sum;
}
int main()
{
cout<<"Enter the no of elements"<<endl;
int n;
cin>>n;
int a[n];
for(int i=0;i<n;i++)
{
a[i]=i+1;
}
int *ad,*bd;
int size=n*sizeof(int);
cudaMalloc(&ad,size);
cudaMemcpy(ad,a,size,cudaMemcpyHostToDevice);
int grids=ceil(n*1.0f/256.0f);
cudaMalloc(&bd,grids*sizeof(int));
dim3 grid(grids,1);
dim3 block(1,1);
int p=n;
while(n>1)
{
sum<<<grid,block>>>(ad,bd,n);
n=ceil(n*1.0f/256.0f);
cudaMemcpy(ad,bd,n*sizeof(int),cudaMemcpyDeviceToDevice);
}
int add[2];
n=p;
cudaMemcpy(add,ad,4,cudaMemcpyDeviceToHost);
cout<<"The sum is "<<add[0]<<endl;
float mean=0.0f;
mean=add[0]/(n*1.0f);
cout<<"The mean is "<<mean<<endl;
} | .file "tmpxft_00054ebe_00000000-6_A1_MEAN.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z3sumPiS_iPiS_i
.type _Z25__device_stub__Z3sumPiS_iPiS_i, @function
_Z25__device_stub__Z3sumPiS_iPiS_i:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3sumPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z25__device_stub__Z3sumPiS_iPiS_i, .-_Z25__device_stub__Z3sumPiS_iPiS_i
.globl _Z3sumPiS_i
.type _Z3sumPiS_i, @function
_Z3sumPiS_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3sumPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3sumPiS_i, .-_Z3sumPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter the no of elements"
.LC5:
.string "The sum is "
.LC6:
.string "The mean is "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r12
pushq %rbx
subq $80, %rsp
.cfi_offset 12, -24
.cfi_offset 3, -32
movq %fs:40, %rax
movq %rax, -24(%rbp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq -76(%rbp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movl -76(%rbp), %esi
movslq %esi, %rcx
leaq 15(,%rcx,4), %rax
movq %rax, %rdi
andq $-16, %rdi
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L12:
cmpq %rdx, %rsp
je .L13
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L12
.L13:
movq %rdi, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L14
orq $0, -8(%rsp,%rax)
.L14:
movq %rsp, %rbx
testl %esi, %esi
jle .L15
movl $1, %eax
.L16:
movl %eax, -4(%rbx,%rax,4)
movq %rax, %rdx
addq $1, %rax
cmpq %rdx, %rcx
jne .L16
.L15:
sall $2, %esi
movslq %esi, %r12
leaq -72(%rbp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq -72(%rbp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2ssl -76(%rbp), %xmm0
mulss .LC1(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC7(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC2(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L17
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC4(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L17:
cvttss2sil %xmm3, %ebx
movslq %ebx, %rsi
salq $2, %rsi
leaq -64(%rbp), %rdi
call cudaMalloc@PLT
movl %ebx, -56(%rbp)
movl $1, -52(%rbp)
movl $1, -48(%rbp)
movl $1, -44(%rbp)
movl $1, -40(%rbp)
movl $1, -36(%rbp)
movl -76(%rbp), %ebx
cmpl $1, %ebx
jg .L21
.L18:
movl %ebx, -76(%rbp)
leaq -32(%rbp), %rdi
movl $2, %ecx
movl $4, %edx
movq -72(%rbp), %rsi
call cudaMemcpy@PLT
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl -32(%rbp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
pxor %xmm1, %xmm1
cvtsi2ssl -32(%rbp), %xmm1
pxor %xmm0, %xmm0
cvtsi2ssl -76(%rbp), %xmm0
divss %xmm0, %xmm1
movss %xmm1, -84(%rbp)
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd -84(%rbp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq -24(%rbp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
leaq -16(%rbp), %rsp
popq %rbx
popq %r12
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L27:
.cfi_restore_state
movl -76(%rbp), %edx
movq -64(%rbp), %rsi
movq -72(%rbp), %rdi
call _Z25__device_stub__Z3sumPiS_iPiS_i
jmp .L19
.L20:
cvttss2sil %xmm2, %edx
movl %edx, -76(%rbp)
movslq %edx, %rdx
salq $2, %rdx
movl $3, %ecx
movq -64(%rbp), %rsi
movq -72(%rbp), %rdi
call cudaMemcpy@PLT
cmpl $1, -76(%rbp)
jle .L18
.L21:
movl -36(%rbp), %ecx
movl $0, %r9d
movl $0, %r8d
movq -44(%rbp), %rdx
movq -56(%rbp), %rdi
movl -48(%rbp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L19:
pxor %xmm0, %xmm0
cvtsi2ssl -76(%rbp), %xmm0
mulss .LC1(%rip), %xmm0
movaps %xmm0, %xmm2
movss .LC7(%rip), %xmm1
andps %xmm0, %xmm1
movss .LC2(%rip), %xmm5
ucomiss %xmm1, %xmm5
jbe .L20
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm2
movss .LC4(%rip), %xmm6
andps %xmm6, %xmm2
addss %xmm2, %xmm1
movss .LC7(%rip), %xmm2
andnps %xmm0, %xmm2
orps %xmm1, %xmm2
jmp .L20
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z3sumPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z3sumPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 998244352
.align 4
.LC2:
.long 1258291200
.align 4
.LC4:
.long 1065353216
.align 4
.LC7:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<iostream>
#include<cstdio>
using namespace std;
__global__ void sum(int *a,int *b,int n)
{
int block=256*blockIdx.x;
int sum=0;
for(int i=block;i<min(block+256,n);i++)
{
sum=sum+a[i];
}
b[blockIdx.x]=sum;
}
int main()
{
cout<<"Enter the no of elements"<<endl;
int n;
cin>>n;
int a[n];
for(int i=0;i<n;i++)
{
a[i]=i+1;
}
int *ad,*bd;
int size=n*sizeof(int);
cudaMalloc(&ad,size);
cudaMemcpy(ad,a,size,cudaMemcpyHostToDevice);
int grids=ceil(n*1.0f/256.0f);
cudaMalloc(&bd,grids*sizeof(int));
dim3 grid(grids,1);
dim3 block(1,1);
int p=n;
while(n>1)
{
sum<<<grid,block>>>(ad,bd,n);
n=ceil(n*1.0f/256.0f);
cudaMemcpy(ad,bd,n*sizeof(int),cudaMemcpyDeviceToDevice);
}
int add[2];
n=p;
cudaMemcpy(add,ad,4,cudaMemcpyDeviceToHost);
cout<<"The sum is "<<add[0]<<endl;
float mean=0.0f;
mean=add[0]/(n*1.0f);
cout<<"The mean is "<<mean<<endl;
} | #include <hip/hip_runtime.h>
#include<iostream>
#include<cstdio>
using namespace std;
__global__ void sum(int *a,int *b,int n)
{
int block=256*blockIdx.x;
int sum=0;
for(int i=block;i<min(block+256,n);i++)
{
sum=sum+a[i];
}
b[blockIdx.x]=sum;
}
int main()
{
cout<<"Enter the no of elements"<<endl;
int n;
cin>>n;
int a[n];
for(int i=0;i<n;i++)
{
a[i]=i+1;
}
int *ad,*bd;
int size=n*sizeof(int);
hipMalloc(&ad,size);
hipMemcpy(ad,a,size,hipMemcpyHostToDevice);
int grids=ceil(n*1.0f/256.0f);
hipMalloc(&bd,grids*sizeof(int));
dim3 grid(grids,1);
dim3 block(1,1);
int p=n;
while(n>1)
{
sum<<<grid,block>>>(ad,bd,n);
n=ceil(n*1.0f/256.0f);
hipMemcpy(ad,bd,n*sizeof(int),hipMemcpyDeviceToDevice);
}
int add[2];
n=p;
hipMemcpy(add,ad,4,hipMemcpyDeviceToHost);
cout<<"The sum is "<<add[0]<<endl;
float mean=0.0f;
mean=add[0]/(n*1.0f);
cout<<"The mean is "<<mean<<endl;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<iostream>
#include<cstdio>
using namespace std;
__global__ void sum(int *a,int *b,int n)
{
int block=256*blockIdx.x;
int sum=0;
for(int i=block;i<min(block+256,n);i++)
{
sum=sum+a[i];
}
b[blockIdx.x]=sum;
}
int main()
{
cout<<"Enter the no of elements"<<endl;
int n;
cin>>n;
int a[n];
for(int i=0;i<n;i++)
{
a[i]=i+1;
}
int *ad,*bd;
int size=n*sizeof(int);
hipMalloc(&ad,size);
hipMemcpy(ad,a,size,hipMemcpyHostToDevice);
int grids=ceil(n*1.0f/256.0f);
hipMalloc(&bd,grids*sizeof(int));
dim3 grid(grids,1);
dim3 block(1,1);
int p=n;
while(n>1)
{
sum<<<grid,block>>>(ad,bd,n);
n=ceil(n*1.0f/256.0f);
hipMemcpy(ad,bd,n*sizeof(int),hipMemcpyDeviceToDevice);
}
int add[2];
n=p;
hipMemcpy(add,ad,4,hipMemcpyDeviceToHost);
cout<<"The sum is "<<add[0]<<endl;
float mean=0.0f;
mean=add[0]/(n*1.0f);
cout<<"The mean is "<<mean<<endl;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3sumPiS_i
.globl _Z3sumPiS_i
.p2align 8
.type _Z3sumPiS_i,@function
_Z3sumPiS_i:
s_load_b32 s3, s[0:1], 0x10
s_lshl_b32 s4, s15, 8
s_mov_b32 s2, s15
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s4, s3
s_cbranch_scc1 .LBB0_3
s_load_b64 s[6:7], s[0:1], 0x0
s_ashr_i32 s5, s4, 31
s_add_i32 s10, s4, 0x100
s_lshl_b64 s[8:9], s[4:5], 2
s_min_i32 s3, s10, s3
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s6, s8
s_addc_u32 s7, s7, s9
.LBB0_2:
s_load_b32 s8, s[6:7], 0x0
s_add_i32 s4, s4, 1
s_waitcnt lgkmcnt(0)
s_add_i32 s5, s8, s5
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_ge_i32 s4, s3
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s5
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3sumPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3sumPiS_i, .Lfunc_end0-_Z3sumPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3sumPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3sumPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<iostream>
#include<cstdio>
using namespace std;
__global__ void sum(int *a,int *b,int n)
{
int block=256*blockIdx.x;
int sum=0;
for(int i=block;i<min(block+256,n);i++)
{
sum=sum+a[i];
}
b[blockIdx.x]=sum;
}
int main()
{
cout<<"Enter the no of elements"<<endl;
int n;
cin>>n;
int a[n];
for(int i=0;i<n;i++)
{
a[i]=i+1;
}
int *ad,*bd;
int size=n*sizeof(int);
hipMalloc(&ad,size);
hipMemcpy(ad,a,size,hipMemcpyHostToDevice);
int grids=ceil(n*1.0f/256.0f);
hipMalloc(&bd,grids*sizeof(int));
dim3 grid(grids,1);
dim3 block(1,1);
int p=n;
while(n>1)
{
sum<<<grid,block>>>(ad,bd,n);
n=ceil(n*1.0f/256.0f);
hipMemcpy(ad,bd,n*sizeof(int),hipMemcpyDeviceToDevice);
}
int add[2];
n=p;
hipMemcpy(add,ad,4,hipMemcpyDeviceToHost);
cout<<"The sum is "<<add[0]<<endl;
float mean=0.0f;
mean=add[0]/(n*1.0f);
cout<<"The mean is "<<mean<<endl;
} | .text
.file "A1_MEAN.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__sumPiS_i # -- Begin function _Z18__device_stub__sumPiS_i
.p2align 4, 0x90
.type _Z18__device_stub__sumPiS_i,@function
_Z18__device_stub__sumPiS_i: # @_Z18__device_stub__sumPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3sumPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__sumPiS_i, .Lfunc_end0-_Z18__device_stub__sumPiS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3b800000 # float 0.00390625
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $136, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $24, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_21
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB1_4
.LBB1_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq -44(%rbp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movq %rsp, -104(%rbp) # 8-byte Spill
movl -44(%rbp), %eax
movq %rsp, %rbx
leaq 15(,%rax,4), %rax
andq $-16, %rax
subq %rax, %rbx
movq %rbx, %rsp
movl -44(%rbp), %eax
testl %eax, %eax
jle .LBB1_7
# %bb.5: # %.lr.ph.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_6: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leaq 1(%rcx), %rdx
movl %edx, (%rbx,%rcx,4)
movq %rdx, %rcx
cmpq %rdx, %rax
jne .LBB1_6
.LBB1_7: # %._crit_edge
shll $2, %eax
movslq %eax, %r14
leaq -56(%rbp), %rdi
movq %r14, %rsi
callq hipMalloc
movq -56(%rbp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
cvtsi2ssl -44(%rbp), %xmm0
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %ebx
movslq %ebx, %rsi
shlq $2, %rsi
leaq -72(%rbp), %rdi
callq hipMalloc
movl -44(%rbp), %eax
movl %eax, -48(%rbp) # 4-byte Spill
cmpl $2, %eax
jl .LBB1_12
# %bb.8:
movabsq $4294967296, %r14 # imm = 0x100000000
orq %r14, %rbx
incq %r14
leaq -120(%rbp), %r13
leaq -112(%rbp), %r15
leaq -96(%rbp), %r12
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_11: # in Loop: Header=BB1_9 Depth=1
xorps %xmm0, %xmm0
cvtsi2ssl -44(%rbp), %xmm0
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %eax
movl %eax, -44(%rbp)
movq -56(%rbp), %rdi
movq -72(%rbp), %rsi
movslq %eax, %rdx
shlq $2, %rdx
movl $3, %ecx
callq hipMemcpy
cmpl $1, -44(%rbp)
jle .LBB1_12
.LBB1_9: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_11
# %bb.10: # in Loop: Header=BB1_9 Depth=1
movq -56(%rbp), %rax
movq -72(%rbp), %rcx
movl -44(%rbp), %edx
movq %rax, -168(%rbp)
movq %rcx, -160(%rbp)
movl %edx, -60(%rbp)
leaq -168(%rbp), %rax
movq %rax, -96(%rbp)
leaq -160(%rbp), %rax
movq %rax, -88(%rbp)
leaq -60(%rbp), %rax
movq %rax, -80(%rbp)
leaq -152(%rbp), %rdi
leaq -136(%rbp), %rsi
movq %r13, %rdx
movq %r15, %rcx
callq __hipPopCallConfiguration
movq -152(%rbp), %rsi
movl -144(%rbp), %edx
movq -136(%rbp), %rcx
movl -128(%rbp), %r8d
movl $_Z3sumPiS_i, %edi
movq %r12, %r9
pushq -112(%rbp)
pushq -120(%rbp)
callq hipLaunchKernel
addq $16, %rsp
jmp .LBB1_11
.LBB1_12: # %._crit_edge32
movl -48(%rbp), %eax # 4-byte Reload
movl %eax, -44(%rbp)
movq -56(%rbp), %rsi
leaq -96(%rbp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl -96(%rbp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_21
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i18
cmpb $0, 56(%rbx)
je .LBB1_15
# %bb.14:
movzbl 67(%rbx), %ecx
jmp .LBB1_16
.LBB1_15:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit21
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cvtsi2ssl -96(%rbp), %xmm1
xorps %xmm0, %xmm0
cvtsi2ssl -44(%rbp), %xmm0
divss %xmm0, %xmm1
movss %xmm1, -48(%rbp) # 4-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss -48(%rbp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_21
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i23
cmpb $0, 56(%rbx)
je .LBB1_19
# %bb.18:
movzbl 67(%rbx), %ecx
jmp .LBB1_20
.LBB1_19:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit26
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq -104(%rbp), %rsp # 8-byte Reload
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB1_21:
.cfi_def_cfa %rbp, 16
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3sumPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3sumPiS_i,@object # @_Z3sumPiS_i
.section .rodata,"a",@progbits
.globl _Z3sumPiS_i
.p2align 3, 0x0
_Z3sumPiS_i:
.quad _Z18__device_stub__sumPiS_i
.size _Z3sumPiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter the no of elements"
.size .L.str, 25
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "The sum is "
.size .L.str.1, 13
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "The mean is "
.size .L.str.2, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3sumPiS_i"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__sumPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3sumPiS_i
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3sumPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*0040*/ IMAD.SHL.U32 R5, R0, 0x100, RZ ; /* 0x0000010000057824 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R2, R5, 0x100, RZ ; /* 0x0000010005027810 */
/* 0x000fc80007ffe0ff */
/*0060*/ IMNMX R2, R2, c[0x0][0x170], PT ; /* 0x00005c0002027a17 */
/* 0x000fc80003800200 */
/*0070*/ ISETP.GE.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x000fda0003f06270 */
/*0080*/ @P0 BRA 0x730 ; /* 0x000006a000000947 */
/* 0x000fea0003800000 */
/*0090*/ LOP3.LUT R2, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff027a12 */
/* 0x000fe200078e33ff */
/*00a0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*00b0*/ IADD3 R3, -R5, -0x101, RZ ; /* 0xfffffeff05037810 */
/* 0x000fc80007ffe1ff */
/*00c0*/ IMNMX R8, R2, R3, !PT ; /* 0x0000000302087217 */
/* 0x000fc80007800200 */
/*00d0*/ IADD3 R3, -R5, -0x2, -R8 ; /* 0xfffffffe05037810 */
/* 0x000fe40007ffe908 */
/*00e0*/ LOP3.LUT R2, RZ, R8, RZ, 0x33, !PT ; /* 0x00000008ff027212 */
/* 0x000fe400078e33ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fc60003f06070 */
/*0100*/ IMAD.IADD R2, R2, 0x1, -R5 ; /* 0x0000000102027824 */
/* 0x000fca00078e0a05 */
/*0110*/ LOP3.LUT R4, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302047812 */
/* 0x000fca00078ec0ff */
/*0120*/ @!P0 BRA 0x660 ; /* 0x0000053000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R7, R4, R8, R5 ; /* 0x0000000804077210 */
/* 0x000fe20007ffe005 */
/*0140*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe400078e00ff */
/*0150*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*0160*/ IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0a07 */
/*0170*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fc600078e0202 */
/*0180*/ ISETP.GT.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe40003f04270 */
/*0190*/ IADD3 R2, P1, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fca0007f3e0ff */
/*01a0*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fcc00008e0603 */
/*01b0*/ @!P0 BRA 0x580 ; /* 0x000003c000008947 */
/* 0x000fea0003800000 */
/*01c0*/ IADD3 R8, R7, -0x1, RZ ; /* 0xffffffff07087810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*01e0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fda0003f24270 */
/*01f0*/ @!P1 BRA 0x400 ; /* 0x0000020000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ LDG.E R13, [R2.64+-0x8] ; /* 0xfffff804020d7981 */
/* 0x000ea8000c1e1900 */
/*0220*/ LDG.E R12, [R2.64+-0x4] ; /* 0xfffffc04020c7981 */
/* 0x000ea8000c1e1900 */
/*0230*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x0000e8000c1e1900 */
/*0240*/ LDG.E R14, [R2.64+0x4] ; /* 0x00000404020e7981 */
/* 0x0000e8000c1e1900 */
/*0250*/ LDG.E R17, [R2.64+0x8] ; /* 0x0000080402117981 */
/* 0x000128000c1e1900 */
/*0260*/ LDG.E R16, [R2.64+0xc] ; /* 0x00000c0402107981 */
/* 0x000128000c1e1900 */
/*0270*/ LDG.E R19, [R2.64+0x10] ; /* 0x0000100402137981 */
/* 0x000168000c1e1900 */
/*0280*/ LDG.E R18, [R2.64+0x14] ; /* 0x0000140402127981 */
/* 0x000168000c1e1900 */
/*0290*/ LDG.E R21, [R2.64+0x18] ; /* 0x0000180402157981 */
/* 0x000168000c1e1900 */
/*02a0*/ LDG.E R20, [R2.64+0x1c] ; /* 0x00001c0402147981 */
/* 0x000168000c1e1900 */
/*02b0*/ LDG.E R23, [R2.64+0x20] ; /* 0x0000200402177981 */
/* 0x000168000c1e1900 */
/*02c0*/ LDG.E R22, [R2.64+0x24] ; /* 0x0000240402167981 */
/* 0x000168000c1e1900 */
/*02d0*/ LDG.E R11, [R2.64+0x28] ; /* 0x00002804020b7981 */
/* 0x000168000c1e1900 */
/*02e0*/ LDG.E R10, [R2.64+0x2c] ; /* 0x00002c04020a7981 */
/* 0x000168000c1e1900 */
/*02f0*/ LDG.E R9, [R2.64+0x30] ; /* 0x0000300402097981 */
/* 0x000168000c1e1900 */
/*0300*/ LDG.E R8, [R2.64+0x34] ; /* 0x0000340402087981 */
/* 0x000162000c1e1900 */
/*0310*/ IADD3 R7, R7, -0x10, RZ ; /* 0xfffffff007077810 */
/* 0x000fc40007ffe0ff */
/*0320*/ IADD3 R5, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x000fe40007ffe0ff */
/*0330*/ ISETP.GT.AND P1, PT, R7, 0xd, PT ; /* 0x0000000d0700780c */
/* 0x000fe40003f24270 */
/*0340*/ IADD3 R12, R12, R13, R6 ; /* 0x0000000d0c0c7210 */
/* 0x004fe40007ffe006 */
/*0350*/ IADD3 R13, P2, R2, 0x40, RZ ; /* 0x00000040020d7810 */
/* 0x000fca0007f5e0ff */
/*0360*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x001fe200010e0603 */
/*0370*/ IADD3 R12, R14, R15, R12 ; /* 0x0000000f0e0c7210 */
/* 0x008fe20007ffe00c */
/*0380*/ IMAD.MOV.U32 R2, RZ, RZ, R13 ; /* 0x000000ffff027224 */
/* 0x000fc600078e000d */
/*0390*/ IADD3 R12, R16, R17, R12 ; /* 0x00000011100c7210 */
/* 0x010fc80007ffe00c */
/*03a0*/ IADD3 R12, R18, R19, R12 ; /* 0x00000013120c7210 */
/* 0x020fc80007ffe00c */
/*03b0*/ IADD3 R12, R20, R21, R12 ; /* 0x00000015140c7210 */
/* 0x000fc80007ffe00c */
/*03c0*/ IADD3 R12, R22, R23, R12 ; /* 0x00000017160c7210 */
/* 0x000fc80007ffe00c */
/*03d0*/ IADD3 R10, R10, R11, R12 ; /* 0x0000000b0a0a7210 */
/* 0x000fc80007ffe00c */
/*03e0*/ IADD3 R6, R8, R9, R10 ; /* 0x0000000908067210 */
/* 0x000fe20007ffe00a */
/*03f0*/ @P1 BRA 0x210 ; /* 0xfffffe1000001947 */
/* 0x000fea000383ffff */
/*0400*/ IADD3 R8, R7, -0x1, RZ ; /* 0xffffffff07087810 */
/* 0x000fc80007ffe0ff */
/*0410*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0420*/ @!P1 BRA 0x560 ; /* 0x0000013000009947 */
/* 0x000fea0003800000 */
/*0430*/ LDG.E R9, [R2.64+-0x8] ; /* 0xfffff80402097981 */
/* 0x000ea8000c1e1900 */
/*0440*/ LDG.E R8, [R2.64+-0x4] ; /* 0xfffffc0402087981 */
/* 0x000ea8000c1e1900 */
/*0450*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x0000e8000c1e1900 */
/*0460*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000404020a7981 */
/* 0x0000e8000c1e1900 */
/*0470*/ LDG.E R13, [R2.64+0x8] ; /* 0x00000804020d7981 */
/* 0x000128000c1e1900 */
/*0480*/ LDG.E R12, [R2.64+0xc] ; /* 0x00000c04020c7981 */
/* 0x000128000c1e1900 */
/*0490*/ LDG.E R15, [R2.64+0x10] ; /* 0x00001004020f7981 */
/* 0x000168000c1e1900 */
/*04a0*/ LDG.E R14, [R2.64+0x14] ; /* 0x00001404020e7981 */
/* 0x000162000c1e1900 */
/*04b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*04c0*/ IADD3 R5, R5, 0x8, RZ ; /* 0x0000000805057810 */
/* 0x000fe40007ffe0ff */
/*04d0*/ IADD3 R7, R7, -0x8, RZ ; /* 0xfffffff807077810 */
/* 0x000fe40007ffe0ff */
/*04e0*/ IADD3 R8, R8, R9, R6 ; /* 0x0000000908087210 */
/* 0x004fe40007ffe006 */
/*04f0*/ IADD3 R9, P1, R2, 0x20, RZ ; /* 0x0000002002097810 */
/* 0x000fca0007f3e0ff */
/*0500*/ IMAD.MOV.U32 R2, RZ, RZ, R9 ; /* 0x000000ffff027224 */
/* 0x001fe200078e0009 */
/*0510*/ IADD3 R8, R10, R11, R8 ; /* 0x0000000b0a087210 */
/* 0x008fe20007ffe008 */
/*0520*/ IMAD.X R10, RZ, RZ, R3, P1 ; /* 0x000000ffff0a7224 */
/* 0x000fc800008e0603 */
/*0530*/ IMAD.MOV.U32 R3, RZ, RZ, R10 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000a */
/*0540*/ IADD3 R8, R12, R13, R8 ; /* 0x0000000d0c087210 */
/* 0x010fc80007ffe008 */
/*0550*/ IADD3 R6, R14, R15, R8 ; /* 0x0000000f0e067210 */
/* 0x020fe40007ffe008 */
/*0560*/ ISETP.NE.OR P0, PT, R7, 0x1, P0 ; /* 0x000000010700780c */
/* 0x000fda0000705670 */
/*0570*/ @!P0 BRA 0x660 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0580*/ LDG.E R9, [R2.64+-0x8] ; /* 0xfffff80402097981 */
/* 0x0000a8000c1e1900 */
/*0590*/ LDG.E R8, [R2.64+-0x4] ; /* 0xfffffc0402087981 */
/* 0x0000a8000c1e1900 */
/*05a0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x0000e8000c1e1900 */
/*05b0*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000404020a7981 */
/* 0x0000e2000c1e1900 */
/*05c0*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fc40007ffe0ff */
/*05d0*/ IADD3 R12, P1, R2, 0x10, RZ ; /* 0x00000010020c7810 */
/* 0x000fe40007f3e0ff */
/*05e0*/ ISETP.NE.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe40003f05270 */
/*05f0*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fe20007ffe0ff */
/*0600*/ IMAD.X R13, RZ, RZ, R3, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe400008e0603 */
/*0610*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x001fe400078e000c */
/*0620*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000d */
/*0630*/ IADD3 R6, R8, R9, R6 ; /* 0x0000000908067210 */
/* 0x004fc80007ffe006 */
/*0640*/ IADD3 R6, R10, R11, R6 ; /* 0x0000000b0a067210 */
/* 0x008fe20007ffe006 */
/*0650*/ @P0 BRA 0x580 ; /* 0xffffff2000000947 */
/* 0x000fea000383ffff */
/*0660*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0670*/ @!P0 BRA 0x730 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0680*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc800078e00ff */
/*0690*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fc800078e0202 */
/*06a0*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0003 */
/*06b0*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */
/* 0x000fcc00078e0005 */
/*06c0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x0000a2000c1e1900 */
/*06d0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fc80007ffe0ff */
/*06e0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*06f0*/ IADD3 R2, P1, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fca0007f3e0ff */
/*0700*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fe400008e0605 */
/*0710*/ IMAD.IADD R6, R3, 0x1, R6 ; /* 0x0000000103067824 */
/* 0x004fc800078e0206 */
/*0720*/ @P0 BRA 0x6b0 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*0730*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0740*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0003 */
/*0750*/ STG.E [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x000fe2000c101904 */
/*0760*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0770*/ BRA 0x770; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3sumPiS_i
.globl _Z3sumPiS_i
.p2align 8
.type _Z3sumPiS_i,@function
_Z3sumPiS_i:
s_load_b32 s3, s[0:1], 0x10
s_lshl_b32 s4, s15, 8
s_mov_b32 s2, s15
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s4, s3
s_cbranch_scc1 .LBB0_3
s_load_b64 s[6:7], s[0:1], 0x0
s_ashr_i32 s5, s4, 31
s_add_i32 s10, s4, 0x100
s_lshl_b64 s[8:9], s[4:5], 2
s_min_i32 s3, s10, s3
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s6, s8
s_addc_u32 s7, s7, s9
.LBB0_2:
s_load_b32 s8, s[6:7], 0x0
s_add_i32 s4, s4, 1
s_waitcnt lgkmcnt(0)
s_add_i32 s5, s8, s5
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_ge_i32 s4, s3
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s5
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3sumPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3sumPiS_i, .Lfunc_end0-_Z3sumPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3sumPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3sumPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00054ebe_00000000-6_A1_MEAN.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z3sumPiS_iPiS_i
.type _Z25__device_stub__Z3sumPiS_iPiS_i, @function
_Z25__device_stub__Z3sumPiS_iPiS_i:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3sumPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z25__device_stub__Z3sumPiS_iPiS_i, .-_Z25__device_stub__Z3sumPiS_iPiS_i
.globl _Z3sumPiS_i
.type _Z3sumPiS_i, @function
_Z3sumPiS_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3sumPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3sumPiS_i, .-_Z3sumPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter the no of elements"
.LC5:
.string "The sum is "
.LC6:
.string "The mean is "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r12
pushq %rbx
subq $80, %rsp
.cfi_offset 12, -24
.cfi_offset 3, -32
movq %fs:40, %rax
movq %rax, -24(%rbp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq -76(%rbp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movl -76(%rbp), %esi
movslq %esi, %rcx
leaq 15(,%rcx,4), %rax
movq %rax, %rdi
andq $-16, %rdi
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L12:
cmpq %rdx, %rsp
je .L13
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L12
.L13:
movq %rdi, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L14
orq $0, -8(%rsp,%rax)
.L14:
movq %rsp, %rbx
testl %esi, %esi
jle .L15
movl $1, %eax
.L16:
movl %eax, -4(%rbx,%rax,4)
movq %rax, %rdx
addq $1, %rax
cmpq %rdx, %rcx
jne .L16
.L15:
sall $2, %esi
movslq %esi, %r12
leaq -72(%rbp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq -72(%rbp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2ssl -76(%rbp), %xmm0
mulss .LC1(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC7(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC2(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L17
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC4(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L17:
cvttss2sil %xmm3, %ebx
movslq %ebx, %rsi
salq $2, %rsi
leaq -64(%rbp), %rdi
call cudaMalloc@PLT
movl %ebx, -56(%rbp)
movl $1, -52(%rbp)
movl $1, -48(%rbp)
movl $1, -44(%rbp)
movl $1, -40(%rbp)
movl $1, -36(%rbp)
movl -76(%rbp), %ebx
cmpl $1, %ebx
jg .L21
.L18:
movl %ebx, -76(%rbp)
leaq -32(%rbp), %rdi
movl $2, %ecx
movl $4, %edx
movq -72(%rbp), %rsi
call cudaMemcpy@PLT
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl -32(%rbp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
pxor %xmm1, %xmm1
cvtsi2ssl -32(%rbp), %xmm1
pxor %xmm0, %xmm0
cvtsi2ssl -76(%rbp), %xmm0
divss %xmm0, %xmm1
movss %xmm1, -84(%rbp)
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd -84(%rbp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq -24(%rbp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
leaq -16(%rbp), %rsp
popq %rbx
popq %r12
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L27:
.cfi_restore_state
movl -76(%rbp), %edx
movq -64(%rbp), %rsi
movq -72(%rbp), %rdi
call _Z25__device_stub__Z3sumPiS_iPiS_i
jmp .L19
.L20:
cvttss2sil %xmm2, %edx
movl %edx, -76(%rbp)
movslq %edx, %rdx
salq $2, %rdx
movl $3, %ecx
movq -64(%rbp), %rsi
movq -72(%rbp), %rdi
call cudaMemcpy@PLT
cmpl $1, -76(%rbp)
jle .L18
.L21:
movl -36(%rbp), %ecx
movl $0, %r9d
movl $0, %r8d
movq -44(%rbp), %rdx
movq -56(%rbp), %rdi
movl -48(%rbp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L19:
pxor %xmm0, %xmm0
cvtsi2ssl -76(%rbp), %xmm0
mulss .LC1(%rip), %xmm0
movaps %xmm0, %xmm2
movss .LC7(%rip), %xmm1
andps %xmm0, %xmm1
movss .LC2(%rip), %xmm5
ucomiss %xmm1, %xmm5
jbe .L20
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm2
movss .LC4(%rip), %xmm6
andps %xmm6, %xmm2
addss %xmm2, %xmm1
movss .LC7(%rip), %xmm2
andnps %xmm0, %xmm2
orps %xmm1, %xmm2
jmp .L20
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z3sumPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z3sumPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 998244352
.align 4
.LC2:
.long 1258291200
.align 4
.LC4:
.long 1065353216
.align 4
.LC7:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "A1_MEAN.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__sumPiS_i # -- Begin function _Z18__device_stub__sumPiS_i
.p2align 4, 0x90
.type _Z18__device_stub__sumPiS_i,@function
_Z18__device_stub__sumPiS_i: # @_Z18__device_stub__sumPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3sumPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__sumPiS_i, .Lfunc_end0-_Z18__device_stub__sumPiS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3b800000 # float 0.00390625
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $136, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $24, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_21
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB1_4
.LBB1_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq -44(%rbp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movq %rsp, -104(%rbp) # 8-byte Spill
movl -44(%rbp), %eax
movq %rsp, %rbx
leaq 15(,%rax,4), %rax
andq $-16, %rax
subq %rax, %rbx
movq %rbx, %rsp
movl -44(%rbp), %eax
testl %eax, %eax
jle .LBB1_7
# %bb.5: # %.lr.ph.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_6: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leaq 1(%rcx), %rdx
movl %edx, (%rbx,%rcx,4)
movq %rdx, %rcx
cmpq %rdx, %rax
jne .LBB1_6
.LBB1_7: # %._crit_edge
shll $2, %eax
movslq %eax, %r14
leaq -56(%rbp), %rdi
movq %r14, %rsi
callq hipMalloc
movq -56(%rbp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
cvtsi2ssl -44(%rbp), %xmm0
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %ebx
movslq %ebx, %rsi
shlq $2, %rsi
leaq -72(%rbp), %rdi
callq hipMalloc
movl -44(%rbp), %eax
movl %eax, -48(%rbp) # 4-byte Spill
cmpl $2, %eax
jl .LBB1_12
# %bb.8:
movabsq $4294967296, %r14 # imm = 0x100000000
orq %r14, %rbx
incq %r14
leaq -120(%rbp), %r13
leaq -112(%rbp), %r15
leaq -96(%rbp), %r12
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_11: # in Loop: Header=BB1_9 Depth=1
xorps %xmm0, %xmm0
cvtsi2ssl -44(%rbp), %xmm0
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %eax
movl %eax, -44(%rbp)
movq -56(%rbp), %rdi
movq -72(%rbp), %rsi
movslq %eax, %rdx
shlq $2, %rdx
movl $3, %ecx
callq hipMemcpy
cmpl $1, -44(%rbp)
jle .LBB1_12
.LBB1_9: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_11
# %bb.10: # in Loop: Header=BB1_9 Depth=1
movq -56(%rbp), %rax
movq -72(%rbp), %rcx
movl -44(%rbp), %edx
movq %rax, -168(%rbp)
movq %rcx, -160(%rbp)
movl %edx, -60(%rbp)
leaq -168(%rbp), %rax
movq %rax, -96(%rbp)
leaq -160(%rbp), %rax
movq %rax, -88(%rbp)
leaq -60(%rbp), %rax
movq %rax, -80(%rbp)
leaq -152(%rbp), %rdi
leaq -136(%rbp), %rsi
movq %r13, %rdx
movq %r15, %rcx
callq __hipPopCallConfiguration
movq -152(%rbp), %rsi
movl -144(%rbp), %edx
movq -136(%rbp), %rcx
movl -128(%rbp), %r8d
movl $_Z3sumPiS_i, %edi
movq %r12, %r9
pushq -112(%rbp)
pushq -120(%rbp)
callq hipLaunchKernel
addq $16, %rsp
jmp .LBB1_11
.LBB1_12: # %._crit_edge32
movl -48(%rbp), %eax # 4-byte Reload
movl %eax, -44(%rbp)
movq -56(%rbp), %rsi
leaq -96(%rbp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl -96(%rbp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_21
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i18
cmpb $0, 56(%rbx)
je .LBB1_15
# %bb.14:
movzbl 67(%rbx), %ecx
jmp .LBB1_16
.LBB1_15:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit21
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cvtsi2ssl -96(%rbp), %xmm1
xorps %xmm0, %xmm0
cvtsi2ssl -44(%rbp), %xmm0
divss %xmm0, %xmm1
movss %xmm1, -48(%rbp) # 4-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss -48(%rbp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_21
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i23
cmpb $0, 56(%rbx)
je .LBB1_19
# %bb.18:
movzbl 67(%rbx), %ecx
jmp .LBB1_20
.LBB1_19:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit26
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq -104(%rbp), %rsp # 8-byte Reload
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB1_21:
.cfi_def_cfa %rbp, 16
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3sumPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3sumPiS_i,@object # @_Z3sumPiS_i
.section .rodata,"a",@progbits
.globl _Z3sumPiS_i
.p2align 3, 0x0
_Z3sumPiS_i:
.quad _Z18__device_stub__sumPiS_i
.size _Z3sumPiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter the no of elements"
.size .L.str, 25
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "The sum is "
.size .L.str.1, 13
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "The mean is "
.size .L.str.2, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3sumPiS_i"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__sumPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3sumPiS_i
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void fillOneIntegerArrayKernel(
int numberRows,
int numberEntries,
int* array,
int constant) {
int index = blockIdx.x * numberEntries + blockIdx.y * numberRows + threadIdx.x;
array[index] = constant;
} | code for sm_80
Function : _Z25fillOneIntegerArrayKerneliiPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0060*/ IMAD R0, R0, c[0x0][0x160], R5 ; /* 0x0000580000007a24 */
/* 0x001fe200078e0205 */
/*0070*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fc600000001ff */
/*0080*/ IMAD R0, R3, c[0x0][0x164], R0 ; /* 0x0000590003007a24 */
/* 0x002fce00078e0200 */
/*0090*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0205 */
/*00a0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void fillOneIntegerArrayKernel(
int numberRows,
int numberEntries,
int* array,
int constant) {
int index = blockIdx.x * numberEntries + blockIdx.y * numberRows + threadIdx.x;
array[index] = constant;
} | .file "tmpxft_00144903_00000000-6_FillOneIntegerArrayKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z25fillOneIntegerArrayKerneliiPiiiiPii
.type _Z48__device_stub__Z25fillOneIntegerArrayKerneliiPiiiiPii, @function
_Z48__device_stub__Z25fillOneIntegerArrayKerneliiPiiiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25fillOneIntegerArrayKerneliiPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z48__device_stub__Z25fillOneIntegerArrayKerneliiPiiiiPii, .-_Z48__device_stub__Z25fillOneIntegerArrayKerneliiPiiiiPii
.globl _Z25fillOneIntegerArrayKerneliiPii
.type _Z25fillOneIntegerArrayKerneliiPii, @function
_Z25fillOneIntegerArrayKerneliiPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z25fillOneIntegerArrayKerneliiPiiiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z25fillOneIntegerArrayKerneliiPii, .-_Z25fillOneIntegerArrayKerneliiPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z25fillOneIntegerArrayKerneliiPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z25fillOneIntegerArrayKerneliiPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void fillOneIntegerArrayKernel(
int numberRows,
int numberEntries,
int* array,
int constant) {
int index = blockIdx.x * numberEntries + blockIdx.y * numberRows + threadIdx.x;
array[index] = constant;
} | #include <hip/hip_runtime.h>
__global__ void fillOneIntegerArrayKernel(
int numberRows,
int numberEntries,
int* array,
int constant) {
int index = blockIdx.x * numberEntries + blockIdx.y * numberRows + threadIdx.x;
array[index] = constant;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void fillOneIntegerArrayKernel(
int numberRows,
int numberEntries,
int* array,
int constant) {
int index = blockIdx.x * numberEntries + blockIdx.y * numberRows + threadIdx.x;
array[index] = constant;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25fillOneIntegerArrayKerneliiPii
.globl _Z25fillOneIntegerArrayKerneliiPii
.p2align 8
.type _Z25fillOneIntegerArrayKerneliiPii,@function
_Z25fillOneIntegerArrayKerneliiPii:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s14, s14, s5
s_mul_i32 s15, s15, s4
v_mov_b32_e32 v2, s0
v_add3_u32 v0, s14, s15, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25fillOneIntegerArrayKerneliiPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25fillOneIntegerArrayKerneliiPii, .Lfunc_end0-_Z25fillOneIntegerArrayKerneliiPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25fillOneIntegerArrayKerneliiPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25fillOneIntegerArrayKerneliiPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void fillOneIntegerArrayKernel(
int numberRows,
int numberEntries,
int* array,
int constant) {
int index = blockIdx.x * numberEntries + blockIdx.y * numberRows + threadIdx.x;
array[index] = constant;
} | .text
.file "FillOneIntegerArrayKernel.hip"
.globl _Z40__device_stub__fillOneIntegerArrayKerneliiPii # -- Begin function _Z40__device_stub__fillOneIntegerArrayKerneliiPii
.p2align 4, 0x90
.type _Z40__device_stub__fillOneIntegerArrayKerneliiPii,@function
_Z40__device_stub__fillOneIntegerArrayKerneliiPii: # @_Z40__device_stub__fillOneIntegerArrayKerneliiPii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25fillOneIntegerArrayKerneliiPii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z40__device_stub__fillOneIntegerArrayKerneliiPii, .Lfunc_end0-_Z40__device_stub__fillOneIntegerArrayKerneliiPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25fillOneIntegerArrayKerneliiPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25fillOneIntegerArrayKerneliiPii,@object # @_Z25fillOneIntegerArrayKerneliiPii
.section .rodata,"a",@progbits
.globl _Z25fillOneIntegerArrayKerneliiPii
.p2align 3, 0x0
_Z25fillOneIntegerArrayKerneliiPii:
.quad _Z40__device_stub__fillOneIntegerArrayKerneliiPii
.size _Z25fillOneIntegerArrayKerneliiPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25fillOneIntegerArrayKerneliiPii"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__fillOneIntegerArrayKerneliiPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25fillOneIntegerArrayKerneliiPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z25fillOneIntegerArrayKerneliiPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0060*/ IMAD R0, R0, c[0x0][0x160], R5 ; /* 0x0000580000007a24 */
/* 0x001fe200078e0205 */
/*0070*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fc600000001ff */
/*0080*/ IMAD R0, R3, c[0x0][0x164], R0 ; /* 0x0000590003007a24 */
/* 0x002fce00078e0200 */
/*0090*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0205 */
/*00a0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25fillOneIntegerArrayKerneliiPii
.globl _Z25fillOneIntegerArrayKerneliiPii
.p2align 8
.type _Z25fillOneIntegerArrayKerneliiPii,@function
_Z25fillOneIntegerArrayKerneliiPii:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s14, s14, s5
s_mul_i32 s15, s15, s4
v_mov_b32_e32 v2, s0
v_add3_u32 v0, s14, s15, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25fillOneIntegerArrayKerneliiPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25fillOneIntegerArrayKerneliiPii, .Lfunc_end0-_Z25fillOneIntegerArrayKerneliiPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25fillOneIntegerArrayKerneliiPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25fillOneIntegerArrayKerneliiPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00144903_00000000-6_FillOneIntegerArrayKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z25fillOneIntegerArrayKerneliiPiiiiPii
.type _Z48__device_stub__Z25fillOneIntegerArrayKerneliiPiiiiPii, @function
_Z48__device_stub__Z25fillOneIntegerArrayKerneliiPiiiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25fillOneIntegerArrayKerneliiPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z48__device_stub__Z25fillOneIntegerArrayKerneliiPiiiiPii, .-_Z48__device_stub__Z25fillOneIntegerArrayKerneliiPiiiiPii
.globl _Z25fillOneIntegerArrayKerneliiPii
.type _Z25fillOneIntegerArrayKerneliiPii, @function
_Z25fillOneIntegerArrayKerneliiPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z25fillOneIntegerArrayKerneliiPiiiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z25fillOneIntegerArrayKerneliiPii, .-_Z25fillOneIntegerArrayKerneliiPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z25fillOneIntegerArrayKerneliiPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z25fillOneIntegerArrayKerneliiPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "FillOneIntegerArrayKernel.hip"
.globl _Z40__device_stub__fillOneIntegerArrayKerneliiPii # -- Begin function _Z40__device_stub__fillOneIntegerArrayKerneliiPii
.p2align 4, 0x90
.type _Z40__device_stub__fillOneIntegerArrayKerneliiPii,@function
_Z40__device_stub__fillOneIntegerArrayKerneliiPii: # @_Z40__device_stub__fillOneIntegerArrayKerneliiPii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25fillOneIntegerArrayKerneliiPii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z40__device_stub__fillOneIntegerArrayKerneliiPii, .Lfunc_end0-_Z40__device_stub__fillOneIntegerArrayKerneliiPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25fillOneIntegerArrayKerneliiPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25fillOneIntegerArrayKerneliiPii,@object # @_Z25fillOneIntegerArrayKerneliiPii
.section .rodata,"a",@progbits
.globl _Z25fillOneIntegerArrayKerneliiPii
.p2align 3, 0x0
_Z25fillOneIntegerArrayKerneliiPii:
.quad _Z40__device_stub__fillOneIntegerArrayKerneliiPii
.size _Z25fillOneIntegerArrayKerneliiPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25fillOneIntegerArrayKerneliiPii"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__fillOneIntegerArrayKerneliiPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25fillOneIntegerArrayKerneliiPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* NiuTrans.Tensor - an open-source tensor library
* Copyright (C) 2017, Natural Language Processing Lab, Northeastern University.
* All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* $Created by: Xu Chen (email: hello_master1954@163.com) 2018-09-17
*/
#ifndef __CROSSENTROPY_CUH__
#define __CROSSENTROPY_CUH__
#include "../XTensor.h"
#include "../XDevice.h"
#include "CrossEntropy.cuh"
#include "CrossEntropy.h"
#include "../core/arithmetic/Div.h"
#include "../core/arithmetic/Multiply.h"
#include "../core/arithmetic/MultiplyDim.h"
#include "../core/math/Unary.h"
#include "../core/math/ScaleAndShift.h"
#include "../core/reduce/ReduceSum.h"
#include "../core/reduce/ReduceSumAll.h"
#include "../core/shape/Transpose.h"
#include "../core/shape/Unsqueeze.h"
#include "../core/shape/IsSameShaped.h"
namespace nts{ // namespace nts(NiuTrans.Tensor)
/*
compute the cross entropy loss (cuda version)
loss = sum_{i} (-gold_i * log(output_i))
where gold and output are distributions
>> output - model prediction
>> gold - gold standard
>> loss - compute loss
>> weight - a rescaling weight given to each class
>> padding - specify a target value that is ignored and does not contribute to the loss computation
>> leadingDim - the leading dimension for the output
*/
void _CudaCrossEntropyFast(const XTensor * output, const XTensor * gold,
XTensor * loss, const XTensor * weight,
const XTensor * padding, int leadingDim)
{
int n = leadingDim < 0 ? output->order - 1 : leadingDim;
if (output->mem != NULL) {
output->mem->LockBuf();
}
XTensor * interBuf1 = NewTensorBufV2(output, output->devID, output->mem);
XTensor * interBuf2 = NewTensorBufV2(output, output->devID, output->mem);
_Log(output, interBuf1);
_Multiply(gold, interBuf1, interBuf2);
if(weight != NULL)
_MultiplyDimMe(interBuf2, weight, n);
_NegateMe(interBuf2);
_ReduceSum(interBuf2, loss, n);
if(padding != NULL)
_MultiplyMe(loss, padding);
DelTensorBuf(interBuf2);
DelTensorBuf(interBuf1);
if (output->mem != NULL) {
output->mem->UnlockBuf();
}
}
/*
compute the cross entropy loss (scalar version)
loss = sum_{i} (-gold_i * log(output_i))
where gold and output are distributions
>> output - model prediction
>> gold - gold standard
>> reduceWay - loss compute way, sum or mean
>> weight - a rescaling weight given to each class
>> padding - specify a target value that is ignored and does not contribute to the loss computation
>> leadingDim - the leading dimension for the output
<< return - the cross entropy loss that is a scalar
*/
DTYPE _CudaCrossEntropyFast(const XTensor * output, const XTensor * gold,
LOSS_COMPUTE_WAY reduceWay, const XTensor * weight,
const XTensor * padding, int leadingDim)
{
DTYPE loss = 0;
int order = output->order;
int n = leadingDim < 0 ? output->order - 1 : leadingDim;
int leadingDimSize = output->GetDim(n);
CheckNTErrors(n >= 0 && n < output->order,
"Wrong leadingDim!");
CheckNTErrors(_IsSameShaped(output, gold),
"The output tensor and gold tensor must be of the same size!");
CheckNTErrors(weight == NULL || weight->unitNum == leadingDimSize,
"Wrong weight tensor!");
CheckNTErrors(padding == NULL || padding->order == output->order - 1,
"Wrong padding tensor!");
CheckNTErrors(gold->dataType == DEFAULT_DTYPE && output->dataType == DEFAULT_DTYPE,
"TODO!");
int * dimSize = new int[output->order - 1];
for (int i = 0; i < order; i++) {
if(i < n)
dimSize[i] = output->dimSize[i];
else if(i > n)
dimSize[i - 1] = output->dimSize[i];
}
if (output->mem != NULL) {
output->mem->LockBuf();
}
XTensor * lossBuf = NewTensorBufV2(output->order - 1, dimSize, output->dataType, output->denseRatio,
output->devID, output->mem);
_CudaCrossEntropyFast(output, gold, lossBuf, weight, padding, leadingDim);
_ReduceSumAll(lossBuf, &loss);
if(reduceWay == REDUCE_MEAN) {
DTYPE nonZeroNum;
if(padding == NULL) {
nonZeroNum = (DTYPE)lossBuf->unitNum;
}
else {
if ((padding->mem != NULL) && (padding->mem != output->mem)) {
padding->mem->LockBuf();
}
XTensor * tmp = NewTensorBufV2(padding, padding->devID, padding->mem);
_IsNonZero(padding, tmp);
_ReduceSumAll(tmp, &nonZeroNum);
DelTensorBuf(tmp);
if ((padding->mem != NULL) && (padding->mem != output->mem)) {
padding->mem->UnlockBuf();
}
}
loss = loss / nonZeroNum;
}
else if(reduceWay == REDUCE_SUM) {
/* don't need to do anything */
}
else {
ShowNTErrors("TODO");
}
delete[] dimSize;
DelTensorBuf(lossBuf);
if (output->mem != NULL) {
output->mem->UnlockBuf();
}
return loss;
}
/*
backward computation of cross entropy function
loss = sum_{i} (-t_i * log(y_i))
dE/dy_i = -t_i / y_i
where E is the error(loss) function that measure the errors in y
with respect to gold standard, and y this the model output
>> dedy - dE/dy (for return)
>> output - model prediction
>> gold - gold standard
>> weight - a rescaling weight given to each class
>> padding - specify a target value that is ignored and does not contribute to the loss computation
>> leadingDim - the leading dimension for the output
*/
void _CudaCrossEntropyBackward(XTensor * dedy, const XTensor * output,
const XTensor * gold, const XTensor * weight,
XTensor * padding, int leadingDim)
{
int n = leadingDim < 0 ? output->order - 1 : leadingDim;
_Div(gold, output, dedy);
_NegateMe(dedy);
if(weight != NULL)
_MultiplyDimMe(dedy, weight, n);
if(padding != NULL) {
int paddingOrder = padding->order;
int * paddingDims = new int[paddingOrder];
memcpy(paddingDims, padding->dimSize, padding->order * sizeof(int));
padding->Reshape(padding->unitNum);
int order = dedy->order;
int * dims = new int[order];
memcpy(dims, dedy->dimSize, dedy->order * sizeof(int));
dedy->Reshape(dedy->unitNum/dedy->GetDim(n), dedy->GetDim(n));
_MultiplyDimMe(dedy, padding, 0);
padding->Reshape(paddingOrder, paddingDims);
dedy->Reshape(order, dims);
delete[] paddingDims;
delete[] dims;
}
if(padding != NULL) {
XTensor * tmp = NewTensor(padding);
_IsNonZero(padding, tmp);
DTYPE nonZeroNum;
_ReduceSumAll(tmp, &nonZeroNum);
_ScaleAndShiftMe(dedy, (DTYPE)1.0/nonZeroNum);
delete tmp;
}
else {
int num = dedy->unitNum / dedy->GetDim(n);
_ScaleAndShiftMe(dedy, (DTYPE)1.0/(DTYPE)num);
}
}
} // namespace nts(NiuTrans.Tensor)
#endif // __CROSSENTROPY_CUH__ | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* NiuTrans.Tensor - an open-source tensor library
* Copyright (C) 2017, Natural Language Processing Lab, Northeastern University.
* All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* $Created by: Xu Chen (email: hello_master1954@163.com) 2018-09-17
*/
#ifndef __CROSSENTROPY_CUH__
#define __CROSSENTROPY_CUH__
#include "../XTensor.h"
#include "../XDevice.h"
#include "CrossEntropy.cuh"
#include "CrossEntropy.h"
#include "../core/arithmetic/Div.h"
#include "../core/arithmetic/Multiply.h"
#include "../core/arithmetic/MultiplyDim.h"
#include "../core/math/Unary.h"
#include "../core/math/ScaleAndShift.h"
#include "../core/reduce/ReduceSum.h"
#include "../core/reduce/ReduceSumAll.h"
#include "../core/shape/Transpose.h"
#include "../core/shape/Unsqueeze.h"
#include "../core/shape/IsSameShaped.h"
namespace nts{ // namespace nts(NiuTrans.Tensor)
/*
compute the cross entropy loss (cuda version)
loss = sum_{i} (-gold_i * log(output_i))
where gold and output are distributions
>> output - model prediction
>> gold - gold standard
>> loss - compute loss
>> weight - a rescaling weight given to each class
>> padding - specify a target value that is ignored and does not contribute to the loss computation
>> leadingDim - the leading dimension for the output
*/
void _CudaCrossEntropyFast(const XTensor * output, const XTensor * gold,
XTensor * loss, const XTensor * weight,
const XTensor * padding, int leadingDim)
{
int n = leadingDim < 0 ? output->order - 1 : leadingDim;
if (output->mem != NULL) {
output->mem->LockBuf();
}
XTensor * interBuf1 = NewTensorBufV2(output, output->devID, output->mem);
XTensor * interBuf2 = NewTensorBufV2(output, output->devID, output->mem);
_Log(output, interBuf1);
_Multiply(gold, interBuf1, interBuf2);
if(weight != NULL)
_MultiplyDimMe(interBuf2, weight, n);
_NegateMe(interBuf2);
_ReduceSum(interBuf2, loss, n);
if(padding != NULL)
_MultiplyMe(loss, padding);
DelTensorBuf(interBuf2);
DelTensorBuf(interBuf1);
if (output->mem != NULL) {
output->mem->UnlockBuf();
}
}
/*
compute the cross entropy loss (scalar version)
loss = sum_{i} (-gold_i * log(output_i))
where gold and output are distributions
>> output - model prediction
>> gold - gold standard
>> reduceWay - loss compute way, sum or mean
>> weight - a rescaling weight given to each class
>> padding - specify a target value that is ignored and does not contribute to the loss computation
>> leadingDim - the leading dimension for the output
<< return - the cross entropy loss that is a scalar
*/
DTYPE _CudaCrossEntropyFast(const XTensor * output, const XTensor * gold,
LOSS_COMPUTE_WAY reduceWay, const XTensor * weight,
const XTensor * padding, int leadingDim)
{
DTYPE loss = 0;
int order = output->order;
int n = leadingDim < 0 ? output->order - 1 : leadingDim;
int leadingDimSize = output->GetDim(n);
CheckNTErrors(n >= 0 && n < output->order,
"Wrong leadingDim!");
CheckNTErrors(_IsSameShaped(output, gold),
"The output tensor and gold tensor must be of the same size!");
CheckNTErrors(weight == NULL || weight->unitNum == leadingDimSize,
"Wrong weight tensor!");
CheckNTErrors(padding == NULL || padding->order == output->order - 1,
"Wrong padding tensor!");
CheckNTErrors(gold->dataType == DEFAULT_DTYPE && output->dataType == DEFAULT_DTYPE,
"TODO!");
int * dimSize = new int[output->order - 1];
for (int i = 0; i < order; i++) {
if(i < n)
dimSize[i] = output->dimSize[i];
else if(i > n)
dimSize[i - 1] = output->dimSize[i];
}
if (output->mem != NULL) {
output->mem->LockBuf();
}
XTensor * lossBuf = NewTensorBufV2(output->order - 1, dimSize, output->dataType, output->denseRatio,
output->devID, output->mem);
_CudaCrossEntropyFast(output, gold, lossBuf, weight, padding, leadingDim);
_ReduceSumAll(lossBuf, &loss);
if(reduceWay == REDUCE_MEAN) {
DTYPE nonZeroNum;
if(padding == NULL) {
nonZeroNum = (DTYPE)lossBuf->unitNum;
}
else {
if ((padding->mem != NULL) && (padding->mem != output->mem)) {
padding->mem->LockBuf();
}
XTensor * tmp = NewTensorBufV2(padding, padding->devID, padding->mem);
_IsNonZero(padding, tmp);
_ReduceSumAll(tmp, &nonZeroNum);
DelTensorBuf(tmp);
if ((padding->mem != NULL) && (padding->mem != output->mem)) {
padding->mem->UnlockBuf();
}
}
loss = loss / nonZeroNum;
}
else if(reduceWay == REDUCE_SUM) {
/* don't need to do anything */
}
else {
ShowNTErrors("TODO");
}
delete[] dimSize;
DelTensorBuf(lossBuf);
if (output->mem != NULL) {
output->mem->UnlockBuf();
}
return loss;
}
/*
backward computation of cross entropy function
loss = sum_{i} (-t_i * log(y_i))
dE/dy_i = -t_i / y_i
where E is the error(loss) function that measure the errors in y
with respect to gold standard, and y this the model output
>> dedy - dE/dy (for return)
>> output - model prediction
>> gold - gold standard
>> weight - a rescaling weight given to each class
>> padding - specify a target value that is ignored and does not contribute to the loss computation
>> leadingDim - the leading dimension for the output
*/
void _CudaCrossEntropyBackward(XTensor * dedy, const XTensor * output,
const XTensor * gold, const XTensor * weight,
XTensor * padding, int leadingDim)
{
int n = leadingDim < 0 ? output->order - 1 : leadingDim;
_Div(gold, output, dedy);
_NegateMe(dedy);
if(weight != NULL)
_MultiplyDimMe(dedy, weight, n);
if(padding != NULL) {
int paddingOrder = padding->order;
int * paddingDims = new int[paddingOrder];
memcpy(paddingDims, padding->dimSize, padding->order * sizeof(int));
padding->Reshape(padding->unitNum);
int order = dedy->order;
int * dims = new int[order];
memcpy(dims, dedy->dimSize, dedy->order * sizeof(int));
dedy->Reshape(dedy->unitNum/dedy->GetDim(n), dedy->GetDim(n));
_MultiplyDimMe(dedy, padding, 0);
padding->Reshape(paddingOrder, paddingDims);
dedy->Reshape(order, dims);
delete[] paddingDims;
delete[] dims;
}
if(padding != NULL) {
XTensor * tmp = NewTensor(padding);
_IsNonZero(padding, tmp);
DTYPE nonZeroNum;
_ReduceSumAll(tmp, &nonZeroNum);
_ScaleAndShiftMe(dedy, (DTYPE)1.0/nonZeroNum);
delete tmp;
}
else {
int num = dedy->unitNum / dedy->GetDim(n);
_ScaleAndShiftMe(dedy, (DTYPE)1.0/(DTYPE)num);
}
}
} // namespace nts(NiuTrans.Tensor)
#endif // __CROSSENTROPY_CUH__ | .file "tmpxft_00155c56_00000000-6_CrossEntropy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3097:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_PS0_S2_S2_i
.type _ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_PS0_S2_S2_i, @function
_ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_PS0_S2_S2_i:
.LFB3092:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbx
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movq %rcx, %r15
movq %r8, %r14
movl %r9d, %r12d
testl %r9d, %r9d
js .L10
.L4:
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .L5
call _ZN3nts4XMem7LockBufEv@PLT
.L5:
movq 40(%rbx), %rdx
movl 72(%rbx), %esi
movq %rbx, %rdi
call _ZN3nts14NewTensorBufV2EPKNS_7XTensorEiPNS_4XMemE@PLT
movq %rax, %r13
movq 40(%rbx), %rdx
movl 72(%rbx), %esi
movq %rbx, %rdi
call _ZN3nts14NewTensorBufV2EPKNS_7XTensorEiPNS_4XMemE@PLT
movq %rax, %rbp
movq %r13, %rsi
movq %rbx, %rdi
call _ZN3nts4_LogEPKNS_7XTensorEPS0_@PLT
movl $0, %ecx
pxor %xmm0, %xmm0
movq %rbp, %rdx
movq %r13, %rsi
movq (%rsp), %rdi
call _ZN3nts9_MultiplyEPKNS_7XTensorES2_PS0_fi@PLT
testq %r15, %r15
je .L6
pxor %xmm0, %xmm0
movl %r12d, %edx
movq %r15, %rsi
movq %rbp, %rdi
call _ZN3nts14_MultiplyDimMeEPNS_7XTensorEPKS0_if@PLT
.L6:
movq %rbp, %rdi
call _ZN3nts9_NegateMeEPNS_7XTensorE@PLT
movl $0, %r8d
movss .LC1(%rip), %xmm0
movl $0, %ecx
movl %r12d, %edx
movq 8(%rsp), %r15
movq %r15, %rsi
movq %rbp, %rdi
call _ZN3nts10_ReduceSumEPKNS_7XTensorEPS0_iS2_fb@PLT
testq %r14, %r14
je .L7
movl $0, %edx
pxor %xmm0, %xmm0
movq %r14, %rsi
movq %r15, %rdi
call _ZN3nts11_MultiplyMeEPNS_7XTensorEPKS0_fi@PLT
.L7:
movq %rbp, %rdi
call _ZN3nts12DelTensorBufEPNS_7XTensorE@PLT
movq %r13, %rdi
call _ZN3nts12DelTensorBufEPNS_7XTensorE@PLT
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .L3
call _ZN3nts4XMem9UnlockBufEv@PLT
.L3:
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl 76(%rdi), %eax
leal -1(%rax), %r12d
jmp .L4
.cfi_endproc
.LFE3092:
.size _ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_PS0_S2_S2_i, .-_ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_PS0_S2_S2_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/NiuTrans/NiuTensor/master/source/tensor/loss/CrossEntropy.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "n >= 0 && n < output->order"
.section .rodata.str1.8
.align 8
.LC4:
.string "[ERROR] calling '%s' (%s line %d): %s\n"
.section .rodata.str1.1
.LC5:
.string "Wrong leadingDim!"
.LC6:
.string "_IsSameShaped(output, gold)"
.section .rodata.str1.8
.align 8
.LC7:
.string "The output tensor and gold tensor must be of the same size!"
.align 8
.LC8:
.string "weight == NULL || weight->unitNum == leadingDimSize"
.section .rodata.str1.1
.LC9:
.string "Wrong weight tensor!"
.section .rodata.str1.8
.align 8
.LC10:
.string "padding == NULL || padding->order == output->order - 1"
.section .rodata.str1.1
.LC11:
.string "Wrong padding tensor!"
.section .rodata.str1.8
.align 8
.LC12:
.string "gold->dataType == DEFAULT_DTYPE && output->dataType == DEFAULT_DTYPE"
.section .rodata.str1.1
.LC13:
.string "TODO!"
.LC14:
.string "TODO"
.LC15:
.string "[ERROR] (%s line %d): %s\n"
.text
.globl _ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_NS_16LOSS_COMPUTE_WAYES2_S2_i
.type _ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_NS_16LOSS_COMPUTE_WAYES2_S2_i, @function
_ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_NS_16LOSS_COMPUTE_WAYES2_S2_i:
.LFB3093:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbx
movq %rsi, (%rsp)
movl %edx, 8(%rsp)
movq %rcx, %r14
movq %r8, %r13
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $0x00000000, 16(%rsp)
movl 76(%rdi), %r15d
testl %r9d, %r9d
js .L46
movl 12(%rsp), %ebp
movl %ebp, %esi
call _ZNK3nts7XTensor6GetDimEi@PLT
movl %eax, %r12d
.L40:
cmpl %ebp, 76(%rbx)
jle .L13
movq (%rsp), %rsi
movq %rbx, %rdi
call _ZN3nts13_IsSameShapedEPKNS_7XTensorES2_@PLT
testb %al, %al
je .L47
testq %r14, %r14
je .L18
cmpl %r12d, 120(%r14)
jne .L48
.L18:
testq %r13, %r13
je .L20
movl 76(%rbx), %eax
subl $1, %eax
cmpl %eax, 76(%r13)
jne .L49
.L20:
movq (%rsp), %rax
cmpl $2, 112(%rax)
jne .L22
cmpl $2, 112(%rbx)
jne .L22
movl 76(%rbx), %eax
leal -1(%rax), %edi
movslq %edi, %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L25
salq $2, %rdi
call _Znam@PLT
movq %rax, %r12
movslq %r15d, %rdx
movl $0, %eax
testl %r15d, %r15d
jg .L31
.L27:
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .L32
call _ZN3nts4XMem7LockBufEv@PLT
.L32:
movl 72(%rbx), %ecx
movss 132(%rbx), %xmm0
movl 112(%rbx), %edx
movl 76(%rbx), %eax
leal -1(%rax), %edi
movq 40(%rbx), %r8
movq %r12, %rsi
call _ZN3nts14NewTensorBufV2EiPKiNS_16TENSOR_DATA_TYPEEfiPNS_4XMemE@PLT
movq %rax, %rbp
movl 12(%rsp), %r9d
movq %r13, %r8
movq %r14, %rcx
movq %rax, %rdx
movq (%rsp), %rsi
movq %rbx, %rdi
call _ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_PS0_S2_S2_i
leaq 16(%rsp), %rsi
movq %rbp, %rdi
call _ZN3nts13_ReduceSumAllEPKNS_7XTensorEPf@PLT
cmpl $1, 8(%rsp)
je .L50
cmpl $0, 8(%rsp)
jne .L51
.L37:
movq %r12, %rdi
call _ZdaPv@PLT
movq %rbp, %rdi
call _ZN3nts12DelTensorBufEPNS_7XTensorE@PLT
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .L39
call _ZN3nts4XMem9UnlockBufEv@PLT
.L39:
movss 16(%rsp), %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L52
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
leal -1(%r15), %ebp
movl %ebp, %esi
call _ZNK3nts7XTensor6GetDimEi@PLT
movl %eax, %r12d
testl %ebp, %ebp
jns .L40
.L13:
subq $8, %rsp
.cfi_def_cfa_offset 104
leaq .LC5(%rip), %rax
pushq %rax
.cfi_def_cfa_offset 112
movl $108, %r9d
leaq 92+.LC2(%rip), %r8
leaq .LC3(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L53
call __cxa_rethrow@PLT
.L53:
call __stack_chk_fail@PLT
.L47:
subq $8, %rsp
.cfi_def_cfa_offset 104
leaq .LC7(%rip), %rax
pushq %rax
.cfi_def_cfa_offset 112
movl $110, %r9d
leaq 92+.LC2(%rip), %r8
leaq .LC6(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L54
call __cxa_rethrow@PLT
.L54:
call __stack_chk_fail@PLT
.L48:
subq $8, %rsp
.cfi_def_cfa_offset 104
leaq .LC9(%rip), %rax
pushq %rax
.cfi_def_cfa_offset 112
movl $112, %r9d
leaq 92+.LC2(%rip), %r8
leaq .LC8(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L55
call __cxa_rethrow@PLT
.L55:
call __stack_chk_fail@PLT
.L49:
subq $8, %rsp
.cfi_def_cfa_offset 104
leaq .LC11(%rip), %rax
pushq %rax
.cfi_def_cfa_offset 112
movl $114, %r9d
leaq 92+.LC2(%rip), %r8
leaq .LC10(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L56
call __cxa_rethrow@PLT
.L56:
call __stack_chk_fail@PLT
.L22:
subq $8, %rsp
.cfi_def_cfa_offset 104
leaq .LC13(%rip), %rax
pushq %rax
.cfi_def_cfa_offset 112
movl $116, %r9d
leaq 92+.LC2(%rip), %r8
leaq .LC12(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L57
call __cxa_rethrow@PLT
.L57:
call __stack_chk_fail@PLT
.L25:
movq 24(%rsp), %rax
subq %fs:40, %rax
je .L28
call __stack_chk_fail@PLT
.L28:
call __cxa_throw_bad_array_new_length@PLT
.L29:
jge .L30
movl 80(%rbx,%rax,4), %ecx
movl %ecx, -4(%r12,%rax,4)
.L30:
addq $1, %rax
cmpq %rdx, %rax
je .L27
.L31:
cmpl %eax, %ebp
jle .L29
movl 80(%rbx,%rax,4), %ecx
movl %ecx, (%r12,%rax,4)
jmp .L30
.L50:
testq %r13, %r13
je .L58
movq 40(%r13), %rdi
testq %rdi, %rdi
je .L36
cmpq 40(%rbx), %rdi
je .L36
call _ZN3nts4XMem7LockBufEv@PLT
.L36:
movq 40(%r13), %rdx
movl 72(%r13), %esi
movq %r13, %rdi
call _ZN3nts14NewTensorBufV2EPKNS_7XTensorEiPNS_4XMemE@PLT
movq %rax, %r14
movq %rax, %rsi
movq %r13, %rdi
call _ZN3nts10_IsNonZeroEPKNS_7XTensorEPS0_@PLT
leaq 20(%rsp), %rsi
movq %r14, %rdi
call _ZN3nts13_ReduceSumAllEPKNS_7XTensorEPf@PLT
movq %r14, %rdi
call _ZN3nts12DelTensorBufEPNS_7XTensorE@PLT
movq 40(%r13), %rdi
testq %rdi, %rdi
je .L35
cmpq 40(%rbx), %rdi
je .L35
call _ZN3nts4XMem9UnlockBufEv@PLT
jmp .L35
.L58:
pxor %xmm0, %xmm0
cvtsi2ssl 120(%rbp), %xmm0
movss %xmm0, 20(%rsp)
.L35:
movss 16(%rsp), %xmm0
divss 20(%rsp), %xmm0
movss %xmm0, 16(%rsp)
jmp .L37
.L51:
leaq .LC14(%rip), %r9
movl $161, %r8d
leaq 92+.LC2(%rip), %rcx
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L59
call __cxa_rethrow@PLT
.L59:
call __stack_chk_fail@PLT
.L52:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3093:
.size _ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_NS_16LOSS_COMPUTE_WAYES2_S2_i, .-_ZN3nts21_CudaCrossEntropyFastEPKNS_7XTensorES2_NS_16LOSS_COMPUTE_WAYES2_S2_i
.globl _ZN3nts25_CudaCrossEntropyBackwardEPNS_7XTensorEPKS0_S3_S3_S1_i
.type _ZN3nts25_CudaCrossEntropyBackwardEPNS_7XTensorEPKS0_S3_S3_S1_i, @function
_ZN3nts25_CudaCrossEntropyBackwardEPNS_7XTensorEPKS0_S3_S3_S1_i:
.LFB3094:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %rbx
movq %rdx, %rdi
movq %rcx, %r13
movq %r8, %rbp
movl %r9d, %r12d
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
testl %r9d, %r9d
js .L75
.L61:
movl $0, %ecx
pxor %xmm0, %xmm0
movq %rbx, %rdx
call _ZN3nts4_DivEPKNS_7XTensorES2_PS0_fi@PLT
movq %rbx, %rdi
call _ZN3nts9_NegateMeEPNS_7XTensorE@PLT
testq %r13, %r13
je .L62
pxor %xmm0, %xmm0
movl %r12d, %edx
movq %r13, %rsi
movq %rbx, %rdi
call _ZN3nts14_MultiplyDimMeEPNS_7XTensorEPKS0_if@PLT
.L62:
testq %rbp, %rbp
je .L76
movl 76(%rbp), %r15d
movslq %r15d, %r13
movabsq $2305843009213693950, %rax
cmpq %r13, %rax
jb .L65
salq $2, %r13
movq %r13, %rdi
call _Znam@PLT
movq %rax, 8(%rsp)
movslq 76(%rbp), %rdx
salq $2, %rdx
leaq 80(%rbp), %rsi
movq %r13, %rcx
movq %rax, %rdi
call __memcpy_chk@PLT
movl 120(%rbp), %esi
movq %rbp, %rdi
call _ZN3nts7XTensor7ReshapeEi@PLT
movl 76(%rbx), %r14d
movslq %r14d, %r13
movabsq $2305843009213693950, %rax
cmpq %r13, %rax
jb .L77
salq $2, %r13
movq %r13, %rdi
call _Znam@PLT
movslq 76(%rbx), %rdx
salq $2, %rdx
leaq 80(%rbx), %rsi
movq %r13, %rcx
movq %rax, 24(%rsp)
movq %rax, %rdi
call __memcpy_chk@PLT
movl %r12d, %esi
movq %rbx, %rdi
call _ZNK3nts7XTensor6GetDimEi@PLT
movl %eax, 20(%rsp)
movl 120(%rbx), %r13d
movl %r12d, %esi
movq %rbx, %rdi
call _ZNK3nts7XTensor6GetDimEi@PLT
movl %eax, %ecx
movl %r13d, %eax
cltd
idivl %ecx
movl %eax, %esi
movl 20(%rsp), %edx
movq %rbx, %rdi
call _ZN3nts7XTensor7ReshapeEii@PLT
pxor %xmm0, %xmm0
movl $0, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call _ZN3nts14_MultiplyDimMeEPNS_7XTensorEPKS0_if@PLT
movq 8(%rsp), %r12
movq %r12, %rdx
movl %r15d, %esi
movq %rbp, %rdi
call _ZN3nts7XTensor7ReshapeEiPKi@PLT
movq 24(%rsp), %r15
movq %r15, %rdx
movl %r14d, %esi
movq %rbx, %rdi
call _ZN3nts7XTensor7ReshapeEiPKi@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq %r15, %rdi
call _ZdaPv@PLT
movl $1, %esi
movq %rbp, %rdi
call _ZN3nts9NewTensorEPKNS_7XTensorEb@PLT
movq %rax, %r12
movq %rax, %rsi
movq %rbp, %rdi
call _ZN3nts10_IsNonZeroEPKNS_7XTensorEPS0_@PLT
leaq 36(%rsp), %rsi
movq %r12, %rdi
call _ZN3nts13_ReduceSumAllEPKNS_7XTensorEPf@PLT
movss .LC1(%rip), %xmm0
divss 36(%rsp), %xmm0
pxor %xmm1, %xmm1
movq %rbx, %rdi
call _ZN3nts16_ScaleAndShiftMeEPNS_7XTensorEff@PLT
testq %r12, %r12
je .L60
movq %r12, %rdi
call _ZN3nts7XTensorD1Ev@PLT
movl $400, %esi
movq %r12, %rdi
call _ZdlPvm@PLT
.L60:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L78
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L75:
.cfi_restore_state
movl 76(%rsi), %eax
leal -1(%rax), %r12d
jmp .L61
.L76:
movl 120(%rbx), %ebp
movl %r12d, %esi
movq %rbx, %rdi
call _ZNK3nts7XTensor6GetDimEi@PLT
movl %eax, %ecx
movl %ebp, %eax
cltd
idivl %ecx
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
movss .LC1(%rip), %xmm0
divss %xmm1, %xmm0
pxor %xmm1, %xmm1
movq %rbx, %rdi
call _ZN3nts16_ScaleAndShiftMeEPNS_7XTensorEff@PLT
jmp .L60
.L65:
movq 40(%rsp), %rax
subq %fs:40, %rax
je .L68
call __stack_chk_fail@PLT
.L68:
call __cxa_throw_bad_array_new_length@PLT
.L77:
movq 40(%rsp), %rax
subq %fs:40, %rax
je .L71
call __stack_chk_fail@PLT
.L71:
call __cxa_throw_bad_array_new_length@PLT
.L78:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3094:
.size _ZN3nts25_CudaCrossEntropyBackwardEPNS_7XTensorEPKS0_S3_S3_S1_i, .-_ZN3nts25_CudaCrossEntropyBackwardEPNS_7XTensorEPKS0_S3_S3_S1_i
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3120:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3120:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* NiuTrans.Tensor - an open-source tensor library
* Copyright (C) 2017, Natural Language Processing Lab, Northeastern University.
* All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* $Created by: Xu Chen (email: hello_master1954@163.com) 2018-09-17
*/
#ifndef __CROSSENTROPY_CUH__
#define __CROSSENTROPY_CUH__
#include "../XTensor.h"
#include "../XDevice.h"
#include "CrossEntropy.cuh"
#include "CrossEntropy.h"
#include "../core/arithmetic/Div.h"
#include "../core/arithmetic/Multiply.h"
#include "../core/arithmetic/MultiplyDim.h"
#include "../core/math/Unary.h"
#include "../core/math/ScaleAndShift.h"
#include "../core/reduce/ReduceSum.h"
#include "../core/reduce/ReduceSumAll.h"
#include "../core/shape/Transpose.h"
#include "../core/shape/Unsqueeze.h"
#include "../core/shape/IsSameShaped.h"
namespace nts{ // namespace nts(NiuTrans.Tensor)
/*
compute the cross entropy loss (cuda version)
loss = sum_{i} (-gold_i * log(output_i))
where gold and output are distributions
>> output - model prediction
>> gold - gold standard
>> loss - compute loss
>> weight - a rescaling weight given to each class
>> padding - specify a target value that is ignored and does not contribute to the loss computation
>> leadingDim - the leading dimension for the output
*/
void _CudaCrossEntropyFast(const XTensor * output, const XTensor * gold,
XTensor * loss, const XTensor * weight,
const XTensor * padding, int leadingDim)
{
int n = leadingDim < 0 ? output->order - 1 : leadingDim;
if (output->mem != NULL) {
output->mem->LockBuf();
}
XTensor * interBuf1 = NewTensorBufV2(output, output->devID, output->mem);
XTensor * interBuf2 = NewTensorBufV2(output, output->devID, output->mem);
_Log(output, interBuf1);
_Multiply(gold, interBuf1, interBuf2);
if(weight != NULL)
_MultiplyDimMe(interBuf2, weight, n);
_NegateMe(interBuf2);
_ReduceSum(interBuf2, loss, n);
if(padding != NULL)
_MultiplyMe(loss, padding);
DelTensorBuf(interBuf2);
DelTensorBuf(interBuf1);
if (output->mem != NULL) {
output->mem->UnlockBuf();
}
}
/*
compute the cross entropy loss (scalar version)
loss = sum_{i} (-gold_i * log(output_i))
where gold and output are distributions
>> output - model prediction
>> gold - gold standard
>> reduceWay - loss compute way, sum or mean
>> weight - a rescaling weight given to each class
>> padding - specify a target value that is ignored and does not contribute to the loss computation
>> leadingDim - the leading dimension for the output
<< return - the cross entropy loss that is a scalar
*/
DTYPE _CudaCrossEntropyFast(const XTensor * output, const XTensor * gold,
LOSS_COMPUTE_WAY reduceWay, const XTensor * weight,
const XTensor * padding, int leadingDim)
{
DTYPE loss = 0;
int order = output->order;
int n = leadingDim < 0 ? output->order - 1 : leadingDim;
int leadingDimSize = output->GetDim(n);
CheckNTErrors(n >= 0 && n < output->order,
"Wrong leadingDim!");
CheckNTErrors(_IsSameShaped(output, gold),
"The output tensor and gold tensor must be of the same size!");
CheckNTErrors(weight == NULL || weight->unitNum == leadingDimSize,
"Wrong weight tensor!");
CheckNTErrors(padding == NULL || padding->order == output->order - 1,
"Wrong padding tensor!");
CheckNTErrors(gold->dataType == DEFAULT_DTYPE && output->dataType == DEFAULT_DTYPE,
"TODO!");
int * dimSize = new int[output->order - 1];
for (int i = 0; i < order; i++) {
if(i < n)
dimSize[i] = output->dimSize[i];
else if(i > n)
dimSize[i - 1] = output->dimSize[i];
}
if (output->mem != NULL) {
output->mem->LockBuf();
}
XTensor * lossBuf = NewTensorBufV2(output->order - 1, dimSize, output->dataType, output->denseRatio,
output->devID, output->mem);
_CudaCrossEntropyFast(output, gold, lossBuf, weight, padding, leadingDim);
_ReduceSumAll(lossBuf, &loss);
if(reduceWay == REDUCE_MEAN) {
DTYPE nonZeroNum;
if(padding == NULL) {
nonZeroNum = (DTYPE)lossBuf->unitNum;
}
else {
if ((padding->mem != NULL) && (padding->mem != output->mem)) {
padding->mem->LockBuf();
}
XTensor * tmp = NewTensorBufV2(padding, padding->devID, padding->mem);
_IsNonZero(padding, tmp);
_ReduceSumAll(tmp, &nonZeroNum);
DelTensorBuf(tmp);
if ((padding->mem != NULL) && (padding->mem != output->mem)) {
padding->mem->UnlockBuf();
}
}
loss = loss / nonZeroNum;
}
else if(reduceWay == REDUCE_SUM) {
/* don't need to do anything */
}
else {
ShowNTErrors("TODO");
}
delete[] dimSize;
DelTensorBuf(lossBuf);
if (output->mem != NULL) {
output->mem->UnlockBuf();
}
return loss;
}
/*
backward computation of cross entropy function
loss = sum_{i} (-t_i * log(y_i))
dE/dy_i = -t_i / y_i
where E is the error(loss) function that measure the errors in y
with respect to gold standard, and y this the model output
>> dedy - dE/dy (for return)
>> output - model prediction
>> gold - gold standard
>> weight - a rescaling weight given to each class
>> padding - specify a target value that is ignored and does not contribute to the loss computation
>> leadingDim - the leading dimension for the output
*/
void _CudaCrossEntropyBackward(XTensor * dedy, const XTensor * output,
const XTensor * gold, const XTensor * weight,
XTensor * padding, int leadingDim)
{
int n = leadingDim < 0 ? output->order - 1 : leadingDim;
_Div(gold, output, dedy);
_NegateMe(dedy);
if(weight != NULL)
_MultiplyDimMe(dedy, weight, n);
if(padding != NULL) {
int paddingOrder = padding->order;
int * paddingDims = new int[paddingOrder];
memcpy(paddingDims, padding->dimSize, padding->order * sizeof(int));
padding->Reshape(padding->unitNum);
int order = dedy->order;
int * dims = new int[order];
memcpy(dims, dedy->dimSize, dedy->order * sizeof(int));
dedy->Reshape(dedy->unitNum/dedy->GetDim(n), dedy->GetDim(n));
_MultiplyDimMe(dedy, padding, 0);
padding->Reshape(paddingOrder, paddingDims);
dedy->Reshape(order, dims);
delete[] paddingDims;
delete[] dims;
}
if(padding != NULL) {
XTensor * tmp = NewTensor(padding);
_IsNonZero(padding, tmp);
DTYPE nonZeroNum;
_ReduceSumAll(tmp, &nonZeroNum);
_ScaleAndShiftMe(dedy, (DTYPE)1.0/nonZeroNum);
delete tmp;
}
else {
int num = dedy->unitNum / dedy->GetDim(n);
_ScaleAndShiftMe(dedy, (DTYPE)1.0/(DTYPE)num);
}
}
} // namespace nts(NiuTrans.Tensor)
#endif // __CROSSENTROPY_CUH__ | /* NiuTrans.Tensor - an open-source tensor library
* Copyright (C) 2017, Natural Language Processing Lab, Northeastern University.
* All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* $Created by: Xu Chen (email: hello_master1954@163.com) 2018-09-17
*/
#ifndef __CROSSENTROPY_CUH__
#define __CROSSENTROPY_CUH__
#include "../XTensor.h"
#include "../XDevice.h"
#include "CrossEntropy.cuh"
#include "CrossEntropy.h"
#include "../core/arithmetic/Div.h"
#include "../core/arithmetic/Multiply.h"
#include "../core/arithmetic/MultiplyDim.h"
#include "../core/math/Unary.h"
#include "../core/math/ScaleAndShift.h"
#include "../core/reduce/ReduceSum.h"
#include "../core/reduce/ReduceSumAll.h"
#include "../core/shape/Transpose.h"
#include "../core/shape/Unsqueeze.h"
#include "../core/shape/IsSameShaped.h"
namespace nts{ // namespace nts(NiuTrans.Tensor)
/*
compute the cross entropy loss (cuda version)
loss = sum_{i} (-gold_i * log(output_i))
where gold and output are distributions
>> output - model prediction
>> gold - gold standard
>> loss - compute loss
>> weight - a rescaling weight given to each class
>> padding - specify a target value that is ignored and does not contribute to the loss computation
>> leadingDim - the leading dimension for the output
*/
void _CudaCrossEntropyFast(const XTensor * output, const XTensor * gold,
XTensor * loss, const XTensor * weight,
const XTensor * padding, int leadingDim)
{
int n = leadingDim < 0 ? output->order - 1 : leadingDim;
if (output->mem != NULL) {
output->mem->LockBuf();
}
XTensor * interBuf1 = NewTensorBufV2(output, output->devID, output->mem);
XTensor * interBuf2 = NewTensorBufV2(output, output->devID, output->mem);
_Log(output, interBuf1);
_Multiply(gold, interBuf1, interBuf2);
if(weight != NULL)
_MultiplyDimMe(interBuf2, weight, n);
_NegateMe(interBuf2);
_ReduceSum(interBuf2, loss, n);
if(padding != NULL)
_MultiplyMe(loss, padding);
DelTensorBuf(interBuf2);
DelTensorBuf(interBuf1);
if (output->mem != NULL) {
output->mem->UnlockBuf();
}
}
/*
compute the cross entropy loss (scalar version)
loss = sum_{i} (-gold_i * log(output_i))
where gold and output are distributions
>> output - model prediction
>> gold - gold standard
>> reduceWay - loss compute way, sum or mean
>> weight - a rescaling weight given to each class
>> padding - specify a target value that is ignored and does not contribute to the loss computation
>> leadingDim - the leading dimension for the output
<< return - the cross entropy loss that is a scalar
*/
DTYPE _CudaCrossEntropyFast(const XTensor * output, const XTensor * gold,
LOSS_COMPUTE_WAY reduceWay, const XTensor * weight,
const XTensor * padding, int leadingDim)
{
DTYPE loss = 0;
int order = output->order;
int n = leadingDim < 0 ? output->order - 1 : leadingDim;
int leadingDimSize = output->GetDim(n);
CheckNTErrors(n >= 0 && n < output->order,
"Wrong leadingDim!");
CheckNTErrors(_IsSameShaped(output, gold),
"The output tensor and gold tensor must be of the same size!");
CheckNTErrors(weight == NULL || weight->unitNum == leadingDimSize,
"Wrong weight tensor!");
CheckNTErrors(padding == NULL || padding->order == output->order - 1,
"Wrong padding tensor!");
CheckNTErrors(gold->dataType == DEFAULT_DTYPE && output->dataType == DEFAULT_DTYPE,
"TODO!");
int * dimSize = new int[output->order - 1];
for (int i = 0; i < order; i++) {
if(i < n)
dimSize[i] = output->dimSize[i];
else if(i > n)
dimSize[i - 1] = output->dimSize[i];
}
if (output->mem != NULL) {
output->mem->LockBuf();
}
XTensor * lossBuf = NewTensorBufV2(output->order - 1, dimSize, output->dataType, output->denseRatio,
output->devID, output->mem);
_CudaCrossEntropyFast(output, gold, lossBuf, weight, padding, leadingDim);
_ReduceSumAll(lossBuf, &loss);
if(reduceWay == REDUCE_MEAN) {
DTYPE nonZeroNum;
if(padding == NULL) {
nonZeroNum = (DTYPE)lossBuf->unitNum;
}
else {
if ((padding->mem != NULL) && (padding->mem != output->mem)) {
padding->mem->LockBuf();
}
XTensor * tmp = NewTensorBufV2(padding, padding->devID, padding->mem);
_IsNonZero(padding, tmp);
_ReduceSumAll(tmp, &nonZeroNum);
DelTensorBuf(tmp);
if ((padding->mem != NULL) && (padding->mem != output->mem)) {
padding->mem->UnlockBuf();
}
}
loss = loss / nonZeroNum;
}
else if(reduceWay == REDUCE_SUM) {
/* don't need to do anything */
}
else {
ShowNTErrors("TODO");
}
delete[] dimSize;
DelTensorBuf(lossBuf);
if (output->mem != NULL) {
output->mem->UnlockBuf();
}
return loss;
}
/*
backward computation of cross entropy function
loss = sum_{i} (-t_i * log(y_i))
dE/dy_i = -t_i / y_i
where E is the error(loss) function that measure the errors in y
with respect to gold standard, and y this the model output
>> dedy - dE/dy (for return)
>> output - model prediction
>> gold - gold standard
>> weight - a rescaling weight given to each class
>> padding - specify a target value that is ignored and does not contribute to the loss computation
>> leadingDim - the leading dimension for the output
*/
void _CudaCrossEntropyBackward(XTensor * dedy, const XTensor * output,
const XTensor * gold, const XTensor * weight,
XTensor * padding, int leadingDim)
{
int n = leadingDim < 0 ? output->order - 1 : leadingDim;
_Div(gold, output, dedy);
_NegateMe(dedy);
if(weight != NULL)
_MultiplyDimMe(dedy, weight, n);
if(padding != NULL) {
int paddingOrder = padding->order;
int * paddingDims = new int[paddingOrder];
memcpy(paddingDims, padding->dimSize, padding->order * sizeof(int));
padding->Reshape(padding->unitNum);
int order = dedy->order;
int * dims = new int[order];
memcpy(dims, dedy->dimSize, dedy->order * sizeof(int));
dedy->Reshape(dedy->unitNum/dedy->GetDim(n), dedy->GetDim(n));
_MultiplyDimMe(dedy, padding, 0);
padding->Reshape(paddingOrder, paddingDims);
dedy->Reshape(order, dims);
delete[] paddingDims;
delete[] dims;
}
if(padding != NULL) {
XTensor * tmp = NewTensor(padding);
_IsNonZero(padding, tmp);
DTYPE nonZeroNum;
_ReduceSumAll(tmp, &nonZeroNum);
_ScaleAndShiftMe(dedy, (DTYPE)1.0/nonZeroNum);
delete tmp;
}
else {
int num = dedy->unitNum / dedy->GetDim(n);
_ScaleAndShiftMe(dedy, (DTYPE)1.0/(DTYPE)num);
}
}
} // namespace nts(NiuTrans.Tensor)
#endif // __CROSSENTROPY_CUH__ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* NiuTrans.Tensor - an open-source tensor library
* Copyright (C) 2017, Natural Language Processing Lab, Northeastern University.
* All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* $Created by: Xu Chen (email: hello_master1954@163.com) 2018-09-17
*/
#ifndef __CROSSENTROPY_CUH__
#define __CROSSENTROPY_CUH__
#include "../XTensor.h"
#include "../XDevice.h"
#include "CrossEntropy.cuh"
#include "CrossEntropy.h"
#include "../core/arithmetic/Div.h"
#include "../core/arithmetic/Multiply.h"
#include "../core/arithmetic/MultiplyDim.h"
#include "../core/math/Unary.h"
#include "../core/math/ScaleAndShift.h"
#include "../core/reduce/ReduceSum.h"
#include "../core/reduce/ReduceSumAll.h"
#include "../core/shape/Transpose.h"
#include "../core/shape/Unsqueeze.h"
#include "../core/shape/IsSameShaped.h"
namespace nts{ // namespace nts(NiuTrans.Tensor)
/*
compute the cross entropy loss (cuda version)
loss = sum_{i} (-gold_i * log(output_i))
where gold and output are distributions
>> output - model prediction
>> gold - gold standard
>> loss - compute loss
>> weight - a rescaling weight given to each class
>> padding - specify a target value that is ignored and does not contribute to the loss computation
>> leadingDim - the leading dimension for the output
*/
void _CudaCrossEntropyFast(const XTensor * output, const XTensor * gold,
XTensor * loss, const XTensor * weight,
const XTensor * padding, int leadingDim)
{
int n = leadingDim < 0 ? output->order - 1 : leadingDim;
if (output->mem != NULL) {
output->mem->LockBuf();
}
XTensor * interBuf1 = NewTensorBufV2(output, output->devID, output->mem);
XTensor * interBuf2 = NewTensorBufV2(output, output->devID, output->mem);
_Log(output, interBuf1);
_Multiply(gold, interBuf1, interBuf2);
if(weight != NULL)
_MultiplyDimMe(interBuf2, weight, n);
_NegateMe(interBuf2);
_ReduceSum(interBuf2, loss, n);
if(padding != NULL)
_MultiplyMe(loss, padding);
DelTensorBuf(interBuf2);
DelTensorBuf(interBuf1);
if (output->mem != NULL) {
output->mem->UnlockBuf();
}
}
/*
compute the cross entropy loss (scalar version)
loss = sum_{i} (-gold_i * log(output_i))
where gold and output are distributions
>> output - model prediction
>> gold - gold standard
>> reduceWay - loss compute way, sum or mean
>> weight - a rescaling weight given to each class
>> padding - specify a target value that is ignored and does not contribute to the loss computation
>> leadingDim - the leading dimension for the output
<< return - the cross entropy loss that is a scalar
*/
DTYPE _CudaCrossEntropyFast(const XTensor * output, const XTensor * gold,
LOSS_COMPUTE_WAY reduceWay, const XTensor * weight,
const XTensor * padding, int leadingDim)
{
DTYPE loss = 0;
int order = output->order;
int n = leadingDim < 0 ? output->order - 1 : leadingDim;
int leadingDimSize = output->GetDim(n);
CheckNTErrors(n >= 0 && n < output->order,
"Wrong leadingDim!");
CheckNTErrors(_IsSameShaped(output, gold),
"The output tensor and gold tensor must be of the same size!");
CheckNTErrors(weight == NULL || weight->unitNum == leadingDimSize,
"Wrong weight tensor!");
CheckNTErrors(padding == NULL || padding->order == output->order - 1,
"Wrong padding tensor!");
CheckNTErrors(gold->dataType == DEFAULT_DTYPE && output->dataType == DEFAULT_DTYPE,
"TODO!");
int * dimSize = new int[output->order - 1];
for (int i = 0; i < order; i++) {
if(i < n)
dimSize[i] = output->dimSize[i];
else if(i > n)
dimSize[i - 1] = output->dimSize[i];
}
if (output->mem != NULL) {
output->mem->LockBuf();
}
XTensor * lossBuf = NewTensorBufV2(output->order - 1, dimSize, output->dataType, output->denseRatio,
output->devID, output->mem);
_CudaCrossEntropyFast(output, gold, lossBuf, weight, padding, leadingDim);
_ReduceSumAll(lossBuf, &loss);
if(reduceWay == REDUCE_MEAN) {
DTYPE nonZeroNum;
if(padding == NULL) {
nonZeroNum = (DTYPE)lossBuf->unitNum;
}
else {
if ((padding->mem != NULL) && (padding->mem != output->mem)) {
padding->mem->LockBuf();
}
XTensor * tmp = NewTensorBufV2(padding, padding->devID, padding->mem);
_IsNonZero(padding, tmp);
_ReduceSumAll(tmp, &nonZeroNum);
DelTensorBuf(tmp);
if ((padding->mem != NULL) && (padding->mem != output->mem)) {
padding->mem->UnlockBuf();
}
}
loss = loss / nonZeroNum;
}
else if(reduceWay == REDUCE_SUM) {
/* don't need to do anything */
}
else {
ShowNTErrors("TODO");
}
delete[] dimSize;
DelTensorBuf(lossBuf);
if (output->mem != NULL) {
output->mem->UnlockBuf();
}
return loss;
}
/*
backward computation of cross entropy function
loss = sum_{i} (-t_i * log(y_i))
dE/dy_i = -t_i / y_i
where E is the error(loss) function that measure the errors in y
with respect to gold standard, and y this the model output
>> dedy - dE/dy (for return)
>> output - model prediction
>> gold - gold standard
>> weight - a rescaling weight given to each class
>> padding - specify a target value that is ignored and does not contribute to the loss computation
>> leadingDim - the leading dimension for the output
*/
void _CudaCrossEntropyBackward(XTensor * dedy, const XTensor * output,
const XTensor * gold, const XTensor * weight,
XTensor * padding, int leadingDim)
{
int n = leadingDim < 0 ? output->order - 1 : leadingDim;
_Div(gold, output, dedy);
_NegateMe(dedy);
if(weight != NULL)
_MultiplyDimMe(dedy, weight, n);
if(padding != NULL) {
int paddingOrder = padding->order;
int * paddingDims = new int[paddingOrder];
memcpy(paddingDims, padding->dimSize, padding->order * sizeof(int));
padding->Reshape(padding->unitNum);
int order = dedy->order;
int * dims = new int[order];
memcpy(dims, dedy->dimSize, dedy->order * sizeof(int));
dedy->Reshape(dedy->unitNum/dedy->GetDim(n), dedy->GetDim(n));
_MultiplyDimMe(dedy, padding, 0);
padding->Reshape(paddingOrder, paddingDims);
dedy->Reshape(order, dims);
delete[] paddingDims;
delete[] dims;
}
if(padding != NULL) {
XTensor * tmp = NewTensor(padding);
_IsNonZero(padding, tmp);
DTYPE nonZeroNum;
_ReduceSumAll(tmp, &nonZeroNum);
_ScaleAndShiftMe(dedy, (DTYPE)1.0/nonZeroNum);
delete tmp;
}
else {
int num = dedy->unitNum / dedy->GetDim(n);
_ScaleAndShiftMe(dedy, (DTYPE)1.0/(DTYPE)num);
}
}
} // namespace nts(NiuTrans.Tensor)
#endif // __CROSSENTROPY_CUH__ | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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