system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00199f7d_00000000-6_cosineSimilarityCuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z20cosineSimilarityCudaP6float3mPfP6float3mPf
.type _Z49__device_stub__Z20cosineSimilarityCudaP6float3mPfP6float3mPf, @function
_Z49__device_stub__Z20cosineSimilarityCudaP6float3mPfP6float3mPf:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20cosineSimilarityCudaP6float3mPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z20cosineSimilarityCudaP6float3mPfP6float3mPf, .-_Z49__device_stub__Z20cosineSimilarityCudaP6float3mPfP6float3mPf
.globl _Z20cosineSimilarityCudaP6float3mPf
.type _Z20cosineSimilarityCudaP6float3mPf, @function
_Z20cosineSimilarityCudaP6float3mPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z20cosineSimilarityCudaP6float3mPfP6float3mPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20cosineSimilarityCudaP6float3mPf, .-_Z20cosineSimilarityCudaP6float3mPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20cosineSimilarityCudaP6float3mPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20cosineSimilarityCudaP6float3mPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cosineSimilarityCuda.hip"
.globl _Z35__device_stub__cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf # -- Begin function _Z35__device_stub__cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf
.p2align 4, 0x90
.type _Z35__device_stub__cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf,@function
_Z35__device_stub__cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf: # @_Z35__device_stub__cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z35__device_stub__cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf, .Lfunc_end0-_Z35__device_stub__cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf,@object # @_Z20cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf
.section .rodata,"a",@progbits
.globl _Z20cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf
.p2align 3, 0x0
_Z20cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf:
.quad _Z35__device_stub__cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf
.size _Z20cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf"
.size .L__unnamed_1, 53
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<math.h>
__global__
void sub(float *a,float *b,int count,float mean)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if(id<count)
{
b[id] = (a[id]-mean)*(a[id]-mean);
}
}
int main(void)
{
float h_a[10],h_b[10],mean,std_dev=0,var=0;
int i,count=10,sum=0;
float *d_a,*d_b;
for(i=0;i<count;i++)
{
h_a[i] = i;
h_b[i] = 0.0;
}
printf("\n\tPrinting Array: ");
for(i=0;i<count;i++)
{
printf("\n\t %f ",h_a[i]);
}
printf("\n\n\tAddition of Array = ");
for(i=0;i<count;i++)
{
sum+=h_a[i];
}
printf(" %d",sum);
mean = (float)sum/count;
printf("\n\tMean = %f",mean);
cudaMalloc(&d_a,sizeof(int)*count);
cudaMemcpy(d_a,h_a,sizeof(int)*count,cudaMemcpyHostToDevice);
cudaMalloc(&d_b,sizeof(int)*count);
cudaMemcpy(d_b,h_b,sizeof(int)*count,cudaMemcpyHostToDevice);
sub<<<1,10>>>(d_a,d_b,count,mean);
cudaMemcpy(h_b,d_b,sizeof(int)*count,cudaMemcpyDeviceToHost);
for(i=0;i<count;i++)
{
var+=h_b[i];
}
var = var/(count);
printf("\n\tVariance = %f",var);
std_dev = sqrt(var);
printf("\n\tStandard Deviation = %f",std_dev);
cudaFree(d_a);
cudaFree(d_b);
return 0;
} | code for sm_80
Function : _Z3subPfS_if
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0205 */
/*00b0*/ FADD R0, R2, -c[0x0][0x174] ; /* 0x80005d0002007621 */
/* 0x004fc80000000000 */
/*00c0*/ FMUL R7, R0, R0 ; /* 0x0000000000077220 */
/* 0x000fca0000400000 */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<math.h>
__global__
void sub(float *a,float *b,int count,float mean)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if(id<count)
{
b[id] = (a[id]-mean)*(a[id]-mean);
}
}
int main(void)
{
float h_a[10],h_b[10],mean,std_dev=0,var=0;
int i,count=10,sum=0;
float *d_a,*d_b;
for(i=0;i<count;i++)
{
h_a[i] = i;
h_b[i] = 0.0;
}
printf("\n\tPrinting Array: ");
for(i=0;i<count;i++)
{
printf("\n\t %f ",h_a[i]);
}
printf("\n\n\tAddition of Array = ");
for(i=0;i<count;i++)
{
sum+=h_a[i];
}
printf(" %d",sum);
mean = (float)sum/count;
printf("\n\tMean = %f",mean);
cudaMalloc(&d_a,sizeof(int)*count);
cudaMemcpy(d_a,h_a,sizeof(int)*count,cudaMemcpyHostToDevice);
cudaMalloc(&d_b,sizeof(int)*count);
cudaMemcpy(d_b,h_b,sizeof(int)*count,cudaMemcpyHostToDevice);
sub<<<1,10>>>(d_a,d_b,count,mean);
cudaMemcpy(h_b,d_b,sizeof(int)*count,cudaMemcpyDeviceToHost);
for(i=0;i<count;i++)
{
var+=h_b[i];
}
var = var/(count);
printf("\n\tVariance = %f",var);
std_dev = sqrt(var);
printf("\n\tStandard Deviation = %f",std_dev);
cudaFree(d_a);
cudaFree(d_b);
return 0;
} | .file "tmpxft_00026a09_00000000-6_cuda_standardDeviation.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3subPfS_ifPfS_if
.type _Z26__device_stub__Z3subPfS_ifPfS_if, @function
_Z26__device_stub__Z3subPfS_ifPfS_if:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3subPfS_if(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3subPfS_ifPfS_if, .-_Z26__device_stub__Z3subPfS_ifPfS_if
.globl _Z3subPfS_if
.type _Z3subPfS_if, @function
_Z3subPfS_if:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3subPfS_ifPfS_if
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3subPfS_if, .-_Z3subPfS_if
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\n\tPrinting Array: "
.LC2:
.string "\n\t %f "
.LC3:
.string "\n\n\tAddition of Array = "
.LC4:
.string " %d"
.LC6:
.string "\n\tMean = %f"
.LC7:
.string "\n\tVariance = %f"
.LC8:
.string "\n\tStandard Deviation = %f"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $168, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 64(%rsp,%rax,4)
movl $0x00000000, 112(%rsp,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L12
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 64(%rsp), %rbx
leaq 104(%rsp), %r12
movq %rbx, %rbp
leaq .LC2(%rip), %r13
.L13:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbp
cmpq %r12, %rbp
jne .L13
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebp
.L14:
pxor %xmm0, %xmm0
cvtsi2ssl %ebp, %xmm0
addss (%rbx), %xmm0
cvttss2sil %xmm0, %ebp
addq $4, %rbx
cmpq %r12, %rbx
jne .L14
movl %ebp, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %ebp, %xmm0
divss .LC5(%rip), %xmm0
movss %xmm0, 12(%rsp)
cvtss2sd %xmm0, %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 24(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 112(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $10, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L15:
leaq 112(%rsp), %rbx
movl $2, %ecx
movl $40, %edx
movq 32(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
leaq 152(%rsp), %rdx
pxor %xmm0, %xmm0
.L16:
addss (%rax), %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L16
divss .LC5(%rip), %xmm0
movss %xmm0, 12(%rsp)
cvtss2sd %xmm0, %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
movss 12(%rsp), %xmm1
ucomiss %xmm1, %xmm0
ja .L26
sqrtss %xmm1, %xmm1
movaps %xmm1, %xmm0
.L19:
cvtss2sd %xmm0, %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movss 12(%rsp), %xmm0
movl $10, %edx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z26__device_stub__Z3subPfS_ifPfS_if
jmp .L15
.L26:
movss 12(%rsp), %xmm0
call sqrtf@PLT
jmp .L19
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z3subPfS_if"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z3subPfS_if(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1092616192
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<math.h>
__global__
void sub(float *a,float *b,int count,float mean)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if(id<count)
{
b[id] = (a[id]-mean)*(a[id]-mean);
}
}
int main(void)
{
float h_a[10],h_b[10],mean,std_dev=0,var=0;
int i,count=10,sum=0;
float *d_a,*d_b;
for(i=0;i<count;i++)
{
h_a[i] = i;
h_b[i] = 0.0;
}
printf("\n\tPrinting Array: ");
for(i=0;i<count;i++)
{
printf("\n\t %f ",h_a[i]);
}
printf("\n\n\tAddition of Array = ");
for(i=0;i<count;i++)
{
sum+=h_a[i];
}
printf(" %d",sum);
mean = (float)sum/count;
printf("\n\tMean = %f",mean);
cudaMalloc(&d_a,sizeof(int)*count);
cudaMemcpy(d_a,h_a,sizeof(int)*count,cudaMemcpyHostToDevice);
cudaMalloc(&d_b,sizeof(int)*count);
cudaMemcpy(d_b,h_b,sizeof(int)*count,cudaMemcpyHostToDevice);
sub<<<1,10>>>(d_a,d_b,count,mean);
cudaMemcpy(h_b,d_b,sizeof(int)*count,cudaMemcpyDeviceToHost);
for(i=0;i<count;i++)
{
var+=h_b[i];
}
var = var/(count);
printf("\n\tVariance = %f",var);
std_dev = sqrt(var);
printf("\n\tStandard Deviation = %f",std_dev);
cudaFree(d_a);
cudaFree(d_b);
return 0;
} | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<math.h>
__global__
void sub(float *a,float *b,int count,float mean)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if(id<count)
{
b[id] = (a[id]-mean)*(a[id]-mean);
}
}
int main(void)
{
float h_a[10],h_b[10],mean,std_dev=0,var=0;
int i,count=10,sum=0;
float *d_a,*d_b;
for(i=0;i<count;i++)
{
h_a[i] = i;
h_b[i] = 0.0;
}
printf("\n\tPrinting Array: ");
for(i=0;i<count;i++)
{
printf("\n\t %f ",h_a[i]);
}
printf("\n\n\tAddition of Array = ");
for(i=0;i<count;i++)
{
sum+=h_a[i];
}
printf(" %d",sum);
mean = (float)sum/count;
printf("\n\tMean = %f",mean);
hipMalloc(&d_a,sizeof(int)*count);
hipMemcpy(d_a,h_a,sizeof(int)*count,hipMemcpyHostToDevice);
hipMalloc(&d_b,sizeof(int)*count);
hipMemcpy(d_b,h_b,sizeof(int)*count,hipMemcpyHostToDevice);
sub<<<1,10>>>(d_a,d_b,count,mean);
hipMemcpy(h_b,d_b,sizeof(int)*count,hipMemcpyDeviceToHost);
for(i=0;i<count;i++)
{
var+=h_b[i];
}
var = var/(count);
printf("\n\tVariance = %f",var);
std_dev = sqrt(var);
printf("\n\tStandard Deviation = %f",std_dev);
hipFree(d_a);
hipFree(d_b);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<math.h>
__global__
void sub(float *a,float *b,int count,float mean)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if(id<count)
{
b[id] = (a[id]-mean)*(a[id]-mean);
}
}
int main(void)
{
float h_a[10],h_b[10],mean,std_dev=0,var=0;
int i,count=10,sum=0;
float *d_a,*d_b;
for(i=0;i<count;i++)
{
h_a[i] = i;
h_b[i] = 0.0;
}
printf("\n\tPrinting Array: ");
for(i=0;i<count;i++)
{
printf("\n\t %f ",h_a[i]);
}
printf("\n\n\tAddition of Array = ");
for(i=0;i<count;i++)
{
sum+=h_a[i];
}
printf(" %d",sum);
mean = (float)sum/count;
printf("\n\tMean = %f",mean);
hipMalloc(&d_a,sizeof(int)*count);
hipMemcpy(d_a,h_a,sizeof(int)*count,hipMemcpyHostToDevice);
hipMalloc(&d_b,sizeof(int)*count);
hipMemcpy(d_b,h_b,sizeof(int)*count,hipMemcpyHostToDevice);
sub<<<1,10>>>(d_a,d_b,count,mean);
hipMemcpy(h_b,d_b,sizeof(int)*count,hipMemcpyDeviceToHost);
for(i=0;i<count;i++)
{
var+=h_b[i];
}
var = var/(count);
printf("\n\tVariance = %f",var);
std_dev = sqrt(var);
printf("\n\tStandard Deviation = %f",std_dev);
hipFree(d_a);
hipFree(d_b);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3subPfS_if
.globl _Z3subPfS_if
.p2align 8
.type _Z3subPfS_if,@function
_Z3subPfS_if:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_subrev_f32_e32 v2, s0, v2
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3subPfS_if
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3subPfS_if, .Lfunc_end0-_Z3subPfS_if
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3subPfS_if
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3subPfS_if.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<math.h>
__global__
void sub(float *a,float *b,int count,float mean)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if(id<count)
{
b[id] = (a[id]-mean)*(a[id]-mean);
}
}
int main(void)
{
float h_a[10],h_b[10],mean,std_dev=0,var=0;
int i,count=10,sum=0;
float *d_a,*d_b;
for(i=0;i<count;i++)
{
h_a[i] = i;
h_b[i] = 0.0;
}
printf("\n\tPrinting Array: ");
for(i=0;i<count;i++)
{
printf("\n\t %f ",h_a[i]);
}
printf("\n\n\tAddition of Array = ");
for(i=0;i<count;i++)
{
sum+=h_a[i];
}
printf(" %d",sum);
mean = (float)sum/count;
printf("\n\tMean = %f",mean);
hipMalloc(&d_a,sizeof(int)*count);
hipMemcpy(d_a,h_a,sizeof(int)*count,hipMemcpyHostToDevice);
hipMalloc(&d_b,sizeof(int)*count);
hipMemcpy(d_b,h_b,sizeof(int)*count,hipMemcpyHostToDevice);
sub<<<1,10>>>(d_a,d_b,count,mean);
hipMemcpy(h_b,d_b,sizeof(int)*count,hipMemcpyDeviceToHost);
for(i=0;i<count;i++)
{
var+=h_b[i];
}
var = var/(count);
printf("\n\tVariance = %f",var);
std_dev = sqrt(var);
printf("\n\tStandard Deviation = %f",std_dev);
hipFree(d_a);
hipFree(d_b);
return 0;
} | .text
.file "cuda_standardDeviation.hip"
.globl _Z18__device_stub__subPfS_if # -- Begin function _Z18__device_stub__subPfS_if
.p2align 4, 0x90
.type _Z18__device_stub__subPfS_if,@function
_Z18__device_stub__subPfS_if: # @_Z18__device_stub__subPfS_if
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movss %xmm0, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3subPfS_if, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__subPfS_if, .Lfunc_end0-_Z18__device_stub__subPfS_if
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x41200000 # float 10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $216, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
xorps %xmm0, %xmm0
movaps %xmm0, 128(%rsp)
movaps %xmm0, 144(%rsp)
movq $0, 160(%rsp)
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, 176(%rsp,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB1_1
# %bb.2:
xorl %ebx, %ebx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movss 176(%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB1_3
# %bb.4:
xorl %r14d, %r14d
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ebx, %xmm0
addss 176(%rsp,%r14,4), %xmm0
cvttss2si %xmm0, %ebx
incq %r14
cmpq $10, %r14
jne .LBB1_5
# %bb.6:
movl $.L.str.3, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
xorps %xmm0, %xmm0
cvtsi2ss %ebx, %xmm0
divss .LCPI1_0(%rip), %xmm0
movss %xmm0, 4(%rsp) # 4-byte Spill
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 176(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $10, 28(%rsp)
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 24(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3subPfS_if, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq 8(%rsp), %rsi
leaq 128(%rsp), %rdi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_9: # =>This Inner Loop Header: Depth=1
addss 128(%rsp,%rax,4), %xmm0
incq %rax
cmpq $10, %rax
jne .LBB1_9
# %bb.10:
divss .LCPI1_0(%rip), %xmm0
movss %xmm0, 4(%rsp) # 4-byte Spill
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
xorps %xmm0, %xmm0
movss 4(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
jb .LBB1_12
# %bb.11:
sqrtss %xmm0, %xmm0
jmp .LBB1_13
.LBB1_12: # %call.sqrt
callq sqrtf
.LBB1_13: # %.split
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3subPfS_if, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3subPfS_if,@object # @_Z3subPfS_if
.section .rodata,"a",@progbits
.globl _Z3subPfS_if
.p2align 3, 0x0
_Z3subPfS_if:
.quad _Z18__device_stub__subPfS_if
.size _Z3subPfS_if, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n\tPrinting Array: "
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n\t %f "
.size .L.str.1, 8
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n\n\tAddition of Array = "
.size .L.str.2, 24
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " %d"
.size .L.str.3, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\n\tMean = %f"
.size .L.str.4, 12
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\n\tVariance = %f"
.size .L.str.5, 16
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\n\tStandard Deviation = %f"
.size .L.str.6, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3subPfS_if"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__subPfS_if
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3subPfS_if
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3subPfS_if
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0205 */
/*00b0*/ FADD R0, R2, -c[0x0][0x174] ; /* 0x80005d0002007621 */
/* 0x004fc80000000000 */
/*00c0*/ FMUL R7, R0, R0 ; /* 0x0000000000077220 */
/* 0x000fca0000400000 */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3subPfS_if
.globl _Z3subPfS_if
.p2align 8
.type _Z3subPfS_if,@function
_Z3subPfS_if:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_subrev_f32_e32 v2, s0, v2
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3subPfS_if
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3subPfS_if, .Lfunc_end0-_Z3subPfS_if
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3subPfS_if
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3subPfS_if.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00026a09_00000000-6_cuda_standardDeviation.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3subPfS_ifPfS_if
.type _Z26__device_stub__Z3subPfS_ifPfS_if, @function
_Z26__device_stub__Z3subPfS_ifPfS_if:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3subPfS_if(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3subPfS_ifPfS_if, .-_Z26__device_stub__Z3subPfS_ifPfS_if
.globl _Z3subPfS_if
.type _Z3subPfS_if, @function
_Z3subPfS_if:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3subPfS_ifPfS_if
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3subPfS_if, .-_Z3subPfS_if
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\n\tPrinting Array: "
.LC2:
.string "\n\t %f "
.LC3:
.string "\n\n\tAddition of Array = "
.LC4:
.string " %d"
.LC6:
.string "\n\tMean = %f"
.LC7:
.string "\n\tVariance = %f"
.LC8:
.string "\n\tStandard Deviation = %f"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $168, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 64(%rsp,%rax,4)
movl $0x00000000, 112(%rsp,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L12
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 64(%rsp), %rbx
leaq 104(%rsp), %r12
movq %rbx, %rbp
leaq .LC2(%rip), %r13
.L13:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbp
cmpq %r12, %rbp
jne .L13
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebp
.L14:
pxor %xmm0, %xmm0
cvtsi2ssl %ebp, %xmm0
addss (%rbx), %xmm0
cvttss2sil %xmm0, %ebp
addq $4, %rbx
cmpq %r12, %rbx
jne .L14
movl %ebp, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %ebp, %xmm0
divss .LC5(%rip), %xmm0
movss %xmm0, 12(%rsp)
cvtss2sd %xmm0, %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 24(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 112(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $10, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L15:
leaq 112(%rsp), %rbx
movl $2, %ecx
movl $40, %edx
movq 32(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
leaq 152(%rsp), %rdx
pxor %xmm0, %xmm0
.L16:
addss (%rax), %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L16
divss .LC5(%rip), %xmm0
movss %xmm0, 12(%rsp)
cvtss2sd %xmm0, %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
movss 12(%rsp), %xmm1
ucomiss %xmm1, %xmm0
ja .L26
sqrtss %xmm1, %xmm1
movaps %xmm1, %xmm0
.L19:
cvtss2sd %xmm0, %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movss 12(%rsp), %xmm0
movl $10, %edx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z26__device_stub__Z3subPfS_ifPfS_if
jmp .L15
.L26:
movss 12(%rsp), %xmm0
call sqrtf@PLT
jmp .L19
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z3subPfS_if"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z3subPfS_if(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1092616192
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_standardDeviation.hip"
.globl _Z18__device_stub__subPfS_if # -- Begin function _Z18__device_stub__subPfS_if
.p2align 4, 0x90
.type _Z18__device_stub__subPfS_if,@function
_Z18__device_stub__subPfS_if: # @_Z18__device_stub__subPfS_if
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movss %xmm0, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3subPfS_if, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__subPfS_if, .Lfunc_end0-_Z18__device_stub__subPfS_if
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x41200000 # float 10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $216, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
xorps %xmm0, %xmm0
movaps %xmm0, 128(%rsp)
movaps %xmm0, 144(%rsp)
movq $0, 160(%rsp)
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, 176(%rsp,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB1_1
# %bb.2:
xorl %ebx, %ebx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movss 176(%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB1_3
# %bb.4:
xorl %r14d, %r14d
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ebx, %xmm0
addss 176(%rsp,%r14,4), %xmm0
cvttss2si %xmm0, %ebx
incq %r14
cmpq $10, %r14
jne .LBB1_5
# %bb.6:
movl $.L.str.3, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
xorps %xmm0, %xmm0
cvtsi2ss %ebx, %xmm0
divss .LCPI1_0(%rip), %xmm0
movss %xmm0, 4(%rsp) # 4-byte Spill
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 176(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $10, 28(%rsp)
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 24(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3subPfS_if, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq 8(%rsp), %rsi
leaq 128(%rsp), %rdi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_9: # =>This Inner Loop Header: Depth=1
addss 128(%rsp,%rax,4), %xmm0
incq %rax
cmpq $10, %rax
jne .LBB1_9
# %bb.10:
divss .LCPI1_0(%rip), %xmm0
movss %xmm0, 4(%rsp) # 4-byte Spill
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
xorps %xmm0, %xmm0
movss 4(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
jb .LBB1_12
# %bb.11:
sqrtss %xmm0, %xmm0
jmp .LBB1_13
.LBB1_12: # %call.sqrt
callq sqrtf
.LBB1_13: # %.split
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3subPfS_if, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3subPfS_if,@object # @_Z3subPfS_if
.section .rodata,"a",@progbits
.globl _Z3subPfS_if
.p2align 3, 0x0
_Z3subPfS_if:
.quad _Z18__device_stub__subPfS_if
.size _Z3subPfS_if, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n\tPrinting Array: "
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n\t %f "
.size .L.str.1, 8
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n\n\tAddition of Array = "
.size .L.str.2, 24
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " %d"
.size .L.str.3, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\n\tMean = %f"
.size .L.str.4, 12
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\n\tVariance = %f"
.size .L.str.5, 16
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\n\tStandard Deviation = %f"
.size .L.str.6, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3subPfS_if"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__subPfS_if
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3subPfS_if
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kernel(float *A, float *C, const int N)
{
int i = blockIdx.x * blockDim.x + threadIdx.x*16;
if (i < N) C[i] = A[i];
} | code for sm_80
Function : _Z6kernelPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0030*/ SHF.L.U32 R0, R0, 0x4, RZ ; /* 0x0000000400007819 */
/* 0x001fca00000006ff */
/*0040*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x002fca00078e0200 */
/*0050*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0090*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0205 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0205 */
/*00c0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kernel(float *A, float *C, const int N)
{
int i = blockIdx.x * blockDim.x + threadIdx.x*16;
if (i < N) C[i] = A[i];
} | .file "tmpxft_00098636_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z6kernelPfS_iPfS_i
.type _Z28__device_stub__Z6kernelPfS_iPfS_i, @function
_Z28__device_stub__Z6kernelPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z6kernelPfS_iPfS_i, .-_Z28__device_stub__Z6kernelPfS_iPfS_i
.globl _Z6kernelPfS_i
.type _Z6kernelPfS_i, @function
_Z6kernelPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6kernelPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6kernelPfS_i, .-_Z6kernelPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kernel(float *A, float *C, const int N)
{
int i = blockIdx.x * blockDim.x + threadIdx.x*16;
if (i < N) C[i] = A[i];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel(float *A, float *C, const int N)
{
int i = blockIdx.x * blockDim.x + threadIdx.x*16;
if (i < N) C[i] = A[i];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel(float *A, float *C, const int N)
{
int i = blockIdx.x * blockDim.x + threadIdx.x*16;
if (i < N) C[i] = A[i];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPfS_i
.globl _Z6kernelPfS_i
.p2align 8
.type _Z6kernelPfS_i,@function
_Z6kernelPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s2
s_mov_b32 s2, exec_lo
v_lshl_add_u32 v0, v0, 4, s15
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPfS_i, .Lfunc_end0-_Z6kernelPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel(float *A, float *C, const int N)
{
int i = blockIdx.x * blockDim.x + threadIdx.x*16;
if (i < N) C[i] = A[i];
} | .text
.file "kernel.hip"
.globl _Z21__device_stub__kernelPfS_i # -- Begin function _Z21__device_stub__kernelPfS_i
.p2align 4, 0x90
.type _Z21__device_stub__kernelPfS_i,@function
_Z21__device_stub__kernelPfS_i: # @_Z21__device_stub__kernelPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPfS_i, .Lfunc_end0-_Z21__device_stub__kernelPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPfS_i,@object # @_Z6kernelPfS_i
.section .rodata,"a",@progbits
.globl _Z6kernelPfS_i
.p2align 3, 0x0
_Z6kernelPfS_i:
.quad _Z21__device_stub__kernelPfS_i
.size _Z6kernelPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelPfS_i"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0030*/ SHF.L.U32 R0, R0, 0x4, RZ ; /* 0x0000000400007819 */
/* 0x001fca00000006ff */
/*0040*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x002fca00078e0200 */
/*0050*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0090*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0205 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0205 */
/*00c0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPfS_i
.globl _Z6kernelPfS_i
.p2align 8
.type _Z6kernelPfS_i,@function
_Z6kernelPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s2
s_mov_b32 s2, exec_lo
v_lshl_add_u32 v0, v0, 4, s15
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPfS_i, .Lfunc_end0-_Z6kernelPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00098636_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z6kernelPfS_iPfS_i
.type _Z28__device_stub__Z6kernelPfS_iPfS_i, @function
_Z28__device_stub__Z6kernelPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z6kernelPfS_iPfS_i, .-_Z28__device_stub__Z6kernelPfS_iPfS_i
.globl _Z6kernelPfS_i
.type _Z6kernelPfS_i, @function
_Z6kernelPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6kernelPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6kernelPfS_i, .-_Z6kernelPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z21__device_stub__kernelPfS_i # -- Begin function _Z21__device_stub__kernelPfS_i
.p2align 4, 0x90
.type _Z21__device_stub__kernelPfS_i,@function
_Z21__device_stub__kernelPfS_i: # @_Z21__device_stub__kernelPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPfS_i, .Lfunc_end0-_Z21__device_stub__kernelPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPfS_i,@object # @_Z6kernelPfS_i
.section .rodata,"a",@progbits
.globl _Z6kernelPfS_i
.p2align 3, 0x0
_Z6kernelPfS_i:
.quad _Z21__device_stub__kernelPfS_i
.size _Z6kernelPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelPfS_i"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
#define N 1<<7
#define THREADS_PER_BLOCK 1024
__global__ void dot(float *a, float *b, float *c) {
__shared__ float temp[THREADS_PER_BLOCK];
int index = threadIdx.x + blockIdx.x * blockDim.x;
if (index >= N) return;
temp[threadIdx.x] = a[index] * b[index];
__syncthreads();
if (0 == threadIdx.x) {
float sum = 0.0;
int max = THREADS_PER_BLOCK;
if (N < max) max = N;
for (int i = 0; i < max; i++) {
sum += temp[i];
}
//c[0] = sum;
atomicAdd(c, sum);
}
}
void random_floats(float *a, float size)
{
int i;
for (i=0; i<size; i++)
a[i] = i;
return;
}
int main(void) {
int num_SMs;
int devId = 0; // Unique GPU
cudaDeviceGetAttribute(&num_SMs, cudaDevAttrMultiProcessorCount, devId); // Y devId?
printf("Number of SMs: %d\n", num_SMs);
int i;
float result;
float *a, *b, *c; // host copies of a, b, c
float *dev_a, *dev_b, *dev_c; // device copies of a, b, c
int size = N * sizeof(float); // we need space for N floats
// allocate device copies of a, b, c
cudaMalloc( (void**)&dev_a, size );
cudaMalloc( (void**)&dev_b, size );
cudaMalloc( (void**)&dev_c, sizeof(float) );
a = (float*)malloc( size );
b = (float*)malloc( size );
c = (float*)malloc( sizeof(float) );
random_floats( a, N );
random_floats( b, N );
/*
printf("a = ");
for (i=0; i<N; i++) printf("%d, ", a[i]);
printf("\n");
printf("b = ");
for (i=0; i<N; i++) printf("%d, ", b[i]);
printf("\n");
*/
result = 0;
for (i=0; i<N; i++) result += a[i] * b[i];
*c = 0;
// copy inputs to device
cudaMemcpy( dev_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy( dev_b, b, size, cudaMemcpyHostToDevice);
int blocks = (int)(N/THREADS_PER_BLOCK) + 1; // ceil(...)
//if(blocks<1) blocks=1;
// launch dot() kernel
dot <<< blocks, THREADS_PER_BLOCK >>> (dev_a, dev_b, dev_c);
// copy device result back to host copy of c
cudaMemcpy(c, dev_c, sizeof(float) , cudaMemcpyDeviceToHost);
printf("*c = %.2f\n", *c);
printf("result = %.2f\n", result);
free(a); free(b); free(c);
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
return 0;
} | code for sm_80
Function : _Z3dotPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R7 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0207 */
/*0040*/ ISETP.GT.AND P0, PT, R2, 0x7f, PT ; /* 0x0000007f0200780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R2, R3, c[0x0][0x168] ; /* 0x00005a0002047625 */
/* 0x000fc800078e0203 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe400078e0203 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00d0*/ FMUL R0, R4, R3 ; /* 0x0000000304007220 */
/* 0x004fca0000400000 */
/*00e0*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x0001e80000004800 */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0100*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0110*/ LDS.128 R8, [RZ] ; /* 0x00000000ff087984 */
/* 0x001e220000000c00 */
/*0120*/ MOV R2, c[0x0][0x170] ; /* 0x00005c0000027a02 */
/* 0x000fc40000000f00 */
/*0130*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fe20000000f00 */
/*0140*/ LDS.128 R16, [0x10] ; /* 0x00001000ff107984 */
/* 0x000e680000000c00 */
/*0150*/ LDS.128 R12, [0x20] ; /* 0x00002000ff0c7984 */
/* 0x000ea80000000c00 */
/*0160*/ LDS.128 R4, [0x30] ; /* 0x00003000ff047984 */
/* 0x000ee20000000c00 */
/*0170*/ FADD R8, RZ, R8 ; /* 0x00000008ff087221 */
/* 0x001fc80000000000 */
/*0180*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x000fc80000000000 */
/*0190*/ FADD R10, R9, R10 ; /* 0x0000000a090a7221 */
/* 0x000fc80000000000 */
/*01a0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x000fc80000000000 */
/*01b0*/ FADD R16, R11, R16 ; /* 0x000000100b107221 */
/* 0x002fe40000000000 */
/*01c0*/ LDS.128 R8, [0x40] ; /* 0x00004000ff087984 */
/* 0x000e240000000c00 */
/*01d0*/ FADD R17, R16, R17 ; /* 0x0000001110117221 */
/* 0x000fc80000000000 */
/*01e0*/ FADD R18, R17, R18 ; /* 0x0000001211127221 */
/* 0x000fc80000000000 */
/*01f0*/ FADD R19, R18, R19 ; /* 0x0000001312137221 */
/* 0x000fc80000000000 */
/*0200*/ FADD R12, R19, R12 ; /* 0x0000000c130c7221 */
/* 0x004fe40000000000 */
/*0210*/ LDS.128 R16, [0x50] ; /* 0x00005000ff107984 */
/* 0x000e640000000c00 */
/*0220*/ FADD R13, R12, R13 ; /* 0x0000000d0c0d7221 */
/* 0x000fc80000000000 */
/*0230*/ FADD R14, R13, R14 ; /* 0x0000000e0d0e7221 */
/* 0x000fc80000000000 */
/*0240*/ FADD R15, R14, R15 ; /* 0x0000000f0e0f7221 */
/* 0x000fc80000000000 */
/*0250*/ FADD R4, R15, R4 ; /* 0x000000040f047221 */
/* 0x008fe40000000000 */
/*0260*/ LDS.128 R12, [0x60] ; /* 0x00006000ff0c7984 */
/* 0x000ea40000000c00 */
/*0270*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x000fc80000000000 */
/*0280*/ FADD R6, R5, R6 ; /* 0x0000000605067221 */
/* 0x000fc80000000000 */
/*0290*/ FADD R7, R6, R7 ; /* 0x0000000706077221 */
/* 0x000fc80000000000 */
/*02a0*/ FADD R8, R7, R8 ; /* 0x0000000807087221 */
/* 0x001fe40000000000 */
/*02b0*/ LDS.128 R4, [0x70] ; /* 0x00007000ff047984 */
/* 0x000e240000000c00 */
/*02c0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x000fc80000000000 */
/*02d0*/ FADD R10, R9, R10 ; /* 0x0000000a090a7221 */
/* 0x000fc80000000000 */
/*02e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x000fc80000000000 */
/*02f0*/ FADD R16, R11, R16 ; /* 0x000000100b107221 */
/* 0x002fe40000000000 */
/*0300*/ LDS.128 R8, [0x80] ; /* 0x00008000ff087984 */
/* 0x000e640000000c00 */
/*0310*/ FADD R17, R16, R17 ; /* 0x0000001110117221 */
/* 0x000fc80000000000 */
/*0320*/ FADD R18, R17, R18 ; /* 0x0000001211127221 */
/* 0x000fc80000000000 */
/*0330*/ FADD R19, R18, R19 ; /* 0x0000001312137221 */
/* 0x000fc80000000000 */
/*0340*/ FADD R12, R19, R12 ; /* 0x0000000c130c7221 */
/* 0x004fe40000000000 */
/*0350*/ LDS.128 R16, [0x90] ; /* 0x00009000ff107984 */
/* 0x000ea40000000c00 */
/*0360*/ FADD R13, R12, R13 ; /* 0x0000000d0c0d7221 */
/* 0x000fc80000000000 */
/*0370*/ FADD R14, R13, R14 ; /* 0x0000000e0d0e7221 */
/* 0x000fc80000000000 */
/*0380*/ FADD R15, R14, R15 ; /* 0x0000000f0e0f7221 */
/* 0x000fc80000000000 */
/*0390*/ FADD R4, R15, R4 ; /* 0x000000040f047221 */
/* 0x001fe40000000000 */
/*03a0*/ LDS.128 R12, [0xa0] ; /* 0x0000a000ff0c7984 */
/* 0x000e240000000c00 */
/*03b0*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x000fc80000000000 */
/*03c0*/ FADD R6, R5, R6 ; /* 0x0000000605067221 */
/* 0x000fc80000000000 */
/*03d0*/ FADD R7, R6, R7 ; /* 0x0000000706077221 */
/* 0x000fc80000000000 */
/*03e0*/ FADD R8, R7, R8 ; /* 0x0000000807087221 */
/* 0x002fe40000000000 */
/*03f0*/ LDS.128 R4, [0xb0] ; /* 0x0000b000ff047984 */
/* 0x000e640000000c00 */
/*0400*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x000fc80000000000 */
/*0410*/ FADD R10, R9, R10 ; /* 0x0000000a090a7221 */
/* 0x000fc80000000000 */
/*0420*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x000fc80000000000 */
/*0430*/ FADD R16, R11, R16 ; /* 0x000000100b107221 */
/* 0x004fe40000000000 */
/*0440*/ LDS.128 R8, [0xc0] ; /* 0x0000c000ff087984 */
/* 0x000ea40000000c00 */
/*0450*/ FADD R17, R16, R17 ; /* 0x0000001110117221 */
/* 0x000fc80000000000 */
/*0460*/ FADD R18, R17, R18 ; /* 0x0000001211127221 */
/* 0x000fc80000000000 */
/*0470*/ FADD R19, R18, R19 ; /* 0x0000001312137221 */
/* 0x000fc80000000000 */
/*0480*/ FADD R12, R19, R12 ; /* 0x0000000c130c7221 */
/* 0x001fe40000000000 */
/*0490*/ LDS.128 R16, [0xd0] ; /* 0x0000d000ff107984 */
/* 0x000e240000000c00 */
/*04a0*/ FADD R13, R12, R13 ; /* 0x0000000d0c0d7221 */
/* 0x000fc80000000000 */
/*04b0*/ FADD R14, R13, R14 ; /* 0x0000000e0d0e7221 */
/* 0x000fc80000000000 */
/*04c0*/ FADD R15, R14, R15 ; /* 0x0000000f0e0f7221 */
/* 0x000fc80000000000 */
/*04d0*/ FADD R4, R15, R4 ; /* 0x000000040f047221 */
/* 0x002fe40000000000 */
/*04e0*/ LDS.128 R12, [0xe0] ; /* 0x0000e000ff0c7984 */
/* 0x000e640000000c00 */
/*04f0*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x000fc80000000000 */
/*0500*/ FADD R6, R5, R6 ; /* 0x0000000605067221 */
/* 0x000fc80000000000 */
/*0510*/ FADD R7, R6, R7 ; /* 0x0000000706077221 */
/* 0x000fc80000000000 */
/*0520*/ FADD R8, R7, R8 ; /* 0x0000000807087221 */
/* 0x004fe40000000000 */
/*0530*/ LDS.128 R4, [0xf0] ; /* 0x0000f000ff047984 */
/* 0x000ea40000000c00 */
/*0540*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x000fc80000000000 */
/*0550*/ FADD R10, R9, R10 ; /* 0x0000000a090a7221 */
/* 0x000fc80000000000 */
/*0560*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x000fc80000000000 */
/*0570*/ FADD R16, R11, R16 ; /* 0x000000100b107221 */
/* 0x001fe40000000000 */
/*0580*/ LDS.128 R8, [0x100] ; /* 0x00010000ff087984 */
/* 0x000e240000000c00 */
/*0590*/ FADD R17, R16, R17 ; /* 0x0000001110117221 */
/* 0x000fc80000000000 */
/*05a0*/ FADD R18, R17, R18 ; /* 0x0000001211127221 */
/* 0x000fc80000000000 */
/*05b0*/ FADD R19, R18, R19 ; /* 0x0000001312137221 */
/* 0x000fc80000000000 */
/*05c0*/ FADD R12, R19, R12 ; /* 0x0000000c130c7221 */
/* 0x002fe40000000000 */
/*05d0*/ LDS.128 R16, [0x110] ; /* 0x00011000ff107984 */
/* 0x000e640000000c00 */
/*05e0*/ FADD R13, R12, R13 ; /* 0x0000000d0c0d7221 */
/* 0x000fc80000000000 */
/*05f0*/ FADD R14, R13, R14 ; /* 0x0000000e0d0e7221 */
/* 0x000fc80000000000 */
/*0600*/ FADD R15, R14, R15 ; /* 0x0000000f0e0f7221 */
/* 0x000fc80000000000 */
/*0610*/ FADD R4, R15, R4 ; /* 0x000000040f047221 */
/* 0x004fe40000000000 */
/*0620*/ LDS.128 R12, [0x120] ; /* 0x00012000ff0c7984 */
/* 0x000ea40000000c00 */
/*0630*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x000fc80000000000 */
/*0640*/ FADD R6, R5, R6 ; /* 0x0000000605067221 */
/* 0x000fc80000000000 */
/*0650*/ FADD R7, R6, R7 ; /* 0x0000000706077221 */
/* 0x000fc80000000000 */
/*0660*/ FADD R8, R7, R8 ; /* 0x0000000807087221 */
/* 0x001fe40000000000 */
/*0670*/ LDS.128 R4, [0x130] ; /* 0x00013000ff047984 */
/* 0x000e240000000c00 */
/*0680*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x000fc80000000000 */
/*0690*/ FADD R10, R9, R10 ; /* 0x0000000a090a7221 */
/* 0x000fc80000000000 */
/*06a0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x000fc80000000000 */
/*06b0*/ FADD R16, R11, R16 ; /* 0x000000100b107221 */
/* 0x002fe40000000000 */
/*06c0*/ LDS.128 R8, [0x140] ; /* 0x00014000ff087984 */
/* 0x000e640000000c00 */
/*06d0*/ FADD R17, R16, R17 ; /* 0x0000001110117221 */
/* 0x000fc80000000000 */
/*06e0*/ FADD R18, R17, R18 ; /* 0x0000001211127221 */
/* 0x000fc80000000000 */
/*06f0*/ FADD R19, R18, R19 ; /* 0x0000001312137221 */
/* 0x000fc80000000000 */
/*0700*/ FADD R12, R19, R12 ; /* 0x0000000c130c7221 */
/* 0x004fe40000000000 */
/*0710*/ LDS.128 R16, [0x150] ; /* 0x00015000ff107984 */
/* 0x000ea40000000c00 */
/*0720*/ FADD R13, R12, R13 ; /* 0x0000000d0c0d7221 */
/* 0x000fc80000000000 */
/*0730*/ FADD R14, R13, R14 ; /* 0x0000000e0d0e7221 */
/* 0x000fc80000000000 */
/*0740*/ FADD R15, R14, R15 ; /* 0x0000000f0e0f7221 */
/* 0x000fc80000000000 */
/*0750*/ FADD R4, R15, R4 ; /* 0x000000040f047221 */
/* 0x001fe40000000000 */
/*0760*/ LDS.128 R12, [0x160] ; /* 0x00016000ff0c7984 */
/* 0x000e240000000c00 */
/*0770*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x000fc80000000000 */
/*0780*/ FADD R6, R5, R6 ; /* 0x0000000605067221 */
/* 0x000fc80000000000 */
/*0790*/ FADD R7, R6, R7 ; /* 0x0000000706077221 */
/* 0x000fc80000000000 */
/*07a0*/ FADD R8, R7, R8 ; /* 0x0000000807087221 */
/* 0x002fe40000000000 */
/*07b0*/ LDS.128 R4, [0x170] ; /* 0x00017000ff047984 */
/* 0x000e640000000c00 */
/*07c0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x000fc80000000000 */
/*07d0*/ FADD R10, R9, R10 ; /* 0x0000000a090a7221 */
/* 0x000fc80000000000 */
/*07e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x000fc80000000000 */
/*07f0*/ FADD R16, R11, R16 ; /* 0x000000100b107221 */
/* 0x004fe40000000000 */
/*0800*/ LDS.128 R8, [0x180] ; /* 0x00018000ff087984 */
/* 0x000ea40000000c00 */
/*0810*/ FADD R17, R16, R17 ; /* 0x0000001110117221 */
/* 0x000fc80000000000 */
/*0820*/ FADD R18, R17, R18 ; /* 0x0000001211127221 */
/* 0x000fc80000000000 */
/*0830*/ FADD R19, R18, R19 ; /* 0x0000001312137221 */
/* 0x000fc80000000000 */
/*0840*/ FADD R12, R19, R12 ; /* 0x0000000c130c7221 */
/* 0x001fe40000000000 */
/*0850*/ LDS.128 R16, [0x190] ; /* 0x00019000ff107984 */
/* 0x000e240000000c00 */
/*0860*/ FADD R13, R12, R13 ; /* 0x0000000d0c0d7221 */
/* 0x000fc80000000000 */
/*0870*/ FADD R14, R13, R14 ; /* 0x0000000e0d0e7221 */
/* 0x000fc80000000000 */
/*0880*/ FADD R15, R14, R15 ; /* 0x0000000f0e0f7221 */
/* 0x000fc80000000000 */
/*0890*/ FADD R4, R15, R4 ; /* 0x000000040f047221 */
/* 0x002fe40000000000 */
/*08a0*/ LDS.128 R12, [0x1a0] ; /* 0x0001a000ff0c7984 */
/* 0x000e640000000c00 */
/*08b0*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x000fc80000000000 */
/*08c0*/ FADD R6, R5, R6 ; /* 0x0000000605067221 */
/* 0x000fc80000000000 */
/*08d0*/ FADD R7, R6, R7 ; /* 0x0000000706077221 */
/* 0x000fc80000000000 */
/*08e0*/ FADD R8, R7, R8 ; /* 0x0000000807087221 */
/* 0x004fe40000000000 */
/*08f0*/ LDS.128 R4, [0x1b0] ; /* 0x0001b000ff047984 */
/* 0x000ea40000000c00 */
/*0900*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x000fc80000000000 */
/*0910*/ FADD R10, R9, R10 ; /* 0x0000000a090a7221 */
/* 0x000fc80000000000 */
/*0920*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x000fc80000000000 */
/*0930*/ FADD R16, R11, R16 ; /* 0x000000100b107221 */
/* 0x001fe40000000000 */
/*0940*/ LDS.128 R8, [0x1c0] ; /* 0x0001c000ff087984 */
/* 0x000e240000000c00 */
/*0950*/ FADD R17, R16, R17 ; /* 0x0000001110117221 */
/* 0x000fc80000000000 */
/*0960*/ FADD R18, R17, R18 ; /* 0x0000001211127221 */
/* 0x000fc80000000000 */
/*0970*/ FADD R19, R18, R19 ; /* 0x0000001312137221 */
/* 0x000fc80000000000 */
/*0980*/ FADD R12, R19, R12 ; /* 0x0000000c130c7221 */
/* 0x002fe40000000000 */
/*0990*/ LDS.128 R16, [0x1d0] ; /* 0x0001d000ff107984 */
/* 0x000e640000000c00 */
/*09a0*/ FADD R13, R12, R13 ; /* 0x0000000d0c0d7221 */
/* 0x000fc80000000000 */
/*09b0*/ FADD R14, R13, R14 ; /* 0x0000000e0d0e7221 */
/* 0x000fc80000000000 */
/*09c0*/ FADD R15, R14, R15 ; /* 0x0000000f0e0f7221 */
/* 0x000fc80000000000 */
/*09d0*/ FADD R4, R15, R4 ; /* 0x000000040f047221 */
/* 0x004fe40000000000 */
/*09e0*/ LDS.128 R12, [0x1e0] ; /* 0x0001e000ff0c7984 */
/* 0x000ea40000000c00 */
/*09f0*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x000fc80000000000 */
/*0a00*/ FADD R6, R5, R6 ; /* 0x0000000605067221 */
/* 0x000fc80000000000 */
/*0a10*/ FADD R7, R6, R7 ; /* 0x0000000706077221 */
/* 0x000fc80000000000 */
/*0a20*/ FADD R8, R7, R8 ; /* 0x0000000807087221 */
/* 0x001fe40000000000 */
/*0a30*/ LDS.128 R4, [0x1f0] ; /* 0x0001f000ff047984 */
/* 0x000e240000000c00 */
/*0a40*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x000fc80000000000 */
/*0a50*/ FADD R10, R9, R10 ; /* 0x0000000a090a7221 */
/* 0x000fc80000000000 */
/*0a60*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x000fc80000000000 */
/*0a70*/ FADD R16, R11, R16 ; /* 0x000000100b107221 */
/* 0x002fc80000000000 */
/*0a80*/ FADD R17, R16, R17 ; /* 0x0000001110117221 */
/* 0x000fc80000000000 */
/*0a90*/ FADD R18, R17, R18 ; /* 0x0000001211127221 */
/* 0x000fc80000000000 */
/*0aa0*/ FADD R19, R18, R19 ; /* 0x0000001312137221 */
/* 0x000fc80000000000 */
/*0ab0*/ FADD R12, R19, R12 ; /* 0x0000000c130c7221 */
/* 0x004fc80000000000 */
/*0ac0*/ FADD R13, R12, R13 ; /* 0x0000000d0c0d7221 */
/* 0x000fc80000000000 */
/*0ad0*/ FADD R14, R13, R14 ; /* 0x0000000e0d0e7221 */
/* 0x000fc80000000000 */
/*0ae0*/ FADD R15, R14, R15 ; /* 0x0000000f0e0f7221 */
/* 0x000fc80000000000 */
/*0af0*/ FADD R4, R15, R4 ; /* 0x000000040f047221 */
/* 0x001fc80000000000 */
/*0b00*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x000fc80000000000 */
/*0b10*/ FADD R6, R5, R6 ; /* 0x0000000605067221 */
/* 0x000fc80000000000 */
/*0b20*/ FADD R7, R6, R7 ; /* 0x0000000706077221 */
/* 0x000fca0000000000 */
/*0b30*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], R7 ; /* 0x000000070200798e */
/* 0x000fe2000c10e784 */
/*0b40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b50*/ BRA 0xb50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#define N 1<<7
#define THREADS_PER_BLOCK 1024
__global__ void dot(float *a, float *b, float *c) {
__shared__ float temp[THREADS_PER_BLOCK];
int index = threadIdx.x + blockIdx.x * blockDim.x;
if (index >= N) return;
temp[threadIdx.x] = a[index] * b[index];
__syncthreads();
if (0 == threadIdx.x) {
float sum = 0.0;
int max = THREADS_PER_BLOCK;
if (N < max) max = N;
for (int i = 0; i < max; i++) {
sum += temp[i];
}
//c[0] = sum;
atomicAdd(c, sum);
}
}
void random_floats(float *a, float size)
{
int i;
for (i=0; i<size; i++)
a[i] = i;
return;
}
int main(void) {
int num_SMs;
int devId = 0; // Unique GPU
cudaDeviceGetAttribute(&num_SMs, cudaDevAttrMultiProcessorCount, devId); // Y devId?
printf("Number of SMs: %d\n", num_SMs);
int i;
float result;
float *a, *b, *c; // host copies of a, b, c
float *dev_a, *dev_b, *dev_c; // device copies of a, b, c
int size = N * sizeof(float); // we need space for N floats
// allocate device copies of a, b, c
cudaMalloc( (void**)&dev_a, size );
cudaMalloc( (void**)&dev_b, size );
cudaMalloc( (void**)&dev_c, sizeof(float) );
a = (float*)malloc( size );
b = (float*)malloc( size );
c = (float*)malloc( sizeof(float) );
random_floats( a, N );
random_floats( b, N );
/*
printf("a = ");
for (i=0; i<N; i++) printf("%d, ", a[i]);
printf("\n");
printf("b = ");
for (i=0; i<N; i++) printf("%d, ", b[i]);
printf("\n");
*/
result = 0;
for (i=0; i<N; i++) result += a[i] * b[i];
*c = 0;
// copy inputs to device
cudaMemcpy( dev_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy( dev_b, b, size, cudaMemcpyHostToDevice);
int blocks = (int)(N/THREADS_PER_BLOCK) + 1; // ceil(...)
//if(blocks<1) blocks=1;
// launch dot() kernel
dot <<< blocks, THREADS_PER_BLOCK >>> (dev_a, dev_b, dev_c);
// copy device result back to host copy of c
cudaMemcpy(c, dev_c, sizeof(float) , cudaMemcpyDeviceToHost);
printf("*c = %.2f\n", *c);
printf("result = %.2f\n", result);
free(a); free(b); free(c);
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
return 0;
} | .file "tmpxft_001a2db7_00000000-6_my-atomic-5.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13random_floatsPff
.type _Z13random_floatsPff, @function
_Z13random_floatsPff:
.LFB2057:
.cfi_startproc
endbr64
movl $1, %eax
pxor %xmm1, %xmm1
comiss %xmm1, %xmm0
jbe .L3
.L6:
movss %xmm1, -4(%rdi,%rax,4)
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
addq $1, %rax
comiss %xmm1, %xmm0
ja .L6
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z13random_floatsPff, .-_Z13random_floatsPff
.globl _Z26__device_stub__Z3dotPfS_S_PfS_S_
.type _Z26__device_stub__Z3dotPfS_S_PfS_S_, @function
_Z26__device_stub__Z3dotPfS_S_PfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3dotPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z26__device_stub__Z3dotPfS_S_PfS_S_, .-_Z26__device_stub__Z3dotPfS_S_PfS_S_
.globl _Z3dotPfS_S_
.type _Z3dotPfS_S_, @function
_Z3dotPfS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3dotPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z3dotPfS_S_, .-_Z3dotPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Number of SMs: %d\n"
.LC3:
.string "*c = %.2f\n"
.LC4:
.string "result = %.2f\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 20(%rsp), %rdi
movl $0, %edx
movl $16, %esi
call cudaDeviceGetAttribute@PLT
movl 20(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 24(%rsp), %rdi
movl $268435456, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $268435456, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $268435456, %edi
call malloc@PLT
movq %rax, %rbp
movl $268435456, %edi
call malloc@PLT
movq %rax, %rbx
movl $4, %edi
call malloc@PLT
movq %rax, %r12
movss .LC2(%rip), %xmm0
movq %rbp, %rdi
call _Z13random_floatsPff
movss .LC2(%rip), %xmm0
movq %rbx, %rdi
call _Z13random_floatsPff
movl $0, %eax
movl $0x00000000, 12(%rsp)
.L19:
movss 0(%rbp,%rax), %xmm0
mulss (%rbx,%rax), %xmm0
addss 12(%rsp), %xmm0
movss %xmm0, 12(%rsp)
addq $4, %rax
cmpq $512, %rax
jne .L19
movl $0x00000000, (%r12)
movl $1, %ecx
movl $268435456, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $268435456, %edx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $2, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movl $2, %ecx
movl $4, %edx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z26__device_stub__Z3dotPfS_S_PfS_S_
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z3dotPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z3dotPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1124073472
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#define N 1<<7
#define THREADS_PER_BLOCK 1024
__global__ void dot(float *a, float *b, float *c) {
__shared__ float temp[THREADS_PER_BLOCK];
int index = threadIdx.x + blockIdx.x * blockDim.x;
if (index >= N) return;
temp[threadIdx.x] = a[index] * b[index];
__syncthreads();
if (0 == threadIdx.x) {
float sum = 0.0;
int max = THREADS_PER_BLOCK;
if (N < max) max = N;
for (int i = 0; i < max; i++) {
sum += temp[i];
}
//c[0] = sum;
atomicAdd(c, sum);
}
}
void random_floats(float *a, float size)
{
int i;
for (i=0; i<size; i++)
a[i] = i;
return;
}
int main(void) {
int num_SMs;
int devId = 0; // Unique GPU
cudaDeviceGetAttribute(&num_SMs, cudaDevAttrMultiProcessorCount, devId); // Y devId?
printf("Number of SMs: %d\n", num_SMs);
int i;
float result;
float *a, *b, *c; // host copies of a, b, c
float *dev_a, *dev_b, *dev_c; // device copies of a, b, c
int size = N * sizeof(float); // we need space for N floats
// allocate device copies of a, b, c
cudaMalloc( (void**)&dev_a, size );
cudaMalloc( (void**)&dev_b, size );
cudaMalloc( (void**)&dev_c, sizeof(float) );
a = (float*)malloc( size );
b = (float*)malloc( size );
c = (float*)malloc( sizeof(float) );
random_floats( a, N );
random_floats( b, N );
/*
printf("a = ");
for (i=0; i<N; i++) printf("%d, ", a[i]);
printf("\n");
printf("b = ");
for (i=0; i<N; i++) printf("%d, ", b[i]);
printf("\n");
*/
result = 0;
for (i=0; i<N; i++) result += a[i] * b[i];
*c = 0;
// copy inputs to device
cudaMemcpy( dev_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy( dev_b, b, size, cudaMemcpyHostToDevice);
int blocks = (int)(N/THREADS_PER_BLOCK) + 1; // ceil(...)
//if(blocks<1) blocks=1;
// launch dot() kernel
dot <<< blocks, THREADS_PER_BLOCK >>> (dev_a, dev_b, dev_c);
// copy device result back to host copy of c
cudaMemcpy(c, dev_c, sizeof(float) , cudaMemcpyDeviceToHost);
printf("*c = %.2f\n", *c);
printf("result = %.2f\n", result);
free(a); free(b); free(c);
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#define N 1<<7
#define THREADS_PER_BLOCK 1024
__global__ void dot(float *a, float *b, float *c) {
__shared__ float temp[THREADS_PER_BLOCK];
int index = threadIdx.x + blockIdx.x * blockDim.x;
if (index >= N) return;
temp[threadIdx.x] = a[index] * b[index];
__syncthreads();
if (0 == threadIdx.x) {
float sum = 0.0;
int max = THREADS_PER_BLOCK;
if (N < max) max = N;
for (int i = 0; i < max; i++) {
sum += temp[i];
}
//c[0] = sum;
atomicAdd(c, sum);
}
}
void random_floats(float *a, float size)
{
int i;
for (i=0; i<size; i++)
a[i] = i;
return;
}
int main(void) {
int num_SMs;
int devId = 0; // Unique GPU
hipDeviceGetAttribute(&num_SMs, hipDeviceAttributeMultiprocessorCount, devId); // Y devId?
printf("Number of SMs: %d\n", num_SMs);
int i;
float result;
float *a, *b, *c; // host copies of a, b, c
float *dev_a, *dev_b, *dev_c; // device copies of a, b, c
int size = N * sizeof(float); // we need space for N floats
// allocate device copies of a, b, c
hipMalloc( (void**)&dev_a, size );
hipMalloc( (void**)&dev_b, size );
hipMalloc( (void**)&dev_c, sizeof(float) );
a = (float*)malloc( size );
b = (float*)malloc( size );
c = (float*)malloc( sizeof(float) );
random_floats( a, N );
random_floats( b, N );
/*
printf("a = ");
for (i=0; i<N; i++) printf("%d, ", a[i]);
printf("\n");
printf("b = ");
for (i=0; i<N; i++) printf("%d, ", b[i]);
printf("\n");
*/
result = 0;
for (i=0; i<N; i++) result += a[i] * b[i];
*c = 0;
// copy inputs to device
hipMemcpy( dev_a, a, size, hipMemcpyHostToDevice);
hipMemcpy( dev_b, b, size, hipMemcpyHostToDevice);
int blocks = (int)(N/THREADS_PER_BLOCK) + 1; // ceil(...)
//if(blocks<1) blocks=1;
// launch dot() kernel
dot <<< blocks, THREADS_PER_BLOCK >>> (dev_a, dev_b, dev_c);
// copy device result back to host copy of c
hipMemcpy(c, dev_c, sizeof(float) , hipMemcpyDeviceToHost);
printf("*c = %.2f\n", *c);
printf("result = %.2f\n", result);
free(a); free(b); free(c);
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#define N 1<<7
#define THREADS_PER_BLOCK 1024
__global__ void dot(float *a, float *b, float *c) {
__shared__ float temp[THREADS_PER_BLOCK];
int index = threadIdx.x + blockIdx.x * blockDim.x;
if (index >= N) return;
temp[threadIdx.x] = a[index] * b[index];
__syncthreads();
if (0 == threadIdx.x) {
float sum = 0.0;
int max = THREADS_PER_BLOCK;
if (N < max) max = N;
for (int i = 0; i < max; i++) {
sum += temp[i];
}
//c[0] = sum;
atomicAdd(c, sum);
}
}
void random_floats(float *a, float size)
{
int i;
for (i=0; i<size; i++)
a[i] = i;
return;
}
int main(void) {
int num_SMs;
int devId = 0; // Unique GPU
hipDeviceGetAttribute(&num_SMs, hipDeviceAttributeMultiprocessorCount, devId); // Y devId?
printf("Number of SMs: %d\n", num_SMs);
int i;
float result;
float *a, *b, *c; // host copies of a, b, c
float *dev_a, *dev_b, *dev_c; // device copies of a, b, c
int size = N * sizeof(float); // we need space for N floats
// allocate device copies of a, b, c
hipMalloc( (void**)&dev_a, size );
hipMalloc( (void**)&dev_b, size );
hipMalloc( (void**)&dev_c, sizeof(float) );
a = (float*)malloc( size );
b = (float*)malloc( size );
c = (float*)malloc( sizeof(float) );
random_floats( a, N );
random_floats( b, N );
/*
printf("a = ");
for (i=0; i<N; i++) printf("%d, ", a[i]);
printf("\n");
printf("b = ");
for (i=0; i<N; i++) printf("%d, ", b[i]);
printf("\n");
*/
result = 0;
for (i=0; i<N; i++) result += a[i] * b[i];
*c = 0;
// copy inputs to device
hipMemcpy( dev_a, a, size, hipMemcpyHostToDevice);
hipMemcpy( dev_b, b, size, hipMemcpyHostToDevice);
int blocks = (int)(N/THREADS_PER_BLOCK) + 1; // ceil(...)
//if(blocks<1) blocks=1;
// launch dot() kernel
dot <<< blocks, THREADS_PER_BLOCK >>> (dev_a, dev_b, dev_c);
// copy device result back to host copy of c
hipMemcpy(c, dev_c, sizeof(float) , hipMemcpyDeviceToHost);
printf("*c = %.2f\n", *c);
printf("result = %.2f\n", result);
free(a); free(b); free(c);
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3dotPfS_S_
.globl _Z3dotPfS_S_
.p2align 8
.type _Z3dotPfS_S_,@function
_Z3dotPfS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x80, v1
s_cbranch_execz .LBB0_7
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v0
global_load_b32 v3, v[3:4], off
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_dual_mul_f32 v1, v3, v1 :: v_dual_lshlrev_b32 v2, 2, v0
ds_store_b32 v2, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v0, 0
.LBB0_3:
v_mov_b32_e32 v1, s2
s_add_i32 s2, s2, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_eq_i32 s2, 0x200
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v0, v1
s_cbranch_scc0 .LBB0_3
s_mov_b32 s3, exec_lo
s_mov_b32 s2, 0
v_mbcnt_lo_u32_b32 v1, s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, 0, v1
s_and_b32 s4, exec_lo, vcc_lo
s_mov_b32 exec_lo, s4
s_cbranch_execz .LBB0_7
s_load_b64 s[0:1], s[0:1], 0x10
s_bcnt1_i32_b32 s3, s3
v_mov_b32_e32 v3, 0
v_cvt_f32_ubyte0_e32 v1, s3
s_waitcnt lgkmcnt(0)
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_dual_mul_f32 v2, v0, v1 :: v_dual_mov_b32 v1, s4
.LBB0_6:
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v0, v1, v2
global_atomic_cmpswap_b32 v0, v3, v[0:1], s[0:1] glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v0, v1
v_mov_b32_e32 v1, v0
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_6
.LBB0_7:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3dotPfS_S_
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3dotPfS_S_, .Lfunc_end0-_Z3dotPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3dotPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3dotPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#define N 1<<7
#define THREADS_PER_BLOCK 1024
__global__ void dot(float *a, float *b, float *c) {
__shared__ float temp[THREADS_PER_BLOCK];
int index = threadIdx.x + blockIdx.x * blockDim.x;
if (index >= N) return;
temp[threadIdx.x] = a[index] * b[index];
__syncthreads();
if (0 == threadIdx.x) {
float sum = 0.0;
int max = THREADS_PER_BLOCK;
if (N < max) max = N;
for (int i = 0; i < max; i++) {
sum += temp[i];
}
//c[0] = sum;
atomicAdd(c, sum);
}
}
void random_floats(float *a, float size)
{
int i;
for (i=0; i<size; i++)
a[i] = i;
return;
}
int main(void) {
int num_SMs;
int devId = 0; // Unique GPU
hipDeviceGetAttribute(&num_SMs, hipDeviceAttributeMultiprocessorCount, devId); // Y devId?
printf("Number of SMs: %d\n", num_SMs);
int i;
float result;
float *a, *b, *c; // host copies of a, b, c
float *dev_a, *dev_b, *dev_c; // device copies of a, b, c
int size = N * sizeof(float); // we need space for N floats
// allocate device copies of a, b, c
hipMalloc( (void**)&dev_a, size );
hipMalloc( (void**)&dev_b, size );
hipMalloc( (void**)&dev_c, sizeof(float) );
a = (float*)malloc( size );
b = (float*)malloc( size );
c = (float*)malloc( sizeof(float) );
random_floats( a, N );
random_floats( b, N );
/*
printf("a = ");
for (i=0; i<N; i++) printf("%d, ", a[i]);
printf("\n");
printf("b = ");
for (i=0; i<N; i++) printf("%d, ", b[i]);
printf("\n");
*/
result = 0;
for (i=0; i<N; i++) result += a[i] * b[i];
*c = 0;
// copy inputs to device
hipMemcpy( dev_a, a, size, hipMemcpyHostToDevice);
hipMemcpy( dev_b, b, size, hipMemcpyHostToDevice);
int blocks = (int)(N/THREADS_PER_BLOCK) + 1; // ceil(...)
//if(blocks<1) blocks=1;
// launch dot() kernel
dot <<< blocks, THREADS_PER_BLOCK >>> (dev_a, dev_b, dev_c);
// copy device result back to host copy of c
hipMemcpy(c, dev_c, sizeof(float) , hipMemcpyDeviceToHost);
printf("*c = %.2f\n", *c);
printf("result = %.2f\n", result);
free(a); free(b); free(c);
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
return 0;
} | .text
.file "my-atomic-5.hip"
.globl _Z18__device_stub__dotPfS_S_ # -- Begin function _Z18__device_stub__dotPfS_S_
.p2align 4, 0x90
.type _Z18__device_stub__dotPfS_S_,@function
_Z18__device_stub__dotPfS_S_: # @_Z18__device_stub__dotPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3dotPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__dotPfS_S_, .Lfunc_end0-_Z18__device_stub__dotPfS_S_
.cfi_endproc
# -- End function
.globl _Z13random_floatsPff # -- Begin function _Z13random_floatsPff
.p2align 4, 0x90
.type _Z13random_floatsPff,@function
_Z13random_floatsPff: # @_Z13random_floatsPff
.cfi_startproc
# %bb.0:
xorps %xmm1, %xmm1
ucomiss %xmm1, %xmm0
jbe .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss %xmm1, (%rdi,%rax,4)
incq %rax
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
ucomiss %xmm1, %xmm0
ja .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z13random_floatsPff, .Lfunc_end1-_Z13random_floatsPff
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $136, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 36(%rsp), %rdi
xorl %r12d, %r12d
movl $63, %esi
xorl %edx, %edx
callq hipDeviceGetAttribute
movl 36(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 24(%rsp), %rdi
movl $268435456, %esi # imm = 0x10000000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $268435456, %esi # imm = 0x10000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movl $268435456, %edi # imm = 0x10000000
callq malloc
movq %rax, %rbx
movl $268435456, %edi # imm = 0x10000000
callq malloc
movq %rax, %r14
movl $4, %edi
callq malloc
movq %rax, %r15
xorps %xmm0, %xmm0
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss %xmm0, (%rbx,%r12,4)
incq %r12
xorps %xmm0, %xmm0
cvtsi2ss %r12d, %xmm0
cmpq $128, %r12
jne .LBB2_1
# %bb.2: # %.lr.ph.i28.preheader
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i28
# =>This Inner Loop Header: Depth=1
movss %xmm0, (%r14,%rax,4)
incq %rax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
cmpq $128, %rax
jne .LBB2_3
# %bb.4: # %_Z13random_floatsPff.exit31.preheader
xorps %xmm1, %xmm1
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_5: # %_Z13random_floatsPff.exit31
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%r14,%rax,4), %xmm0
addss %xmm0, %xmm1
incq %rax
cmpq $128, %rax
jne .LBB2_5
# %bb.6:
movss %xmm1, 32(%rsp) # 4-byte Spill
movl $0, (%r15)
movq 24(%rsp), %rdi
movl $268435456, %edx # imm = 0x10000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $268435456, %edx # imm = 0x10000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 1022(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3dotPfS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
movq 8(%rsp), %rsi
movl $4, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movss (%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movss 32(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3dotPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3dotPfS_S_,@object # @_Z3dotPfS_S_
.section .rodata,"a",@progbits
.globl _Z3dotPfS_S_
.p2align 3, 0x0
_Z3dotPfS_S_:
.quad _Z18__device_stub__dotPfS_S_
.size _Z3dotPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Number of SMs: %d\n"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "*c = %.2f\n"
.size .L.str.1, 15
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "result = %.2f\n"
.size .L.str.2, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3dotPfS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__dotPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3dotPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3dotPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R7 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0207 */
/*0040*/ ISETP.GT.AND P0, PT, R2, 0x7f, PT ; /* 0x0000007f0200780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R2, R3, c[0x0][0x168] ; /* 0x00005a0002047625 */
/* 0x000fc800078e0203 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe400078e0203 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00d0*/ FMUL R0, R4, R3 ; /* 0x0000000304007220 */
/* 0x004fca0000400000 */
/*00e0*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x0001e80000004800 */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0100*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0110*/ LDS.128 R8, [RZ] ; /* 0x00000000ff087984 */
/* 0x001e220000000c00 */
/*0120*/ MOV R2, c[0x0][0x170] ; /* 0x00005c0000027a02 */
/* 0x000fc40000000f00 */
/*0130*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fe20000000f00 */
/*0140*/ LDS.128 R16, [0x10] ; /* 0x00001000ff107984 */
/* 0x000e680000000c00 */
/*0150*/ LDS.128 R12, [0x20] ; /* 0x00002000ff0c7984 */
/* 0x000ea80000000c00 */
/*0160*/ LDS.128 R4, [0x30] ; /* 0x00003000ff047984 */
/* 0x000ee20000000c00 */
/*0170*/ FADD R8, RZ, R8 ; /* 0x00000008ff087221 */
/* 0x001fc80000000000 */
/*0180*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x000fc80000000000 */
/*0190*/ FADD R10, R9, R10 ; /* 0x0000000a090a7221 */
/* 0x000fc80000000000 */
/*01a0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x000fc80000000000 */
/*01b0*/ FADD R16, R11, R16 ; /* 0x000000100b107221 */
/* 0x002fe40000000000 */
/*01c0*/ LDS.128 R8, [0x40] ; /* 0x00004000ff087984 */
/* 0x000e240000000c00 */
/*01d0*/ FADD R17, R16, R17 ; /* 0x0000001110117221 */
/* 0x000fc80000000000 */
/*01e0*/ FADD R18, R17, R18 ; /* 0x0000001211127221 */
/* 0x000fc80000000000 */
/*01f0*/ FADD R19, R18, R19 ; /* 0x0000001312137221 */
/* 0x000fc80000000000 */
/*0200*/ FADD R12, R19, R12 ; /* 0x0000000c130c7221 */
/* 0x004fe40000000000 */
/*0210*/ LDS.128 R16, [0x50] ; /* 0x00005000ff107984 */
/* 0x000e640000000c00 */
/*0220*/ FADD R13, R12, R13 ; /* 0x0000000d0c0d7221 */
/* 0x000fc80000000000 */
/*0230*/ FADD R14, R13, R14 ; /* 0x0000000e0d0e7221 */
/* 0x000fc80000000000 */
/*0240*/ FADD R15, R14, R15 ; /* 0x0000000f0e0f7221 */
/* 0x000fc80000000000 */
/*0250*/ FADD R4, R15, R4 ; /* 0x000000040f047221 */
/* 0x008fe40000000000 */
/*0260*/ LDS.128 R12, [0x60] ; /* 0x00006000ff0c7984 */
/* 0x000ea40000000c00 */
/*0270*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x000fc80000000000 */
/*0280*/ FADD R6, R5, R6 ; /* 0x0000000605067221 */
/* 0x000fc80000000000 */
/*0290*/ FADD R7, R6, R7 ; /* 0x0000000706077221 */
/* 0x000fc80000000000 */
/*02a0*/ FADD R8, R7, R8 ; /* 0x0000000807087221 */
/* 0x001fe40000000000 */
/*02b0*/ LDS.128 R4, [0x70] ; /* 0x00007000ff047984 */
/* 0x000e240000000c00 */
/*02c0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x000fc80000000000 */
/*02d0*/ FADD R10, R9, R10 ; /* 0x0000000a090a7221 */
/* 0x000fc80000000000 */
/*02e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x000fc80000000000 */
/*02f0*/ FADD R16, R11, R16 ; /* 0x000000100b107221 */
/* 0x002fe40000000000 */
/*0300*/ LDS.128 R8, [0x80] ; /* 0x00008000ff087984 */
/* 0x000e640000000c00 */
/*0310*/ FADD R17, R16, R17 ; /* 0x0000001110117221 */
/* 0x000fc80000000000 */
/*0320*/ FADD R18, R17, R18 ; /* 0x0000001211127221 */
/* 0x000fc80000000000 */
/*0330*/ FADD R19, R18, R19 ; /* 0x0000001312137221 */
/* 0x000fc80000000000 */
/*0340*/ FADD R12, R19, R12 ; /* 0x0000000c130c7221 */
/* 0x004fe40000000000 */
/*0350*/ LDS.128 R16, [0x90] ; /* 0x00009000ff107984 */
/* 0x000ea40000000c00 */
/*0360*/ FADD R13, R12, R13 ; /* 0x0000000d0c0d7221 */
/* 0x000fc80000000000 */
/*0370*/ FADD R14, R13, R14 ; /* 0x0000000e0d0e7221 */
/* 0x000fc80000000000 */
/*0380*/ FADD R15, R14, R15 ; /* 0x0000000f0e0f7221 */
/* 0x000fc80000000000 */
/*0390*/ FADD R4, R15, R4 ; /* 0x000000040f047221 */
/* 0x001fe40000000000 */
/*03a0*/ LDS.128 R12, [0xa0] ; /* 0x0000a000ff0c7984 */
/* 0x000e240000000c00 */
/*03b0*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x000fc80000000000 */
/*03c0*/ FADD R6, R5, R6 ; /* 0x0000000605067221 */
/* 0x000fc80000000000 */
/*03d0*/ FADD R7, R6, R7 ; /* 0x0000000706077221 */
/* 0x000fc80000000000 */
/*03e0*/ FADD R8, R7, R8 ; /* 0x0000000807087221 */
/* 0x002fe40000000000 */
/*03f0*/ LDS.128 R4, [0xb0] ; /* 0x0000b000ff047984 */
/* 0x000e640000000c00 */
/*0400*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x000fc80000000000 */
/*0410*/ FADD R10, R9, R10 ; /* 0x0000000a090a7221 */
/* 0x000fc80000000000 */
/*0420*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x000fc80000000000 */
/*0430*/ FADD R16, R11, R16 ; /* 0x000000100b107221 */
/* 0x004fe40000000000 */
/*0440*/ LDS.128 R8, [0xc0] ; /* 0x0000c000ff087984 */
/* 0x000ea40000000c00 */
/*0450*/ FADD R17, R16, R17 ; /* 0x0000001110117221 */
/* 0x000fc80000000000 */
/*0460*/ FADD R18, R17, R18 ; /* 0x0000001211127221 */
/* 0x000fc80000000000 */
/*0470*/ FADD R19, R18, R19 ; /* 0x0000001312137221 */
/* 0x000fc80000000000 */
/*0480*/ FADD R12, R19, R12 ; /* 0x0000000c130c7221 */
/* 0x001fe40000000000 */
/*0490*/ LDS.128 R16, [0xd0] ; /* 0x0000d000ff107984 */
/* 0x000e240000000c00 */
/*04a0*/ FADD R13, R12, R13 ; /* 0x0000000d0c0d7221 */
/* 0x000fc80000000000 */
/*04b0*/ FADD R14, R13, R14 ; /* 0x0000000e0d0e7221 */
/* 0x000fc80000000000 */
/*04c0*/ FADD R15, R14, R15 ; /* 0x0000000f0e0f7221 */
/* 0x000fc80000000000 */
/*04d0*/ FADD R4, R15, R4 ; /* 0x000000040f047221 */
/* 0x002fe40000000000 */
/*04e0*/ LDS.128 R12, [0xe0] ; /* 0x0000e000ff0c7984 */
/* 0x000e640000000c00 */
/*04f0*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x000fc80000000000 */
/*0500*/ FADD R6, R5, R6 ; /* 0x0000000605067221 */
/* 0x000fc80000000000 */
/*0510*/ FADD R7, R6, R7 ; /* 0x0000000706077221 */
/* 0x000fc80000000000 */
/*0520*/ FADD R8, R7, R8 ; /* 0x0000000807087221 */
/* 0x004fe40000000000 */
/*0530*/ LDS.128 R4, [0xf0] ; /* 0x0000f000ff047984 */
/* 0x000ea40000000c00 */
/*0540*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x000fc80000000000 */
/*0550*/ FADD R10, R9, R10 ; /* 0x0000000a090a7221 */
/* 0x000fc80000000000 */
/*0560*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x000fc80000000000 */
/*0570*/ FADD R16, R11, R16 ; /* 0x000000100b107221 */
/* 0x001fe40000000000 */
/*0580*/ LDS.128 R8, [0x100] ; /* 0x00010000ff087984 */
/* 0x000e240000000c00 */
/*0590*/ FADD R17, R16, R17 ; /* 0x0000001110117221 */
/* 0x000fc80000000000 */
/*05a0*/ FADD R18, R17, R18 ; /* 0x0000001211127221 */
/* 0x000fc80000000000 */
/*05b0*/ FADD R19, R18, R19 ; /* 0x0000001312137221 */
/* 0x000fc80000000000 */
/*05c0*/ FADD R12, R19, R12 ; /* 0x0000000c130c7221 */
/* 0x002fe40000000000 */
/*05d0*/ LDS.128 R16, [0x110] ; /* 0x00011000ff107984 */
/* 0x000e640000000c00 */
/*05e0*/ FADD R13, R12, R13 ; /* 0x0000000d0c0d7221 */
/* 0x000fc80000000000 */
/*05f0*/ FADD R14, R13, R14 ; /* 0x0000000e0d0e7221 */
/* 0x000fc80000000000 */
/*0600*/ FADD R15, R14, R15 ; /* 0x0000000f0e0f7221 */
/* 0x000fc80000000000 */
/*0610*/ FADD R4, R15, R4 ; /* 0x000000040f047221 */
/* 0x004fe40000000000 */
/*0620*/ LDS.128 R12, [0x120] ; /* 0x00012000ff0c7984 */
/* 0x000ea40000000c00 */
/*0630*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x000fc80000000000 */
/*0640*/ FADD R6, R5, R6 ; /* 0x0000000605067221 */
/* 0x000fc80000000000 */
/*0650*/ FADD R7, R6, R7 ; /* 0x0000000706077221 */
/* 0x000fc80000000000 */
/*0660*/ FADD R8, R7, R8 ; /* 0x0000000807087221 */
/* 0x001fe40000000000 */
/*0670*/ LDS.128 R4, [0x130] ; /* 0x00013000ff047984 */
/* 0x000e240000000c00 */
/*0680*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x000fc80000000000 */
/*0690*/ FADD R10, R9, R10 ; /* 0x0000000a090a7221 */
/* 0x000fc80000000000 */
/*06a0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x000fc80000000000 */
/*06b0*/ FADD R16, R11, R16 ; /* 0x000000100b107221 */
/* 0x002fe40000000000 */
/*06c0*/ LDS.128 R8, [0x140] ; /* 0x00014000ff087984 */
/* 0x000e640000000c00 */
/*06d0*/ FADD R17, R16, R17 ; /* 0x0000001110117221 */
/* 0x000fc80000000000 */
/*06e0*/ FADD R18, R17, R18 ; /* 0x0000001211127221 */
/* 0x000fc80000000000 */
/*06f0*/ FADD R19, R18, R19 ; /* 0x0000001312137221 */
/* 0x000fc80000000000 */
/*0700*/ FADD R12, R19, R12 ; /* 0x0000000c130c7221 */
/* 0x004fe40000000000 */
/*0710*/ LDS.128 R16, [0x150] ; /* 0x00015000ff107984 */
/* 0x000ea40000000c00 */
/*0720*/ FADD R13, R12, R13 ; /* 0x0000000d0c0d7221 */
/* 0x000fc80000000000 */
/*0730*/ FADD R14, R13, R14 ; /* 0x0000000e0d0e7221 */
/* 0x000fc80000000000 */
/*0740*/ FADD R15, R14, R15 ; /* 0x0000000f0e0f7221 */
/* 0x000fc80000000000 */
/*0750*/ FADD R4, R15, R4 ; /* 0x000000040f047221 */
/* 0x001fe40000000000 */
/*0760*/ LDS.128 R12, [0x160] ; /* 0x00016000ff0c7984 */
/* 0x000e240000000c00 */
/*0770*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x000fc80000000000 */
/*0780*/ FADD R6, R5, R6 ; /* 0x0000000605067221 */
/* 0x000fc80000000000 */
/*0790*/ FADD R7, R6, R7 ; /* 0x0000000706077221 */
/* 0x000fc80000000000 */
/*07a0*/ FADD R8, R7, R8 ; /* 0x0000000807087221 */
/* 0x002fe40000000000 */
/*07b0*/ LDS.128 R4, [0x170] ; /* 0x00017000ff047984 */
/* 0x000e640000000c00 */
/*07c0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x000fc80000000000 */
/*07d0*/ FADD R10, R9, R10 ; /* 0x0000000a090a7221 */
/* 0x000fc80000000000 */
/*07e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x000fc80000000000 */
/*07f0*/ FADD R16, R11, R16 ; /* 0x000000100b107221 */
/* 0x004fe40000000000 */
/*0800*/ LDS.128 R8, [0x180] ; /* 0x00018000ff087984 */
/* 0x000ea40000000c00 */
/*0810*/ FADD R17, R16, R17 ; /* 0x0000001110117221 */
/* 0x000fc80000000000 */
/*0820*/ FADD R18, R17, R18 ; /* 0x0000001211127221 */
/* 0x000fc80000000000 */
/*0830*/ FADD R19, R18, R19 ; /* 0x0000001312137221 */
/* 0x000fc80000000000 */
/*0840*/ FADD R12, R19, R12 ; /* 0x0000000c130c7221 */
/* 0x001fe40000000000 */
/*0850*/ LDS.128 R16, [0x190] ; /* 0x00019000ff107984 */
/* 0x000e240000000c00 */
/*0860*/ FADD R13, R12, R13 ; /* 0x0000000d0c0d7221 */
/* 0x000fc80000000000 */
/*0870*/ FADD R14, R13, R14 ; /* 0x0000000e0d0e7221 */
/* 0x000fc80000000000 */
/*0880*/ FADD R15, R14, R15 ; /* 0x0000000f0e0f7221 */
/* 0x000fc80000000000 */
/*0890*/ FADD R4, R15, R4 ; /* 0x000000040f047221 */
/* 0x002fe40000000000 */
/*08a0*/ LDS.128 R12, [0x1a0] ; /* 0x0001a000ff0c7984 */
/* 0x000e640000000c00 */
/*08b0*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x000fc80000000000 */
/*08c0*/ FADD R6, R5, R6 ; /* 0x0000000605067221 */
/* 0x000fc80000000000 */
/*08d0*/ FADD R7, R6, R7 ; /* 0x0000000706077221 */
/* 0x000fc80000000000 */
/*08e0*/ FADD R8, R7, R8 ; /* 0x0000000807087221 */
/* 0x004fe40000000000 */
/*08f0*/ LDS.128 R4, [0x1b0] ; /* 0x0001b000ff047984 */
/* 0x000ea40000000c00 */
/*0900*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x000fc80000000000 */
/*0910*/ FADD R10, R9, R10 ; /* 0x0000000a090a7221 */
/* 0x000fc80000000000 */
/*0920*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x000fc80000000000 */
/*0930*/ FADD R16, R11, R16 ; /* 0x000000100b107221 */
/* 0x001fe40000000000 */
/*0940*/ LDS.128 R8, [0x1c0] ; /* 0x0001c000ff087984 */
/* 0x000e240000000c00 */
/*0950*/ FADD R17, R16, R17 ; /* 0x0000001110117221 */
/* 0x000fc80000000000 */
/*0960*/ FADD R18, R17, R18 ; /* 0x0000001211127221 */
/* 0x000fc80000000000 */
/*0970*/ FADD R19, R18, R19 ; /* 0x0000001312137221 */
/* 0x000fc80000000000 */
/*0980*/ FADD R12, R19, R12 ; /* 0x0000000c130c7221 */
/* 0x002fe40000000000 */
/*0990*/ LDS.128 R16, [0x1d0] ; /* 0x0001d000ff107984 */
/* 0x000e640000000c00 */
/*09a0*/ FADD R13, R12, R13 ; /* 0x0000000d0c0d7221 */
/* 0x000fc80000000000 */
/*09b0*/ FADD R14, R13, R14 ; /* 0x0000000e0d0e7221 */
/* 0x000fc80000000000 */
/*09c0*/ FADD R15, R14, R15 ; /* 0x0000000f0e0f7221 */
/* 0x000fc80000000000 */
/*09d0*/ FADD R4, R15, R4 ; /* 0x000000040f047221 */
/* 0x004fe40000000000 */
/*09e0*/ LDS.128 R12, [0x1e0] ; /* 0x0001e000ff0c7984 */
/* 0x000ea40000000c00 */
/*09f0*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x000fc80000000000 */
/*0a00*/ FADD R6, R5, R6 ; /* 0x0000000605067221 */
/* 0x000fc80000000000 */
/*0a10*/ FADD R7, R6, R7 ; /* 0x0000000706077221 */
/* 0x000fc80000000000 */
/*0a20*/ FADD R8, R7, R8 ; /* 0x0000000807087221 */
/* 0x001fe40000000000 */
/*0a30*/ LDS.128 R4, [0x1f0] ; /* 0x0001f000ff047984 */
/* 0x000e240000000c00 */
/*0a40*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x000fc80000000000 */
/*0a50*/ FADD R10, R9, R10 ; /* 0x0000000a090a7221 */
/* 0x000fc80000000000 */
/*0a60*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x000fc80000000000 */
/*0a70*/ FADD R16, R11, R16 ; /* 0x000000100b107221 */
/* 0x002fc80000000000 */
/*0a80*/ FADD R17, R16, R17 ; /* 0x0000001110117221 */
/* 0x000fc80000000000 */
/*0a90*/ FADD R18, R17, R18 ; /* 0x0000001211127221 */
/* 0x000fc80000000000 */
/*0aa0*/ FADD R19, R18, R19 ; /* 0x0000001312137221 */
/* 0x000fc80000000000 */
/*0ab0*/ FADD R12, R19, R12 ; /* 0x0000000c130c7221 */
/* 0x004fc80000000000 */
/*0ac0*/ FADD R13, R12, R13 ; /* 0x0000000d0c0d7221 */
/* 0x000fc80000000000 */
/*0ad0*/ FADD R14, R13, R14 ; /* 0x0000000e0d0e7221 */
/* 0x000fc80000000000 */
/*0ae0*/ FADD R15, R14, R15 ; /* 0x0000000f0e0f7221 */
/* 0x000fc80000000000 */
/*0af0*/ FADD R4, R15, R4 ; /* 0x000000040f047221 */
/* 0x001fc80000000000 */
/*0b00*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x000fc80000000000 */
/*0b10*/ FADD R6, R5, R6 ; /* 0x0000000605067221 */
/* 0x000fc80000000000 */
/*0b20*/ FADD R7, R6, R7 ; /* 0x0000000706077221 */
/* 0x000fca0000000000 */
/*0b30*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], R7 ; /* 0x000000070200798e */
/* 0x000fe2000c10e784 */
/*0b40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b50*/ BRA 0xb50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3dotPfS_S_
.globl _Z3dotPfS_S_
.p2align 8
.type _Z3dotPfS_S_,@function
_Z3dotPfS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x80, v1
s_cbranch_execz .LBB0_7
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v0
global_load_b32 v3, v[3:4], off
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_dual_mul_f32 v1, v3, v1 :: v_dual_lshlrev_b32 v2, 2, v0
ds_store_b32 v2, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v0, 0
.LBB0_3:
v_mov_b32_e32 v1, s2
s_add_i32 s2, s2, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_eq_i32 s2, 0x200
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v0, v1
s_cbranch_scc0 .LBB0_3
s_mov_b32 s3, exec_lo
s_mov_b32 s2, 0
v_mbcnt_lo_u32_b32 v1, s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, 0, v1
s_and_b32 s4, exec_lo, vcc_lo
s_mov_b32 exec_lo, s4
s_cbranch_execz .LBB0_7
s_load_b64 s[0:1], s[0:1], 0x10
s_bcnt1_i32_b32 s3, s3
v_mov_b32_e32 v3, 0
v_cvt_f32_ubyte0_e32 v1, s3
s_waitcnt lgkmcnt(0)
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_dual_mul_f32 v2, v0, v1 :: v_dual_mov_b32 v1, s4
.LBB0_6:
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v0, v1, v2
global_atomic_cmpswap_b32 v0, v3, v[0:1], s[0:1] glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v0, v1
v_mov_b32_e32 v1, v0
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_6
.LBB0_7:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3dotPfS_S_
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3dotPfS_S_, .Lfunc_end0-_Z3dotPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3dotPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3dotPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a2db7_00000000-6_my-atomic-5.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13random_floatsPff
.type _Z13random_floatsPff, @function
_Z13random_floatsPff:
.LFB2057:
.cfi_startproc
endbr64
movl $1, %eax
pxor %xmm1, %xmm1
comiss %xmm1, %xmm0
jbe .L3
.L6:
movss %xmm1, -4(%rdi,%rax,4)
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
addq $1, %rax
comiss %xmm1, %xmm0
ja .L6
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z13random_floatsPff, .-_Z13random_floatsPff
.globl _Z26__device_stub__Z3dotPfS_S_PfS_S_
.type _Z26__device_stub__Z3dotPfS_S_PfS_S_, @function
_Z26__device_stub__Z3dotPfS_S_PfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3dotPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z26__device_stub__Z3dotPfS_S_PfS_S_, .-_Z26__device_stub__Z3dotPfS_S_PfS_S_
.globl _Z3dotPfS_S_
.type _Z3dotPfS_S_, @function
_Z3dotPfS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3dotPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z3dotPfS_S_, .-_Z3dotPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Number of SMs: %d\n"
.LC3:
.string "*c = %.2f\n"
.LC4:
.string "result = %.2f\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 20(%rsp), %rdi
movl $0, %edx
movl $16, %esi
call cudaDeviceGetAttribute@PLT
movl 20(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 24(%rsp), %rdi
movl $268435456, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $268435456, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $268435456, %edi
call malloc@PLT
movq %rax, %rbp
movl $268435456, %edi
call malloc@PLT
movq %rax, %rbx
movl $4, %edi
call malloc@PLT
movq %rax, %r12
movss .LC2(%rip), %xmm0
movq %rbp, %rdi
call _Z13random_floatsPff
movss .LC2(%rip), %xmm0
movq %rbx, %rdi
call _Z13random_floatsPff
movl $0, %eax
movl $0x00000000, 12(%rsp)
.L19:
movss 0(%rbp,%rax), %xmm0
mulss (%rbx,%rax), %xmm0
addss 12(%rsp), %xmm0
movss %xmm0, 12(%rsp)
addq $4, %rax
cmpq $512, %rax
jne .L19
movl $0x00000000, (%r12)
movl $1, %ecx
movl $268435456, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $268435456, %edx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $2, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movl $2, %ecx
movl $4, %edx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z26__device_stub__Z3dotPfS_S_PfS_S_
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z3dotPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z3dotPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1124073472
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "my-atomic-5.hip"
.globl _Z18__device_stub__dotPfS_S_ # -- Begin function _Z18__device_stub__dotPfS_S_
.p2align 4, 0x90
.type _Z18__device_stub__dotPfS_S_,@function
_Z18__device_stub__dotPfS_S_: # @_Z18__device_stub__dotPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3dotPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__dotPfS_S_, .Lfunc_end0-_Z18__device_stub__dotPfS_S_
.cfi_endproc
# -- End function
.globl _Z13random_floatsPff # -- Begin function _Z13random_floatsPff
.p2align 4, 0x90
.type _Z13random_floatsPff,@function
_Z13random_floatsPff: # @_Z13random_floatsPff
.cfi_startproc
# %bb.0:
xorps %xmm1, %xmm1
ucomiss %xmm1, %xmm0
jbe .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss %xmm1, (%rdi,%rax,4)
incq %rax
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
ucomiss %xmm1, %xmm0
ja .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z13random_floatsPff, .Lfunc_end1-_Z13random_floatsPff
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $136, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 36(%rsp), %rdi
xorl %r12d, %r12d
movl $63, %esi
xorl %edx, %edx
callq hipDeviceGetAttribute
movl 36(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 24(%rsp), %rdi
movl $268435456, %esi # imm = 0x10000000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $268435456, %esi # imm = 0x10000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movl $268435456, %edi # imm = 0x10000000
callq malloc
movq %rax, %rbx
movl $268435456, %edi # imm = 0x10000000
callq malloc
movq %rax, %r14
movl $4, %edi
callq malloc
movq %rax, %r15
xorps %xmm0, %xmm0
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss %xmm0, (%rbx,%r12,4)
incq %r12
xorps %xmm0, %xmm0
cvtsi2ss %r12d, %xmm0
cmpq $128, %r12
jne .LBB2_1
# %bb.2: # %.lr.ph.i28.preheader
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i28
# =>This Inner Loop Header: Depth=1
movss %xmm0, (%r14,%rax,4)
incq %rax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
cmpq $128, %rax
jne .LBB2_3
# %bb.4: # %_Z13random_floatsPff.exit31.preheader
xorps %xmm1, %xmm1
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_5: # %_Z13random_floatsPff.exit31
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%r14,%rax,4), %xmm0
addss %xmm0, %xmm1
incq %rax
cmpq $128, %rax
jne .LBB2_5
# %bb.6:
movss %xmm1, 32(%rsp) # 4-byte Spill
movl $0, (%r15)
movq 24(%rsp), %rdi
movl $268435456, %edx # imm = 0x10000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $268435456, %edx # imm = 0x10000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 1022(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3dotPfS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
movq 8(%rsp), %rsi
movl $4, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movss (%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movss 32(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3dotPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3dotPfS_S_,@object # @_Z3dotPfS_S_
.section .rodata,"a",@progbits
.globl _Z3dotPfS_S_
.p2align 3, 0x0
_Z3dotPfS_S_:
.quad _Z18__device_stub__dotPfS_S_
.size _Z3dotPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Number of SMs: %d\n"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "*c = %.2f\n"
.size .L.str.1, 15
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "result = %.2f\n"
.size .L.str.2, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3dotPfS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__dotPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3dotPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void increment_kernel(int *g_data, int inc_value) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
g_data[idx] = g_data[idx] + inc_value;
} | code for sm_80
Function : _Z16increment_kernelPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0080*/ IADD3 R5, R0, c[0x0][0x168], RZ ; /* 0x00005a0000057a10 */
/* 0x004fca0007ffe0ff */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void increment_kernel(int *g_data, int inc_value) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
g_data[idx] = g_data[idx] + inc_value;
} | .file "tmpxft_0009d8d4_00000000-6_increment_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z16increment_kernelPiiPii
.type _Z37__device_stub__Z16increment_kernelPiiPii, @function
_Z37__device_stub__Z16increment_kernelPiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16increment_kernelPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z16increment_kernelPiiPii, .-_Z37__device_stub__Z16increment_kernelPiiPii
.globl _Z16increment_kernelPii
.type _Z16increment_kernelPii, @function
_Z16increment_kernelPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z16increment_kernelPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16increment_kernelPii, .-_Z16increment_kernelPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16increment_kernelPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16increment_kernelPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void increment_kernel(int *g_data, int inc_value) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
g_data[idx] = g_data[idx] + inc_value;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void increment_kernel(int *g_data, int inc_value) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
g_data[idx] = g_data[idx] + inc_value;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void increment_kernel(int *g_data, int inc_value) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
g_data[idx] = g_data[idx] + inc_value;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16increment_kernelPii
.globl _Z16increment_kernelPii
.p2align 8
.type _Z16increment_kernelPii,@function
_Z16increment_kernelPii:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_load_b64 s[2:3], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_load_b32 s0, s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, s0, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16increment_kernelPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16increment_kernelPii, .Lfunc_end0-_Z16increment_kernelPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16increment_kernelPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16increment_kernelPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void increment_kernel(int *g_data, int inc_value) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
g_data[idx] = g_data[idx] + inc_value;
} | .text
.file "increment_kernel.hip"
.globl _Z31__device_stub__increment_kernelPii # -- Begin function _Z31__device_stub__increment_kernelPii
.p2align 4, 0x90
.type _Z31__device_stub__increment_kernelPii,@function
_Z31__device_stub__increment_kernelPii: # @_Z31__device_stub__increment_kernelPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16increment_kernelPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z31__device_stub__increment_kernelPii, .Lfunc_end0-_Z31__device_stub__increment_kernelPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16increment_kernelPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16increment_kernelPii,@object # @_Z16increment_kernelPii
.section .rodata,"a",@progbits
.globl _Z16increment_kernelPii
.p2align 3, 0x0
_Z16increment_kernelPii:
.quad _Z31__device_stub__increment_kernelPii
.size _Z16increment_kernelPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16increment_kernelPii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__increment_kernelPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16increment_kernelPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16increment_kernelPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0080*/ IADD3 R5, R0, c[0x0][0x168], RZ ; /* 0x00005a0000057a10 */
/* 0x004fca0007ffe0ff */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16increment_kernelPii
.globl _Z16increment_kernelPii
.p2align 8
.type _Z16increment_kernelPii,@function
_Z16increment_kernelPii:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_load_b64 s[2:3], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_load_b32 s0, s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, s0, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16increment_kernelPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16increment_kernelPii, .Lfunc_end0-_Z16increment_kernelPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16increment_kernelPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16increment_kernelPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009d8d4_00000000-6_increment_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z16increment_kernelPiiPii
.type _Z37__device_stub__Z16increment_kernelPiiPii, @function
_Z37__device_stub__Z16increment_kernelPiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16increment_kernelPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z16increment_kernelPiiPii, .-_Z37__device_stub__Z16increment_kernelPiiPii
.globl _Z16increment_kernelPii
.type _Z16increment_kernelPii, @function
_Z16increment_kernelPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z16increment_kernelPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16increment_kernelPii, .-_Z16increment_kernelPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16increment_kernelPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16increment_kernelPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "increment_kernel.hip"
.globl _Z31__device_stub__increment_kernelPii # -- Begin function _Z31__device_stub__increment_kernelPii
.p2align 4, 0x90
.type _Z31__device_stub__increment_kernelPii,@function
_Z31__device_stub__increment_kernelPii: # @_Z31__device_stub__increment_kernelPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16increment_kernelPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z31__device_stub__increment_kernelPii, .Lfunc_end0-_Z31__device_stub__increment_kernelPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16increment_kernelPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16increment_kernelPii,@object # @_Z16increment_kernelPii
.section .rodata,"a",@progbits
.globl _Z16increment_kernelPii
.p2align 3, 0x0
_Z16increment_kernelPii:
.quad _Z31__device_stub__increment_kernelPii
.size _Z16increment_kernelPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16increment_kernelPii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__increment_kernelPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16increment_kernelPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/*
Detected 1 CUDA Capable device(s)
Device 0: "GeForce GT 320M"
CUDA Driver Version / Runtime Version 5.0 / 5.0
CUDA Capability Major/Minor version number: 1.2
Total amount of global memory: 1024 MBytes (1073741824 bytes)
( 3) Multiprocessors x ( 8) CUDA Cores/MP: 24 CUDA Cores
GPU Clock rate: 1100 MHz (1.10 GHz)
Memory Clock rate: 790 Mhz
Memory Bus Width: 128-bit
Max Texture Dimension Size (x,y,z) 1D=(8192), 2D=(65536,32768), 3D=(2048,2048,2048)
Max Layered Texture Size (dim) x layers 1D=(8192) x 512, 2D=(8192,8192) x 512
Total amount of constant memory: 65536 bytes
Total amount of shared memory per block: 16384 bytes
Total number of registers available per block: 16384
Warp size: 32
Maximum number of threads per multiprocessor: 1024
Maximum number of threads per block: 512
Maximum sizes of each dimension of a block: 512 x 512 x 64
Maximum sizes of each dimension of a grid: 65535 x 65535 x 1
Maximum memory pitch: 2147483647 bytes
Texture alignment: 256 bytes
Concurrent copy and kernel execution: Yes with 1 copy engine(s)
Run time limit on kernels: Yes
Integrated GPU sharing Host Memory: No
Support host page-locked memory mapping: Yes
Alignment requirement for Surfaces: Yes
Device has ECC support: Disabled
CUDA Device Driver Mode (TCC or WDDM): WDDM (Windows Display Driver Model)
Device supports Unified Addressing (UVA): No
Device PCI Bus ID / PCI location ID: 2 / 0
Compute Mode:
< Default (multiple host threads can use ::cudaSetDevice() with device simultaneously) >
deviceQuery, CUDA Driver = CUDART, CUDA Driver Version = 5.0, CUDA Runtime Version = 5.0, NumDevs = 1, Device0 = GeForce GT 320M
*/
__global__ void freqencyStep1(char *d_dat,int len, int *d_freq)
{//²½ÖèÒ»£¬ÏȽ«Êý¾Ý¼ÓºÍµ½share memoryÖУ¬È»ºóÔÙÀÛ¼Óµ½ÏÔ´æÉÏ¡£
///ÕâÀïÒ²ÓÐÁ½ÖÖ·½·¨£¬ÕâÊÇ·½·¨Ò»£¬share memoryºá×ÅÓá£ÁíÒ»ÖÖ·½·¨£¬½«share memoryÊú×ÅÓã¨ÔÚ½øÐпéÄÚÀÛ¼Óʱ£¬Ö»ÓÃÇ°26¸öÏß³ÌÍê³É0µ½127µÄÀÛ¼Ó¡£¡£
///·½·¨¶þµÄÀÛ¼Óʱ£¬×îºÃÀÛ¼Óµ½¶Ô½ÇÏßÉÏ£¬È»ºóÔÚд³öʱ£¬¿ÉÒÔ±ÜÃâbank conflict¡£
__shared__ int sfreq[3456];//27*128////share memoryºá×Å·Å£¬Ã¿Ïß³Ì27¸öint.
for(int i=threadIdx.x ;i< 3456;i += blockDim.x)
sfreq[i] = 0;////ÏÈÇå¿Õ¡£
__syncthreads();
int *myfreq = &sfreq[27*threadIdx.x];
int gridsize = blockDim.x * gridDim.x;
for(int i=threadIdx.x + blockIdx.x*blockDim.x; i< len; i += gridsize)
//if((d_dat[i]>='a')&&(d_dat[i]<='z'))//Èç¹ûÈ·¶¨Êý¾ÝÖ»ÊÇa--z£¬¿ÉÒÔ°ÑifÈ¥µô¡£
myfreq[d_dat[i]-'a']++;
__syncthreads();///¸÷Ïß³Ìͳ¼Æµ½×Ô¼ºµÄsharememoryÖС£
///ÓÃÒ»¸öÑ»·ÊµÏÖÕÛ°ë¼Ó¡£
for(int roll = 64;roll>=1; roll>>=1)
{
if(threadIdx.x <roll)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+roll)+i];
}
__syncthreads();
}
#if 0
if(threadIdx.x<64)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+64)+i];
}
__syncthreads();
if(threadIdx.x<32)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+32)+i];
}
__syncthreads();
if(threadIdx.x<16)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+16)+i];
}
if(threadIdx.x< 8)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+ 8)+i];
}
if(threadIdx.x< 4)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+ 4)+i];
}
if(threadIdx.x< 2)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+ 2)+i];
}
if(threadIdx.x == 0)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x )+i];
}
#endif
__syncthreads();
if(threadIdx.x<26)///Èç¹ûÏÔ¿¨Ö§³ÖÔ×Ó¼Ó£¬¿ÉÒÔʹÓÃÔ×Ó¼Ó£¬Ö±½Ó¼Óµ½ÏÔ´æÉÏ¡£ÄÇÑù¾ÍûÓеڶþ²½¡£ 1.1¼°ÒÔÉÏÖ§³ÖÈ«¾ÖÏÔ´æµÄ32λÔ×Ó²Ù×÷¡£
atomicAdd(&d_freq[threadIdx.x],sfreq[threadIdx.x]);
} | code for sm_80
Function : _Z13freqencyStep1PciPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ BSSY B0, 0xc0 ; /* 0x0000009000007945 */
/* 0x000fe60003800000 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0040*/ ISETP.GE.AND P0, PT, R0, 0xd80, PT ; /* 0x00000d800000780c */
/* 0x001fda0003f06270 */
/*0050*/ @P0 BRA 0xb0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x002fca00078e0000 */
/*0070*/ STS [R2.X4], RZ ; /* 0x000000ff02007388 */
/* 0x0001e40000004800 */
/*0080*/ IADD3 R2, R2, c[0x0][0x0], RZ ; /* 0x0000000002027a10 */
/* 0x001fc80007ffe0ff */
/*0090*/ ISETP.GE.AND P0, PT, R2, 0xd80, PT ; /* 0x00000d800200780c */
/* 0x000fda0003f06270 */
/*00a0*/ @!P0 BRA 0x70 ; /* 0xffffffc000008947 */
/* 0x000fea000383ffff */
/*00b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*00c0*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x000fe200078e0200 */
/*00d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe80000010000 */
/*00e0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fe40003f06270 */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0100*/ BSSY B0, 0x630 ; /* 0x0000052000007945 */
/* 0x000ff40003800000 */
/*0110*/ @P0 BRA 0x620 ; /* 0x0000050000000947 */
/* 0x000fea0003800000 */
/*0120*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff027624 */
/* 0x000fe200078e00ff */
/*0130*/ BSSY B1, 0x400 ; /* 0x000002c000017945 */
/* 0x000fe60003800000 */
/*0140*/ IMAD R2, R2, c[0x0][0xc], RZ ; /* 0x0000030002027a24 */
/* 0x000fc800078e02ff */
/*0150*/ I2F.U32.RP R6, R2 ; /* 0x0000000200067306 */
/* 0x000e220000209000 */
/*0160*/ IADD3 R4, R2.reuse, R3, RZ ; /* 0x0000000302047210 */
/* 0x040fe20007ffe0ff */
/*0170*/ IMAD.MOV R9, RZ, RZ, -R2 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a02 */
/*0180*/ ISETP.NE.U32.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f45070 */
/*0190*/ LOP3.LUT R7, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff077212 */
/* 0x000fe200078e33ff */
/*01a0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc600078e00ff */
/*01b0*/ IADD3 R7, R7, c[0x0][0x168], R2 ; /* 0x00005a0007077a10 */
/* 0x000fe20007ffe002 */
/*01c0*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*01d0*/ IADD3 R5, R6, 0xffffffe, RZ ; /* 0x0ffffffe06057810 */
/* 0x001fcc0007ffe0ff */
/*01e0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e24000021f000 */
/*01f0*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x001fc800078e02ff */
/*0200*/ IMAD.HI.U32 R4, R5, R9, R4 ; /* 0x0000000905047227 */
/* 0x000fcc00078e0004 */
/*0210*/ IMAD.HI.U32 R4, R4, R7, RZ ; /* 0x0000000704047227 */
/* 0x000fc800078e00ff */
/*0220*/ IMAD.MOV R5, RZ, RZ, -R4 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a04 */
/*0230*/ IMAD R7, R2, R5, R7 ; /* 0x0000000502077224 */
/* 0x000fca00078e0207 */
/*0240*/ ISETP.GE.U32.AND P0, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fda0003f06070 */
/*0250*/ @P0 IMAD.IADD R7, R7, 0x1, -R2 ; /* 0x0000000107070824 */
/* 0x000fe200078e0a02 */
/*0260*/ @P0 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104040810 */
/* 0x000fc80007ffe0ff */
/*0270*/ ISETP.GE.U32.AND P1, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fe20003f26070 */
/*0280*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1b ; /* 0x0000001bff077424 */
/* 0x000fd800078e00ff */
/*0290*/ @P1 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104041810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ @!P2 LOP3.LUT R4, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff04a212 */
/* 0x000fc800078e33ff */
/*02b0*/ IADD3 R5, R4.reuse, 0x1, RZ ; /* 0x0000000104057810 */
/* 0x040fe40007ffe0ff */
/*02c0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f06070 */
/*02d0*/ IMAD R4, R0, R7, -0x61 ; /* 0xffffff9f00047424 */
/* 0x000fe200078e0207 */
/*02e0*/ LOP3.LUT P1, R5, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305057812 */
/* 0x000fda000782c0ff */
/*02f0*/ @!P1 BRA 0x3f0 ; /* 0x000000f000009947 */
/* 0x000fea0003800000 */
/*0300*/ IADD3 R11, P1, R3, c[0x0][0x160], RZ ; /* 0x00005800030b7a10 */
/* 0x000fc80007f3e0ff */
/*0310*/ LEA.HI.X.SX32 R10, R3, c[0x0][0x164], 0x1, P1 ; /* 0x00005900030a7a11 */
/* 0x000fca00008f0eff */
/*0320*/ IMAD.MOV.U32 R7, RZ, RZ, R10 ; /* 0x000000ffff077224 */
/* 0x000fe200078e000a */
/*0330*/ MOV R6, R11 ; /* 0x0000000b00067202 */
/* 0x000fca0000000f00 */
/*0340*/ LDG.E.S8 R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea2000c1e1300 */
/*0350*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe20007ffe0ff */
/*0360*/ IMAD.IADD R3, R2.reuse, 0x1, R3 ; /* 0x0000000102037824 */
/* 0x040fe200078e0203 */
/*0370*/ IADD3 R11, P2, R2.reuse, R11, RZ ; /* 0x0000000b020b7210 */
/* 0x040fe40007f5e0ff */
/*0380*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f25270 */
/*0390*/ LEA.HI.X.SX32 R10, R2, R10, 0x1, P2 ; /* 0x0000000a020a7211 */
/* 0x000fe200010f0eff */
/*03a0*/ IMAD.IADD R8, R4, 0x1, R7 ; /* 0x0000000104087824 */
/* 0x005fca00078e0207 */
/*03b0*/ LDS R9, [R8.X4] ; /* 0x0000000008097984 */
/* 0x000e240000004800 */
/*03c0*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x001fca0007ffe0ff */
/*03d0*/ STS [R8.X4], R9 ; /* 0x0000000908007388 */
/* 0x0001e20000004800 */
/*03e0*/ @P1 BRA 0x320 ; /* 0xffffff3000001947 */
/* 0x000fea000383ffff */
/*03f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0400*/ @!P0 BRA 0x620 ; /* 0x0000021000008947 */
/* 0x000fea0003800000 */
/*0410*/ SHF.R.S32.HI R5, RZ, 0x1f, R2 ; /* 0x0000001fff057819 */
/* 0x000fe40000011402 */
/*0420*/ IADD3 R6, P0, R3, c[0x0][0x160], RZ ; /* 0x0000580003067a10 */
/* 0x000fc80007f1e0ff */
/*0430*/ LEA.HI.X.SX32 R7, R3, c[0x0][0x164], 0x1, P0 ; /* 0x0000590003077a11 */
/* 0x000fca00000f0eff */
/*0440*/ LDG.E.S8 R15, [R6.64] ; /* 0x00000004060f7981 */
/* 0x000ea2000c1e1300 */
/*0450*/ IADD3 R8, P0, R2, R6, RZ ; /* 0x0000000602087210 */
/* 0x001fca0007f1e0ff */
/*0460*/ IMAD.X R9, R5, 0x1, R7, P0 ; /* 0x0000000105097824 */
/* 0x000fca00000e0607 */
/*0470*/ LDG.E.S8 R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000ee2000c1e1300 */
/*0480*/ IADD3 R10, P0, R2, R8, RZ ; /* 0x00000008020a7210 */
/* 0x000fc80007f1e0ff */
/*0490*/ IADD3.X R11, R5, R9, RZ, P0, !PT ; /* 0x00000009050b7210 */
/* 0x000fca00007fe4ff */
/*04a0*/ LDG.E.S8 R19, [R10.64] ; /* 0x000000040a137981 */
/* 0x000f22000c1e1300 */
/*04b0*/ IADD3 R12, P0, R2, R10, RZ ; /* 0x0000000a020c7210 */
/* 0x000fca0007f1e0ff */
/*04c0*/ IMAD.X R13, R5, 0x1, R11, P0 ; /* 0x00000001050d7824 */
/* 0x000fcc00000e060b */
/*04d0*/ LDG.E.S8 R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000f62000c1e1300 */
/*04e0*/ IADD3 R3, R2, R3, R2 ; /* 0x0000000302037210 */
/* 0x000fc80007ffe002 */
/*04f0*/ IADD3 R3, R2, R3, R2 ; /* 0x0000000302037210 */
/* 0x000fc80007ffe002 */
/*0500*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fe20003f06270 */
/*0510*/ IMAD.IADD R15, R4, 0x1, R15 ; /* 0x00000001040f7824 */
/* 0x004fca00078e020f */
/*0520*/ LDS R6, [R15.X4] ; /* 0x000000000f067984 */
/* 0x000e220000004800 */
/*0530*/ IMAD.IADD R17, R4.reuse, 0x1, R17 ; /* 0x0000000104117824 */
/* 0x048fe200078e0211 */
/*0540*/ IADD3 R19, R4.reuse, R19, RZ ; /* 0x0000001304137210 */
/* 0x050fe20007ffe0ff */
/*0550*/ IMAD.IADD R13, R4, 0x1, R13 ; /* 0x00000001040d7824 */
/* 0x020fe200078e020d */
/*0560*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x001fca0007ffe0ff */
/*0570*/ STS [R15.X4], R6 ; /* 0x000000060f007388 */
/* 0x000fe80000004800 */
/*0580*/ LDS R7, [R17.X4] ; /* 0x0000000011077984 */
/* 0x000e240000004800 */
/*0590*/ IADD3 R8, R7, 0x1, RZ ; /* 0x0000000107087810 */
/* 0x001fca0007ffe0ff */
/*05a0*/ STS [R17.X4], R8 ; /* 0x0000000811007388 */
/* 0x000fe80000004800 */
/*05b0*/ LDS R7, [R19.X4] ; /* 0x0000000013077984 */
/* 0x000e240000004800 */
/*05c0*/ IADD3 R10, R7, 0x1, RZ ; /* 0x00000001070a7810 */
/* 0x001fca0007ffe0ff */
/*05d0*/ STS [R19.X4], R10 ; /* 0x0000000a13007388 */
/* 0x000fe80000004800 */
/*05e0*/ LDS R7, [R13.X4] ; /* 0x000000000d077984 */
/* 0x000e240000004800 */
/*05f0*/ IADD3 R12, R7, 0x1, RZ ; /* 0x00000001070c7810 */
/* 0x001fca0007ffe0ff */
/*0600*/ STS [R13.X4], R12 ; /* 0x0000000c0d007388 */
/* 0x0001e20000004800 */
/*0610*/ @!P0 BRA 0x420 ; /* 0xfffffe0000008947 */
/* 0x000fea000383ffff */
/*0620*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0630*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0640*/ IMAD R2, R0, 0x6c, RZ ; /* 0x0000006c00027824 */
/* 0x000fe400078e02ff */
/*0650*/ IMAD.MOV.U32 R3, RZ, RZ, 0x40 ; /* 0x00000040ff037424 */
/* 0x000fca00078e00ff */
/*0660*/ ISETP.GE.U32.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x000fe20003f06070 */
/*0670*/ BSSY B0, 0xd40 ; /* 0x000006c000007945 */
/* 0x000fd80003800000 */
/*0680*/ @P0 BRA 0xd30 ; /* 0x000006a000000947 */
/* 0x001fea0003800000 */
/*0690*/ IMAD.IADD R4, R0, 0x1, R3 ; /* 0x0000000100047824 */
/* 0x000fe200078e0203 */
/*06a0*/ LDS R5, [R2] ; /* 0x0000000002057984 */
/* 0x000fe60000000800 */
/*06b0*/ IMAD R4, R4, 0x6c, RZ ; /* 0x0000006c04047824 */
/* 0x000fca00078e02ff */
/*06c0*/ LDS R6, [R4] ; /* 0x0000000004067984 */
/* 0x000e640000000800 */
/*06d0*/ IADD3 R5, R5, R6, RZ ; /* 0x0000000605057210 */
/* 0x002fe40007ffe0ff */
/*06e0*/ LDS R6, [R2+0x4] ; /* 0x0000040002067984 */
/* 0x000fe80000000800 */
/*06f0*/ STS [R2], R5 ; /* 0x0000000502007388 */
/* 0x000fe80000000800 */
/*0700*/ LDS R7, [R4+0x4] ; /* 0x0000040004077984 */
/* 0x000e680000000800 */
/*0710*/ LDS R5, [R2+0x10] ; /* 0x0000100002057984 */
/* 0x000fe20000000800 */
/*0720*/ IMAD.IADD R7, R6, 0x1, R7 ; /* 0x0000000106077824 */
/* 0x002fc600078e0207 */
/*0730*/ LDS R6, [R2+0x8] ; /* 0x0000080002067984 */
/* 0x000fe80000000800 */
/*0740*/ STS [R2+0x4], R7 ; /* 0x0000040702007388 */
/* 0x000fe80000000800 */
/*0750*/ LDS R9, [R4+0x8] ; /* 0x0000080004097984 */
/* 0x001e240000000800 */
/*0760*/ IMAD.IADD R9, R6, 0x1, R9 ; /* 0x0000000106097824 */
/* 0x001fc400078e0209 */
/*0770*/ LDS R6, [R2+0xc] ; /* 0x00000c0002067984 */
/* 0x000fe80000000800 */
/*0780*/ STS [R2+0x8], R9 ; /* 0x0000080902007388 */
/* 0x000fe80000000800 */
/*0790*/ LDS R11, [R4+0xc] ; /* 0x00000c00040b7984 */
/* 0x000e240000000800 */
/*07a0*/ IMAD.IADD R11, R6, 0x1, R11 ; /* 0x00000001060b7824 */
/* 0x001fca00078e020b */
/*07b0*/ STS [R2+0xc], R11 ; /* 0x00000c0b02007388 */
/* 0x000fe80000000800 */
/*07c0*/ LDS R6, [R4+0x10] ; /* 0x0000100004067984 */
/* 0x000e240000000800 */
/*07d0*/ IADD3 R5, R5, R6, RZ ; /* 0x0000000605057210 */
/* 0x001fe40007ffe0ff */
/*07e0*/ LDS R6, [R2+0x14] ; /* 0x0000140002067984 */
/* 0x000fe80000000800 */
/*07f0*/ STS [R2+0x10], R5 ; /* 0x0000100502007388 */
/* 0x000fe80000000800 */
/*0800*/ LDS R7, [R4+0x14] ; /* 0x0000140004077984 */
/* 0x000e280000000800 */
/*0810*/ LDS R5, [R2+0x20] ; /* 0x0000200002057984 */
/* 0x000fe20000000800 */
/*0820*/ IMAD.IADD R7, R6, 0x1, R7 ; /* 0x0000000106077824 */
/* 0x001fc600078e0207 */
/*0830*/ LDS R6, [R2+0x18] ; /* 0x0000180002067984 */
/* 0x000fe80000000800 */
/*0840*/ STS [R2+0x14], R7 ; /* 0x0000140702007388 */
/* 0x000fe80000000800 */
/*0850*/ LDS R9, [R4+0x18] ; /* 0x0000180004097984 */
/* 0x000e240000000800 */
/*0860*/ IMAD.IADD R9, R6, 0x1, R9 ; /* 0x0000000106097824 */
/* 0x001fc400078e0209 */
/*0870*/ LDS R6, [R2+0x1c] ; /* 0x00001c0002067984 */
/* 0x000fe80000000800 */
/*0880*/ STS [R2+0x18], R9 ; /* 0x0000180902007388 */
/* 0x000fe80000000800 */
/*0890*/ LDS R11, [R4+0x1c] ; /* 0x00001c00040b7984 */
/* 0x000e240000000800 */
/*08a0*/ IMAD.IADD R11, R6, 0x1, R11 ; /* 0x00000001060b7824 */
/* 0x001fca00078e020b */
/*08b0*/ STS [R2+0x1c], R11 ; /* 0x00001c0b02007388 */
/* 0x000fe80000000800 */
/*08c0*/ LDS R6, [R4+0x20] ; /* 0x0000200004067984 */
/* 0x000e240000000800 */
/*08d0*/ IADD3 R5, R5, R6, RZ ; /* 0x0000000605057210 */
/* 0x001fe40007ffe0ff */
/*08e0*/ LDS R6, [R2+0x24] ; /* 0x0000240002067984 */
/* 0x000fe80000000800 */
/*08f0*/ STS [R2+0x20], R5 ; /* 0x0000200502007388 */
/* 0x000fe80000000800 */
/*0900*/ LDS R7, [R4+0x24] ; /* 0x0000240004077984 */
/* 0x000e280000000800 */
/*0910*/ LDS R5, [R2+0x30] ; /* 0x0000300002057984 */
/* 0x000fe20000000800 */
/*0920*/ IMAD.IADD R7, R6, 0x1, R7 ; /* 0x0000000106077824 */
/* 0x001fc600078e0207 */
/*0930*/ LDS R6, [R2+0x28] ; /* 0x0000280002067984 */
/* 0x000fe80000000800 */
/*0940*/ STS [R2+0x24], R7 ; /* 0x0000240702007388 */
/* 0x000fe80000000800 */
/*0950*/ LDS R9, [R4+0x28] ; /* 0x0000280004097984 */
/* 0x000e240000000800 */
/*0960*/ IMAD.IADD R9, R6, 0x1, R9 ; /* 0x0000000106097824 */
/* 0x001fc400078e0209 */
/*0970*/ LDS R6, [R2+0x2c] ; /* 0x00002c0002067984 */
/* 0x000fe80000000800 */
/*0980*/ STS [R2+0x28], R9 ; /* 0x0000280902007388 */
/* 0x000fe80000000800 */
/*0990*/ LDS R11, [R4+0x2c] ; /* 0x00002c00040b7984 */
/* 0x000e240000000800 */
/*09a0*/ IMAD.IADD R11, R6, 0x1, R11 ; /* 0x00000001060b7824 */
/* 0x001fca00078e020b */
/*09b0*/ STS [R2+0x2c], R11 ; /* 0x00002c0b02007388 */
/* 0x000fe80000000800 */
/*09c0*/ LDS R6, [R4+0x30] ; /* 0x0000300004067984 */
/* 0x000e240000000800 */
/*09d0*/ IADD3 R5, R5, R6, RZ ; /* 0x0000000605057210 */
/* 0x001fe40007ffe0ff */
/*09e0*/ LDS R6, [R2+0x34] ; /* 0x0000340002067984 */
/* 0x000fe80000000800 */
/*09f0*/ STS [R2+0x30], R5 ; /* 0x0000300502007388 */
/* 0x000fe80000000800 */
/*0a00*/ LDS R7, [R4+0x34] ; /* 0x0000340004077984 */
/* 0x000e280000000800 */
/*0a10*/ LDS R5, [R2+0x40] ; /* 0x0000400002057984 */
/* 0x000fe20000000800 */
/*0a20*/ IMAD.IADD R7, R6, 0x1, R7 ; /* 0x0000000106077824 */
/* 0x001fc600078e0207 */
/*0a30*/ LDS R6, [R2+0x38] ; /* 0x0000380002067984 */
/* 0x000fe80000000800 */
/*0a40*/ STS [R2+0x34], R7 ; /* 0x0000340702007388 */
/* 0x000fe80000000800 */
/*0a50*/ LDS R9, [R4+0x38] ; /* 0x0000380004097984 */
/* 0x000e240000000800 */
/*0a60*/ IMAD.IADD R9, R6, 0x1, R9 ; /* 0x0000000106097824 */
/* 0x001fc400078e0209 */
/*0a70*/ LDS R6, [R2+0x3c] ; /* 0x00003c0002067984 */
/* 0x000fe80000000800 */
/*0a80*/ STS [R2+0x38], R9 ; /* 0x0000380902007388 */
/* 0x000fe80000000800 */
/*0a90*/ LDS R11, [R4+0x3c] ; /* 0x00003c00040b7984 */
/* 0x000e240000000800 */
/*0aa0*/ IMAD.IADD R11, R6, 0x1, R11 ; /* 0x00000001060b7824 */
/* 0x001fca00078e020b */
/*0ab0*/ STS [R2+0x3c], R11 ; /* 0x00003c0b02007388 */
/* 0x000fe80000000800 */
/*0ac0*/ LDS R6, [R4+0x40] ; /* 0x0000400004067984 */
/* 0x000e240000000800 */
/*0ad0*/ IADD3 R5, R5, R6, RZ ; /* 0x0000000605057210 */
/* 0x001fe40007ffe0ff */
/*0ae0*/ LDS R6, [R2+0x44] ; /* 0x0000440002067984 */
/* 0x000fe80000000800 */
/*0af0*/ STS [R2+0x40], R5 ; /* 0x0000400502007388 */
/* 0x000fe80000000800 */
/*0b00*/ LDS R7, [R4+0x44] ; /* 0x0000440004077984 */
/* 0x000e280000000800 */
/*0b10*/ LDS R5, [R2+0x50] ; /* 0x0000500002057984 */
/* 0x000fe20000000800 */
/*0b20*/ IMAD.IADD R7, R6, 0x1, R7 ; /* 0x0000000106077824 */
/* 0x001fc600078e0207 */
/*0b30*/ LDS R6, [R2+0x48] ; /* 0x0000480002067984 */
/* 0x000fe80000000800 */
/*0b40*/ STS [R2+0x44], R7 ; /* 0x0000440702007388 */
/* 0x000fe80000000800 */
/*0b50*/ LDS R9, [R4+0x48] ; /* 0x0000480004097984 */
/* 0x000e240000000800 */
/*0b60*/ IMAD.IADD R9, R6, 0x1, R9 ; /* 0x0000000106097824 */
/* 0x001fc400078e0209 */
/*0b70*/ LDS R6, [R2+0x4c] ; /* 0x00004c0002067984 */
/* 0x000fe80000000800 */
/*0b80*/ STS [R2+0x48], R9 ; /* 0x0000480902007388 */
/* 0x000fe80000000800 */
/*0b90*/ LDS R11, [R4+0x4c] ; /* 0x00004c00040b7984 */
/* 0x000e240000000800 */
/*0ba0*/ IMAD.IADD R11, R6, 0x1, R11 ; /* 0x00000001060b7824 */
/* 0x001fca00078e020b */
/*0bb0*/ STS [R2+0x4c], R11 ; /* 0x00004c0b02007388 */
/* 0x000fe80000000800 */
/*0bc0*/ LDS R6, [R4+0x50] ; /* 0x0000500004067984 */
/* 0x000e240000000800 */
/*0bd0*/ IADD3 R5, R5, R6, RZ ; /* 0x0000000605057210 */
/* 0x001fe40007ffe0ff */
/*0be0*/ LDS R6, [R2+0x54] ; /* 0x0000540002067984 */
/* 0x000fe80000000800 */
/*0bf0*/ STS [R2+0x50], R5 ; /* 0x0000500502007388 */
/* 0x000fe80000000800 */
/*0c00*/ LDS R7, [R4+0x54] ; /* 0x0000540004077984 */
/* 0x000e280000000800 */
/*0c10*/ LDS R5, [R2+0x60] ; /* 0x0000600002057984 */
/* 0x000fe20000000800 */
/*0c20*/ IMAD.IADD R7, R6, 0x1, R7 ; /* 0x0000000106077824 */
/* 0x001fc600078e0207 */
/*0c30*/ LDS R6, [R2+0x58] ; /* 0x0000580002067984 */
/* 0x000fe80000000800 */
/*0c40*/ STS [R2+0x54], R7 ; /* 0x0000540702007388 */
/* 0x000fe80000000800 */
/*0c50*/ LDS R9, [R4+0x58] ; /* 0x0000580004097984 */
/* 0x000e240000000800 */
/*0c60*/ IMAD.IADD R9, R6, 0x1, R9 ; /* 0x0000000106097824 */
/* 0x001fc400078e0209 */
/*0c70*/ LDS R6, [R2+0x5c] ; /* 0x00005c0002067984 */
/* 0x000fe80000000800 */
/*0c80*/ STS [R2+0x58], R9 ; /* 0x0000580902007388 */
/* 0x000fe80000000800 */
/*0c90*/ LDS R11, [R4+0x5c] ; /* 0x00005c00040b7984 */
/* 0x000e240000000800 */
/*0ca0*/ IMAD.IADD R11, R6, 0x1, R11 ; /* 0x00000001060b7824 */
/* 0x001fca00078e020b */
/*0cb0*/ STS [R2+0x5c], R11 ; /* 0x00005c0b02007388 */
/* 0x000fe80000000800 */
/*0cc0*/ LDS R6, [R4+0x60] ; /* 0x0000600004067984 */
/* 0x000e240000000800 */
/*0cd0*/ IADD3 R5, R5, R6, RZ ; /* 0x0000000605057210 */
/* 0x001fe40007ffe0ff */
/*0ce0*/ LDS R6, [R2+0x64] ; /* 0x0000640002067984 */
/* 0x000fe80000000800 */
/*0cf0*/ STS [R2+0x60], R5 ; /* 0x0000600502007388 */
/* 0x000fe80000000800 */
/*0d00*/ LDS R7, [R4+0x64] ; /* 0x0000640004077984 */
/* 0x000e240000000800 */
/*0d10*/ IMAD.IADD R7, R6, 0x1, R7 ; /* 0x0000000106077824 */
/* 0x001fca00078e0207 */
/*0d20*/ STS [R2+0x64], R7 ; /* 0x0000640702007388 */
/* 0x0001e40000000800 */
/*0d30*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0d40*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0d50*/ ISETP.GT.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fe40003f04270 */
/*0d60*/ SHF.R.S32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fd60000011403 */
/*0d70*/ @P0 BRA 0x660 ; /* 0xfffff8e000000947 */
/* 0x000fea000383ffff */
/*0d80*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0d90*/ ISETP.GT.U32.AND P0, PT, R0, 0x19, PT ; /* 0x000000190000780c */
/* 0x000fda0003f04070 */
/*0da0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0db0*/ LDS R5, [R0.X4] ; /* 0x0000000000057984 */
/* 0x000e620000004800 */
/*0dc0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0dd0*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x001fca00078e0003 */
/*0de0*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x002fe2000c10e184 */
/*0df0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e00*/ BRA 0xe00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/*
Detected 1 CUDA Capable device(s)
Device 0: "GeForce GT 320M"
CUDA Driver Version / Runtime Version 5.0 / 5.0
CUDA Capability Major/Minor version number: 1.2
Total amount of global memory: 1024 MBytes (1073741824 bytes)
( 3) Multiprocessors x ( 8) CUDA Cores/MP: 24 CUDA Cores
GPU Clock rate: 1100 MHz (1.10 GHz)
Memory Clock rate: 790 Mhz
Memory Bus Width: 128-bit
Max Texture Dimension Size (x,y,z) 1D=(8192), 2D=(65536,32768), 3D=(2048,2048,2048)
Max Layered Texture Size (dim) x layers 1D=(8192) x 512, 2D=(8192,8192) x 512
Total amount of constant memory: 65536 bytes
Total amount of shared memory per block: 16384 bytes
Total number of registers available per block: 16384
Warp size: 32
Maximum number of threads per multiprocessor: 1024
Maximum number of threads per block: 512
Maximum sizes of each dimension of a block: 512 x 512 x 64
Maximum sizes of each dimension of a grid: 65535 x 65535 x 1
Maximum memory pitch: 2147483647 bytes
Texture alignment: 256 bytes
Concurrent copy and kernel execution: Yes with 1 copy engine(s)
Run time limit on kernels: Yes
Integrated GPU sharing Host Memory: No
Support host page-locked memory mapping: Yes
Alignment requirement for Surfaces: Yes
Device has ECC support: Disabled
CUDA Device Driver Mode (TCC or WDDM): WDDM (Windows Display Driver Model)
Device supports Unified Addressing (UVA): No
Device PCI Bus ID / PCI location ID: 2 / 0
Compute Mode:
< Default (multiple host threads can use ::cudaSetDevice() with device simultaneously) >
deviceQuery, CUDA Driver = CUDART, CUDA Driver Version = 5.0, CUDA Runtime Version = 5.0, NumDevs = 1, Device0 = GeForce GT 320M
*/
__global__ void freqencyStep1(char *d_dat,int len, int *d_freq)
{//²½ÖèÒ»£¬ÏȽ«Êý¾Ý¼ÓºÍµ½share memoryÖУ¬È»ºóÔÙÀÛ¼Óµ½ÏÔ´æÉÏ¡£
///ÕâÀïÒ²ÓÐÁ½ÖÖ·½·¨£¬ÕâÊÇ·½·¨Ò»£¬share memoryºá×ÅÓá£ÁíÒ»ÖÖ·½·¨£¬½«share memoryÊú×ÅÓã¨ÔÚ½øÐпéÄÚÀÛ¼Óʱ£¬Ö»ÓÃÇ°26¸öÏß³ÌÍê³É0µ½127µÄÀÛ¼Ó¡£¡£
///·½·¨¶þµÄÀÛ¼Óʱ£¬×îºÃÀÛ¼Óµ½¶Ô½ÇÏßÉÏ£¬È»ºóÔÚд³öʱ£¬¿ÉÒÔ±ÜÃâbank conflict¡£
__shared__ int sfreq[3456];//27*128////share memoryºá×Å·Å£¬Ã¿Ïß³Ì27¸öint.
for(int i=threadIdx.x ;i< 3456;i += blockDim.x)
sfreq[i] = 0;////ÏÈÇå¿Õ¡£
__syncthreads();
int *myfreq = &sfreq[27*threadIdx.x];
int gridsize = blockDim.x * gridDim.x;
for(int i=threadIdx.x + blockIdx.x*blockDim.x; i< len; i += gridsize)
//if((d_dat[i]>='a')&&(d_dat[i]<='z'))//Èç¹ûÈ·¶¨Êý¾ÝÖ»ÊÇa--z£¬¿ÉÒÔ°ÑifÈ¥µô¡£
myfreq[d_dat[i]-'a']++;
__syncthreads();///¸÷Ïß³Ìͳ¼Æµ½×Ô¼ºµÄsharememoryÖС£
///ÓÃÒ»¸öÑ»·ÊµÏÖÕÛ°ë¼Ó¡£
for(int roll = 64;roll>=1; roll>>=1)
{
if(threadIdx.x <roll)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+roll)+i];
}
__syncthreads();
}
#if 0
if(threadIdx.x<64)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+64)+i];
}
__syncthreads();
if(threadIdx.x<32)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+32)+i];
}
__syncthreads();
if(threadIdx.x<16)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+16)+i];
}
if(threadIdx.x< 8)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+ 8)+i];
}
if(threadIdx.x< 4)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+ 4)+i];
}
if(threadIdx.x< 2)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+ 2)+i];
}
if(threadIdx.x == 0)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x )+i];
}
#endif
__syncthreads();
if(threadIdx.x<26)///Èç¹ûÏÔ¿¨Ö§³ÖÔ×Ó¼Ó£¬¿ÉÒÔʹÓÃÔ×Ó¼Ó£¬Ö±½Ó¼Óµ½ÏÔ´æÉÏ¡£ÄÇÑù¾ÍûÓеڶþ²½¡£ 1.1¼°ÒÔÉÏÖ§³ÖÈ«¾ÖÏÔ´æµÄ32λÔ×Ó²Ù×÷¡£
atomicAdd(&d_freq[threadIdx.x],sfreq[threadIdx.x]);
} | .file "tmpxft_00057c71_00000000-6_freqencyStep1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z13freqencyStep1PciPiPciPi
.type _Z36__device_stub__Z13freqencyStep1PciPiPciPi, @function
_Z36__device_stub__Z13freqencyStep1PciPiPciPi:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13freqencyStep1PciPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z13freqencyStep1PciPiPciPi, .-_Z36__device_stub__Z13freqencyStep1PciPiPciPi
.globl _Z13freqencyStep1PciPi
.type _Z13freqencyStep1PciPi, @function
_Z13freqencyStep1PciPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13freqencyStep1PciPiPciPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13freqencyStep1PciPi, .-_Z13freqencyStep1PciPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13freqencyStep1PciPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13freqencyStep1PciPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/*
Detected 1 CUDA Capable device(s)
Device 0: "GeForce GT 320M"
CUDA Driver Version / Runtime Version 5.0 / 5.0
CUDA Capability Major/Minor version number: 1.2
Total amount of global memory: 1024 MBytes (1073741824 bytes)
( 3) Multiprocessors x ( 8) CUDA Cores/MP: 24 CUDA Cores
GPU Clock rate: 1100 MHz (1.10 GHz)
Memory Clock rate: 790 Mhz
Memory Bus Width: 128-bit
Max Texture Dimension Size (x,y,z) 1D=(8192), 2D=(65536,32768), 3D=(2048,2048,2048)
Max Layered Texture Size (dim) x layers 1D=(8192) x 512, 2D=(8192,8192) x 512
Total amount of constant memory: 65536 bytes
Total amount of shared memory per block: 16384 bytes
Total number of registers available per block: 16384
Warp size: 32
Maximum number of threads per multiprocessor: 1024
Maximum number of threads per block: 512
Maximum sizes of each dimension of a block: 512 x 512 x 64
Maximum sizes of each dimension of a grid: 65535 x 65535 x 1
Maximum memory pitch: 2147483647 bytes
Texture alignment: 256 bytes
Concurrent copy and kernel execution: Yes with 1 copy engine(s)
Run time limit on kernels: Yes
Integrated GPU sharing Host Memory: No
Support host page-locked memory mapping: Yes
Alignment requirement for Surfaces: Yes
Device has ECC support: Disabled
CUDA Device Driver Mode (TCC or WDDM): WDDM (Windows Display Driver Model)
Device supports Unified Addressing (UVA): No
Device PCI Bus ID / PCI location ID: 2 / 0
Compute Mode:
< Default (multiple host threads can use ::cudaSetDevice() with device simultaneously) >
deviceQuery, CUDA Driver = CUDART, CUDA Driver Version = 5.0, CUDA Runtime Version = 5.0, NumDevs = 1, Device0 = GeForce GT 320M
*/
__global__ void freqencyStep1(char *d_dat,int len, int *d_freq)
{//²½ÖèÒ»£¬ÏȽ«Êý¾Ý¼ÓºÍµ½share memoryÖУ¬È»ºóÔÙÀÛ¼Óµ½ÏÔ´æÉÏ¡£
///ÕâÀïÒ²ÓÐÁ½ÖÖ·½·¨£¬ÕâÊÇ·½·¨Ò»£¬share memoryºá×ÅÓá£ÁíÒ»ÖÖ·½·¨£¬½«share memoryÊú×ÅÓã¨ÔÚ½øÐпéÄÚÀÛ¼Óʱ£¬Ö»ÓÃÇ°26¸öÏß³ÌÍê³É0µ½127µÄÀÛ¼Ó¡£¡£
///·½·¨¶þµÄÀÛ¼Óʱ£¬×îºÃÀÛ¼Óµ½¶Ô½ÇÏßÉÏ£¬È»ºóÔÚд³öʱ£¬¿ÉÒÔ±ÜÃâbank conflict¡£
__shared__ int sfreq[3456];//27*128////share memoryºá×Å·Å£¬Ã¿Ïß³Ì27¸öint.
for(int i=threadIdx.x ;i< 3456;i += blockDim.x)
sfreq[i] = 0;////ÏÈÇå¿Õ¡£
__syncthreads();
int *myfreq = &sfreq[27*threadIdx.x];
int gridsize = blockDim.x * gridDim.x;
for(int i=threadIdx.x + blockIdx.x*blockDim.x; i< len; i += gridsize)
//if((d_dat[i]>='a')&&(d_dat[i]<='z'))//Èç¹ûÈ·¶¨Êý¾ÝÖ»ÊÇa--z£¬¿ÉÒÔ°ÑifÈ¥µô¡£
myfreq[d_dat[i]-'a']++;
__syncthreads();///¸÷Ïß³Ìͳ¼Æµ½×Ô¼ºµÄsharememoryÖС£
///ÓÃÒ»¸öÑ»·ÊµÏÖÕÛ°ë¼Ó¡£
for(int roll = 64;roll>=1; roll>>=1)
{
if(threadIdx.x <roll)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+roll)+i];
}
__syncthreads();
}
#if 0
if(threadIdx.x<64)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+64)+i];
}
__syncthreads();
if(threadIdx.x<32)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+32)+i];
}
__syncthreads();
if(threadIdx.x<16)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+16)+i];
}
if(threadIdx.x< 8)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+ 8)+i];
}
if(threadIdx.x< 4)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+ 4)+i];
}
if(threadIdx.x< 2)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+ 2)+i];
}
if(threadIdx.x == 0)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x )+i];
}
#endif
__syncthreads();
if(threadIdx.x<26)///Èç¹ûÏÔ¿¨Ö§³ÖÔ×Ó¼Ó£¬¿ÉÒÔʹÓÃÔ×Ó¼Ó£¬Ö±½Ó¼Óµ½ÏÔ´æÉÏ¡£ÄÇÑù¾ÍûÓеڶþ²½¡£ 1.1¼°ÒÔÉÏÖ§³ÖÈ«¾ÖÏÔ´æµÄ32λÔ×Ó²Ù×÷¡£
atomicAdd(&d_freq[threadIdx.x],sfreq[threadIdx.x]);
} | #include <hip/hip_runtime.h>
#include "includes.h"
/*
Detected 1 CUDA Capable device(s)
Device 0: "GeForce GT 320M"
CUDA Driver Version / Runtime Version 5.0 / 5.0
CUDA Capability Major/Minor version number: 1.2
Total amount of global memory: 1024 MBytes (1073741824 bytes)
( 3) Multiprocessors x ( 8) CUDA Cores/MP: 24 CUDA Cores
GPU Clock rate: 1100 MHz (1.10 GHz)
Memory Clock rate: 790 Mhz
Memory Bus Width: 128-bit
Max Texture Dimension Size (x,y,z) 1D=(8192), 2D=(65536,32768), 3D=(2048,2048,2048)
Max Layered Texture Size (dim) x layers 1D=(8192) x 512, 2D=(8192,8192) x 512
Total amount of constant memory: 65536 bytes
Total amount of shared memory per block: 16384 bytes
Total number of registers available per block: 16384
Warp size: 32
Maximum number of threads per multiprocessor: 1024
Maximum number of threads per block: 512
Maximum sizes of each dimension of a block: 512 x 512 x 64
Maximum sizes of each dimension of a grid: 65535 x 65535 x 1
Maximum memory pitch: 2147483647 bytes
Texture alignment: 256 bytes
Concurrent copy and kernel execution: Yes with 1 copy engine(s)
Run time limit on kernels: Yes
Integrated GPU sharing Host Memory: No
Support host page-locked memory mapping: Yes
Alignment requirement for Surfaces: Yes
Device has ECC support: Disabled
CUDA Device Driver Mode (TCC or WDDM): WDDM (Windows Display Driver Model)
Device supports Unified Addressing (UVA): No
Device PCI Bus ID / PCI location ID: 2 / 0
Compute Mode:
< Default (multiple host threads can use ::cudaSetDevice() with device simultaneously) >
deviceQuery, CUDA Driver = CUDART, CUDA Driver Version = 5.0, CUDA Runtime Version = 5.0, NumDevs = 1, Device0 = GeForce GT 320M
*/
__global__ void freqencyStep1(char *d_dat,int len, int *d_freq)
{//²½ÖèÒ»£¬ÏȽ«Êý¾Ý¼ÓºÍµ½share memoryÖУ¬È»ºóÔÙÀÛ¼Óµ½ÏÔ´æÉÏ¡£
///ÕâÀïÒ²ÓÐÁ½ÖÖ·½·¨£¬ÕâÊÇ·½·¨Ò»£¬share memoryºá×ÅÓá£ÁíÒ»ÖÖ·½·¨£¬½«share memoryÊú×ÅÓã¨ÔÚ½øÐпéÄÚÀÛ¼Óʱ£¬Ö»ÓÃÇ°26¸öÏß³ÌÍê³É0µ½127µÄÀÛ¼Ó¡£¡£
///·½·¨¶þµÄÀÛ¼Óʱ£¬×îºÃÀÛ¼Óµ½¶Ô½ÇÏßÉÏ£¬È»ºóÔÚд³öʱ£¬¿ÉÒÔ±ÜÃâbank conflict¡£
__shared__ int sfreq[3456];//27*128////share memoryºá×Å·Å£¬Ã¿Ïß³Ì27¸öint.
for(int i=threadIdx.x ;i< 3456;i += blockDim.x)
sfreq[i] = 0;////ÏÈÇå¿Õ¡£
__syncthreads();
int *myfreq = &sfreq[27*threadIdx.x];
int gridsize = blockDim.x * gridDim.x;
for(int i=threadIdx.x + blockIdx.x*blockDim.x; i< len; i += gridsize)
//if((d_dat[i]>='a')&&(d_dat[i]<='z'))//Èç¹ûÈ·¶¨Êý¾ÝÖ»ÊÇa--z£¬¿ÉÒÔ°ÑifÈ¥µô¡£
myfreq[d_dat[i]-'a']++;
__syncthreads();///¸÷Ïß³Ìͳ¼Æµ½×Ô¼ºµÄsharememoryÖС£
///ÓÃÒ»¸öÑ»·ÊµÏÖÕÛ°ë¼Ó¡£
for(int roll = 64;roll>=1; roll>>=1)
{
if(threadIdx.x <roll)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+roll)+i];
}
__syncthreads();
}
#if 0
if(threadIdx.x<64)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+64)+i];
}
__syncthreads();
if(threadIdx.x<32)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+32)+i];
}
__syncthreads();
if(threadIdx.x<16)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+16)+i];
}
if(threadIdx.x< 8)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+ 8)+i];
}
if(threadIdx.x< 4)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+ 4)+i];
}
if(threadIdx.x< 2)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+ 2)+i];
}
if(threadIdx.x == 0)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x )+i];
}
#endif
__syncthreads();
if(threadIdx.x<26)///Èç¹ûÏÔ¿¨Ö§³ÖÔ×Ó¼Ó£¬¿ÉÒÔʹÓÃÔ×Ó¼Ó£¬Ö±½Ó¼Óµ½ÏÔ´æÉÏ¡£ÄÇÑù¾ÍûÓеڶþ²½¡£ 1.1¼°ÒÔÉÏÖ§³ÖÈ«¾ÖÏÔ´æµÄ32λÔ×Ó²Ù×÷¡£
atomicAdd(&d_freq[threadIdx.x],sfreq[threadIdx.x]);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/*
Detected 1 CUDA Capable device(s)
Device 0: "GeForce GT 320M"
CUDA Driver Version / Runtime Version 5.0 / 5.0
CUDA Capability Major/Minor version number: 1.2
Total amount of global memory: 1024 MBytes (1073741824 bytes)
( 3) Multiprocessors x ( 8) CUDA Cores/MP: 24 CUDA Cores
GPU Clock rate: 1100 MHz (1.10 GHz)
Memory Clock rate: 790 Mhz
Memory Bus Width: 128-bit
Max Texture Dimension Size (x,y,z) 1D=(8192), 2D=(65536,32768), 3D=(2048,2048,2048)
Max Layered Texture Size (dim) x layers 1D=(8192) x 512, 2D=(8192,8192) x 512
Total amount of constant memory: 65536 bytes
Total amount of shared memory per block: 16384 bytes
Total number of registers available per block: 16384
Warp size: 32
Maximum number of threads per multiprocessor: 1024
Maximum number of threads per block: 512
Maximum sizes of each dimension of a block: 512 x 512 x 64
Maximum sizes of each dimension of a grid: 65535 x 65535 x 1
Maximum memory pitch: 2147483647 bytes
Texture alignment: 256 bytes
Concurrent copy and kernel execution: Yes with 1 copy engine(s)
Run time limit on kernels: Yes
Integrated GPU sharing Host Memory: No
Support host page-locked memory mapping: Yes
Alignment requirement for Surfaces: Yes
Device has ECC support: Disabled
CUDA Device Driver Mode (TCC or WDDM): WDDM (Windows Display Driver Model)
Device supports Unified Addressing (UVA): No
Device PCI Bus ID / PCI location ID: 2 / 0
Compute Mode:
< Default (multiple host threads can use ::cudaSetDevice() with device simultaneously) >
deviceQuery, CUDA Driver = CUDART, CUDA Driver Version = 5.0, CUDA Runtime Version = 5.0, NumDevs = 1, Device0 = GeForce GT 320M
*/
__global__ void freqencyStep1(char *d_dat,int len, int *d_freq)
{//²½ÖèÒ»£¬ÏȽ«Êý¾Ý¼ÓºÍµ½share memoryÖУ¬È»ºóÔÙÀÛ¼Óµ½ÏÔ´æÉÏ¡£
///ÕâÀïÒ²ÓÐÁ½ÖÖ·½·¨£¬ÕâÊÇ·½·¨Ò»£¬share memoryºá×ÅÓá£ÁíÒ»ÖÖ·½·¨£¬½«share memoryÊú×ÅÓã¨ÔÚ½øÐпéÄÚÀÛ¼Óʱ£¬Ö»ÓÃÇ°26¸öÏß³ÌÍê³É0µ½127µÄÀÛ¼Ó¡£¡£
///·½·¨¶þµÄÀÛ¼Óʱ£¬×îºÃÀÛ¼Óµ½¶Ô½ÇÏßÉÏ£¬È»ºóÔÚд³öʱ£¬¿ÉÒÔ±ÜÃâbank conflict¡£
__shared__ int sfreq[3456];//27*128////share memoryºá×Å·Å£¬Ã¿Ïß³Ì27¸öint.
for(int i=threadIdx.x ;i< 3456;i += blockDim.x)
sfreq[i] = 0;////ÏÈÇå¿Õ¡£
__syncthreads();
int *myfreq = &sfreq[27*threadIdx.x];
int gridsize = blockDim.x * gridDim.x;
for(int i=threadIdx.x + blockIdx.x*blockDim.x; i< len; i += gridsize)
//if((d_dat[i]>='a')&&(d_dat[i]<='z'))//Èç¹ûÈ·¶¨Êý¾ÝÖ»ÊÇa--z£¬¿ÉÒÔ°ÑifÈ¥µô¡£
myfreq[d_dat[i]-'a']++;
__syncthreads();///¸÷Ïß³Ìͳ¼Æµ½×Ô¼ºµÄsharememoryÖС£
///ÓÃÒ»¸öÑ»·ÊµÏÖÕÛ°ë¼Ó¡£
for(int roll = 64;roll>=1; roll>>=1)
{
if(threadIdx.x <roll)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+roll)+i];
}
__syncthreads();
}
#if 0
if(threadIdx.x<64)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+64)+i];
}
__syncthreads();
if(threadIdx.x<32)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+32)+i];
}
__syncthreads();
if(threadIdx.x<16)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+16)+i];
}
if(threadIdx.x< 8)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+ 8)+i];
}
if(threadIdx.x< 4)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+ 4)+i];
}
if(threadIdx.x< 2)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+ 2)+i];
}
if(threadIdx.x == 0)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x )+i];
}
#endif
__syncthreads();
if(threadIdx.x<26)///Èç¹ûÏÔ¿¨Ö§³ÖÔ×Ó¼Ó£¬¿ÉÒÔʹÓÃÔ×Ó¼Ó£¬Ö±½Ó¼Óµ½ÏÔ´æÉÏ¡£ÄÇÑù¾ÍûÓеڶþ²½¡£ 1.1¼°ÒÔÉÏÖ§³ÖÈ«¾ÖÏÔ´æµÄ32λÔ×Ó²Ù×÷¡£
atomicAdd(&d_freq[threadIdx.x],sfreq[threadIdx.x]);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13freqencyStep1PciPi
.globl _Z13freqencyStep1PciPi
.p2align 8
.type _Z13freqencyStep1PciPi,@function
_Z13freqencyStep1PciPi:
s_load_b32 s2, s[0:1], 0x24
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v2, 2, v0
v_mov_b32_e32 v3, v0
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s4, s2, 2
.LBB0_1:
v_add_nc_u32_e32 v3, s2, v3
ds_store_b32 v2, v1
v_add_nc_u32_e32 v2, s4, v2
v_cmp_lt_u32_e32 vcc_lo, 0xd7f, v3
s_or_b32 s3, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_1
s_or_b32 exec_lo, exec_lo, s3
s_clause 0x1
s_load_b32 s5, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x8
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s6, s5, 0xffff
s_mov_b32 s5, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
v_mul_u32_u24_e32 v2, 27, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v4, 2, v2
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_5
s_load_b32 s2, s[2:3], 0x0
s_load_b64 s[8:9], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v1
v_add_nc_u32_e32 v5, 0xfffffe7c, v4
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s2, s6
v_add_co_u32 v2, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_ashr_i32 s6, s3, 31
.p2align 6
.LBB0_4:
global_load_i8 v6, v[2:3], off
v_add_nc_u32_e32 v1, s3, v1
v_add_co_u32 v2, vcc_lo, v2, s3
v_add_co_ci_u32_e32 v3, vcc_lo, s6, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s2, s4, v1
s_or_b32 s7, s2, s7
s_waitcnt vmcnt(0)
v_lshl_add_u32 v6, v6, 2, v5
ds_load_b32 v7, v6
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v7, 1, v7
ds_store_b32 v6, v7
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_4
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s5
s_mov_b32 s2, 64
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_7
.p2align 6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s3
s_lshr_b32 s3, s2, 1
s_cmp_lt_u32 s2, 2
s_mov_b32 s2, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_10
.LBB0_7:
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB0_6
v_add_nc_u32_e32 v1, s2, v0
s_mov_b32 s4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_u32_u24_e32 v1, 27, v1
v_lshlrev_b32_e32 v1, 2, v1
.LBB0_9:
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v2, s4, v1
v_add_nc_u32_e32 v3, s4, v4
s_add_i32 s4, s4, 4
ds_load_b32 v2, v2
ds_load_b32 v5, v3
s_cmpk_lg_i32 s4, 0x68
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v5, v2
ds_store_b32 v3, v2
s_cbranch_scc1 .LBB0_9
s_branch .LBB0_6
.LBB0_10:
s_set_inst_prefetch_distance 0x2
s_barrier
buffer_gl0_inv
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 26, v0
s_cbranch_execz .LBB0_12
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13freqencyStep1PciPi
.amdhsa_group_segment_fixed_size 13824
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13freqencyStep1PciPi, .Lfunc_end0-_Z13freqencyStep1PciPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 13824
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13freqencyStep1PciPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13freqencyStep1PciPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/*
Detected 1 CUDA Capable device(s)
Device 0: "GeForce GT 320M"
CUDA Driver Version / Runtime Version 5.0 / 5.0
CUDA Capability Major/Minor version number: 1.2
Total amount of global memory: 1024 MBytes (1073741824 bytes)
( 3) Multiprocessors x ( 8) CUDA Cores/MP: 24 CUDA Cores
GPU Clock rate: 1100 MHz (1.10 GHz)
Memory Clock rate: 790 Mhz
Memory Bus Width: 128-bit
Max Texture Dimension Size (x,y,z) 1D=(8192), 2D=(65536,32768), 3D=(2048,2048,2048)
Max Layered Texture Size (dim) x layers 1D=(8192) x 512, 2D=(8192,8192) x 512
Total amount of constant memory: 65536 bytes
Total amount of shared memory per block: 16384 bytes
Total number of registers available per block: 16384
Warp size: 32
Maximum number of threads per multiprocessor: 1024
Maximum number of threads per block: 512
Maximum sizes of each dimension of a block: 512 x 512 x 64
Maximum sizes of each dimension of a grid: 65535 x 65535 x 1
Maximum memory pitch: 2147483647 bytes
Texture alignment: 256 bytes
Concurrent copy and kernel execution: Yes with 1 copy engine(s)
Run time limit on kernels: Yes
Integrated GPU sharing Host Memory: No
Support host page-locked memory mapping: Yes
Alignment requirement for Surfaces: Yes
Device has ECC support: Disabled
CUDA Device Driver Mode (TCC or WDDM): WDDM (Windows Display Driver Model)
Device supports Unified Addressing (UVA): No
Device PCI Bus ID / PCI location ID: 2 / 0
Compute Mode:
< Default (multiple host threads can use ::cudaSetDevice() with device simultaneously) >
deviceQuery, CUDA Driver = CUDART, CUDA Driver Version = 5.0, CUDA Runtime Version = 5.0, NumDevs = 1, Device0 = GeForce GT 320M
*/
__global__ void freqencyStep1(char *d_dat,int len, int *d_freq)
{//²½ÖèÒ»£¬ÏȽ«Êý¾Ý¼ÓºÍµ½share memoryÖУ¬È»ºóÔÙÀÛ¼Óµ½ÏÔ´æÉÏ¡£
///ÕâÀïÒ²ÓÐÁ½ÖÖ·½·¨£¬ÕâÊÇ·½·¨Ò»£¬share memoryºá×ÅÓá£ÁíÒ»ÖÖ·½·¨£¬½«share memoryÊú×ÅÓã¨ÔÚ½øÐпéÄÚÀÛ¼Óʱ£¬Ö»ÓÃÇ°26¸öÏß³ÌÍê³É0µ½127µÄÀÛ¼Ó¡£¡£
///·½·¨¶þµÄÀÛ¼Óʱ£¬×îºÃÀÛ¼Óµ½¶Ô½ÇÏßÉÏ£¬È»ºóÔÚд³öʱ£¬¿ÉÒÔ±ÜÃâbank conflict¡£
__shared__ int sfreq[3456];//27*128////share memoryºá×Å·Å£¬Ã¿Ïß³Ì27¸öint.
for(int i=threadIdx.x ;i< 3456;i += blockDim.x)
sfreq[i] = 0;////ÏÈÇå¿Õ¡£
__syncthreads();
int *myfreq = &sfreq[27*threadIdx.x];
int gridsize = blockDim.x * gridDim.x;
for(int i=threadIdx.x + blockIdx.x*blockDim.x; i< len; i += gridsize)
//if((d_dat[i]>='a')&&(d_dat[i]<='z'))//Èç¹ûÈ·¶¨Êý¾ÝÖ»ÊÇa--z£¬¿ÉÒÔ°ÑifÈ¥µô¡£
myfreq[d_dat[i]-'a']++;
__syncthreads();///¸÷Ïß³Ìͳ¼Æµ½×Ô¼ºµÄsharememoryÖС£
///ÓÃÒ»¸öÑ»·ÊµÏÖÕÛ°ë¼Ó¡£
for(int roll = 64;roll>=1; roll>>=1)
{
if(threadIdx.x <roll)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+roll)+i];
}
__syncthreads();
}
#if 0
if(threadIdx.x<64)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+64)+i];
}
__syncthreads();
if(threadIdx.x<32)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+32)+i];
}
__syncthreads();
if(threadIdx.x<16)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+16)+i];
}
if(threadIdx.x< 8)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+ 8)+i];
}
if(threadIdx.x< 4)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+ 4)+i];
}
if(threadIdx.x< 2)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x+ 2)+i];
}
if(threadIdx.x == 0)
{
for(int i=0;i<26;i++)
myfreq[i] += sfreq[27*(threadIdx.x )+i];
}
#endif
__syncthreads();
if(threadIdx.x<26)///Èç¹ûÏÔ¿¨Ö§³ÖÔ×Ó¼Ó£¬¿ÉÒÔʹÓÃÔ×Ó¼Ó£¬Ö±½Ó¼Óµ½ÏÔ´æÉÏ¡£ÄÇÑù¾ÍûÓеڶþ²½¡£ 1.1¼°ÒÔÉÏÖ§³ÖÈ«¾ÖÏÔ´æµÄ32λÔ×Ó²Ù×÷¡£
atomicAdd(&d_freq[threadIdx.x],sfreq[threadIdx.x]);
} | .text
.file "freqencyStep1.hip"
.globl _Z28__device_stub__freqencyStep1PciPi # -- Begin function _Z28__device_stub__freqencyStep1PciPi
.p2align 4, 0x90
.type _Z28__device_stub__freqencyStep1PciPi,@function
_Z28__device_stub__freqencyStep1PciPi: # @_Z28__device_stub__freqencyStep1PciPi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13freqencyStep1PciPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__freqencyStep1PciPi, .Lfunc_end0-_Z28__device_stub__freqencyStep1PciPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13freqencyStep1PciPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13freqencyStep1PciPi,@object # @_Z13freqencyStep1PciPi
.section .rodata,"a",@progbits
.globl _Z13freqencyStep1PciPi
.p2align 3, 0x0
_Z13freqencyStep1PciPi:
.quad _Z28__device_stub__freqencyStep1PciPi
.size _Z13freqencyStep1PciPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13freqencyStep1PciPi"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__freqencyStep1PciPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13freqencyStep1PciPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13freqencyStep1PciPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ BSSY B0, 0xc0 ; /* 0x0000009000007945 */
/* 0x000fe60003800000 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0040*/ ISETP.GE.AND P0, PT, R0, 0xd80, PT ; /* 0x00000d800000780c */
/* 0x001fda0003f06270 */
/*0050*/ @P0 BRA 0xb0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x002fca00078e0000 */
/*0070*/ STS [R2.X4], RZ ; /* 0x000000ff02007388 */
/* 0x0001e40000004800 */
/*0080*/ IADD3 R2, R2, c[0x0][0x0], RZ ; /* 0x0000000002027a10 */
/* 0x001fc80007ffe0ff */
/*0090*/ ISETP.GE.AND P0, PT, R2, 0xd80, PT ; /* 0x00000d800200780c */
/* 0x000fda0003f06270 */
/*00a0*/ @!P0 BRA 0x70 ; /* 0xffffffc000008947 */
/* 0x000fea000383ffff */
/*00b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*00c0*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x000fe200078e0200 */
/*00d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe80000010000 */
/*00e0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fe40003f06270 */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0100*/ BSSY B0, 0x630 ; /* 0x0000052000007945 */
/* 0x000ff40003800000 */
/*0110*/ @P0 BRA 0x620 ; /* 0x0000050000000947 */
/* 0x000fea0003800000 */
/*0120*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff027624 */
/* 0x000fe200078e00ff */
/*0130*/ BSSY B1, 0x400 ; /* 0x000002c000017945 */
/* 0x000fe60003800000 */
/*0140*/ IMAD R2, R2, c[0x0][0xc], RZ ; /* 0x0000030002027a24 */
/* 0x000fc800078e02ff */
/*0150*/ I2F.U32.RP R6, R2 ; /* 0x0000000200067306 */
/* 0x000e220000209000 */
/*0160*/ IADD3 R4, R2.reuse, R3, RZ ; /* 0x0000000302047210 */
/* 0x040fe20007ffe0ff */
/*0170*/ IMAD.MOV R9, RZ, RZ, -R2 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a02 */
/*0180*/ ISETP.NE.U32.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f45070 */
/*0190*/ LOP3.LUT R7, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff077212 */
/* 0x000fe200078e33ff */
/*01a0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc600078e00ff */
/*01b0*/ IADD3 R7, R7, c[0x0][0x168], R2 ; /* 0x00005a0007077a10 */
/* 0x000fe20007ffe002 */
/*01c0*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*01d0*/ IADD3 R5, R6, 0xffffffe, RZ ; /* 0x0ffffffe06057810 */
/* 0x001fcc0007ffe0ff */
/*01e0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e24000021f000 */
/*01f0*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x001fc800078e02ff */
/*0200*/ IMAD.HI.U32 R4, R5, R9, R4 ; /* 0x0000000905047227 */
/* 0x000fcc00078e0004 */
/*0210*/ IMAD.HI.U32 R4, R4, R7, RZ ; /* 0x0000000704047227 */
/* 0x000fc800078e00ff */
/*0220*/ IMAD.MOV R5, RZ, RZ, -R4 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a04 */
/*0230*/ IMAD R7, R2, R5, R7 ; /* 0x0000000502077224 */
/* 0x000fca00078e0207 */
/*0240*/ ISETP.GE.U32.AND P0, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fda0003f06070 */
/*0250*/ @P0 IMAD.IADD R7, R7, 0x1, -R2 ; /* 0x0000000107070824 */
/* 0x000fe200078e0a02 */
/*0260*/ @P0 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104040810 */
/* 0x000fc80007ffe0ff */
/*0270*/ ISETP.GE.U32.AND P1, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fe20003f26070 */
/*0280*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1b ; /* 0x0000001bff077424 */
/* 0x000fd800078e00ff */
/*0290*/ @P1 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104041810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ @!P2 LOP3.LUT R4, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff04a212 */
/* 0x000fc800078e33ff */
/*02b0*/ IADD3 R5, R4.reuse, 0x1, RZ ; /* 0x0000000104057810 */
/* 0x040fe40007ffe0ff */
/*02c0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f06070 */
/*02d0*/ IMAD R4, R0, R7, -0x61 ; /* 0xffffff9f00047424 */
/* 0x000fe200078e0207 */
/*02e0*/ LOP3.LUT P1, R5, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305057812 */
/* 0x000fda000782c0ff */
/*02f0*/ @!P1 BRA 0x3f0 ; /* 0x000000f000009947 */
/* 0x000fea0003800000 */
/*0300*/ IADD3 R11, P1, R3, c[0x0][0x160], RZ ; /* 0x00005800030b7a10 */
/* 0x000fc80007f3e0ff */
/*0310*/ LEA.HI.X.SX32 R10, R3, c[0x0][0x164], 0x1, P1 ; /* 0x00005900030a7a11 */
/* 0x000fca00008f0eff */
/*0320*/ IMAD.MOV.U32 R7, RZ, RZ, R10 ; /* 0x000000ffff077224 */
/* 0x000fe200078e000a */
/*0330*/ MOV R6, R11 ; /* 0x0000000b00067202 */
/* 0x000fca0000000f00 */
/*0340*/ LDG.E.S8 R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea2000c1e1300 */
/*0350*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe20007ffe0ff */
/*0360*/ IMAD.IADD R3, R2.reuse, 0x1, R3 ; /* 0x0000000102037824 */
/* 0x040fe200078e0203 */
/*0370*/ IADD3 R11, P2, R2.reuse, R11, RZ ; /* 0x0000000b020b7210 */
/* 0x040fe40007f5e0ff */
/*0380*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f25270 */
/*0390*/ LEA.HI.X.SX32 R10, R2, R10, 0x1, P2 ; /* 0x0000000a020a7211 */
/* 0x000fe200010f0eff */
/*03a0*/ IMAD.IADD R8, R4, 0x1, R7 ; /* 0x0000000104087824 */
/* 0x005fca00078e0207 */
/*03b0*/ LDS R9, [R8.X4] ; /* 0x0000000008097984 */
/* 0x000e240000004800 */
/*03c0*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x001fca0007ffe0ff */
/*03d0*/ STS [R8.X4], R9 ; /* 0x0000000908007388 */
/* 0x0001e20000004800 */
/*03e0*/ @P1 BRA 0x320 ; /* 0xffffff3000001947 */
/* 0x000fea000383ffff */
/*03f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0400*/ @!P0 BRA 0x620 ; /* 0x0000021000008947 */
/* 0x000fea0003800000 */
/*0410*/ SHF.R.S32.HI R5, RZ, 0x1f, R2 ; /* 0x0000001fff057819 */
/* 0x000fe40000011402 */
/*0420*/ IADD3 R6, P0, R3, c[0x0][0x160], RZ ; /* 0x0000580003067a10 */
/* 0x000fc80007f1e0ff */
/*0430*/ LEA.HI.X.SX32 R7, R3, c[0x0][0x164], 0x1, P0 ; /* 0x0000590003077a11 */
/* 0x000fca00000f0eff */
/*0440*/ LDG.E.S8 R15, [R6.64] ; /* 0x00000004060f7981 */
/* 0x000ea2000c1e1300 */
/*0450*/ IADD3 R8, P0, R2, R6, RZ ; /* 0x0000000602087210 */
/* 0x001fca0007f1e0ff */
/*0460*/ IMAD.X R9, R5, 0x1, R7, P0 ; /* 0x0000000105097824 */
/* 0x000fca00000e0607 */
/*0470*/ LDG.E.S8 R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000ee2000c1e1300 */
/*0480*/ IADD3 R10, P0, R2, R8, RZ ; /* 0x00000008020a7210 */
/* 0x000fc80007f1e0ff */
/*0490*/ IADD3.X R11, R5, R9, RZ, P0, !PT ; /* 0x00000009050b7210 */
/* 0x000fca00007fe4ff */
/*04a0*/ LDG.E.S8 R19, [R10.64] ; /* 0x000000040a137981 */
/* 0x000f22000c1e1300 */
/*04b0*/ IADD3 R12, P0, R2, R10, RZ ; /* 0x0000000a020c7210 */
/* 0x000fca0007f1e0ff */
/*04c0*/ IMAD.X R13, R5, 0x1, R11, P0 ; /* 0x00000001050d7824 */
/* 0x000fcc00000e060b */
/*04d0*/ LDG.E.S8 R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000f62000c1e1300 */
/*04e0*/ IADD3 R3, R2, R3, R2 ; /* 0x0000000302037210 */
/* 0x000fc80007ffe002 */
/*04f0*/ IADD3 R3, R2, R3, R2 ; /* 0x0000000302037210 */
/* 0x000fc80007ffe002 */
/*0500*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fe20003f06270 */
/*0510*/ IMAD.IADD R15, R4, 0x1, R15 ; /* 0x00000001040f7824 */
/* 0x004fca00078e020f */
/*0520*/ LDS R6, [R15.X4] ; /* 0x000000000f067984 */
/* 0x000e220000004800 */
/*0530*/ IMAD.IADD R17, R4.reuse, 0x1, R17 ; /* 0x0000000104117824 */
/* 0x048fe200078e0211 */
/*0540*/ IADD3 R19, R4.reuse, R19, RZ ; /* 0x0000001304137210 */
/* 0x050fe20007ffe0ff */
/*0550*/ IMAD.IADD R13, R4, 0x1, R13 ; /* 0x00000001040d7824 */
/* 0x020fe200078e020d */
/*0560*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x001fca0007ffe0ff */
/*0570*/ STS [R15.X4], R6 ; /* 0x000000060f007388 */
/* 0x000fe80000004800 */
/*0580*/ LDS R7, [R17.X4] ; /* 0x0000000011077984 */
/* 0x000e240000004800 */
/*0590*/ IADD3 R8, R7, 0x1, RZ ; /* 0x0000000107087810 */
/* 0x001fca0007ffe0ff */
/*05a0*/ STS [R17.X4], R8 ; /* 0x0000000811007388 */
/* 0x000fe80000004800 */
/*05b0*/ LDS R7, [R19.X4] ; /* 0x0000000013077984 */
/* 0x000e240000004800 */
/*05c0*/ IADD3 R10, R7, 0x1, RZ ; /* 0x00000001070a7810 */
/* 0x001fca0007ffe0ff */
/*05d0*/ STS [R19.X4], R10 ; /* 0x0000000a13007388 */
/* 0x000fe80000004800 */
/*05e0*/ LDS R7, [R13.X4] ; /* 0x000000000d077984 */
/* 0x000e240000004800 */
/*05f0*/ IADD3 R12, R7, 0x1, RZ ; /* 0x00000001070c7810 */
/* 0x001fca0007ffe0ff */
/*0600*/ STS [R13.X4], R12 ; /* 0x0000000c0d007388 */
/* 0x0001e20000004800 */
/*0610*/ @!P0 BRA 0x420 ; /* 0xfffffe0000008947 */
/* 0x000fea000383ffff */
/*0620*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0630*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0640*/ IMAD R2, R0, 0x6c, RZ ; /* 0x0000006c00027824 */
/* 0x000fe400078e02ff */
/*0650*/ IMAD.MOV.U32 R3, RZ, RZ, 0x40 ; /* 0x00000040ff037424 */
/* 0x000fca00078e00ff */
/*0660*/ ISETP.GE.U32.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x000fe20003f06070 */
/*0670*/ BSSY B0, 0xd40 ; /* 0x000006c000007945 */
/* 0x000fd80003800000 */
/*0680*/ @P0 BRA 0xd30 ; /* 0x000006a000000947 */
/* 0x001fea0003800000 */
/*0690*/ IMAD.IADD R4, R0, 0x1, R3 ; /* 0x0000000100047824 */
/* 0x000fe200078e0203 */
/*06a0*/ LDS R5, [R2] ; /* 0x0000000002057984 */
/* 0x000fe60000000800 */
/*06b0*/ IMAD R4, R4, 0x6c, RZ ; /* 0x0000006c04047824 */
/* 0x000fca00078e02ff */
/*06c0*/ LDS R6, [R4] ; /* 0x0000000004067984 */
/* 0x000e640000000800 */
/*06d0*/ IADD3 R5, R5, R6, RZ ; /* 0x0000000605057210 */
/* 0x002fe40007ffe0ff */
/*06e0*/ LDS R6, [R2+0x4] ; /* 0x0000040002067984 */
/* 0x000fe80000000800 */
/*06f0*/ STS [R2], R5 ; /* 0x0000000502007388 */
/* 0x000fe80000000800 */
/*0700*/ LDS R7, [R4+0x4] ; /* 0x0000040004077984 */
/* 0x000e680000000800 */
/*0710*/ LDS R5, [R2+0x10] ; /* 0x0000100002057984 */
/* 0x000fe20000000800 */
/*0720*/ IMAD.IADD R7, R6, 0x1, R7 ; /* 0x0000000106077824 */
/* 0x002fc600078e0207 */
/*0730*/ LDS R6, [R2+0x8] ; /* 0x0000080002067984 */
/* 0x000fe80000000800 */
/*0740*/ STS [R2+0x4], R7 ; /* 0x0000040702007388 */
/* 0x000fe80000000800 */
/*0750*/ LDS R9, [R4+0x8] ; /* 0x0000080004097984 */
/* 0x001e240000000800 */
/*0760*/ IMAD.IADD R9, R6, 0x1, R9 ; /* 0x0000000106097824 */
/* 0x001fc400078e0209 */
/*0770*/ LDS R6, [R2+0xc] ; /* 0x00000c0002067984 */
/* 0x000fe80000000800 */
/*0780*/ STS [R2+0x8], R9 ; /* 0x0000080902007388 */
/* 0x000fe80000000800 */
/*0790*/ LDS R11, [R4+0xc] ; /* 0x00000c00040b7984 */
/* 0x000e240000000800 */
/*07a0*/ IMAD.IADD R11, R6, 0x1, R11 ; /* 0x00000001060b7824 */
/* 0x001fca00078e020b */
/*07b0*/ STS [R2+0xc], R11 ; /* 0x00000c0b02007388 */
/* 0x000fe80000000800 */
/*07c0*/ LDS R6, [R4+0x10] ; /* 0x0000100004067984 */
/* 0x000e240000000800 */
/*07d0*/ IADD3 R5, R5, R6, RZ ; /* 0x0000000605057210 */
/* 0x001fe40007ffe0ff */
/*07e0*/ LDS R6, [R2+0x14] ; /* 0x0000140002067984 */
/* 0x000fe80000000800 */
/*07f0*/ STS [R2+0x10], R5 ; /* 0x0000100502007388 */
/* 0x000fe80000000800 */
/*0800*/ LDS R7, [R4+0x14] ; /* 0x0000140004077984 */
/* 0x000e280000000800 */
/*0810*/ LDS R5, [R2+0x20] ; /* 0x0000200002057984 */
/* 0x000fe20000000800 */
/*0820*/ IMAD.IADD R7, R6, 0x1, R7 ; /* 0x0000000106077824 */
/* 0x001fc600078e0207 */
/*0830*/ LDS R6, [R2+0x18] ; /* 0x0000180002067984 */
/* 0x000fe80000000800 */
/*0840*/ STS [R2+0x14], R7 ; /* 0x0000140702007388 */
/* 0x000fe80000000800 */
/*0850*/ LDS R9, [R4+0x18] ; /* 0x0000180004097984 */
/* 0x000e240000000800 */
/*0860*/ IMAD.IADD R9, R6, 0x1, R9 ; /* 0x0000000106097824 */
/* 0x001fc400078e0209 */
/*0870*/ LDS R6, [R2+0x1c] ; /* 0x00001c0002067984 */
/* 0x000fe80000000800 */
/*0880*/ STS [R2+0x18], R9 ; /* 0x0000180902007388 */
/* 0x000fe80000000800 */
/*0890*/ LDS R11, [R4+0x1c] ; /* 0x00001c00040b7984 */
/* 0x000e240000000800 */
/*08a0*/ IMAD.IADD R11, R6, 0x1, R11 ; /* 0x00000001060b7824 */
/* 0x001fca00078e020b */
/*08b0*/ STS [R2+0x1c], R11 ; /* 0x00001c0b02007388 */
/* 0x000fe80000000800 */
/*08c0*/ LDS R6, [R4+0x20] ; /* 0x0000200004067984 */
/* 0x000e240000000800 */
/*08d0*/ IADD3 R5, R5, R6, RZ ; /* 0x0000000605057210 */
/* 0x001fe40007ffe0ff */
/*08e0*/ LDS R6, [R2+0x24] ; /* 0x0000240002067984 */
/* 0x000fe80000000800 */
/*08f0*/ STS [R2+0x20], R5 ; /* 0x0000200502007388 */
/* 0x000fe80000000800 */
/*0900*/ LDS R7, [R4+0x24] ; /* 0x0000240004077984 */
/* 0x000e280000000800 */
/*0910*/ LDS R5, [R2+0x30] ; /* 0x0000300002057984 */
/* 0x000fe20000000800 */
/*0920*/ IMAD.IADD R7, R6, 0x1, R7 ; /* 0x0000000106077824 */
/* 0x001fc600078e0207 */
/*0930*/ LDS R6, [R2+0x28] ; /* 0x0000280002067984 */
/* 0x000fe80000000800 */
/*0940*/ STS [R2+0x24], R7 ; /* 0x0000240702007388 */
/* 0x000fe80000000800 */
/*0950*/ LDS R9, [R4+0x28] ; /* 0x0000280004097984 */
/* 0x000e240000000800 */
/*0960*/ IMAD.IADD R9, R6, 0x1, R9 ; /* 0x0000000106097824 */
/* 0x001fc400078e0209 */
/*0970*/ LDS R6, [R2+0x2c] ; /* 0x00002c0002067984 */
/* 0x000fe80000000800 */
/*0980*/ STS [R2+0x28], R9 ; /* 0x0000280902007388 */
/* 0x000fe80000000800 */
/*0990*/ LDS R11, [R4+0x2c] ; /* 0x00002c00040b7984 */
/* 0x000e240000000800 */
/*09a0*/ IMAD.IADD R11, R6, 0x1, R11 ; /* 0x00000001060b7824 */
/* 0x001fca00078e020b */
/*09b0*/ STS [R2+0x2c], R11 ; /* 0x00002c0b02007388 */
/* 0x000fe80000000800 */
/*09c0*/ LDS R6, [R4+0x30] ; /* 0x0000300004067984 */
/* 0x000e240000000800 */
/*09d0*/ IADD3 R5, R5, R6, RZ ; /* 0x0000000605057210 */
/* 0x001fe40007ffe0ff */
/*09e0*/ LDS R6, [R2+0x34] ; /* 0x0000340002067984 */
/* 0x000fe80000000800 */
/*09f0*/ STS [R2+0x30], R5 ; /* 0x0000300502007388 */
/* 0x000fe80000000800 */
/*0a00*/ LDS R7, [R4+0x34] ; /* 0x0000340004077984 */
/* 0x000e280000000800 */
/*0a10*/ LDS R5, [R2+0x40] ; /* 0x0000400002057984 */
/* 0x000fe20000000800 */
/*0a20*/ IMAD.IADD R7, R6, 0x1, R7 ; /* 0x0000000106077824 */
/* 0x001fc600078e0207 */
/*0a30*/ LDS R6, [R2+0x38] ; /* 0x0000380002067984 */
/* 0x000fe80000000800 */
/*0a40*/ STS [R2+0x34], R7 ; /* 0x0000340702007388 */
/* 0x000fe80000000800 */
/*0a50*/ LDS R9, [R4+0x38] ; /* 0x0000380004097984 */
/* 0x000e240000000800 */
/*0a60*/ IMAD.IADD R9, R6, 0x1, R9 ; /* 0x0000000106097824 */
/* 0x001fc400078e0209 */
/*0a70*/ LDS R6, [R2+0x3c] ; /* 0x00003c0002067984 */
/* 0x000fe80000000800 */
/*0a80*/ STS [R2+0x38], R9 ; /* 0x0000380902007388 */
/* 0x000fe80000000800 */
/*0a90*/ LDS R11, [R4+0x3c] ; /* 0x00003c00040b7984 */
/* 0x000e240000000800 */
/*0aa0*/ IMAD.IADD R11, R6, 0x1, R11 ; /* 0x00000001060b7824 */
/* 0x001fca00078e020b */
/*0ab0*/ STS [R2+0x3c], R11 ; /* 0x00003c0b02007388 */
/* 0x000fe80000000800 */
/*0ac0*/ LDS R6, [R4+0x40] ; /* 0x0000400004067984 */
/* 0x000e240000000800 */
/*0ad0*/ IADD3 R5, R5, R6, RZ ; /* 0x0000000605057210 */
/* 0x001fe40007ffe0ff */
/*0ae0*/ LDS R6, [R2+0x44] ; /* 0x0000440002067984 */
/* 0x000fe80000000800 */
/*0af0*/ STS [R2+0x40], R5 ; /* 0x0000400502007388 */
/* 0x000fe80000000800 */
/*0b00*/ LDS R7, [R4+0x44] ; /* 0x0000440004077984 */
/* 0x000e280000000800 */
/*0b10*/ LDS R5, [R2+0x50] ; /* 0x0000500002057984 */
/* 0x000fe20000000800 */
/*0b20*/ IMAD.IADD R7, R6, 0x1, R7 ; /* 0x0000000106077824 */
/* 0x001fc600078e0207 */
/*0b30*/ LDS R6, [R2+0x48] ; /* 0x0000480002067984 */
/* 0x000fe80000000800 */
/*0b40*/ STS [R2+0x44], R7 ; /* 0x0000440702007388 */
/* 0x000fe80000000800 */
/*0b50*/ LDS R9, [R4+0x48] ; /* 0x0000480004097984 */
/* 0x000e240000000800 */
/*0b60*/ IMAD.IADD R9, R6, 0x1, R9 ; /* 0x0000000106097824 */
/* 0x001fc400078e0209 */
/*0b70*/ LDS R6, [R2+0x4c] ; /* 0x00004c0002067984 */
/* 0x000fe80000000800 */
/*0b80*/ STS [R2+0x48], R9 ; /* 0x0000480902007388 */
/* 0x000fe80000000800 */
/*0b90*/ LDS R11, [R4+0x4c] ; /* 0x00004c00040b7984 */
/* 0x000e240000000800 */
/*0ba0*/ IMAD.IADD R11, R6, 0x1, R11 ; /* 0x00000001060b7824 */
/* 0x001fca00078e020b */
/*0bb0*/ STS [R2+0x4c], R11 ; /* 0x00004c0b02007388 */
/* 0x000fe80000000800 */
/*0bc0*/ LDS R6, [R4+0x50] ; /* 0x0000500004067984 */
/* 0x000e240000000800 */
/*0bd0*/ IADD3 R5, R5, R6, RZ ; /* 0x0000000605057210 */
/* 0x001fe40007ffe0ff */
/*0be0*/ LDS R6, [R2+0x54] ; /* 0x0000540002067984 */
/* 0x000fe80000000800 */
/*0bf0*/ STS [R2+0x50], R5 ; /* 0x0000500502007388 */
/* 0x000fe80000000800 */
/*0c00*/ LDS R7, [R4+0x54] ; /* 0x0000540004077984 */
/* 0x000e280000000800 */
/*0c10*/ LDS R5, [R2+0x60] ; /* 0x0000600002057984 */
/* 0x000fe20000000800 */
/*0c20*/ IMAD.IADD R7, R6, 0x1, R7 ; /* 0x0000000106077824 */
/* 0x001fc600078e0207 */
/*0c30*/ LDS R6, [R2+0x58] ; /* 0x0000580002067984 */
/* 0x000fe80000000800 */
/*0c40*/ STS [R2+0x54], R7 ; /* 0x0000540702007388 */
/* 0x000fe80000000800 */
/*0c50*/ LDS R9, [R4+0x58] ; /* 0x0000580004097984 */
/* 0x000e240000000800 */
/*0c60*/ IMAD.IADD R9, R6, 0x1, R9 ; /* 0x0000000106097824 */
/* 0x001fc400078e0209 */
/*0c70*/ LDS R6, [R2+0x5c] ; /* 0x00005c0002067984 */
/* 0x000fe80000000800 */
/*0c80*/ STS [R2+0x58], R9 ; /* 0x0000580902007388 */
/* 0x000fe80000000800 */
/*0c90*/ LDS R11, [R4+0x5c] ; /* 0x00005c00040b7984 */
/* 0x000e240000000800 */
/*0ca0*/ IMAD.IADD R11, R6, 0x1, R11 ; /* 0x00000001060b7824 */
/* 0x001fca00078e020b */
/*0cb0*/ STS [R2+0x5c], R11 ; /* 0x00005c0b02007388 */
/* 0x000fe80000000800 */
/*0cc0*/ LDS R6, [R4+0x60] ; /* 0x0000600004067984 */
/* 0x000e240000000800 */
/*0cd0*/ IADD3 R5, R5, R6, RZ ; /* 0x0000000605057210 */
/* 0x001fe40007ffe0ff */
/*0ce0*/ LDS R6, [R2+0x64] ; /* 0x0000640002067984 */
/* 0x000fe80000000800 */
/*0cf0*/ STS [R2+0x60], R5 ; /* 0x0000600502007388 */
/* 0x000fe80000000800 */
/*0d00*/ LDS R7, [R4+0x64] ; /* 0x0000640004077984 */
/* 0x000e240000000800 */
/*0d10*/ IMAD.IADD R7, R6, 0x1, R7 ; /* 0x0000000106077824 */
/* 0x001fca00078e0207 */
/*0d20*/ STS [R2+0x64], R7 ; /* 0x0000640702007388 */
/* 0x0001e40000000800 */
/*0d30*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0d40*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0d50*/ ISETP.GT.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fe40003f04270 */
/*0d60*/ SHF.R.S32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fd60000011403 */
/*0d70*/ @P0 BRA 0x660 ; /* 0xfffff8e000000947 */
/* 0x000fea000383ffff */
/*0d80*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0d90*/ ISETP.GT.U32.AND P0, PT, R0, 0x19, PT ; /* 0x000000190000780c */
/* 0x000fda0003f04070 */
/*0da0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0db0*/ LDS R5, [R0.X4] ; /* 0x0000000000057984 */
/* 0x000e620000004800 */
/*0dc0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0dd0*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x001fca00078e0003 */
/*0de0*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x002fe2000c10e184 */
/*0df0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e00*/ BRA 0xe00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13freqencyStep1PciPi
.globl _Z13freqencyStep1PciPi
.p2align 8
.type _Z13freqencyStep1PciPi,@function
_Z13freqencyStep1PciPi:
s_load_b32 s2, s[0:1], 0x24
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v2, 2, v0
v_mov_b32_e32 v3, v0
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s4, s2, 2
.LBB0_1:
v_add_nc_u32_e32 v3, s2, v3
ds_store_b32 v2, v1
v_add_nc_u32_e32 v2, s4, v2
v_cmp_lt_u32_e32 vcc_lo, 0xd7f, v3
s_or_b32 s3, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_1
s_or_b32 exec_lo, exec_lo, s3
s_clause 0x1
s_load_b32 s5, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x8
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s6, s5, 0xffff
s_mov_b32 s5, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
v_mul_u32_u24_e32 v2, 27, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v4, 2, v2
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_5
s_load_b32 s2, s[2:3], 0x0
s_load_b64 s[8:9], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v1
v_add_nc_u32_e32 v5, 0xfffffe7c, v4
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s2, s6
v_add_co_u32 v2, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_ashr_i32 s6, s3, 31
.p2align 6
.LBB0_4:
global_load_i8 v6, v[2:3], off
v_add_nc_u32_e32 v1, s3, v1
v_add_co_u32 v2, vcc_lo, v2, s3
v_add_co_ci_u32_e32 v3, vcc_lo, s6, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s2, s4, v1
s_or_b32 s7, s2, s7
s_waitcnt vmcnt(0)
v_lshl_add_u32 v6, v6, 2, v5
ds_load_b32 v7, v6
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v7, 1, v7
ds_store_b32 v6, v7
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_4
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s5
s_mov_b32 s2, 64
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_7
.p2align 6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s3
s_lshr_b32 s3, s2, 1
s_cmp_lt_u32 s2, 2
s_mov_b32 s2, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_10
.LBB0_7:
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB0_6
v_add_nc_u32_e32 v1, s2, v0
s_mov_b32 s4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_u32_u24_e32 v1, 27, v1
v_lshlrev_b32_e32 v1, 2, v1
.LBB0_9:
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v2, s4, v1
v_add_nc_u32_e32 v3, s4, v4
s_add_i32 s4, s4, 4
ds_load_b32 v2, v2
ds_load_b32 v5, v3
s_cmpk_lg_i32 s4, 0x68
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v5, v2
ds_store_b32 v3, v2
s_cbranch_scc1 .LBB0_9
s_branch .LBB0_6
.LBB0_10:
s_set_inst_prefetch_distance 0x2
s_barrier
buffer_gl0_inv
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 26, v0
s_cbranch_execz .LBB0_12
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13freqencyStep1PciPi
.amdhsa_group_segment_fixed_size 13824
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13freqencyStep1PciPi, .Lfunc_end0-_Z13freqencyStep1PciPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 13824
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13freqencyStep1PciPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13freqencyStep1PciPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00057c71_00000000-6_freqencyStep1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z13freqencyStep1PciPiPciPi
.type _Z36__device_stub__Z13freqencyStep1PciPiPciPi, @function
_Z36__device_stub__Z13freqencyStep1PciPiPciPi:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13freqencyStep1PciPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z13freqencyStep1PciPiPciPi, .-_Z36__device_stub__Z13freqencyStep1PciPiPciPi
.globl _Z13freqencyStep1PciPi
.type _Z13freqencyStep1PciPi, @function
_Z13freqencyStep1PciPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13freqencyStep1PciPiPciPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13freqencyStep1PciPi, .-_Z13freqencyStep1PciPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13freqencyStep1PciPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13freqencyStep1PciPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "freqencyStep1.hip"
.globl _Z28__device_stub__freqencyStep1PciPi # -- Begin function _Z28__device_stub__freqencyStep1PciPi
.p2align 4, 0x90
.type _Z28__device_stub__freqencyStep1PciPi,@function
_Z28__device_stub__freqencyStep1PciPi: # @_Z28__device_stub__freqencyStep1PciPi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13freqencyStep1PciPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__freqencyStep1PciPi, .Lfunc_end0-_Z28__device_stub__freqencyStep1PciPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13freqencyStep1PciPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13freqencyStep1PciPi,@object # @_Z13freqencyStep1PciPi
.section .rodata,"a",@progbits
.globl _Z13freqencyStep1PciPi
.p2align 3, 0x0
_Z13freqencyStep1PciPi:
.quad _Z28__device_stub__freqencyStep1PciPi
.size _Z13freqencyStep1PciPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13freqencyStep1PciPi"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__freqencyStep1PciPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13freqencyStep1PciPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ unsigned int getGid3d3d(){
int blockId = blockIdx.x + blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z)
+ (threadIdx.y * blockDim.x)
+ (threadIdx.z * (blockDim.x * blockDim.y)) + threadIdx.x;
return threadId;
}
__global__ void aux_fields(double *V, double *K, double gdt, double dt, double* Ax, double *Ay, double* Az, double *px, double *py, double *pz, double* pAx, double* pAy, double* pAz, double2* GV, double2* EV, double2* GK, double2* EK, double2* GpAx, double2* GpAy, double2* GpAz, double2* EpAx, double2* EpAy, double2* EpAz){
int gid = getGid3d3d();
int xid = blockDim.x*blockIdx.x + threadIdx.x;
int yid = blockDim.y*blockIdx.y + threadIdx.y;
int zid = blockDim.z*blockIdx.z + threadIdx.z;
GV[gid].x = exp(-V[gid]*(gdt/(2*HBAR)));
GK[gid].x = exp(-K[gid]*(gdt/HBAR));
GV[gid].y = 0.0;
GK[gid].y = 0.0;
// Ax and Ay will be calculated here but are used only for
// debugging. They may be needed later for magnetic field calc
pAx[gid] = Ax[gid] * px[xid];
pAy[gid] = Ay[gid] * py[yid];
pAz[gid] = Az[gid] * pz[zid];
GpAx[gid].x = exp(-pAx[gid]*gdt);
GpAx[gid].y = 0;
GpAy[gid].x = exp(-pAy[gid]*gdt);
GpAy[gid].y = 0;
GpAz[gid].x = exp(-pAz[gid]*gdt);
GpAz[gid].y = 0;
EV[gid].x=cos(-V[gid]*(dt/(2*HBAR)));
EV[gid].y=sin(-V[gid]*(dt/(2*HBAR)));
EK[gid].x=cos(-K[gid]*(dt/HBAR));
EK[gid].y=sin(-K[gid]*(dt/HBAR));
EpAz[gid].x=cos(-pAz[gid]*dt);
EpAz[gid].y=sin(-pAz[gid]*dt);
EpAy[gid].x=cos(-pAy[gid]*dt);
EpAy[gid].y=sin(-pAy[gid]*dt);
EpAx[gid].x=cos(-pAx[gid]*dt);
EpAx[gid].y=sin(-pAx[gid]*dt);
} | .file "tmpxft_000e61ae_00000000-6_aux_fields.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10getGid3d3dv
.type _Z10getGid3d3dv, @function
_Z10getGid3d3dv:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z10getGid3d3dv, .-_Z10getGid3d3dv
.globl _Z88__device_stub__Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_PdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_
.type _Z88__device_stub__Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_PdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_, @function
_Z88__device_stub__Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_PdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_:
.LFB2052:
.cfi_startproc
endbr64
subq $456, %rsp
.cfi_def_cfa_offset 464
movq %rdi, 184(%rsp)
movq %rsi, 176(%rsp)
movsd %xmm0, 168(%rsp)
movsd %xmm1, 160(%rsp)
movq %rdx, 152(%rsp)
movq %rcx, 144(%rsp)
movq %r8, 136(%rsp)
movq %r9, 128(%rsp)
movq 464(%rsp), %rax
movq %rax, 120(%rsp)
movq 472(%rsp), %rax
movq %rax, 112(%rsp)
movq 480(%rsp), %rax
movq %rax, 104(%rsp)
movq 488(%rsp), %rax
movq %rax, 96(%rsp)
movq 496(%rsp), %rax
movq %rax, 88(%rsp)
movq 504(%rsp), %rax
movq %rax, 80(%rsp)
movq 512(%rsp), %rax
movq %rax, 72(%rsp)
movq 520(%rsp), %rax
movq %rax, 64(%rsp)
movq 528(%rsp), %rax
movq %rax, 56(%rsp)
movq 536(%rsp), %rax
movq %rax, 48(%rsp)
movq 544(%rsp), %rax
movq %rax, 40(%rsp)
movq 552(%rsp), %rax
movq %rax, 32(%rsp)
movq 560(%rsp), %rax
movq %rax, 24(%rsp)
movq 568(%rsp), %rax
movq %rax, 16(%rsp)
movq 576(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 440(%rsp)
xorl %eax, %eax
leaq 184(%rsp), %rax
movq %rax, 256(%rsp)
leaq 176(%rsp), %rax
movq %rax, 264(%rsp)
leaq 168(%rsp), %rax
movq %rax, 272(%rsp)
leaq 160(%rsp), %rax
movq %rax, 280(%rsp)
leaq 152(%rsp), %rax
movq %rax, 288(%rsp)
leaq 144(%rsp), %rax
movq %rax, 296(%rsp)
leaq 136(%rsp), %rax
movq %rax, 304(%rsp)
leaq 128(%rsp), %rax
movq %rax, 312(%rsp)
leaq 120(%rsp), %rax
movq %rax, 320(%rsp)
leaq 112(%rsp), %rax
movq %rax, 328(%rsp)
leaq 104(%rsp), %rax
movq %rax, 336(%rsp)
leaq 96(%rsp), %rax
movq %rax, 344(%rsp)
leaq 88(%rsp), %rax
movq %rax, 352(%rsp)
leaq 80(%rsp), %rax
movq %rax, 360(%rsp)
leaq 72(%rsp), %rax
movq %rax, 368(%rsp)
leaq 64(%rsp), %rax
movq %rax, 376(%rsp)
leaq 56(%rsp), %rax
movq %rax, 384(%rsp)
leaq 48(%rsp), %rax
movq %rax, 392(%rsp)
leaq 40(%rsp), %rax
movq %rax, 400(%rsp)
leaq 32(%rsp), %rax
movq %rax, 408(%rsp)
leaq 24(%rsp), %rax
movq %rax, 416(%rsp)
leaq 16(%rsp), %rax
movq %rax, 424(%rsp)
leaq 8(%rsp), %rax
movq %rax, 432(%rsp)
movl $1, 208(%rsp)
movl $1, 212(%rsp)
movl $1, 216(%rsp)
movl $1, 220(%rsp)
movl $1, 224(%rsp)
movl $1, 228(%rsp)
leaq 200(%rsp), %rcx
leaq 192(%rsp), %rdx
leaq 220(%rsp), %rsi
leaq 208(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 440(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $456, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 200(%rsp)
.cfi_def_cfa_offset 472
pushq 200(%rsp)
.cfi_def_cfa_offset 480
leaq 272(%rsp), %r9
movq 236(%rsp), %rcx
movl 244(%rsp), %r8d
movq 224(%rsp), %rsi
movl 232(%rsp), %edx
leaq _Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 464
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z88__device_stub__Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_PdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_, .-_Z88__device_stub__Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_PdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_
.globl _Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_
.type _Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_, @function
_Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_:
.LFB2053:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 136(%rsp)
.cfi_def_cfa_offset 32
pushq 136(%rsp)
.cfi_def_cfa_offset 40
pushq 136(%rsp)
.cfi_def_cfa_offset 48
pushq 136(%rsp)
.cfi_def_cfa_offset 56
pushq 136(%rsp)
.cfi_def_cfa_offset 64
pushq 136(%rsp)
.cfi_def_cfa_offset 72
pushq 136(%rsp)
.cfi_def_cfa_offset 80
pushq 136(%rsp)
.cfi_def_cfa_offset 88
pushq 136(%rsp)
.cfi_def_cfa_offset 96
pushq 136(%rsp)
.cfi_def_cfa_offset 104
pushq 136(%rsp)
.cfi_def_cfa_offset 112
pushq 136(%rsp)
.cfi_def_cfa_offset 120
pushq 136(%rsp)
.cfi_def_cfa_offset 128
pushq 136(%rsp)
.cfi_def_cfa_offset 136
pushq 136(%rsp)
.cfi_def_cfa_offset 144
call _Z88__device_stub__Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_PdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_
addq $136, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_, .-_Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ unsigned int getGid3d3d(){
int blockId = blockIdx.x + blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z)
+ (threadIdx.y * blockDim.x)
+ (threadIdx.z * (blockDim.x * blockDim.y)) + threadIdx.x;
return threadId;
}
__global__ void aux_fields(double *V, double *K, double gdt, double dt, double* Ax, double *Ay, double* Az, double *px, double *py, double *pz, double* pAx, double* pAy, double* pAz, double2* GV, double2* EV, double2* GK, double2* EK, double2* GpAx, double2* GpAy, double2* GpAz, double2* EpAx, double2* EpAy, double2* EpAz){
int gid = getGid3d3d();
int xid = blockDim.x*blockIdx.x + threadIdx.x;
int yid = blockDim.y*blockIdx.y + threadIdx.y;
int zid = blockDim.z*blockIdx.z + threadIdx.z;
GV[gid].x = exp(-V[gid]*(gdt/(2*HBAR)));
GK[gid].x = exp(-K[gid]*(gdt/HBAR));
GV[gid].y = 0.0;
GK[gid].y = 0.0;
// Ax and Ay will be calculated here but are used only for
// debugging. They may be needed later for magnetic field calc
pAx[gid] = Ax[gid] * px[xid];
pAy[gid] = Ay[gid] * py[yid];
pAz[gid] = Az[gid] * pz[zid];
GpAx[gid].x = exp(-pAx[gid]*gdt);
GpAx[gid].y = 0;
GpAy[gid].x = exp(-pAy[gid]*gdt);
GpAy[gid].y = 0;
GpAz[gid].x = exp(-pAz[gid]*gdt);
GpAz[gid].y = 0;
EV[gid].x=cos(-V[gid]*(dt/(2*HBAR)));
EV[gid].y=sin(-V[gid]*(dt/(2*HBAR)));
EK[gid].x=cos(-K[gid]*(dt/HBAR));
EK[gid].y=sin(-K[gid]*(dt/HBAR));
EpAz[gid].x=cos(-pAz[gid]*dt);
EpAz[gid].y=sin(-pAz[gid]*dt);
EpAy[gid].x=cos(-pAy[gid]*dt);
EpAy[gid].y=sin(-pAy[gid]*dt);
EpAx[gid].x=cos(-pAx[gid]*dt);
EpAx[gid].y=sin(-pAx[gid]*dt);
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ unsigned int getGid3d3d(){
int blockId = blockIdx.x + blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z)
+ (threadIdx.y * blockDim.x)
+ (threadIdx.z * (blockDim.x * blockDim.y)) + threadIdx.x;
return threadId;
}
__global__ void aux_fields(double *V, double *K, double gdt, double dt, double* Ax, double *Ay, double* Az, double *px, double *py, double *pz, double* pAx, double* pAy, double* pAz, double2* GV, double2* EV, double2* GK, double2* EK, double2* GpAx, double2* GpAy, double2* GpAz, double2* EpAx, double2* EpAy, double2* EpAz){
int gid = getGid3d3d();
int xid = blockDim.x*blockIdx.x + threadIdx.x;
int yid = blockDim.y*blockIdx.y + threadIdx.y;
int zid = blockDim.z*blockIdx.z + threadIdx.z;
GV[gid].x = exp(-V[gid]*(gdt/(2*HBAR)));
GK[gid].x = exp(-K[gid]*(gdt/HBAR));
GV[gid].y = 0.0;
GK[gid].y = 0.0;
// Ax and Ay will be calculated here but are used only for
// debugging. They may be needed later for magnetic field calc
pAx[gid] = Ax[gid] * px[xid];
pAy[gid] = Ay[gid] * py[yid];
pAz[gid] = Az[gid] * pz[zid];
GpAx[gid].x = exp(-pAx[gid]*gdt);
GpAx[gid].y = 0;
GpAy[gid].x = exp(-pAy[gid]*gdt);
GpAy[gid].y = 0;
GpAz[gid].x = exp(-pAz[gid]*gdt);
GpAz[gid].y = 0;
EV[gid].x=cos(-V[gid]*(dt/(2*HBAR)));
EV[gid].y=sin(-V[gid]*(dt/(2*HBAR)));
EK[gid].x=cos(-K[gid]*(dt/HBAR));
EK[gid].y=sin(-K[gid]*(dt/HBAR));
EpAz[gid].x=cos(-pAz[gid]*dt);
EpAz[gid].y=sin(-pAz[gid]*dt);
EpAy[gid].x=cos(-pAy[gid]*dt);
EpAy[gid].y=sin(-pAy[gid]*dt);
EpAx[gid].x=cos(-pAx[gid]*dt);
EpAx[gid].y=sin(-pAx[gid]*dt);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ unsigned int getGid3d3d(){
int blockId = blockIdx.x + blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z)
+ (threadIdx.y * blockDim.x)
+ (threadIdx.z * (blockDim.x * blockDim.y)) + threadIdx.x;
return threadId;
}
__global__ void aux_fields(double *V, double *K, double gdt, double dt, double* Ax, double *Ay, double* Az, double *px, double *py, double *pz, double* pAx, double* pAy, double* pAz, double2* GV, double2* EV, double2* GK, double2* EK, double2* GpAx, double2* GpAy, double2* GpAz, double2* EpAx, double2* EpAy, double2* EpAz){
int gid = getGid3d3d();
int xid = blockDim.x*blockIdx.x + threadIdx.x;
int yid = blockDim.y*blockIdx.y + threadIdx.y;
int zid = blockDim.z*blockIdx.z + threadIdx.z;
GV[gid].x = exp(-V[gid]*(gdt/(2*HBAR)));
GK[gid].x = exp(-K[gid]*(gdt/HBAR));
GV[gid].y = 0.0;
GK[gid].y = 0.0;
// Ax and Ay will be calculated here but are used only for
// debugging. They may be needed later for magnetic field calc
pAx[gid] = Ax[gid] * px[xid];
pAy[gid] = Ay[gid] * py[yid];
pAz[gid] = Az[gid] * pz[zid];
GpAx[gid].x = exp(-pAx[gid]*gdt);
GpAx[gid].y = 0;
GpAy[gid].x = exp(-pAy[gid]*gdt);
GpAy[gid].y = 0;
GpAz[gid].x = exp(-pAz[gid]*gdt);
GpAz[gid].y = 0;
EV[gid].x=cos(-V[gid]*(dt/(2*HBAR)));
EV[gid].y=sin(-V[gid]*(dt/(2*HBAR)));
EK[gid].x=cos(-K[gid]*(dt/HBAR));
EK[gid].y=sin(-K[gid]*(dt/HBAR));
EpAz[gid].x=cos(-pAz[gid]*dt);
EpAz[gid].y=sin(-pAz[gid]*dt);
EpAy[gid].x=cos(-pAy[gid]*dt);
EpAy[gid].y=sin(-pAy[gid]*dt);
EpAx[gid].x=cos(-pAx[gid]*dt);
EpAx[gid].y=sin(-pAx[gid]*dt);
} | .text
.file "aux_fields.hip"
.globl _Z25__device_stub__aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P15HIP_vector_typeIdLj2EES2_S2_S2_S2_S2_S2_S2_S2_S2_ # -- Begin function _Z25__device_stub__aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P15HIP_vector_typeIdLj2EES2_S2_S2_S2_S2_S2_S2_S2_S2_
.p2align 4, 0x90
.type _Z25__device_stub__aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P15HIP_vector_typeIdLj2EES2_S2_S2_S2_S2_S2_S2_S2_S2_,@function
_Z25__device_stub__aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P15HIP_vector_typeIdLj2EES2_S2_S2_S2_S2_S2_S2_S2_S2_: # @_Z25__device_stub__aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P15HIP_vector_typeIdLj2EES2_S2_S2_S2_S2_S2_S2_S2_S2_
.cfi_startproc
# %bb.0:
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 304
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movsd %xmm0, 88(%rsp)
movsd %xmm1, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 304(%rsp), %rax
movq %rax, 176(%rsp)
leaq 312(%rsp), %rax
movq %rax, 184(%rsp)
leaq 320(%rsp), %rax
movq %rax, 192(%rsp)
leaq 328(%rsp), %rax
movq %rax, 200(%rsp)
leaq 336(%rsp), %rax
movq %rax, 208(%rsp)
leaq 344(%rsp), %rax
movq %rax, 216(%rsp)
leaq 352(%rsp), %rax
movq %rax, 224(%rsp)
leaq 360(%rsp), %rax
movq %rax, 232(%rsp)
leaq 368(%rsp), %rax
movq %rax, 240(%rsp)
leaq 376(%rsp), %rax
movq %rax, 248(%rsp)
leaq 384(%rsp), %rax
movq %rax, 256(%rsp)
leaq 392(%rsp), %rax
movq %rax, 264(%rsp)
leaq 400(%rsp), %rax
movq %rax, 272(%rsp)
leaq 408(%rsp), %rax
movq %rax, 280(%rsp)
leaq 416(%rsp), %rax
movq %rax, 288(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P15HIP_vector_typeIdLj2EES2_S2_S2_S2_S2_S2_S2_S2_S2_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $312, %rsp # imm = 0x138
.cfi_adjust_cfa_offset -312
retq
.Lfunc_end0:
.size _Z25__device_stub__aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P15HIP_vector_typeIdLj2EES2_S2_S2_S2_S2_S2_S2_S2_S2_, .Lfunc_end0-_Z25__device_stub__aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P15HIP_vector_typeIdLj2EES2_S2_S2_S2_S2_S2_S2_S2_S2_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P15HIP_vector_typeIdLj2EES2_S2_S2_S2_S2_S2_S2_S2_S2_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P15HIP_vector_typeIdLj2EES2_S2_S2_S2_S2_S2_S2_S2_S2_,@object # @_Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P15HIP_vector_typeIdLj2EES2_S2_S2_S2_S2_S2_S2_S2_S2_
.section .rodata,"a",@progbits
.globl _Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P15HIP_vector_typeIdLj2EES2_S2_S2_S2_S2_S2_S2_S2_S2_
.p2align 3, 0x0
_Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P15HIP_vector_typeIdLj2EES2_S2_S2_S2_S2_S2_S2_S2_S2_:
.quad _Z25__device_stub__aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P15HIP_vector_typeIdLj2EES2_S2_S2_S2_S2_S2_S2_S2_S2_
.size _Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P15HIP_vector_typeIdLj2EES2_S2_S2_S2_S2_S2_S2_S2_S2_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P15HIP_vector_typeIdLj2EES2_S2_S2_S2_S2_S2_S2_S2_S2_"
.size .L__unnamed_1, 91
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P15HIP_vector_typeIdLj2EES2_S2_S2_S2_S2_S2_S2_S2_S2_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P15HIP_vector_typeIdLj2EES2_S2_S2_S2_S2_S2_S2_S2_S2_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e61ae_00000000-6_aux_fields.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10getGid3d3dv
.type _Z10getGid3d3dv, @function
_Z10getGid3d3dv:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z10getGid3d3dv, .-_Z10getGid3d3dv
.globl _Z88__device_stub__Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_PdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_
.type _Z88__device_stub__Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_PdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_, @function
_Z88__device_stub__Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_PdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_:
.LFB2052:
.cfi_startproc
endbr64
subq $456, %rsp
.cfi_def_cfa_offset 464
movq %rdi, 184(%rsp)
movq %rsi, 176(%rsp)
movsd %xmm0, 168(%rsp)
movsd %xmm1, 160(%rsp)
movq %rdx, 152(%rsp)
movq %rcx, 144(%rsp)
movq %r8, 136(%rsp)
movq %r9, 128(%rsp)
movq 464(%rsp), %rax
movq %rax, 120(%rsp)
movq 472(%rsp), %rax
movq %rax, 112(%rsp)
movq 480(%rsp), %rax
movq %rax, 104(%rsp)
movq 488(%rsp), %rax
movq %rax, 96(%rsp)
movq 496(%rsp), %rax
movq %rax, 88(%rsp)
movq 504(%rsp), %rax
movq %rax, 80(%rsp)
movq 512(%rsp), %rax
movq %rax, 72(%rsp)
movq 520(%rsp), %rax
movq %rax, 64(%rsp)
movq 528(%rsp), %rax
movq %rax, 56(%rsp)
movq 536(%rsp), %rax
movq %rax, 48(%rsp)
movq 544(%rsp), %rax
movq %rax, 40(%rsp)
movq 552(%rsp), %rax
movq %rax, 32(%rsp)
movq 560(%rsp), %rax
movq %rax, 24(%rsp)
movq 568(%rsp), %rax
movq %rax, 16(%rsp)
movq 576(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 440(%rsp)
xorl %eax, %eax
leaq 184(%rsp), %rax
movq %rax, 256(%rsp)
leaq 176(%rsp), %rax
movq %rax, 264(%rsp)
leaq 168(%rsp), %rax
movq %rax, 272(%rsp)
leaq 160(%rsp), %rax
movq %rax, 280(%rsp)
leaq 152(%rsp), %rax
movq %rax, 288(%rsp)
leaq 144(%rsp), %rax
movq %rax, 296(%rsp)
leaq 136(%rsp), %rax
movq %rax, 304(%rsp)
leaq 128(%rsp), %rax
movq %rax, 312(%rsp)
leaq 120(%rsp), %rax
movq %rax, 320(%rsp)
leaq 112(%rsp), %rax
movq %rax, 328(%rsp)
leaq 104(%rsp), %rax
movq %rax, 336(%rsp)
leaq 96(%rsp), %rax
movq %rax, 344(%rsp)
leaq 88(%rsp), %rax
movq %rax, 352(%rsp)
leaq 80(%rsp), %rax
movq %rax, 360(%rsp)
leaq 72(%rsp), %rax
movq %rax, 368(%rsp)
leaq 64(%rsp), %rax
movq %rax, 376(%rsp)
leaq 56(%rsp), %rax
movq %rax, 384(%rsp)
leaq 48(%rsp), %rax
movq %rax, 392(%rsp)
leaq 40(%rsp), %rax
movq %rax, 400(%rsp)
leaq 32(%rsp), %rax
movq %rax, 408(%rsp)
leaq 24(%rsp), %rax
movq %rax, 416(%rsp)
leaq 16(%rsp), %rax
movq %rax, 424(%rsp)
leaq 8(%rsp), %rax
movq %rax, 432(%rsp)
movl $1, 208(%rsp)
movl $1, 212(%rsp)
movl $1, 216(%rsp)
movl $1, 220(%rsp)
movl $1, 224(%rsp)
movl $1, 228(%rsp)
leaq 200(%rsp), %rcx
leaq 192(%rsp), %rdx
leaq 220(%rsp), %rsi
leaq 208(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 440(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $456, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 200(%rsp)
.cfi_def_cfa_offset 472
pushq 200(%rsp)
.cfi_def_cfa_offset 480
leaq 272(%rsp), %r9
movq 236(%rsp), %rcx
movl 244(%rsp), %r8d
movq 224(%rsp), %rsi
movl 232(%rsp), %edx
leaq _Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 464
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z88__device_stub__Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_PdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_, .-_Z88__device_stub__Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_PdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_
.globl _Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_
.type _Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_, @function
_Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_:
.LFB2053:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 136(%rsp)
.cfi_def_cfa_offset 32
pushq 136(%rsp)
.cfi_def_cfa_offset 40
pushq 136(%rsp)
.cfi_def_cfa_offset 48
pushq 136(%rsp)
.cfi_def_cfa_offset 56
pushq 136(%rsp)
.cfi_def_cfa_offset 64
pushq 136(%rsp)
.cfi_def_cfa_offset 72
pushq 136(%rsp)
.cfi_def_cfa_offset 80
pushq 136(%rsp)
.cfi_def_cfa_offset 88
pushq 136(%rsp)
.cfi_def_cfa_offset 96
pushq 136(%rsp)
.cfi_def_cfa_offset 104
pushq 136(%rsp)
.cfi_def_cfa_offset 112
pushq 136(%rsp)
.cfi_def_cfa_offset 120
pushq 136(%rsp)
.cfi_def_cfa_offset 128
pushq 136(%rsp)
.cfi_def_cfa_offset 136
pushq 136(%rsp)
.cfi_def_cfa_offset 144
call _Z88__device_stub__Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_PdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_
addq $136, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_, .-_Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P7double2S1_S1_S1_S1_S1_S1_S1_S1_S1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "aux_fields.hip"
.globl _Z25__device_stub__aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P15HIP_vector_typeIdLj2EES2_S2_S2_S2_S2_S2_S2_S2_S2_ # -- Begin function _Z25__device_stub__aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P15HIP_vector_typeIdLj2EES2_S2_S2_S2_S2_S2_S2_S2_S2_
.p2align 4, 0x90
.type _Z25__device_stub__aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P15HIP_vector_typeIdLj2EES2_S2_S2_S2_S2_S2_S2_S2_S2_,@function
_Z25__device_stub__aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P15HIP_vector_typeIdLj2EES2_S2_S2_S2_S2_S2_S2_S2_S2_: # @_Z25__device_stub__aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P15HIP_vector_typeIdLj2EES2_S2_S2_S2_S2_S2_S2_S2_S2_
.cfi_startproc
# %bb.0:
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 304
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movsd %xmm0, 88(%rsp)
movsd %xmm1, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 304(%rsp), %rax
movq %rax, 176(%rsp)
leaq 312(%rsp), %rax
movq %rax, 184(%rsp)
leaq 320(%rsp), %rax
movq %rax, 192(%rsp)
leaq 328(%rsp), %rax
movq %rax, 200(%rsp)
leaq 336(%rsp), %rax
movq %rax, 208(%rsp)
leaq 344(%rsp), %rax
movq %rax, 216(%rsp)
leaq 352(%rsp), %rax
movq %rax, 224(%rsp)
leaq 360(%rsp), %rax
movq %rax, 232(%rsp)
leaq 368(%rsp), %rax
movq %rax, 240(%rsp)
leaq 376(%rsp), %rax
movq %rax, 248(%rsp)
leaq 384(%rsp), %rax
movq %rax, 256(%rsp)
leaq 392(%rsp), %rax
movq %rax, 264(%rsp)
leaq 400(%rsp), %rax
movq %rax, 272(%rsp)
leaq 408(%rsp), %rax
movq %rax, 280(%rsp)
leaq 416(%rsp), %rax
movq %rax, 288(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P15HIP_vector_typeIdLj2EES2_S2_S2_S2_S2_S2_S2_S2_S2_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $312, %rsp # imm = 0x138
.cfi_adjust_cfa_offset -312
retq
.Lfunc_end0:
.size _Z25__device_stub__aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P15HIP_vector_typeIdLj2EES2_S2_S2_S2_S2_S2_S2_S2_S2_, .Lfunc_end0-_Z25__device_stub__aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P15HIP_vector_typeIdLj2EES2_S2_S2_S2_S2_S2_S2_S2_S2_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P15HIP_vector_typeIdLj2EES2_S2_S2_S2_S2_S2_S2_S2_S2_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P15HIP_vector_typeIdLj2EES2_S2_S2_S2_S2_S2_S2_S2_S2_,@object # @_Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P15HIP_vector_typeIdLj2EES2_S2_S2_S2_S2_S2_S2_S2_S2_
.section .rodata,"a",@progbits
.globl _Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P15HIP_vector_typeIdLj2EES2_S2_S2_S2_S2_S2_S2_S2_S2_
.p2align 3, 0x0
_Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P15HIP_vector_typeIdLj2EES2_S2_S2_S2_S2_S2_S2_S2_S2_:
.quad _Z25__device_stub__aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P15HIP_vector_typeIdLj2EES2_S2_S2_S2_S2_S2_S2_S2_S2_
.size _Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P15HIP_vector_typeIdLj2EES2_S2_S2_S2_S2_S2_S2_S2_S2_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P15HIP_vector_typeIdLj2EES2_S2_S2_S2_S2_S2_S2_S2_S2_"
.size .L__unnamed_1, 91
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P15HIP_vector_typeIdLj2EES2_S2_S2_S2_S2_S2_S2_S2_S2_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10aux_fieldsPdS_ddS_S_S_S_S_S_S_S_S_P15HIP_vector_typeIdLj2EES2_S2_S2_S2_S2_S2_S2_S2_S2_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C" __global__ void directCoulombSumReference(float4* atomInfo, int numberOfAtoms, float gridSpacing, int gridSize, float* energyGrid)
{
int xIndex = blockIdx.x*blockDim.x + threadIdx.x;
int yIndex = blockIdx.y*blockDim.y + threadIdx.y;
int zIndex = blockIdx.z*blockDim.z + threadIdx.z;
if ((xIndex >= gridSize) || (yIndex >= gridSize) || (xIndex >= gridSize))
return;
int outIndex = blockDim.y*gridDim.y * blockDim.x*gridDim.x * zIndex + blockDim.x*gridDim.x * yIndex + xIndex;
float coordX = gridSpacing * xIndex;
float coordY = gridSpacing * yIndex;
float coordZ = gridSpacing * zIndex;
float energyValue = 0.0f;
for (int i = 0; i < numberOfAtoms; i++)
{
float dX = coordX - atomInfo[i].x;
float dY = coordY - atomInfo[i].y;
float dZ = coordZ - atomInfo[i].z;
float partialResult = rsqrt(dX * dX + dY * dY + dZ*dZ);
energyValue += atomInfo[i].w * partialResult;
}
energyGrid[outIndex] += energyValue;
} | code for sm_80
Function : directCoulombSumReference
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R21, SR_CTAID.X ; /* 0x0000000000157919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0030*/ S2R R24, SR_CTAID.Y ; /* 0x0000000000187919 */
/* 0x000e680000002600 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R21, R21, c[0x0][0x0], R0 ; /* 0x0000000015157a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R21, c[0x0][0x170], PT ; /* 0x00005c0015007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R24, R24, c[0x0][0x4], R3 ; /* 0x0000010018187a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R24, c[0x0][0x170], P0 ; /* 0x00005c0018007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ S2R R23, SR_TID.Z ; /* 0x0000000000177919 */
/* 0x000e220000002300 */
/*00b0*/ MOV R22, c[0x0][0x168] ; /* 0x00005a0000167a02 */
/* 0x000fe20000000f00 */
/*00c0*/ ULDC UR4, c[0x0][0x10] ; /* 0x0000040000047ab9 */
/* 0x000fe40000000800 */
/*00d0*/ S2R R0, SR_CTAID.Z ; /* 0x0000000000007919 */
/* 0x000e220000002700 */
/*00e0*/ ULDC.64 UR6, c[0x0][0x0] ; /* 0x0000000000067ab9 */
/* 0x000fe20000000a00 */
/*00f0*/ ISETP.GE.AND P0, PT, R22, 0x1, PT ; /* 0x000000011600780c */
/* 0x000fe20003f06270 */
/*0100*/ UIMAD UR4, UR7, UR4, URZ ; /* 0x00000004070472a4 */
/* 0x000fe4000f8e023f */
/*0110*/ ULDC UR5, c[0x0][0xc] ; /* 0x0000030000057ab9 */
/* 0x000fe40000000800 */
/*0120*/ UIMAD UR5, UR5, UR6, URZ ; /* 0x00000006050572a4 */
/* 0x000fc4000f8e023f */
/*0130*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0140*/ IMAD R23, R0, c[0x0][0x8], R23 ; /* 0x0000020000177a24 */
/* 0x001fe200078e0217 */
/*0150*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fc600000001ff */
/*0160*/ IMAD R20, R23, UR4, R24 ; /* 0x0000000417147c24 */
/* 0x000fc8000f8e0218 */
/*0170*/ IMAD R20, R20, UR5, R21 ; /* 0x0000000514147c24 */
/* 0x000fe2000f8e0215 */
/*0180*/ @!P0 BRA 0x750 ; /* 0x000005c000008947 */
/* 0x000fea0003800000 */
/*0190*/ IADD3 R0, R22.reuse, -0x1, RZ ; /* 0xffffffff16007810 */
/* 0x040fe20007ffe0ff */
/*01a0*/ I2F R21, R21 ; /* 0x0000001500157306 */
/* 0x000e220000201400 */
/*01b0*/ LOP3.LUT R22, R22, 0x3, RZ, 0xc0, !PT ; /* 0x0000000316167812 */
/* 0x000fe200078ec0ff */
/*01c0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*01d0*/ ISETP.GE.U32.AND P1, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f26070 */
/*01e0*/ ISETP.NE.AND P0, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fe40003f05270 */
/*01f0*/ MOV R0, RZ ; /* 0x000000ff00007202 */
/* 0x000fe20000000f00 */
/*0200*/ I2F R24, R24 ; /* 0x0000001800187306 */
/* 0x000e700000201400 */
/*0210*/ I2F R23, R23 ; /* 0x0000001700177306 */
/* 0x000ea20000201400 */
/*0220*/ @!P1 BRA 0x5e0 ; /* 0x000003b000009947 */
/* 0x000fea0003800000 */
/*0230*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x001fe200000001ff */
/*0240*/ IADD3 R25, -R22, c[0x0][0x168], RZ ; /* 0x00005a0016197a10 */
/* 0x000fe20007ffe1ff */
/*0250*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0260*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fc40000000f00 */
/*0270*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fca0000000f00 */
/*0280*/ LDG.E.128 R4, [R2.64] ; /* 0x0000000802047981 */
/* 0x000ee8000c1e1d00 */
/*0290*/ LDG.E.128 R8, [R2.64+0x10] ; /* 0x0000100802087981 */
/* 0x000f28000c1e1d00 */
/*02a0*/ LDG.E.128 R12, [R2.64+0x20] ; /* 0x00002008020c7981 */
/* 0x000f68000c1e1d00 */
/*02b0*/ LDG.E.128 R16, [R2.64+0x30] ; /* 0x0000300802107981 */
/* 0x004ea2000c1e1d00 */
/*02c0*/ IADD3 R25, R25, -0x4, RZ ; /* 0xfffffffc19197810 */
/* 0x000fe20007ffe0ff */
/*02d0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*02e0*/ FFMA R5, R24, c[0x0][0x16c], -R5 ; /* 0x00005b0018057a23 */
/* 0x00afc40000000805 */
/*02f0*/ FFMA R4, R21, c[0x0][0x16c], -R4 ; /* 0x00005b0015047a23 */
/* 0x000fe40000000804 */
/*0300*/ FMUL R5, R5, R5 ; /* 0x0000000505057220 */
/* 0x000fe40000400000 */
/*0310*/ FFMA R9, R24, c[0x0][0x16c], -R9 ; /* 0x00005b0018097a23 */
/* 0x010fe40000000809 */
/*0320*/ FFMA R4, R4, R4, R5 ; /* 0x0000000404047223 */
/* 0x000fe40000000005 */
/*0330*/ FFMA R8, R21, c[0x0][0x16c], -R8 ; /* 0x00005b0015087a23 */
/* 0x000fe40000000808 */
/*0340*/ FMUL R9, R9, R9 ; /* 0x0000000909097220 */
/* 0x000fc40000400000 */
/*0350*/ FFMA R13, R24, c[0x0][0x16c], -R13 ; /* 0x00005b00180d7a23 */
/* 0x020fe4000000080d */
/*0360*/ FFMA R5, R23.reuse, c[0x0][0x16c], -R6 ; /* 0x00005b0017057a23 */
/* 0x040fe40000000806 */
/*0370*/ FFMA R9, R8, R8, R9 ; /* 0x0000000808097223 */
/* 0x000fe40000000009 */
/*0380*/ FFMA R10, R23, c[0x0][0x16c], -R10 ; /* 0x00005b00170a7a23 */
/* 0x000fe4000000080a */
/*0390*/ FFMA R12, R21, c[0x0][0x16c], -R12 ; /* 0x00005b00150c7a23 */
/* 0x000fe4000000080c */
/*03a0*/ FMUL R13, R13, R13 ; /* 0x0000000d0d0d7220 */
/* 0x000fc40000400000 */
/*03b0*/ FFMA R4, R5, R5, R4 ; /* 0x0000000505047223 */
/* 0x000fe40000000004 */
/*03c0*/ FFMA R17, R24, c[0x0][0x16c], -R17 ; /* 0x00005b0018117a23 */
/* 0x004fe40000000811 */
/*03d0*/ FFMA R5, R10, R10, R9 ; /* 0x0000000a0a057223 */
/* 0x000fe20000000009 */
/*03e0*/ FSETP.GEU.AND P2, PT, |R4|, 1.175494350822287508e-38, PT ; /* 0x008000000400780b */
/* 0x000fe20003f4e200 */
/*03f0*/ FFMA R13, R12, R12, R13 ; /* 0x0000000c0c0d7223 */
/* 0x000fe4000000000d */
/*0400*/ FFMA R14, R23, c[0x0][0x16c], -R14 ; /* 0x00005b00170e7a23 */
/* 0x000fe2000000080e */
/*0410*/ FSETP.GEU.AND P3, PT, |R5|, 1.175494350822287508e-38, PT ; /* 0x008000000500780b */
/* 0x000fe20003f6e200 */
/*0420*/ FFMA R16, R21, c[0x0][0x16c], -R16 ; /* 0x00005b0015107a23 */
/* 0x000fc40000000810 */
/*0430*/ FMUL R17, R17, R17 ; /* 0x0000001111117220 */
/* 0x000fe40000400000 */
/*0440*/ FFMA R13, R14, R14, R13 ; /* 0x0000000e0e0d7223 */
/* 0x000fe4000000000d */
/*0450*/ FFMA R17, R16, R16, R17 ; /* 0x0000001010117223 */
/* 0x000fe40000000011 */
/*0460*/ FFMA R18, R23, c[0x0][0x16c], -R18 ; /* 0x00005b0017127a23 */
/* 0x000fe20000000812 */
/*0470*/ FSETP.GEU.AND P4, PT, |R13|, 1.175494350822287508e-38, PT ; /* 0x008000000d00780b */
/* 0x000fe20003f8e200 */
/*0480*/ @!P2 FMUL R4, R4, 16777216 ; /* 0x4b8000000404a820 */
/* 0x000fe40000400000 */
/*0490*/ FFMA R17, R18, R18, R17 ; /* 0x0000001212117223 */
/* 0x000fc40000000011 */
/*04a0*/ MUFU.RSQ R6, R4 ; /* 0x0000000400067308 */
/* 0x000e220000001400 */
/*04b0*/ @!P3 FMUL R5, R5, 16777216 ; /* 0x4b8000000505b820 */
/* 0x000fe40000400000 */
/*04c0*/ FSETP.GEU.AND P1, PT, |R17|, 1.175494350822287508e-38, PT ; /* 0x008000001100780b */
/* 0x000fca0003f2e200 */
/*04d0*/ MUFU.RSQ R8, R5 ; /* 0x0000000500087308 */
/* 0x000e620000001400 */
/*04e0*/ @!P4 FMUL R13, R13, 16777216 ; /* 0x4b8000000d0dc820 */
/* 0x000fce0000400000 */
/*04f0*/ MUFU.RSQ R9, R13 ; /* 0x0000000d00097308 */
/* 0x000ea20000001400 */
/*0500*/ @!P1 FMUL R17, R17, 16777216 ; /* 0x4b80000011119820 */
/* 0x000fe40000400000 */
/*0510*/ @!P2 FMUL R6, R6, 4096 ; /* 0x458000000606a820 */
/* 0x001fe20000400000 */
/*0520*/ ISETP.NE.AND P2, PT, R25, RZ, PT ; /* 0x000000ff1900720c */
/* 0x000fc60003f45270 */
/*0530*/ FFMA R0, R7, R6, R0 ; /* 0x0000000607007223 */
/* 0x000fe20000000000 */
/*0540*/ MUFU.RSQ R10, R17 ; /* 0x00000011000a7308 */
/* 0x000e220000001400 */
/*0550*/ @!P3 FMUL R8, R8, 4096 ; /* 0x458000000808b820 */
/* 0x002fe20000400000 */
/*0560*/ IADD3 R2, P3, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x000fc60007f7e0ff */
/*0570*/ FFMA R0, R11, R8, R0 ; /* 0x000000080b007223 */
/* 0x000fe20000000000 */
/*0580*/ IADD3.X R3, RZ, R3, RZ, P3, !PT ; /* 0x00000003ff037210 */
/* 0x000fe20001ffe4ff */
/*0590*/ @!P4 FMUL R9, R9, 4096 ; /* 0x458000000909c820 */
/* 0x004fc80000400000 */
/*05a0*/ FFMA R0, R15, R9, R0 ; /* 0x000000090f007223 */
/* 0x000fe40000000000 */
/*05b0*/ @!P1 FMUL R10, R10, 4096 ; /* 0x458000000a0a9820 */
/* 0x001fc80000400000 */
/*05c0*/ FFMA R0, R19, R10, R0 ; /* 0x0000000a13007223 */
/* 0x000fe20000000000 */
/*05d0*/ @P2 BRA 0x280 ; /* 0xfffffca000002947 */
/* 0x000fea000383ffff */
/*05e0*/ @!P0 BRA 0x750 ; /* 0x0000016000008947 */
/* 0x001fea0003800000 */
/*05f0*/ UMOV UR5, 0x10 ; /* 0x0000001000057882 */
/* 0x000fe40000000000 */
/*0600*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe40000000a00 */
/*0610*/ UIMAD.WIDE UR4, UR4, UR5, UR6 ; /* 0x00000005040472a5 */
/* 0x000fcc000f8e0206 */
/*0620*/ MOV R4, UR4 ; /* 0x0000000400047c02 */
/* 0x000fe40008000f00 */
/*0630*/ MOV R5, UR5 ; /* 0x0000000500057c02 */
/* 0x000fcc0008000f00 */
/*0640*/ LDG.E.128 R4, [R4.64] ; /* 0x0000000804047981 */
/* 0x000ee2000c1e1d00 */
/*0650*/ IADD3 R22, R22, -0x1, RZ ; /* 0xffffffff16167810 */
/* 0x000fe20007ffe0ff */
/*0660*/ UIADD3 UR4, UP0, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fc6000ff1e03f */
/*0670*/ ISETP.NE.AND P1, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fe20003f25270 */
/*0680*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*0690*/ FFMA R3, R24, c[0x0][0x16c], -R5 ; /* 0x00005b0018037a23 */
/* 0x00afe40000000805 */
/*06a0*/ FFMA R2, R21, c[0x0][0x16c], -R4 ; /* 0x00005b0015027a23 */
/* 0x000fe40000000804 */
/*06b0*/ FMUL R3, R3, R3 ; /* 0x0000000303037220 */
/* 0x000fe40000400000 */
/*06c0*/ FFMA R6, R23, c[0x0][0x16c], -R6 ; /* 0x00005b0017067a23 */
/* 0x004fe40000000806 */
/*06d0*/ FFMA R3, R2, R2, R3 ; /* 0x0000000202037223 */
/* 0x000fc80000000003 */
/*06e0*/ FFMA R3, R6, R6, R3 ; /* 0x0000000606037223 */
/* 0x000fca0000000003 */
/*06f0*/ FSETP.GEU.AND P0, PT, |R3|, 1.175494350822287508e-38, PT ; /* 0x008000000300780b */
/* 0x000fda0003f0e200 */
/*0700*/ @!P0 FMUL R3, R3, 16777216 ; /* 0x4b80000003038820 */
/* 0x000fc80000400000 */
/*0710*/ MUFU.RSQ R2, R3 ; /* 0x0000000300027308 */
/* 0x000e240000001400 */
/*0720*/ @!P0 FMUL R2, R2, 4096 ; /* 0x4580000002028820 */
/* 0x001fc80000400000 */
/*0730*/ FFMA R0, R7, R2, R0 ; /* 0x0000000207007223 */
/* 0x000fe20000000000 */
/*0740*/ @P1 BRA 0x620 ; /* 0xfffffed000001947 */
/* 0x000fea000383ffff */
/*0750*/ MOV R21, 0x4 ; /* 0x0000000400157802 */
/* 0x000fca0000000f00 */
/*0760*/ IMAD.WIDE R20, R20, R21, c[0x0][0x178] ; /* 0x00005e0014147625 */
/* 0x000fca00078e0215 */
/*0770*/ LDG.E R3, [R20.64] ; /* 0x0000000814037981 */
/* 0x000ee4000c1e1900 */
/*0780*/ FADD R3, R3, R0 ; /* 0x0000000003037221 */
/* 0x008fca0000000000 */
/*0790*/ STG.E [R20.64], R3 ; /* 0x0000000314007986 */
/* 0x000fe2000c101908 */
/*07a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07b0*/ BRA 0x7b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C" __global__ void directCoulombSumReference(float4* atomInfo, int numberOfAtoms, float gridSpacing, int gridSize, float* energyGrid)
{
int xIndex = blockIdx.x*blockDim.x + threadIdx.x;
int yIndex = blockIdx.y*blockDim.y + threadIdx.y;
int zIndex = blockIdx.z*blockDim.z + threadIdx.z;
if ((xIndex >= gridSize) || (yIndex >= gridSize) || (xIndex >= gridSize))
return;
int outIndex = blockDim.y*gridDim.y * blockDim.x*gridDim.x * zIndex + blockDim.x*gridDim.x * yIndex + xIndex;
float coordX = gridSpacing * xIndex;
float coordY = gridSpacing * yIndex;
float coordZ = gridSpacing * zIndex;
float energyValue = 0.0f;
for (int i = 0; i < numberOfAtoms; i++)
{
float dX = coordX - atomInfo[i].x;
float dY = coordY - atomInfo[i].y;
float dZ = coordZ - atomInfo[i].z;
float partialResult = rsqrt(dX * dX + dY * dY + dZ*dZ);
energyValue += atomInfo[i].w * partialResult;
}
energyGrid[outIndex] += energyValue;
} | .file "tmpxft_000b7ada_00000000-6_CoulombSum3dReference.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z56__device_stub__Z25directCoulombSumReferenceP6float4ifiPfP6float4ifiPf
.type _Z56__device_stub__Z25directCoulombSumReferenceP6float4ifiPfP6float4ifiPf, @function
_Z56__device_stub__Z25directCoulombSumReferenceP6float4ifiPfP6float4ifiPf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movss %xmm0, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq directCoulombSumReference(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z56__device_stub__Z25directCoulombSumReferenceP6float4ifiPfP6float4ifiPf, .-_Z56__device_stub__Z25directCoulombSumReferenceP6float4ifiPfP6float4ifiPf
.globl directCoulombSumReference
.type directCoulombSumReference, @function
directCoulombSumReference:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z56__device_stub__Z25directCoulombSumReferenceP6float4ifiPfP6float4ifiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size directCoulombSumReference, .-directCoulombSumReference
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "directCoulombSumReference"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq directCoulombSumReference(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C" __global__ void directCoulombSumReference(float4* atomInfo, int numberOfAtoms, float gridSpacing, int gridSize, float* energyGrid)
{
int xIndex = blockIdx.x*blockDim.x + threadIdx.x;
int yIndex = blockIdx.y*blockDim.y + threadIdx.y;
int zIndex = blockIdx.z*blockDim.z + threadIdx.z;
if ((xIndex >= gridSize) || (yIndex >= gridSize) || (xIndex >= gridSize))
return;
int outIndex = blockDim.y*gridDim.y * blockDim.x*gridDim.x * zIndex + blockDim.x*gridDim.x * yIndex + xIndex;
float coordX = gridSpacing * xIndex;
float coordY = gridSpacing * yIndex;
float coordZ = gridSpacing * zIndex;
float energyValue = 0.0f;
for (int i = 0; i < numberOfAtoms; i++)
{
float dX = coordX - atomInfo[i].x;
float dY = coordY - atomInfo[i].y;
float dZ = coordZ - atomInfo[i].z;
float partialResult = rsqrt(dX * dX + dY * dY + dZ*dZ);
energyValue += atomInfo[i].w * partialResult;
}
energyGrid[outIndex] += energyValue;
} | #include <hip/hip_runtime.h>
extern "C" __global__ void directCoulombSumReference(float4* atomInfo, int numberOfAtoms, float gridSpacing, int gridSize, float* energyGrid)
{
int xIndex = blockIdx.x*blockDim.x + threadIdx.x;
int yIndex = blockIdx.y*blockDim.y + threadIdx.y;
int zIndex = blockIdx.z*blockDim.z + threadIdx.z;
if ((xIndex >= gridSize) || (yIndex >= gridSize) || (xIndex >= gridSize))
return;
int outIndex = blockDim.y*gridDim.y * blockDim.x*gridDim.x * zIndex + blockDim.x*gridDim.x * yIndex + xIndex;
float coordX = gridSpacing * xIndex;
float coordY = gridSpacing * yIndex;
float coordZ = gridSpacing * zIndex;
float energyValue = 0.0f;
for (int i = 0; i < numberOfAtoms; i++)
{
float dX = coordX - atomInfo[i].x;
float dY = coordY - atomInfo[i].y;
float dZ = coordZ - atomInfo[i].z;
float partialResult = rsqrt(dX * dX + dY * dY + dZ*dZ);
energyValue += atomInfo[i].w * partialResult;
}
energyGrid[outIndex] += energyValue;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C" __global__ void directCoulombSumReference(float4* atomInfo, int numberOfAtoms, float gridSpacing, int gridSize, float* energyGrid)
{
int xIndex = blockIdx.x*blockDim.x + threadIdx.x;
int yIndex = blockIdx.y*blockDim.y + threadIdx.y;
int zIndex = blockIdx.z*blockDim.z + threadIdx.z;
if ((xIndex >= gridSize) || (yIndex >= gridSize) || (xIndex >= gridSize))
return;
int outIndex = blockDim.y*gridDim.y * blockDim.x*gridDim.x * zIndex + blockDim.x*gridDim.x * yIndex + xIndex;
float coordX = gridSpacing * xIndex;
float coordY = gridSpacing * yIndex;
float coordZ = gridSpacing * zIndex;
float energyValue = 0.0f;
for (int i = 0; i < numberOfAtoms; i++)
{
float dX = coordX - atomInfo[i].x;
float dY = coordY - atomInfo[i].y;
float dZ = coordZ - atomInfo[i].z;
float partialResult = rsqrt(dX * dX + dY * dY + dZ*dZ);
energyValue += atomInfo[i].w * partialResult;
}
energyGrid[outIndex] += energyValue;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected directCoulombSumReference
.globl directCoulombSumReference
.p2align 8
.type directCoulombSumReference,@function
directCoulombSumReference:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s5, s[0:1], 0x10
v_and_b32_e32 v3, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s4, 0xffff
s_lshr_b32 s7, s4, 16
v_mad_u64_u32 v[1:2], null, s13, s6, v[3:4]
v_mad_u64_u32 v[2:3], null, s14, s7, v[4:5]
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v3, v1, v2
v_cmpx_gt_i32_e64 s5, v3
s_cbranch_execz .LBB0_6
s_load_b32 s4, s[2:3], 0x10
s_load_b32 s8, s[0:1], 0x8
v_bfe_u32 v0, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_cmp_lt_i32 s8, 1
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s15, s4, v[0:1]
s_cbranch_scc1 .LBB0_4
s_clause 0x1
s_load_b32 s9, s[0:1], 0xc
s_load_b64 s[4:5], s[0:1], 0x0
v_cvt_f32_i32_e32 v0, v1
v_cvt_f32_i32_e32 v5, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v6, v3
s_waitcnt lgkmcnt(0)
v_dual_mul_f32 v4, s9, v0 :: v_dual_mul_f32 v5, s9, v5
s_delay_alu instid0(VALU_DEP_2)
v_mul_f32_e32 v6, s9, v6
v_mov_b32_e32 v0, 0
s_add_u32 s4, s4, 8
s_addc_u32 s5, s5, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_3:
s_add_u32 s10, s4, -8
s_addc_u32 s11, s5, -1
s_add_u32 s12, s4, -4
s_addc_u32 s13, s5, -1
s_clause 0x2
s_load_b32 s9, s[10:11], 0x0
s_load_b32 s12, s[12:13], 0x0
s_load_b64 s[10:11], s[4:5], 0x0
s_add_i32 s8, s8, -1
s_add_u32 s4, s4, 16
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s8, 0
s_waitcnt lgkmcnt(0)
v_dual_subrev_f32 v8, s9, v4 :: v_dual_subrev_f32 v7, s12, v5
v_subrev_f32_e32 v9, s10, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v7, v7
v_fmac_f32_e32 v7, v8, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v9, v9
v_cvt_f64_f32_e32 v[7:8], v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_rsq_f64_e32 v[9:10], v[7:8]
s_waitcnt_depctr 0xfff
v_mul_f64 v[7:8], v[9:10], -v[7:8]
v_cmp_class_f64_e64 vcc_lo, v[9:10], 0x180
v_fma_f64 v[7:8], v[7:8], v[9:10], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f64 v[11:12], v[9:10], v[7:8]
v_fma_f64 v[7:8], v[7:8], 0x3fd80000, 0.5
v_fma_f64 v[7:8], v[11:12], v[7:8], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v8, v10, v8 :: v_dual_cndmask_b32 v7, v9, v7
v_cvt_f32_f64_e32 v7, v[7:8]
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v0, s11, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v0, 0
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[2:3], s[2:3], 0x0
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s7
s_mul_i32 s2, s2, s6
v_mad_u64_u32 v[4:5], null, s3, v3, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s2, v4, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[2:3]
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v3, v[1:2], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v3
global_store_b32 v[1:2], v0, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel directCoulombSumReference
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size directCoulombSumReference, .Lfunc_end0-directCoulombSumReference
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: directCoulombSumReference
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: directCoulombSumReference.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C" __global__ void directCoulombSumReference(float4* atomInfo, int numberOfAtoms, float gridSpacing, int gridSize, float* energyGrid)
{
int xIndex = blockIdx.x*blockDim.x + threadIdx.x;
int yIndex = blockIdx.y*blockDim.y + threadIdx.y;
int zIndex = blockIdx.z*blockDim.z + threadIdx.z;
if ((xIndex >= gridSize) || (yIndex >= gridSize) || (xIndex >= gridSize))
return;
int outIndex = blockDim.y*gridDim.y * blockDim.x*gridDim.x * zIndex + blockDim.x*gridDim.x * yIndex + xIndex;
float coordX = gridSpacing * xIndex;
float coordY = gridSpacing * yIndex;
float coordZ = gridSpacing * zIndex;
float energyValue = 0.0f;
for (int i = 0; i < numberOfAtoms; i++)
{
float dX = coordX - atomInfo[i].x;
float dY = coordY - atomInfo[i].y;
float dZ = coordZ - atomInfo[i].z;
float partialResult = rsqrt(dX * dX + dY * dY + dZ*dZ);
energyValue += atomInfo[i].w * partialResult;
}
energyGrid[outIndex] += energyValue;
} | .text
.file "CoulombSum3dReference.hip"
.globl __device_stub__directCoulombSumReference # -- Begin function __device_stub__directCoulombSumReference
.p2align 4, 0x90
.type __device_stub__directCoulombSumReference,@function
__device_stub__directCoulombSumReference: # @__device_stub__directCoulombSumReference
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movss %xmm0, 8(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $directCoulombSumReference, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__directCoulombSumReference, .Lfunc_end0-__device_stub__directCoulombSumReference
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $directCoulombSumReference, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type directCoulombSumReference,@object # @directCoulombSumReference
.section .rodata,"a",@progbits
.globl directCoulombSumReference
.p2align 3, 0x0
directCoulombSumReference:
.quad __device_stub__directCoulombSumReference
.size directCoulombSumReference, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "directCoulombSumReference"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__directCoulombSumReference
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym directCoulombSumReference
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : directCoulombSumReference
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R21, SR_CTAID.X ; /* 0x0000000000157919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0030*/ S2R R24, SR_CTAID.Y ; /* 0x0000000000187919 */
/* 0x000e680000002600 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R21, R21, c[0x0][0x0], R0 ; /* 0x0000000015157a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R21, c[0x0][0x170], PT ; /* 0x00005c0015007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R24, R24, c[0x0][0x4], R3 ; /* 0x0000010018187a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R24, c[0x0][0x170], P0 ; /* 0x00005c0018007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ S2R R23, SR_TID.Z ; /* 0x0000000000177919 */
/* 0x000e220000002300 */
/*00b0*/ MOV R22, c[0x0][0x168] ; /* 0x00005a0000167a02 */
/* 0x000fe20000000f00 */
/*00c0*/ ULDC UR4, c[0x0][0x10] ; /* 0x0000040000047ab9 */
/* 0x000fe40000000800 */
/*00d0*/ S2R R0, SR_CTAID.Z ; /* 0x0000000000007919 */
/* 0x000e220000002700 */
/*00e0*/ ULDC.64 UR6, c[0x0][0x0] ; /* 0x0000000000067ab9 */
/* 0x000fe20000000a00 */
/*00f0*/ ISETP.GE.AND P0, PT, R22, 0x1, PT ; /* 0x000000011600780c */
/* 0x000fe20003f06270 */
/*0100*/ UIMAD UR4, UR7, UR4, URZ ; /* 0x00000004070472a4 */
/* 0x000fe4000f8e023f */
/*0110*/ ULDC UR5, c[0x0][0xc] ; /* 0x0000030000057ab9 */
/* 0x000fe40000000800 */
/*0120*/ UIMAD UR5, UR5, UR6, URZ ; /* 0x00000006050572a4 */
/* 0x000fc4000f8e023f */
/*0130*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0140*/ IMAD R23, R0, c[0x0][0x8], R23 ; /* 0x0000020000177a24 */
/* 0x001fe200078e0217 */
/*0150*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fc600000001ff */
/*0160*/ IMAD R20, R23, UR4, R24 ; /* 0x0000000417147c24 */
/* 0x000fc8000f8e0218 */
/*0170*/ IMAD R20, R20, UR5, R21 ; /* 0x0000000514147c24 */
/* 0x000fe2000f8e0215 */
/*0180*/ @!P0 BRA 0x750 ; /* 0x000005c000008947 */
/* 0x000fea0003800000 */
/*0190*/ IADD3 R0, R22.reuse, -0x1, RZ ; /* 0xffffffff16007810 */
/* 0x040fe20007ffe0ff */
/*01a0*/ I2F R21, R21 ; /* 0x0000001500157306 */
/* 0x000e220000201400 */
/*01b0*/ LOP3.LUT R22, R22, 0x3, RZ, 0xc0, !PT ; /* 0x0000000316167812 */
/* 0x000fe200078ec0ff */
/*01c0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*01d0*/ ISETP.GE.U32.AND P1, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f26070 */
/*01e0*/ ISETP.NE.AND P0, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fe40003f05270 */
/*01f0*/ MOV R0, RZ ; /* 0x000000ff00007202 */
/* 0x000fe20000000f00 */
/*0200*/ I2F R24, R24 ; /* 0x0000001800187306 */
/* 0x000e700000201400 */
/*0210*/ I2F R23, R23 ; /* 0x0000001700177306 */
/* 0x000ea20000201400 */
/*0220*/ @!P1 BRA 0x5e0 ; /* 0x000003b000009947 */
/* 0x000fea0003800000 */
/*0230*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x001fe200000001ff */
/*0240*/ IADD3 R25, -R22, c[0x0][0x168], RZ ; /* 0x00005a0016197a10 */
/* 0x000fe20007ffe1ff */
/*0250*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0260*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fc40000000f00 */
/*0270*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fca0000000f00 */
/*0280*/ LDG.E.128 R4, [R2.64] ; /* 0x0000000802047981 */
/* 0x000ee8000c1e1d00 */
/*0290*/ LDG.E.128 R8, [R2.64+0x10] ; /* 0x0000100802087981 */
/* 0x000f28000c1e1d00 */
/*02a0*/ LDG.E.128 R12, [R2.64+0x20] ; /* 0x00002008020c7981 */
/* 0x000f68000c1e1d00 */
/*02b0*/ LDG.E.128 R16, [R2.64+0x30] ; /* 0x0000300802107981 */
/* 0x004ea2000c1e1d00 */
/*02c0*/ IADD3 R25, R25, -0x4, RZ ; /* 0xfffffffc19197810 */
/* 0x000fe20007ffe0ff */
/*02d0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*02e0*/ FFMA R5, R24, c[0x0][0x16c], -R5 ; /* 0x00005b0018057a23 */
/* 0x00afc40000000805 */
/*02f0*/ FFMA R4, R21, c[0x0][0x16c], -R4 ; /* 0x00005b0015047a23 */
/* 0x000fe40000000804 */
/*0300*/ FMUL R5, R5, R5 ; /* 0x0000000505057220 */
/* 0x000fe40000400000 */
/*0310*/ FFMA R9, R24, c[0x0][0x16c], -R9 ; /* 0x00005b0018097a23 */
/* 0x010fe40000000809 */
/*0320*/ FFMA R4, R4, R4, R5 ; /* 0x0000000404047223 */
/* 0x000fe40000000005 */
/*0330*/ FFMA R8, R21, c[0x0][0x16c], -R8 ; /* 0x00005b0015087a23 */
/* 0x000fe40000000808 */
/*0340*/ FMUL R9, R9, R9 ; /* 0x0000000909097220 */
/* 0x000fc40000400000 */
/*0350*/ FFMA R13, R24, c[0x0][0x16c], -R13 ; /* 0x00005b00180d7a23 */
/* 0x020fe4000000080d */
/*0360*/ FFMA R5, R23.reuse, c[0x0][0x16c], -R6 ; /* 0x00005b0017057a23 */
/* 0x040fe40000000806 */
/*0370*/ FFMA R9, R8, R8, R9 ; /* 0x0000000808097223 */
/* 0x000fe40000000009 */
/*0380*/ FFMA R10, R23, c[0x0][0x16c], -R10 ; /* 0x00005b00170a7a23 */
/* 0x000fe4000000080a */
/*0390*/ FFMA R12, R21, c[0x0][0x16c], -R12 ; /* 0x00005b00150c7a23 */
/* 0x000fe4000000080c */
/*03a0*/ FMUL R13, R13, R13 ; /* 0x0000000d0d0d7220 */
/* 0x000fc40000400000 */
/*03b0*/ FFMA R4, R5, R5, R4 ; /* 0x0000000505047223 */
/* 0x000fe40000000004 */
/*03c0*/ FFMA R17, R24, c[0x0][0x16c], -R17 ; /* 0x00005b0018117a23 */
/* 0x004fe40000000811 */
/*03d0*/ FFMA R5, R10, R10, R9 ; /* 0x0000000a0a057223 */
/* 0x000fe20000000009 */
/*03e0*/ FSETP.GEU.AND P2, PT, |R4|, 1.175494350822287508e-38, PT ; /* 0x008000000400780b */
/* 0x000fe20003f4e200 */
/*03f0*/ FFMA R13, R12, R12, R13 ; /* 0x0000000c0c0d7223 */
/* 0x000fe4000000000d */
/*0400*/ FFMA R14, R23, c[0x0][0x16c], -R14 ; /* 0x00005b00170e7a23 */
/* 0x000fe2000000080e */
/*0410*/ FSETP.GEU.AND P3, PT, |R5|, 1.175494350822287508e-38, PT ; /* 0x008000000500780b */
/* 0x000fe20003f6e200 */
/*0420*/ FFMA R16, R21, c[0x0][0x16c], -R16 ; /* 0x00005b0015107a23 */
/* 0x000fc40000000810 */
/*0430*/ FMUL R17, R17, R17 ; /* 0x0000001111117220 */
/* 0x000fe40000400000 */
/*0440*/ FFMA R13, R14, R14, R13 ; /* 0x0000000e0e0d7223 */
/* 0x000fe4000000000d */
/*0450*/ FFMA R17, R16, R16, R17 ; /* 0x0000001010117223 */
/* 0x000fe40000000011 */
/*0460*/ FFMA R18, R23, c[0x0][0x16c], -R18 ; /* 0x00005b0017127a23 */
/* 0x000fe20000000812 */
/*0470*/ FSETP.GEU.AND P4, PT, |R13|, 1.175494350822287508e-38, PT ; /* 0x008000000d00780b */
/* 0x000fe20003f8e200 */
/*0480*/ @!P2 FMUL R4, R4, 16777216 ; /* 0x4b8000000404a820 */
/* 0x000fe40000400000 */
/*0490*/ FFMA R17, R18, R18, R17 ; /* 0x0000001212117223 */
/* 0x000fc40000000011 */
/*04a0*/ MUFU.RSQ R6, R4 ; /* 0x0000000400067308 */
/* 0x000e220000001400 */
/*04b0*/ @!P3 FMUL R5, R5, 16777216 ; /* 0x4b8000000505b820 */
/* 0x000fe40000400000 */
/*04c0*/ FSETP.GEU.AND P1, PT, |R17|, 1.175494350822287508e-38, PT ; /* 0x008000001100780b */
/* 0x000fca0003f2e200 */
/*04d0*/ MUFU.RSQ R8, R5 ; /* 0x0000000500087308 */
/* 0x000e620000001400 */
/*04e0*/ @!P4 FMUL R13, R13, 16777216 ; /* 0x4b8000000d0dc820 */
/* 0x000fce0000400000 */
/*04f0*/ MUFU.RSQ R9, R13 ; /* 0x0000000d00097308 */
/* 0x000ea20000001400 */
/*0500*/ @!P1 FMUL R17, R17, 16777216 ; /* 0x4b80000011119820 */
/* 0x000fe40000400000 */
/*0510*/ @!P2 FMUL R6, R6, 4096 ; /* 0x458000000606a820 */
/* 0x001fe20000400000 */
/*0520*/ ISETP.NE.AND P2, PT, R25, RZ, PT ; /* 0x000000ff1900720c */
/* 0x000fc60003f45270 */
/*0530*/ FFMA R0, R7, R6, R0 ; /* 0x0000000607007223 */
/* 0x000fe20000000000 */
/*0540*/ MUFU.RSQ R10, R17 ; /* 0x00000011000a7308 */
/* 0x000e220000001400 */
/*0550*/ @!P3 FMUL R8, R8, 4096 ; /* 0x458000000808b820 */
/* 0x002fe20000400000 */
/*0560*/ IADD3 R2, P3, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x000fc60007f7e0ff */
/*0570*/ FFMA R0, R11, R8, R0 ; /* 0x000000080b007223 */
/* 0x000fe20000000000 */
/*0580*/ IADD3.X R3, RZ, R3, RZ, P3, !PT ; /* 0x00000003ff037210 */
/* 0x000fe20001ffe4ff */
/*0590*/ @!P4 FMUL R9, R9, 4096 ; /* 0x458000000909c820 */
/* 0x004fc80000400000 */
/*05a0*/ FFMA R0, R15, R9, R0 ; /* 0x000000090f007223 */
/* 0x000fe40000000000 */
/*05b0*/ @!P1 FMUL R10, R10, 4096 ; /* 0x458000000a0a9820 */
/* 0x001fc80000400000 */
/*05c0*/ FFMA R0, R19, R10, R0 ; /* 0x0000000a13007223 */
/* 0x000fe20000000000 */
/*05d0*/ @P2 BRA 0x280 ; /* 0xfffffca000002947 */
/* 0x000fea000383ffff */
/*05e0*/ @!P0 BRA 0x750 ; /* 0x0000016000008947 */
/* 0x001fea0003800000 */
/*05f0*/ UMOV UR5, 0x10 ; /* 0x0000001000057882 */
/* 0x000fe40000000000 */
/*0600*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe40000000a00 */
/*0610*/ UIMAD.WIDE UR4, UR4, UR5, UR6 ; /* 0x00000005040472a5 */
/* 0x000fcc000f8e0206 */
/*0620*/ MOV R4, UR4 ; /* 0x0000000400047c02 */
/* 0x000fe40008000f00 */
/*0630*/ MOV R5, UR5 ; /* 0x0000000500057c02 */
/* 0x000fcc0008000f00 */
/*0640*/ LDG.E.128 R4, [R4.64] ; /* 0x0000000804047981 */
/* 0x000ee2000c1e1d00 */
/*0650*/ IADD3 R22, R22, -0x1, RZ ; /* 0xffffffff16167810 */
/* 0x000fe20007ffe0ff */
/*0660*/ UIADD3 UR4, UP0, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fc6000ff1e03f */
/*0670*/ ISETP.NE.AND P1, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fe20003f25270 */
/*0680*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*0690*/ FFMA R3, R24, c[0x0][0x16c], -R5 ; /* 0x00005b0018037a23 */
/* 0x00afe40000000805 */
/*06a0*/ FFMA R2, R21, c[0x0][0x16c], -R4 ; /* 0x00005b0015027a23 */
/* 0x000fe40000000804 */
/*06b0*/ FMUL R3, R3, R3 ; /* 0x0000000303037220 */
/* 0x000fe40000400000 */
/*06c0*/ FFMA R6, R23, c[0x0][0x16c], -R6 ; /* 0x00005b0017067a23 */
/* 0x004fe40000000806 */
/*06d0*/ FFMA R3, R2, R2, R3 ; /* 0x0000000202037223 */
/* 0x000fc80000000003 */
/*06e0*/ FFMA R3, R6, R6, R3 ; /* 0x0000000606037223 */
/* 0x000fca0000000003 */
/*06f0*/ FSETP.GEU.AND P0, PT, |R3|, 1.175494350822287508e-38, PT ; /* 0x008000000300780b */
/* 0x000fda0003f0e200 */
/*0700*/ @!P0 FMUL R3, R3, 16777216 ; /* 0x4b80000003038820 */
/* 0x000fc80000400000 */
/*0710*/ MUFU.RSQ R2, R3 ; /* 0x0000000300027308 */
/* 0x000e240000001400 */
/*0720*/ @!P0 FMUL R2, R2, 4096 ; /* 0x4580000002028820 */
/* 0x001fc80000400000 */
/*0730*/ FFMA R0, R7, R2, R0 ; /* 0x0000000207007223 */
/* 0x000fe20000000000 */
/*0740*/ @P1 BRA 0x620 ; /* 0xfffffed000001947 */
/* 0x000fea000383ffff */
/*0750*/ MOV R21, 0x4 ; /* 0x0000000400157802 */
/* 0x000fca0000000f00 */
/*0760*/ IMAD.WIDE R20, R20, R21, c[0x0][0x178] ; /* 0x00005e0014147625 */
/* 0x000fca00078e0215 */
/*0770*/ LDG.E R3, [R20.64] ; /* 0x0000000814037981 */
/* 0x000ee4000c1e1900 */
/*0780*/ FADD R3, R3, R0 ; /* 0x0000000003037221 */
/* 0x008fca0000000000 */
/*0790*/ STG.E [R20.64], R3 ; /* 0x0000000314007986 */
/* 0x000fe2000c101908 */
/*07a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07b0*/ BRA 0x7b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected directCoulombSumReference
.globl directCoulombSumReference
.p2align 8
.type directCoulombSumReference,@function
directCoulombSumReference:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s5, s[0:1], 0x10
v_and_b32_e32 v3, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s4, 0xffff
s_lshr_b32 s7, s4, 16
v_mad_u64_u32 v[1:2], null, s13, s6, v[3:4]
v_mad_u64_u32 v[2:3], null, s14, s7, v[4:5]
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v3, v1, v2
v_cmpx_gt_i32_e64 s5, v3
s_cbranch_execz .LBB0_6
s_load_b32 s4, s[2:3], 0x10
s_load_b32 s8, s[0:1], 0x8
v_bfe_u32 v0, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_cmp_lt_i32 s8, 1
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s15, s4, v[0:1]
s_cbranch_scc1 .LBB0_4
s_clause 0x1
s_load_b32 s9, s[0:1], 0xc
s_load_b64 s[4:5], s[0:1], 0x0
v_cvt_f32_i32_e32 v0, v1
v_cvt_f32_i32_e32 v5, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v6, v3
s_waitcnt lgkmcnt(0)
v_dual_mul_f32 v4, s9, v0 :: v_dual_mul_f32 v5, s9, v5
s_delay_alu instid0(VALU_DEP_2)
v_mul_f32_e32 v6, s9, v6
v_mov_b32_e32 v0, 0
s_add_u32 s4, s4, 8
s_addc_u32 s5, s5, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_3:
s_add_u32 s10, s4, -8
s_addc_u32 s11, s5, -1
s_add_u32 s12, s4, -4
s_addc_u32 s13, s5, -1
s_clause 0x2
s_load_b32 s9, s[10:11], 0x0
s_load_b32 s12, s[12:13], 0x0
s_load_b64 s[10:11], s[4:5], 0x0
s_add_i32 s8, s8, -1
s_add_u32 s4, s4, 16
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s8, 0
s_waitcnt lgkmcnt(0)
v_dual_subrev_f32 v8, s9, v4 :: v_dual_subrev_f32 v7, s12, v5
v_subrev_f32_e32 v9, s10, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v7, v7
v_fmac_f32_e32 v7, v8, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v9, v9
v_cvt_f64_f32_e32 v[7:8], v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_rsq_f64_e32 v[9:10], v[7:8]
s_waitcnt_depctr 0xfff
v_mul_f64 v[7:8], v[9:10], -v[7:8]
v_cmp_class_f64_e64 vcc_lo, v[9:10], 0x180
v_fma_f64 v[7:8], v[7:8], v[9:10], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f64 v[11:12], v[9:10], v[7:8]
v_fma_f64 v[7:8], v[7:8], 0x3fd80000, 0.5
v_fma_f64 v[7:8], v[11:12], v[7:8], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v8, v10, v8 :: v_dual_cndmask_b32 v7, v9, v7
v_cvt_f32_f64_e32 v7, v[7:8]
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v0, s11, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v0, 0
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[2:3], s[2:3], 0x0
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s7
s_mul_i32 s2, s2, s6
v_mad_u64_u32 v[4:5], null, s3, v3, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s2, v4, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[2:3]
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v3, v[1:2], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v3
global_store_b32 v[1:2], v0, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel directCoulombSumReference
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size directCoulombSumReference, .Lfunc_end0-directCoulombSumReference
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: directCoulombSumReference
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: directCoulombSumReference.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b7ada_00000000-6_CoulombSum3dReference.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z56__device_stub__Z25directCoulombSumReferenceP6float4ifiPfP6float4ifiPf
.type _Z56__device_stub__Z25directCoulombSumReferenceP6float4ifiPfP6float4ifiPf, @function
_Z56__device_stub__Z25directCoulombSumReferenceP6float4ifiPfP6float4ifiPf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movss %xmm0, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq directCoulombSumReference(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z56__device_stub__Z25directCoulombSumReferenceP6float4ifiPfP6float4ifiPf, .-_Z56__device_stub__Z25directCoulombSumReferenceP6float4ifiPfP6float4ifiPf
.globl directCoulombSumReference
.type directCoulombSumReference, @function
directCoulombSumReference:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z56__device_stub__Z25directCoulombSumReferenceP6float4ifiPfP6float4ifiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size directCoulombSumReference, .-directCoulombSumReference
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "directCoulombSumReference"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq directCoulombSumReference(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "CoulombSum3dReference.hip"
.globl __device_stub__directCoulombSumReference # -- Begin function __device_stub__directCoulombSumReference
.p2align 4, 0x90
.type __device_stub__directCoulombSumReference,@function
__device_stub__directCoulombSumReference: # @__device_stub__directCoulombSumReference
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movss %xmm0, 8(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $directCoulombSumReference, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__directCoulombSumReference, .Lfunc_end0-__device_stub__directCoulombSumReference
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $directCoulombSumReference, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type directCoulombSumReference,@object # @directCoulombSumReference
.section .rodata,"a",@progbits
.globl directCoulombSumReference
.p2align 3, 0x0
directCoulombSumReference:
.quad __device_stub__directCoulombSumReference
.size directCoulombSumReference, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "directCoulombSumReference"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__directCoulombSumReference
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym directCoulombSumReference
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <math.h>
// Kernel function to add the elements of two arrays
__global__
void haversine(int n, float *x, float *y)
{
//int index = threadIdx.x;
//int stride = blockDim.x;
// for (int i = index; i < n; i += stride)
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
float R = 6378.137;
float toRad = 3.14159/180;
for (int i = index; i < n; i += stride) {
// y[i] = atan(sqrt(x[i])) * sin(sqrt(y[i])) *4;
float lon1 = x[i];
float lon2 = x[i];
float lat1 = y[i];
float lat2 = y[i];
lon1 = lon1 * toRad;
lon2 = lon2 * toRad;
lat1 = lat1 * toRad;
lat2 = lat2 * toRad;
float dlon = lon2 - lon1;
float dlat = lat2 - lat1;
double a = pow(sin(dlat / 2), 2) + (cos(lat1) * cos(lat2) * pow(sin(dlon / 2),2));
double d = 2 * atan2(sqrt(a), sqrt(1 - a)) * R;
x[i] = float(d);
}
}
int main(void)
{
int N = pow(2,30);
std::cout << "In: " << N << std::endl;
float *x, *y;
// Allocate Unified Memory – accessible from CPU or GPU
cudaMallocManaged(&x, N*sizeof(float));
cudaMallocManaged(&y, N*sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Run kernel on 1M elements on the GPU
// int blockSize = 1024;
// int numBlocks = (N + blockSize - 1) / blockSize;
// haversine<<<numBlocks, blockSize>>>(N, x, y);
//add<<<1,1>>>(N, x, y);
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
std::cout << numBlocks << std::endl;
for (int z = 1; z < 1000; z++) { // Run 1000 calls to function to fill GPU for ~1 minute
haversine<<<numBlocks, blockSize>>>(N, x, y);
}
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
std::cout << "First: " << x[0] << std::endl;
// Free memory
cudaFree(x);
cudaFree(y);
return 0;
} | .file "tmpxft_000b7dfa_00000000-6_array.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9haversineiPfS_iPfS_
.type _Z31__device_stub__Z9haversineiPfS_iPfS_, @function
_Z31__device_stub__Z9haversineiPfS_iPfS_:
.LFB3695:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9haversineiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z31__device_stub__Z9haversineiPfS_iPfS_, .-_Z31__device_stub__Z9haversineiPfS_iPfS_
.globl _Z9haversineiPfS_
.type _Z9haversineiPfS_, @function
_Z9haversineiPfS_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9haversineiPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z9haversineiPfS_, .-_Z9haversineiPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "In: "
.LC3:
.string "First: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $1073741824, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rsp, %rdi
movl $1, %edx
movabsq $4294967296, %rbx
movq %rbx, %rsi
call cudaMallocManaged@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movq %rbx, %rsi
call cudaMallocManaged@PLT
movl $0, %eax
movss .LC1(%rip), %xmm1
movss .LC2(%rip), %xmm0
movq %rbx, %rcx
.L12:
movq (%rsp), %rdx
movss %xmm1, (%rdx,%rax)
movq 8(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L12
movl $4194304, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $999, %ebx
jmp .L14
.L13:
subl $1, %ebx
je .L19
.L14:
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $4194304, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movl $1073741824, %edi
call _Z31__device_stub__Z9haversineiPfS_iPfS_
jmp .L13
.L19:
call cudaDeviceSynchronize@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z9haversineiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z9haversineiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <math.h>
// Kernel function to add the elements of two arrays
__global__
void haversine(int n, float *x, float *y)
{
//int index = threadIdx.x;
//int stride = blockDim.x;
// for (int i = index; i < n; i += stride)
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
float R = 6378.137;
float toRad = 3.14159/180;
for (int i = index; i < n; i += stride) {
// y[i] = atan(sqrt(x[i])) * sin(sqrt(y[i])) *4;
float lon1 = x[i];
float lon2 = x[i];
float lat1 = y[i];
float lat2 = y[i];
lon1 = lon1 * toRad;
lon2 = lon2 * toRad;
lat1 = lat1 * toRad;
lat2 = lat2 * toRad;
float dlon = lon2 - lon1;
float dlat = lat2 - lat1;
double a = pow(sin(dlat / 2), 2) + (cos(lat1) * cos(lat2) * pow(sin(dlon / 2),2));
double d = 2 * atan2(sqrt(a), sqrt(1 - a)) * R;
x[i] = float(d);
}
}
int main(void)
{
int N = pow(2,30);
std::cout << "In: " << N << std::endl;
float *x, *y;
// Allocate Unified Memory – accessible from CPU or GPU
cudaMallocManaged(&x, N*sizeof(float));
cudaMallocManaged(&y, N*sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Run kernel on 1M elements on the GPU
// int blockSize = 1024;
// int numBlocks = (N + blockSize - 1) / blockSize;
// haversine<<<numBlocks, blockSize>>>(N, x, y);
//add<<<1,1>>>(N, x, y);
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
std::cout << numBlocks << std::endl;
for (int z = 1; z < 1000; z++) { // Run 1000 calls to function to fill GPU for ~1 minute
haversine<<<numBlocks, blockSize>>>(N, x, y);
}
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
std::cout << "First: " << x[0] << std::endl;
// Free memory
cudaFree(x);
cudaFree(y);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
// Kernel function to add the elements of two arrays
__global__
void haversine(int n, float *x, float *y)
{
//int index = threadIdx.x;
//int stride = blockDim.x;
// for (int i = index; i < n; i += stride)
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
float R = 6378.137;
float toRad = 3.14159/180;
for (int i = index; i < n; i += stride) {
// y[i] = atan(sqrt(x[i])) * sin(sqrt(y[i])) *4;
float lon1 = x[i];
float lon2 = x[i];
float lat1 = y[i];
float lat2 = y[i];
lon1 = lon1 * toRad;
lon2 = lon2 * toRad;
lat1 = lat1 * toRad;
lat2 = lat2 * toRad;
float dlon = lon2 - lon1;
float dlat = lat2 - lat1;
double a = pow(sin(dlat / 2), 2) + (cos(lat1) * cos(lat2) * pow(sin(dlon / 2),2));
double d = 2 * atan2(sqrt(a), sqrt(1 - a)) * R;
x[i] = float(d);
}
}
int main(void)
{
int N = pow(2,30);
std::cout << "In: " << N << std::endl;
float *x, *y;
// Allocate Unified Memory – accessible from CPU or GPU
hipMallocManaged(&x, N*sizeof(float));
hipMallocManaged(&y, N*sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Run kernel on 1M elements on the GPU
// int blockSize = 1024;
// int numBlocks = (N + blockSize - 1) / blockSize;
// haversine<<<numBlocks, blockSize>>>(N, x, y);
//add<<<1,1>>>(N, x, y);
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
std::cout << numBlocks << std::endl;
for (int z = 1; z < 1000; z++) { // Run 1000 calls to function to fill GPU for ~1 minute
haversine<<<numBlocks, blockSize>>>(N, x, y);
}
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
std::cout << "First: " << x[0] << std::endl;
// Free memory
hipFree(x);
hipFree(y);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
// Kernel function to add the elements of two arrays
__global__
void haversine(int n, float *x, float *y)
{
//int index = threadIdx.x;
//int stride = blockDim.x;
// for (int i = index; i < n; i += stride)
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
float R = 6378.137;
float toRad = 3.14159/180;
for (int i = index; i < n; i += stride) {
// y[i] = atan(sqrt(x[i])) * sin(sqrt(y[i])) *4;
float lon1 = x[i];
float lon2 = x[i];
float lat1 = y[i];
float lat2 = y[i];
lon1 = lon1 * toRad;
lon2 = lon2 * toRad;
lat1 = lat1 * toRad;
lat2 = lat2 * toRad;
float dlon = lon2 - lon1;
float dlat = lat2 - lat1;
double a = pow(sin(dlat / 2), 2) + (cos(lat1) * cos(lat2) * pow(sin(dlon / 2),2));
double d = 2 * atan2(sqrt(a), sqrt(1 - a)) * R;
x[i] = float(d);
}
}
int main(void)
{
int N = pow(2,30);
std::cout << "In: " << N << std::endl;
float *x, *y;
// Allocate Unified Memory – accessible from CPU or GPU
hipMallocManaged(&x, N*sizeof(float));
hipMallocManaged(&y, N*sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Run kernel on 1M elements on the GPU
// int blockSize = 1024;
// int numBlocks = (N + blockSize - 1) / blockSize;
// haversine<<<numBlocks, blockSize>>>(N, x, y);
//add<<<1,1>>>(N, x, y);
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
std::cout << numBlocks << std::endl;
for (int z = 1; z < 1000; z++) { // Run 1000 calls to function to fill GPU for ~1 minute
haversine<<<numBlocks, blockSize>>>(N, x, y);
}
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
std::cout << "First: " << x[0] << std::endl;
// Free memory
hipFree(x);
hipFree(y);
return 0;
} | .text
.file "array.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__haversineiPfS_ # -- Begin function _Z24__device_stub__haversineiPfS_
.p2align 4, 0x90
.type _Z24__device_stub__haversineiPfS_,@function
_Z24__device_stub__haversineiPfS_: # @_Z24__device_stub__haversineiPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9haversineiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__haversineiPfS_, .Lfunc_end0-_Z24__device_stub__haversineiPfS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $1073741824, %esi # imm = 0x40000000
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_19
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %ecx
jmp .LBB1_4
.LBB1_3:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movabsq $4294967296, %rbx # imm = 0x100000000
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 8(%rsp), %rdi
movq %rbx, %rsi
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movq %rbx, %rsi
movl $1, %edx
callq hipMallocManaged
movq 8(%rsp), %rax
xorl %ecx, %ecx
movq 16(%rsp), %rdx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rax,%rcx,4) # imm = 0x3F800000
movl $1073741824, (%rdx,%rcx,4) # imm = 0x40000000
incq %rcx
cmpq $1073741824, %rcx # imm = 0x40000000
jne .LBB1_5
# %bb.6:
movl $_ZSt4cout, %edi
movl $4194304, %esi # imm = 0x400000
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_19
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i22
cmpb $0, 56(%r14)
je .LBB1_9
# %bb.8:
movzbl 67(%r14), %ecx
jmp .LBB1_10
.LBB1_9:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit25
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $999, %r12d # imm = 0x3E7
leaq 256(%rbx), %r14
addq $4194304, %rbx # imm = 0x400000
leaq 40(%rsp), %r13
leaq 32(%rsp), %rbp
leaq 96(%rsp), %r15
jmp .LBB1_11
.p2align 4, 0x90
.LBB1_13: # in Loop: Header=BB1_11 Depth=1
decl %r12d
je .LBB1_14
.LBB1_11: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_13
# %bb.12: # in Loop: Header=BB1_11 Depth=1
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movl $1073741824, 28(%rsp) # imm = 0x40000000
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z9haversineiPfS_, %edi
movq %r15, %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_13
.LBB1_14:
callq hipDeviceSynchronize
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 8(%rsp), %rax
movss (%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_19
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i27
cmpb $0, 56(%rbx)
je .LBB1_17
# %bb.16:
movzbl 67(%rbx), %ecx
jmp .LBB1_18
.LBB1_17:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit30
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_19:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9haversineiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9haversineiPfS_,@object # @_Z9haversineiPfS_
.section .rodata,"a",@progbits
.globl _Z9haversineiPfS_
.p2align 3, 0x0
_Z9haversineiPfS_:
.quad _Z24__device_stub__haversineiPfS_
.size _Z9haversineiPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "In: "
.size .L.str, 5
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "First: "
.size .L.str.1, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9haversineiPfS_"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__haversineiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9haversineiPfS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b7dfa_00000000-6_array.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9haversineiPfS_iPfS_
.type _Z31__device_stub__Z9haversineiPfS_iPfS_, @function
_Z31__device_stub__Z9haversineiPfS_iPfS_:
.LFB3695:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9haversineiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z31__device_stub__Z9haversineiPfS_iPfS_, .-_Z31__device_stub__Z9haversineiPfS_iPfS_
.globl _Z9haversineiPfS_
.type _Z9haversineiPfS_, @function
_Z9haversineiPfS_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9haversineiPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z9haversineiPfS_, .-_Z9haversineiPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "In: "
.LC3:
.string "First: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $1073741824, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rsp, %rdi
movl $1, %edx
movabsq $4294967296, %rbx
movq %rbx, %rsi
call cudaMallocManaged@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movq %rbx, %rsi
call cudaMallocManaged@PLT
movl $0, %eax
movss .LC1(%rip), %xmm1
movss .LC2(%rip), %xmm0
movq %rbx, %rcx
.L12:
movq (%rsp), %rdx
movss %xmm1, (%rdx,%rax)
movq 8(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L12
movl $4194304, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $999, %ebx
jmp .L14
.L13:
subl $1, %ebx
je .L19
.L14:
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $4194304, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movl $1073741824, %edi
call _Z31__device_stub__Z9haversineiPfS_iPfS_
jmp .L13
.L19:
call cudaDeviceSynchronize@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z9haversineiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z9haversineiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "array.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__haversineiPfS_ # -- Begin function _Z24__device_stub__haversineiPfS_
.p2align 4, 0x90
.type _Z24__device_stub__haversineiPfS_,@function
_Z24__device_stub__haversineiPfS_: # @_Z24__device_stub__haversineiPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9haversineiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__haversineiPfS_, .Lfunc_end0-_Z24__device_stub__haversineiPfS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $1073741824, %esi # imm = 0x40000000
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_19
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %ecx
jmp .LBB1_4
.LBB1_3:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movabsq $4294967296, %rbx # imm = 0x100000000
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 8(%rsp), %rdi
movq %rbx, %rsi
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movq %rbx, %rsi
movl $1, %edx
callq hipMallocManaged
movq 8(%rsp), %rax
xorl %ecx, %ecx
movq 16(%rsp), %rdx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rax,%rcx,4) # imm = 0x3F800000
movl $1073741824, (%rdx,%rcx,4) # imm = 0x40000000
incq %rcx
cmpq $1073741824, %rcx # imm = 0x40000000
jne .LBB1_5
# %bb.6:
movl $_ZSt4cout, %edi
movl $4194304, %esi # imm = 0x400000
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_19
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i22
cmpb $0, 56(%r14)
je .LBB1_9
# %bb.8:
movzbl 67(%r14), %ecx
jmp .LBB1_10
.LBB1_9:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit25
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $999, %r12d # imm = 0x3E7
leaq 256(%rbx), %r14
addq $4194304, %rbx # imm = 0x400000
leaq 40(%rsp), %r13
leaq 32(%rsp), %rbp
leaq 96(%rsp), %r15
jmp .LBB1_11
.p2align 4, 0x90
.LBB1_13: # in Loop: Header=BB1_11 Depth=1
decl %r12d
je .LBB1_14
.LBB1_11: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_13
# %bb.12: # in Loop: Header=BB1_11 Depth=1
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movl $1073741824, 28(%rsp) # imm = 0x40000000
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z9haversineiPfS_, %edi
movq %r15, %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_13
.LBB1_14:
callq hipDeviceSynchronize
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 8(%rsp), %rax
movss (%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_19
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i27
cmpb $0, 56(%rbx)
je .LBB1_17
# %bb.16:
movzbl 67(%rbx), %ecx
jmp .LBB1_18
.LBB1_17:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit30
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_19:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9haversineiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9haversineiPfS_,@object # @_Z9haversineiPfS_
.section .rodata,"a",@progbits
.globl _Z9haversineiPfS_
.p2align 3, 0x0
_Z9haversineiPfS_:
.quad _Z24__device_stub__haversineiPfS_
.size _Z9haversineiPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "In: "
.size .L.str, 5
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "First: "
.size .L.str.1, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9haversineiPfS_"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__haversineiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9haversineiPfS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /**
* CUDA Thrust example showing addition of 2 vectors
* (compare with that of raw CUDA)
*
* Danny George 2012
*/
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/fill.h>
#include <thrust/functional.h>
#include <thrust/transform.h>
#include <iostream>
template <class T>
void print_vector_naive(T& v) {
if (v.size() > 50) {
// print first and last bits of vector
for (int i=0; i<10; i++) {
std::cout << "[" << i << "] = " << v[i] << std::endl;
}
std::cout << " ....... " << std::endl;
for (int i=v.size()-10; i<v.size(); i++) {
std::cout << "[" << i << "] = " << v[i] << std::endl;
}
} else {
// print the whole thing...
for (int i=0; i<v.size(); i++) {
std::cout << "[" << i << "] = " << v[i] << std::endl;
}
}
}
int main(int argc, char *argv[])
{
const int N = 10000;
thrust::host_vector<int> h1(N);
thrust::host_vector<int> h2(N);
// initialize host vectors (would be more efficient to do this on the device)
thrust::fill(h1.begin(), h1.end(), 111);
thrust::fill(h2.begin(), h2.end(), 222);
// init & copy host data to device vectors
thrust::device_vector<int> d1(h1);
thrust::device_vector<int> d2(h2);
thrust::device_vector<int> dr(N);
thrust::plus<int> binary_op;
// transform is essentially a 'map' operation (std::map is used for a container)
// perform 'binary_op' on each pairwise element from d1 to d2 and store in dr
thrust::transform(d1.begin(), d1.end(), d2.begin(), dr.begin(), binary_op);
// NOTE: you MUST ensure that 'd2' and 'dr' have room for
// at least d1.end() - d1.begin() elements
// copy result back to host
h1 = dr;
print_vector_naive(h1);
return 0;
} | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tElN6thrust20THRUST_200700_800_NS8cuda_cub11__transform18binary_transform_fINS7_6detail15normal_iteratorINS7_10device_ptrIiEEEESF_SF_NS9_14no_stencil_tagENS7_4plusIiEENS9_21always_true_predicateEEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R0, P1, R2.reuse, R9, RZ ; /* 0x0000000902007210 */
/* 0x042fe40007f3e0ff */
/*0060*/ IADD3 R8, P0, -R2, c[0x0][0x160], RZ ; /* 0x0000580002087a10 */
/* 0x000fc60007f1e1ff */
/*0070*/ IMAD.X R5, RZ, RZ, R3, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0603 */
/*0080*/ IADD3.X R3, ~R3, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590003037a10 */
/* 0x000fe200007fe5ff */
/*0090*/ IMAD.SHL.U32 R2, R0, 0x4, RZ ; /* 0x0000000400027824 */
/* 0x000fe200078e00ff */
/*00a0*/ ISETP.GT.U32.AND P0, PT, R8, 0x1ff, PT ; /* 0x000001ff0800780c */
/* 0x000fe40003f04070 */
/*00b0*/ SHF.L.U64.HI R0, R0, 0x2, R5 ; /* 0x0000000200007819 */
/* 0x000fe40000010205 */
/*00c0*/ ISETP.GT.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fe40003f04300 */
/*00d0*/ IADD3 R4, P1, R2.reuse, c[0x0][0x168], RZ ; /* 0x00005a0002047a10 */
/* 0x040fe40007f3e0ff */
/*00e0*/ IADD3 R6, P2, R2, c[0x0][0x170], RZ ; /* 0x00005c0002067a10 */
/* 0x000fc40007f5e0ff */
/*00f0*/ IADD3 R2, P3, R2, c[0x0][0x178], RZ ; /* 0x00005e0002027a10 */
/* 0x000fe40007f7e0ff */
/*0100*/ IADD3.X R5, R0.reuse, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000057a10 */
/* 0x040fe40000ffe4ff */
/*0110*/ IADD3.X R7, R0.reuse, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0000077a10 */
/* 0x040fe400017fe4ff */
/*0120*/ IADD3.X R3, R0, c[0x0][0x17c], RZ, P3, !PT ; /* 0x00005f0000037a10 */
/* 0x000fe20001ffe4ff */
/*0130*/ @P0 BRA 0x270 ; /* 0x0000013000000947 */
/* 0x000fea0003800000 */
/*0140*/ IADD3 R0, R9, 0x100, RZ ; /* 0x0000010009007810 */
/* 0x000fe20007ffe0ff */
/*0150*/ BSSY B0, 0x210 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0160*/ ISETP.GT.U32.AND P0, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x000fe40003f04070 */
/*0170*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff097819 */
/* 0x000fc40000011408 */
/*0180*/ ISETP.GT.U32.AND P1, PT, R8, R0, PT ; /* 0x000000000800720c */
/* 0x000fe40003f24070 */
/*0190*/ ISETP.GT.AND.EX P0, PT, R9.reuse, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x040fe40003f04300 */
/*01a0*/ ISETP.GT.AND.EX P1, PT, R9, RZ, PT, P1 ; /* 0x000000ff0900720c */
/* 0x000fd60003f24310 */
/*01b0*/ @!P0 BRA 0x200 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*01c0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea8000c1e1900 */
/*01d0*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000ea4000c1e1900 */
/*01e0*/ IMAD.IADD R9, R0, 0x1, R9 ; /* 0x0000000100097824 */
/* 0x004fca00078e0209 */
/*01f0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e4000c101904 */
/*0200*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0210*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0220*/ LDG.E R6, [R6.64+0x400] ; /* 0x0004000406067981 */
/* 0x000ea8000c1e1900 */
/*0230*/ LDG.E R5, [R4.64+0x400] ; /* 0x0004000404057981 */
/* 0x000ea4000c1e1900 */
/*0240*/ IMAD.IADD R9, R6, 0x1, R5 ; /* 0x0000000106097824 */
/* 0x005fca00078e0205 */
/*0250*/ STG.E [R2.64+0x400], R9 ; /* 0x0004000902007986 */
/* 0x000fe2000c101904 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000ea4000c1e1900 */
/*0290*/ IMAD.IADD R9, R0, 0x1, R9 ; /* 0x0000000100097824 */
/* 0x004fca00078e0209 */
/*02a0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*02b0*/ LDG.E R0, [R6.64+0x400] ; /* 0x0004000406007981 */
/* 0x000ea8000c1e1900 */
/*02c0*/ LDG.E R11, [R4.64+0x400] ; /* 0x00040004040b7981 */
/* 0x000ea4000c1e1900 */
/*02d0*/ IMAD.IADD R11, R0, 0x1, R11 ; /* 0x00000001000b7824 */
/* 0x004fca00078e020b */
/*02e0*/ STG.E [R2.64+0x400], R11 ; /* 0x0004000b02007986 */
/* 0x000fe2000c101904 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIiEEiEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x040fe40007f3e1ff */
/*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */
/* 0x002fe40007f5e0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */
/* 0x000fe40003f04070 */
/*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */
/* 0x000fe20000ffe5ff */
/*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fe400078210ff */
/*00b0*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fc40003f04100 */
/*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */
/* 0x000fd600008f1403 */
/*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */
/* 0x000fe40000011404 */
/*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */
/* 0x000fca00078e00ff */
/*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e2000c101904 */
/*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fc80003f04070 */
/*0150*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x001fca00078e00ff */
/*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fca00078e00ff */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* CUDA Thrust example showing addition of 2 vectors
* (compare with that of raw CUDA)
*
* Danny George 2012
*/
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/fill.h>
#include <thrust/functional.h>
#include <thrust/transform.h>
#include <iostream>
template <class T>
void print_vector_naive(T& v) {
if (v.size() > 50) {
// print first and last bits of vector
for (int i=0; i<10; i++) {
std::cout << "[" << i << "] = " << v[i] << std::endl;
}
std::cout << " ....... " << std::endl;
for (int i=v.size()-10; i<v.size(); i++) {
std::cout << "[" << i << "] = " << v[i] << std::endl;
}
} else {
// print the whole thing...
for (int i=0; i<v.size(); i++) {
std::cout << "[" << i << "] = " << v[i] << std::endl;
}
}
}
int main(int argc, char *argv[])
{
const int N = 10000;
thrust::host_vector<int> h1(N);
thrust::host_vector<int> h2(N);
// initialize host vectors (would be more efficient to do this on the device)
thrust::fill(h1.begin(), h1.end(), 111);
thrust::fill(h2.begin(), h2.end(), 222);
// init & copy host data to device vectors
thrust::device_vector<int> d1(h1);
thrust::device_vector<int> d2(h2);
thrust::device_vector<int> dr(N);
thrust::plus<int> binary_op;
// transform is essentially a 'map' operation (std::map is used for a container)
// perform 'binary_op' on each pairwise element from d1 to d2 and store in dr
thrust::transform(d1.begin(), d1.end(), d2.begin(), dr.begin(), binary_op);
// NOTE: you MUST ensure that 'd2' and 'dr' have room for
// at least d1.end() - d1.begin() elements
// copy result back to host
h1 = dr;
print_vector_naive(h1);
return 0;
} | /**
* CUDA Thrust example showing addition of 2 vectors
* (compare with that of raw CUDA)
*
* Danny George 2012
*/
#include <hip/hip_runtime.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/fill.h>
#include <thrust/functional.h>
#include <thrust/transform.h>
#include <iostream>
template <class T>
void print_vector_naive(T& v) {
if (v.size() > 50) {
// print first and last bits of vector
for (int i=0; i<10; i++) {
std::cout << "[" << i << "] = " << v[i] << std::endl;
}
std::cout << " ....... " << std::endl;
for (int i=v.size()-10; i<v.size(); i++) {
std::cout << "[" << i << "] = " << v[i] << std::endl;
}
} else {
// print the whole thing...
for (int i=0; i<v.size(); i++) {
std::cout << "[" << i << "] = " << v[i] << std::endl;
}
}
}
int main(int argc, char *argv[])
{
const int N = 10000;
thrust::host_vector<int> h1(N);
thrust::host_vector<int> h2(N);
// initialize host vectors (would be more efficient to do this on the device)
thrust::fill(h1.begin(), h1.end(), 111);
thrust::fill(h2.begin(), h2.end(), 222);
// init & copy host data to device vectors
thrust::device_vector<int> d1(h1);
thrust::device_vector<int> d2(h2);
thrust::device_vector<int> dr(N);
thrust::plus<int> binary_op;
// transform is essentially a 'map' operation (std::map is used for a container)
// perform 'binary_op' on each pairwise element from d1 to d2 and store in dr
thrust::transform(d1.begin(), d1.end(), d2.begin(), dr.begin(), binary_op);
// NOTE: you MUST ensure that 'd2' and 'dr' have room for
// at least d1.end() - d1.begin() elements
// copy result back to host
h1 = dr;
print_vector_naive(h1);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
* CUDA Thrust example showing addition of 2 vectors
* (compare with that of raw CUDA)
*
* Danny George 2012
*/
#include <hip/hip_runtime.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/fill.h>
#include <thrust/functional.h>
#include <thrust/transform.h>
#include <iostream>
template <class T>
void print_vector_naive(T& v) {
if (v.size() > 50) {
// print first and last bits of vector
for (int i=0; i<10; i++) {
std::cout << "[" << i << "] = " << v[i] << std::endl;
}
std::cout << " ....... " << std::endl;
for (int i=v.size()-10; i<v.size(); i++) {
std::cout << "[" << i << "] = " << v[i] << std::endl;
}
} else {
// print the whole thing...
for (int i=0; i<v.size(); i++) {
std::cout << "[" << i << "] = " << v[i] << std::endl;
}
}
}
int main(int argc, char *argv[])
{
const int N = 10000;
thrust::host_vector<int> h1(N);
thrust::host_vector<int> h2(N);
// initialize host vectors (would be more efficient to do this on the device)
thrust::fill(h1.begin(), h1.end(), 111);
thrust::fill(h2.begin(), h2.end(), 222);
// init & copy host data to device vectors
thrust::device_vector<int> d1(h1);
thrust::device_vector<int> d2(h2);
thrust::device_vector<int> dr(N);
thrust::plus<int> binary_op;
// transform is essentially a 'map' operation (std::map is used for a container)
// perform 'binary_op' on each pairwise element from d1 to d2 and store in dr
thrust::transform(d1.begin(), d1.end(), d2.begin(), dr.begin(), binary_op);
// NOTE: you MUST ensure that 'd2' and 'dr' have room for
// at least d1.end() - d1.begin() elements
// copy result back to host
h1 = dr;
print_vector_naive(h1);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_:
s_load_b128 s[4:7], s[0:1], 0x10
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_mov_b32_e32 v2, s6
flat_store_b32 v[0:1], v2
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,comdat
.Lfunc_end0:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_, .Lfunc_end0-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_4plusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_4plusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_4plusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_4plusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_4plusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_4plusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_:
s_load_b128 s[4:7], s[0:1], 0x20
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_add_co_u32 v0, s2, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s3, 0, s2
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
flat_load_b32 v2, v[2:3]
flat_load_b32 v3, v[4:5]
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
flat_store_b32 v[0:1], v2
.LBB1_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_4plusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_4plusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_4plusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,comdat
.Lfunc_end1:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_4plusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_, .Lfunc_end1-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_4plusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 32
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_4plusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_4plusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tElN6thrust20THRUST_200700_800_NS8cuda_cub11__transform18binary_transform_fINS7_6detail15normal_iteratorINS7_10device_ptrIiEEEESF_SF_NS9_14no_stencil_tagENS7_4plusIiEENS9_21always_true_predicateEEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R0, P1, R2.reuse, R9, RZ ; /* 0x0000000902007210 */
/* 0x042fe40007f3e0ff */
/*0060*/ IADD3 R8, P0, -R2, c[0x0][0x160], RZ ; /* 0x0000580002087a10 */
/* 0x000fc60007f1e1ff */
/*0070*/ IMAD.X R5, RZ, RZ, R3, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0603 */
/*0080*/ IADD3.X R3, ~R3, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590003037a10 */
/* 0x000fe200007fe5ff */
/*0090*/ IMAD.SHL.U32 R2, R0, 0x4, RZ ; /* 0x0000000400027824 */
/* 0x000fe200078e00ff */
/*00a0*/ ISETP.GT.U32.AND P0, PT, R8, 0x1ff, PT ; /* 0x000001ff0800780c */
/* 0x000fe40003f04070 */
/*00b0*/ SHF.L.U64.HI R0, R0, 0x2, R5 ; /* 0x0000000200007819 */
/* 0x000fe40000010205 */
/*00c0*/ ISETP.GT.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fe40003f04300 */
/*00d0*/ IADD3 R4, P1, R2.reuse, c[0x0][0x168], RZ ; /* 0x00005a0002047a10 */
/* 0x040fe40007f3e0ff */
/*00e0*/ IADD3 R6, P2, R2, c[0x0][0x170], RZ ; /* 0x00005c0002067a10 */
/* 0x000fc40007f5e0ff */
/*00f0*/ IADD3 R2, P3, R2, c[0x0][0x178], RZ ; /* 0x00005e0002027a10 */
/* 0x000fe40007f7e0ff */
/*0100*/ IADD3.X R5, R0.reuse, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000057a10 */
/* 0x040fe40000ffe4ff */
/*0110*/ IADD3.X R7, R0.reuse, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0000077a10 */
/* 0x040fe400017fe4ff */
/*0120*/ IADD3.X R3, R0, c[0x0][0x17c], RZ, P3, !PT ; /* 0x00005f0000037a10 */
/* 0x000fe20001ffe4ff */
/*0130*/ @P0 BRA 0x270 ; /* 0x0000013000000947 */
/* 0x000fea0003800000 */
/*0140*/ IADD3 R0, R9, 0x100, RZ ; /* 0x0000010009007810 */
/* 0x000fe20007ffe0ff */
/*0150*/ BSSY B0, 0x210 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0160*/ ISETP.GT.U32.AND P0, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x000fe40003f04070 */
/*0170*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff097819 */
/* 0x000fc40000011408 */
/*0180*/ ISETP.GT.U32.AND P1, PT, R8, R0, PT ; /* 0x000000000800720c */
/* 0x000fe40003f24070 */
/*0190*/ ISETP.GT.AND.EX P0, PT, R9.reuse, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x040fe40003f04300 */
/*01a0*/ ISETP.GT.AND.EX P1, PT, R9, RZ, PT, P1 ; /* 0x000000ff0900720c */
/* 0x000fd60003f24310 */
/*01b0*/ @!P0 BRA 0x200 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*01c0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea8000c1e1900 */
/*01d0*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000ea4000c1e1900 */
/*01e0*/ IMAD.IADD R9, R0, 0x1, R9 ; /* 0x0000000100097824 */
/* 0x004fca00078e0209 */
/*01f0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e4000c101904 */
/*0200*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0210*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0220*/ LDG.E R6, [R6.64+0x400] ; /* 0x0004000406067981 */
/* 0x000ea8000c1e1900 */
/*0230*/ LDG.E R5, [R4.64+0x400] ; /* 0x0004000404057981 */
/* 0x000ea4000c1e1900 */
/*0240*/ IMAD.IADD R9, R6, 0x1, R5 ; /* 0x0000000106097824 */
/* 0x005fca00078e0205 */
/*0250*/ STG.E [R2.64+0x400], R9 ; /* 0x0004000902007986 */
/* 0x000fe2000c101904 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000ea4000c1e1900 */
/*0290*/ IMAD.IADD R9, R0, 0x1, R9 ; /* 0x0000000100097824 */
/* 0x004fca00078e0209 */
/*02a0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*02b0*/ LDG.E R0, [R6.64+0x400] ; /* 0x0004000406007981 */
/* 0x000ea8000c1e1900 */
/*02c0*/ LDG.E R11, [R4.64+0x400] ; /* 0x00040004040b7981 */
/* 0x000ea4000c1e1900 */
/*02d0*/ IMAD.IADD R11, R0, 0x1, R11 ; /* 0x00000001000b7824 */
/* 0x004fca00078e020b */
/*02e0*/ STG.E [R2.64+0x400], R11 ; /* 0x0004000b02007986 */
/* 0x000fe2000c101904 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIiEEiEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x040fe40007f3e1ff */
/*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */
/* 0x002fe40007f5e0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */
/* 0x000fe40003f04070 */
/*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */
/* 0x000fe20000ffe5ff */
/*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fe400078210ff */
/*00b0*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fc40003f04100 */
/*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */
/* 0x000fd600008f1403 */
/*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */
/* 0x000fe40000011404 */
/*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */
/* 0x000fca00078e00ff */
/*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e2000c101904 */
/*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fc80003f04070 */
/*0150*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x001fca00078e00ff */
/*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fca00078e00ff */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_:
s_load_b128 s[4:7], s[0:1], 0x10
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_mov_b32_e32 v2, s6
flat_store_b32 v[0:1], v2
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,comdat
.Lfunc_end0:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_, .Lfunc_end0-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_4plusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_4plusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_4plusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_4plusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_4plusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_4plusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_:
s_load_b128 s[4:7], s[0:1], 0x20
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_add_co_u32 v0, s2, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s3, 0, s2
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
flat_load_b32 v2, v[2:3]
flat_load_b32 v3, v[4:5]
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
flat_store_b32 v[0:1], v2
.LBB1_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_4plusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_4plusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_4plusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,comdat
.Lfunc_end1:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_4plusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_, .Lfunc_end1-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_4plusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 32
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_4plusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_4plusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<cuda.h>
#include <cuda_runtime.h>
#define N (1024*1024)
#define M (1000000)
__global__ void cudakernel(float *buf)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
buf[i] = 1.0f * i / N;
for(int j = 0; j < M; j++)
buf[i] = buf[i] * buf[i] - 0.25f;
}
int main()
{
float data[N]; int count = 0;
float *d_data;
cudaMalloc(&d_data, N * sizeof(float));
cudakernel<<<N/256, 256>>>(d_data);
cudaMemcpy(data, d_data, N * sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(d_data);
int sel;
printf("Enter an index: ");
scanf("%d", &sel);
printf("data[%d] = %f\n", sel, data[sel]);
} | code for sm_80
Function : _Z10cudakernelPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fe200078e0203 */
/*0050*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fc600000001ff */
/*0060*/ I2F R0, R4 ; /* 0x0000000400007306 */
/* 0x000e2e0000201400 */
/*0070*/ IMAD.WIDE R2, R4, R3, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fc800078e0203 */
/*0080*/ FMUL R5, R0, 9.5367431640625e-07 ; /* 0x3580000000057820 */
/* 0x001fe20000400000 */
/*0090*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fc800000001ff */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001ea000c101904 */
/*00b0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x001fe20000000005 */
/*00c0*/ IADD3 R0, R0, 0x140, RZ ; /* 0x0000014000007810 */
/* 0x000fc60007ffe0ff */
/*00d0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fe20000000005 */
/*00e0*/ ISETP.NE.AND P0, PT, R0, 0xf4240, PT ; /* 0x000f42400000780c */
/* 0x000fc60003f05270 */
/*00f0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0100*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0110*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0120*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0130*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0140*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0150*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0160*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0170*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0180*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0190*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*01a0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*01b0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*01c0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*01d0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*01e0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*01f0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0200*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0210*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0220*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0230*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0240*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0250*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0260*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0270*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0280*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0290*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*02a0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*02b0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*02c0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*02d0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*02e0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*02f0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0300*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0310*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0320*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0330*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0340*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0350*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0360*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0370*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0380*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0390*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*03a0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*03b0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*03c0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*03d0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*03e0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*03f0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0400*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0410*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0420*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0430*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0440*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0450*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0460*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0470*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0480*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0490*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*04a0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*04b0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*04c0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*04d0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*04e0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*04f0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0500*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0510*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0520*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0530*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0540*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0550*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0560*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0570*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0580*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0590*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*05a0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*05b0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*05c0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*05d0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*05e0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*05f0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0600*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0610*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0620*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0630*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0640*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0650*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0660*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0670*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0680*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0690*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*06a0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*06b0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*06c0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*06d0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*06e0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*06f0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0700*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0710*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0720*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0730*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0740*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0750*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0760*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0770*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0780*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0790*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*07a0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*07b0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*07c0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*07d0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*07e0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*07f0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0800*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0810*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0820*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0830*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0840*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0850*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0860*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0870*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0880*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0890*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*08a0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*08b0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*08c0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*08d0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*08e0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*08f0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0900*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0910*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0920*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0930*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0940*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0950*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0960*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0970*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0980*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0990*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*09a0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*09b0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*09c0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*09d0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*09e0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*09f0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0a00*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0a10*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0a20*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0a30*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0a40*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0a50*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0a60*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0a70*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0a80*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0a90*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0aa0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0ab0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0ac0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0ad0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0ae0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0af0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0b00*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0b10*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0b20*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0b30*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0b40*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0b50*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0b60*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0b70*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0b80*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0b90*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0ba0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0bb0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0bc0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0bd0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0be0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0bf0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0c00*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0c10*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0c20*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0c30*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0c40*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0c50*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0c60*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0c70*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0c80*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0c90*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0ca0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0cb0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0cc0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0cd0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0ce0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0cf0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0d00*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0d10*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0d20*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0d30*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0d40*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0d50*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0d60*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0d70*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0d80*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0d90*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0da0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0db0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0dc0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0dd0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0de0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0df0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0e00*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0e10*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0e20*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0e30*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0e40*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0e50*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0e60*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0e70*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0e80*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0e90*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0ea0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0eb0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0ec0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0ed0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0ee0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0ef0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0f00*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0f10*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0f20*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0f30*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0f40*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0f50*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0f60*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0f70*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0f80*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0f90*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0fa0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0fb0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0fc0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0fd0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0fe0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*0ff0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*1000*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*1010*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*1020*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*1030*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*1040*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*1050*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*1060*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*1070*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*1080*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*1090*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*10a0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*10b0*/ FFMA R5, R5, R5, -0.25 ; /* 0xbe80000005057423 */
/* 0x000fc80000000005 */
/*10c0*/ FFMA R4, R5, R5, -0.25 ; /* 0xbe80000005047423 */
/* 0x000fc80000000005 */
/*10d0*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*10e0*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*10f0*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1100*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1110*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1120*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1130*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1140*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1150*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1160*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1170*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1180*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1190*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*11a0*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*11b0*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*11c0*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*11d0*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*11e0*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*11f0*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1200*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1210*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1220*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1230*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1240*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1250*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1260*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1270*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1280*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1290*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*12a0*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*12b0*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*12c0*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*12d0*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*12e0*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*12f0*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1300*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1310*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1320*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1330*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1340*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1350*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1360*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1370*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1380*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1390*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*13a0*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*13b0*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*13c0*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*13d0*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*13e0*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*13f0*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1400*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1410*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1420*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1430*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1440*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1450*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1460*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1470*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1480*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*1490*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*14a0*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*14b0*/ FFMA R4, R4, R4, -0.25 ; /* 0xbe80000004047423 */
/* 0x000fc80000000004 */
/*14c0*/ FFMA R5, R4, R4, -0.25 ; /* 0xbe80000004057423 */
/* 0x000fe20000000004 */
/*14d0*/ @!P0 CALL.REL.NOINC 0x14f0 ; /* 0x0000001000008944 */
/* 0x000fe20003c00000 */
/*14e0*/ BRA 0xb0 ; /* 0xffffebc000007947 */
/* 0x000fea000383ffff */
/*14f0*/ NOP ; /* 0x0000000000007918 */
/* 0x000fc60000000000 */
/*1500*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*1510*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1520*/ BRA 0x1520; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*15a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*15b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*15c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*15d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*15e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*15f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<cuda.h>
#include <cuda_runtime.h>
#define N (1024*1024)
#define M (1000000)
__global__ void cudakernel(float *buf)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
buf[i] = 1.0f * i / N;
for(int j = 0; j < M; j++)
buf[i] = buf[i] * buf[i] - 0.25f;
}
int main()
{
float data[N]; int count = 0;
float *d_data;
cudaMalloc(&d_data, N * sizeof(float));
cudakernel<<<N/256, 256>>>(d_data);
cudaMemcpy(data, d_data, N * sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(d_data);
int sel;
printf("Enter an index: ");
scanf("%d", &sel);
printf("data[%d] = %f\n", sel, data[sel]);
} | .file "tmpxft_001a0377_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z10cudakernelPfPf
.type _Z30__device_stub__Z10cudakernelPfPf, @function
_Z30__device_stub__Z10cudakernelPfPf:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10cudakernelPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z10cudakernelPfPf, .-_Z30__device_stub__Z10cudakernelPfPf
.globl _Z10cudakernelPf
.type _Z10cudakernelPf, @function
_Z10cudakernelPf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10cudakernelPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10cudakernelPf, .-_Z10cudakernelPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter an index: "
.LC1:
.string "%d"
.LC2:
.string "data[%d] = %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
leaq -4194304(%rsp), %r11
.cfi_def_cfa 11, 4194312
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $56, %rsp
.cfi_def_cfa_offset 4194368
movq %fs:40, %rax
movq %rax, 4194344(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $4096, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 32(%rsp), %rdi
movl $2, %ecx
movl $4194304, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 20(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 20(%rsp), %edx
movslq %edx, %rax
pxor %xmm0, %xmm0
cvtss2sd 32(%rsp,%rax,4), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 4194344(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $4194360, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq (%rsp), %rdi
call _Z30__device_stub__Z10cudakernelPfPf
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z10cudakernelPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10cudakernelPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<cuda.h>
#include <cuda_runtime.h>
#define N (1024*1024)
#define M (1000000)
__global__ void cudakernel(float *buf)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
buf[i] = 1.0f * i / N;
for(int j = 0; j < M; j++)
buf[i] = buf[i] * buf[i] - 0.25f;
}
int main()
{
float data[N]; int count = 0;
float *d_data;
cudaMalloc(&d_data, N * sizeof(float));
cudakernel<<<N/256, 256>>>(d_data);
cudaMemcpy(data, d_data, N * sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(d_data);
int sel;
printf("Enter an index: ");
scanf("%d", &sel);
printf("data[%d] = %f\n", sel, data[sel]);
} | #include<stdio.h>
#include<hip/hip_runtime.h>
#define N (1024*1024)
#define M (1000000)
__global__ void cudakernel(float *buf)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
buf[i] = 1.0f * i / N;
for(int j = 0; j < M; j++)
buf[i] = buf[i] * buf[i] - 0.25f;
}
int main()
{
float data[N]; int count = 0;
float *d_data;
hipMalloc(&d_data, N * sizeof(float));
cudakernel<<<N/256, 256>>>(d_data);
hipMemcpy(data, d_data, N * sizeof(float), hipMemcpyDeviceToHost);
hipFree(d_data);
int sel;
printf("Enter an index: ");
scanf("%d", &sel);
printf("data[%d] = %f\n", sel, data[sel]);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<stdio.h>
#include<hip/hip_runtime.h>
#define N (1024*1024)
#define M (1000000)
__global__ void cudakernel(float *buf)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
buf[i] = 1.0f * i / N;
for(int j = 0; j < M; j++)
buf[i] = buf[i] * buf[i] - 0.25f;
}
int main()
{
float data[N]; int count = 0;
float *d_data;
hipMalloc(&d_data, N * sizeof(float));
cudakernel<<<N/256, 256>>>(d_data);
hipMemcpy(data, d_data, N * sizeof(float), hipMemcpyDeviceToHost);
hipFree(d_data);
int sel;
printf("Enter an index: ");
scanf("%d", &sel);
printf("data[%d] = %f\n", sel, data[sel]);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10cudakernelPf
.globl _Z10cudakernelPf
.p2align 8
.type _Z10cudakernelPf,@function
_Z10cudakernelPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_cvt_f32_i32_e32 v3, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mul_f32_e32 v2, 0x35800000, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s0, 0xf4240
global_store_b32 v[0:1], v2, off
.LBB0_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_fmaak_f32 v2, v2, v2, 0xbe800000
s_add_i32 s0, s0, -1
s_cmp_eq_u32 s0, 0
s_cbranch_scc0 .LBB0_1
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10cudakernelPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10cudakernelPf, .Lfunc_end0-_Z10cudakernelPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10cudakernelPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10cudakernelPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<stdio.h>
#include<hip/hip_runtime.h>
#define N (1024*1024)
#define M (1000000)
__global__ void cudakernel(float *buf)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
buf[i] = 1.0f * i / N;
for(int j = 0; j < M; j++)
buf[i] = buf[i] * buf[i] - 0.25f;
}
int main()
{
float data[N]; int count = 0;
float *d_data;
hipMalloc(&d_data, N * sizeof(float));
cudakernel<<<N/256, 256>>>(d_data);
hipMemcpy(data, d_data, N * sizeof(float), hipMemcpyDeviceToHost);
hipFree(d_data);
int sel;
printf("Enter an index: ");
scanf("%d", &sel);
printf("data[%d] = %f\n", sel, data[sel]);
} | .text
.file "test.hip"
.globl _Z25__device_stub__cudakernelPf # -- Begin function _Z25__device_stub__cudakernelPf
.p2align 4, 0x90
.type _Z25__device_stub__cudakernelPf,@function
_Z25__device_stub__cudakernelPf: # @_Z25__device_stub__cudakernelPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10cudakernelPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z25__device_stub__cudakernelPf, .Lfunc_end0-_Z25__device_stub__cudakernelPf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $4194376, %rsp # imm = 0x400048
.cfi_def_cfa_offset 4194384
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 3840(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 32(%rsp)
leaq 64(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z10cudakernelPf, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 64(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 16(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 16(%rsp), %rsi
movss 64(%rsp,%rsi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
# kill: def $esi killed $esi killed $rsi
movb $1, %al
callq printf
xorl %eax, %eax
addq $4194376, %rsp # imm = 0x400048
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10cudakernelPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10cudakernelPf,@object # @_Z10cudakernelPf
.section .rodata,"a",@progbits
.globl _Z10cudakernelPf
.p2align 3, 0x0
_Z10cudakernelPf:
.quad _Z25__device_stub__cudakernelPf
.size _Z10cudakernelPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter an index: "
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "data[%d] = %f\n"
.size .L.str.2, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10cudakernelPf"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__cudakernelPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10cudakernelPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a0377_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z10cudakernelPfPf
.type _Z30__device_stub__Z10cudakernelPfPf, @function
_Z30__device_stub__Z10cudakernelPfPf:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10cudakernelPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z10cudakernelPfPf, .-_Z30__device_stub__Z10cudakernelPfPf
.globl _Z10cudakernelPf
.type _Z10cudakernelPf, @function
_Z10cudakernelPf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10cudakernelPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10cudakernelPf, .-_Z10cudakernelPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter an index: "
.LC1:
.string "%d"
.LC2:
.string "data[%d] = %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
leaq -4194304(%rsp), %r11
.cfi_def_cfa 11, 4194312
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $56, %rsp
.cfi_def_cfa_offset 4194368
movq %fs:40, %rax
movq %rax, 4194344(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $4096, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 32(%rsp), %rdi
movl $2, %ecx
movl $4194304, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 20(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 20(%rsp), %edx
movslq %edx, %rax
pxor %xmm0, %xmm0
cvtss2sd 32(%rsp,%rax,4), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 4194344(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $4194360, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq (%rsp), %rdi
call _Z30__device_stub__Z10cudakernelPfPf
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z10cudakernelPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10cudakernelPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl _Z25__device_stub__cudakernelPf # -- Begin function _Z25__device_stub__cudakernelPf
.p2align 4, 0x90
.type _Z25__device_stub__cudakernelPf,@function
_Z25__device_stub__cudakernelPf: # @_Z25__device_stub__cudakernelPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10cudakernelPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z25__device_stub__cudakernelPf, .Lfunc_end0-_Z25__device_stub__cudakernelPf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $4194376, %rsp # imm = 0x400048
.cfi_def_cfa_offset 4194384
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 3840(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 32(%rsp)
leaq 64(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z10cudakernelPf, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 64(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 16(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 16(%rsp), %rsi
movss 64(%rsp,%rsi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
# kill: def $esi killed $esi killed $rsi
movb $1, %al
callq printf
xorl %eax, %eax
addq $4194376, %rsp # imm = 0x400048
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10cudakernelPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10cudakernelPf,@object # @_Z10cudakernelPf
.section .rodata,"a",@progbits
.globl _Z10cudakernelPf
.p2align 3, 0x0
_Z10cudakernelPf:
.quad _Z25__device_stub__cudakernelPf
.size _Z10cudakernelPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter an index: "
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "data[%d] = %f\n"
.size .L.str.2, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10cudakernelPf"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__cudakernelPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10cudakernelPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void findAdjacencySizesKernel(int size, int *adjIndexes, int *output)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx < size)
{
output[idx] = adjIndexes[idx + 1] - adjIndexes[idx];
}
} | code for sm_80
Function : _Z24findAdjacencySizesKerneliPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fca00078e0205 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*00a0*/ LDG.E R7, [R2.64+0x4] ; /* 0x0000040402077981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe200078e0205 */
/*00c0*/ IADD3 R7, -R0, R7, RZ ; /* 0x0000000700077210 */
/* 0x004fca0007ffe1ff */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void findAdjacencySizesKernel(int size, int *adjIndexes, int *output)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx < size)
{
output[idx] = adjIndexes[idx + 1] - adjIndexes[idx];
}
} | .file "tmpxft_00069a65_00000000-6_findAdjacencySizesKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z24findAdjacencySizesKerneliPiS_iPiS_
.type _Z47__device_stub__Z24findAdjacencySizesKerneliPiS_iPiS_, @function
_Z47__device_stub__Z24findAdjacencySizesKerneliPiS_iPiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z24findAdjacencySizesKerneliPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z24findAdjacencySizesKerneliPiS_iPiS_, .-_Z47__device_stub__Z24findAdjacencySizesKerneliPiS_iPiS_
.globl _Z24findAdjacencySizesKerneliPiS_
.type _Z24findAdjacencySizesKerneliPiS_, @function
_Z24findAdjacencySizesKerneliPiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z24findAdjacencySizesKerneliPiS_iPiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24findAdjacencySizesKerneliPiS_, .-_Z24findAdjacencySizesKerneliPiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24findAdjacencySizesKerneliPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24findAdjacencySizesKerneliPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void findAdjacencySizesKernel(int size, int *adjIndexes, int *output)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx < size)
{
output[idx] = adjIndexes[idx + 1] - adjIndexes[idx];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void findAdjacencySizesKernel(int size, int *adjIndexes, int *output)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx < size)
{
output[idx] = adjIndexes[idx + 1] - adjIndexes[idx];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void findAdjacencySizesKernel(int size, int *adjIndexes, int *output)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx < size)
{
output[idx] = adjIndexes[idx + 1] - adjIndexes[idx];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24findAdjacencySizesKerneliPiS_
.globl _Z24findAdjacencySizesKerneliPiS_
.p2align 8
.type _Z24findAdjacencySizesKerneliPiS_,@function
_Z24findAdjacencySizesKerneliPiS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24findAdjacencySizesKerneliPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24findAdjacencySizesKerneliPiS_, .Lfunc_end0-_Z24findAdjacencySizesKerneliPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24findAdjacencySizesKerneliPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24findAdjacencySizesKerneliPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void findAdjacencySizesKernel(int size, int *adjIndexes, int *output)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx < size)
{
output[idx] = adjIndexes[idx + 1] - adjIndexes[idx];
}
} | .text
.file "findAdjacencySizesKernel.hip"
.globl _Z39__device_stub__findAdjacencySizesKerneliPiS_ # -- Begin function _Z39__device_stub__findAdjacencySizesKerneliPiS_
.p2align 4, 0x90
.type _Z39__device_stub__findAdjacencySizesKerneliPiS_,@function
_Z39__device_stub__findAdjacencySizesKerneliPiS_: # @_Z39__device_stub__findAdjacencySizesKerneliPiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24findAdjacencySizesKerneliPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z39__device_stub__findAdjacencySizesKerneliPiS_, .Lfunc_end0-_Z39__device_stub__findAdjacencySizesKerneliPiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24findAdjacencySizesKerneliPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24findAdjacencySizesKerneliPiS_,@object # @_Z24findAdjacencySizesKerneliPiS_
.section .rodata,"a",@progbits
.globl _Z24findAdjacencySizesKerneliPiS_
.p2align 3, 0x0
_Z24findAdjacencySizesKerneliPiS_:
.quad _Z39__device_stub__findAdjacencySizesKerneliPiS_
.size _Z24findAdjacencySizesKerneliPiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24findAdjacencySizesKerneliPiS_"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__findAdjacencySizesKerneliPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24findAdjacencySizesKerneliPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z24findAdjacencySizesKerneliPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fca00078e0205 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*00a0*/ LDG.E R7, [R2.64+0x4] ; /* 0x0000040402077981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe200078e0205 */
/*00c0*/ IADD3 R7, -R0, R7, RZ ; /* 0x0000000700077210 */
/* 0x004fca0007ffe1ff */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24findAdjacencySizesKerneliPiS_
.globl _Z24findAdjacencySizesKerneliPiS_
.p2align 8
.type _Z24findAdjacencySizesKerneliPiS_,@function
_Z24findAdjacencySizesKerneliPiS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24findAdjacencySizesKerneliPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24findAdjacencySizesKerneliPiS_, .Lfunc_end0-_Z24findAdjacencySizesKerneliPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24findAdjacencySizesKerneliPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24findAdjacencySizesKerneliPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00069a65_00000000-6_findAdjacencySizesKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z24findAdjacencySizesKerneliPiS_iPiS_
.type _Z47__device_stub__Z24findAdjacencySizesKerneliPiS_iPiS_, @function
_Z47__device_stub__Z24findAdjacencySizesKerneliPiS_iPiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z24findAdjacencySizesKerneliPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z24findAdjacencySizesKerneliPiS_iPiS_, .-_Z47__device_stub__Z24findAdjacencySizesKerneliPiS_iPiS_
.globl _Z24findAdjacencySizesKerneliPiS_
.type _Z24findAdjacencySizesKerneliPiS_, @function
_Z24findAdjacencySizesKerneliPiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z24findAdjacencySizesKerneliPiS_iPiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24findAdjacencySizesKerneliPiS_, .-_Z24findAdjacencySizesKerneliPiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24findAdjacencySizesKerneliPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24findAdjacencySizesKerneliPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "findAdjacencySizesKernel.hip"
.globl _Z39__device_stub__findAdjacencySizesKerneliPiS_ # -- Begin function _Z39__device_stub__findAdjacencySizesKerneliPiS_
.p2align 4, 0x90
.type _Z39__device_stub__findAdjacencySizesKerneliPiS_,@function
_Z39__device_stub__findAdjacencySizesKerneliPiS_: # @_Z39__device_stub__findAdjacencySizesKerneliPiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24findAdjacencySizesKerneliPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z39__device_stub__findAdjacencySizesKerneliPiS_, .Lfunc_end0-_Z39__device_stub__findAdjacencySizesKerneliPiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24findAdjacencySizesKerneliPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24findAdjacencySizesKerneliPiS_,@object # @_Z24findAdjacencySizesKerneliPiS_
.section .rodata,"a",@progbits
.globl _Z24findAdjacencySizesKerneliPiS_
.p2align 3, 0x0
_Z24findAdjacencySizesKerneliPiS_:
.quad _Z39__device_stub__findAdjacencySizesKerneliPiS_
.size _Z24findAdjacencySizesKerneliPiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24findAdjacencySizesKerneliPiS_"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__findAdjacencySizesKerneliPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24findAdjacencySizesKerneliPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //
// Created by heidies on 7/8/18.
//
#include <cuda_runtime.h>
#include <iostream>
#include <sys/time.h>
using namespace std;
#define CHECK(call) \
{ \
const cudaError_t error = call; \
if(error != cudaSuccess){ \
printf("Error: %s %d, ", __FILE__, __LINE__); \
printf("code: %d, reason %s\n", error, cudaGetErrorString(error)); \
exit(1); \
} \
}
int recursiveReduce(int *data, const int size){
if(size == 1) return data[0];
int const stride = size / 2;
for(int i = 0; i < stride; i++){
data[i] += data[i + stride];
}
return recursiveReduce(data, stride);
}
__global__ void warmingUp(int *g_idata, int *g_odata, unsigned int n){
unsigned int tid = threadIdx.x;
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
int *idata = g_idata + blockIdx.x * blockDim.x;
if(idx >= n) return ;
for(int stride = 1; stride < blockDim.x; stride <<= 1){
if(tid % (2 * stride) == 0)
idata[tid] += idata[tid + stride];
__syncthreads();
}
if(tid == 0) g_odata[blockIdx.x] = idata[0];
}
__global__ void reduceNeighbored(int *g_idata, int *g_odata, unsigned int n){
unsigned int tid = threadIdx.x;
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
int *idata = g_idata + blockIdx.x * blockDim.x;
if(idx >= n) return ;
for(int stride = 1; stride < blockDim.x; stride <<= 1){
if(tid % (2 * stride) == 0)
idata[tid] += idata[tid + stride];
__syncthreads();
}
if(tid == 0) g_odata[blockIdx.x] = idata[0];
}
__global__ void reduceNeighboredLess(int *g_idata, int *g_odata, unsigned int n){
unsigned int tid = threadIdx.x;
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
int *idata = g_idata + blockIdx.x * blockDim.x;
if(idx >= n) return;
for(int stride = 1; stride < blockDim.x; stride <<= 1){
int index = 2 * stride * tid;
if(index < blockDim.x / 2)
idata[tid] += idata[tid + stride];
__syncthreads();
}
if(tid == 0) g_odata[blockIdx.x] = idata[0];
}
__global__ void reduceInterleaved(int *g_idata, int *g_odata, unsigned int n){
unsigned int tid = threadIdx.x;
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
int *idata = g_idata + blockIdx.x * blockDim.x;
if(idx >= n) return;
for(int stride = blockDim.x / 2; stride > 0; stride >>= 1){
if(tid < stride)
idata[tid] += idata[tid + stride];
__syncthreads();
}
if(tid == 0) g_odata[blockIdx.x] = idata[0];
}
__global__ void reduceUnrolling2(int *g_idata, int *g_odata, unsigned int n){
unsigned int tid = threadIdx.x;
unsigned int idx = (2 * blockIdx.x) * blockDim.x + threadIdx.x;
int *idata = g_idata + (2 * blockIdx.x) * blockDim.x;
if(idx + blockDim.x < n) g_idata[idx] += g_idata[idx + blockDim.x];
__syncthreads();
for(int stride = blockDim.x / 2; stride > 0; stride >>= 1){
if(tid < stride)
idata[tid] += idata[tid + stride];
__syncthreads();
}
if(tid == 0) g_odata[blockIdx.x] = idata[0];
}
__global__ void reduceUnrolling4(int *g_idata, int *g_odata, unsigned int n){
unsigned int tid = threadIdx.x;
unsigned int idx = (4 * blockIdx.x) * blockDim.x + threadIdx.x;
int *idata = g_idata + (4 * blockIdx.x) * blockDim.x;
if(idx + 3 * blockDim.x < n){
g_idata[idx] += g_idata[idx + blockDim.x];
g_idata[idx] += g_idata[idx + 2 * blockDim.x];
g_idata[idx] += g_idata[idx + 3 * blockDim.x];
}
__syncthreads();
for(int stride = blockDim.x / 2; stride > 0; stride >>= 1){
if(tid < stride)
idata[tid] += idata[tid + stride];
__syncthreads();
}
if(tid == 0) g_odata[blockIdx.x] = idata[0];
}
__global__ void reduceUnrolling8(int *g_idata, int *g_odata, unsigned int n){
unsigned int tid = threadIdx.x;
unsigned int idx = (8 * blockIdx.x) * blockDim.x + threadIdx.x;
int *idata = g_idata + (8 * blockIdx.x) * blockDim.x;
if(idx + 7 * blockDim.x < n){
g_idata[idx] += g_idata[idx + blockDim.x];
g_idata[idx] += g_idata[idx + 2 * blockDim.x];
g_idata[idx] += g_idata[idx + 3 * blockDim.x];
g_idata[idx] += g_idata[idx + 4 * blockDim.x];
g_idata[idx] += g_idata[idx + 5 * blockDim.x];
g_idata[idx] += g_idata[idx + 6 * blockDim.x];
g_idata[idx] += g_idata[idx + 7 * blockDim.x];
}
__syncthreads();
for(int stride = blockDim.x / 2; stride > 0; stride >>= 1){
if(tid < stride)
idata[tid] += idata[tid + stride];
__syncthreads();
}
if(tid == 0) g_odata[blockIdx.x] = idata[0];
}
__global__ void reduceUnrollWarps8(int *g_idata, int *g_odata, unsigned int n){
unsigned int tid = threadIdx.x;
unsigned int idx = (8 * blockIdx.x) * blockDim.x + threadIdx.x;
int *idata = g_idata + (8 * blockIdx.x) * blockDim.x;
if(idx + 7 * blockDim.x < n){
g_idata[idx] += g_idata[idx + blockDim.x];
g_idata[idx] += g_idata[idx + 2 * blockDim.x];
g_idata[idx] += g_idata[idx + 3 * blockDim.x];
g_idata[idx] += g_idata[idx + 4 * blockDim.x];
g_idata[idx] += g_idata[idx + 5 * blockDim.x];
g_idata[idx] += g_idata[idx + 6 * blockDim.x];
g_idata[idx] += g_idata[idx + 7 * blockDim.x];
}
__syncthreads();
for(int stride = blockDim.x / 2; stride > 32; stride >>= 1){
if(tid < stride)
idata[tid] += idata[tid + stride];
__syncthreads();
}
if(tid < 32){
volatile int *vmem = idata;
vmem[tid] += vmem[tid + 32];
vmem[tid] += vmem[tid + 16];
vmem[tid] += vmem[tid + 8];
vmem[tid] += vmem[tid + 4];
vmem[tid] += vmem[tid + 2];
vmem[tid] += vmem[tid + 1];
}
if(tid == 0) g_odata[blockIdx.x] = idata[0];
}
__global__ void reduceCompleteUnrollWarps8(int *g_idata, int *g_odata, unsigned int n){
unsigned int tid = threadIdx.x;
unsigned int idx = (8 * blockIdx.x) * blockDim.x + threadIdx.x;
int *idata = g_idata + (8 * blockIdx.x) * blockDim.x;
if(idx + 7 * blockDim.x < n){
g_idata[idx] += g_idata[idx + blockDim.x];
g_idata[idx] += g_idata[idx + 2 * blockDim.x];
g_idata[idx] += g_idata[idx + 3 * blockDim.x];
g_idata[idx] += g_idata[idx + 4 * blockDim.x];
g_idata[idx] += g_idata[idx + 5 * blockDim.x];
g_idata[idx] += g_idata[idx + 6 * blockDim.x];
g_idata[idx] += g_idata[idx + 7 * blockDim.x];
}
__syncthreads();
if(blockDim.x >= 1024 && tid < 512)
idata[tid] += idata[tid + 512];
__syncthreads();
if(blockDim.x >= 512 && tid < 256)
idata[tid] += idata[tid + 256];
__syncthreads();
if(blockDim.x >= 256 && tid < 128)
idata[tid] += idata[tid + 128];
__syncthreads();
if(blockDim.x >= 128 && tid < 64)
idata[idx] += idata[tid + 64];
__syncthreads();
if(tid < 32){
volatile int *vmem = idata;
vmem[tid] += vmem[tid + 32];
vmem[tid] += vmem[tid + 16];
vmem[tid] += vmem[tid + 8];
vmem[tid] += vmem[tid + 4];
vmem[tid] += vmem[tid + 2];
vmem[tid] += vmem[tid + 1];
}
if(tid == 0) g_odata[blockIdx.x] = idata[0];
}
template <unsigned int iBlockSize>
__global__ void reduceCompleteUnroll(int *g_idata, int *g_odata, unsigned int n){
unsigned int tid = threadIdx.x;
unsigned int idx = (8 * blockIdx.x) * blockDim.x + threadIdx.x;
int *idata = g_idata + (8 * blockIdx.x) * blockDim.x;
if(idx + 7 * blockDim.x < n){
g_idata[idx] += g_idata[idx + blockDim.x];
g_idata[idx] += g_idata[idx + 2 * blockDim.x];
g_idata[idx] += g_idata[idx + 3 * blockDim.x];
g_idata[idx] += g_idata[idx + 4 * blockDim.x];
g_idata[idx] += g_idata[idx + 5 * blockDim.x];
g_idata[idx] += g_idata[idx + 6 * blockDim.x];
g_idata[idx] += g_idata[idx + 7 * blockDim.x];
}
__syncthreads();
if(iBlockSize >= 1024 && tid < 512)
idata[tid] += idata[tid + 512];
__syncthreads();
if(iBlockSize >= 512 && tid < 256)
idata[tid] += idata[tid + 256];
__syncthreads();
if(iBlockSize >= 256 && tid < 128)
idata[tid] += idata[tid + 128];
__syncthreads();
if(iBlockSize >= 128 && tid < 64)
idata[idx] += idata[tid + 64];
__syncthreads();
if(tid < 32){
volatile int *vmem = idata;
vmem[tid] += vmem[tid + 32];
vmem[tid] += vmem[tid + 16];
vmem[tid] += vmem[tid + 8];
vmem[tid] += vmem[tid + 4];
vmem[tid] += vmem[tid + 2];
vmem[tid] += vmem[tid + 1];
}
if(tid == 0) g_odata[blockIdx.x] = idata[0];
}
double seconds(){
struct timeval tp;
gettimeofday(&tp, NULL);
return ((double)tp.tv_sec + (double)tp.tv_usec * 1e-6) * 1e+3;
}
int main(int argc, char **argv){
int dev = 0;
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, dev);
cout << "Starting reduction at " << argv[0] << " ";
cout << "device " << dev << ": " << deviceProp.name << " ";
cudaSetDevice(dev);
bool bResult = false;
int size = 1 << 24;
cout << " with array size " << size << " ";
int blocksize = 512;
if(argc > 1)
blocksize = atoi(argv[1]);
dim3 block (blocksize, 1);
dim3 grid ((size + block.x - 1) / block.x, 1);
cout << "grid " << grid.x << " block " << block.x << endl;
size_t nBytes = size * sizeof(int);
int *h_idata = (int *)malloc(nBytes);
int *h_odata = (int *)malloc(grid.x * sizeof(int));
int *tmp = (int *)malloc(nBytes);
for(int i = 0; i < size; ++ i){
h_idata[i] = (int)(rand() & 0xFF);
}
memcpy(tmp, h_idata, nBytes);
double iStart, iElaps;
int gpu_sum = 0;
int *d_idata = NULL;
cudaMalloc((void **)&d_idata, nBytes);
int *d_odata = NULL;
cudaMalloc((void **)&d_odata, grid.x * sizeof(int));
iStart = seconds();
int cpu_sum = recursiveReduce(tmp, size);
iElaps = seconds() - iStart;
cout << "cpu reduce elapsed " << iElaps << " ms cpu_sum: " << cpu_sum << endl;
cudaMemcpy(d_idata, h_idata, nBytes, cudaMemcpyHostToDevice);
cudaDeviceSynchronize();
iStart = seconds();
warmingUp<<<grid, block>>>(d_idata, d_odata, size);
cudaDeviceSynchronize();
iElaps = seconds() - iStart;
cudaMemcpy(h_odata, d_odata, grid.x * sizeof(int), cudaMemcpyDeviceToHost);
gpu_sum = 0;
for(int i = 0; i < grid.x; ++ i){
gpu_sum += h_odata[i];
}
cout << "gpu warmingUp elapsed " << iElaps << " ms gpu_sum: " << gpu_sum << " <<<grid " << grid.x << " block " << block.x << ">>>" << endl;
cudaMemcpy(d_idata, h_idata, nBytes, cudaMemcpyHostToDevice);
cudaDeviceSynchronize();
iStart = seconds();
reduceNeighbored<<<grid, block>>>(d_idata, d_odata, size);
cudaDeviceSynchronize();
iElaps = seconds() - iStart;
cudaMemcpy(h_odata, d_odata, grid.x * sizeof(int), cudaMemcpyDeviceToHost);
gpu_sum = 0;
for(int i = 0; i < grid.x; ++ i){
gpu_sum += h_odata[i];
}
cout << "gpu Neighbored elapsed " << iElaps << " ms gpu_sum: " << gpu_sum << " <<<grid " << grid.x << " block " << block.x << ">>>" << endl;
cudaMemcpy(d_idata, h_idata, nBytes, cudaMemcpyHostToDevice);
cudaDeviceSynchronize();
iStart = seconds();
reduceCompleteUnrollWarps8<<<grid.x / 8, block>>>(d_idata, d_odata, size);
cudaDeviceSynchronize();
iElaps = seconds() - iStart;
cudaMemcpy(h_odata, d_odata, grid.x * sizeof(int), cudaMemcpyDeviceToHost);
gpu_sum = 0;
for(int i = 0; i < grid.x / 8; ++ i){
gpu_sum += h_odata[i];
}
cout << "gpu nroll elapsed " << iElaps << " ms gpu_sum: " << gpu_sum << " <<<grid " << grid.x / 8 << " block " << block.x << ">>>" << endl;
free(h_idata);
free(h_odata);
free(tmp);
cudaFree(d_idata);
cudaFree(d_odata);
cudaDeviceReset();
bResult = (gpu_sum == cpu_sum);
if(!bResult) cout << "Test failed!" << endl;
return EXIT_SUCCESS;
} | .file "tmpxft_0008318b_00000000-6_reduceInteger.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3676:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3676:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15recursiveReducePii
.type _Z15recursiveReducePii, @function
_Z15recursiveReducePii:
.LFB3669:
.cfi_startproc
endbr64
cmpl $1, %esi
je .L12
subq $8, %rsp
.cfi_def_cfa_offset 16
movl %esi, %edx
movl %esi, %eax
shrl $31, %eax
leal (%rax,%rsi), %esi
sarl %esi
cmpl $1, %edx
jle .L6
movslq %esi, %rax
leaq (%rdi,%rax,4), %rcx
movl $0, %eax
.L7:
movl (%rcx,%rax,4), %edx
addl %edx, (%rdi,%rax,4)
addq $1, %rax
cmpl %eax, %esi
jg .L7
.L6:
call _Z15recursiveReducePii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L12:
movl (%rdi), %eax
ret
.cfi_endproc
.LFE3669:
.size _Z15recursiveReducePii, .-_Z15recursiveReducePii
.globl _Z7secondsv
.type _Z7secondsv, @function
_Z7secondsv:
.LFB3672:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
mulsd .LC1(%rip), %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size _Z7secondsv, .-_Z7secondsv
.globl _Z31__device_stub__Z9warmingUpPiS_jPiS_j
.type _Z31__device_stub__Z9warmingUpPiS_jPiS_j, @function
_Z31__device_stub__Z9warmingUpPiS_jPiS_j:
.LFB3698:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9warmingUpPiS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z31__device_stub__Z9warmingUpPiS_jPiS_j, .-_Z31__device_stub__Z9warmingUpPiS_jPiS_j
.globl _Z9warmingUpPiS_j
.type _Z9warmingUpPiS_j, @function
_Z9warmingUpPiS_j:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9warmingUpPiS_jPiS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z9warmingUpPiS_j, .-_Z9warmingUpPiS_j
.globl _Z39__device_stub__Z16reduceNeighboredPiS_jPiS_j
.type _Z39__device_stub__Z16reduceNeighboredPiS_jPiS_j, @function
_Z39__device_stub__Z16reduceNeighboredPiS_jPiS_j:
.LFB3700:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16reduceNeighboredPiS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3700:
.size _Z39__device_stub__Z16reduceNeighboredPiS_jPiS_j, .-_Z39__device_stub__Z16reduceNeighboredPiS_jPiS_j
.globl _Z16reduceNeighboredPiS_j
.type _Z16reduceNeighboredPiS_j, @function
_Z16reduceNeighboredPiS_j:
.LFB3701:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16reduceNeighboredPiS_jPiS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _Z16reduceNeighboredPiS_j, .-_Z16reduceNeighboredPiS_j
.globl _Z43__device_stub__Z20reduceNeighboredLessPiS_jPiS_j
.type _Z43__device_stub__Z20reduceNeighboredLessPiS_jPiS_j, @function
_Z43__device_stub__Z20reduceNeighboredLessPiS_jPiS_j:
.LFB3702:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20reduceNeighboredLessPiS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3702:
.size _Z43__device_stub__Z20reduceNeighboredLessPiS_jPiS_j, .-_Z43__device_stub__Z20reduceNeighboredLessPiS_jPiS_j
.globl _Z20reduceNeighboredLessPiS_j
.type _Z20reduceNeighboredLessPiS_j, @function
_Z20reduceNeighboredLessPiS_j:
.LFB3703:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z20reduceNeighboredLessPiS_jPiS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3703:
.size _Z20reduceNeighboredLessPiS_j, .-_Z20reduceNeighboredLessPiS_j
.globl _Z40__device_stub__Z17reduceInterleavedPiS_jPiS_j
.type _Z40__device_stub__Z17reduceInterleavedPiS_jPiS_j, @function
_Z40__device_stub__Z17reduceInterleavedPiS_jPiS_j:
.LFB3704:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L45
.L41:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17reduceInterleavedPiS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L41
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3704:
.size _Z40__device_stub__Z17reduceInterleavedPiS_jPiS_j, .-_Z40__device_stub__Z17reduceInterleavedPiS_jPiS_j
.globl _Z17reduceInterleavedPiS_j
.type _Z17reduceInterleavedPiS_j, @function
_Z17reduceInterleavedPiS_j:
.LFB3705:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z17reduceInterleavedPiS_jPiS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3705:
.size _Z17reduceInterleavedPiS_j, .-_Z17reduceInterleavedPiS_j
.globl _Z39__device_stub__Z16reduceUnrolling2PiS_jPiS_j
.type _Z39__device_stub__Z16reduceUnrolling2PiS_jPiS_j, @function
_Z39__device_stub__Z16reduceUnrolling2PiS_jPiS_j:
.LFB3706:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L53
.L49:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L54
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16reduceUnrolling2PiS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L49
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3706:
.size _Z39__device_stub__Z16reduceUnrolling2PiS_jPiS_j, .-_Z39__device_stub__Z16reduceUnrolling2PiS_jPiS_j
.globl _Z16reduceUnrolling2PiS_j
.type _Z16reduceUnrolling2PiS_j, @function
_Z16reduceUnrolling2PiS_j:
.LFB3707:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16reduceUnrolling2PiS_jPiS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3707:
.size _Z16reduceUnrolling2PiS_j, .-_Z16reduceUnrolling2PiS_j
.globl _Z39__device_stub__Z16reduceUnrolling4PiS_jPiS_j
.type _Z39__device_stub__Z16reduceUnrolling4PiS_jPiS_j, @function
_Z39__device_stub__Z16reduceUnrolling4PiS_jPiS_j:
.LFB3708:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L61
.L57:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L62
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L61:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16reduceUnrolling4PiS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L57
.L62:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3708:
.size _Z39__device_stub__Z16reduceUnrolling4PiS_jPiS_j, .-_Z39__device_stub__Z16reduceUnrolling4PiS_jPiS_j
.globl _Z16reduceUnrolling4PiS_j
.type _Z16reduceUnrolling4PiS_j, @function
_Z16reduceUnrolling4PiS_j:
.LFB3709:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16reduceUnrolling4PiS_jPiS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3709:
.size _Z16reduceUnrolling4PiS_j, .-_Z16reduceUnrolling4PiS_j
.globl _Z39__device_stub__Z16reduceUnrolling8PiS_jPiS_j
.type _Z39__device_stub__Z16reduceUnrolling8PiS_jPiS_j, @function
_Z39__device_stub__Z16reduceUnrolling8PiS_jPiS_j:
.LFB3710:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L69
.L65:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L70
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L69:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16reduceUnrolling8PiS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L65
.L70:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3710:
.size _Z39__device_stub__Z16reduceUnrolling8PiS_jPiS_j, .-_Z39__device_stub__Z16reduceUnrolling8PiS_jPiS_j
.globl _Z16reduceUnrolling8PiS_j
.type _Z16reduceUnrolling8PiS_j, @function
_Z16reduceUnrolling8PiS_j:
.LFB3711:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16reduceUnrolling8PiS_jPiS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3711:
.size _Z16reduceUnrolling8PiS_j, .-_Z16reduceUnrolling8PiS_j
.globl _Z41__device_stub__Z18reduceUnrollWarps8PiS_jPiS_j
.type _Z41__device_stub__Z18reduceUnrollWarps8PiS_jPiS_j, @function
_Z41__device_stub__Z18reduceUnrollWarps8PiS_jPiS_j:
.LFB3712:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L77
.L73:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L78
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L77:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18reduceUnrollWarps8PiS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L73
.L78:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3712:
.size _Z41__device_stub__Z18reduceUnrollWarps8PiS_jPiS_j, .-_Z41__device_stub__Z18reduceUnrollWarps8PiS_jPiS_j
.globl _Z18reduceUnrollWarps8PiS_j
.type _Z18reduceUnrollWarps8PiS_j, @function
_Z18reduceUnrollWarps8PiS_j:
.LFB3713:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z18reduceUnrollWarps8PiS_jPiS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3713:
.size _Z18reduceUnrollWarps8PiS_j, .-_Z18reduceUnrollWarps8PiS_j
.globl _Z49__device_stub__Z26reduceCompleteUnrollWarps8PiS_jPiS_j
.type _Z49__device_stub__Z26reduceCompleteUnrollWarps8PiS_jPiS_j, @function
_Z49__device_stub__Z26reduceCompleteUnrollWarps8PiS_jPiS_j:
.LFB3714:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L85
.L81:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L86
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L85:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26reduceCompleteUnrollWarps8PiS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L81
.L86:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3714:
.size _Z49__device_stub__Z26reduceCompleteUnrollWarps8PiS_jPiS_j, .-_Z49__device_stub__Z26reduceCompleteUnrollWarps8PiS_jPiS_j
.globl _Z26reduceCompleteUnrollWarps8PiS_j
.type _Z26reduceCompleteUnrollWarps8PiS_j, @function
_Z26reduceCompleteUnrollWarps8PiS_j:
.LFB3715:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z26reduceCompleteUnrollWarps8PiS_jPiS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3715:
.size _Z26reduceCompleteUnrollWarps8PiS_j, .-_Z26reduceCompleteUnrollWarps8PiS_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Starting reduction at "
.LC3:
.string " "
.LC4:
.string "device "
.LC5:
.string ": "
.LC6:
.string " with array size "
.LC7:
.string " "
.LC8:
.string "grid "
.LC9:
.string " block "
.LC10:
.string "cpu reduce elapsed "
.LC11:
.string " ms cpu_sum: "
.LC12:
.string "gpu warmingUp elapsed "
.LC13:
.string " ms gpu_sum: "
.LC14:
.string " <<<grid "
.LC15:
.string ">>>"
.LC16:
.string "gpu Neighbored elapsed "
.LC17:
.string "gpu nroll elapsed "
.LC18:
.string "Test failed!"
.text
.globl main
.type main, @function
main:
.LFB3673:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1160, %rsp
.cfi_def_cfa_offset 1216
movl %edi, %r12d
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 1144(%rsp)
xorl %eax, %eax
leaq 112(%rsp), %r14
movl $0, %esi
movq %r14, %rdi
call cudaGetDeviceProperties_v2@PLT
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 0(%rbp), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC3(%rip), %r13
movq %r13, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $0, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r14, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r13, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $0, %edi
call cudaSetDevice@PLT
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $16777216, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC7(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $512, %ebx
cmpl $1, %r12d
jg .L112
.L90:
movl %ebx, (%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leal 16777215(%rbx), %eax
movl $0, %edx
divl %ebx
movl %eax, %r13d
movl $1, 92(%rsp)
movl $1, 96(%rsp)
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r13d, %r15d
movq %r15, 24(%rsp)
movq %r15, %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC9(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %eax
movq %rax, 8(%rsp)
movq %rax, %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $67108864, %edi
call malloc@PLT
movq %rax, %r14
salq $2, %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %r12
movl $67108864, %edi
call malloc@PLT
movq %rax, 16(%rsp)
movq %r14, %rbx
leaq 67108864(%r14), %rbp
.L91:
call rand@PLT
movzbl %al, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L91
movl $67108864, %edx
movq %r14, %rsi
movq 16(%rsp), %rbx
movq %rbx, %rdi
call memcpy@PLT
movq $0, 56(%rsp)
leaq 56(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
movq $0, 64(%rsp)
leaq 64(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
call _Z7secondsv
movsd %xmm0, 32(%rsp)
movl $16777216, %esi
movq %rbx, %rdi
call _Z15recursiveReducePii
movl %eax, %ebp
movl %eax, 44(%rsp)
call _Z7secondsv
movapd %xmm0, %xmm1
subsd 32(%rsp), %xmm1
movq %xmm1, %rbx
leaq .LC10(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC11(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebp, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %ecx
movl $67108864, %edx
movq %r14, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
call _Z7secondsv
movsd %xmm0, 32(%rsp)
movl %r13d, 88(%rsp)
movl (%rsp), %eax
movl %eax, 76(%rsp)
movl 84(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movq 88(%rsp), %rdi
movl 96(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L113
.L92:
call cudaDeviceSynchronize@PLT
call _Z7secondsv
subsd 32(%rsp), %xmm0
movq %xmm0, %rbp
movl $2, %ecx
movq %r15, %rdx
movq 64(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
cmpl $-16777216, (%rsp)
ja .L104
movl $0, %eax
movl $0, %ebx
.L94:
addl (%r12,%rax,4), %ebx
addq $1, %rax
cmpl %r13d, %eax
jb .L94
.L93:
leaq .LC12(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC13(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC14(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 24(%rsp), %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC9(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 8(%rsp), %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC15(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %ecx
movl $67108864, %edx
movq %r14, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
call _Z7secondsv
movsd %xmm0, 32(%rsp)
movl 84(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movq 88(%rsp), %rdi
movl 96(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L114
.L95:
call cudaDeviceSynchronize@PLT
call _Z7secondsv
subsd 32(%rsp), %xmm0
movq %xmm0, %rbp
movl $2, %ecx
movq %r15, %rdx
movq 64(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
cmpl $-16777216, (%rsp)
ja .L105
movl $0, %eax
movl $0, %ebx
.L97:
addl (%r12,%rax,4), %ebx
addq $1, %rax
cmpl %r13d, %eax
jb .L97
.L96:
leaq .LC16(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC13(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC14(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 24(%rsp), %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC9(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 8(%rsp), %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC15(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %ecx
movl $67108864, %edx
movq %r14, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
call _Z7secondsv
movsd %xmm0, (%rsp)
movl %r13d, %ebx
shrl $3, %ebx
movl %ebx, 100(%rsp)
movl $1, 104(%rsp)
movl 84(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movq 100(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L115
.L98:
call cudaDeviceSynchronize@PLT
call _Z7secondsv
subsd (%rsp), %xmm0
movsd %xmm0, (%rsp)
movl $2, %ecx
movq %r15, %rdx
movq 64(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
cmpl $7, %r13d
jbe .L106
movl $0, %eax
movl $0, %ebp
.L100:
addl (%r12,%rax,4), %ebp
addq $1, %rax
cmpl %ebx, %eax
jb .L100
.L99:
leaq .LC17(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd (%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC13(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebp, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC14(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC9(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 8(%rsp), %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC15(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r14, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
call cudaDeviceReset@PLT
cmpl %ebp, 44(%rsp)
jne .L116
.L101:
movq 1144(%rsp), %rax
subq %fs:40, %rax
jne .L117
movl $0, %eax
addq $1160, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L112:
.cfi_restore_state
movq 8(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebx
jmp .L90
.L113:
movl $16777216, %edx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z31__device_stub__Z9warmingUpPiS_jPiS_j
jmp .L92
.L104:
movl $0, %ebx
jmp .L93
.L114:
movl $16777216, %edx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z39__device_stub__Z16reduceNeighboredPiS_jPiS_j
jmp .L95
.L105:
movl $0, %ebx
jmp .L96
.L115:
movl $16777216, %edx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z49__device_stub__Z26reduceCompleteUnrollWarps8PiS_jPiS_j
jmp .L98
.L106:
movl $0, %ebp
jmp .L99
.L116:
leaq .LC18(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L101
.L117:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3673:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC19:
.string "_Z26reduceCompleteUnrollWarps8PiS_j"
.section .rodata.str1.1
.LC20:
.string "_Z18reduceUnrollWarps8PiS_j"
.LC21:
.string "_Z16reduceUnrolling8PiS_j"
.LC22:
.string "_Z16reduceUnrolling4PiS_j"
.LC23:
.string "_Z16reduceUnrolling2PiS_j"
.LC24:
.string "_Z17reduceInterleavedPiS_j"
.LC25:
.string "_Z20reduceNeighboredLessPiS_j"
.LC26:
.string "_Z16reduceNeighboredPiS_j"
.LC27:
.string "_Z9warmingUpPiS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3717:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z26reduceCompleteUnrollWarps8PiS_j(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z18reduceUnrollWarps8PiS_j(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _Z16reduceUnrolling8PiS_j(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _Z16reduceUnrolling4PiS_j(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC23(%rip), %rdx
movq %rdx, %rcx
leaq _Z16reduceUnrolling2PiS_j(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC24(%rip), %rdx
movq %rdx, %rcx
leaq _Z17reduceInterleavedPiS_j(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC25(%rip), %rdx
movq %rdx, %rcx
leaq _Z20reduceNeighboredLessPiS_j(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC26(%rip), %rdx
movq %rdx, %rcx
leaq _Z16reduceNeighboredPiS_j(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC27(%rip), %rdx
movq %rdx, %rcx
leaq _Z9warmingUpPiS_j(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3717:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1598689907
.long 1051772663
.align 8
.LC1:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //
// Created by heidies on 7/8/18.
//
#include <cuda_runtime.h>
#include <iostream>
#include <sys/time.h>
using namespace std;
#define CHECK(call) \
{ \
const cudaError_t error = call; \
if(error != cudaSuccess){ \
printf("Error: %s %d, ", __FILE__, __LINE__); \
printf("code: %d, reason %s\n", error, cudaGetErrorString(error)); \
exit(1); \
} \
}
int recursiveReduce(int *data, const int size){
if(size == 1) return data[0];
int const stride = size / 2;
for(int i = 0; i < stride; i++){
data[i] += data[i + stride];
}
return recursiveReduce(data, stride);
}
__global__ void warmingUp(int *g_idata, int *g_odata, unsigned int n){
unsigned int tid = threadIdx.x;
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
int *idata = g_idata + blockIdx.x * blockDim.x;
if(idx >= n) return ;
for(int stride = 1; stride < blockDim.x; stride <<= 1){
if(tid % (2 * stride) == 0)
idata[tid] += idata[tid + stride];
__syncthreads();
}
if(tid == 0) g_odata[blockIdx.x] = idata[0];
}
__global__ void reduceNeighbored(int *g_idata, int *g_odata, unsigned int n){
unsigned int tid = threadIdx.x;
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
int *idata = g_idata + blockIdx.x * blockDim.x;
if(idx >= n) return ;
for(int stride = 1; stride < blockDim.x; stride <<= 1){
if(tid % (2 * stride) == 0)
idata[tid] += idata[tid + stride];
__syncthreads();
}
if(tid == 0) g_odata[blockIdx.x] = idata[0];
}
__global__ void reduceNeighboredLess(int *g_idata, int *g_odata, unsigned int n){
unsigned int tid = threadIdx.x;
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
int *idata = g_idata + blockIdx.x * blockDim.x;
if(idx >= n) return;
for(int stride = 1; stride < blockDim.x; stride <<= 1){
int index = 2 * stride * tid;
if(index < blockDim.x / 2)
idata[tid] += idata[tid + stride];
__syncthreads();
}
if(tid == 0) g_odata[blockIdx.x] = idata[0];
}
__global__ void reduceInterleaved(int *g_idata, int *g_odata, unsigned int n){
unsigned int tid = threadIdx.x;
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
int *idata = g_idata + blockIdx.x * blockDim.x;
if(idx >= n) return;
for(int stride = blockDim.x / 2; stride > 0; stride >>= 1){
if(tid < stride)
idata[tid] += idata[tid + stride];
__syncthreads();
}
if(tid == 0) g_odata[blockIdx.x] = idata[0];
}
__global__ void reduceUnrolling2(int *g_idata, int *g_odata, unsigned int n){
unsigned int tid = threadIdx.x;
unsigned int idx = (2 * blockIdx.x) * blockDim.x + threadIdx.x;
int *idata = g_idata + (2 * blockIdx.x) * blockDim.x;
if(idx + blockDim.x < n) g_idata[idx] += g_idata[idx + blockDim.x];
__syncthreads();
for(int stride = blockDim.x / 2; stride > 0; stride >>= 1){
if(tid < stride)
idata[tid] += idata[tid + stride];
__syncthreads();
}
if(tid == 0) g_odata[blockIdx.x] = idata[0];
}
__global__ void reduceUnrolling4(int *g_idata, int *g_odata, unsigned int n){
unsigned int tid = threadIdx.x;
unsigned int idx = (4 * blockIdx.x) * blockDim.x + threadIdx.x;
int *idata = g_idata + (4 * blockIdx.x) * blockDim.x;
if(idx + 3 * blockDim.x < n){
g_idata[idx] += g_idata[idx + blockDim.x];
g_idata[idx] += g_idata[idx + 2 * blockDim.x];
g_idata[idx] += g_idata[idx + 3 * blockDim.x];
}
__syncthreads();
for(int stride = blockDim.x / 2; stride > 0; stride >>= 1){
if(tid < stride)
idata[tid] += idata[tid + stride];
__syncthreads();
}
if(tid == 0) g_odata[blockIdx.x] = idata[0];
}
__global__ void reduceUnrolling8(int *g_idata, int *g_odata, unsigned int n){
unsigned int tid = threadIdx.x;
unsigned int idx = (8 * blockIdx.x) * blockDim.x + threadIdx.x;
int *idata = g_idata + (8 * blockIdx.x) * blockDim.x;
if(idx + 7 * blockDim.x < n){
g_idata[idx] += g_idata[idx + blockDim.x];
g_idata[idx] += g_idata[idx + 2 * blockDim.x];
g_idata[idx] += g_idata[idx + 3 * blockDim.x];
g_idata[idx] += g_idata[idx + 4 * blockDim.x];
g_idata[idx] += g_idata[idx + 5 * blockDim.x];
g_idata[idx] += g_idata[idx + 6 * blockDim.x];
g_idata[idx] += g_idata[idx + 7 * blockDim.x];
}
__syncthreads();
for(int stride = blockDim.x / 2; stride > 0; stride >>= 1){
if(tid < stride)
idata[tid] += idata[tid + stride];
__syncthreads();
}
if(tid == 0) g_odata[blockIdx.x] = idata[0];
}
__global__ void reduceUnrollWarps8(int *g_idata, int *g_odata, unsigned int n){
unsigned int tid = threadIdx.x;
unsigned int idx = (8 * blockIdx.x) * blockDim.x + threadIdx.x;
int *idata = g_idata + (8 * blockIdx.x) * blockDim.x;
if(idx + 7 * blockDim.x < n){
g_idata[idx] += g_idata[idx + blockDim.x];
g_idata[idx] += g_idata[idx + 2 * blockDim.x];
g_idata[idx] += g_idata[idx + 3 * blockDim.x];
g_idata[idx] += g_idata[idx + 4 * blockDim.x];
g_idata[idx] += g_idata[idx + 5 * blockDim.x];
g_idata[idx] += g_idata[idx + 6 * blockDim.x];
g_idata[idx] += g_idata[idx + 7 * blockDim.x];
}
__syncthreads();
for(int stride = blockDim.x / 2; stride > 32; stride >>= 1){
if(tid < stride)
idata[tid] += idata[tid + stride];
__syncthreads();
}
if(tid < 32){
volatile int *vmem = idata;
vmem[tid] += vmem[tid + 32];
vmem[tid] += vmem[tid + 16];
vmem[tid] += vmem[tid + 8];
vmem[tid] += vmem[tid + 4];
vmem[tid] += vmem[tid + 2];
vmem[tid] += vmem[tid + 1];
}
if(tid == 0) g_odata[blockIdx.x] = idata[0];
}
__global__ void reduceCompleteUnrollWarps8(int *g_idata, int *g_odata, unsigned int n){
unsigned int tid = threadIdx.x;
unsigned int idx = (8 * blockIdx.x) * blockDim.x + threadIdx.x;
int *idata = g_idata + (8 * blockIdx.x) * blockDim.x;
if(idx + 7 * blockDim.x < n){
g_idata[idx] += g_idata[idx + blockDim.x];
g_idata[idx] += g_idata[idx + 2 * blockDim.x];
g_idata[idx] += g_idata[idx + 3 * blockDim.x];
g_idata[idx] += g_idata[idx + 4 * blockDim.x];
g_idata[idx] += g_idata[idx + 5 * blockDim.x];
g_idata[idx] += g_idata[idx + 6 * blockDim.x];
g_idata[idx] += g_idata[idx + 7 * blockDim.x];
}
__syncthreads();
if(blockDim.x >= 1024 && tid < 512)
idata[tid] += idata[tid + 512];
__syncthreads();
if(blockDim.x >= 512 && tid < 256)
idata[tid] += idata[tid + 256];
__syncthreads();
if(blockDim.x >= 256 && tid < 128)
idata[tid] += idata[tid + 128];
__syncthreads();
if(blockDim.x >= 128 && tid < 64)
idata[idx] += idata[tid + 64];
__syncthreads();
if(tid < 32){
volatile int *vmem = idata;
vmem[tid] += vmem[tid + 32];
vmem[tid] += vmem[tid + 16];
vmem[tid] += vmem[tid + 8];
vmem[tid] += vmem[tid + 4];
vmem[tid] += vmem[tid + 2];
vmem[tid] += vmem[tid + 1];
}
if(tid == 0) g_odata[blockIdx.x] = idata[0];
}
template <unsigned int iBlockSize>
__global__ void reduceCompleteUnroll(int *g_idata, int *g_odata, unsigned int n){
unsigned int tid = threadIdx.x;
unsigned int idx = (8 * blockIdx.x) * blockDim.x + threadIdx.x;
int *idata = g_idata + (8 * blockIdx.x) * blockDim.x;
if(idx + 7 * blockDim.x < n){
g_idata[idx] += g_idata[idx + blockDim.x];
g_idata[idx] += g_idata[idx + 2 * blockDim.x];
g_idata[idx] += g_idata[idx + 3 * blockDim.x];
g_idata[idx] += g_idata[idx + 4 * blockDim.x];
g_idata[idx] += g_idata[idx + 5 * blockDim.x];
g_idata[idx] += g_idata[idx + 6 * blockDim.x];
g_idata[idx] += g_idata[idx + 7 * blockDim.x];
}
__syncthreads();
if(iBlockSize >= 1024 && tid < 512)
idata[tid] += idata[tid + 512];
__syncthreads();
if(iBlockSize >= 512 && tid < 256)
idata[tid] += idata[tid + 256];
__syncthreads();
if(iBlockSize >= 256 && tid < 128)
idata[tid] += idata[tid + 128];
__syncthreads();
if(iBlockSize >= 128 && tid < 64)
idata[idx] += idata[tid + 64];
__syncthreads();
if(tid < 32){
volatile int *vmem = idata;
vmem[tid] += vmem[tid + 32];
vmem[tid] += vmem[tid + 16];
vmem[tid] += vmem[tid + 8];
vmem[tid] += vmem[tid + 4];
vmem[tid] += vmem[tid + 2];
vmem[tid] += vmem[tid + 1];
}
if(tid == 0) g_odata[blockIdx.x] = idata[0];
}
double seconds(){
struct timeval tp;
gettimeofday(&tp, NULL);
return ((double)tp.tv_sec + (double)tp.tv_usec * 1e-6) * 1e+3;
}
int main(int argc, char **argv){
int dev = 0;
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, dev);
cout << "Starting reduction at " << argv[0] << " ";
cout << "device " << dev << ": " << deviceProp.name << " ";
cudaSetDevice(dev);
bool bResult = false;
int size = 1 << 24;
cout << " with array size " << size << " ";
int blocksize = 512;
if(argc > 1)
blocksize = atoi(argv[1]);
dim3 block (blocksize, 1);
dim3 grid ((size + block.x - 1) / block.x, 1);
cout << "grid " << grid.x << " block " << block.x << endl;
size_t nBytes = size * sizeof(int);
int *h_idata = (int *)malloc(nBytes);
int *h_odata = (int *)malloc(grid.x * sizeof(int));
int *tmp = (int *)malloc(nBytes);
for(int i = 0; i < size; ++ i){
h_idata[i] = (int)(rand() & 0xFF);
}
memcpy(tmp, h_idata, nBytes);
double iStart, iElaps;
int gpu_sum = 0;
int *d_idata = NULL;
cudaMalloc((void **)&d_idata, nBytes);
int *d_odata = NULL;
cudaMalloc((void **)&d_odata, grid.x * sizeof(int));
iStart = seconds();
int cpu_sum = recursiveReduce(tmp, size);
iElaps = seconds() - iStart;
cout << "cpu reduce elapsed " << iElaps << " ms cpu_sum: " << cpu_sum << endl;
cudaMemcpy(d_idata, h_idata, nBytes, cudaMemcpyHostToDevice);
cudaDeviceSynchronize();
iStart = seconds();
warmingUp<<<grid, block>>>(d_idata, d_odata, size);
cudaDeviceSynchronize();
iElaps = seconds() - iStart;
cudaMemcpy(h_odata, d_odata, grid.x * sizeof(int), cudaMemcpyDeviceToHost);
gpu_sum = 0;
for(int i = 0; i < grid.x; ++ i){
gpu_sum += h_odata[i];
}
cout << "gpu warmingUp elapsed " << iElaps << " ms gpu_sum: " << gpu_sum << " <<<grid " << grid.x << " block " << block.x << ">>>" << endl;
cudaMemcpy(d_idata, h_idata, nBytes, cudaMemcpyHostToDevice);
cudaDeviceSynchronize();
iStart = seconds();
reduceNeighbored<<<grid, block>>>(d_idata, d_odata, size);
cudaDeviceSynchronize();
iElaps = seconds() - iStart;
cudaMemcpy(h_odata, d_odata, grid.x * sizeof(int), cudaMemcpyDeviceToHost);
gpu_sum = 0;
for(int i = 0; i < grid.x; ++ i){
gpu_sum += h_odata[i];
}
cout << "gpu Neighbored elapsed " << iElaps << " ms gpu_sum: " << gpu_sum << " <<<grid " << grid.x << " block " << block.x << ">>>" << endl;
cudaMemcpy(d_idata, h_idata, nBytes, cudaMemcpyHostToDevice);
cudaDeviceSynchronize();
iStart = seconds();
reduceCompleteUnrollWarps8<<<grid.x / 8, block>>>(d_idata, d_odata, size);
cudaDeviceSynchronize();
iElaps = seconds() - iStart;
cudaMemcpy(h_odata, d_odata, grid.x * sizeof(int), cudaMemcpyDeviceToHost);
gpu_sum = 0;
for(int i = 0; i < grid.x / 8; ++ i){
gpu_sum += h_odata[i];
}
cout << "gpu nroll elapsed " << iElaps << " ms gpu_sum: " << gpu_sum << " <<<grid " << grid.x / 8 << " block " << block.x << ">>>" << endl;
free(h_idata);
free(h_odata);
free(tmp);
cudaFree(d_idata);
cudaFree(d_odata);
cudaDeviceReset();
bResult = (gpu_sum == cpu_sum);
if(!bResult) cout << "Test failed!" << endl;
return EXIT_SUCCESS;
} | //
// Created by heidies on 7/8/18.
//
#include <hip/hip_runtime.h>
#include <iostream>
#include <sys/time.h>
using namespace std;
#define CHECK(call) \
{ \
const hipError_t error = call; \
if(error != hipSuccess){ \
printf("Error: %s %d, ", __FILE__, __LINE__); \
printf("code: %d, reason %s\n", error, hipGetErrorString(error)); \
exit(1); \
} \
}
int recursiveReduce(int *data, const int size){
if(size == 1) return data[0];
int const stride = size / 2;
for(int i = 0; i < stride; i++){
data[i] += data[i + stride];
}
return recursiveReduce(data, stride);
}
__global__ void warmingUp(int *g_idata, int *g_odata, unsigned int n){
unsigned int tid = threadIdx.x;
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
int *idata = g_idata + blockIdx.x * blockDim.x;
if(idx >= n) return ;
for(int stride = 1; stride < blockDim.x; stride <<= 1){
if(tid % (2 * stride) == 0)
idata[tid] += idata[tid + stride];
__syncthreads();
}
if(tid == 0) g_odata[blockIdx.x] = idata[0];
}
__global__ void reduceNeighbored(int *g_idata, int *g_odata, unsigned int n){
unsigned int tid = threadIdx.x;
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
int *idata = g_idata + blockIdx.x * blockDim.x;
if(idx >= n) return ;
for(int stride = 1; stride < blockDim.x; stride <<= 1){
if(tid % (2 * stride) == 0)
idata[tid] += idata[tid + stride];
__syncthreads();
}
if(tid == 0) g_odata[blockIdx.x] = idata[0];
}
__global__ void reduceNeighboredLess(int *g_idata, int *g_odata, unsigned int n){
unsigned int tid = threadIdx.x;
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
int *idata = g_idata + blockIdx.x * blockDim.x;
if(idx >= n) return;
for(int stride = 1; stride < blockDim.x; stride <<= 1){
int index = 2 * stride * tid;
if(index < blockDim.x / 2)
idata[tid] += idata[tid + stride];
__syncthreads();
}
if(tid == 0) g_odata[blockIdx.x] = idata[0];
}
__global__ void reduceInterleaved(int *g_idata, int *g_odata, unsigned int n){
unsigned int tid = threadIdx.x;
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
int *idata = g_idata + blockIdx.x * blockDim.x;
if(idx >= n) return;
for(int stride = blockDim.x / 2; stride > 0; stride >>= 1){
if(tid < stride)
idata[tid] += idata[tid + stride];
__syncthreads();
}
if(tid == 0) g_odata[blockIdx.x] = idata[0];
}
__global__ void reduceUnrolling2(int *g_idata, int *g_odata, unsigned int n){
unsigned int tid = threadIdx.x;
unsigned int idx = (2 * blockIdx.x) * blockDim.x + threadIdx.x;
int *idata = g_idata + (2 * blockIdx.x) * blockDim.x;
if(idx + blockDim.x < n) g_idata[idx] += g_idata[idx + blockDim.x];
__syncthreads();
for(int stride = blockDim.x / 2; stride > 0; stride >>= 1){
if(tid < stride)
idata[tid] += idata[tid + stride];
__syncthreads();
}
if(tid == 0) g_odata[blockIdx.x] = idata[0];
}
__global__ void reduceUnrolling4(int *g_idata, int *g_odata, unsigned int n){
unsigned int tid = threadIdx.x;
unsigned int idx = (4 * blockIdx.x) * blockDim.x + threadIdx.x;
int *idata = g_idata + (4 * blockIdx.x) * blockDim.x;
if(idx + 3 * blockDim.x < n){
g_idata[idx] += g_idata[idx + blockDim.x];
g_idata[idx] += g_idata[idx + 2 * blockDim.x];
g_idata[idx] += g_idata[idx + 3 * blockDim.x];
}
__syncthreads();
for(int stride = blockDim.x / 2; stride > 0; stride >>= 1){
if(tid < stride)
idata[tid] += idata[tid + stride];
__syncthreads();
}
if(tid == 0) g_odata[blockIdx.x] = idata[0];
}
__global__ void reduceUnrolling8(int *g_idata, int *g_odata, unsigned int n){
unsigned int tid = threadIdx.x;
unsigned int idx = (8 * blockIdx.x) * blockDim.x + threadIdx.x;
int *idata = g_idata + (8 * blockIdx.x) * blockDim.x;
if(idx + 7 * blockDim.x < n){
g_idata[idx] += g_idata[idx + blockDim.x];
g_idata[idx] += g_idata[idx + 2 * blockDim.x];
g_idata[idx] += g_idata[idx + 3 * blockDim.x];
g_idata[idx] += g_idata[idx + 4 * blockDim.x];
g_idata[idx] += g_idata[idx + 5 * blockDim.x];
g_idata[idx] += g_idata[idx + 6 * blockDim.x];
g_idata[idx] += g_idata[idx + 7 * blockDim.x];
}
__syncthreads();
for(int stride = blockDim.x / 2; stride > 0; stride >>= 1){
if(tid < stride)
idata[tid] += idata[tid + stride];
__syncthreads();
}
if(tid == 0) g_odata[blockIdx.x] = idata[0];
}
__global__ void reduceUnrollWarps8(int *g_idata, int *g_odata, unsigned int n){
unsigned int tid = threadIdx.x;
unsigned int idx = (8 * blockIdx.x) * blockDim.x + threadIdx.x;
int *idata = g_idata + (8 * blockIdx.x) * blockDim.x;
if(idx + 7 * blockDim.x < n){
g_idata[idx] += g_idata[idx + blockDim.x];
g_idata[idx] += g_idata[idx + 2 * blockDim.x];
g_idata[idx] += g_idata[idx + 3 * blockDim.x];
g_idata[idx] += g_idata[idx + 4 * blockDim.x];
g_idata[idx] += g_idata[idx + 5 * blockDim.x];
g_idata[idx] += g_idata[idx + 6 * blockDim.x];
g_idata[idx] += g_idata[idx + 7 * blockDim.x];
}
__syncthreads();
for(int stride = blockDim.x / 2; stride > 32; stride >>= 1){
if(tid < stride)
idata[tid] += idata[tid + stride];
__syncthreads();
}
if(tid < 32){
volatile int *vmem = idata;
vmem[tid] += vmem[tid + 32];
vmem[tid] += vmem[tid + 16];
vmem[tid] += vmem[tid + 8];
vmem[tid] += vmem[tid + 4];
vmem[tid] += vmem[tid + 2];
vmem[tid] += vmem[tid + 1];
}
if(tid == 0) g_odata[blockIdx.x] = idata[0];
}
__global__ void reduceCompleteUnrollWarps8(int *g_idata, int *g_odata, unsigned int n){
unsigned int tid = threadIdx.x;
unsigned int idx = (8 * blockIdx.x) * blockDim.x + threadIdx.x;
int *idata = g_idata + (8 * blockIdx.x) * blockDim.x;
if(idx + 7 * blockDim.x < n){
g_idata[idx] += g_idata[idx + blockDim.x];
g_idata[idx] += g_idata[idx + 2 * blockDim.x];
g_idata[idx] += g_idata[idx + 3 * blockDim.x];
g_idata[idx] += g_idata[idx + 4 * blockDim.x];
g_idata[idx] += g_idata[idx + 5 * blockDim.x];
g_idata[idx] += g_idata[idx + 6 * blockDim.x];
g_idata[idx] += g_idata[idx + 7 * blockDim.x];
}
__syncthreads();
if(blockDim.x >= 1024 && tid < 512)
idata[tid] += idata[tid + 512];
__syncthreads();
if(blockDim.x >= 512 && tid < 256)
idata[tid] += idata[tid + 256];
__syncthreads();
if(blockDim.x >= 256 && tid < 128)
idata[tid] += idata[tid + 128];
__syncthreads();
if(blockDim.x >= 128 && tid < 64)
idata[idx] += idata[tid + 64];
__syncthreads();
if(tid < 32){
volatile int *vmem = idata;
vmem[tid] += vmem[tid + 32];
vmem[tid] += vmem[tid + 16];
vmem[tid] += vmem[tid + 8];
vmem[tid] += vmem[tid + 4];
vmem[tid] += vmem[tid + 2];
vmem[tid] += vmem[tid + 1];
}
if(tid == 0) g_odata[blockIdx.x] = idata[0];
}
template <unsigned int iBlockSize>
__global__ void reduceCompleteUnroll(int *g_idata, int *g_odata, unsigned int n){
unsigned int tid = threadIdx.x;
unsigned int idx = (8 * blockIdx.x) * blockDim.x + threadIdx.x;
int *idata = g_idata + (8 * blockIdx.x) * blockDim.x;
if(idx + 7 * blockDim.x < n){
g_idata[idx] += g_idata[idx + blockDim.x];
g_idata[idx] += g_idata[idx + 2 * blockDim.x];
g_idata[idx] += g_idata[idx + 3 * blockDim.x];
g_idata[idx] += g_idata[idx + 4 * blockDim.x];
g_idata[idx] += g_idata[idx + 5 * blockDim.x];
g_idata[idx] += g_idata[idx + 6 * blockDim.x];
g_idata[idx] += g_idata[idx + 7 * blockDim.x];
}
__syncthreads();
if(iBlockSize >= 1024 && tid < 512)
idata[tid] += idata[tid + 512];
__syncthreads();
if(iBlockSize >= 512 && tid < 256)
idata[tid] += idata[tid + 256];
__syncthreads();
if(iBlockSize >= 256 && tid < 128)
idata[tid] += idata[tid + 128];
__syncthreads();
if(iBlockSize >= 128 && tid < 64)
idata[idx] += idata[tid + 64];
__syncthreads();
if(tid < 32){
volatile int *vmem = idata;
vmem[tid] += vmem[tid + 32];
vmem[tid] += vmem[tid + 16];
vmem[tid] += vmem[tid + 8];
vmem[tid] += vmem[tid + 4];
vmem[tid] += vmem[tid + 2];
vmem[tid] += vmem[tid + 1];
}
if(tid == 0) g_odata[blockIdx.x] = idata[0];
}
double seconds(){
struct timeval tp;
gettimeofday(&tp, NULL);
return ((double)tp.tv_sec + (double)tp.tv_usec * 1e-6) * 1e+3;
}
int main(int argc, char **argv){
int dev = 0;
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, dev);
cout << "Starting reduction at " << argv[0] << " ";
cout << "device " << dev << ": " << deviceProp.name << " ";
hipSetDevice(dev);
bool bResult = false;
int size = 1 << 24;
cout << " with array size " << size << " ";
int blocksize = 512;
if(argc > 1)
blocksize = atoi(argv[1]);
dim3 block (blocksize, 1);
dim3 grid ((size + block.x - 1) / block.x, 1);
cout << "grid " << grid.x << " block " << block.x << endl;
size_t nBytes = size * sizeof(int);
int *h_idata = (int *)malloc(nBytes);
int *h_odata = (int *)malloc(grid.x * sizeof(int));
int *tmp = (int *)malloc(nBytes);
for(int i = 0; i < size; ++ i){
h_idata[i] = (int)(rand() & 0xFF);
}
memcpy(tmp, h_idata, nBytes);
double iStart, iElaps;
int gpu_sum = 0;
int *d_idata = NULL;
hipMalloc((void **)&d_idata, nBytes);
int *d_odata = NULL;
hipMalloc((void **)&d_odata, grid.x * sizeof(int));
iStart = seconds();
int cpu_sum = recursiveReduce(tmp, size);
iElaps = seconds() - iStart;
cout << "cpu reduce elapsed " << iElaps << " ms cpu_sum: " << cpu_sum << endl;
hipMemcpy(d_idata, h_idata, nBytes, hipMemcpyHostToDevice);
hipDeviceSynchronize();
iStart = seconds();
warmingUp<<<grid, block>>>(d_idata, d_odata, size);
hipDeviceSynchronize();
iElaps = seconds() - iStart;
hipMemcpy(h_odata, d_odata, grid.x * sizeof(int), hipMemcpyDeviceToHost);
gpu_sum = 0;
for(int i = 0; i < grid.x; ++ i){
gpu_sum += h_odata[i];
}
cout << "gpu warmingUp elapsed " << iElaps << " ms gpu_sum: " << gpu_sum << " <<<grid " << grid.x << " block " << block.x << ">>>" << endl;
hipMemcpy(d_idata, h_idata, nBytes, hipMemcpyHostToDevice);
hipDeviceSynchronize();
iStart = seconds();
reduceNeighbored<<<grid, block>>>(d_idata, d_odata, size);
hipDeviceSynchronize();
iElaps = seconds() - iStart;
hipMemcpy(h_odata, d_odata, grid.x * sizeof(int), hipMemcpyDeviceToHost);
gpu_sum = 0;
for(int i = 0; i < grid.x; ++ i){
gpu_sum += h_odata[i];
}
cout << "gpu Neighbored elapsed " << iElaps << " ms gpu_sum: " << gpu_sum << " <<<grid " << grid.x << " block " << block.x << ">>>" << endl;
hipMemcpy(d_idata, h_idata, nBytes, hipMemcpyHostToDevice);
hipDeviceSynchronize();
iStart = seconds();
reduceCompleteUnrollWarps8<<<grid.x / 8, block>>>(d_idata, d_odata, size);
hipDeviceSynchronize();
iElaps = seconds() - iStart;
hipMemcpy(h_odata, d_odata, grid.x * sizeof(int), hipMemcpyDeviceToHost);
gpu_sum = 0;
for(int i = 0; i < grid.x / 8; ++ i){
gpu_sum += h_odata[i];
}
cout << "gpu nroll elapsed " << iElaps << " ms gpu_sum: " << gpu_sum << " <<<grid " << grid.x / 8 << " block " << block.x << ">>>" << endl;
free(h_idata);
free(h_odata);
free(tmp);
hipFree(d_idata);
hipFree(d_odata);
hipDeviceReset();
bResult = (gpu_sum == cpu_sum);
if(!bResult) cout << "Test failed!" << endl;
return EXIT_SUCCESS;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | ////////////////////////////////////////////////////////////////////////////////
//
// FILE: burrows_wheeler_encoder.cu
// DESCRIPTION: uses bitonic sort to encode a string with BWT
// AUTHOR: Dan Fabian
// DATE: 4/5/2020
#include <iostream>
#include <stdio.h>
using std::cout; using std::endl;
// constants, MUST BE A POWER OF 2 IN LENGTH
const int SIZE = 8;
const char STRING[] = "^BANANA|";
// kernal func prototype
__global__ void bitonic_sort(char *string, int *indices);
////////////////////////////////////////////////////////////////////////////////
//
// MAIN
int main()
{
// create array of vals
char *string_d;
int *indices = new int[SIZE], *indices_d;
// copy string to device memory and allocate mem
int stringMem = sizeof(char) * SIZE, indexMem = sizeof(int) * SIZE;
cudaMalloc((void**)&string_d, stringMem);
cudaMalloc((void**)&indices_d, indexMem);
cudaMemcpy(string_d, STRING, stringMem, cudaMemcpyHostToDevice);
cudaMemcpy(indices_d, indices, indexMem, cudaMemcpyHostToDevice);
// sort
bitonic_sort<<<1, SIZE>>>(string_d, indices_d);
// copy device memory back to host
cudaMemcpy(indices, indices_d, indexMem, cudaMemcpyDeviceToHost);
// print out encoded string
for (int i = 0; i < SIZE; ++i)
if (indices[i] != 0)
cout << STRING[indices[i] - 1] << ' ';
else
cout << STRING[SIZE - 1] << ' ';
cout << endl;
// free all device memory
cudaFree(indices_d); cudaFree(string_d);
cudaDeviceSynchronize();
}
////////////////////////////////////////////////////////////////////////////////
//
// KERNEL function
////////////////////////////////////////
// compare strings
__device__ bool lessThan(char *string, const int& pos1, const int& pos2, const int &size)
{
int i = 0;
while (string[(pos1 + i) % size] == string[(pos2 + i) % size] && i < size) ++i;
if (i == size) return false;
return string[(pos1 + i) % size] < string[(pos2 + i) % size];
}
////////////////////////////////////////
// gpu sort func
__global__ void bitonic_sort(char *string, int *indices)
{
const int size = SIZE;
// create shared arrays
static __shared__ char string_s[size]; // holds original string
static __shared__ int indices_s[size]; // holds char indices of sorted array
// thread idx
int idx = threadIdx.x;
// load 1 elem in each array per index
string_s[idx] = string[idx];
indices_s[idx] = idx;
// bitonic sort alg
int tmp, elemIdx1, elemIdx2, strIdx1, strIdx2;
bool max; // if max then put max elem in higher index
for (int i = 2; i <= size; i *= 2)
{
// bitonic merge of size i
max = (idx % i) < (i / 2);
for (int j = i / 2; j > 0; j /= 2)
{
// get element indices to compare
elemIdx1 = (idx / j) * (j * 2) + idx % j;
elemIdx2 = elemIdx1 + j;
strIdx1 = indices_s[elemIdx1];
strIdx2 = indices_s[elemIdx2];
// check if swap is needed
if ((elemIdx2 < size) &&
((max && lessThan(string_s, strIdx2, strIdx1, size)) ||
(!max && lessThan(string_s, strIdx1, strIdx2, size))))
{
// swap indices
tmp = indices_s[elemIdx1];
indices_s[elemIdx1] = indices_s[elemIdx2];
indices_s[elemIdx2] = tmp;
}
// need to sync before next step
__syncthreads();
}
}
// transfer memory to global
indices[idx] = indices_s[idx];
} | .file "tmpxft_000011e1_00000000-6_burrows_wheeler_encoder.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8lessThanPcRKiS1_S1_
.type _Z8lessThanPcRKiS1_S1_, @function
_Z8lessThanPcRKiS1_S1_:
.LFB3670:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3670:
.size _Z8lessThanPcRKiS1_S1_, .-_Z8lessThanPcRKiS1_S1_
.globl _Z34__device_stub__Z12bitonic_sortPcPiPcPi
.type _Z34__device_stub__Z12bitonic_sortPcPiPcPi, @function
_Z34__device_stub__Z12bitonic_sortPcPiPcPi:
.LFB3695:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12bitonic_sortPcPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z34__device_stub__Z12bitonic_sortPcPiPcPi, .-_Z34__device_stub__Z12bitonic_sortPcPiPcPi
.globl _Z12bitonic_sortPcPi
.type _Z12bitonic_sortPcPi, @function
_Z12bitonic_sortPcPi:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z12bitonic_sortPcPiPcPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z12bitonic_sortPcPi, .-_Z12bitonic_sortPcPi
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $32, %edi
call _Znam@PLT
movq %rax, %r12
movq %rsp, %rdi
movl $8, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8, %edx
leaq _ZL6STRING(%rip), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $32, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $8, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L14:
movl $2, %ecx
movl $32, %edx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq %r12, %rbx
addq $32, %r12
leaq _ZSt4cout(%rip), %rbp
leaq 28(%rsp), %r13
leaq _ZL6STRING(%rip), %r14
jmp .L25
.L29:
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z34__device_stub__Z12bitonic_sortPcPiPcPi
jmp .L14
.L16:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rbp, %rdi
jmp .L17
.L18:
movl $32, %esi
call _ZNSo3putEc@PLT
.L20:
addq $4, %rbx
cmpq %r12, %rbx
je .L30
.L25:
movl (%rbx), %eax
testl %eax, %eax
je .L15
subl $1, %eax
cltq
movzbl (%r14,%rax), %esi
movb %sil, 28(%rsp)
movq 0(%rbp), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rbp,%rax)
je .L16
movl $1, %edx
movq %r13, %rsi
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rdi
.L17:
movb $32, 28(%rsp)
movq (%rdi), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L18
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L20
.L15:
movb $124, 28(%rsp)
movq 0(%rbp), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rbp,%rax)
je .L21
movl $1, %edx
movq %r13, %rsi
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rdi
.L22:
movb $32, 28(%rsp)
movq (%rdi), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L23
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L20
.L21:
movl $124, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rbp, %rdi
jmp .L22
.L23:
movl $32, %esi
call _ZNSo3putEc@PLT
jmp .L20
.L30:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq (%rsp), %rdi
call cudaFree@PLT
call cudaDeviceSynchronize@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12bitonic_sortPcPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12bitonic_sortPcPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata
.align 8
.type _ZL6STRING, @object
.size _ZL6STRING, 9
_ZL6STRING:
.string "^BANANA|"
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | ////////////////////////////////////////////////////////////////////////////////
//
// FILE: burrows_wheeler_encoder.cu
// DESCRIPTION: uses bitonic sort to encode a string with BWT
// AUTHOR: Dan Fabian
// DATE: 4/5/2020
#include <iostream>
#include <stdio.h>
using std::cout; using std::endl;
// constants, MUST BE A POWER OF 2 IN LENGTH
const int SIZE = 8;
const char STRING[] = "^BANANA|";
// kernal func prototype
__global__ void bitonic_sort(char *string, int *indices);
////////////////////////////////////////////////////////////////////////////////
//
// MAIN
int main()
{
// create array of vals
char *string_d;
int *indices = new int[SIZE], *indices_d;
// copy string to device memory and allocate mem
int stringMem = sizeof(char) * SIZE, indexMem = sizeof(int) * SIZE;
cudaMalloc((void**)&string_d, stringMem);
cudaMalloc((void**)&indices_d, indexMem);
cudaMemcpy(string_d, STRING, stringMem, cudaMemcpyHostToDevice);
cudaMemcpy(indices_d, indices, indexMem, cudaMemcpyHostToDevice);
// sort
bitonic_sort<<<1, SIZE>>>(string_d, indices_d);
// copy device memory back to host
cudaMemcpy(indices, indices_d, indexMem, cudaMemcpyDeviceToHost);
// print out encoded string
for (int i = 0; i < SIZE; ++i)
if (indices[i] != 0)
cout << STRING[indices[i] - 1] << ' ';
else
cout << STRING[SIZE - 1] << ' ';
cout << endl;
// free all device memory
cudaFree(indices_d); cudaFree(string_d);
cudaDeviceSynchronize();
}
////////////////////////////////////////////////////////////////////////////////
//
// KERNEL function
////////////////////////////////////////
// compare strings
__device__ bool lessThan(char *string, const int& pos1, const int& pos2, const int &size)
{
int i = 0;
while (string[(pos1 + i) % size] == string[(pos2 + i) % size] && i < size) ++i;
if (i == size) return false;
return string[(pos1 + i) % size] < string[(pos2 + i) % size];
}
////////////////////////////////////////
// gpu sort func
__global__ void bitonic_sort(char *string, int *indices)
{
const int size = SIZE;
// create shared arrays
static __shared__ char string_s[size]; // holds original string
static __shared__ int indices_s[size]; // holds char indices of sorted array
// thread idx
int idx = threadIdx.x;
// load 1 elem in each array per index
string_s[idx] = string[idx];
indices_s[idx] = idx;
// bitonic sort alg
int tmp, elemIdx1, elemIdx2, strIdx1, strIdx2;
bool max; // if max then put max elem in higher index
for (int i = 2; i <= size; i *= 2)
{
// bitonic merge of size i
max = (idx % i) < (i / 2);
for (int j = i / 2; j > 0; j /= 2)
{
// get element indices to compare
elemIdx1 = (idx / j) * (j * 2) + idx % j;
elemIdx2 = elemIdx1 + j;
strIdx1 = indices_s[elemIdx1];
strIdx2 = indices_s[elemIdx2];
// check if swap is needed
if ((elemIdx2 < size) &&
((max && lessThan(string_s, strIdx2, strIdx1, size)) ||
(!max && lessThan(string_s, strIdx1, strIdx2, size))))
{
// swap indices
tmp = indices_s[elemIdx1];
indices_s[elemIdx1] = indices_s[elemIdx2];
indices_s[elemIdx2] = tmp;
}
// need to sync before next step
__syncthreads();
}
}
// transfer memory to global
indices[idx] = indices_s[idx];
} | ////////////////////////////////////////////////////////////////////////////////
//
// FILE: burrows_wheeler_encoder.cu
// DESCRIPTION: uses bitonic sort to encode a string with BWT
// AUTHOR: Dan Fabian
// DATE: 4/5/2020
#include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
using std::cout; using std::endl;
// constants, MUST BE A POWER OF 2 IN LENGTH
const int SIZE = 8;
const char STRING[] = "^BANANA|";
// kernal func prototype
__global__ void bitonic_sort(char *string, int *indices);
////////////////////////////////////////////////////////////////////////////////
//
// MAIN
int main()
{
// create array of vals
char *string_d;
int *indices = new int[SIZE], *indices_d;
// copy string to device memory and allocate mem
int stringMem = sizeof(char) * SIZE, indexMem = sizeof(int) * SIZE;
hipMalloc((void**)&string_d, stringMem);
hipMalloc((void**)&indices_d, indexMem);
hipMemcpy(string_d, STRING, stringMem, hipMemcpyHostToDevice);
hipMemcpy(indices_d, indices, indexMem, hipMemcpyHostToDevice);
// sort
bitonic_sort<<<1, SIZE>>>(string_d, indices_d);
// copy device memory back to host
hipMemcpy(indices, indices_d, indexMem, hipMemcpyDeviceToHost);
// print out encoded string
for (int i = 0; i < SIZE; ++i)
if (indices[i] != 0)
cout << STRING[indices[i] - 1] << ' ';
else
cout << STRING[SIZE - 1] << ' ';
cout << endl;
// free all device memory
hipFree(indices_d); hipFree(string_d);
hipDeviceSynchronize();
}
////////////////////////////////////////////////////////////////////////////////
//
// KERNEL function
////////////////////////////////////////
// compare strings
__device__ bool lessThan(char *string, const int& pos1, const int& pos2, const int &size)
{
int i = 0;
while (string[(pos1 + i) % size] == string[(pos2 + i) % size] && i < size) ++i;
if (i == size) return false;
return string[(pos1 + i) % size] < string[(pos2 + i) % size];
}
////////////////////////////////////////
// gpu sort func
__global__ void bitonic_sort(char *string, int *indices)
{
const int size = SIZE;
// create shared arrays
static __shared__ char string_s[size]; // holds original string
static __shared__ int indices_s[size]; // holds char indices of sorted array
// thread idx
int idx = threadIdx.x;
// load 1 elem in each array per index
string_s[idx] = string[idx];
indices_s[idx] = idx;
// bitonic sort alg
int tmp, elemIdx1, elemIdx2, strIdx1, strIdx2;
bool max; // if max then put max elem in higher index
for (int i = 2; i <= size; i *= 2)
{
// bitonic merge of size i
max = (idx % i) < (i / 2);
for (int j = i / 2; j > 0; j /= 2)
{
// get element indices to compare
elemIdx1 = (idx / j) * (j * 2) + idx % j;
elemIdx2 = elemIdx1 + j;
strIdx1 = indices_s[elemIdx1];
strIdx2 = indices_s[elemIdx2];
// check if swap is needed
if ((elemIdx2 < size) &&
((max && lessThan(string_s, strIdx2, strIdx1, size)) ||
(!max && lessThan(string_s, strIdx1, strIdx2, size))))
{
// swap indices
tmp = indices_s[elemIdx1];
indices_s[elemIdx1] = indices_s[elemIdx2];
indices_s[elemIdx2] = tmp;
}
// need to sync before next step
__syncthreads();
}
}
// transfer memory to global
indices[idx] = indices_s[idx];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | ////////////////////////////////////////////////////////////////////////////////
//
// FILE: burrows_wheeler_encoder.cu
// DESCRIPTION: uses bitonic sort to encode a string with BWT
// AUTHOR: Dan Fabian
// DATE: 4/5/2020
#include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
using std::cout; using std::endl;
// constants, MUST BE A POWER OF 2 IN LENGTH
const int SIZE = 8;
const char STRING[] = "^BANANA|";
// kernal func prototype
__global__ void bitonic_sort(char *string, int *indices);
////////////////////////////////////////////////////////////////////////////////
//
// MAIN
int main()
{
// create array of vals
char *string_d;
int *indices = new int[SIZE], *indices_d;
// copy string to device memory and allocate mem
int stringMem = sizeof(char) * SIZE, indexMem = sizeof(int) * SIZE;
hipMalloc((void**)&string_d, stringMem);
hipMalloc((void**)&indices_d, indexMem);
hipMemcpy(string_d, STRING, stringMem, hipMemcpyHostToDevice);
hipMemcpy(indices_d, indices, indexMem, hipMemcpyHostToDevice);
// sort
bitonic_sort<<<1, SIZE>>>(string_d, indices_d);
// copy device memory back to host
hipMemcpy(indices, indices_d, indexMem, hipMemcpyDeviceToHost);
// print out encoded string
for (int i = 0; i < SIZE; ++i)
if (indices[i] != 0)
cout << STRING[indices[i] - 1] << ' ';
else
cout << STRING[SIZE - 1] << ' ';
cout << endl;
// free all device memory
hipFree(indices_d); hipFree(string_d);
hipDeviceSynchronize();
}
////////////////////////////////////////////////////////////////////////////////
//
// KERNEL function
////////////////////////////////////////
// compare strings
__device__ bool lessThan(char *string, const int& pos1, const int& pos2, const int &size)
{
int i = 0;
while (string[(pos1 + i) % size] == string[(pos2 + i) % size] && i < size) ++i;
if (i == size) return false;
return string[(pos1 + i) % size] < string[(pos2 + i) % size];
}
////////////////////////////////////////
// gpu sort func
__global__ void bitonic_sort(char *string, int *indices)
{
const int size = SIZE;
// create shared arrays
static __shared__ char string_s[size]; // holds original string
static __shared__ int indices_s[size]; // holds char indices of sorted array
// thread idx
int idx = threadIdx.x;
// load 1 elem in each array per index
string_s[idx] = string[idx];
indices_s[idx] = idx;
// bitonic sort alg
int tmp, elemIdx1, elemIdx2, strIdx1, strIdx2;
bool max; // if max then put max elem in higher index
for (int i = 2; i <= size; i *= 2)
{
// bitonic merge of size i
max = (idx % i) < (i / 2);
for (int j = i / 2; j > 0; j /= 2)
{
// get element indices to compare
elemIdx1 = (idx / j) * (j * 2) + idx % j;
elemIdx2 = elemIdx1 + j;
strIdx1 = indices_s[elemIdx1];
strIdx2 = indices_s[elemIdx2];
// check if swap is needed
if ((elemIdx2 < size) &&
((max && lessThan(string_s, strIdx2, strIdx1, size)) ||
(!max && lessThan(string_s, strIdx1, strIdx2, size))))
{
// swap indices
tmp = indices_s[elemIdx1];
indices_s[elemIdx1] = indices_s[elemIdx2];
indices_s[elemIdx2] = tmp;
}
// need to sync before next step
__syncthreads();
}
}
// transfer memory to global
indices[idx] = indices_s[idx];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12bitonic_sortPcPi
.globl _Z12bitonic_sortPcPi
.p2align 8
.type _Z12bitonic_sortPcPi,@function
_Z12bitonic_sortPcPi:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
s_mov_b32 s4, 2
s_waitcnt lgkmcnt(0)
global_load_u8 v2, v0, s[2:3]
s_waitcnt vmcnt(0)
ds_store_b8 v0, v2 offset:32
ds_store_b32 v1, v0
s_branch .LBB0_2
.LBB0_1:
s_lshl_b32 s2, s4, 1
s_cmp_gt_u32 s4, 4
s_mov_b32 s4, s2
s_cbranch_scc1 .LBB0_15
.LBB0_2:
s_add_i32 s2, s4, -1
s_lshr_b32 s5, s4, 1
v_and_b32_e32 v2, s2, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_le_u32_e32 vcc_lo, s5, v2
s_branch .LBB0_4
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s6
s_lshr_b32 s2, s5, 1
s_cmp_lt_u32 s5, 2
s_mov_b32 s5, s2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_1
.LBB0_4:
v_cvt_f32_u32_e32 v2, s5
s_sub_i32 s2, 0, s5
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s2, v2
v_mul_hi_u32 v3, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v3
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, v2, s5
v_add_nc_u32_e32 v4, 1, v2
v_sub_nc_u32_e32 v3, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v5, s5, v3
v_cmp_le_u32_e64 s2, s5, v3
v_cndmask_b32_e64 v2, v2, v4, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v3, v5, s2
v_add_nc_u32_e32 v4, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_u32_e64 s2, s5, v3
v_cndmask_b32_e64 v2, v2, v4, s2
s_add_i32 s2, s5, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v3, s2, v0
v_mul_lo_u32 v2, s5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 1, v3
v_add_nc_u32_e32 v3, s5, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e32 8, v3
s_cbranch_execz .LBB0_3
v_lshlrev_b32_e32 v2, 2, v2
v_lshlrev_b32_e32 v3, 2, v3
s_mov_b32 s7, 0
ds_load_b32 v4, v2
ds_load_b32 v5, v3
s_and_saveexec_b32 s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s8, exec_lo, s2
s_cbranch_execz .LBB0_9
s_mov_b32 s3, 0
.p2align 6
.LBB0_7:
s_waitcnt lgkmcnt(1)
v_add_nc_u32_e32 v6, s7, v4
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v7, s7, v5
s_cmp_gt_u32 s7, 7
s_cselect_b32 s9, -1, 0
v_ashrrev_i32_e32 v8, 31, v6
s_add_i32 s7, s7, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v8, 29, v8
v_add_nc_u32_e32 v8, v6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v8, -8, v8
v_sub_nc_u32_e32 v6, v6, v8
v_mov_b32_e32 v8, s7
v_ashrrev_i32_e32 v9, 31, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v9, 29, v9
v_add_nc_u32_e32 v9, v7, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v9, -8, v9
v_sub_nc_u32_e32 v7, v7, v9
ds_load_u8 v6, v6 offset:32
ds_load_u8 v7, v7 offset:32
s_waitcnt lgkmcnt(0)
v_cmp_ne_u16_e64 s2, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, s9, s2
s_and_b32 s2, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s3, s2, s3
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_7
s_or_b32 exec_lo, exec_lo, s3
v_bfe_i32 v7, v7, 0, 8
v_bfe_i32 v6, v6, 0, 8
v_cmp_ne_u32_e64 s2, 9, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_i16_e64 s3, v6, v7
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s7, s2, exec_lo
.LBB0_9:
s_and_not1_saveexec_b32 s8, s8
s_cbranch_execz .LBB0_13
s_mov_b32 s3, 0
s_mov_b32 s9, 0
.p2align 6
.LBB0_11:
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v6, s9, v5
v_add_nc_u32_e32 v7, s9, v4
s_cmp_gt_u32 s9, 7
s_cselect_b32 s10, -1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v6
s_add_i32 s9, s9, 1
v_lshrrev_b32_e32 v8, 29, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v8, v6, v8
v_and_b32_e32 v8, -8, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v6, v6, v8
v_mov_b32_e32 v8, s9
v_ashrrev_i32_e32 v9, 31, v7
v_lshrrev_b32_e32 v9, 29, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v9, v7, v9
v_and_b32_e32 v9, -8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v7, v7, v9
ds_load_u8 v6, v6 offset:32
ds_load_u8 v7, v7 offset:32
s_waitcnt lgkmcnt(0)
v_cmp_ne_u16_e64 s2, v6, v7
s_or_b32 s2, s10, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, exec_lo, s2
s_or_b32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_11
s_or_b32 exec_lo, exec_lo, s3
v_bfe_i32 v7, v7, 0, 8
v_bfe_i32 v6, v6, 0, 8
v_cmp_ne_u32_e64 s2, 9, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_i16_e64 s3, v6, v7
s_and_b32 s2, s2, s3
s_and_not1_b32 s3, s7, exec_lo
s_and_b32 s2, s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s7, s3, s2
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s7
s_cbranch_execz .LBB0_3
s_waitcnt lgkmcnt(0)
ds_store_b32 v2, v5
ds_store_b32 v3, v4
s_branch .LBB0_3
.LBB0_15:
s_load_b64 s[0:1], s[0:1], 0x8
ds_load_b32 v1, v1
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12bitonic_sortPcPi
.amdhsa_group_segment_fixed_size 40
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 11
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12bitonic_sortPcPi, .Lfunc_end0-_Z12bitonic_sortPcPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 40
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12bitonic_sortPcPi
.private_segment_fixed_size: 0
.sgpr_count: 13
.sgpr_spill_count: 0
.symbol: _Z12bitonic_sortPcPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | ////////////////////////////////////////////////////////////////////////////////
//
// FILE: burrows_wheeler_encoder.cu
// DESCRIPTION: uses bitonic sort to encode a string with BWT
// AUTHOR: Dan Fabian
// DATE: 4/5/2020
#include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
using std::cout; using std::endl;
// constants, MUST BE A POWER OF 2 IN LENGTH
const int SIZE = 8;
const char STRING[] = "^BANANA|";
// kernal func prototype
__global__ void bitonic_sort(char *string, int *indices);
////////////////////////////////////////////////////////////////////////////////
//
// MAIN
int main()
{
// create array of vals
char *string_d;
int *indices = new int[SIZE], *indices_d;
// copy string to device memory and allocate mem
int stringMem = sizeof(char) * SIZE, indexMem = sizeof(int) * SIZE;
hipMalloc((void**)&string_d, stringMem);
hipMalloc((void**)&indices_d, indexMem);
hipMemcpy(string_d, STRING, stringMem, hipMemcpyHostToDevice);
hipMemcpy(indices_d, indices, indexMem, hipMemcpyHostToDevice);
// sort
bitonic_sort<<<1, SIZE>>>(string_d, indices_d);
// copy device memory back to host
hipMemcpy(indices, indices_d, indexMem, hipMemcpyDeviceToHost);
// print out encoded string
for (int i = 0; i < SIZE; ++i)
if (indices[i] != 0)
cout << STRING[indices[i] - 1] << ' ';
else
cout << STRING[SIZE - 1] << ' ';
cout << endl;
// free all device memory
hipFree(indices_d); hipFree(string_d);
hipDeviceSynchronize();
}
////////////////////////////////////////////////////////////////////////////////
//
// KERNEL function
////////////////////////////////////////
// compare strings
__device__ bool lessThan(char *string, const int& pos1, const int& pos2, const int &size)
{
int i = 0;
while (string[(pos1 + i) % size] == string[(pos2 + i) % size] && i < size) ++i;
if (i == size) return false;
return string[(pos1 + i) % size] < string[(pos2 + i) % size];
}
////////////////////////////////////////
// gpu sort func
__global__ void bitonic_sort(char *string, int *indices)
{
const int size = SIZE;
// create shared arrays
static __shared__ char string_s[size]; // holds original string
static __shared__ int indices_s[size]; // holds char indices of sorted array
// thread idx
int idx = threadIdx.x;
// load 1 elem in each array per index
string_s[idx] = string[idx];
indices_s[idx] = idx;
// bitonic sort alg
int tmp, elemIdx1, elemIdx2, strIdx1, strIdx2;
bool max; // if max then put max elem in higher index
for (int i = 2; i <= size; i *= 2)
{
// bitonic merge of size i
max = (idx % i) < (i / 2);
for (int j = i / 2; j > 0; j /= 2)
{
// get element indices to compare
elemIdx1 = (idx / j) * (j * 2) + idx % j;
elemIdx2 = elemIdx1 + j;
strIdx1 = indices_s[elemIdx1];
strIdx2 = indices_s[elemIdx2];
// check if swap is needed
if ((elemIdx2 < size) &&
((max && lessThan(string_s, strIdx2, strIdx1, size)) ||
(!max && lessThan(string_s, strIdx1, strIdx2, size))))
{
// swap indices
tmp = indices_s[elemIdx1];
indices_s[elemIdx1] = indices_s[elemIdx2];
indices_s[elemIdx2] = tmp;
}
// need to sync before next step
__syncthreads();
}
}
// transfer memory to global
indices[idx] = indices_s[idx];
} | .text
.file "burrows_wheeler_encoder.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $32, %edi
callq _Znam
movq %rax, %rbx
leaq 32(%rsp), %rdi
movl $8, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $32, %esi
callq hipMalloc
movq 32(%rsp), %rdi
movl $_ZL6STRING, %esi
movl $8, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $32, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 7(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq 32(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
leaq 96(%rsp), %rax
movq %rax, 16(%rsp)
leaq 88(%rsp), %rax
movq %rax, 24(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z12bitonic_sortPcPi, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
movq 8(%rsp), %rsi
movl $32, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
leaq 16(%rsp), %r14
jmp .LBB0_3
.p2align 4, 0x90
.LBB0_17: # in Loop: Header=BB0_3 Depth=1
movq %r15, %rdi
movl $32, %esi
callq _ZNSo3putEc
.LBB0_18: # in Loop: Header=BB0_3 Depth=1
incq %r12
cmpq $8, %r12
je .LBB0_6
.LBB0_3: # =>This Inner Loop Header: Depth=1
movslq (%rbx,%r12,4), %rax
testq %rax, %rax
je .LBB0_15
# %bb.4: # in Loop: Header=BB0_3 Depth=1
movzbl _ZL6STRING-1(%rax), %eax
movb %al, 16(%rsp)
movq _ZSt4cout(%rip), %rcx
movq -24(%rcx), %rcx
cmpq $0, _ZSt4cout+16(%rcx)
jne .LBB0_5
# %bb.11: # in Loop: Header=BB0_3 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %r15d
movl $_ZSt4cout, %edi
jmp .LBB0_12
.p2align 4, 0x90
.LBB0_15: # in Loop: Header=BB0_3 Depth=1
movb $124, 16(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
cmpq $0, _ZSt4cout+16(%rax)
je .LBB0_16
.LBB0_5: # in Loop: Header=BB0_3 Depth=1
movl $_ZSt4cout, %edi
movl $1, %edx
movq %r14, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rax, %r15
jmp .LBB0_13
.LBB0_16: # in Loop: Header=BB0_3 Depth=1
movl $_ZSt4cout, %r15d
movl $_ZSt4cout, %edi
movl $124, %esi
.LBB0_12: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
# in Loop: Header=BB0_3 Depth=1
callq _ZNSo3putEc
.LBB0_13: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
# in Loop: Header=BB0_3 Depth=1
movb $32, 16(%rsp)
movq (%r15), %rax
movq -24(%rax), %rax
cmpq $0, 16(%r15,%rax)
je .LBB0_17
# %bb.14: # in Loop: Header=BB0_3 Depth=1
movl $1, %edx
movq %r15, %rdi
movq %r14, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_18
.LBB0_6:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_19
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_9
# %bb.8:
movzbl 67(%rbx), %eax
jmp .LBB0_10
.LBB0_9:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
callq hipDeviceSynchronize
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_19:
.cfi_def_cfa_offset 144
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z27__device_stub__bitonic_sortPcPi # -- Begin function _Z27__device_stub__bitonic_sortPcPi
.p2align 4, 0x90
.type _Z27__device_stub__bitonic_sortPcPi,@function
_Z27__device_stub__bitonic_sortPcPi: # @_Z27__device_stub__bitonic_sortPcPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12bitonic_sortPcPi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z27__device_stub__bitonic_sortPcPi, .Lfunc_end1-_Z27__device_stub__bitonic_sortPcPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12bitonic_sortPcPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _ZL6STRING,@object # @_ZL6STRING
.section .rodata,"a",@progbits
_ZL6STRING:
.asciz "^BANANA|"
.size _ZL6STRING, 9
.type _Z12bitonic_sortPcPi,@object # @_Z12bitonic_sortPcPi
.globl _Z12bitonic_sortPcPi
.p2align 3, 0x0
_Z12bitonic_sortPcPi:
.quad _Z27__device_stub__bitonic_sortPcPi
.size _Z12bitonic_sortPcPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12bitonic_sortPcPi"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__bitonic_sortPcPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZL6STRING
.addrsig_sym _Z12bitonic_sortPcPi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000011e1_00000000-6_burrows_wheeler_encoder.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8lessThanPcRKiS1_S1_
.type _Z8lessThanPcRKiS1_S1_, @function
_Z8lessThanPcRKiS1_S1_:
.LFB3670:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3670:
.size _Z8lessThanPcRKiS1_S1_, .-_Z8lessThanPcRKiS1_S1_
.globl _Z34__device_stub__Z12bitonic_sortPcPiPcPi
.type _Z34__device_stub__Z12bitonic_sortPcPiPcPi, @function
_Z34__device_stub__Z12bitonic_sortPcPiPcPi:
.LFB3695:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12bitonic_sortPcPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z34__device_stub__Z12bitonic_sortPcPiPcPi, .-_Z34__device_stub__Z12bitonic_sortPcPiPcPi
.globl _Z12bitonic_sortPcPi
.type _Z12bitonic_sortPcPi, @function
_Z12bitonic_sortPcPi:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z12bitonic_sortPcPiPcPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z12bitonic_sortPcPi, .-_Z12bitonic_sortPcPi
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $32, %edi
call _Znam@PLT
movq %rax, %r12
movq %rsp, %rdi
movl $8, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8, %edx
leaq _ZL6STRING(%rip), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $32, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $8, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L14:
movl $2, %ecx
movl $32, %edx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq %r12, %rbx
addq $32, %r12
leaq _ZSt4cout(%rip), %rbp
leaq 28(%rsp), %r13
leaq _ZL6STRING(%rip), %r14
jmp .L25
.L29:
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z34__device_stub__Z12bitonic_sortPcPiPcPi
jmp .L14
.L16:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rbp, %rdi
jmp .L17
.L18:
movl $32, %esi
call _ZNSo3putEc@PLT
.L20:
addq $4, %rbx
cmpq %r12, %rbx
je .L30
.L25:
movl (%rbx), %eax
testl %eax, %eax
je .L15
subl $1, %eax
cltq
movzbl (%r14,%rax), %esi
movb %sil, 28(%rsp)
movq 0(%rbp), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rbp,%rax)
je .L16
movl $1, %edx
movq %r13, %rsi
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rdi
.L17:
movb $32, 28(%rsp)
movq (%rdi), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L18
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L20
.L15:
movb $124, 28(%rsp)
movq 0(%rbp), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rbp,%rax)
je .L21
movl $1, %edx
movq %r13, %rsi
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rdi
.L22:
movb $32, 28(%rsp)
movq (%rdi), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L23
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L20
.L21:
movl $124, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rbp, %rdi
jmp .L22
.L23:
movl $32, %esi
call _ZNSo3putEc@PLT
jmp .L20
.L30:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq (%rsp), %rdi
call cudaFree@PLT
call cudaDeviceSynchronize@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12bitonic_sortPcPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12bitonic_sortPcPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata
.align 8
.type _ZL6STRING, @object
.size _ZL6STRING, 9
_ZL6STRING:
.string "^BANANA|"
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "burrows_wheeler_encoder.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $32, %edi
callq _Znam
movq %rax, %rbx
leaq 32(%rsp), %rdi
movl $8, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $32, %esi
callq hipMalloc
movq 32(%rsp), %rdi
movl $_ZL6STRING, %esi
movl $8, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $32, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 7(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq 32(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
leaq 96(%rsp), %rax
movq %rax, 16(%rsp)
leaq 88(%rsp), %rax
movq %rax, 24(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z12bitonic_sortPcPi, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
movq 8(%rsp), %rsi
movl $32, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
leaq 16(%rsp), %r14
jmp .LBB0_3
.p2align 4, 0x90
.LBB0_17: # in Loop: Header=BB0_3 Depth=1
movq %r15, %rdi
movl $32, %esi
callq _ZNSo3putEc
.LBB0_18: # in Loop: Header=BB0_3 Depth=1
incq %r12
cmpq $8, %r12
je .LBB0_6
.LBB0_3: # =>This Inner Loop Header: Depth=1
movslq (%rbx,%r12,4), %rax
testq %rax, %rax
je .LBB0_15
# %bb.4: # in Loop: Header=BB0_3 Depth=1
movzbl _ZL6STRING-1(%rax), %eax
movb %al, 16(%rsp)
movq _ZSt4cout(%rip), %rcx
movq -24(%rcx), %rcx
cmpq $0, _ZSt4cout+16(%rcx)
jne .LBB0_5
# %bb.11: # in Loop: Header=BB0_3 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %r15d
movl $_ZSt4cout, %edi
jmp .LBB0_12
.p2align 4, 0x90
.LBB0_15: # in Loop: Header=BB0_3 Depth=1
movb $124, 16(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
cmpq $0, _ZSt4cout+16(%rax)
je .LBB0_16
.LBB0_5: # in Loop: Header=BB0_3 Depth=1
movl $_ZSt4cout, %edi
movl $1, %edx
movq %r14, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rax, %r15
jmp .LBB0_13
.LBB0_16: # in Loop: Header=BB0_3 Depth=1
movl $_ZSt4cout, %r15d
movl $_ZSt4cout, %edi
movl $124, %esi
.LBB0_12: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
# in Loop: Header=BB0_3 Depth=1
callq _ZNSo3putEc
.LBB0_13: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
# in Loop: Header=BB0_3 Depth=1
movb $32, 16(%rsp)
movq (%r15), %rax
movq -24(%rax), %rax
cmpq $0, 16(%r15,%rax)
je .LBB0_17
# %bb.14: # in Loop: Header=BB0_3 Depth=1
movl $1, %edx
movq %r15, %rdi
movq %r14, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_18
.LBB0_6:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_19
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_9
# %bb.8:
movzbl 67(%rbx), %eax
jmp .LBB0_10
.LBB0_9:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
callq hipDeviceSynchronize
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_19:
.cfi_def_cfa_offset 144
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z27__device_stub__bitonic_sortPcPi # -- Begin function _Z27__device_stub__bitonic_sortPcPi
.p2align 4, 0x90
.type _Z27__device_stub__bitonic_sortPcPi,@function
_Z27__device_stub__bitonic_sortPcPi: # @_Z27__device_stub__bitonic_sortPcPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12bitonic_sortPcPi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z27__device_stub__bitonic_sortPcPi, .Lfunc_end1-_Z27__device_stub__bitonic_sortPcPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12bitonic_sortPcPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _ZL6STRING,@object # @_ZL6STRING
.section .rodata,"a",@progbits
_ZL6STRING:
.asciz "^BANANA|"
.size _ZL6STRING, 9
.type _Z12bitonic_sortPcPi,@object # @_Z12bitonic_sortPcPi
.globl _Z12bitonic_sortPcPi
.p2align 3, 0x0
_Z12bitonic_sortPcPi:
.quad _Z27__device_stub__bitonic_sortPcPi
.size _Z12bitonic_sortPcPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12bitonic_sortPcPi"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__bitonic_sortPcPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZL6STRING
.addrsig_sym _Z12bitonic_sortPcPi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#define N 32
__global__ void kernel(int* input, int* output){
for(int i=0; i<N; i++)
output[i] = 2 * input[i];
}
int main(void){
int *h_input, *h_output;
int *d_input, *d_output;
h_input = (int*)malloc(N*sizeof(int));
h_output = (int*)malloc(N*sizeof(int));
cudaMalloc((void**)&d_input, N*sizeof(int));
cudaMalloc((void**)&d_output, N*sizeof(int));
for(int i=0; i<N; i++) h_input[i] = i+1;
cudaMemcpy(d_input, h_input, N*sizeof(int), cudaMemcpyHostToDevice);
kernel<<<1, 1>>> (d_input, d_output);
cudaDeviceSynchronize();
cudaMemcpy(h_output, d_output, N*sizeof(int), cudaMemcpyDeviceToHost);
for(int i=0; i<N; i++) printf("%d -> %d\n", h_input[i], h_output[i]);
free(h_input);
free(h_output);
cudaFree(d_input);
cudaFree(d_output);
return 0;
} | code for sm_80
Function : _Z6kernelPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0040*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea2000c1e1900 */
/*0050*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe200078e00ff */
/*0070*/ SHF.L.U32 R7, R0, 0x1, RZ ; /* 0x0000000100077819 */
/* 0x004fca00000006ff */
/*0080*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*0090*/ LDG.E R0, [R4.64+0x4] ; /* 0x0000040404007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ IMAD.SHL.U32 R9, R0, 0x2, RZ ; /* 0x0000000200097824 */
/* 0x004fca00078e00ff */
/*00b0*/ STG.E [R2.64+0x4], R9 ; /* 0x0000040902007986 */
/* 0x0003e8000c101904 */
/*00c0*/ LDG.E R0, [R4.64+0x8] ; /* 0x0000080404007981 */
/* 0x000ea4000c1e1900 */
/*00d0*/ SHF.L.U32 R11, R0, 0x1, RZ ; /* 0x00000001000b7819 */
/* 0x004fca00000006ff */
/*00e0*/ STG.E [R2.64+0x8], R11 ; /* 0x0000080b02007986 */
/* 0x0005e8000c101904 */
/*00f0*/ LDG.E R0, [R4.64+0xc] ; /* 0x00000c0404007981 */
/* 0x000ee4000c1e1900 */
/*0100*/ IMAD.SHL.U32 R13, R0, 0x2, RZ ; /* 0x00000002000d7824 */
/* 0x008fca00078e00ff */
/*0110*/ STG.E [R2.64+0xc], R13 ; /* 0x00000c0d02007986 */
/* 0x0007e8000c101904 */
/*0120*/ LDG.E R0, [R4.64+0x10] ; /* 0x0000100404007981 */
/* 0x000e24000c1e1900 */
/*0130*/ SHF.L.U32 R7, R0, 0x1, RZ ; /* 0x0000000100077819 */
/* 0x001fca00000006ff */
/*0140*/ STG.E [R2.64+0x10], R7 ; /* 0x0000100702007986 */
/* 0x0001e8000c101904 */
/*0150*/ LDG.E R0, [R4.64+0x14] ; /* 0x0000140404007981 */
/* 0x000e64000c1e1900 */
/*0160*/ IMAD.SHL.U32 R9, R0, 0x2, RZ ; /* 0x0000000200097824 */
/* 0x002fca00078e00ff */
/*0170*/ STG.E [R2.64+0x14], R9 ; /* 0x0000140902007986 */
/* 0x0003e8000c101904 */
/*0180*/ LDG.E R0, [R4.64+0x18] ; /* 0x0000180404007981 */
/* 0x000ea4000c1e1900 */
/*0190*/ SHF.L.U32 R11, R0, 0x1, RZ ; /* 0x00000001000b7819 */
/* 0x004fca00000006ff */
/*01a0*/ STG.E [R2.64+0x18], R11 ; /* 0x0000180b02007986 */
/* 0x0005e8000c101904 */
/*01b0*/ LDG.E R0, [R4.64+0x1c] ; /* 0x00001c0404007981 */
/* 0x000ee4000c1e1900 */
/*01c0*/ IMAD.SHL.U32 R13, R0, 0x2, RZ ; /* 0x00000002000d7824 */
/* 0x008fca00078e00ff */
/*01d0*/ STG.E [R2.64+0x1c], R13 ; /* 0x00001c0d02007986 */
/* 0x0007e8000c101904 */
/*01e0*/ LDG.E R0, [R4.64+0x20] ; /* 0x0000200404007981 */
/* 0x000e24000c1e1900 */
/*01f0*/ SHF.L.U32 R7, R0, 0x1, RZ ; /* 0x0000000100077819 */
/* 0x001fca00000006ff */
/*0200*/ STG.E [R2.64+0x20], R7 ; /* 0x0000200702007986 */
/* 0x0001e8000c101904 */
/*0210*/ LDG.E R0, [R4.64+0x24] ; /* 0x0000240404007981 */
/* 0x000e64000c1e1900 */
/*0220*/ IMAD.SHL.U32 R9, R0, 0x2, RZ ; /* 0x0000000200097824 */
/* 0x002fca00078e00ff */
/*0230*/ STG.E [R2.64+0x24], R9 ; /* 0x0000240902007986 */
/* 0x0003e8000c101904 */
/*0240*/ LDG.E R0, [R4.64+0x28] ; /* 0x0000280404007981 */
/* 0x000ea4000c1e1900 */
/*0250*/ SHF.L.U32 R11, R0, 0x1, RZ ; /* 0x00000001000b7819 */
/* 0x004fca00000006ff */
/*0260*/ STG.E [R2.64+0x28], R11 ; /* 0x0000280b02007986 */
/* 0x0005e8000c101904 */
/*0270*/ LDG.E R0, [R4.64+0x2c] ; /* 0x00002c0404007981 */
/* 0x000ee4000c1e1900 */
/*0280*/ IMAD.SHL.U32 R13, R0, 0x2, RZ ; /* 0x00000002000d7824 */
/* 0x008fca00078e00ff */
/*0290*/ STG.E [R2.64+0x2c], R13 ; /* 0x00002c0d02007986 */
/* 0x0007e8000c101904 */
/*02a0*/ LDG.E R0, [R4.64+0x30] ; /* 0x0000300404007981 */
/* 0x000e24000c1e1900 */
/*02b0*/ SHF.L.U32 R7, R0, 0x1, RZ ; /* 0x0000000100077819 */
/* 0x001fca00000006ff */
/*02c0*/ STG.E [R2.64+0x30], R7 ; /* 0x0000300702007986 */
/* 0x0001e8000c101904 */
/*02d0*/ LDG.E R0, [R4.64+0x34] ; /* 0x0000340404007981 */
/* 0x000e64000c1e1900 */
/*02e0*/ IMAD.SHL.U32 R9, R0, 0x2, RZ ; /* 0x0000000200097824 */
/* 0x002fca00078e00ff */
/*02f0*/ STG.E [R2.64+0x34], R9 ; /* 0x0000340902007986 */
/* 0x0003e8000c101904 */
/*0300*/ LDG.E R0, [R4.64+0x38] ; /* 0x0000380404007981 */
/* 0x000ea4000c1e1900 */
/*0310*/ SHF.L.U32 R11, R0, 0x1, RZ ; /* 0x00000001000b7819 */
/* 0x004fca00000006ff */
/*0320*/ STG.E [R2.64+0x38], R11 ; /* 0x0000380b02007986 */
/* 0x0005e8000c101904 */
/*0330*/ LDG.E R0, [R4.64+0x3c] ; /* 0x00003c0404007981 */
/* 0x000ee4000c1e1900 */
/*0340*/ IMAD.SHL.U32 R13, R0, 0x2, RZ ; /* 0x00000002000d7824 */
/* 0x008fca00078e00ff */
/*0350*/ STG.E [R2.64+0x3c], R13 ; /* 0x00003c0d02007986 */
/* 0x0007e8000c101904 */
/*0360*/ LDG.E R0, [R4.64+0x40] ; /* 0x0000400404007981 */
/* 0x000e24000c1e1900 */
/*0370*/ SHF.L.U32 R7, R0, 0x1, RZ ; /* 0x0000000100077819 */
/* 0x001fca00000006ff */
/*0380*/ STG.E [R2.64+0x40], R7 ; /* 0x0000400702007986 */
/* 0x0001e8000c101904 */
/*0390*/ LDG.E R0, [R4.64+0x44] ; /* 0x0000440404007981 */
/* 0x000e64000c1e1900 */
/*03a0*/ IMAD.SHL.U32 R9, R0, 0x2, RZ ; /* 0x0000000200097824 */
/* 0x002fca00078e00ff */
/*03b0*/ STG.E [R2.64+0x44], R9 ; /* 0x0000440902007986 */
/* 0x0003e8000c101904 */
/*03c0*/ LDG.E R0, [R4.64+0x48] ; /* 0x0000480404007981 */
/* 0x000ea4000c1e1900 */
/*03d0*/ SHF.L.U32 R11, R0, 0x1, RZ ; /* 0x00000001000b7819 */
/* 0x004fca00000006ff */
/*03e0*/ STG.E [R2.64+0x48], R11 ; /* 0x0000480b02007986 */
/* 0x0005e8000c101904 */
/*03f0*/ LDG.E R0, [R4.64+0x4c] ; /* 0x00004c0404007981 */
/* 0x000ee4000c1e1900 */
/*0400*/ IMAD.SHL.U32 R13, R0, 0x2, RZ ; /* 0x00000002000d7824 */
/* 0x008fca00078e00ff */
/*0410*/ STG.E [R2.64+0x4c], R13 ; /* 0x00004c0d02007986 */
/* 0x0007e8000c101904 */
/*0420*/ LDG.E R0, [R4.64+0x50] ; /* 0x0000500404007981 */
/* 0x000e24000c1e1900 */
/*0430*/ SHF.L.U32 R7, R0, 0x1, RZ ; /* 0x0000000100077819 */
/* 0x001fca00000006ff */
/*0440*/ STG.E [R2.64+0x50], R7 ; /* 0x0000500702007986 */
/* 0x0001e8000c101904 */
/*0450*/ LDG.E R0, [R4.64+0x54] ; /* 0x0000540404007981 */
/* 0x000e64000c1e1900 */
/*0460*/ IMAD.SHL.U32 R9, R0, 0x2, RZ ; /* 0x0000000200097824 */
/* 0x002fca00078e00ff */
/*0470*/ STG.E [R2.64+0x54], R9 ; /* 0x0000540902007986 */
/* 0x0003e8000c101904 */
/*0480*/ LDG.E R0, [R4.64+0x58] ; /* 0x0000580404007981 */
/* 0x000ea4000c1e1900 */
/*0490*/ SHF.L.U32 R11, R0, 0x1, RZ ; /* 0x00000001000b7819 */
/* 0x004fca00000006ff */
/*04a0*/ STG.E [R2.64+0x58], R11 ; /* 0x0000580b02007986 */
/* 0x0005e8000c101904 */
/*04b0*/ LDG.E R0, [R4.64+0x5c] ; /* 0x00005c0404007981 */
/* 0x000ee4000c1e1900 */
/*04c0*/ IMAD.SHL.U32 R13, R0, 0x2, RZ ; /* 0x00000002000d7824 */
/* 0x008fca00078e00ff */
/*04d0*/ STG.E [R2.64+0x5c], R13 ; /* 0x00005c0d02007986 */
/* 0x0007e8000c101904 */
/*04e0*/ LDG.E R0, [R4.64+0x60] ; /* 0x0000600404007981 */
/* 0x000e24000c1e1900 */
/*04f0*/ SHF.L.U32 R7, R0, 0x1, RZ ; /* 0x0000000100077819 */
/* 0x001fca00000006ff */
/*0500*/ STG.E [R2.64+0x60], R7 ; /* 0x0000600702007986 */
/* 0x0001e8000c101904 */
/*0510*/ LDG.E R0, [R4.64+0x64] ; /* 0x0000640404007981 */
/* 0x000e64000c1e1900 */
/*0520*/ IMAD.SHL.U32 R9, R0, 0x2, RZ ; /* 0x0000000200097824 */
/* 0x002fca00078e00ff */
/*0530*/ STG.E [R2.64+0x64], R9 ; /* 0x0000640902007986 */
/* 0x0003e8000c101904 */
/*0540*/ LDG.E R0, [R4.64+0x68] ; /* 0x0000680404007981 */
/* 0x000ea4000c1e1900 */
/*0550*/ SHF.L.U32 R11, R0, 0x1, RZ ; /* 0x00000001000b7819 */
/* 0x004fca00000006ff */
/*0560*/ STG.E [R2.64+0x68], R11 ; /* 0x0000680b02007986 */
/* 0x0005e8000c101904 */
/*0570*/ LDG.E R0, [R4.64+0x6c] ; /* 0x00006c0404007981 */
/* 0x000ee4000c1e1900 */
/*0580*/ IMAD.SHL.U32 R13, R0, 0x2, RZ ; /* 0x00000002000d7824 */
/* 0x008fca00078e00ff */
/*0590*/ STG.E [R2.64+0x6c], R13 ; /* 0x00006c0d02007986 */
/* 0x0007e8000c101904 */
/*05a0*/ LDG.E R0, [R4.64+0x70] ; /* 0x0000700404007981 */
/* 0x000e24000c1e1900 */
/*05b0*/ SHF.L.U32 R7, R0, 0x1, RZ ; /* 0x0000000100077819 */
/* 0x001fca00000006ff */
/*05c0*/ STG.E [R2.64+0x70], R7 ; /* 0x0000700702007986 */
/* 0x000fe8000c101904 */
/*05d0*/ LDG.E R0, [R4.64+0x74] ; /* 0x0000740404007981 */
/* 0x000e64000c1e1900 */
/*05e0*/ IMAD.SHL.U32 R9, R0, 0x2, RZ ; /* 0x0000000200097824 */
/* 0x002fca00078e00ff */
/*05f0*/ STG.E [R2.64+0x74], R9 ; /* 0x0000740902007986 */
/* 0x000fe8000c101904 */
/*0600*/ LDG.E R0, [R4.64+0x78] ; /* 0x0000780404007981 */
/* 0x000ea4000c1e1900 */
/*0610*/ SHF.L.U32 R11, R0, 0x1, RZ ; /* 0x00000001000b7819 */
/* 0x004fca00000006ff */
/*0620*/ STG.E [R2.64+0x78], R11 ; /* 0x0000780b02007986 */
/* 0x000fe8000c101904 */
/*0630*/ LDG.E R0, [R4.64+0x7c] ; /* 0x00007c0404007981 */
/* 0x000ee4000c1e1900 */
/*0640*/ IMAD.SHL.U32 R13, R0, 0x2, RZ ; /* 0x00000002000d7824 */
/* 0x008fca00078e00ff */
/*0650*/ STG.E [R2.64+0x7c], R13 ; /* 0x00007c0d02007986 */
/* 0x000fe2000c101904 */
/*0660*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0670*/ BRA 0x670; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define N 32
__global__ void kernel(int* input, int* output){
for(int i=0; i<N; i++)
output[i] = 2 * input[i];
}
int main(void){
int *h_input, *h_output;
int *d_input, *d_output;
h_input = (int*)malloc(N*sizeof(int));
h_output = (int*)malloc(N*sizeof(int));
cudaMalloc((void**)&d_input, N*sizeof(int));
cudaMalloc((void**)&d_output, N*sizeof(int));
for(int i=0; i<N; i++) h_input[i] = i+1;
cudaMemcpy(d_input, h_input, N*sizeof(int), cudaMemcpyHostToDevice);
kernel<<<1, 1>>> (d_input, d_output);
cudaDeviceSynchronize();
cudaMemcpy(h_output, d_output, N*sizeof(int), cudaMemcpyDeviceToHost);
for(int i=0; i<N; i++) printf("%d -> %d\n", h_input[i], h_output[i]);
free(h_input);
free(h_output);
cudaFree(d_input);
cudaFree(d_output);
return 0;
} | .file "tmpxft_00141690_00000000-6_simple.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6kernelPiS_PiS_
.type _Z27__device_stub__Z6kernelPiS_PiS_, @function
_Z27__device_stub__Z6kernelPiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z6kernelPiS_PiS_, .-_Z27__device_stub__Z6kernelPiS_PiS_
.globl _Z6kernelPiS_
.type _Z6kernelPiS_, @function
_Z6kernelPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6kernelPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelPiS_, .-_Z6kernelPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d -> %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $128, %edi
call malloc@PLT
movq %rax, %rbp
movl $128, %edi
call malloc@PLT
movq %rax, %r12
movq %rsp, %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
movl $1, %eax
.L12:
movl %eax, -4(%rbp,%rax,4)
addq $1, %rax
cmpq $33, %rax
jne .L12
movl $1, %ecx
movl $128, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $128, %edx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %r13
.L14:
movl (%r12,%rbx), %ecx
movl 0(%rbp,%rbx), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $128, %rbx
jne .L14
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z27__device_stub__Z6kernelPiS_PiS_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z6kernelPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define N 32
__global__ void kernel(int* input, int* output){
for(int i=0; i<N; i++)
output[i] = 2 * input[i];
}
int main(void){
int *h_input, *h_output;
int *d_input, *d_output;
h_input = (int*)malloc(N*sizeof(int));
h_output = (int*)malloc(N*sizeof(int));
cudaMalloc((void**)&d_input, N*sizeof(int));
cudaMalloc((void**)&d_output, N*sizeof(int));
for(int i=0; i<N; i++) h_input[i] = i+1;
cudaMemcpy(d_input, h_input, N*sizeof(int), cudaMemcpyHostToDevice);
kernel<<<1, 1>>> (d_input, d_output);
cudaDeviceSynchronize();
cudaMemcpy(h_output, d_output, N*sizeof(int), cudaMemcpyDeviceToHost);
for(int i=0; i<N; i++) printf("%d -> %d\n", h_input[i], h_output[i]);
free(h_input);
free(h_output);
cudaFree(d_input);
cudaFree(d_output);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define N 32
__global__ void kernel(int* input, int* output){
for(int i=0; i<N; i++)
output[i] = 2 * input[i];
}
int main(void){
int *h_input, *h_output;
int *d_input, *d_output;
h_input = (int*)malloc(N*sizeof(int));
h_output = (int*)malloc(N*sizeof(int));
hipMalloc((void**)&d_input, N*sizeof(int));
hipMalloc((void**)&d_output, N*sizeof(int));
for(int i=0; i<N; i++) h_input[i] = i+1;
hipMemcpy(d_input, h_input, N*sizeof(int), hipMemcpyHostToDevice);
kernel<<<1, 1>>> (d_input, d_output);
hipDeviceSynchronize();
hipMemcpy(h_output, d_output, N*sizeof(int), hipMemcpyDeviceToHost);
for(int i=0; i<N; i++) printf("%d -> %d\n", h_input[i], h_output[i]);
free(h_input);
free(h_output);
hipFree(d_input);
hipFree(d_output);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define N 32
__global__ void kernel(int* input, int* output){
for(int i=0; i<N; i++)
output[i] = 2 * input[i];
}
int main(void){
int *h_input, *h_output;
int *d_input, *d_output;
h_input = (int*)malloc(N*sizeof(int));
h_output = (int*)malloc(N*sizeof(int));
hipMalloc((void**)&d_input, N*sizeof(int));
hipMalloc((void**)&d_output, N*sizeof(int));
for(int i=0; i<N; i++) h_input[i] = i+1;
hipMemcpy(d_input, h_input, N*sizeof(int), hipMemcpyHostToDevice);
kernel<<<1, 1>>> (d_input, d_output);
hipDeviceSynchronize();
hipMemcpy(h_output, d_output, N*sizeof(int), hipMemcpyDeviceToHost);
for(int i=0; i<N; i++) printf("%d -> %d\n", h_input[i], h_output[i]);
free(h_input);
free(h_output);
hipFree(d_input);
hipFree(d_output);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPiS_
.globl _Z6kernelPiS_
.p2align 8
.type _Z6kernelPiS_,@function
_Z6kernelPiS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_mov_b64 s[4:5], 0
.LBB0_1:
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s0, s4
s_addc_u32 s7, s1, s5
global_load_b32 v1, v0, s[6:7]
s_add_u32 s6, s2, s4
s_addc_u32 s7, s3, s5
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmpk_eq_i32 s4, 0x80
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v1, 1, v1
global_store_b32 v0, v1, s[6:7]
s_cbranch_scc0 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPiS_, .Lfunc_end0-_Z6kernelPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPiS_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z6kernelPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define N 32
__global__ void kernel(int* input, int* output){
for(int i=0; i<N; i++)
output[i] = 2 * input[i];
}
int main(void){
int *h_input, *h_output;
int *d_input, *d_output;
h_input = (int*)malloc(N*sizeof(int));
h_output = (int*)malloc(N*sizeof(int));
hipMalloc((void**)&d_input, N*sizeof(int));
hipMalloc((void**)&d_output, N*sizeof(int));
for(int i=0; i<N; i++) h_input[i] = i+1;
hipMemcpy(d_input, h_input, N*sizeof(int), hipMemcpyHostToDevice);
kernel<<<1, 1>>> (d_input, d_output);
hipDeviceSynchronize();
hipMemcpy(h_output, d_output, N*sizeof(int), hipMemcpyDeviceToHost);
for(int i=0; i<N; i++) printf("%d -> %d\n", h_input[i], h_output[i]);
free(h_input);
free(h_output);
hipFree(d_input);
hipFree(d_output);
return 0;
} | .text
.file "simple.hip"
.globl _Z21__device_stub__kernelPiS_ # -- Begin function _Z21__device_stub__kernelPiS_
.p2align 4, 0x90
.type _Z21__device_stub__kernelPiS_,@function
_Z21__device_stub__kernelPiS_: # @_Z21__device_stub__kernelPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPiS_, .Lfunc_end0-_Z21__device_stub__kernelPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $128, %edi
callq malloc
movq %rax, %rbx
movl $128, %edi
callq malloc
movq %rax, %r14
leaq 8(%rsp), %rdi
movl $128, %esi
callq hipMalloc
movq %rsp, %rdi
movl $128, %esi
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq 1(%rax), %rcx
movl %ecx, (%rbx,%rax,4)
movq %rcx, %rax
cmpq $32, %rcx
jne .LBB1_1
# %bb.2:
movq 8(%rsp), %rdi
movl $128, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
movq (%rsp), %rsi
movl $128, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl (%r14,%r15,4), %edx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $32, %r15
jne .LBB1_5
# %bb.6:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPiS_,@object # @_Z6kernelPiS_
.section .rodata,"a",@progbits
.globl _Z6kernelPiS_
.p2align 3, 0x0
_Z6kernelPiS_:
.quad _Z21__device_stub__kernelPiS_
.size _Z6kernelPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d -> %d\n"
.size .L.str, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPiS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0040*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea2000c1e1900 */
/*0050*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe200078e00ff */
/*0070*/ SHF.L.U32 R7, R0, 0x1, RZ ; /* 0x0000000100077819 */
/* 0x004fca00000006ff */
/*0080*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*0090*/ LDG.E R0, [R4.64+0x4] ; /* 0x0000040404007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ IMAD.SHL.U32 R9, R0, 0x2, RZ ; /* 0x0000000200097824 */
/* 0x004fca00078e00ff */
/*00b0*/ STG.E [R2.64+0x4], R9 ; /* 0x0000040902007986 */
/* 0x0003e8000c101904 */
/*00c0*/ LDG.E R0, [R4.64+0x8] ; /* 0x0000080404007981 */
/* 0x000ea4000c1e1900 */
/*00d0*/ SHF.L.U32 R11, R0, 0x1, RZ ; /* 0x00000001000b7819 */
/* 0x004fca00000006ff */
/*00e0*/ STG.E [R2.64+0x8], R11 ; /* 0x0000080b02007986 */
/* 0x0005e8000c101904 */
/*00f0*/ LDG.E R0, [R4.64+0xc] ; /* 0x00000c0404007981 */
/* 0x000ee4000c1e1900 */
/*0100*/ IMAD.SHL.U32 R13, R0, 0x2, RZ ; /* 0x00000002000d7824 */
/* 0x008fca00078e00ff */
/*0110*/ STG.E [R2.64+0xc], R13 ; /* 0x00000c0d02007986 */
/* 0x0007e8000c101904 */
/*0120*/ LDG.E R0, [R4.64+0x10] ; /* 0x0000100404007981 */
/* 0x000e24000c1e1900 */
/*0130*/ SHF.L.U32 R7, R0, 0x1, RZ ; /* 0x0000000100077819 */
/* 0x001fca00000006ff */
/*0140*/ STG.E [R2.64+0x10], R7 ; /* 0x0000100702007986 */
/* 0x0001e8000c101904 */
/*0150*/ LDG.E R0, [R4.64+0x14] ; /* 0x0000140404007981 */
/* 0x000e64000c1e1900 */
/*0160*/ IMAD.SHL.U32 R9, R0, 0x2, RZ ; /* 0x0000000200097824 */
/* 0x002fca00078e00ff */
/*0170*/ STG.E [R2.64+0x14], R9 ; /* 0x0000140902007986 */
/* 0x0003e8000c101904 */
/*0180*/ LDG.E R0, [R4.64+0x18] ; /* 0x0000180404007981 */
/* 0x000ea4000c1e1900 */
/*0190*/ SHF.L.U32 R11, R0, 0x1, RZ ; /* 0x00000001000b7819 */
/* 0x004fca00000006ff */
/*01a0*/ STG.E [R2.64+0x18], R11 ; /* 0x0000180b02007986 */
/* 0x0005e8000c101904 */
/*01b0*/ LDG.E R0, [R4.64+0x1c] ; /* 0x00001c0404007981 */
/* 0x000ee4000c1e1900 */
/*01c0*/ IMAD.SHL.U32 R13, R0, 0x2, RZ ; /* 0x00000002000d7824 */
/* 0x008fca00078e00ff */
/*01d0*/ STG.E [R2.64+0x1c], R13 ; /* 0x00001c0d02007986 */
/* 0x0007e8000c101904 */
/*01e0*/ LDG.E R0, [R4.64+0x20] ; /* 0x0000200404007981 */
/* 0x000e24000c1e1900 */
/*01f0*/ SHF.L.U32 R7, R0, 0x1, RZ ; /* 0x0000000100077819 */
/* 0x001fca00000006ff */
/*0200*/ STG.E [R2.64+0x20], R7 ; /* 0x0000200702007986 */
/* 0x0001e8000c101904 */
/*0210*/ LDG.E R0, [R4.64+0x24] ; /* 0x0000240404007981 */
/* 0x000e64000c1e1900 */
/*0220*/ IMAD.SHL.U32 R9, R0, 0x2, RZ ; /* 0x0000000200097824 */
/* 0x002fca00078e00ff */
/*0230*/ STG.E [R2.64+0x24], R9 ; /* 0x0000240902007986 */
/* 0x0003e8000c101904 */
/*0240*/ LDG.E R0, [R4.64+0x28] ; /* 0x0000280404007981 */
/* 0x000ea4000c1e1900 */
/*0250*/ SHF.L.U32 R11, R0, 0x1, RZ ; /* 0x00000001000b7819 */
/* 0x004fca00000006ff */
/*0260*/ STG.E [R2.64+0x28], R11 ; /* 0x0000280b02007986 */
/* 0x0005e8000c101904 */
/*0270*/ LDG.E R0, [R4.64+0x2c] ; /* 0x00002c0404007981 */
/* 0x000ee4000c1e1900 */
/*0280*/ IMAD.SHL.U32 R13, R0, 0x2, RZ ; /* 0x00000002000d7824 */
/* 0x008fca00078e00ff */
/*0290*/ STG.E [R2.64+0x2c], R13 ; /* 0x00002c0d02007986 */
/* 0x0007e8000c101904 */
/*02a0*/ LDG.E R0, [R4.64+0x30] ; /* 0x0000300404007981 */
/* 0x000e24000c1e1900 */
/*02b0*/ SHF.L.U32 R7, R0, 0x1, RZ ; /* 0x0000000100077819 */
/* 0x001fca00000006ff */
/*02c0*/ STG.E [R2.64+0x30], R7 ; /* 0x0000300702007986 */
/* 0x0001e8000c101904 */
/*02d0*/ LDG.E R0, [R4.64+0x34] ; /* 0x0000340404007981 */
/* 0x000e64000c1e1900 */
/*02e0*/ IMAD.SHL.U32 R9, R0, 0x2, RZ ; /* 0x0000000200097824 */
/* 0x002fca00078e00ff */
/*02f0*/ STG.E [R2.64+0x34], R9 ; /* 0x0000340902007986 */
/* 0x0003e8000c101904 */
/*0300*/ LDG.E R0, [R4.64+0x38] ; /* 0x0000380404007981 */
/* 0x000ea4000c1e1900 */
/*0310*/ SHF.L.U32 R11, R0, 0x1, RZ ; /* 0x00000001000b7819 */
/* 0x004fca00000006ff */
/*0320*/ STG.E [R2.64+0x38], R11 ; /* 0x0000380b02007986 */
/* 0x0005e8000c101904 */
/*0330*/ LDG.E R0, [R4.64+0x3c] ; /* 0x00003c0404007981 */
/* 0x000ee4000c1e1900 */
/*0340*/ IMAD.SHL.U32 R13, R0, 0x2, RZ ; /* 0x00000002000d7824 */
/* 0x008fca00078e00ff */
/*0350*/ STG.E [R2.64+0x3c], R13 ; /* 0x00003c0d02007986 */
/* 0x0007e8000c101904 */
/*0360*/ LDG.E R0, [R4.64+0x40] ; /* 0x0000400404007981 */
/* 0x000e24000c1e1900 */
/*0370*/ SHF.L.U32 R7, R0, 0x1, RZ ; /* 0x0000000100077819 */
/* 0x001fca00000006ff */
/*0380*/ STG.E [R2.64+0x40], R7 ; /* 0x0000400702007986 */
/* 0x0001e8000c101904 */
/*0390*/ LDG.E R0, [R4.64+0x44] ; /* 0x0000440404007981 */
/* 0x000e64000c1e1900 */
/*03a0*/ IMAD.SHL.U32 R9, R0, 0x2, RZ ; /* 0x0000000200097824 */
/* 0x002fca00078e00ff */
/*03b0*/ STG.E [R2.64+0x44], R9 ; /* 0x0000440902007986 */
/* 0x0003e8000c101904 */
/*03c0*/ LDG.E R0, [R4.64+0x48] ; /* 0x0000480404007981 */
/* 0x000ea4000c1e1900 */
/*03d0*/ SHF.L.U32 R11, R0, 0x1, RZ ; /* 0x00000001000b7819 */
/* 0x004fca00000006ff */
/*03e0*/ STG.E [R2.64+0x48], R11 ; /* 0x0000480b02007986 */
/* 0x0005e8000c101904 */
/*03f0*/ LDG.E R0, [R4.64+0x4c] ; /* 0x00004c0404007981 */
/* 0x000ee4000c1e1900 */
/*0400*/ IMAD.SHL.U32 R13, R0, 0x2, RZ ; /* 0x00000002000d7824 */
/* 0x008fca00078e00ff */
/*0410*/ STG.E [R2.64+0x4c], R13 ; /* 0x00004c0d02007986 */
/* 0x0007e8000c101904 */
/*0420*/ LDG.E R0, [R4.64+0x50] ; /* 0x0000500404007981 */
/* 0x000e24000c1e1900 */
/*0430*/ SHF.L.U32 R7, R0, 0x1, RZ ; /* 0x0000000100077819 */
/* 0x001fca00000006ff */
/*0440*/ STG.E [R2.64+0x50], R7 ; /* 0x0000500702007986 */
/* 0x0001e8000c101904 */
/*0450*/ LDG.E R0, [R4.64+0x54] ; /* 0x0000540404007981 */
/* 0x000e64000c1e1900 */
/*0460*/ IMAD.SHL.U32 R9, R0, 0x2, RZ ; /* 0x0000000200097824 */
/* 0x002fca00078e00ff */
/*0470*/ STG.E [R2.64+0x54], R9 ; /* 0x0000540902007986 */
/* 0x0003e8000c101904 */
/*0480*/ LDG.E R0, [R4.64+0x58] ; /* 0x0000580404007981 */
/* 0x000ea4000c1e1900 */
/*0490*/ SHF.L.U32 R11, R0, 0x1, RZ ; /* 0x00000001000b7819 */
/* 0x004fca00000006ff */
/*04a0*/ STG.E [R2.64+0x58], R11 ; /* 0x0000580b02007986 */
/* 0x0005e8000c101904 */
/*04b0*/ LDG.E R0, [R4.64+0x5c] ; /* 0x00005c0404007981 */
/* 0x000ee4000c1e1900 */
/*04c0*/ IMAD.SHL.U32 R13, R0, 0x2, RZ ; /* 0x00000002000d7824 */
/* 0x008fca00078e00ff */
/*04d0*/ STG.E [R2.64+0x5c], R13 ; /* 0x00005c0d02007986 */
/* 0x0007e8000c101904 */
/*04e0*/ LDG.E R0, [R4.64+0x60] ; /* 0x0000600404007981 */
/* 0x000e24000c1e1900 */
/*04f0*/ SHF.L.U32 R7, R0, 0x1, RZ ; /* 0x0000000100077819 */
/* 0x001fca00000006ff */
/*0500*/ STG.E [R2.64+0x60], R7 ; /* 0x0000600702007986 */
/* 0x0001e8000c101904 */
/*0510*/ LDG.E R0, [R4.64+0x64] ; /* 0x0000640404007981 */
/* 0x000e64000c1e1900 */
/*0520*/ IMAD.SHL.U32 R9, R0, 0x2, RZ ; /* 0x0000000200097824 */
/* 0x002fca00078e00ff */
/*0530*/ STG.E [R2.64+0x64], R9 ; /* 0x0000640902007986 */
/* 0x0003e8000c101904 */
/*0540*/ LDG.E R0, [R4.64+0x68] ; /* 0x0000680404007981 */
/* 0x000ea4000c1e1900 */
/*0550*/ SHF.L.U32 R11, R0, 0x1, RZ ; /* 0x00000001000b7819 */
/* 0x004fca00000006ff */
/*0560*/ STG.E [R2.64+0x68], R11 ; /* 0x0000680b02007986 */
/* 0x0005e8000c101904 */
/*0570*/ LDG.E R0, [R4.64+0x6c] ; /* 0x00006c0404007981 */
/* 0x000ee4000c1e1900 */
/*0580*/ IMAD.SHL.U32 R13, R0, 0x2, RZ ; /* 0x00000002000d7824 */
/* 0x008fca00078e00ff */
/*0590*/ STG.E [R2.64+0x6c], R13 ; /* 0x00006c0d02007986 */
/* 0x0007e8000c101904 */
/*05a0*/ LDG.E R0, [R4.64+0x70] ; /* 0x0000700404007981 */
/* 0x000e24000c1e1900 */
/*05b0*/ SHF.L.U32 R7, R0, 0x1, RZ ; /* 0x0000000100077819 */
/* 0x001fca00000006ff */
/*05c0*/ STG.E [R2.64+0x70], R7 ; /* 0x0000700702007986 */
/* 0x000fe8000c101904 */
/*05d0*/ LDG.E R0, [R4.64+0x74] ; /* 0x0000740404007981 */
/* 0x000e64000c1e1900 */
/*05e0*/ IMAD.SHL.U32 R9, R0, 0x2, RZ ; /* 0x0000000200097824 */
/* 0x002fca00078e00ff */
/*05f0*/ STG.E [R2.64+0x74], R9 ; /* 0x0000740902007986 */
/* 0x000fe8000c101904 */
/*0600*/ LDG.E R0, [R4.64+0x78] ; /* 0x0000780404007981 */
/* 0x000ea4000c1e1900 */
/*0610*/ SHF.L.U32 R11, R0, 0x1, RZ ; /* 0x00000001000b7819 */
/* 0x004fca00000006ff */
/*0620*/ STG.E [R2.64+0x78], R11 ; /* 0x0000780b02007986 */
/* 0x000fe8000c101904 */
/*0630*/ LDG.E R0, [R4.64+0x7c] ; /* 0x00007c0404007981 */
/* 0x000ee4000c1e1900 */
/*0640*/ IMAD.SHL.U32 R13, R0, 0x2, RZ ; /* 0x00000002000d7824 */
/* 0x008fca00078e00ff */
/*0650*/ STG.E [R2.64+0x7c], R13 ; /* 0x00007c0d02007986 */
/* 0x000fe2000c101904 */
/*0660*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0670*/ BRA 0x670; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPiS_
.globl _Z6kernelPiS_
.p2align 8
.type _Z6kernelPiS_,@function
_Z6kernelPiS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_mov_b64 s[4:5], 0
.LBB0_1:
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s0, s4
s_addc_u32 s7, s1, s5
global_load_b32 v1, v0, s[6:7]
s_add_u32 s6, s2, s4
s_addc_u32 s7, s3, s5
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmpk_eq_i32 s4, 0x80
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v1, 1, v1
global_store_b32 v0, v1, s[6:7]
s_cbranch_scc0 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPiS_, .Lfunc_end0-_Z6kernelPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPiS_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z6kernelPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00141690_00000000-6_simple.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6kernelPiS_PiS_
.type _Z27__device_stub__Z6kernelPiS_PiS_, @function
_Z27__device_stub__Z6kernelPiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z6kernelPiS_PiS_, .-_Z27__device_stub__Z6kernelPiS_PiS_
.globl _Z6kernelPiS_
.type _Z6kernelPiS_, @function
_Z6kernelPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6kernelPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelPiS_, .-_Z6kernelPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d -> %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $128, %edi
call malloc@PLT
movq %rax, %rbp
movl $128, %edi
call malloc@PLT
movq %rax, %r12
movq %rsp, %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
movl $1, %eax
.L12:
movl %eax, -4(%rbp,%rax,4)
addq $1, %rax
cmpq $33, %rax
jne .L12
movl $1, %ecx
movl $128, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $128, %edx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %r13
.L14:
movl (%r12,%rbx), %ecx
movl 0(%rbp,%rbx), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $128, %rbx
jne .L14
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z27__device_stub__Z6kernelPiS_PiS_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z6kernelPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "simple.hip"
.globl _Z21__device_stub__kernelPiS_ # -- Begin function _Z21__device_stub__kernelPiS_
.p2align 4, 0x90
.type _Z21__device_stub__kernelPiS_,@function
_Z21__device_stub__kernelPiS_: # @_Z21__device_stub__kernelPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPiS_, .Lfunc_end0-_Z21__device_stub__kernelPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $128, %edi
callq malloc
movq %rax, %rbx
movl $128, %edi
callq malloc
movq %rax, %r14
leaq 8(%rsp), %rdi
movl $128, %esi
callq hipMalloc
movq %rsp, %rdi
movl $128, %esi
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq 1(%rax), %rcx
movl %ecx, (%rbx,%rax,4)
movq %rcx, %rax
cmpq $32, %rcx
jne .LBB1_1
# %bb.2:
movq 8(%rsp), %rdi
movl $128, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
movq (%rsp), %rsi
movl $128, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl (%r14,%r15,4), %edx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $32, %r15
jne .LBB1_5
# %bb.6:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPiS_,@object # @_Z6kernelPiS_
.section .rodata,"a",@progbits
.globl _Z6kernelPiS_
.p2align 3, 0x0
_Z6kernelPiS_:
.quad _Z21__device_stub__kernelPiS_
.size _Z6kernelPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d -> %d\n"
.size .L.str, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPiS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
Uses N blocks with N threads
SOR Stokes Flow with no slip b.c. on top/bottom and no flux b.c. on left/right written by Dmitriy Kats
Inputs: N is the number of grid points in each direction,
mu is the viscosity
Pdiff is the pressure drop in the x direction
omega is the SOR factor
toltau is the tolerance of the residual
Outputs: The final velocities and pressure
*/
#include <stdlib.h>
#include <stdio.h>
#include<math.h>
#include <time.h>
//Kernels to udpate u, v, and p
//The inputs also considers if it is a red or black point udpate
__global__ void update_u(double* U, double* Uresid, double* P, double* Presid, double* FAC1, double* OMEGA, int RedorBlack);
__global__ void update_v(double* V, double* Vresid, double* P, double* Presid, double* FAC1, double* OMEGA, int RedorBlack);
__global__ void update_p(double* U, double* V, double* P, double* Presid, double* FAC1, double* OMEGA, double* Pdiff, int RedorBlack);
__device__ static int dev_N;
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
int main (int argc, char * argv[]){
// Choose the GPU card
cudaDeviceProp prop;
int dev;
memset(&prop, 0, sizeof(cudaDeviceProp));
prop.multiProcessorCount = 13;
cudaChooseDevice(&dev, &prop);
cudaSetDevice(dev);
// Create the CUDA events that will be used for timing the kernel function
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// Click, the timer has started running
cudaEventRecord(start, 0);
int N;
double mu, pdiff, omega, toltau;
N=atoi(argv[1]);
mu=atof(argv[2]);
pdiff=atof(argv[3]);
omega=atof(argv[4]);
toltau=atof(argv[5]);
double dx=1.0/((double)N-1.0);
double fac1=dx/mu; //precompute the factor
double residABSMAX = 99.0;
int numberOfIterations=0;
double* dev_fac1;
double* dev_omega;
double* dev_pdiff;
double *dev_u, *dev_uresid;
double *dev_v, *dev_vresid;
double *dev_p, *dev_presid;
//allocate memory for the velocities and pressure
double *u = (double*)malloc(N*(N-1)*sizeof(double));
double *uresid = (double*)malloc(N*(N-1)*sizeof(double));
double *v = (double*)malloc((N-1)*N*sizeof(double));
double *vresid = (double*)malloc((N-1)*N*sizeof(double));
double *p = (double*)malloc((N+1)*(N-1)*sizeof(double));
double *presid = (double*)malloc((N+1)*(N-1)*sizeof(double));
//allocate Cuda memory
cudaMalloc((void**)&dev_fac1, sizeof(double));
cudaMalloc((void**)&dev_omega, sizeof(double));
cudaMalloc((void**)&dev_pdiff, sizeof(double));
cudaMalloc((void**)&dev_u, N*(N-1)*sizeof(double));
cudaMalloc((void**)&dev_uresid, N*(N-1)*sizeof(double));
cudaMalloc((void**)&dev_v, (N-1)*N*sizeof(double));
cudaMalloc((void**)&dev_vresid, (N-1)*N*sizeof(double));
cudaMalloc((void**)&dev_p, (N+1)*(N-1)*sizeof(double));
cudaMalloc((void**)&dev_presid, (N+1)*(N-1)*sizeof(double));
//Intialize to zero
int i, j;
for(i=0; i<N; i++)
{
for(j=0; j<N-1; j++)
{
u[i+j*N]=0.0;
uresid[i+j*N]=0.0;
}
}
for(i=0; i<N-1; i++)
{
for(j=0; j<N; j++)
{
v[i+j*(N-1)]=0.0;
vresid[i+j*(N-1)]=0.0;
}
}
for(i=0; i<N+1; i++)
{
for(j=0; j<N-1; j++)
{
p[i+j*(N+1)]=0.0;
presid[i+j*(N+1)]=0.0;
}
}
//Copy the values to the device
cudaMemcpy(dev_u, u, N*(N-1)*sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(dev_uresid, uresid, N*(N-1)*sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(dev_v, v, (N-1)*N*sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(dev_vresid, vresid, (N-1)*N*sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(dev_p, p, (N+1)*(N-1)*sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(dev_presid, presid, (N+1)*(N-1)*sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(dev_N, &N, sizeof(int));
cudaMemcpy(dev_fac1, &fac1, sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(dev_omega, &omega, sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(dev_pdiff, &pdiff, sizeof(double), cudaMemcpyHostToDevice);
dim3 meshDim(N,N); //This one will be for the velocities
dim3 meshDim2(N+1,N); //This one will be for the pressure
while(residABSMAX>=toltau)
{
residABSMAX=0.1*toltau;
//Solve in the next six lines
update_u<<<meshDim,1>>>(dev_u, dev_uresid, dev_p, dev_presid, dev_fac1, dev_omega, 0);
update_u<<<meshDim,1>>>(dev_u, dev_uresid, dev_p, dev_presid, dev_fac1, dev_omega, 1);
update_v<<<meshDim,1>>>(dev_v, dev_vresid, dev_p, dev_presid, dev_fac1, dev_omega, 0);
update_v<<<meshDim,1>>>(dev_v, dev_vresid, dev_p, dev_presid, dev_fac1, dev_omega, 1);
update_p<<<meshDim2,1>>>(dev_u, dev_v, dev_p, dev_presid, dev_fac1, dev_omega, dev_pdiff, 0);
update_p<<<meshDim2,1>>>(dev_u, dev_v, dev_p, dev_presid, dev_fac1, dev_omega, dev_pdiff, 1);
//This is slow but I ran out of time
//Copy the residuals to the host to find the max residual
cudaMemcpy(uresid, dev_uresid, N*(N-1)*sizeof(double), cudaMemcpyDeviceToHost);
cudaMemcpy(vresid, dev_vresid, (N-1)*N*sizeof(double), cudaMemcpyDeviceToHost);
cudaMemcpy(presid, dev_presid, (N+1)*(N-1)*sizeof(double), cudaMemcpyDeviceToHost);
for(i=0; i<N; i++)
{
for(j=0; j<N-1; j++)
{
if(fabs(uresid[i+j*N])>residABSMAX)
{
residABSMAX=fabs(uresid[i+j*N]);
}
}
}
for(i=0; i<N-1; i++)
{
for(j=0; j<N; j++)
{
if(fabs(vresid[i+j*(N-1)])>residABSMAX)
{
residABSMAX=fabs(vresid[i+j*(N-1)]);
}
}
}
for(i=0; i<N+1; i++)
{
for(j=0; j<N-1; j++)
{
if(fabs(presid[i+j*(N+1)])>residABSMAX)
{
residABSMAX=fabs(presid[i+j*(N+1)]);
}
}
}
//Check for errors
gpuErrchk(cudaPeekAtLastError() );
gpuErrchk(cudaDeviceSynchronize() );
numberOfIterations+=1;
if (numberOfIterations>10000)
{ //fail safe to save data and exit
cudaMemcpy(u, dev_u, N*(N-1)*sizeof(double), cudaMemcpyDeviceToHost);
cudaMemcpy(v, dev_v, (N-1)*N*sizeof(double), cudaMemcpyDeviceToHost);
cudaMemcpy(p, dev_p, (N+1)*(N-1)*sizeof(double), cudaMemcpyDeviceToHost);
printf("Reached fail safe. The max residual is %10e. The number of iterations is %i\n", residABSMAX, numberOfIterations);
FILE *fpu = fopen("StokesU.out", "wb");
fwrite(u, sizeof(double), N*(N-1), fpu);
fclose (fpu);
FILE *fpv = fopen("StokesV.out", "wb");
fwrite(v, sizeof(double), (N-1)*N, fpv);
fclose (fpv);
FILE *fpP = fopen("StokesP.out", "wb");
fwrite(p, sizeof(double), (N+1)*(N-1), fpP);
fclose (fpP);
cudaFree(dev_u);
cudaFree(dev_uresid);
cudaFree(dev_v);
cudaFree(dev_vresid);
cudaFree(dev_p);
cudaFree(dev_presid);
cudaFree(dev_fac1);
cudaFree(dev_omega);
cudaFree(dev_pdiff);
free(u);
free(uresid);
free(v);
free(vresid);
free(p);
free(presid);
return 0;
}
}
cudaMemcpy(u, dev_u, N*(N-1)*sizeof(double), cudaMemcpyDeviceToHost);
cudaMemcpy(v, dev_v, (N-1)*N*sizeof(double), cudaMemcpyDeviceToHost);
cudaMemcpy(p, dev_p, (N+1)*(N-1)*sizeof(double), cudaMemcpyDeviceToHost);
//export the data
FILE *fpu = fopen("StokesU.out", "wb");
fwrite(u, sizeof(double), N*(N-1), fpu);
fclose (fpu);
FILE *fpv = fopen("StokesV.out", "wb");
fwrite(v, sizeof(double), (N-1)*N, fpv);
fclose (fpv);
FILE *fpP = fopen("StokesP.out", "wb");
fwrite(p, sizeof(double), (N+1)*(N-1), fpP);
fclose (fpP);
//stop the timer
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
// The elapsed time is computed by taking the difference between start and stop
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
printf("N:%i omega:%f\n", N, omega);
printf("The max residual is %10e and the number of iterations is %i\n", residABSMAX, numberOfIterations);
printf("Time: %gms\n", elapsedTime);
//clean up timer
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaFree(dev_u);
cudaFree(dev_uresid);
cudaFree(dev_v);
cudaFree(dev_vresid);
cudaFree(dev_p);
cudaFree(dev_presid);
cudaFree(dev_fac1);
cudaFree(dev_omega);
free(u);
free(uresid);
free(v);
free(vresid);
free(p);
free(presid);
return 0;
}
__global__ void update_u(double* U, double* Uresid, double* P, double* Presid, double* FAC1, double* OMEGA, int RorB)
{
int EvenOrOdd=(blockIdx.x+blockIdx.y)%2;
int u_ij00 = blockIdx.x + blockIdx.y * gridDim.x;
int u_ijp0 = (blockIdx.x + 1)%gridDim.x + blockIdx.y * gridDim.x; //down for u
int u_ijm0 = (blockIdx.x + gridDim.x - 1)%gridDim.x + blockIdx.y * gridDim.x; //up for u
int u_ij0p = blockIdx.x + ((blockIdx.y + 1)%gridDim.y) * gridDim.x; //east for u
int u_ij0m = blockIdx.x + ((blockIdx.y + gridDim.y - 1)%gridDim.y) * gridDim.x; //west for u
int p_ij00 = blockIdx.x + blockIdx.y * (gridDim.x+1);
int p_ijp0 = (blockIdx.x + 1)%(gridDim.x+1) + blockIdx.y * (gridDim.x+1); //down for p
//int p_ijm0 = (blockIdx.x + gridDim.x)%(gridDim.x+1) + blockIdx.y * (gridDim.x+1); //up for p
//int p_ij0p = blockIdx.x + ((blockIdx.y + 1)%gridDim.y) *(gridDim.x+1); //east for p
//int p_ij0m = blockIdx.x + ((blockIdx.y + gridDim.y - 1)%gridDim.y) * (gridDim.x+1); //west for p
//UPDATE INLET
if (blockIdx.y==0 && blockIdx.x==0 && EvenOrOdd==RorB)
{ //Corner point
Uresid[u_ij00]= (-U[u_ij00]+ U[u_ijp0])+(-3.0*U[u_ij00]+U[u_ij0p])-*FAC1*(P[p_ijp0]-P[p_ij00]);
U[u_ij00]=U[u_ij00]+*OMEGA*Uresid[u_ij00];
}
if (blockIdx.y>0 && blockIdx.y<(dev_N-2) && blockIdx.x==0 && EvenOrOdd==RorB)
{ //Middle points
Uresid[u_ij00]=(-U[u_ij00]+ U[u_ijp0])+(U[u_ij0m]-2.0*U[u_ij00]+U[u_ij0p])-*FAC1*(P[p_ijp0]-P[p_ij00]);
U[u_ij00]=U[u_ij00]+*OMEGA*Uresid[u_ij00];
}
if (blockIdx.y==(dev_N-2) && blockIdx.x==0 && EvenOrOdd==RorB)
{ //Corner point
Uresid[u_ij00]= (-U[u_ij00]+ U[u_ijp0])+(U[u_ij0m]-3.0*U[u_ij00])-*FAC1*(P[p_ijp0]-P[p_ij00]);
U[u_ij00]=U[u_ij00]+*OMEGA*Uresid[u_ij00];
}
//UPDATE BULK
if (blockIdx.y==0 && blockIdx.x>0 && blockIdx.x<(dev_N-1)&& EvenOrOdd==RorB)
{ // boundary condition
Uresid[u_ij00]= (U[u_ijm0]-2.0*U[u_ij00]+ U[u_ijp0])+(-3.0*U[u_ij00]+U[u_ij0p])-*FAC1*(P[p_ijp0]-P[p_ij00]);
U[u_ij00]=U[u_ij00]+*OMEGA*Uresid[u_ij00];
}
if (blockIdx.y>0 && blockIdx.y<(dev_N-2) && blockIdx.x>0 && blockIdx.x<(dev_N-1)&& EvenOrOdd==RorB)
{ //interior
Uresid[u_ij00]= (U[u_ijm0]-2.0*U[u_ij00]+ U[u_ijp0])+(U[u_ij0m]-2.0*U[u_ij00]+U[u_ij0p])-*FAC1*(P[p_ijp0]-P[p_ij00]);
U[u_ij00]=U[u_ij00]+*OMEGA*Uresid[u_ij00];
}
if (blockIdx.y==(dev_N-2) && blockIdx.x>0 && blockIdx.x<(dev_N-1)&& EvenOrOdd==RorB)
{ //boundary condition
Uresid[u_ij00]= (U[u_ijm0]-2.0*U[u_ij00]+ U[u_ijp0])+(U[u_ij0m]-3.0*U[u_ij00])-*FAC1*(P[p_ijp0]-P[p_ij00]);
U[u_ij00]=U[u_ij00]+*OMEGA*Uresid[u_ij00];
}
//Update Outlet
if (blockIdx.y==0 && blockIdx.x==(dev_N-1)&& EvenOrOdd==RorB)
{ //boundary condition
Uresid[u_ij00]= (U[u_ijm0]-U[u_ij00])+(-3.0*U[u_ij00]+U[u_ij0p])-*FAC1*(P[p_ijp0]-P[p_ij00]);
U[u_ij00]=U[u_ij00]+*OMEGA*Uresid[u_ij00];
}
if (blockIdx.y>0 && blockIdx.y<(dev_N-2) && blockIdx.x==(dev_N-1)&& EvenOrOdd==RorB)
{ //middle points on outlet
Uresid[u_ij00]= (U[u_ijm0]-U[u_ij00])+(U[u_ij0m]-2.0*U[u_ij00]+U[u_ij0p])-*FAC1*(P[p_ijp0]-P[p_ij00]);
U[u_ij00]=U[u_ij00]+*OMEGA*Uresid[u_ij00];
}
if (blockIdx.y==(dev_N-2) && blockIdx.x==(dev_N-1)&& EvenOrOdd==RorB)
{ //boundary node
Uresid[u_ij00]= (U[u_ijm0]-U[u_ij00])+(U[u_ij0m]-3.0*U[u_ij00])-*FAC1*(P[p_ijp0]-P[p_ij00]);
U[u_ij00]=U[u_ij00]+*OMEGA*Uresid[u_ij00];
}
__syncthreads();
}
__global__ void update_v(double* V, double* Vresid, double* P, double* Presid, double* FAC1, double* OMEGA, int RorB)
{
int EvenOrOdd=(blockIdx.x+blockIdx.y)%2;
int v_ij00 = blockIdx.x + blockIdx.y * (gridDim.x-1);
int v_ijp0 = (blockIdx.x + 1)%(gridDim.x-1) + blockIdx.y * (gridDim.x-1); //down for v
int v_ijm0 = (blockIdx.x + gridDim.x - 2)%(gridDim.x-1) + blockIdx.y * (gridDim.x-1); //up for v
int v_ij0p = blockIdx.x + ((blockIdx.y + 1)%gridDim.y) * (gridDim.x-1); //east for v
int v_ij0m = blockIdx.x + ((blockIdx.y + gridDim.y - 1)%gridDim.y) * (gridDim.x-1); //west for v
//int p_ij00 = blockIdx.x + blockIdx.y * (gridDim.x+1);
int p_ijp0 = (blockIdx.x + 1)%(gridDim.x+1) + blockIdx.y * (gridDim.x+1); //down for p
//int p_ijm0 = (blockIdx.x + gridDim.x)%(gridDim.x+1) + blockIdx.y * (gridDim.x+1); //up for p
//int p_ij0p = blockIdx.x + ((blockIdx.y + 1)%gridDim.y) *(gridDim.x+1); //east for p
//int p_ij0m = blockIdx.x + ((blockIdx.y + gridDim.y - 1)%gridDim.y) * (gridDim.x+1); //west for p
int p_ijpm = (blockIdx.x + 1)%(gridDim.x+1) + ((blockIdx.y + gridDim.y - 1)%gridDim.y) * (gridDim.x+1); //sw for p
//Update inlet similarly to above
if (blockIdx.y==0 && blockIdx.x==0 && EvenOrOdd==RorB)
{ //no velocity boundary condition
Vresid[v_ij00]= 0.0;
V[v_ij00]=0.0;
}
if (blockIdx.y>0 && blockIdx.y<(dev_N-1) && blockIdx.x==0 && EvenOrOdd==RorB)
{
Vresid[v_ij00]=(-V[v_ij00]+ V[v_ijp0])+(V[v_ij0m]-2.0*V[v_ij00]+V[v_ij0p])-*FAC1*(P[p_ijp0]-P[p_ijpm]);
V[v_ij00]=V[v_ij00]+*OMEGA*Vresid[v_ij00];
}
if (blockIdx.y==(dev_N-1) && blockIdx.x==0 && EvenOrOdd==0)
{
Vresid[v_ij00]= 0.0;
V[v_ij00]=0.0;
}
//Update Bulk similarly to above
if (blockIdx.y==0 && blockIdx.x>0 && blockIdx.x<(dev_N-2)&& EvenOrOdd==RorB)
{
Vresid[v_ij00]= 0.0;
V[v_ij00]=0.0;
}
if (blockIdx.y>0 && blockIdx.y<(dev_N-1) && blockIdx.x>0 && blockIdx.x<(dev_N-2)&& EvenOrOdd==RorB)
{
Vresid[v_ij00]=(V[v_ijm0]-2.0*V[v_ij00]+ V[v_ijp0])+(V[v_ij0m]-2.0*V[v_ij00]+V[v_ij0p])-*FAC1*(P[p_ijp0]-P[p_ijpm]);
V[v_ij00]=V[v_ij00]+*OMEGA*Vresid[v_ij00];
}
if (blockIdx.y==(dev_N-1) && blockIdx.x>0 && blockIdx.x<(dev_N-2)&& EvenOrOdd==RorB)
{
Vresid[v_ij00]=0.0;
V[v_ij00]=0.0;
}
//Update Outlet
if (blockIdx.y==0 && blockIdx.x==(dev_N-2)&& EvenOrOdd==RorB)
{
Vresid[v_ij00]= 0.0;
V[v_ij00]=0.0;
}
if (blockIdx.y>0 && blockIdx.y<(dev_N-1) && blockIdx.x==(dev_N-2)&& EvenOrOdd==RorB)
{
Vresid[v_ij00]=(V[v_ijm0]-V[v_ij00])+(V[v_ij0m]-2.0*V[v_ij00]+V[v_ij0p])-*FAC1*(P[p_ijp0]-P[p_ijpm]);
V[v_ij00]=V[v_ij00]+*OMEGA*Vresid[v_ij00];
}
if (blockIdx.y==(dev_N-1) && blockIdx.x==(dev_N-2)&& EvenOrOdd==RorB)
{
Vresid[v_ij00]= 0.0;
V[v_ij00]=0.0;
}
__syncthreads();
}
__global__ void update_p(double* U, double* V, double* P, double* Presid, double* FAC1, double* OMEGA, double* Pdiff, int RorB)
{
int EvenOrOdd=((int) (blockIdx.x+blockIdx.y)%2);
int u_ij00 = blockIdx.x + blockIdx.y * (gridDim.x-1);
int u_ijm0 = (blockIdx.x + gridDim.x - 2)%(gridDim.x-1) + blockIdx.y * (gridDim.x-1); //up for u
int v_ijm0 = (blockIdx.x + gridDim.x - 3)%(gridDim.x-2) + blockIdx.y * (gridDim.x-2); //up for v
int v_ijmp = (blockIdx.x + gridDim.x - 3)%(gridDim.x-2) + ((blockIdx.y + 1)%gridDim.y) * (gridDim.x-2);
int p_ij00 = blockIdx.x + blockIdx.y * (gridDim.x);
int p_ijp0 = (blockIdx.x + 1)%(gridDim.x) + blockIdx.y * (gridDim.x); //down for p
int p_ijm0 = (blockIdx.x + gridDim.x-1)%(gridDim.x) + blockIdx.y * (gridDim.x); //up for p
//Update the boundary with the right pressure drop
if (blockIdx.y<(dev_N-1) && blockIdx.x==0 && EvenOrOdd==RorB)
{
Presid[p_ij00]=2.0*(*Pdiff)-P[p_ijp0]-P[p_ij00];
P[p_ij00]=2.0*(*Pdiff)-P[p_ijp0];
}
//Update interior nodes
if (blockIdx.y<(dev_N-1) && blockIdx.x>0 && blockIdx.x<(dev_N) && EvenOrOdd==RorB)
{
Presid[p_ij00]=-(U[u_ij00]-U[u_ijm0])-(V[v_ijmp]-V[v_ijm0]);
P[p_ij00]=P[p_ij00]+*OMEGA*Presid[p_ij00];
}
//Update boundary conditions
if (blockIdx.y<(dev_N-1) && blockIdx.x==(dev_N) && EvenOrOdd==RorB)
{
P[p_ij00]=-P[p_ijm0];
}
__syncthreads();
} | .file "tmpxft_000cc681_00000000-6_sorGPU_DKfinal.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z8update_uPdS_S_S_S_S_iPdS_S_S_S_S_i
.type _Z38__device_stub__Z8update_uPdS_S_S_S_S_iPdS_S_S_S_S_i, @function
_Z38__device_stub__Z8update_uPdS_S_S_S_S_iPdS_S_S_S_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8update_uPdS_S_S_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z38__device_stub__Z8update_uPdS_S_S_S_S_iPdS_S_S_S_S_i, .-_Z38__device_stub__Z8update_uPdS_S_S_S_S_iPdS_S_S_S_S_i
.globl _Z8update_uPdS_S_S_S_S_i
.type _Z8update_uPdS_S_S_S_S_i, @function
_Z8update_uPdS_S_S_S_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z38__device_stub__Z8update_uPdS_S_S_S_S_iPdS_S_S_S_S_i
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z8update_uPdS_S_S_S_S_i, .-_Z8update_uPdS_S_S_S_S_i
.globl _Z38__device_stub__Z8update_vPdS_S_S_S_S_iPdS_S_S_S_S_i
.type _Z38__device_stub__Z8update_vPdS_S_S_S_S_iPdS_S_S_S_S_i, @function
_Z38__device_stub__Z8update_vPdS_S_S_S_S_iPdS_S_S_S_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8update_vPdS_S_S_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z38__device_stub__Z8update_vPdS_S_S_S_S_iPdS_S_S_S_S_i, .-_Z38__device_stub__Z8update_vPdS_S_S_S_S_iPdS_S_S_S_S_i
.globl _Z8update_vPdS_S_S_S_S_i
.type _Z8update_vPdS_S_S_S_S_i, @function
_Z8update_vPdS_S_S_S_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z38__device_stub__Z8update_vPdS_S_S_S_S_iPdS_S_S_S_S_i
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z8update_vPdS_S_S_S_S_i, .-_Z8update_vPdS_S_S_S_S_i
.globl _Z40__device_stub__Z8update_pPdS_S_S_S_S_S_iPdS_S_S_S_S_S_i
.type _Z40__device_stub__Z8update_pPdS_S_S_S_S_S_iPdS_S_S_S_S_S_i, @function
_Z40__device_stub__Z8update_pPdS_S_S_S_S_S_iPdS_S_S_S_S_S_i:
.LFB2087:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 224(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 232(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z8update_pPdS_S_S_S_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z40__device_stub__Z8update_pPdS_S_S_S_S_S_iPdS_S_S_S_S_S_i, .-_Z40__device_stub__Z8update_pPdS_S_S_S_S_S_iPdS_S_S_S_S_S_i
.globl _Z8update_pPdS_S_S_S_S_S_i
.type _Z8update_pPdS_S_S_S_S_S_i, @function
_Z8update_pPdS_S_S_S_S_S_i:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z40__device_stub__Z8update_pPdS_S_S_S_S_S_iPdS_S_S_S_S_S_i
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z8update_pPdS_S_S_S_S_S_i, .-_Z8update_pPdS_S_S_S_S_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "/home/ubuntu/Datasets/stackv2/train-structured/dmitriy-kats/StokesFlowCUDA/master/sorGPU_DKfinal.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "GPUassert: %s %s %d\n"
.section .rodata.str1.8
.align 8
.LC7:
.string "Reached fail safe. The max residual is %10e. The number of iterations is %i\n"
.section .rodata.str1.1
.LC8:
.string "wb"
.LC9:
.string "StokesU.out"
.LC10:
.string "StokesV.out"
.LC11:
.string "StokesP.out"
.LC12:
.string "N:%i omega:%f\n"
.section .rodata.str1.8
.align 8
.LC13:
.string "The max residual is %10e and the number of iterations is %i\n"
.section .rodata.str1.1
.LC14:
.string "Time: %gms\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1240, %rsp
.cfi_def_cfa_offset 1296
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 1224(%rsp)
xorl %eax, %eax
leaq 192(%rsp), %rsi
movl $129, %ecx
movq %rsi, %rdi
rep stosq
movl $13, 580(%rsp)
leaq 32(%rsp), %rdi
call cudaChooseDevice@PLT
movl 32(%rsp), %edi
call cudaSetDevice@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 36(%rsp)
movq 16(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movq 24(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 32(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movl 36(%rsp), %r15d
pxor %xmm1, %xmm1
cvtsi2sdl %r15d, %xmm1
movsd .LC1(%rip), %xmm0
subsd %xmm0, %xmm1
divsd %xmm1, %xmm0
divsd 8(%rsp), %xmm0
movsd %xmm0, 72(%rsp)
leal -1(%r15), %r12d
imull %r12d, %r15d
movslq %r15d, %rbp
salq $3, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbp
addl %r15d, %r12d
movslq %r12d, %r12
salq $3, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %r15
movq %r12, %rdi
call malloc@PLT
movq %rax, %r12
leaq 80(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
leaq 96(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
movl 36(%rsp), %eax
leal -1(%rax), %esi
imull %eax, %esi
movslq %esi, %rsi
salq $3, %rsi
leaq 104(%rsp), %rdi
call cudaMalloc@PLT
movl 36(%rsp), %eax
leal -1(%rax), %esi
imull %eax, %esi
movslq %esi, %rsi
salq $3, %rsi
leaq 112(%rsp), %rdi
call cudaMalloc@PLT
movl 36(%rsp), %eax
leal -1(%rax), %esi
imull %eax, %esi
movslq %esi, %rsi
salq $3, %rsi
leaq 120(%rsp), %rdi
call cudaMalloc@PLT
movl 36(%rsp), %eax
leal -1(%rax), %esi
imull %eax, %esi
movslq %esi, %rsi
salq $3, %rsi
leaq 128(%rsp), %rdi
call cudaMalloc@PLT
movl 36(%rsp), %eax
leal 1(%rax), %esi
subl $1, %eax
imull %eax, %esi
movslq %esi, %rsi
salq $3, %rsi
leaq 136(%rsp), %rdi
call cudaMalloc@PLT
movl 36(%rsp), %eax
leal 1(%rax), %esi
subl $1, %eax
imull %eax, %esi
movslq %esi, %rsi
salq $3, %rsi
leaq 144(%rsp), %rdi
call cudaMalloc@PLT
movl 36(%rsp), %ecx
testl %ecx, %ecx
jle .L28
movslq %ecx, %r9
leaq 0(,%r9,8), %rdi
movl $0, %r8d
leal -1(%rcx), %esi
jmp .L29
.L30:
movq $0x000000000, 0(%r13,%rax)
movq $0x000000000, (%rbx,%rax)
addl $1, %edx
addq %rdi, %rax
cmpl %esi, %edx
jne .L30
.L33:
addq $1, %r8
cmpq %r9, %r8
je .L31
.L29:
leaq 0(,%r8,8), %rax
movl $0, %edx
cmpl $1, %ecx
jg .L30
jmp .L33
.L38:
movq $0x000000000, (%r15,%rax)
movq $0x000000000, (%r12,%rax)
addl $1, %edx
addq %r8, %rax
cmpl %esi, %edx
jne .L38
.L41:
addq $1, %r9
cmpq %r10, %r9
je .L39
.L37:
leaq 0(,%r9,8), %rax
movl $0, %edx
testl %edi, %edi
jg .L38
jmp .L41
.L98:
subq $8, %rsp
.cfi_def_cfa_offset 1304
pushq $0
.cfi_def_cfa_offset 1312
movq 104(%rsp), %r9
movq 96(%rsp), %r8
movq 160(%rsp), %rcx
movq 152(%rsp), %rdx
movq 128(%rsp), %rsi
movq 120(%rsp), %rdi
call _Z38__device_stub__Z8update_uPdS_S_S_S_S_iPdS_S_S_S_S_i
addq $16, %rsp
.cfi_def_cfa_offset 1296
jmp .L43
.L99:
subq $8, %rsp
.cfi_def_cfa_offset 1304
pushq $1
.cfi_def_cfa_offset 1312
movq 104(%rsp), %r9
movq 96(%rsp), %r8
movq 160(%rsp), %rcx
movq 152(%rsp), %rdx
movq 128(%rsp), %rsi
movq 120(%rsp), %rdi
call _Z38__device_stub__Z8update_uPdS_S_S_S_S_iPdS_S_S_S_S_i
addq $16, %rsp
.cfi_def_cfa_offset 1296
jmp .L44
.L100:
subq $8, %rsp
.cfi_def_cfa_offset 1304
pushq $0
.cfi_def_cfa_offset 1312
movq 104(%rsp), %r9
movq 96(%rsp), %r8
movq 160(%rsp), %rcx
movq 152(%rsp), %rdx
movq 144(%rsp), %rsi
movq 136(%rsp), %rdi
call _Z38__device_stub__Z8update_vPdS_S_S_S_S_iPdS_S_S_S_S_i
addq $16, %rsp
.cfi_def_cfa_offset 1296
jmp .L45
.L101:
subq $8, %rsp
.cfi_def_cfa_offset 1304
pushq $1
.cfi_def_cfa_offset 1312
movq 104(%rsp), %r9
movq 96(%rsp), %r8
movq 160(%rsp), %rcx
movq 152(%rsp), %rdx
movq 144(%rsp), %rsi
movq 136(%rsp), %rdi
call _Z38__device_stub__Z8update_vPdS_S_S_S_S_iPdS_S_S_S_S_i
addq $16, %rsp
.cfi_def_cfa_offset 1296
jmp .L46
.L102:
pushq $0
.cfi_def_cfa_offset 1304
pushq 104(%rsp)
.cfi_def_cfa_offset 1312
movq 104(%rsp), %r9
movq 96(%rsp), %r8
movq 160(%rsp), %rcx
movq 152(%rsp), %rdx
movq 136(%rsp), %rsi
movq 120(%rsp), %rdi
call _Z40__device_stub__Z8update_pPdS_S_S_S_S_S_iPdS_S_S_S_S_S_i
addq $16, %rsp
.cfi_def_cfa_offset 1296
jmp .L47
.L103:
pushq $1
.cfi_def_cfa_offset 1304
pushq 104(%rsp)
.cfi_def_cfa_offset 1312
movq 104(%rsp), %r9
movq 96(%rsp), %r8
movq 160(%rsp), %rcx
movq 152(%rsp), %rdx
movq 136(%rsp), %rsi
movq 120(%rsp), %rdi
call _Z40__device_stub__Z8update_pPdS_S_S_S_S_S_iPdS_S_S_S_S_S_i
addq $16, %rsp
.cfi_def_cfa_offset 1296
jmp .L48
.L52:
movsd (%rdx), %xmm0
andpd .LC4(%rip), %xmm0
maxsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
addl $1, %eax
addq %rsi, %rdx
cmpl %edi, %eax
jne .L52
.L55:
addl $1, %r8d
addq $8, %r9
cmpl %ecx, %r8d
je .L53
.L50:
movq %r9, %rdx
movl $0, %eax
cmpl $1, %ecx
jg .L52
jmp .L55
.L62:
movsd (%rdx), %xmm0
andpd .LC4(%rip), %xmm0
maxsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
addl $1, %eax
addq %rsi, %rdx
cmpl %eax, %ecx
jne .L62
.L65:
addl $1, %r8d
addq $8, %r9
cmpl %r8d, %r10d
je .L63
.L60:
movq %r9, %rdx
movl $0, %eax
testl %edi, %edi
jg .L62
jmp .L65
.L95:
movl %eax, %ebx
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $206, %r9d
leaq .LC5(%rip), %r8
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L96:
movl %eax, %ebx
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $207, %r9d
leaq .LC5(%rip), %r8
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L97:
movl 36(%rsp), %eax
leal -1(%rax), %edx
imull %eax, %edx
movslq %edx, %rdx
salq $3, %rdx
movl $2, %ecx
movq 104(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl 36(%rsp), %eax
leal -1(%rax), %edx
imull %eax, %edx
movslq %edx, %rdx
salq $3, %rdx
movl $2, %ecx
movq 120(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl 36(%rsp), %eax
leal 1(%rax), %edx
subl $1, %eax
imull %eax, %edx
movslq %edx, %rdx
salq $3, %rdx
movl $2, %ecx
movq 136(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
leaq .LC8(%rip), %rsi
leaq .LC9(%rip), %rdi
call fopen@PLT
movq %rax, %rdi
movl 36(%rsp), %eax
leal -1(%rax), %edx
imull %eax, %edx
movslq %edx, %rdx
movq %rdi, 16(%rsp)
movq %rdi, %rcx
movl $8, %esi
movq %r13, %rdi
call fwrite@PLT
movq 16(%rsp), %rdi
call fclose@PLT
leaq .LC8(%rip), %rsi
leaq .LC10(%rip), %rdi
call fopen@PLT
movq %rax, %rdi
movl 36(%rsp), %eax
leal -1(%rax), %edx
imull %eax, %edx
movslq %edx, %rdx
movq %rdi, 16(%rsp)
movq %rdi, %rcx
movl $8, %esi
movq %r14, %rdi
call fwrite@PLT
movq 16(%rsp), %rdi
call fclose@PLT
leaq .LC8(%rip), %rsi
leaq .LC11(%rip), %rdi
call fopen@PLT
movq %rax, %rdi
movl 36(%rsp), %eax
leal 1(%rax), %edx
subl $1, %eax
imull %eax, %edx
movslq %edx, %rdx
movq %rdi, 16(%rsp)
movq %rdi, %rcx
movl $8, %esi
movq %r15, %rdi
call fwrite@PLT
movq 16(%rsp), %rdi
call fclose@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 180(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
movsd 64(%rsp), %xmm0
movl 36(%rsp), %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 28(%rsp), %edx
movsd 8(%rsp), %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 180(%rsp), %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 112(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rdi
call cudaFree@PLT
movq 128(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rdi
call cudaFree@PLT
movq 144(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
.L68:
movq 1224(%rsp), %rax
subq %fs:40, %rax
jne .L94
movl $0, %eax
addq $1240, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
leal -1(%rcx), %edi
jns .L59
.L63:
call cudaPeekAtLastError@PLT
testl %eax, %eax
jne .L95
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L96
addl $1, 28(%rsp)
movl 28(%rsp), %eax
cmpl $10001, %eax
jne .L42
movl 36(%rsp), %eax
leal -1(%rax), %edx
imull %eax, %edx
movslq %edx, %rdx
salq $3, %rdx
movl $2, %ecx
movq 104(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl 36(%rsp), %eax
leal -1(%rax), %edx
imull %eax, %edx
movslq %edx, %rdx
salq $3, %rdx
movl $2, %ecx
movq 120(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl 36(%rsp), %eax
leal 1(%rax), %edx
subl $1, %eax
imull %eax, %edx
movslq %edx, %rdx
salq $3, %rdx
movl $2, %ecx
movq 136(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl $10001, %edx
movsd 8(%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC8(%rip), %rsi
leaq .LC9(%rip), %rdi
call fopen@PLT
movq %rax, %rdi
movl 36(%rsp), %eax
leal -1(%rax), %edx
imull %eax, %edx
movslq %edx, %rdx
movq %rdi, 8(%rsp)
movq %rdi, %rcx
movl $8, %esi
movq %r13, %rdi
call fwrite@PLT
movq 8(%rsp), %rdi
call fclose@PLT
leaq .LC8(%rip), %rsi
leaq .LC10(%rip), %rdi
call fopen@PLT
movq %rax, %rdi
movl 36(%rsp), %eax
leal -1(%rax), %edx
imull %eax, %edx
movslq %edx, %rdx
movq %rdi, 8(%rsp)
movq %rdi, %rcx
movl $8, %esi
movq %r14, %rdi
call fwrite@PLT
movq 8(%rsp), %rdi
call fclose@PLT
leaq .LC8(%rip), %rsi
leaq .LC11(%rip), %rdi
call fopen@PLT
movq %rax, %rdi
movl 36(%rsp), %eax
leal 1(%rax), %edx
subl $1, %eax
imull %eax, %edx
movslq %edx, %rdx
movq %rdi, 8(%rsp)
movq %rdi, %rcx
movl $8, %esi
movq %r15, %rdi
call fwrite@PLT
movq 8(%rsp), %rdi
call fclose@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 112(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rdi
call cudaFree@PLT
movq 128(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rdi
call cudaFree@PLT
movq 144(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
jmp .L68
.L53:
leal -1(%rcx), %edi
testl %edi, %edi
jle .L59
movq %rbp, %r8
leal -1(%rcx), %r9d
movslq %edi, %rsi
salq $3, %rsi
movl $0, %r10d
.L56:
movq %r8, %rdx
movl $0, %eax
.L58:
movsd (%rdx), %xmm0
andpd .LC4(%rip), %xmm0
maxsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
addl $1, %eax
addq %rsi, %rdx
cmpl %ecx, %eax
jne .L58
addl $1, %r10d
addq $8, %r8
cmpl %r9d, %r10d
jne .L56
.L59:
movq %r12, %r9
leal 1(%rcx), %r10d
movslq %ecx, %rax
leaq 8(,%rax,8), %rsi
movl $0, %r8d
subl $1, %ecx
jmp .L60
.L28:
leal -1(%rcx), %edi
jns .L36
.L39:
imull %ecx, %edi
movslq %edi, %rdx
salq $3, %rdx
movl $1, %ecx
movq %r13, %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
movl 36(%rsp), %eax
leal -1(%rax), %edx
imull %eax, %edx
movslq %edx, %rdx
salq $3, %rdx
movl $1, %ecx
movq %rbx, %rsi
movq 112(%rsp), %rdi
call cudaMemcpy@PLT
movl 36(%rsp), %eax
leal -1(%rax), %edx
imull %eax, %edx
movslq %edx, %rdx
salq $3, %rdx
movl $1, %ecx
movq %r14, %rsi
movq 120(%rsp), %rdi
call cudaMemcpy@PLT
movl 36(%rsp), %eax
leal -1(%rax), %edx
imull %eax, %edx
movslq %edx, %rdx
salq $3, %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 128(%rsp), %rdi
call cudaMemcpy@PLT
movl 36(%rsp), %eax
leal 1(%rax), %edx
subl $1, %eax
imull %eax, %edx
movslq %edx, %rdx
salq $3, %rdx
movl $1, %ecx
movq %r15, %rsi
movq 136(%rsp), %rdi
call cudaMemcpy@PLT
movl 36(%rsp), %eax
leal 1(%rax), %edx
subl $1, %eax
imull %eax, %edx
movslq %edx, %rdx
salq $3, %rdx
movl $1, %ecx
movq %r12, %rsi
movq 144(%rsp), %rdi
call cudaMemcpy@PLT
leaq 36(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL5dev_N(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 72(%rsp), %rsi
movl $1, %ecx
movl $8, %edx
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $8, %edx
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
leaq 56(%rsp), %rsi
movl $1, %ecx
movl $8, %edx
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
movl 36(%rsp), %eax
movl %eax, 156(%rsp)
movl %eax, 160(%rsp)
movl $1, 164(%rsp)
leal 1(%rax), %edx
movl %edx, 168(%rsp)
movl %eax, 172(%rsp)
movl $1, 176(%rsp)
movl $0, 28(%rsp)
movsd .LC0(%rip), %xmm7
movsd %xmm7, 8(%rsp)
.L42:
movsd 8(%rsp), %xmm6
comisd 16(%rsp), %xmm6
jb .L97
movsd 16(%rsp), %xmm5
mulsd .LC3(%rip), %xmm5
movsd %xmm5, 8(%rsp)
movl $1, 180(%rsp)
movl $1, 184(%rsp)
movl $1, 188(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 180(%rsp), %rdx
movl $1, %ecx
movq 156(%rsp), %rdi
movl 164(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L98
.L43:
movl $1, 180(%rsp)
movl $1, 184(%rsp)
movl $1, 188(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 180(%rsp), %rdx
movl $1, %ecx
movq 156(%rsp), %rdi
movl 164(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L99
.L44:
movl $1, 180(%rsp)
movl $1, 184(%rsp)
movl $1, 188(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 180(%rsp), %rdx
movl $1, %ecx
movq 156(%rsp), %rdi
movl 164(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L100
.L45:
movl $1, 180(%rsp)
movl $1, 184(%rsp)
movl $1, 188(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 180(%rsp), %rdx
movl $1, %ecx
movq 156(%rsp), %rdi
movl 164(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L101
.L46:
movl $1, 180(%rsp)
movl $1, 184(%rsp)
movl $1, 188(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 180(%rsp), %rdx
movl $1, %ecx
movq 168(%rsp), %rdi
movl 176(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L102
.L47:
movl $1, 180(%rsp)
movl $1, 184(%rsp)
movl $1, 188(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 180(%rsp), %rdx
movl $1, %ecx
movq 168(%rsp), %rdi
movl 176(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L103
.L48:
movl 36(%rsp), %eax
leal -1(%rax), %edx
imull %eax, %edx
movslq %edx, %rdx
salq $3, %rdx
movl $2, %ecx
movq 112(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl 36(%rsp), %eax
leal -1(%rax), %edx
imull %eax, %edx
movslq %edx, %rdx
salq $3, %rdx
movl $2, %ecx
movq 128(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl 36(%rsp), %eax
leal 1(%rax), %edx
subl $1, %eax
imull %eax, %edx
movslq %edx, %rdx
salq $3, %rdx
movl $2, %ecx
movq 144(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl 36(%rsp), %ecx
testl %ecx, %ecx
jle .L49
movq %rbx, %r9
movslq %ecx, %rsi
salq $3, %rsi
movl $0, %r8d
leal -1(%rcx), %edi
jmp .L50
.L31:
leal -1(%rcx), %edi
testl %edi, %edi
jle .L36
leal -1(%rcx), %r9d
movslq %edi, %rsi
salq $3, %rsi
movl $0, %r8d
.L34:
leaq 0(,%r8,8), %rax
movl $0, %edx
.L35:
movq $0x000000000, (%r14,%rax)
movq $0x000000000, 0(%rbp,%rax)
addl $1, %edx
addq %rsi, %rax
cmpl %ecx, %edx
jne .L35
addq $1, %r8
cmpq %r9, %r8
jne .L34
.L36:
leal 1(%rcx), %r10d
movslq %ecx, %rax
leaq 8(,%rax,8), %r8
movl $0, %r9d
leal -1(%rcx), %esi
jmp .L37
.L94:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC15:
.string "_Z8update_pPdS_S_S_S_S_S_i"
.LC16:
.string "_Z8update_vPdS_S_S_S_S_i"
.LC17:
.string "_Z8update_uPdS_S_S_S_S_i"
.LC18:
.string "dev_N"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z8update_pPdS_S_S_S_S_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z8update_vPdS_S_S_S_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z8update_uPdS_S_S_S_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5dev_N(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL5dev_N
.comm _ZL5dev_N,4,4
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1079558144
.align 8
.LC1:
.long 0
.long 1072693248
.align 8
.LC3:
.long -1717986918
.long 1069128089
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long -1
.long 2147483647
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
Uses N blocks with N threads
SOR Stokes Flow with no slip b.c. on top/bottom and no flux b.c. on left/right written by Dmitriy Kats
Inputs: N is the number of grid points in each direction,
mu is the viscosity
Pdiff is the pressure drop in the x direction
omega is the SOR factor
toltau is the tolerance of the residual
Outputs: The final velocities and pressure
*/
#include <stdlib.h>
#include <stdio.h>
#include<math.h>
#include <time.h>
//Kernels to udpate u, v, and p
//The inputs also considers if it is a red or black point udpate
__global__ void update_u(double* U, double* Uresid, double* P, double* Presid, double* FAC1, double* OMEGA, int RedorBlack);
__global__ void update_v(double* V, double* Vresid, double* P, double* Presid, double* FAC1, double* OMEGA, int RedorBlack);
__global__ void update_p(double* U, double* V, double* P, double* Presid, double* FAC1, double* OMEGA, double* Pdiff, int RedorBlack);
__device__ static int dev_N;
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
int main (int argc, char * argv[]){
// Choose the GPU card
cudaDeviceProp prop;
int dev;
memset(&prop, 0, sizeof(cudaDeviceProp));
prop.multiProcessorCount = 13;
cudaChooseDevice(&dev, &prop);
cudaSetDevice(dev);
// Create the CUDA events that will be used for timing the kernel function
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// Click, the timer has started running
cudaEventRecord(start, 0);
int N;
double mu, pdiff, omega, toltau;
N=atoi(argv[1]);
mu=atof(argv[2]);
pdiff=atof(argv[3]);
omega=atof(argv[4]);
toltau=atof(argv[5]);
double dx=1.0/((double)N-1.0);
double fac1=dx/mu; //precompute the factor
double residABSMAX = 99.0;
int numberOfIterations=0;
double* dev_fac1;
double* dev_omega;
double* dev_pdiff;
double *dev_u, *dev_uresid;
double *dev_v, *dev_vresid;
double *dev_p, *dev_presid;
//allocate memory for the velocities and pressure
double *u = (double*)malloc(N*(N-1)*sizeof(double));
double *uresid = (double*)malloc(N*(N-1)*sizeof(double));
double *v = (double*)malloc((N-1)*N*sizeof(double));
double *vresid = (double*)malloc((N-1)*N*sizeof(double));
double *p = (double*)malloc((N+1)*(N-1)*sizeof(double));
double *presid = (double*)malloc((N+1)*(N-1)*sizeof(double));
//allocate Cuda memory
cudaMalloc((void**)&dev_fac1, sizeof(double));
cudaMalloc((void**)&dev_omega, sizeof(double));
cudaMalloc((void**)&dev_pdiff, sizeof(double));
cudaMalloc((void**)&dev_u, N*(N-1)*sizeof(double));
cudaMalloc((void**)&dev_uresid, N*(N-1)*sizeof(double));
cudaMalloc((void**)&dev_v, (N-1)*N*sizeof(double));
cudaMalloc((void**)&dev_vresid, (N-1)*N*sizeof(double));
cudaMalloc((void**)&dev_p, (N+1)*(N-1)*sizeof(double));
cudaMalloc((void**)&dev_presid, (N+1)*(N-1)*sizeof(double));
//Intialize to zero
int i, j;
for(i=0; i<N; i++)
{
for(j=0; j<N-1; j++)
{
u[i+j*N]=0.0;
uresid[i+j*N]=0.0;
}
}
for(i=0; i<N-1; i++)
{
for(j=0; j<N; j++)
{
v[i+j*(N-1)]=0.0;
vresid[i+j*(N-1)]=0.0;
}
}
for(i=0; i<N+1; i++)
{
for(j=0; j<N-1; j++)
{
p[i+j*(N+1)]=0.0;
presid[i+j*(N+1)]=0.0;
}
}
//Copy the values to the device
cudaMemcpy(dev_u, u, N*(N-1)*sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(dev_uresid, uresid, N*(N-1)*sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(dev_v, v, (N-1)*N*sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(dev_vresid, vresid, (N-1)*N*sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(dev_p, p, (N+1)*(N-1)*sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(dev_presid, presid, (N+1)*(N-1)*sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(dev_N, &N, sizeof(int));
cudaMemcpy(dev_fac1, &fac1, sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(dev_omega, &omega, sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(dev_pdiff, &pdiff, sizeof(double), cudaMemcpyHostToDevice);
dim3 meshDim(N,N); //This one will be for the velocities
dim3 meshDim2(N+1,N); //This one will be for the pressure
while(residABSMAX>=toltau)
{
residABSMAX=0.1*toltau;
//Solve in the next six lines
update_u<<<meshDim,1>>>(dev_u, dev_uresid, dev_p, dev_presid, dev_fac1, dev_omega, 0);
update_u<<<meshDim,1>>>(dev_u, dev_uresid, dev_p, dev_presid, dev_fac1, dev_omega, 1);
update_v<<<meshDim,1>>>(dev_v, dev_vresid, dev_p, dev_presid, dev_fac1, dev_omega, 0);
update_v<<<meshDim,1>>>(dev_v, dev_vresid, dev_p, dev_presid, dev_fac1, dev_omega, 1);
update_p<<<meshDim2,1>>>(dev_u, dev_v, dev_p, dev_presid, dev_fac1, dev_omega, dev_pdiff, 0);
update_p<<<meshDim2,1>>>(dev_u, dev_v, dev_p, dev_presid, dev_fac1, dev_omega, dev_pdiff, 1);
//This is slow but I ran out of time
//Copy the residuals to the host to find the max residual
cudaMemcpy(uresid, dev_uresid, N*(N-1)*sizeof(double), cudaMemcpyDeviceToHost);
cudaMemcpy(vresid, dev_vresid, (N-1)*N*sizeof(double), cudaMemcpyDeviceToHost);
cudaMemcpy(presid, dev_presid, (N+1)*(N-1)*sizeof(double), cudaMemcpyDeviceToHost);
for(i=0; i<N; i++)
{
for(j=0; j<N-1; j++)
{
if(fabs(uresid[i+j*N])>residABSMAX)
{
residABSMAX=fabs(uresid[i+j*N]);
}
}
}
for(i=0; i<N-1; i++)
{
for(j=0; j<N; j++)
{
if(fabs(vresid[i+j*(N-1)])>residABSMAX)
{
residABSMAX=fabs(vresid[i+j*(N-1)]);
}
}
}
for(i=0; i<N+1; i++)
{
for(j=0; j<N-1; j++)
{
if(fabs(presid[i+j*(N+1)])>residABSMAX)
{
residABSMAX=fabs(presid[i+j*(N+1)]);
}
}
}
//Check for errors
gpuErrchk(cudaPeekAtLastError() );
gpuErrchk(cudaDeviceSynchronize() );
numberOfIterations+=1;
if (numberOfIterations>10000)
{ //fail safe to save data and exit
cudaMemcpy(u, dev_u, N*(N-1)*sizeof(double), cudaMemcpyDeviceToHost);
cudaMemcpy(v, dev_v, (N-1)*N*sizeof(double), cudaMemcpyDeviceToHost);
cudaMemcpy(p, dev_p, (N+1)*(N-1)*sizeof(double), cudaMemcpyDeviceToHost);
printf("Reached fail safe. The max residual is %10e. The number of iterations is %i\n", residABSMAX, numberOfIterations);
FILE *fpu = fopen("StokesU.out", "wb");
fwrite(u, sizeof(double), N*(N-1), fpu);
fclose (fpu);
FILE *fpv = fopen("StokesV.out", "wb");
fwrite(v, sizeof(double), (N-1)*N, fpv);
fclose (fpv);
FILE *fpP = fopen("StokesP.out", "wb");
fwrite(p, sizeof(double), (N+1)*(N-1), fpP);
fclose (fpP);
cudaFree(dev_u);
cudaFree(dev_uresid);
cudaFree(dev_v);
cudaFree(dev_vresid);
cudaFree(dev_p);
cudaFree(dev_presid);
cudaFree(dev_fac1);
cudaFree(dev_omega);
cudaFree(dev_pdiff);
free(u);
free(uresid);
free(v);
free(vresid);
free(p);
free(presid);
return 0;
}
}
cudaMemcpy(u, dev_u, N*(N-1)*sizeof(double), cudaMemcpyDeviceToHost);
cudaMemcpy(v, dev_v, (N-1)*N*sizeof(double), cudaMemcpyDeviceToHost);
cudaMemcpy(p, dev_p, (N+1)*(N-1)*sizeof(double), cudaMemcpyDeviceToHost);
//export the data
FILE *fpu = fopen("StokesU.out", "wb");
fwrite(u, sizeof(double), N*(N-1), fpu);
fclose (fpu);
FILE *fpv = fopen("StokesV.out", "wb");
fwrite(v, sizeof(double), (N-1)*N, fpv);
fclose (fpv);
FILE *fpP = fopen("StokesP.out", "wb");
fwrite(p, sizeof(double), (N+1)*(N-1), fpP);
fclose (fpP);
//stop the timer
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
// The elapsed time is computed by taking the difference between start and stop
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
printf("N:%i omega:%f\n", N, omega);
printf("The max residual is %10e and the number of iterations is %i\n", residABSMAX, numberOfIterations);
printf("Time: %gms\n", elapsedTime);
//clean up timer
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaFree(dev_u);
cudaFree(dev_uresid);
cudaFree(dev_v);
cudaFree(dev_vresid);
cudaFree(dev_p);
cudaFree(dev_presid);
cudaFree(dev_fac1);
cudaFree(dev_omega);
free(u);
free(uresid);
free(v);
free(vresid);
free(p);
free(presid);
return 0;
}
__global__ void update_u(double* U, double* Uresid, double* P, double* Presid, double* FAC1, double* OMEGA, int RorB)
{
int EvenOrOdd=(blockIdx.x+blockIdx.y)%2;
int u_ij00 = blockIdx.x + blockIdx.y * gridDim.x;
int u_ijp0 = (blockIdx.x + 1)%gridDim.x + blockIdx.y * gridDim.x; //down for u
int u_ijm0 = (blockIdx.x + gridDim.x - 1)%gridDim.x + blockIdx.y * gridDim.x; //up for u
int u_ij0p = blockIdx.x + ((blockIdx.y + 1)%gridDim.y) * gridDim.x; //east for u
int u_ij0m = blockIdx.x + ((blockIdx.y + gridDim.y - 1)%gridDim.y) * gridDim.x; //west for u
int p_ij00 = blockIdx.x + blockIdx.y * (gridDim.x+1);
int p_ijp0 = (blockIdx.x + 1)%(gridDim.x+1) + blockIdx.y * (gridDim.x+1); //down for p
//int p_ijm0 = (blockIdx.x + gridDim.x)%(gridDim.x+1) + blockIdx.y * (gridDim.x+1); //up for p
//int p_ij0p = blockIdx.x + ((blockIdx.y + 1)%gridDim.y) *(gridDim.x+1); //east for p
//int p_ij0m = blockIdx.x + ((blockIdx.y + gridDim.y - 1)%gridDim.y) * (gridDim.x+1); //west for p
//UPDATE INLET
if (blockIdx.y==0 && blockIdx.x==0 && EvenOrOdd==RorB)
{ //Corner point
Uresid[u_ij00]= (-U[u_ij00]+ U[u_ijp0])+(-3.0*U[u_ij00]+U[u_ij0p])-*FAC1*(P[p_ijp0]-P[p_ij00]);
U[u_ij00]=U[u_ij00]+*OMEGA*Uresid[u_ij00];
}
if (blockIdx.y>0 && blockIdx.y<(dev_N-2) && blockIdx.x==0 && EvenOrOdd==RorB)
{ //Middle points
Uresid[u_ij00]=(-U[u_ij00]+ U[u_ijp0])+(U[u_ij0m]-2.0*U[u_ij00]+U[u_ij0p])-*FAC1*(P[p_ijp0]-P[p_ij00]);
U[u_ij00]=U[u_ij00]+*OMEGA*Uresid[u_ij00];
}
if (blockIdx.y==(dev_N-2) && blockIdx.x==0 && EvenOrOdd==RorB)
{ //Corner point
Uresid[u_ij00]= (-U[u_ij00]+ U[u_ijp0])+(U[u_ij0m]-3.0*U[u_ij00])-*FAC1*(P[p_ijp0]-P[p_ij00]);
U[u_ij00]=U[u_ij00]+*OMEGA*Uresid[u_ij00];
}
//UPDATE BULK
if (blockIdx.y==0 && blockIdx.x>0 && blockIdx.x<(dev_N-1)&& EvenOrOdd==RorB)
{ // boundary condition
Uresid[u_ij00]= (U[u_ijm0]-2.0*U[u_ij00]+ U[u_ijp0])+(-3.0*U[u_ij00]+U[u_ij0p])-*FAC1*(P[p_ijp0]-P[p_ij00]);
U[u_ij00]=U[u_ij00]+*OMEGA*Uresid[u_ij00];
}
if (blockIdx.y>0 && blockIdx.y<(dev_N-2) && blockIdx.x>0 && blockIdx.x<(dev_N-1)&& EvenOrOdd==RorB)
{ //interior
Uresid[u_ij00]= (U[u_ijm0]-2.0*U[u_ij00]+ U[u_ijp0])+(U[u_ij0m]-2.0*U[u_ij00]+U[u_ij0p])-*FAC1*(P[p_ijp0]-P[p_ij00]);
U[u_ij00]=U[u_ij00]+*OMEGA*Uresid[u_ij00];
}
if (blockIdx.y==(dev_N-2) && blockIdx.x>0 && blockIdx.x<(dev_N-1)&& EvenOrOdd==RorB)
{ //boundary condition
Uresid[u_ij00]= (U[u_ijm0]-2.0*U[u_ij00]+ U[u_ijp0])+(U[u_ij0m]-3.0*U[u_ij00])-*FAC1*(P[p_ijp0]-P[p_ij00]);
U[u_ij00]=U[u_ij00]+*OMEGA*Uresid[u_ij00];
}
//Update Outlet
if (blockIdx.y==0 && blockIdx.x==(dev_N-1)&& EvenOrOdd==RorB)
{ //boundary condition
Uresid[u_ij00]= (U[u_ijm0]-U[u_ij00])+(-3.0*U[u_ij00]+U[u_ij0p])-*FAC1*(P[p_ijp0]-P[p_ij00]);
U[u_ij00]=U[u_ij00]+*OMEGA*Uresid[u_ij00];
}
if (blockIdx.y>0 && blockIdx.y<(dev_N-2) && blockIdx.x==(dev_N-1)&& EvenOrOdd==RorB)
{ //middle points on outlet
Uresid[u_ij00]= (U[u_ijm0]-U[u_ij00])+(U[u_ij0m]-2.0*U[u_ij00]+U[u_ij0p])-*FAC1*(P[p_ijp0]-P[p_ij00]);
U[u_ij00]=U[u_ij00]+*OMEGA*Uresid[u_ij00];
}
if (blockIdx.y==(dev_N-2) && blockIdx.x==(dev_N-1)&& EvenOrOdd==RorB)
{ //boundary node
Uresid[u_ij00]= (U[u_ijm0]-U[u_ij00])+(U[u_ij0m]-3.0*U[u_ij00])-*FAC1*(P[p_ijp0]-P[p_ij00]);
U[u_ij00]=U[u_ij00]+*OMEGA*Uresid[u_ij00];
}
__syncthreads();
}
__global__ void update_v(double* V, double* Vresid, double* P, double* Presid, double* FAC1, double* OMEGA, int RorB)
{
int EvenOrOdd=(blockIdx.x+blockIdx.y)%2;
int v_ij00 = blockIdx.x + blockIdx.y * (gridDim.x-1);
int v_ijp0 = (blockIdx.x + 1)%(gridDim.x-1) + blockIdx.y * (gridDim.x-1); //down for v
int v_ijm0 = (blockIdx.x + gridDim.x - 2)%(gridDim.x-1) + blockIdx.y * (gridDim.x-1); //up for v
int v_ij0p = blockIdx.x + ((blockIdx.y + 1)%gridDim.y) * (gridDim.x-1); //east for v
int v_ij0m = blockIdx.x + ((blockIdx.y + gridDim.y - 1)%gridDim.y) * (gridDim.x-1); //west for v
//int p_ij00 = blockIdx.x + blockIdx.y * (gridDim.x+1);
int p_ijp0 = (blockIdx.x + 1)%(gridDim.x+1) + blockIdx.y * (gridDim.x+1); //down for p
//int p_ijm0 = (blockIdx.x + gridDim.x)%(gridDim.x+1) + blockIdx.y * (gridDim.x+1); //up for p
//int p_ij0p = blockIdx.x + ((blockIdx.y + 1)%gridDim.y) *(gridDim.x+1); //east for p
//int p_ij0m = blockIdx.x + ((blockIdx.y + gridDim.y - 1)%gridDim.y) * (gridDim.x+1); //west for p
int p_ijpm = (blockIdx.x + 1)%(gridDim.x+1) + ((blockIdx.y + gridDim.y - 1)%gridDim.y) * (gridDim.x+1); //sw for p
//Update inlet similarly to above
if (blockIdx.y==0 && blockIdx.x==0 && EvenOrOdd==RorB)
{ //no velocity boundary condition
Vresid[v_ij00]= 0.0;
V[v_ij00]=0.0;
}
if (blockIdx.y>0 && blockIdx.y<(dev_N-1) && blockIdx.x==0 && EvenOrOdd==RorB)
{
Vresid[v_ij00]=(-V[v_ij00]+ V[v_ijp0])+(V[v_ij0m]-2.0*V[v_ij00]+V[v_ij0p])-*FAC1*(P[p_ijp0]-P[p_ijpm]);
V[v_ij00]=V[v_ij00]+*OMEGA*Vresid[v_ij00];
}
if (blockIdx.y==(dev_N-1) && blockIdx.x==0 && EvenOrOdd==0)
{
Vresid[v_ij00]= 0.0;
V[v_ij00]=0.0;
}
//Update Bulk similarly to above
if (blockIdx.y==0 && blockIdx.x>0 && blockIdx.x<(dev_N-2)&& EvenOrOdd==RorB)
{
Vresid[v_ij00]= 0.0;
V[v_ij00]=0.0;
}
if (blockIdx.y>0 && blockIdx.y<(dev_N-1) && blockIdx.x>0 && blockIdx.x<(dev_N-2)&& EvenOrOdd==RorB)
{
Vresid[v_ij00]=(V[v_ijm0]-2.0*V[v_ij00]+ V[v_ijp0])+(V[v_ij0m]-2.0*V[v_ij00]+V[v_ij0p])-*FAC1*(P[p_ijp0]-P[p_ijpm]);
V[v_ij00]=V[v_ij00]+*OMEGA*Vresid[v_ij00];
}
if (blockIdx.y==(dev_N-1) && blockIdx.x>0 && blockIdx.x<(dev_N-2)&& EvenOrOdd==RorB)
{
Vresid[v_ij00]=0.0;
V[v_ij00]=0.0;
}
//Update Outlet
if (blockIdx.y==0 && blockIdx.x==(dev_N-2)&& EvenOrOdd==RorB)
{
Vresid[v_ij00]= 0.0;
V[v_ij00]=0.0;
}
if (blockIdx.y>0 && blockIdx.y<(dev_N-1) && blockIdx.x==(dev_N-2)&& EvenOrOdd==RorB)
{
Vresid[v_ij00]=(V[v_ijm0]-V[v_ij00])+(V[v_ij0m]-2.0*V[v_ij00]+V[v_ij0p])-*FAC1*(P[p_ijp0]-P[p_ijpm]);
V[v_ij00]=V[v_ij00]+*OMEGA*Vresid[v_ij00];
}
if (blockIdx.y==(dev_N-1) && blockIdx.x==(dev_N-2)&& EvenOrOdd==RorB)
{
Vresid[v_ij00]= 0.0;
V[v_ij00]=0.0;
}
__syncthreads();
}
__global__ void update_p(double* U, double* V, double* P, double* Presid, double* FAC1, double* OMEGA, double* Pdiff, int RorB)
{
int EvenOrOdd=((int) (blockIdx.x+blockIdx.y)%2);
int u_ij00 = blockIdx.x + blockIdx.y * (gridDim.x-1);
int u_ijm0 = (blockIdx.x + gridDim.x - 2)%(gridDim.x-1) + blockIdx.y * (gridDim.x-1); //up for u
int v_ijm0 = (blockIdx.x + gridDim.x - 3)%(gridDim.x-2) + blockIdx.y * (gridDim.x-2); //up for v
int v_ijmp = (blockIdx.x + gridDim.x - 3)%(gridDim.x-2) + ((blockIdx.y + 1)%gridDim.y) * (gridDim.x-2);
int p_ij00 = blockIdx.x + blockIdx.y * (gridDim.x);
int p_ijp0 = (blockIdx.x + 1)%(gridDim.x) + blockIdx.y * (gridDim.x); //down for p
int p_ijm0 = (blockIdx.x + gridDim.x-1)%(gridDim.x) + blockIdx.y * (gridDim.x); //up for p
//Update the boundary with the right pressure drop
if (blockIdx.y<(dev_N-1) && blockIdx.x==0 && EvenOrOdd==RorB)
{
Presid[p_ij00]=2.0*(*Pdiff)-P[p_ijp0]-P[p_ij00];
P[p_ij00]=2.0*(*Pdiff)-P[p_ijp0];
}
//Update interior nodes
if (blockIdx.y<(dev_N-1) && blockIdx.x>0 && blockIdx.x<(dev_N) && EvenOrOdd==RorB)
{
Presid[p_ij00]=-(U[u_ij00]-U[u_ijm0])-(V[v_ijmp]-V[v_ijm0]);
P[p_ij00]=P[p_ij00]+*OMEGA*Presid[p_ij00];
}
//Update boundary conditions
if (blockIdx.y<(dev_N-1) && blockIdx.x==(dev_N) && EvenOrOdd==RorB)
{
P[p_ij00]=-P[p_ijm0];
}
__syncthreads();
} | /*
Uses N blocks with N threads
SOR Stokes Flow with no slip b.c. on top/bottom and no flux b.c. on left/right written by Dmitriy Kats
Inputs: N is the number of grid points in each direction,
mu is the viscosity
Pdiff is the pressure drop in the x direction
omega is the SOR factor
toltau is the tolerance of the residual
Outputs: The final velocities and pressure
*/
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include<math.h>
#include <time.h>
//Kernels to udpate u, v, and p
//The inputs also considers if it is a red or black point udpate
__global__ void update_u(double* U, double* Uresid, double* P, double* Presid, double* FAC1, double* OMEGA, int RedorBlack);
__global__ void update_v(double* V, double* Vresid, double* P, double* Presid, double* FAC1, double* OMEGA, int RedorBlack);
__global__ void update_p(double* U, double* V, double* P, double* Presid, double* FAC1, double* OMEGA, double* Pdiff, int RedorBlack);
__device__ static int dev_N;
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
int main (int argc, char * argv[]){
// Choose the GPU card
hipDeviceProp_t prop;
int dev;
memset(&prop, 0, sizeof(hipDeviceProp_t));
prop.multiProcessorCount = 13;
hipChooseDevice(&dev, &prop);
hipSetDevice(dev);
// Create the CUDA events that will be used for timing the kernel function
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// Click, the timer has started running
hipEventRecord(start, 0);
int N;
double mu, pdiff, omega, toltau;
N=atoi(argv[1]);
mu=atof(argv[2]);
pdiff=atof(argv[3]);
omega=atof(argv[4]);
toltau=atof(argv[5]);
double dx=1.0/((double)N-1.0);
double fac1=dx/mu; //precompute the factor
double residABSMAX = 99.0;
int numberOfIterations=0;
double* dev_fac1;
double* dev_omega;
double* dev_pdiff;
double *dev_u, *dev_uresid;
double *dev_v, *dev_vresid;
double *dev_p, *dev_presid;
//allocate memory for the velocities and pressure
double *u = (double*)malloc(N*(N-1)*sizeof(double));
double *uresid = (double*)malloc(N*(N-1)*sizeof(double));
double *v = (double*)malloc((N-1)*N*sizeof(double));
double *vresid = (double*)malloc((N-1)*N*sizeof(double));
double *p = (double*)malloc((N+1)*(N-1)*sizeof(double));
double *presid = (double*)malloc((N+1)*(N-1)*sizeof(double));
//allocate Cuda memory
hipMalloc((void**)&dev_fac1, sizeof(double));
hipMalloc((void**)&dev_omega, sizeof(double));
hipMalloc((void**)&dev_pdiff, sizeof(double));
hipMalloc((void**)&dev_u, N*(N-1)*sizeof(double));
hipMalloc((void**)&dev_uresid, N*(N-1)*sizeof(double));
hipMalloc((void**)&dev_v, (N-1)*N*sizeof(double));
hipMalloc((void**)&dev_vresid, (N-1)*N*sizeof(double));
hipMalloc((void**)&dev_p, (N+1)*(N-1)*sizeof(double));
hipMalloc((void**)&dev_presid, (N+1)*(N-1)*sizeof(double));
//Intialize to zero
int i, j;
for(i=0; i<N; i++)
{
for(j=0; j<N-1; j++)
{
u[i+j*N]=0.0;
uresid[i+j*N]=0.0;
}
}
for(i=0; i<N-1; i++)
{
for(j=0; j<N; j++)
{
v[i+j*(N-1)]=0.0;
vresid[i+j*(N-1)]=0.0;
}
}
for(i=0; i<N+1; i++)
{
for(j=0; j<N-1; j++)
{
p[i+j*(N+1)]=0.0;
presid[i+j*(N+1)]=0.0;
}
}
//Copy the values to the device
hipMemcpy(dev_u, u, N*(N-1)*sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(dev_uresid, uresid, N*(N-1)*sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(dev_v, v, (N-1)*N*sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(dev_vresid, vresid, (N-1)*N*sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(dev_p, p, (N+1)*(N-1)*sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(dev_presid, presid, (N+1)*(N-1)*sizeof(double), hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(dev_N), &N, sizeof(int));
hipMemcpy(dev_fac1, &fac1, sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(dev_omega, &omega, sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(dev_pdiff, &pdiff, sizeof(double), hipMemcpyHostToDevice);
dim3 meshDim(N,N); //This one will be for the velocities
dim3 meshDim2(N+1,N); //This one will be for the pressure
while(residABSMAX>=toltau)
{
residABSMAX=0.1*toltau;
//Solve in the next six lines
update_u<<<meshDim,1>>>(dev_u, dev_uresid, dev_p, dev_presid, dev_fac1, dev_omega, 0);
update_u<<<meshDim,1>>>(dev_u, dev_uresid, dev_p, dev_presid, dev_fac1, dev_omega, 1);
update_v<<<meshDim,1>>>(dev_v, dev_vresid, dev_p, dev_presid, dev_fac1, dev_omega, 0);
update_v<<<meshDim,1>>>(dev_v, dev_vresid, dev_p, dev_presid, dev_fac1, dev_omega, 1);
update_p<<<meshDim2,1>>>(dev_u, dev_v, dev_p, dev_presid, dev_fac1, dev_omega, dev_pdiff, 0);
update_p<<<meshDim2,1>>>(dev_u, dev_v, dev_p, dev_presid, dev_fac1, dev_omega, dev_pdiff, 1);
//This is slow but I ran out of time
//Copy the residuals to the host to find the max residual
hipMemcpy(uresid, dev_uresid, N*(N-1)*sizeof(double), hipMemcpyDeviceToHost);
hipMemcpy(vresid, dev_vresid, (N-1)*N*sizeof(double), hipMemcpyDeviceToHost);
hipMemcpy(presid, dev_presid, (N+1)*(N-1)*sizeof(double), hipMemcpyDeviceToHost);
for(i=0; i<N; i++)
{
for(j=0; j<N-1; j++)
{
if(fabs(uresid[i+j*N])>residABSMAX)
{
residABSMAX=fabs(uresid[i+j*N]);
}
}
}
for(i=0; i<N-1; i++)
{
for(j=0; j<N; j++)
{
if(fabs(vresid[i+j*(N-1)])>residABSMAX)
{
residABSMAX=fabs(vresid[i+j*(N-1)]);
}
}
}
for(i=0; i<N+1; i++)
{
for(j=0; j<N-1; j++)
{
if(fabs(presid[i+j*(N+1)])>residABSMAX)
{
residABSMAX=fabs(presid[i+j*(N+1)]);
}
}
}
//Check for errors
gpuErrchk(hipPeekAtLastError() );
gpuErrchk(hipDeviceSynchronize() );
numberOfIterations+=1;
if (numberOfIterations>10000)
{ //fail safe to save data and exit
hipMemcpy(u, dev_u, N*(N-1)*sizeof(double), hipMemcpyDeviceToHost);
hipMemcpy(v, dev_v, (N-1)*N*sizeof(double), hipMemcpyDeviceToHost);
hipMemcpy(p, dev_p, (N+1)*(N-1)*sizeof(double), hipMemcpyDeviceToHost);
printf("Reached fail safe. The max residual is %10e. The number of iterations is %i\n", residABSMAX, numberOfIterations);
FILE *fpu = fopen("StokesU.out", "wb");
fwrite(u, sizeof(double), N*(N-1), fpu);
fclose (fpu);
FILE *fpv = fopen("StokesV.out", "wb");
fwrite(v, sizeof(double), (N-1)*N, fpv);
fclose (fpv);
FILE *fpP = fopen("StokesP.out", "wb");
fwrite(p, sizeof(double), (N+1)*(N-1), fpP);
fclose (fpP);
hipFree(dev_u);
hipFree(dev_uresid);
hipFree(dev_v);
hipFree(dev_vresid);
hipFree(dev_p);
hipFree(dev_presid);
hipFree(dev_fac1);
hipFree(dev_omega);
hipFree(dev_pdiff);
free(u);
free(uresid);
free(v);
free(vresid);
free(p);
free(presid);
return 0;
}
}
hipMemcpy(u, dev_u, N*(N-1)*sizeof(double), hipMemcpyDeviceToHost);
hipMemcpy(v, dev_v, (N-1)*N*sizeof(double), hipMemcpyDeviceToHost);
hipMemcpy(p, dev_p, (N+1)*(N-1)*sizeof(double), hipMemcpyDeviceToHost);
//export the data
FILE *fpu = fopen("StokesU.out", "wb");
fwrite(u, sizeof(double), N*(N-1), fpu);
fclose (fpu);
FILE *fpv = fopen("StokesV.out", "wb");
fwrite(v, sizeof(double), (N-1)*N, fpv);
fclose (fpv);
FILE *fpP = fopen("StokesP.out", "wb");
fwrite(p, sizeof(double), (N+1)*(N-1), fpP);
fclose (fpP);
//stop the timer
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
// The elapsed time is computed by taking the difference between start and stop
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
printf("N:%i omega:%f\n", N, omega);
printf("The max residual is %10e and the number of iterations is %i\n", residABSMAX, numberOfIterations);
printf("Time: %gms\n", elapsedTime);
//clean up timer
hipEventDestroy(start);
hipEventDestroy(stop);
hipFree(dev_u);
hipFree(dev_uresid);
hipFree(dev_v);
hipFree(dev_vresid);
hipFree(dev_p);
hipFree(dev_presid);
hipFree(dev_fac1);
hipFree(dev_omega);
free(u);
free(uresid);
free(v);
free(vresid);
free(p);
free(presid);
return 0;
}
__global__ void update_u(double* U, double* Uresid, double* P, double* Presid, double* FAC1, double* OMEGA, int RorB)
{
int EvenOrOdd=(blockIdx.x+blockIdx.y)%2;
int u_ij00 = blockIdx.x + blockIdx.y * gridDim.x;
int u_ijp0 = (blockIdx.x + 1)%gridDim.x + blockIdx.y * gridDim.x; //down for u
int u_ijm0 = (blockIdx.x + gridDim.x - 1)%gridDim.x + blockIdx.y * gridDim.x; //up for u
int u_ij0p = blockIdx.x + ((blockIdx.y + 1)%gridDim.y) * gridDim.x; //east for u
int u_ij0m = blockIdx.x + ((blockIdx.y + gridDim.y - 1)%gridDim.y) * gridDim.x; //west for u
int p_ij00 = blockIdx.x + blockIdx.y * (gridDim.x+1);
int p_ijp0 = (blockIdx.x + 1)%(gridDim.x+1) + blockIdx.y * (gridDim.x+1); //down for p
//int p_ijm0 = (blockIdx.x + gridDim.x)%(gridDim.x+1) + blockIdx.y * (gridDim.x+1); //up for p
//int p_ij0p = blockIdx.x + ((blockIdx.y + 1)%gridDim.y) *(gridDim.x+1); //east for p
//int p_ij0m = blockIdx.x + ((blockIdx.y + gridDim.y - 1)%gridDim.y) * (gridDim.x+1); //west for p
//UPDATE INLET
if (blockIdx.y==0 && blockIdx.x==0 && EvenOrOdd==RorB)
{ //Corner point
Uresid[u_ij00]= (-U[u_ij00]+ U[u_ijp0])+(-3.0*U[u_ij00]+U[u_ij0p])-*FAC1*(P[p_ijp0]-P[p_ij00]);
U[u_ij00]=U[u_ij00]+*OMEGA*Uresid[u_ij00];
}
if (blockIdx.y>0 && blockIdx.y<(dev_N-2) && blockIdx.x==0 && EvenOrOdd==RorB)
{ //Middle points
Uresid[u_ij00]=(-U[u_ij00]+ U[u_ijp0])+(U[u_ij0m]-2.0*U[u_ij00]+U[u_ij0p])-*FAC1*(P[p_ijp0]-P[p_ij00]);
U[u_ij00]=U[u_ij00]+*OMEGA*Uresid[u_ij00];
}
if (blockIdx.y==(dev_N-2) && blockIdx.x==0 && EvenOrOdd==RorB)
{ //Corner point
Uresid[u_ij00]= (-U[u_ij00]+ U[u_ijp0])+(U[u_ij0m]-3.0*U[u_ij00])-*FAC1*(P[p_ijp0]-P[p_ij00]);
U[u_ij00]=U[u_ij00]+*OMEGA*Uresid[u_ij00];
}
//UPDATE BULK
if (blockIdx.y==0 && blockIdx.x>0 && blockIdx.x<(dev_N-1)&& EvenOrOdd==RorB)
{ // boundary condition
Uresid[u_ij00]= (U[u_ijm0]-2.0*U[u_ij00]+ U[u_ijp0])+(-3.0*U[u_ij00]+U[u_ij0p])-*FAC1*(P[p_ijp0]-P[p_ij00]);
U[u_ij00]=U[u_ij00]+*OMEGA*Uresid[u_ij00];
}
if (blockIdx.y>0 && blockIdx.y<(dev_N-2) && blockIdx.x>0 && blockIdx.x<(dev_N-1)&& EvenOrOdd==RorB)
{ //interior
Uresid[u_ij00]= (U[u_ijm0]-2.0*U[u_ij00]+ U[u_ijp0])+(U[u_ij0m]-2.0*U[u_ij00]+U[u_ij0p])-*FAC1*(P[p_ijp0]-P[p_ij00]);
U[u_ij00]=U[u_ij00]+*OMEGA*Uresid[u_ij00];
}
if (blockIdx.y==(dev_N-2) && blockIdx.x>0 && blockIdx.x<(dev_N-1)&& EvenOrOdd==RorB)
{ //boundary condition
Uresid[u_ij00]= (U[u_ijm0]-2.0*U[u_ij00]+ U[u_ijp0])+(U[u_ij0m]-3.0*U[u_ij00])-*FAC1*(P[p_ijp0]-P[p_ij00]);
U[u_ij00]=U[u_ij00]+*OMEGA*Uresid[u_ij00];
}
//Update Outlet
if (blockIdx.y==0 && blockIdx.x==(dev_N-1)&& EvenOrOdd==RorB)
{ //boundary condition
Uresid[u_ij00]= (U[u_ijm0]-U[u_ij00])+(-3.0*U[u_ij00]+U[u_ij0p])-*FAC1*(P[p_ijp0]-P[p_ij00]);
U[u_ij00]=U[u_ij00]+*OMEGA*Uresid[u_ij00];
}
if (blockIdx.y>0 && blockIdx.y<(dev_N-2) && blockIdx.x==(dev_N-1)&& EvenOrOdd==RorB)
{ //middle points on outlet
Uresid[u_ij00]= (U[u_ijm0]-U[u_ij00])+(U[u_ij0m]-2.0*U[u_ij00]+U[u_ij0p])-*FAC1*(P[p_ijp0]-P[p_ij00]);
U[u_ij00]=U[u_ij00]+*OMEGA*Uresid[u_ij00];
}
if (blockIdx.y==(dev_N-2) && blockIdx.x==(dev_N-1)&& EvenOrOdd==RorB)
{ //boundary node
Uresid[u_ij00]= (U[u_ijm0]-U[u_ij00])+(U[u_ij0m]-3.0*U[u_ij00])-*FAC1*(P[p_ijp0]-P[p_ij00]);
U[u_ij00]=U[u_ij00]+*OMEGA*Uresid[u_ij00];
}
__syncthreads();
}
__global__ void update_v(double* V, double* Vresid, double* P, double* Presid, double* FAC1, double* OMEGA, int RorB)
{
int EvenOrOdd=(blockIdx.x+blockIdx.y)%2;
int v_ij00 = blockIdx.x + blockIdx.y * (gridDim.x-1);
int v_ijp0 = (blockIdx.x + 1)%(gridDim.x-1) + blockIdx.y * (gridDim.x-1); //down for v
int v_ijm0 = (blockIdx.x + gridDim.x - 2)%(gridDim.x-1) + blockIdx.y * (gridDim.x-1); //up for v
int v_ij0p = blockIdx.x + ((blockIdx.y + 1)%gridDim.y) * (gridDim.x-1); //east for v
int v_ij0m = blockIdx.x + ((blockIdx.y + gridDim.y - 1)%gridDim.y) * (gridDim.x-1); //west for v
//int p_ij00 = blockIdx.x + blockIdx.y * (gridDim.x+1);
int p_ijp0 = (blockIdx.x + 1)%(gridDim.x+1) + blockIdx.y * (gridDim.x+1); //down for p
//int p_ijm0 = (blockIdx.x + gridDim.x)%(gridDim.x+1) + blockIdx.y * (gridDim.x+1); //up for p
//int p_ij0p = blockIdx.x + ((blockIdx.y + 1)%gridDim.y) *(gridDim.x+1); //east for p
//int p_ij0m = blockIdx.x + ((blockIdx.y + gridDim.y - 1)%gridDim.y) * (gridDim.x+1); //west for p
int p_ijpm = (blockIdx.x + 1)%(gridDim.x+1) + ((blockIdx.y + gridDim.y - 1)%gridDim.y) * (gridDim.x+1); //sw for p
//Update inlet similarly to above
if (blockIdx.y==0 && blockIdx.x==0 && EvenOrOdd==RorB)
{ //no velocity boundary condition
Vresid[v_ij00]= 0.0;
V[v_ij00]=0.0;
}
if (blockIdx.y>0 && blockIdx.y<(dev_N-1) && blockIdx.x==0 && EvenOrOdd==RorB)
{
Vresid[v_ij00]=(-V[v_ij00]+ V[v_ijp0])+(V[v_ij0m]-2.0*V[v_ij00]+V[v_ij0p])-*FAC1*(P[p_ijp0]-P[p_ijpm]);
V[v_ij00]=V[v_ij00]+*OMEGA*Vresid[v_ij00];
}
if (blockIdx.y==(dev_N-1) && blockIdx.x==0 && EvenOrOdd==0)
{
Vresid[v_ij00]= 0.0;
V[v_ij00]=0.0;
}
//Update Bulk similarly to above
if (blockIdx.y==0 && blockIdx.x>0 && blockIdx.x<(dev_N-2)&& EvenOrOdd==RorB)
{
Vresid[v_ij00]= 0.0;
V[v_ij00]=0.0;
}
if (blockIdx.y>0 && blockIdx.y<(dev_N-1) && blockIdx.x>0 && blockIdx.x<(dev_N-2)&& EvenOrOdd==RorB)
{
Vresid[v_ij00]=(V[v_ijm0]-2.0*V[v_ij00]+ V[v_ijp0])+(V[v_ij0m]-2.0*V[v_ij00]+V[v_ij0p])-*FAC1*(P[p_ijp0]-P[p_ijpm]);
V[v_ij00]=V[v_ij00]+*OMEGA*Vresid[v_ij00];
}
if (blockIdx.y==(dev_N-1) && blockIdx.x>0 && blockIdx.x<(dev_N-2)&& EvenOrOdd==RorB)
{
Vresid[v_ij00]=0.0;
V[v_ij00]=0.0;
}
//Update Outlet
if (blockIdx.y==0 && blockIdx.x==(dev_N-2)&& EvenOrOdd==RorB)
{
Vresid[v_ij00]= 0.0;
V[v_ij00]=0.0;
}
if (blockIdx.y>0 && blockIdx.y<(dev_N-1) && blockIdx.x==(dev_N-2)&& EvenOrOdd==RorB)
{
Vresid[v_ij00]=(V[v_ijm0]-V[v_ij00])+(V[v_ij0m]-2.0*V[v_ij00]+V[v_ij0p])-*FAC1*(P[p_ijp0]-P[p_ijpm]);
V[v_ij00]=V[v_ij00]+*OMEGA*Vresid[v_ij00];
}
if (blockIdx.y==(dev_N-1) && blockIdx.x==(dev_N-2)&& EvenOrOdd==RorB)
{
Vresid[v_ij00]= 0.0;
V[v_ij00]=0.0;
}
__syncthreads();
}
__global__ void update_p(double* U, double* V, double* P, double* Presid, double* FAC1, double* OMEGA, double* Pdiff, int RorB)
{
int EvenOrOdd=((int) (blockIdx.x+blockIdx.y)%2);
int u_ij00 = blockIdx.x + blockIdx.y * (gridDim.x-1);
int u_ijm0 = (blockIdx.x + gridDim.x - 2)%(gridDim.x-1) + blockIdx.y * (gridDim.x-1); //up for u
int v_ijm0 = (blockIdx.x + gridDim.x - 3)%(gridDim.x-2) + blockIdx.y * (gridDim.x-2); //up for v
int v_ijmp = (blockIdx.x + gridDim.x - 3)%(gridDim.x-2) + ((blockIdx.y + 1)%gridDim.y) * (gridDim.x-2);
int p_ij00 = blockIdx.x + blockIdx.y * (gridDim.x);
int p_ijp0 = (blockIdx.x + 1)%(gridDim.x) + blockIdx.y * (gridDim.x); //down for p
int p_ijm0 = (blockIdx.x + gridDim.x-1)%(gridDim.x) + blockIdx.y * (gridDim.x); //up for p
//Update the boundary with the right pressure drop
if (blockIdx.y<(dev_N-1) && blockIdx.x==0 && EvenOrOdd==RorB)
{
Presid[p_ij00]=2.0*(*Pdiff)-P[p_ijp0]-P[p_ij00];
P[p_ij00]=2.0*(*Pdiff)-P[p_ijp0];
}
//Update interior nodes
if (blockIdx.y<(dev_N-1) && blockIdx.x>0 && blockIdx.x<(dev_N) && EvenOrOdd==RorB)
{
Presid[p_ij00]=-(U[u_ij00]-U[u_ijm0])-(V[v_ijmp]-V[v_ijm0]);
P[p_ij00]=P[p_ij00]+*OMEGA*Presid[p_ij00];
}
//Update boundary conditions
if (blockIdx.y<(dev_N-1) && blockIdx.x==(dev_N) && EvenOrOdd==RorB)
{
P[p_ij00]=-P[p_ijm0];
}
__syncthreads();
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
// filename: eeTanh.cu
// a simple CUDA kernel to square the elements of a matrix
extern "C" // ensure function name to be exactly "eeTanh"
{
}
__global__ void tanhGradient(int N, int M, float *z, float *tanh_grad_z) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int index = j*N + i;
float c1 = __fdividef(2.0, 3.0);
if (i < N && j < M) {
float el = __fmul_rn(z[index], c1);
if (el > 4.97) {
z[index] = 1.7159;
tanh_grad_z[index] = 0.0;
}
else if(el < -4.97) {
z[index] = -1.7159;
tanh_grad_z[index] = 0.0;
}
else {
float x2 = __fmul_rn(el, el);
float a = __fmul_rn(el, __fmaf_rn(x2, __fmaf_rn(x2, __fadd_rn(378.0, x2), 17235.0), 135135.0));
float b = __fmaf_rn(x2, __fmaf_rn(x2, __fmaf_rn(x2, 28.0, 3150.0), 62370.0), 135135.0);
float tanh = __fdividef(a, b);
z[index] = __fmul_rn(1.7159, tanh);
tanh_grad_z[index] = __fmul_rn(1.7159, __fmul_rn(__fmaf_rn(-tanh, tanh, 1.0), c1));
}
}
} | code for sm_80
Function : _Z12tanhGradientiiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x164], PT ; /* 0x0000590003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x160], P0 ; /* 0x0000580000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R3, c[0x0][0x160], R0 ; /* 0x0000580003007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0205 */
/*00e0*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1900 */
/*00f0*/ FMUL R8, R4, 0.6666666865348815918 ; /* 0x3f2aaaab04087820 */
/* 0x004fe40000400000 */
/*0100*/ IMAD.WIDE R4, R0, R5, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fe400078e0205 */
/*0110*/ F2F.F64.F32 R6, R8 ; /* 0x0000000800067310 */
/* 0x000e240000201800 */
/*0120*/ DSETP.GT.AND P0, PT, R6, c[0x2][0x0], PT ; /* 0x008000000600762a */
/* 0x001e1c0003f04000 */
/*0130*/ @P0 BRA 0x2f0 ; /* 0x000001b000000947 */
/* 0x001fea0003800000 */
/*0140*/ DSETP.GEU.AND P0, PT, R6, c[0x2][0x8], PT ; /* 0x008002000600762a */
/* 0x000e1c0003f0e000 */
/*0150*/ @!P0 BRA 0x2b0 ; /* 0x0000015000008947 */
/* 0x001fea0003800000 */
/*0160*/ MOV R7, 0x41e00000 ; /* 0x41e0000000077802 */
/* 0x000fe20000000f00 */
/*0170*/ FMUL R0, R8, R8 ; /* 0x0000000808007220 */
/* 0x000fc80000400000 */
/*0180*/ FFMA R7, R0, R7, 3150 ; /* 0x4544e00000077423 */
/* 0x000fc80000000007 */
/*0190*/ FFMA R7, R0, R7, 62370 ; /* 0x4773a20000077423 */
/* 0x000fc80000000007 */
/*01a0*/ FFMA R6, R0.reuse, R7, 135135 ; /* 0x4803f7c000067423 */
/* 0x040fe40000000007 */
/*01b0*/ FADD R7, R0, 378 ; /* 0x43bd000000077421 */
/* 0x000fc60000000000 */
/*01c0*/ FSETP.GEU.AND P0, PT, |R6|, 1.175494350822287508e-38, PT ; /* 0x008000000600780b */
/* 0x000fe20003f0e200 */
/*01d0*/ FFMA R7, R0, R7, 17235 ; /* 0x4686a60000077423 */
/* 0x000fc80000000007 */
/*01e0*/ FFMA R7, R0, R7, 135135 ; /* 0x4803f7c000077423 */
/* 0x000fc80000000007 */
/*01f0*/ FMUL R7, R8, R7 ; /* 0x0000000708077220 */
/* 0x000fc80000400000 */
/*0200*/ @!P0 FMUL R6, R6, 16777216 ; /* 0x4b80000006068820 */
/* 0x000fe40000400000 */
/*0210*/ @!P0 FMUL R7, R7, 16777216 ; /* 0x4b80000007078820 */
/* 0x000fc80000400000 */
/*0220*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x000e240000001000 */
/*0230*/ FMUL R7, R6, R7 ; /* 0x0000000706077220 */
/* 0x001fc80000400000 */
/*0240*/ FFMA R0, -R7.reuse, R7, 1 ; /* 0x3f80000007007423 */
/* 0x040fe40000000107 */
/*0250*/ FMUL R7, R7, 1.7158999443054199219 ; /* 0x3fdba29c07077820 */
/* 0x000fe40000400000 */
/*0260*/ FMUL R0, R0, 0.6666666865348815918 ; /* 0x3f2aaaab00007820 */
/* 0x000fc60000400000 */
/*0270*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0280*/ FMUL R9, R0, 1.7158999443054199219 ; /* 0x3fdba29c00097820 */
/* 0x000fca0000400000 */
/*0290*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe2000c101904 */
/*02a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02b0*/ MOV R7, 0xbfdba29c ; /* 0xbfdba29c00077802 */
/* 0x000fca0000000f00 */
/*02c0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*02d0*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe2000c101904 */
/*02e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02f0*/ MOV R7, 0x3fdba29c ; /* 0x3fdba29c00077802 */
/* 0x000fca0000000f00 */
/*0300*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*0310*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe2000c101904 */
/*0320*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0330*/ BRA 0x330; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
// filename: eeTanh.cu
// a simple CUDA kernel to square the elements of a matrix
extern "C" // ensure function name to be exactly "eeTanh"
{
}
__global__ void tanhGradient(int N, int M, float *z, float *tanh_grad_z) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int index = j*N + i;
float c1 = __fdividef(2.0, 3.0);
if (i < N && j < M) {
float el = __fmul_rn(z[index], c1);
if (el > 4.97) {
z[index] = 1.7159;
tanh_grad_z[index] = 0.0;
}
else if(el < -4.97) {
z[index] = -1.7159;
tanh_grad_z[index] = 0.0;
}
else {
float x2 = __fmul_rn(el, el);
float a = __fmul_rn(el, __fmaf_rn(x2, __fmaf_rn(x2, __fadd_rn(378.0, x2), 17235.0), 135135.0));
float b = __fmaf_rn(x2, __fmaf_rn(x2, __fmaf_rn(x2, 28.0, 3150.0), 62370.0), 135135.0);
float tanh = __fdividef(a, b);
z[index] = __fmul_rn(1.7159, tanh);
tanh_grad_z[index] = __fmul_rn(1.7159, __fmul_rn(__fmaf_rn(-tanh, tanh, 1.0), c1));
}
}
} | .file "tmpxft_000776fb_00000000-6_tanhGradient.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z12tanhGradientiiPfS_iiPfS_
.type _Z36__device_stub__Z12tanhGradientiiPfS_iiPfS_, @function
_Z36__device_stub__Z12tanhGradientiiPfS_iiPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12tanhGradientiiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z12tanhGradientiiPfS_iiPfS_, .-_Z36__device_stub__Z12tanhGradientiiPfS_iiPfS_
.globl _Z12tanhGradientiiPfS_
.type _Z12tanhGradientiiPfS_, @function
_Z12tanhGradientiiPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12tanhGradientiiPfS_iiPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12tanhGradientiiPfS_, .-_Z12tanhGradientiiPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12tanhGradientiiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12tanhGradientiiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
// filename: eeTanh.cu
// a simple CUDA kernel to square the elements of a matrix
extern "C" // ensure function name to be exactly "eeTanh"
{
}
__global__ void tanhGradient(int N, int M, float *z, float *tanh_grad_z) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int index = j*N + i;
float c1 = __fdividef(2.0, 3.0);
if (i < N && j < M) {
float el = __fmul_rn(z[index], c1);
if (el > 4.97) {
z[index] = 1.7159;
tanh_grad_z[index] = 0.0;
}
else if(el < -4.97) {
z[index] = -1.7159;
tanh_grad_z[index] = 0.0;
}
else {
float x2 = __fmul_rn(el, el);
float a = __fmul_rn(el, __fmaf_rn(x2, __fmaf_rn(x2, __fadd_rn(378.0, x2), 17235.0), 135135.0));
float b = __fmaf_rn(x2, __fmaf_rn(x2, __fmaf_rn(x2, 28.0, 3150.0), 62370.0), 135135.0);
float tanh = __fdividef(a, b);
z[index] = __fmul_rn(1.7159, tanh);
tanh_grad_z[index] = __fmul_rn(1.7159, __fmul_rn(__fmaf_rn(-tanh, tanh, 1.0), c1));
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
// filename: eeTanh.cu
// a simple CUDA kernel to square the elements of a matrix
extern "C" // ensure function name to be exactly "eeTanh"
{
}
__global__ void tanhGradient(int N, int M, float *z, float *tanh_grad_z) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int index = j*N + i;
float c1 = __fdividef(2.0, 3.0);
if (i < N && j < M) {
float el = __fmul_rn(z[index], c1);
if (el > 4.97) {
z[index] = 1.7159;
tanh_grad_z[index] = 0.0;
}
else if(el < -4.97) {
z[index] = -1.7159;
tanh_grad_z[index] = 0.0;
}
else {
float x2 = __fmul_rn(el, el);
float a = __fmul_rn(el, __fmaf_rn(x2, __fmaf_rn(x2, __fadd_rn(378.0, x2), 17235.0), 135135.0));
float b = __fmaf_rn(x2, __fmaf_rn(x2, __fmaf_rn(x2, 28.0, 3150.0), 62370.0), 135135.0);
float tanh = __fdividef(a, b);
z[index] = __fmul_rn(1.7159, tanh);
tanh_grad_z[index] = __fmul_rn(1.7159, __fmul_rn(__fmaf_rn(-tanh, tanh, 1.0), c1));
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// filename: eeTanh.cu
// a simple CUDA kernel to square the elements of a matrix
extern "C" // ensure function name to be exactly "eeTanh"
{
}
__global__ void tanhGradient(int N, int M, float *z, float *tanh_grad_z) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int index = j*N + i;
float c1 = __fdividef(2.0, 3.0);
if (i < N && j < M) {
float el = __fmul_rn(z[index], c1);
if (el > 4.97) {
z[index] = 1.7159;
tanh_grad_z[index] = 0.0;
}
else if(el < -4.97) {
z[index] = -1.7159;
tanh_grad_z[index] = 0.0;
}
else {
float x2 = __fmul_rn(el, el);
float a = __fmul_rn(el, __fmaf_rn(x2, __fmaf_rn(x2, __fadd_rn(378.0, x2), 17235.0), 135135.0));
float b = __fmaf_rn(x2, __fmaf_rn(x2, __fmaf_rn(x2, 28.0, 3150.0), 62370.0), 135135.0);
float tanh = __fdividef(a, b);
z[index] = __fmul_rn(1.7159, tanh);
tanh_grad_z[index] = __fmul_rn(1.7159, __fmul_rn(__fmaf_rn(-tanh, tanh, 1.0), c1));
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12tanhGradientiiPfS_
.globl _Z12tanhGradientiiPfS_
.p2align 8
.type _Z12tanhGradientiiPfS_,@function
_Z12tanhGradientiiPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v2
v_cmp_gt_i32_e64 s2, s5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_10
s_load_b64 s[2:3], s[0:1], 0x8
v_mad_u64_u32 v[0:1], null, v3, s4, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_mov_b32 s3, 0x4013e147
s_mov_b32 s2, 0xae147ae1
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v7, 0x3f2aaaab, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[4:5], v7
v_cmp_nlt_f64_e32 vcc_lo, s[2:3], v[4:5]
s_and_saveexec_b32 s3, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s4, exec_lo, s3
s_cbranch_execz .LBB0_7
s_mov_b32 s3, 0xc013e147
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ngt_f64_e32 vcc_lo, s[2:3], v[4:5]
s_and_saveexec_b32 s2, vcc_lo
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_4
v_mul_f32_e32 v4, v7, v7
v_fmaak_f32 v5, v7, v7, 0x43bd0000
s_mov_b32 s3, 0x41e00000
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v5, v4, v5, 0x4686a600
v_fmaak_f32 v5, v4, v5, 0x4803f7c0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmaak_f32 v6, s3, v4, 0x4544e000 :: v_dual_mul_f32 v5, v7, v5
v_fmaak_f32 v6, v4, v6, 0x4773a200
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v4, v4, v6, 0x4803f7c0
v_div_scale_f32 v6, null, v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v7, v6
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v6, v7, 1.0
v_fmac_f32_e32 v7, v8, v7
v_div_scale_f32 v8, vcc_lo, v5, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v9, v8, v7
v_fma_f32 v10, -v6, v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v9, v10, v7
v_fma_f32 v6, -v6, v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v6, v6, v7, v9
v_div_fixup_f32 v4, v6, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v5, -v4, v4, 1.0
v_mul_f32_e32 v4, 0x3fdba29c, v4
v_mul_f32_e32 v5, 0x3f2aaaab, v5
global_store_b32 v[2:3], v4, off
v_mul_f32_e32 v6, 0x3fdba29c, v5
.LBB0_4:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v4, 0xbfdba29c
v_mov_b32_e32 v6, 0
global_store_b32 v[2:3], v4, off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_7:
s_and_not1_saveexec_b32 s2, s4
s_cbranch_execz .LBB0_9
v_mov_b32_e32 v4, 0x3fdba29c
v_mov_b32_e32 v6, 0
global_store_b32 v[2:3], v4, off
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12tanhGradientiiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12tanhGradientiiPfS_, .Lfunc_end0-_Z12tanhGradientiiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12tanhGradientiiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12tanhGradientiiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// filename: eeTanh.cu
// a simple CUDA kernel to square the elements of a matrix
extern "C" // ensure function name to be exactly "eeTanh"
{
}
__global__ void tanhGradient(int N, int M, float *z, float *tanh_grad_z) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int index = j*N + i;
float c1 = __fdividef(2.0, 3.0);
if (i < N && j < M) {
float el = __fmul_rn(z[index], c1);
if (el > 4.97) {
z[index] = 1.7159;
tanh_grad_z[index] = 0.0;
}
else if(el < -4.97) {
z[index] = -1.7159;
tanh_grad_z[index] = 0.0;
}
else {
float x2 = __fmul_rn(el, el);
float a = __fmul_rn(el, __fmaf_rn(x2, __fmaf_rn(x2, __fadd_rn(378.0, x2), 17235.0), 135135.0));
float b = __fmaf_rn(x2, __fmaf_rn(x2, __fmaf_rn(x2, 28.0, 3150.0), 62370.0), 135135.0);
float tanh = __fdividef(a, b);
z[index] = __fmul_rn(1.7159, tanh);
tanh_grad_z[index] = __fmul_rn(1.7159, __fmul_rn(__fmaf_rn(-tanh, tanh, 1.0), c1));
}
}
} | .text
.file "tanhGradient.hip"
.globl _Z27__device_stub__tanhGradientiiPfS_ # -- Begin function _Z27__device_stub__tanhGradientiiPfS_
.p2align 4, 0x90
.type _Z27__device_stub__tanhGradientiiPfS_,@function
_Z27__device_stub__tanhGradientiiPfS_: # @_Z27__device_stub__tanhGradientiiPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12tanhGradientiiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__tanhGradientiiPfS_, .Lfunc_end0-_Z27__device_stub__tanhGradientiiPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12tanhGradientiiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12tanhGradientiiPfS_,@object # @_Z12tanhGradientiiPfS_
.section .rodata,"a",@progbits
.globl _Z12tanhGradientiiPfS_
.p2align 3, 0x0
_Z12tanhGradientiiPfS_:
.quad _Z27__device_stub__tanhGradientiiPfS_
.size _Z12tanhGradientiiPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12tanhGradientiiPfS_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__tanhGradientiiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12tanhGradientiiPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12tanhGradientiiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x164], PT ; /* 0x0000590003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x160], P0 ; /* 0x0000580000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R3, c[0x0][0x160], R0 ; /* 0x0000580003007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0205 */
/*00e0*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1900 */
/*00f0*/ FMUL R8, R4, 0.6666666865348815918 ; /* 0x3f2aaaab04087820 */
/* 0x004fe40000400000 */
/*0100*/ IMAD.WIDE R4, R0, R5, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fe400078e0205 */
/*0110*/ F2F.F64.F32 R6, R8 ; /* 0x0000000800067310 */
/* 0x000e240000201800 */
/*0120*/ DSETP.GT.AND P0, PT, R6, c[0x2][0x0], PT ; /* 0x008000000600762a */
/* 0x001e1c0003f04000 */
/*0130*/ @P0 BRA 0x2f0 ; /* 0x000001b000000947 */
/* 0x001fea0003800000 */
/*0140*/ DSETP.GEU.AND P0, PT, R6, c[0x2][0x8], PT ; /* 0x008002000600762a */
/* 0x000e1c0003f0e000 */
/*0150*/ @!P0 BRA 0x2b0 ; /* 0x0000015000008947 */
/* 0x001fea0003800000 */
/*0160*/ MOV R7, 0x41e00000 ; /* 0x41e0000000077802 */
/* 0x000fe20000000f00 */
/*0170*/ FMUL R0, R8, R8 ; /* 0x0000000808007220 */
/* 0x000fc80000400000 */
/*0180*/ FFMA R7, R0, R7, 3150 ; /* 0x4544e00000077423 */
/* 0x000fc80000000007 */
/*0190*/ FFMA R7, R0, R7, 62370 ; /* 0x4773a20000077423 */
/* 0x000fc80000000007 */
/*01a0*/ FFMA R6, R0.reuse, R7, 135135 ; /* 0x4803f7c000067423 */
/* 0x040fe40000000007 */
/*01b0*/ FADD R7, R0, 378 ; /* 0x43bd000000077421 */
/* 0x000fc60000000000 */
/*01c0*/ FSETP.GEU.AND P0, PT, |R6|, 1.175494350822287508e-38, PT ; /* 0x008000000600780b */
/* 0x000fe20003f0e200 */
/*01d0*/ FFMA R7, R0, R7, 17235 ; /* 0x4686a60000077423 */
/* 0x000fc80000000007 */
/*01e0*/ FFMA R7, R0, R7, 135135 ; /* 0x4803f7c000077423 */
/* 0x000fc80000000007 */
/*01f0*/ FMUL R7, R8, R7 ; /* 0x0000000708077220 */
/* 0x000fc80000400000 */
/*0200*/ @!P0 FMUL R6, R6, 16777216 ; /* 0x4b80000006068820 */
/* 0x000fe40000400000 */
/*0210*/ @!P0 FMUL R7, R7, 16777216 ; /* 0x4b80000007078820 */
/* 0x000fc80000400000 */
/*0220*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x000e240000001000 */
/*0230*/ FMUL R7, R6, R7 ; /* 0x0000000706077220 */
/* 0x001fc80000400000 */
/*0240*/ FFMA R0, -R7.reuse, R7, 1 ; /* 0x3f80000007007423 */
/* 0x040fe40000000107 */
/*0250*/ FMUL R7, R7, 1.7158999443054199219 ; /* 0x3fdba29c07077820 */
/* 0x000fe40000400000 */
/*0260*/ FMUL R0, R0, 0.6666666865348815918 ; /* 0x3f2aaaab00007820 */
/* 0x000fc60000400000 */
/*0270*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0280*/ FMUL R9, R0, 1.7158999443054199219 ; /* 0x3fdba29c00097820 */
/* 0x000fca0000400000 */
/*0290*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe2000c101904 */
/*02a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02b0*/ MOV R7, 0xbfdba29c ; /* 0xbfdba29c00077802 */
/* 0x000fca0000000f00 */
/*02c0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*02d0*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe2000c101904 */
/*02e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02f0*/ MOV R7, 0x3fdba29c ; /* 0x3fdba29c00077802 */
/* 0x000fca0000000f00 */
/*0300*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*0310*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe2000c101904 */
/*0320*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0330*/ BRA 0x330; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12tanhGradientiiPfS_
.globl _Z12tanhGradientiiPfS_
.p2align 8
.type _Z12tanhGradientiiPfS_,@function
_Z12tanhGradientiiPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v2
v_cmp_gt_i32_e64 s2, s5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_10
s_load_b64 s[2:3], s[0:1], 0x8
v_mad_u64_u32 v[0:1], null, v3, s4, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_mov_b32 s3, 0x4013e147
s_mov_b32 s2, 0xae147ae1
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v7, 0x3f2aaaab, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[4:5], v7
v_cmp_nlt_f64_e32 vcc_lo, s[2:3], v[4:5]
s_and_saveexec_b32 s3, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s4, exec_lo, s3
s_cbranch_execz .LBB0_7
s_mov_b32 s3, 0xc013e147
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ngt_f64_e32 vcc_lo, s[2:3], v[4:5]
s_and_saveexec_b32 s2, vcc_lo
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_4
v_mul_f32_e32 v4, v7, v7
v_fmaak_f32 v5, v7, v7, 0x43bd0000
s_mov_b32 s3, 0x41e00000
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v5, v4, v5, 0x4686a600
v_fmaak_f32 v5, v4, v5, 0x4803f7c0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmaak_f32 v6, s3, v4, 0x4544e000 :: v_dual_mul_f32 v5, v7, v5
v_fmaak_f32 v6, v4, v6, 0x4773a200
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v4, v4, v6, 0x4803f7c0
v_div_scale_f32 v6, null, v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v7, v6
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v6, v7, 1.0
v_fmac_f32_e32 v7, v8, v7
v_div_scale_f32 v8, vcc_lo, v5, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v9, v8, v7
v_fma_f32 v10, -v6, v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v9, v10, v7
v_fma_f32 v6, -v6, v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v6, v6, v7, v9
v_div_fixup_f32 v4, v6, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v5, -v4, v4, 1.0
v_mul_f32_e32 v4, 0x3fdba29c, v4
v_mul_f32_e32 v5, 0x3f2aaaab, v5
global_store_b32 v[2:3], v4, off
v_mul_f32_e32 v6, 0x3fdba29c, v5
.LBB0_4:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v4, 0xbfdba29c
v_mov_b32_e32 v6, 0
global_store_b32 v[2:3], v4, off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_7:
s_and_not1_saveexec_b32 s2, s4
s_cbranch_execz .LBB0_9
v_mov_b32_e32 v4, 0x3fdba29c
v_mov_b32_e32 v6, 0
global_store_b32 v[2:3], v4, off
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12tanhGradientiiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12tanhGradientiiPfS_, .Lfunc_end0-_Z12tanhGradientiiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12tanhGradientiiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12tanhGradientiiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000776fb_00000000-6_tanhGradient.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z12tanhGradientiiPfS_iiPfS_
.type _Z36__device_stub__Z12tanhGradientiiPfS_iiPfS_, @function
_Z36__device_stub__Z12tanhGradientiiPfS_iiPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12tanhGradientiiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z12tanhGradientiiPfS_iiPfS_, .-_Z36__device_stub__Z12tanhGradientiiPfS_iiPfS_
.globl _Z12tanhGradientiiPfS_
.type _Z12tanhGradientiiPfS_, @function
_Z12tanhGradientiiPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12tanhGradientiiPfS_iiPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12tanhGradientiiPfS_, .-_Z12tanhGradientiiPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12tanhGradientiiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12tanhGradientiiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "tanhGradient.hip"
.globl _Z27__device_stub__tanhGradientiiPfS_ # -- Begin function _Z27__device_stub__tanhGradientiiPfS_
.p2align 4, 0x90
.type _Z27__device_stub__tanhGradientiiPfS_,@function
_Z27__device_stub__tanhGradientiiPfS_: # @_Z27__device_stub__tanhGradientiiPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12tanhGradientiiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__tanhGradientiiPfS_, .Lfunc_end0-_Z27__device_stub__tanhGradientiiPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12tanhGradientiiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12tanhGradientiiPfS_,@object # @_Z12tanhGradientiiPfS_
.section .rodata,"a",@progbits
.globl _Z12tanhGradientiiPfS_
.p2align 3, 0x0
_Z12tanhGradientiiPfS_:
.quad _Z27__device_stub__tanhGradientiiPfS_
.size _Z12tanhGradientiiPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12tanhGradientiiPfS_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__tanhGradientiiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12tanhGradientiiPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cstdio>
#include <cuda_runtime.h>
#include "main.cuh"
#define gpuCheck(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
namespace {
constexpr size_t tile = 16;
__global__
void matmulV1(const float* a, const float* b, float* c, int i, int j, int k) {
// Figure out the output element I am writing to
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if (row > i || col > k) {
return;
}
float dotp = 0.0;
for (auto idx = 0U ; idx < j ; ++idx) {
dotp += (a[row * j + idx] * b[col + idx * j]);
}
c[row * k + col] = dotp;
}
__global__
void matmulV2(const float* a, const float* b, float* c, int i, int j, int k) {
__shared__ float rowa[tile][tile];
__shared__ float cola[tile][tile];
// Figure out the output element I am writing to
// For this to work blockDim.x == tile, blockDim.y = tile
const int col = blockIdx.x * tile + threadIdx.x;
const int row = blockIdx.y * tile + threadIdx.y;
if (row > i || col > k) {
return;
}
const int tx = threadIdx.x;
const int ty = threadIdx.y;
float dotp = 0.0;
for (auto idx = 0 ; idx < j ; idx += tile) {
if ((idx + tx) < j)
rowa[ty][tx] = a[row * j + idx + tx];
if ((idx + ty < j))
cola[ty][tx] = b[col + (idx + ty) * j];
__syncthreads();
for (auto i = 0U ; i < tile ; ++i) {
// Don't add elements beyond the vector boundaries
dotp += rowa[ty][i] * cola[i][tx];
}
__syncthreads();
}
c[row * k + col] = dotp;
}
template <typename T>
void kernelRunner(const std::vector<float>& a,
const std::vector<float>& b,
std::vector<float>& c,
int i,
int j,
int k,
T fn) {
const auto a_n = a.size() * sizeof(float);
const auto b_n = b.size() * sizeof(float);
const auto c_n = c.size() * sizeof(float);
float* d_a;
float* d_b;
float* d_c;
gpuCheck(cudaMalloc(&d_a, a_n));
gpuCheck(cudaMalloc(&d_b, b_n));
gpuCheck(cudaMalloc(&d_c, c_n));
gpuCheck(cudaMemcpy(d_a, a.data(), a_n, cudaMemcpyHostToDevice));
gpuCheck(cudaMemcpy(d_b, b.data(), b_n, cudaMemcpyHostToDevice));
gpuCheck(cudaMemcpy(d_c, c.data(), c_n, cudaMemcpyHostToDevice));
dim3 dimGrid(ceil(i/(float)tile), ceil(k/(float)tile), 1);
dim3 dimBlock(tile, tile, 1);
printf("GridDim %d, %d, %d\n", dimGrid.x, dimGrid.y, dimGrid.z);
printf("BlockDim %d, %d, %d\n", dimBlock.x, dimBlock.y, dimBlock.z);
for (auto i = 0U ; i < 200 ; ++i) {
fn<<<dimGrid, dimBlock>>>(d_a, d_b, d_c, i, j, k);
gpuCheck(cudaPeekAtLastError());
cudaDeviceSynchronize();
}
gpuCheck(cudaMemcpy(c.data(), d_c, c_n, cudaMemcpyDeviceToHost));
gpuCheck(cudaFree(d_a));
gpuCheck(cudaFree(d_b));
gpuCheck(cudaFree(d_c));
}
} // unnamed namespace
namespace wrapper {
void matMulV1(const std::vector<float>& a,
const std::vector<float>& b,
std::vector<float>& c,
int i,
int j,
int k) {
kernelRunner(a, b, c, i, j, k, ::matmulV1);
}
// TODO: hook it up with the kernel that uses shared memory
void matMulV2(const std::vector<float>& a,
const std::vector<float>& b,
std::vector<float>& c,
int i,
int j,
int k) {
kernelRunner(a, b, c, i, j, k, ::matmulV2);
}
void print_cuda_properties() {
cudaDeviceProp props;
cudaGetDeviceProperties(&props, 0);
fprintf(stdout, "Warp size: %d\n", props.warpSize);
fprintf(stdout, "Max grid size: %d, %d, %d\n", props.maxGridSize[0], props.maxGridSize[1], props.maxGridSize[2]);
}
} | code for sm_80
Function : _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV2EPKfS1_Pfiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R17, SR_CTAID.X ; /* 0x0000000000117919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0040*/ S2R R16, SR_TID.Y ; /* 0x0000000000107919 */
/* 0x000e620000002200 */
/*0050*/ LEA R17, R17, R0, 0x4 ; /* 0x0000000011117211 */
/* 0x001fc800078e20ff */
/*0060*/ ISETP.GT.AND P0, PT, R17, c[0x0][0x180], PT ; /* 0x0000600011007a0c */
/* 0x000fe40003f04270 */
/*0070*/ LEA R18, R3, R16, 0x4 ; /* 0x0000001003127211 */
/* 0x002fc800078e20ff */
/*0080*/ ISETP.GT.OR P0, PT, R18, c[0x0][0x178], P0 ; /* 0x00005e0012007a0c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x17c] ; /* 0x00005f0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe200000001ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f06270 */
/*00f0*/ IMAD R2, R18, c[0x0][0x180], R17 ; /* 0x0000600012027a24 */
/* 0x000fcc00078e0211 */
/*0100*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fcc00078e0203 */
/*0110*/ @!P0 BRA 0x4d0 ; /* 0x000003b000008947 */
/* 0x000fea0003800000 */
/*0120*/ SHF.L.U32 R21, R16, 0x6, RZ ; /* 0x0000000610157819 */
/* 0x000fe400000006ff */
/*0130*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R23, RZ ; /* 0x000000ff00177202 */
/* 0x000fe40000000f00 */
/*0150*/ LEA R19, R0, R21, 0x2 ; /* 0x0000001500137211 */
/* 0x000fe400078e10ff */
/*0160*/ IADD3 R5, R0, R23.reuse, RZ ; /* 0x0000001700057210 */
/* 0x080fe40007ffe0ff */
/*0170*/ IADD3 R10, R16, R23, RZ ; /* 0x00000017100a7210 */
/* 0x000fe40007ffe0ff */
/*0180*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x17c], PT ; /* 0x00005f0005007a0c */
/* 0x000fc40003f06270 */
/*0190*/ ISETP.GE.AND P1, PT, R10, c[0x0][0x17c], PT ; /* 0x00005f000a007a0c */
/* 0x000fd60003f26270 */
/*01a0*/ @!P0 IMAD R4, R18, c[0x0][0x17c], R5 ; /* 0x00005f0012048a24 */
/* 0x000fe200078e0205 */
/*01b0*/ @!P0 MOV R5, 0x4 ; /* 0x0000000400058802 */
/* 0x000fe20000000f00 */
/*01c0*/ @!P1 IMAD R10, R10, c[0x0][0x17c], R17 ; /* 0x00005f000a0a9a24 */
/* 0x000fe200078e0211 */
/*01d0*/ @!P1 MOV R11, 0x4 ; /* 0x00000004000b9802 */
/* 0x000fc60000000f00 */
/*01e0*/ @!P0 IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004048625 */
/* 0x000fc800078e0205 */
/*01f0*/ @!P1 IMAD.WIDE R10, R10, R11, c[0x0][0x168] ; /* 0x00005a000a0a9625 */
/* 0x000fe200078e020b */
/*0200*/ @!P0 LDG.E R8, [R4.64] ; /* 0x0000000404088981 */
/* 0x000eaa000c1e1900 */
/*0210*/ @!P1 LDG.E R10, [R10.64] ; /* 0x000000040a0a9981 */
/* 0x000ee2000c1e1900 */
/*0220*/ IADD3 R23, R23, 0x10, RZ ; /* 0x0000001017177810 */
/* 0x000fc60007ffe0ff */
/*0230*/ @!P0 STS [R19], R8 ; /* 0x0000000813008388 */
/* 0x004fe20000000800 */
/*0240*/ ISETP.GE.AND P0, PT, R23, c[0x0][0x17c], PT ; /* 0x00005f0017007a0c */
/* 0x000fc60003f06270 */
/*0250*/ @!P1 STS [R19+0x400], R10 ; /* 0x0004000a13009388 */
/* 0x008fe80000000800 */
/*0260*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0270*/ LDS R26, [R0.X4+0x400] ; /* 0x00040000001a7984 */
/* 0x000fe80000004800 */
/*0280*/ LDS.128 R12, [R21] ; /* 0x00000000150c7984 */
/* 0x000e280000000c00 */
/*0290*/ LDS R27, [R0.X4+0x440] ; /* 0x00044000001b7984 */
/* 0x000e680000004800 */
/*02a0*/ LDS R28, [R0.X4+0x480] ; /* 0x00048000001c7984 */
/* 0x000ea80000004800 */
/*02b0*/ LDS R24, [R0.X4+0x4c0] ; /* 0x0004c00000187984 */
/* 0x000ee80000004800 */
/*02c0*/ LDS R29, [R0.X4+0x500] ; /* 0x00050000001d7984 */
/* 0x000fe80000004800 */
/*02d0*/ LDS.128 R4, [R21+0x10] ; /* 0x0000100015047984 */
/* 0x000f280000000c00 */
/*02e0*/ LDS R22, [R0.X4+0x540] ; /* 0x0005400000167984 */
/* 0x000f680000004800 */
/*02f0*/ LDS R25, [R0.X4+0x580] ; /* 0x0005800000197984 */
/* 0x000f680000004800 */
/*0300*/ LDS R20, [R0.X4+0x5c0] ; /* 0x0005c00000147984 */
/* 0x000f620000004800 */
/*0310*/ FFMA R12, R26, R12, R9 ; /* 0x0000000c1a0c7223 */
/* 0x001fc60000000009 */
/*0320*/ LDS.128 R8, [R21+0x20] ; /* 0x0000200015087984 */
/* 0x000fe20000000c00 */
/*0330*/ FFMA R13, R27, R13, R12 ; /* 0x0000000d1b0d7223 */
/* 0x002fc6000000000c */
/*0340*/ LDS R27, [R0.X4+0x600] ; /* 0x00060000001b7984 */
/* 0x000e220000004800 */
/*0350*/ FFMA R13, R28, R14, R13 ; /* 0x0000000e1c0d7223 */
/* 0x004fc8000000000d */
/*0360*/ FFMA R13, R24, R15, R13 ; /* 0x0000000f180d7223 */
/* 0x008fe4000000000d */
/*0370*/ LDS R24, [R0.X4+0x640] ; /* 0x0006400000187984 */
/* 0x000e640000004800 */
/*0380*/ FFMA R4, R29, R4, R13 ; /* 0x000000041d047223 */
/* 0x010fe4000000000d */
/*0390*/ LDS R29, [R0.X4+0x680] ; /* 0x00068000001d7984 */
/* 0x000ea40000004800 */
/*03a0*/ FFMA R5, R22, R5, R4 ; /* 0x0000000516057223 */
/* 0x020fe40000000004 */
/*03b0*/ LDS R4, [R0.X4+0x6c0] ; /* 0x0006c00000047984 */
/* 0x000ee40000004800 */
/*03c0*/ FFMA R6, R25, R6, R5 ; /* 0x0000000619067223 */
/* 0x000fc40000000005 */
/*03d0*/ LDS R5, [R0.X4+0x700] ; /* 0x0007000000057984 */
/* 0x000fe40000004800 */
/*03e0*/ FFMA R22, R20, R7, R6 ; /* 0x0000000714167223 */
/* 0x000fe40000000006 */
/*03f0*/ LDS.128 R12, [R21+0x30] ; /* 0x00003000150c7984 */
/* 0x000f280000000c00 */
/*0400*/ LDS R20, [R0.X4+0x740] ; /* 0x0007400000147984 */
/* 0x000f680000004800 */
/*0410*/ LDS R7, [R0.X4+0x780] ; /* 0x0007800000077984 */
/* 0x000f680000004800 */
/*0420*/ LDS R6, [R0.X4+0x7c0] ; /* 0x0007c00000067984 */
/* 0x000f620000004800 */
/*0430*/ FFMA R8, R27, R8, R22 ; /* 0x000000081b087223 */
/* 0x001fc80000000016 */
/*0440*/ FFMA R8, R24, R9, R8 ; /* 0x0000000918087223 */
/* 0x002fc80000000008 */
/*0450*/ FFMA R8, R29, R10, R8 ; /* 0x0000000a1d087223 */
/* 0x004fc80000000008 */
/*0460*/ FFMA R4, R4, R11, R8 ; /* 0x0000000b04047223 */
/* 0x008fc80000000008 */
/*0470*/ FFMA R4, R5, R12, R4 ; /* 0x0000000c05047223 */
/* 0x010fc80000000004 */
/*0480*/ FFMA R4, R20, R13, R4 ; /* 0x0000000d14047223 */
/* 0x020fc80000000004 */
/*0490*/ FFMA R4, R7, R14, R4 ; /* 0x0000000e07047223 */
/* 0x000fc80000000004 */
/*04a0*/ FFMA R9, R6, R15, R4 ; /* 0x0000000f06097223 */
/* 0x000fe20000000004 */
/*04b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04c0*/ @!P0 BRA 0x160 ; /* 0xfffffc9000008947 */
/* 0x000fea000383ffff */
/*04d0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*04e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04f0*/ BRA 0x4f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV1EPKfS1_Pfiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R26, SR_TID.X ; /* 0x00000000001a7919 */
/* 0x000e280000002100 */
/*0030*/ S2R R17, SR_CTAID.Y ; /* 0x0000000000117919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R26 ; /* 0x0000000003007a24 */
/* 0x001fca00078e021a */
/*0060*/ ISETP.GT.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R17, R17, c[0x0][0x4], R2 ; /* 0x0000010011117a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GT.OR P0, PT, R17, c[0x0][0x178], P0 ; /* 0x00005e0011007a0c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe20003f05270 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R25, RZ, RZ, RZ ; /* 0x000000ffff197224 */
/* 0x000fd600078e00ff */
/*00d0*/ @!P0 BRA 0x4e0 ; /* 0x0000040000008947 */
/* 0x000fea0003800000 */
/*00e0*/ MOV R19, c[0x0][0x17c] ; /* 0x00005f0000137a02 */
/* 0x000fe20000000f00 */
/*00f0*/ HFMA2.MMA R20, -RZ, RZ, 0, 0 ; /* 0x00000000ff147435 */
/* 0x000fe200000001ff */
/*0100*/ IMAD.MOV.U32 R25, RZ, RZ, RZ ; /* 0x000000ffff197224 */
/* 0x000fe400078e00ff */
/*0110*/ IADD3 R2, R19.reuse, -0x1, RZ ; /* 0xffffffff13027810 */
/* 0x040fe40007ffe0ff */
/*0120*/ LOP3.LUT R18, R19, 0x3, RZ, 0xc0, !PT ; /* 0x0000000313127812 */
/* 0x000fe400078ec0ff */
/*0130*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0140*/ ISETP.NE.AND P0, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fd60003f05270 */
/*0150*/ @!P1 BRA 0x400 ; /* 0x000002a000009947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R26, R26, c[0x0][0x17c], RZ ; /* 0x00005f001a1a7a10 */
/* 0x000fe20007ffe0ff */
/*0170*/ IMAD R21, R17, R19, 0x3 ; /* 0x0000000311157424 */
/* 0x000fe200078e0213 */
/*0180*/ IADD3 R23, R18, -c[0x0][0x17c], RZ ; /* 0x80005f0012177a10 */
/* 0x000fe20007ffe0ff */
/*0190*/ IMAD R16, R19, 0x2, R0 ; /* 0x0000000213107824 */
/* 0x000fe200078e0200 */
/*01a0*/ MOV R25, RZ ; /* 0x000000ff00197202 */
/* 0x000fe20000000f00 */
/*01b0*/ IMAD R26, R3, c[0x0][0x0], R26 ; /* 0x00000000031a7a24 */
/* 0x000fe200078e021a */
/*01c0*/ MOV R20, RZ ; /* 0x000000ff00147202 */
/* 0x000fe20000000f00 */
/*01d0*/ IMAD R22, R19, 0x3, R0.reuse ; /* 0x0000000313167824 */
/* 0x100fe400078e0200 */
/*01e0*/ IMAD.MOV.U32 R24, RZ, RZ, R0 ; /* 0x000000ffff187224 */
/* 0x000fe400078e0000 */
/*01f0*/ IADD3 R28, R21, -0x3, RZ ; /* 0xfffffffd151c7810 */
/* 0x000fe40007ffe0ff */
/*0200*/ MOV R13, 0x4 ; /* 0x00000004000d7802 */
/* 0x000fc40000000f00 */
/*0210*/ IADD3 R4, R21.reuse, -0x2, RZ ; /* 0xfffffffe15047810 */
/* 0x040fe40007ffe0ff */
/*0220*/ IADD3 R8, R21, -0x1, RZ ; /* 0xffffffff15087810 */
/* 0x000fe20007ffe0ff */
/*0230*/ IMAD.WIDE.U32 R28, R28, R13, c[0x0][0x160] ; /* 0x000058001c1c7625 */
/* 0x000fc800078e000d */
/*0240*/ IMAD.WIDE.U32 R14, R24, R13.reuse, c[0x0][0x168] ; /* 0x00005a00180e7625 */
/* 0x080fe400078e000d */
/*0250*/ LDG.E R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000ea4000c1e1900 */
/*0260*/ IMAD.WIDE.U32 R4, R4, R13.reuse, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x080fe400078e000d */
/*0270*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea4000c1e1900 */
/*0280*/ IMAD.WIDE.U32 R6, R26, R13.reuse, c[0x0][0x168] ; /* 0x00005a001a067625 */
/* 0x080fe400078e000d */
/*0290*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee4000c1e1900 */
/*02a0*/ IMAD.WIDE.U32 R8, R8, R13, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fc400078e000d */
/*02b0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ee4000c1e1900 */
/*02c0*/ IMAD.WIDE.U32 R2, R16, R13.reuse, c[0x0][0x168] ; /* 0x00005a0010027625 */
/* 0x080fe400078e000d */
/*02d0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f24000c1e1900 */
/*02e0*/ IMAD.WIDE.U32 R10, R21, R13.reuse, c[0x0][0x160] ; /* 0x00005800150a7625 */
/* 0x080fe400078e000d */
/*02f0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000f24000c1e1900 */
/*0300*/ IMAD.WIDE.U32 R12, R22, R13, c[0x0][0x168] ; /* 0x00005a00160c7625 */
/* 0x000fc400078e000d */
/*0310*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f68000c1e1900 */
/*0320*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f62000c1e1900 */
/*0330*/ IADD3 R20, R20, 0x4, RZ ; /* 0x0000000414147810 */
/* 0x000fe20007ffe0ff */
/*0340*/ IMAD R26, R19.reuse, 0x4, R26 ; /* 0x00000004131a7824 */
/* 0x040fe200078e021a */
/*0350*/ LEA R16, R19.reuse, R16, 0x2 ; /* 0x0000001013107211 */
/* 0x040fe200078e10ff */
/*0360*/ IMAD R22, R19.reuse, 0x4, R22 ; /* 0x0000000413167824 */
/* 0x040fe200078e0216 */
/*0370*/ LEA R24, R19, R24, 0x2 ; /* 0x0000001813187211 */
/* 0x000fe400078e10ff */
/*0380*/ IADD3 R21, R21, 0x4, RZ ; /* 0x0000000415157810 */
/* 0x000fe20007ffe0ff */
/*0390*/ FFMA R14, R14, R28, R25 ; /* 0x0000001c0e0e7223 */
/* 0x004fc80000000019 */
/*03a0*/ FFMA R5, R7, R4, R14 ; /* 0x0000000407057223 */
/* 0x008fe2000000000e */
/*03b0*/ IADD3 R4, R23, R20, RZ ; /* 0x0000001417047210 */
/* 0x000fc80007ffe0ff */
/*03c0*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f25270 */
/*03d0*/ FFMA R5, R2, R8, R5 ; /* 0x0000000802057223 */
/* 0x010fc80000000005 */
/*03e0*/ FFMA R25, R12, R10, R5 ; /* 0x0000000a0c197223 */
/* 0x020fd00000000005 */
/*03f0*/ @P1 BRA 0x1f0 ; /* 0xfffffdf000001947 */
/* 0x000fea000383ffff */
/*0400*/ @!P0 BRA 0x4e0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0410*/ IMAD R6, R20, c[0x0][0x17c], R0 ; /* 0x00005f0014067a24 */
/* 0x000fe400078e0200 */
/*0420*/ IMAD R20, R17, c[0x0][0x17c], R20 ; /* 0x00005f0011147a24 */
/* 0x000fe400078e0214 */
/*0430*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fd400000001ff */
/*0440*/ IMAD.WIDE.U32 R2, R20, R5, c[0x0][0x160] ; /* 0x0000580014027625 */
/* 0x000fc800078e0005 */
/*0450*/ IMAD.WIDE.U32 R4, R6, R5, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fe400078e0005 */
/*0460*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IADD3 R18, R18, -0x1, RZ ; /* 0xffffffff12127810 */
/* 0x000fe40007ffe0ff */
/*0490*/ IADD3 R20, R20, 0x1, RZ ; /* 0x0000000114147810 */
/* 0x000fe40007ffe0ff */
/*04a0*/ ISETP.NE.AND P0, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fc40003f05270 */
/*04b0*/ IADD3 R6, R6, c[0x0][0x17c], RZ ; /* 0x00005f0006067a10 */
/* 0x000fe20007ffe0ff */
/*04c0*/ FFMA R25, R4, R2, R25 ; /* 0x0000000204197223 */
/* 0x004fd40000000019 */
/*04d0*/ @P0 BRA 0x430 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*04e0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fe20000000f00 */
/*04f0*/ IMAD R2, R17, c[0x0][0x180], R0 ; /* 0x0000600011027a24 */
/* 0x000fc800078e0200 */
/*0500*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0510*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x000fe2000c101904 */
/*0520*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0530*/ BRA 0x530; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdio>
#include <cuda_runtime.h>
#include "main.cuh"
#define gpuCheck(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
namespace {
constexpr size_t tile = 16;
__global__
void matmulV1(const float* a, const float* b, float* c, int i, int j, int k) {
// Figure out the output element I am writing to
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if (row > i || col > k) {
return;
}
float dotp = 0.0;
for (auto idx = 0U ; idx < j ; ++idx) {
dotp += (a[row * j + idx] * b[col + idx * j]);
}
c[row * k + col] = dotp;
}
__global__
void matmulV2(const float* a, const float* b, float* c, int i, int j, int k) {
__shared__ float rowa[tile][tile];
__shared__ float cola[tile][tile];
// Figure out the output element I am writing to
// For this to work blockDim.x == tile, blockDim.y = tile
const int col = blockIdx.x * tile + threadIdx.x;
const int row = blockIdx.y * tile + threadIdx.y;
if (row > i || col > k) {
return;
}
const int tx = threadIdx.x;
const int ty = threadIdx.y;
float dotp = 0.0;
for (auto idx = 0 ; idx < j ; idx += tile) {
if ((idx + tx) < j)
rowa[ty][tx] = a[row * j + idx + tx];
if ((idx + ty < j))
cola[ty][tx] = b[col + (idx + ty) * j];
__syncthreads();
for (auto i = 0U ; i < tile ; ++i) {
// Don't add elements beyond the vector boundaries
dotp += rowa[ty][i] * cola[i][tx];
}
__syncthreads();
}
c[row * k + col] = dotp;
}
template <typename T>
void kernelRunner(const std::vector<float>& a,
const std::vector<float>& b,
std::vector<float>& c,
int i,
int j,
int k,
T fn) {
const auto a_n = a.size() * sizeof(float);
const auto b_n = b.size() * sizeof(float);
const auto c_n = c.size() * sizeof(float);
float* d_a;
float* d_b;
float* d_c;
gpuCheck(cudaMalloc(&d_a, a_n));
gpuCheck(cudaMalloc(&d_b, b_n));
gpuCheck(cudaMalloc(&d_c, c_n));
gpuCheck(cudaMemcpy(d_a, a.data(), a_n, cudaMemcpyHostToDevice));
gpuCheck(cudaMemcpy(d_b, b.data(), b_n, cudaMemcpyHostToDevice));
gpuCheck(cudaMemcpy(d_c, c.data(), c_n, cudaMemcpyHostToDevice));
dim3 dimGrid(ceil(i/(float)tile), ceil(k/(float)tile), 1);
dim3 dimBlock(tile, tile, 1);
printf("GridDim %d, %d, %d\n", dimGrid.x, dimGrid.y, dimGrid.z);
printf("BlockDim %d, %d, %d\n", dimBlock.x, dimBlock.y, dimBlock.z);
for (auto i = 0U ; i < 200 ; ++i) {
fn<<<dimGrid, dimBlock>>>(d_a, d_b, d_c, i, j, k);
gpuCheck(cudaPeekAtLastError());
cudaDeviceSynchronize();
}
gpuCheck(cudaMemcpy(c.data(), d_c, c_n, cudaMemcpyDeviceToHost));
gpuCheck(cudaFree(d_a));
gpuCheck(cudaFree(d_b));
gpuCheck(cudaFree(d_c));
}
} // unnamed namespace
namespace wrapper {
void matMulV1(const std::vector<float>& a,
const std::vector<float>& b,
std::vector<float>& c,
int i,
int j,
int k) {
kernelRunner(a, b, c, i, j, k, ::matmulV1);
}
// TODO: hook it up with the kernel that uses shared memory
void matMulV2(const std::vector<float>& a,
const std::vector<float>& b,
std::vector<float>& c,
int i,
int j,
int k) {
kernelRunner(a, b, c, i, j, k, ::matmulV2);
}
void print_cuda_properties() {
cudaDeviceProp props;
cudaGetDeviceProperties(&props, 0);
fprintf(stdout, "Warp size: %d\n", props.warpSize);
fprintf(stdout, "Max grid size: %d, %d, %d\n", props.maxGridSize[0], props.maxGridSize[1], props.maxGridSize[2]);
}
} | .file "tmpxft_0000de45_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2933:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2933:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Warp size: %d\n"
.LC1:
.string "Max grid size: %d, %d, %d\n"
.text
.globl _ZN7wrapper21print_cuda_propertiesEv
.type _ZN7wrapper21print_cuda_propertiesEv, @function
_ZN7wrapper21print_cuda_propertiesEv:
.LFB2930:
.cfi_startproc
endbr64
subq $1048, %rsp
.cfi_def_cfa_offset 1056
movq %fs:40, %rax
movq %rax, 1032(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
movl 308(%rsp), %ecx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 344(%rsp), %r9d
movl 340(%rsp), %r8d
movl 336(%rsp), %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $1048, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2930:
.size _ZN7wrapper21print_cuda_propertiesEv, .-_ZN7wrapper21print_cuda_propertiesEv
.globl _Z79__device_stub__ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV1EPKfS1_PfiiiPKfS0_Pfiii
.hidden _Z79__device_stub__ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV1EPKfS1_PfiiiPKfS0_Pfiii
.type _Z79__device_stub__ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV1EPKfS1_PfiiiPKfS0_Pfiii, @function
_Z79__device_stub__ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV1EPKfS1_PfiiiPKfS0_Pfiii:
.LFB2955:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV1EPKfS1_Pfiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2955:
.size _Z79__device_stub__ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV1EPKfS1_PfiiiPKfS0_Pfiii, .-_Z79__device_stub__ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV1EPKfS1_PfiiiPKfS0_Pfiii
.globl _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV1EPKfS1_Pfiii
.hidden _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV1EPKfS1_Pfiii
.type _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV1EPKfS1_Pfiii, @function
_ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV1EPKfS1_Pfiii:
.LFB2956:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z79__device_stub__ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV1EPKfS1_PfiiiPKfS0_Pfiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2956:
.size _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV1EPKfS1_Pfiii, .-_ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV1EPKfS1_Pfiii
.globl _Z79__device_stub__ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV2EPKfS1_PfiiiPKfS0_Pfiii
.hidden _Z79__device_stub__ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV2EPKfS1_PfiiiPKfS0_Pfiii
.type _Z79__device_stub__ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV2EPKfS1_PfiiiPKfS0_Pfiii, @function
_Z79__device_stub__ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV2EPKfS1_PfiiiPKfS0_Pfiii:
.LFB2957:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV2EPKfS1_Pfiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2957:
.size _Z79__device_stub__ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV2EPKfS1_PfiiiPKfS0_Pfiii, .-_Z79__device_stub__ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV2EPKfS1_PfiiiPKfS0_Pfiii
.globl _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV2EPKfS1_Pfiii
.hidden _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV2EPKfS1_Pfiii
.type _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV2EPKfS1_Pfiii, @function
_ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV2EPKfS1_Pfiii:
.LFB2958:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z79__device_stub__ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV2EPKfS1_PfiiiPKfS0_Pfiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2958:
.size _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV2EPKfS1_Pfiii, .-_ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV2EPKfS1_Pfiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV2EPKfS1_Pfiii"
.align 8
.LC3:
.string "_ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV1EPKfS1_Pfiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2960:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV2EPKfS1_Pfiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV1EPKfS1_Pfiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2960:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e412kernelRunnerIPFvPKfS2_PfiiiEEEvRKSt6vectorIfSaIfEESA_RS8_iiiT_.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "/home/ubuntu/Datasets/stackv2/train-structured/julitopower/CppLittleExercises/master/cuda_matmul/main.cu"
.section .rodata._ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e412kernelRunnerIPFvPKfS2_PfiiiEEEvRKSt6vectorIfSaIfEESA_RS8_iiiT_.str1.1,"aMS",@progbits,1
.LC5:
.string "GPUassert: %s %s %d\n"
.LC10:
.string "GridDim %d, %d, %d\n"
.LC11:
.string "BlockDim %d, %d, %d\n"
.section .text._ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e412kernelRunnerIPFvPKfS2_PfiiiEEEvRKSt6vectorIfSaIfEESA_RS8_iiiT_,"axG",@progbits,_ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e412kernelRunnerIPFvPKfS2_PfiiiEEEvRKSt6vectorIfSaIfEESA_RS8_iiiT_,comdat
.weak _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e412kernelRunnerIPFvPKfS2_PfiiiEEEvRKSt6vectorIfSaIfEESA_RS8_iiiT_
.hidden _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e412kernelRunnerIPFvPKfS2_PfiiiEEEvRKSt6vectorIfSaIfEESA_RS8_iiiT_
.type _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e412kernelRunnerIPFvPKfS2_PfiiiEEEvRKSt6vectorIfSaIfEESA_RS8_iiiT_, @function
_ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e412kernelRunnerIPFvPKfS2_PfiiiEEEvRKSt6vectorIfSaIfEESA_RS8_iiiT_:
.LFB3008:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r12
movl %ecx, 44(%rsp)
movl %r8d, 40(%rsp)
movl %r9d, 28(%rsp)
movq 176(%rsp), %rax
movq %rax, 32(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq 8(%rdi), %r14
subq (%rdi), %r14
movq 8(%rsi), %r13
movq (%rsi), %r15
movq 8(%rdx), %rax
movq %rax, 16(%rsp)
movq (%rdx), %rax
movq %rax, 8(%rsp)
leaq 56(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L44
subq %r15, %r13
leaq 64(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L45
movq 16(%rsp), %r15
movq 8(%rsp), %rax
subq %rax, %r15
leaq 72(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L46
movq (%rbx), %rsi
movl $1, %ecx
movq %r14, %rdx
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L47
movq 0(%rbp), %rsi
movl $1, %ecx
movq %r13, %rdx
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L48
movq (%r12), %rsi
movl $1, %ecx
movq %r15, %rdx
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L49
pxor %xmm0, %xmm0
cvtsi2ssl 28(%rsp), %xmm0
mulss .LC6(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC12(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC7(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L32
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC9(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L32:
cvttss2siq %xmm3, %r13
pxor %xmm0, %xmm0
cvtsi2ssl 44(%rsp), %xmm0
mulss .LC6(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC12(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC7(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L33
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC9(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L33:
cvttss2siq %xmm3, %r14
movl $1, %r8d
movl %r13d, %ecx
movl %r14d, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %r8d
movl $16, %ecx
movl $16, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L36
.L44:
movl %eax, %edi
movl %eax, %ebx
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $88, %r9d
leaq .LC4(%rip), %r8
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L45:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $89, %r9d
leaq .LC4(%rip), %r8
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r15d, %edi
call exit@PLT
.L46:
movl %eax, %ebx
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $90, %r9d
leaq .LC4(%rip), %r8
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L47:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $92, %r9d
leaq .LC4(%rip), %r8
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L48:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $93, %r9d
leaq .LC4(%rip), %r8
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L49:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $94, %r9d
leaq .LC4(%rip), %r8
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L34:
call cudaPeekAtLastError@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L50
call cudaDeviceSynchronize@PLT
addl $1, %ebx
cmpl $200, %ebx
je .L51
.L36:
movl %r14d, 80(%rsp)
movl %r13d, 84(%rsp)
movl $16, 92(%rsp)
movl $16, 96(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L34
movl 28(%rsp), %r9d
movl 40(%rsp), %r8d
movl %ebx, %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
movq 32(%rsp), %rax
call *%rax
jmp .L34
.L50:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $104, %r9d
leaq .LC4(%rip), %r8
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L51:
movq (%r12), %rdi
movl $2, %ecx
movq %r15, %rdx
movq 72(%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L52
movq 56(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L53
movq 64(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L54
movq 72(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L55
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L56
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $108, %r9d
leaq .LC4(%rip), %r8
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L53:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $109, %r9d
leaq .LC4(%rip), %r8
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L54:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $110, %r9d
leaq .LC4(%rip), %r8
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L55:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $111, %r9d
leaq .LC4(%rip), %r8
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L56:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3008:
.size _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e412kernelRunnerIPFvPKfS2_PfiiiEEEvRKSt6vectorIfSaIfEESA_RS8_iiiT_, .-_ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e412kernelRunnerIPFvPKfS2_PfiiiEEEvRKSt6vectorIfSaIfEESA_RS8_iiiT_
.text
.globl _ZN7wrapper8matMulV1ERKSt6vectorIfSaIfEES4_RS2_iii
.type _ZN7wrapper8matMulV1ERKSt6vectorIfSaIfEES4_RS2_iii, @function
_ZN7wrapper8matMulV1ERKSt6vectorIfSaIfEES4_RS2_iii:
.LFB2928:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
leaq _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV1EPKfS1_Pfiii(%rip), %rax
pushq %rax
.cfi_def_cfa_offset 32
call _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e412kernelRunnerIPFvPKfS2_PfiiiEEEvRKSt6vectorIfSaIfEESA_RS8_iiiT_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2928:
.size _ZN7wrapper8matMulV1ERKSt6vectorIfSaIfEES4_RS2_iii, .-_ZN7wrapper8matMulV1ERKSt6vectorIfSaIfEES4_RS2_iii
.globl _ZN7wrapper8matMulV2ERKSt6vectorIfSaIfEES4_RS2_iii
.type _ZN7wrapper8matMulV2ERKSt6vectorIfSaIfEES4_RS2_iii, @function
_ZN7wrapper8matMulV2ERKSt6vectorIfSaIfEES4_RS2_iii:
.LFB2929:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
leaq _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV2EPKfS1_Pfiii(%rip), %rax
pushq %rax
.cfi_def_cfa_offset 32
call _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e412kernelRunnerIPFvPKfS2_PfiiiEEEvRKSt6vectorIfSaIfEESA_RS8_iiiT_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2929:
.size _ZN7wrapper8matMulV2ERKSt6vectorIfSaIfEES4_RS2_iii, .-_ZN7wrapper8matMulV2ERKSt6vectorIfSaIfEES4_RS2_iii
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC6:
.long 1031798784
.align 4
.LC7:
.long 1258291200
.align 4
.LC9:
.long 1065353216
.align 4
.LC12:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
#include <cuda_runtime.h>
#include "main.cuh"
#define gpuCheck(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
namespace {
constexpr size_t tile = 16;
__global__
void matmulV1(const float* a, const float* b, float* c, int i, int j, int k) {
// Figure out the output element I am writing to
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if (row > i || col > k) {
return;
}
float dotp = 0.0;
for (auto idx = 0U ; idx < j ; ++idx) {
dotp += (a[row * j + idx] * b[col + idx * j]);
}
c[row * k + col] = dotp;
}
__global__
void matmulV2(const float* a, const float* b, float* c, int i, int j, int k) {
__shared__ float rowa[tile][tile];
__shared__ float cola[tile][tile];
// Figure out the output element I am writing to
// For this to work blockDim.x == tile, blockDim.y = tile
const int col = blockIdx.x * tile + threadIdx.x;
const int row = blockIdx.y * tile + threadIdx.y;
if (row > i || col > k) {
return;
}
const int tx = threadIdx.x;
const int ty = threadIdx.y;
float dotp = 0.0;
for (auto idx = 0 ; idx < j ; idx += tile) {
if ((idx + tx) < j)
rowa[ty][tx] = a[row * j + idx + tx];
if ((idx + ty < j))
cola[ty][tx] = b[col + (idx + ty) * j];
__syncthreads();
for (auto i = 0U ; i < tile ; ++i) {
// Don't add elements beyond the vector boundaries
dotp += rowa[ty][i] * cola[i][tx];
}
__syncthreads();
}
c[row * k + col] = dotp;
}
template <typename T>
void kernelRunner(const std::vector<float>& a,
const std::vector<float>& b,
std::vector<float>& c,
int i,
int j,
int k,
T fn) {
const auto a_n = a.size() * sizeof(float);
const auto b_n = b.size() * sizeof(float);
const auto c_n = c.size() * sizeof(float);
float* d_a;
float* d_b;
float* d_c;
gpuCheck(cudaMalloc(&d_a, a_n));
gpuCheck(cudaMalloc(&d_b, b_n));
gpuCheck(cudaMalloc(&d_c, c_n));
gpuCheck(cudaMemcpy(d_a, a.data(), a_n, cudaMemcpyHostToDevice));
gpuCheck(cudaMemcpy(d_b, b.data(), b_n, cudaMemcpyHostToDevice));
gpuCheck(cudaMemcpy(d_c, c.data(), c_n, cudaMemcpyHostToDevice));
dim3 dimGrid(ceil(i/(float)tile), ceil(k/(float)tile), 1);
dim3 dimBlock(tile, tile, 1);
printf("GridDim %d, %d, %d\n", dimGrid.x, dimGrid.y, dimGrid.z);
printf("BlockDim %d, %d, %d\n", dimBlock.x, dimBlock.y, dimBlock.z);
for (auto i = 0U ; i < 200 ; ++i) {
fn<<<dimGrid, dimBlock>>>(d_a, d_b, d_c, i, j, k);
gpuCheck(cudaPeekAtLastError());
cudaDeviceSynchronize();
}
gpuCheck(cudaMemcpy(c.data(), d_c, c_n, cudaMemcpyDeviceToHost));
gpuCheck(cudaFree(d_a));
gpuCheck(cudaFree(d_b));
gpuCheck(cudaFree(d_c));
}
} // unnamed namespace
namespace wrapper {
void matMulV1(const std::vector<float>& a,
const std::vector<float>& b,
std::vector<float>& c,
int i,
int j,
int k) {
kernelRunner(a, b, c, i, j, k, ::matmulV1);
}
// TODO: hook it up with the kernel that uses shared memory
void matMulV2(const std::vector<float>& a,
const std::vector<float>& b,
std::vector<float>& c,
int i,
int j,
int k) {
kernelRunner(a, b, c, i, j, k, ::matmulV2);
}
void print_cuda_properties() {
cudaDeviceProp props;
cudaGetDeviceProperties(&props, 0);
fprintf(stdout, "Warp size: %d\n", props.warpSize);
fprintf(stdout, "Max grid size: %d, %d, %d\n", props.maxGridSize[0], props.maxGridSize[1], props.maxGridSize[2]);
}
} | #pragma once
#include <hip/hip_runtime.h>
#include <vector>
namespace wrapper {
static const size_t TILE_WIDTH = 2;
static const size_t TILE_HEIGHT = 2;
void matMulV1(const std::vector<float>& a,
const std::vector<float>& b,
std::vector<float>& c,
int i,
int j,
int k);
void matMulV2(const std::vector<float>& a,
const std::vector<float>& b,
std::vector<float>& c,
int i,
int j,
int k);
void print_cuda_properties();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #pragma once
#include <hip/hip_runtime.h>
#include <vector>
namespace wrapper {
static const size_t TILE_WIDTH = 2;
static const size_t TILE_HEIGHT = 2;
void matMulV1(const std::vector<float>& a,
const std::vector<float>& b,
std::vector<float>& c,
int i,
int j,
int k);
void matMulV2(const std::vector<float>& a,
const std::vector<float>& b,
std::vector<float>& c,
int i,
int j,
int k);
void print_cuda_properties();
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #pragma once
#include <hip/hip_runtime.h>
#include <vector>
namespace wrapper {
static const size_t TILE_WIDTH = 2;
static const size_t TILE_HEIGHT = 2;
void matMulV1(const std::vector<float>& a,
const std::vector<float>& b,
std::vector<float>& c,
int i,
int j,
int k);
void matMulV2(const std::vector<float>& a,
const std::vector<float>& b,
std::vector<float>& c,
int i,
int j,
int k);
void print_cuda_properties();
} | .text
.file "main.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV2EPKfS1_Pfiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R17, SR_CTAID.X ; /* 0x0000000000117919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0040*/ S2R R16, SR_TID.Y ; /* 0x0000000000107919 */
/* 0x000e620000002200 */
/*0050*/ LEA R17, R17, R0, 0x4 ; /* 0x0000000011117211 */
/* 0x001fc800078e20ff */
/*0060*/ ISETP.GT.AND P0, PT, R17, c[0x0][0x180], PT ; /* 0x0000600011007a0c */
/* 0x000fe40003f04270 */
/*0070*/ LEA R18, R3, R16, 0x4 ; /* 0x0000001003127211 */
/* 0x002fc800078e20ff */
/*0080*/ ISETP.GT.OR P0, PT, R18, c[0x0][0x178], P0 ; /* 0x00005e0012007a0c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x17c] ; /* 0x00005f0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe200000001ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f06270 */
/*00f0*/ IMAD R2, R18, c[0x0][0x180], R17 ; /* 0x0000600012027a24 */
/* 0x000fcc00078e0211 */
/*0100*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fcc00078e0203 */
/*0110*/ @!P0 BRA 0x4d0 ; /* 0x000003b000008947 */
/* 0x000fea0003800000 */
/*0120*/ SHF.L.U32 R21, R16, 0x6, RZ ; /* 0x0000000610157819 */
/* 0x000fe400000006ff */
/*0130*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R23, RZ ; /* 0x000000ff00177202 */
/* 0x000fe40000000f00 */
/*0150*/ LEA R19, R0, R21, 0x2 ; /* 0x0000001500137211 */
/* 0x000fe400078e10ff */
/*0160*/ IADD3 R5, R0, R23.reuse, RZ ; /* 0x0000001700057210 */
/* 0x080fe40007ffe0ff */
/*0170*/ IADD3 R10, R16, R23, RZ ; /* 0x00000017100a7210 */
/* 0x000fe40007ffe0ff */
/*0180*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x17c], PT ; /* 0x00005f0005007a0c */
/* 0x000fc40003f06270 */
/*0190*/ ISETP.GE.AND P1, PT, R10, c[0x0][0x17c], PT ; /* 0x00005f000a007a0c */
/* 0x000fd60003f26270 */
/*01a0*/ @!P0 IMAD R4, R18, c[0x0][0x17c], R5 ; /* 0x00005f0012048a24 */
/* 0x000fe200078e0205 */
/*01b0*/ @!P0 MOV R5, 0x4 ; /* 0x0000000400058802 */
/* 0x000fe20000000f00 */
/*01c0*/ @!P1 IMAD R10, R10, c[0x0][0x17c], R17 ; /* 0x00005f000a0a9a24 */
/* 0x000fe200078e0211 */
/*01d0*/ @!P1 MOV R11, 0x4 ; /* 0x00000004000b9802 */
/* 0x000fc60000000f00 */
/*01e0*/ @!P0 IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004048625 */
/* 0x000fc800078e0205 */
/*01f0*/ @!P1 IMAD.WIDE R10, R10, R11, c[0x0][0x168] ; /* 0x00005a000a0a9625 */
/* 0x000fe200078e020b */
/*0200*/ @!P0 LDG.E R8, [R4.64] ; /* 0x0000000404088981 */
/* 0x000eaa000c1e1900 */
/*0210*/ @!P1 LDG.E R10, [R10.64] ; /* 0x000000040a0a9981 */
/* 0x000ee2000c1e1900 */
/*0220*/ IADD3 R23, R23, 0x10, RZ ; /* 0x0000001017177810 */
/* 0x000fc60007ffe0ff */
/*0230*/ @!P0 STS [R19], R8 ; /* 0x0000000813008388 */
/* 0x004fe20000000800 */
/*0240*/ ISETP.GE.AND P0, PT, R23, c[0x0][0x17c], PT ; /* 0x00005f0017007a0c */
/* 0x000fc60003f06270 */
/*0250*/ @!P1 STS [R19+0x400], R10 ; /* 0x0004000a13009388 */
/* 0x008fe80000000800 */
/*0260*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0270*/ LDS R26, [R0.X4+0x400] ; /* 0x00040000001a7984 */
/* 0x000fe80000004800 */
/*0280*/ LDS.128 R12, [R21] ; /* 0x00000000150c7984 */
/* 0x000e280000000c00 */
/*0290*/ LDS R27, [R0.X4+0x440] ; /* 0x00044000001b7984 */
/* 0x000e680000004800 */
/*02a0*/ LDS R28, [R0.X4+0x480] ; /* 0x00048000001c7984 */
/* 0x000ea80000004800 */
/*02b0*/ LDS R24, [R0.X4+0x4c0] ; /* 0x0004c00000187984 */
/* 0x000ee80000004800 */
/*02c0*/ LDS R29, [R0.X4+0x500] ; /* 0x00050000001d7984 */
/* 0x000fe80000004800 */
/*02d0*/ LDS.128 R4, [R21+0x10] ; /* 0x0000100015047984 */
/* 0x000f280000000c00 */
/*02e0*/ LDS R22, [R0.X4+0x540] ; /* 0x0005400000167984 */
/* 0x000f680000004800 */
/*02f0*/ LDS R25, [R0.X4+0x580] ; /* 0x0005800000197984 */
/* 0x000f680000004800 */
/*0300*/ LDS R20, [R0.X4+0x5c0] ; /* 0x0005c00000147984 */
/* 0x000f620000004800 */
/*0310*/ FFMA R12, R26, R12, R9 ; /* 0x0000000c1a0c7223 */
/* 0x001fc60000000009 */
/*0320*/ LDS.128 R8, [R21+0x20] ; /* 0x0000200015087984 */
/* 0x000fe20000000c00 */
/*0330*/ FFMA R13, R27, R13, R12 ; /* 0x0000000d1b0d7223 */
/* 0x002fc6000000000c */
/*0340*/ LDS R27, [R0.X4+0x600] ; /* 0x00060000001b7984 */
/* 0x000e220000004800 */
/*0350*/ FFMA R13, R28, R14, R13 ; /* 0x0000000e1c0d7223 */
/* 0x004fc8000000000d */
/*0360*/ FFMA R13, R24, R15, R13 ; /* 0x0000000f180d7223 */
/* 0x008fe4000000000d */
/*0370*/ LDS R24, [R0.X4+0x640] ; /* 0x0006400000187984 */
/* 0x000e640000004800 */
/*0380*/ FFMA R4, R29, R4, R13 ; /* 0x000000041d047223 */
/* 0x010fe4000000000d */
/*0390*/ LDS R29, [R0.X4+0x680] ; /* 0x00068000001d7984 */
/* 0x000ea40000004800 */
/*03a0*/ FFMA R5, R22, R5, R4 ; /* 0x0000000516057223 */
/* 0x020fe40000000004 */
/*03b0*/ LDS R4, [R0.X4+0x6c0] ; /* 0x0006c00000047984 */
/* 0x000ee40000004800 */
/*03c0*/ FFMA R6, R25, R6, R5 ; /* 0x0000000619067223 */
/* 0x000fc40000000005 */
/*03d0*/ LDS R5, [R0.X4+0x700] ; /* 0x0007000000057984 */
/* 0x000fe40000004800 */
/*03e0*/ FFMA R22, R20, R7, R6 ; /* 0x0000000714167223 */
/* 0x000fe40000000006 */
/*03f0*/ LDS.128 R12, [R21+0x30] ; /* 0x00003000150c7984 */
/* 0x000f280000000c00 */
/*0400*/ LDS R20, [R0.X4+0x740] ; /* 0x0007400000147984 */
/* 0x000f680000004800 */
/*0410*/ LDS R7, [R0.X4+0x780] ; /* 0x0007800000077984 */
/* 0x000f680000004800 */
/*0420*/ LDS R6, [R0.X4+0x7c0] ; /* 0x0007c00000067984 */
/* 0x000f620000004800 */
/*0430*/ FFMA R8, R27, R8, R22 ; /* 0x000000081b087223 */
/* 0x001fc80000000016 */
/*0440*/ FFMA R8, R24, R9, R8 ; /* 0x0000000918087223 */
/* 0x002fc80000000008 */
/*0450*/ FFMA R8, R29, R10, R8 ; /* 0x0000000a1d087223 */
/* 0x004fc80000000008 */
/*0460*/ FFMA R4, R4, R11, R8 ; /* 0x0000000b04047223 */
/* 0x008fc80000000008 */
/*0470*/ FFMA R4, R5, R12, R4 ; /* 0x0000000c05047223 */
/* 0x010fc80000000004 */
/*0480*/ FFMA R4, R20, R13, R4 ; /* 0x0000000d14047223 */
/* 0x020fc80000000004 */
/*0490*/ FFMA R4, R7, R14, R4 ; /* 0x0000000e07047223 */
/* 0x000fc80000000004 */
/*04a0*/ FFMA R9, R6, R15, R4 ; /* 0x0000000f06097223 */
/* 0x000fe20000000004 */
/*04b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04c0*/ @!P0 BRA 0x160 ; /* 0xfffffc9000008947 */
/* 0x000fea000383ffff */
/*04d0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*04e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04f0*/ BRA 0x4f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV1EPKfS1_Pfiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R26, SR_TID.X ; /* 0x00000000001a7919 */
/* 0x000e280000002100 */
/*0030*/ S2R R17, SR_CTAID.Y ; /* 0x0000000000117919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R26 ; /* 0x0000000003007a24 */
/* 0x001fca00078e021a */
/*0060*/ ISETP.GT.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R17, R17, c[0x0][0x4], R2 ; /* 0x0000010011117a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GT.OR P0, PT, R17, c[0x0][0x178], P0 ; /* 0x00005e0011007a0c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe20003f05270 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R25, RZ, RZ, RZ ; /* 0x000000ffff197224 */
/* 0x000fd600078e00ff */
/*00d0*/ @!P0 BRA 0x4e0 ; /* 0x0000040000008947 */
/* 0x000fea0003800000 */
/*00e0*/ MOV R19, c[0x0][0x17c] ; /* 0x00005f0000137a02 */
/* 0x000fe20000000f00 */
/*00f0*/ HFMA2.MMA R20, -RZ, RZ, 0, 0 ; /* 0x00000000ff147435 */
/* 0x000fe200000001ff */
/*0100*/ IMAD.MOV.U32 R25, RZ, RZ, RZ ; /* 0x000000ffff197224 */
/* 0x000fe400078e00ff */
/*0110*/ IADD3 R2, R19.reuse, -0x1, RZ ; /* 0xffffffff13027810 */
/* 0x040fe40007ffe0ff */
/*0120*/ LOP3.LUT R18, R19, 0x3, RZ, 0xc0, !PT ; /* 0x0000000313127812 */
/* 0x000fe400078ec0ff */
/*0130*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0140*/ ISETP.NE.AND P0, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fd60003f05270 */
/*0150*/ @!P1 BRA 0x400 ; /* 0x000002a000009947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R26, R26, c[0x0][0x17c], RZ ; /* 0x00005f001a1a7a10 */
/* 0x000fe20007ffe0ff */
/*0170*/ IMAD R21, R17, R19, 0x3 ; /* 0x0000000311157424 */
/* 0x000fe200078e0213 */
/*0180*/ IADD3 R23, R18, -c[0x0][0x17c], RZ ; /* 0x80005f0012177a10 */
/* 0x000fe20007ffe0ff */
/*0190*/ IMAD R16, R19, 0x2, R0 ; /* 0x0000000213107824 */
/* 0x000fe200078e0200 */
/*01a0*/ MOV R25, RZ ; /* 0x000000ff00197202 */
/* 0x000fe20000000f00 */
/*01b0*/ IMAD R26, R3, c[0x0][0x0], R26 ; /* 0x00000000031a7a24 */
/* 0x000fe200078e021a */
/*01c0*/ MOV R20, RZ ; /* 0x000000ff00147202 */
/* 0x000fe20000000f00 */
/*01d0*/ IMAD R22, R19, 0x3, R0.reuse ; /* 0x0000000313167824 */
/* 0x100fe400078e0200 */
/*01e0*/ IMAD.MOV.U32 R24, RZ, RZ, R0 ; /* 0x000000ffff187224 */
/* 0x000fe400078e0000 */
/*01f0*/ IADD3 R28, R21, -0x3, RZ ; /* 0xfffffffd151c7810 */
/* 0x000fe40007ffe0ff */
/*0200*/ MOV R13, 0x4 ; /* 0x00000004000d7802 */
/* 0x000fc40000000f00 */
/*0210*/ IADD3 R4, R21.reuse, -0x2, RZ ; /* 0xfffffffe15047810 */
/* 0x040fe40007ffe0ff */
/*0220*/ IADD3 R8, R21, -0x1, RZ ; /* 0xffffffff15087810 */
/* 0x000fe20007ffe0ff */
/*0230*/ IMAD.WIDE.U32 R28, R28, R13, c[0x0][0x160] ; /* 0x000058001c1c7625 */
/* 0x000fc800078e000d */
/*0240*/ IMAD.WIDE.U32 R14, R24, R13.reuse, c[0x0][0x168] ; /* 0x00005a00180e7625 */
/* 0x080fe400078e000d */
/*0250*/ LDG.E R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000ea4000c1e1900 */
/*0260*/ IMAD.WIDE.U32 R4, R4, R13.reuse, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x080fe400078e000d */
/*0270*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea4000c1e1900 */
/*0280*/ IMAD.WIDE.U32 R6, R26, R13.reuse, c[0x0][0x168] ; /* 0x00005a001a067625 */
/* 0x080fe400078e000d */
/*0290*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee4000c1e1900 */
/*02a0*/ IMAD.WIDE.U32 R8, R8, R13, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fc400078e000d */
/*02b0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ee4000c1e1900 */
/*02c0*/ IMAD.WIDE.U32 R2, R16, R13.reuse, c[0x0][0x168] ; /* 0x00005a0010027625 */
/* 0x080fe400078e000d */
/*02d0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f24000c1e1900 */
/*02e0*/ IMAD.WIDE.U32 R10, R21, R13.reuse, c[0x0][0x160] ; /* 0x00005800150a7625 */
/* 0x080fe400078e000d */
/*02f0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000f24000c1e1900 */
/*0300*/ IMAD.WIDE.U32 R12, R22, R13, c[0x0][0x168] ; /* 0x00005a00160c7625 */
/* 0x000fc400078e000d */
/*0310*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f68000c1e1900 */
/*0320*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f62000c1e1900 */
/*0330*/ IADD3 R20, R20, 0x4, RZ ; /* 0x0000000414147810 */
/* 0x000fe20007ffe0ff */
/*0340*/ IMAD R26, R19.reuse, 0x4, R26 ; /* 0x00000004131a7824 */
/* 0x040fe200078e021a */
/*0350*/ LEA R16, R19.reuse, R16, 0x2 ; /* 0x0000001013107211 */
/* 0x040fe200078e10ff */
/*0360*/ IMAD R22, R19.reuse, 0x4, R22 ; /* 0x0000000413167824 */
/* 0x040fe200078e0216 */
/*0370*/ LEA R24, R19, R24, 0x2 ; /* 0x0000001813187211 */
/* 0x000fe400078e10ff */
/*0380*/ IADD3 R21, R21, 0x4, RZ ; /* 0x0000000415157810 */
/* 0x000fe20007ffe0ff */
/*0390*/ FFMA R14, R14, R28, R25 ; /* 0x0000001c0e0e7223 */
/* 0x004fc80000000019 */
/*03a0*/ FFMA R5, R7, R4, R14 ; /* 0x0000000407057223 */
/* 0x008fe2000000000e */
/*03b0*/ IADD3 R4, R23, R20, RZ ; /* 0x0000001417047210 */
/* 0x000fc80007ffe0ff */
/*03c0*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f25270 */
/*03d0*/ FFMA R5, R2, R8, R5 ; /* 0x0000000802057223 */
/* 0x010fc80000000005 */
/*03e0*/ FFMA R25, R12, R10, R5 ; /* 0x0000000a0c197223 */
/* 0x020fd00000000005 */
/*03f0*/ @P1 BRA 0x1f0 ; /* 0xfffffdf000001947 */
/* 0x000fea000383ffff */
/*0400*/ @!P0 BRA 0x4e0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0410*/ IMAD R6, R20, c[0x0][0x17c], R0 ; /* 0x00005f0014067a24 */
/* 0x000fe400078e0200 */
/*0420*/ IMAD R20, R17, c[0x0][0x17c], R20 ; /* 0x00005f0011147a24 */
/* 0x000fe400078e0214 */
/*0430*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fd400000001ff */
/*0440*/ IMAD.WIDE.U32 R2, R20, R5, c[0x0][0x160] ; /* 0x0000580014027625 */
/* 0x000fc800078e0005 */
/*0450*/ IMAD.WIDE.U32 R4, R6, R5, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fe400078e0005 */
/*0460*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IADD3 R18, R18, -0x1, RZ ; /* 0xffffffff12127810 */
/* 0x000fe40007ffe0ff */
/*0490*/ IADD3 R20, R20, 0x1, RZ ; /* 0x0000000114147810 */
/* 0x000fe40007ffe0ff */
/*04a0*/ ISETP.NE.AND P0, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fc40003f05270 */
/*04b0*/ IADD3 R6, R6, c[0x0][0x17c], RZ ; /* 0x00005f0006067a10 */
/* 0x000fe20007ffe0ff */
/*04c0*/ FFMA R25, R4, R2, R25 ; /* 0x0000000204197223 */
/* 0x004fd40000000019 */
/*04d0*/ @P0 BRA 0x430 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*04e0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fe20000000f00 */
/*04f0*/ IMAD R2, R17, c[0x0][0x180], R0 ; /* 0x0000600011027a24 */
/* 0x000fc800078e0200 */
/*0500*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0510*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x000fe2000c101904 */
/*0520*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0530*/ BRA 0x530; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000de45_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2933:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2933:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Warp size: %d\n"
.LC1:
.string "Max grid size: %d, %d, %d\n"
.text
.globl _ZN7wrapper21print_cuda_propertiesEv
.type _ZN7wrapper21print_cuda_propertiesEv, @function
_ZN7wrapper21print_cuda_propertiesEv:
.LFB2930:
.cfi_startproc
endbr64
subq $1048, %rsp
.cfi_def_cfa_offset 1056
movq %fs:40, %rax
movq %rax, 1032(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
movl 308(%rsp), %ecx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 344(%rsp), %r9d
movl 340(%rsp), %r8d
movl 336(%rsp), %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $1048, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2930:
.size _ZN7wrapper21print_cuda_propertiesEv, .-_ZN7wrapper21print_cuda_propertiesEv
.globl _Z79__device_stub__ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV1EPKfS1_PfiiiPKfS0_Pfiii
.hidden _Z79__device_stub__ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV1EPKfS1_PfiiiPKfS0_Pfiii
.type _Z79__device_stub__ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV1EPKfS1_PfiiiPKfS0_Pfiii, @function
_Z79__device_stub__ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV1EPKfS1_PfiiiPKfS0_Pfiii:
.LFB2955:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV1EPKfS1_Pfiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2955:
.size _Z79__device_stub__ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV1EPKfS1_PfiiiPKfS0_Pfiii, .-_Z79__device_stub__ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV1EPKfS1_PfiiiPKfS0_Pfiii
.globl _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV1EPKfS1_Pfiii
.hidden _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV1EPKfS1_Pfiii
.type _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV1EPKfS1_Pfiii, @function
_ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV1EPKfS1_Pfiii:
.LFB2956:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z79__device_stub__ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV1EPKfS1_PfiiiPKfS0_Pfiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2956:
.size _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV1EPKfS1_Pfiii, .-_ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV1EPKfS1_Pfiii
.globl _Z79__device_stub__ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV2EPKfS1_PfiiiPKfS0_Pfiii
.hidden _Z79__device_stub__ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV2EPKfS1_PfiiiPKfS0_Pfiii
.type _Z79__device_stub__ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV2EPKfS1_PfiiiPKfS0_Pfiii, @function
_Z79__device_stub__ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV2EPKfS1_PfiiiPKfS0_Pfiii:
.LFB2957:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV2EPKfS1_Pfiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2957:
.size _Z79__device_stub__ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV2EPKfS1_PfiiiPKfS0_Pfiii, .-_Z79__device_stub__ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV2EPKfS1_PfiiiPKfS0_Pfiii
.globl _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV2EPKfS1_Pfiii
.hidden _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV2EPKfS1_Pfiii
.type _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV2EPKfS1_Pfiii, @function
_ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV2EPKfS1_Pfiii:
.LFB2958:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z79__device_stub__ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV2EPKfS1_PfiiiPKfS0_Pfiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2958:
.size _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV2EPKfS1_Pfiii, .-_ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV2EPKfS1_Pfiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV2EPKfS1_Pfiii"
.align 8
.LC3:
.string "_ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV1EPKfS1_Pfiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2960:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV2EPKfS1_Pfiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV1EPKfS1_Pfiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2960:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e412kernelRunnerIPFvPKfS2_PfiiiEEEvRKSt6vectorIfSaIfEESA_RS8_iiiT_.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "/home/ubuntu/Datasets/stackv2/train-structured/julitopower/CppLittleExercises/master/cuda_matmul/main.cu"
.section .rodata._ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e412kernelRunnerIPFvPKfS2_PfiiiEEEvRKSt6vectorIfSaIfEESA_RS8_iiiT_.str1.1,"aMS",@progbits,1
.LC5:
.string "GPUassert: %s %s %d\n"
.LC10:
.string "GridDim %d, %d, %d\n"
.LC11:
.string "BlockDim %d, %d, %d\n"
.section .text._ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e412kernelRunnerIPFvPKfS2_PfiiiEEEvRKSt6vectorIfSaIfEESA_RS8_iiiT_,"axG",@progbits,_ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e412kernelRunnerIPFvPKfS2_PfiiiEEEvRKSt6vectorIfSaIfEESA_RS8_iiiT_,comdat
.weak _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e412kernelRunnerIPFvPKfS2_PfiiiEEEvRKSt6vectorIfSaIfEESA_RS8_iiiT_
.hidden _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e412kernelRunnerIPFvPKfS2_PfiiiEEEvRKSt6vectorIfSaIfEESA_RS8_iiiT_
.type _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e412kernelRunnerIPFvPKfS2_PfiiiEEEvRKSt6vectorIfSaIfEESA_RS8_iiiT_, @function
_ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e412kernelRunnerIPFvPKfS2_PfiiiEEEvRKSt6vectorIfSaIfEESA_RS8_iiiT_:
.LFB3008:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r12
movl %ecx, 44(%rsp)
movl %r8d, 40(%rsp)
movl %r9d, 28(%rsp)
movq 176(%rsp), %rax
movq %rax, 32(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq 8(%rdi), %r14
subq (%rdi), %r14
movq 8(%rsi), %r13
movq (%rsi), %r15
movq 8(%rdx), %rax
movq %rax, 16(%rsp)
movq (%rdx), %rax
movq %rax, 8(%rsp)
leaq 56(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L44
subq %r15, %r13
leaq 64(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L45
movq 16(%rsp), %r15
movq 8(%rsp), %rax
subq %rax, %r15
leaq 72(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L46
movq (%rbx), %rsi
movl $1, %ecx
movq %r14, %rdx
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L47
movq 0(%rbp), %rsi
movl $1, %ecx
movq %r13, %rdx
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L48
movq (%r12), %rsi
movl $1, %ecx
movq %r15, %rdx
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L49
pxor %xmm0, %xmm0
cvtsi2ssl 28(%rsp), %xmm0
mulss .LC6(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC12(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC7(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L32
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC9(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L32:
cvttss2siq %xmm3, %r13
pxor %xmm0, %xmm0
cvtsi2ssl 44(%rsp), %xmm0
mulss .LC6(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC12(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC7(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L33
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC9(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L33:
cvttss2siq %xmm3, %r14
movl $1, %r8d
movl %r13d, %ecx
movl %r14d, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %r8d
movl $16, %ecx
movl $16, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L36
.L44:
movl %eax, %edi
movl %eax, %ebx
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $88, %r9d
leaq .LC4(%rip), %r8
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L45:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $89, %r9d
leaq .LC4(%rip), %r8
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r15d, %edi
call exit@PLT
.L46:
movl %eax, %ebx
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $90, %r9d
leaq .LC4(%rip), %r8
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L47:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $92, %r9d
leaq .LC4(%rip), %r8
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L48:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $93, %r9d
leaq .LC4(%rip), %r8
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L49:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $94, %r9d
leaq .LC4(%rip), %r8
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L34:
call cudaPeekAtLastError@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L50
call cudaDeviceSynchronize@PLT
addl $1, %ebx
cmpl $200, %ebx
je .L51
.L36:
movl %r14d, 80(%rsp)
movl %r13d, 84(%rsp)
movl $16, 92(%rsp)
movl $16, 96(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L34
movl 28(%rsp), %r9d
movl 40(%rsp), %r8d
movl %ebx, %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
movq 32(%rsp), %rax
call *%rax
jmp .L34
.L50:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $104, %r9d
leaq .LC4(%rip), %r8
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L51:
movq (%r12), %rdi
movl $2, %ecx
movq %r15, %rdx
movq 72(%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L52
movq 56(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L53
movq 64(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L54
movq 72(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L55
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L56
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $108, %r9d
leaq .LC4(%rip), %r8
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L53:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $109, %r9d
leaq .LC4(%rip), %r8
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L54:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $110, %r9d
leaq .LC4(%rip), %r8
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L55:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $111, %r9d
leaq .LC4(%rip), %r8
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L56:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3008:
.size _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e412kernelRunnerIPFvPKfS2_PfiiiEEEvRKSt6vectorIfSaIfEESA_RS8_iiiT_, .-_ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e412kernelRunnerIPFvPKfS2_PfiiiEEEvRKSt6vectorIfSaIfEESA_RS8_iiiT_
.text
.globl _ZN7wrapper8matMulV1ERKSt6vectorIfSaIfEES4_RS2_iii
.type _ZN7wrapper8matMulV1ERKSt6vectorIfSaIfEES4_RS2_iii, @function
_ZN7wrapper8matMulV1ERKSt6vectorIfSaIfEES4_RS2_iii:
.LFB2928:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
leaq _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV1EPKfS1_Pfiii(%rip), %rax
pushq %rax
.cfi_def_cfa_offset 32
call _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e412kernelRunnerIPFvPKfS2_PfiiiEEEvRKSt6vectorIfSaIfEESA_RS8_iiiT_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2928:
.size _ZN7wrapper8matMulV1ERKSt6vectorIfSaIfEES4_RS2_iii, .-_ZN7wrapper8matMulV1ERKSt6vectorIfSaIfEES4_RS2_iii
.globl _ZN7wrapper8matMulV2ERKSt6vectorIfSaIfEES4_RS2_iii
.type _ZN7wrapper8matMulV2ERKSt6vectorIfSaIfEES4_RS2_iii, @function
_ZN7wrapper8matMulV2ERKSt6vectorIfSaIfEES4_RS2_iii:
.LFB2929:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
leaq _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e48matmulV2EPKfS1_Pfiii(%rip), %rax
pushq %rax
.cfi_def_cfa_offset 32
call _ZN39_GLOBAL__N__fcd9f094_7_main_cu_4e68b6e412kernelRunnerIPFvPKfS2_PfiiiEEEvRKSt6vectorIfSaIfEESA_RS8_iiiT_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2929:
.size _ZN7wrapper8matMulV2ERKSt6vectorIfSaIfEES4_RS2_iii, .-_ZN7wrapper8matMulV2ERKSt6vectorIfSaIfEES4_RS2_iii
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC6:
.long 1031798784
.align 4
.LC7:
.long 1258291200
.align 4
.LC9:
.long 1065353216
.align 4
.LC12:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "stdio.h"
#include<iostream>
#include <cuda.h>
#include <cuda_runtime.h>
#include <math.h>
#define TILE_SIZE 2
__global__ void gpu_Matrix_Mul_nonshared(float *d_a, float *d_b, float *d_c, const int size)
{
int row, col;
col = TILE_SIZE * blockIdx.x + threadIdx.x;
row = TILE_SIZE * blockIdx.y + threadIdx.y;
for(int k = 0; k < size; k++){
d_c[row * size + col] += d_a[row * size + k] * d_b[k * size + col];
}
}
__global__ void gpu_Matrix_Mul_shared(float *d_a, float *d_b, float *d_c, const int size)
{
int row, col;
col = TILE_SIZE * blockIdx.x + threadIdx.x;
row = TILE_SIZE * blockIdx.y + threadIdx.y;
__shared__ float share_a[TILE_SIZE][TILE_SIZE];
__shared__ float share_b[TILE_SIZE][TILE_SIZE];
for(int i = 0; i < size/TILE_SIZE; i++){
share_a[threadIdx.y][threadIdx.x] = d_a[row * size + (i*TILE_SIZE + threadIdx.x)];
share_b[threadIdx.y][threadIdx.x] = d_b[(i*TILE_SIZE + threadIdx.x) * size + col];
__syncthreads();
for(int j = 0; j < TILE_SIZE; j++){
d_c[row * size + col] += share_a[threadIdx.y][j] * share_b[j][threadIdx.x];
}
__syncthreads();
}
}
int main(void){
const int size = 4;
float h_a[size][size];
float h_b[size][size];
float h_result[size][size];
float *d_a, *d_b, *d_result;
// Init array
for(int i=0; i < size; i++){
for(int j=0; j<size;j++){
h_a[i][j] = i;
h_b[i][j] = j;
}
}
cudaMalloc((void **)&d_a, size * size * sizeof(int));
cudaMalloc((void **)&d_b, size * size * sizeof(int));
cudaMalloc((void **)&d_result, size * size * sizeof(int));
cudaMemcpy(d_a, h_a, size * size * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, size * size * sizeof(int), cudaMemcpyHostToDevice);
dim3 dimGrid(size/TILE_SIZE, size/TILE_SIZE, 1);
dim3 dimBlock(TILE_SIZE, TILE_SIZE, 1);
// gpu_Matrix_Mul_nonshared << <dimGrid, dimBlock >> > (d_a, d_b, d_result, size);
gpu_Matrix_Mul_shared<<<dimGrid, dimBlock>>> (d_a, d_b, d_result,size);
cudaMemcpy(h_result, d_result, size*size*sizeof(int), cudaMemcpyDeviceToHost);
printf("The result of Matrix multiplication is: \n");
for (int i = 0; i< size; i++)
{
for (int j = 0; j < size; j++)
{
printf("%f ", h_result[i][j]);
}
printf("\n");
}
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_result);
return 0;
} | .file "tmpxft_000e2025_00000000-6_03_matrix_multiplication.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z24gpu_Matrix_Mul_nonsharedPfS_S_iPfS_S_i
.type _Z49__device_stub__Z24gpu_Matrix_Mul_nonsharedPfS_S_iPfS_S_i, @function
_Z49__device_stub__Z24gpu_Matrix_Mul_nonsharedPfS_S_iPfS_S_i:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z24gpu_Matrix_Mul_nonsharedPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z49__device_stub__Z24gpu_Matrix_Mul_nonsharedPfS_S_iPfS_S_i, .-_Z49__device_stub__Z24gpu_Matrix_Mul_nonsharedPfS_S_iPfS_S_i
.globl _Z24gpu_Matrix_Mul_nonsharedPfS_S_i
.type _Z24gpu_Matrix_Mul_nonsharedPfS_S_i, @function
_Z24gpu_Matrix_Mul_nonsharedPfS_S_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z24gpu_Matrix_Mul_nonsharedPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z24gpu_Matrix_Mul_nonsharedPfS_S_i, .-_Z24gpu_Matrix_Mul_nonsharedPfS_S_i
.globl _Z46__device_stub__Z21gpu_Matrix_Mul_sharedPfS_S_iPfS_S_i
.type _Z46__device_stub__Z21gpu_Matrix_Mul_sharedPfS_S_iPfS_S_i, @function
_Z46__device_stub__Z21gpu_Matrix_Mul_sharedPfS_S_iPfS_S_i:
.LFB3696:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21gpu_Matrix_Mul_sharedPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z46__device_stub__Z21gpu_Matrix_Mul_sharedPfS_S_iPfS_S_i, .-_Z46__device_stub__Z21gpu_Matrix_Mul_sharedPfS_S_iPfS_S_i
.globl _Z21gpu_Matrix_Mul_sharedPfS_S_i
.type _Z21gpu_Matrix_Mul_sharedPfS_S_i, @function
_Z21gpu_Matrix_Mul_sharedPfS_S_i:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z21gpu_Matrix_Mul_sharedPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z21gpu_Matrix_Mul_sharedPfS_S_i, .-_Z21gpu_Matrix_Mul_sharedPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "The result of Matrix multiplication is: \n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "%f "
.LC6:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $256, %rsp
.cfi_def_cfa_offset 304
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
leaq 48(%rsp), %rdx
leaq 112(%rsp), %rax
movl $0, %ecx
movss .LC1(%rip), %xmm3
movss .LC2(%rip), %xmm2
movss .LC3(%rip), %xmm1
.L20:
pxor %xmm0, %xmm0
cvtsi2ssl %ecx, %xmm0
movss %xmm0, (%rdx)
movl $0x00000000, (%rax)
movss %xmm0, 4(%rdx)
movss %xmm3, 4(%rax)
movss %xmm0, 8(%rdx)
movss %xmm2, 8(%rax)
movss %xmm0, 12(%rdx)
movss %xmm1, 12(%rax)
addl $1, %ecx
addq $16, %rdx
addq $16, %rax
cmpl $4, %ecx
jne .L20
movq %rsp, %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 112(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, 24(%rsp)
movl $2, 28(%rsp)
movl $1, 32(%rsp)
movl $2, 36(%rsp)
movl $2, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L21:
leaq 176(%rsp), %rdi
movl $2, %ecx
movl $64, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 192(%rsp), %rbp
leaq 256(%rsp), %r14
leaq .LC5(%rip), %r12
leaq .LC6(%rip), %r13
.L22:
leaq -16(%rbp), %rbx
.L23:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L23
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rbp
cmpq %r14, %rbp
jne .L22
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $256, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movl $4, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z46__device_stub__Z21gpu_Matrix_Mul_sharedPfS_S_iPfS_S_i
jmp .L21
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC7:
.string "_Z21gpu_Matrix_Mul_sharedPfS_S_i"
.align 8
.LC8:
.string "_Z24gpu_Matrix_Mul_nonsharedPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z21gpu_Matrix_Mul_sharedPfS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z24gpu_Matrix_Mul_nonsharedPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1073741824
.align 4
.LC3:
.long 1077936128
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "stdio.h"
#include<iostream>
#include <cuda.h>
#include <cuda_runtime.h>
#include <math.h>
#define TILE_SIZE 2
__global__ void gpu_Matrix_Mul_nonshared(float *d_a, float *d_b, float *d_c, const int size)
{
int row, col;
col = TILE_SIZE * blockIdx.x + threadIdx.x;
row = TILE_SIZE * blockIdx.y + threadIdx.y;
for(int k = 0; k < size; k++){
d_c[row * size + col] += d_a[row * size + k] * d_b[k * size + col];
}
}
__global__ void gpu_Matrix_Mul_shared(float *d_a, float *d_b, float *d_c, const int size)
{
int row, col;
col = TILE_SIZE * blockIdx.x + threadIdx.x;
row = TILE_SIZE * blockIdx.y + threadIdx.y;
__shared__ float share_a[TILE_SIZE][TILE_SIZE];
__shared__ float share_b[TILE_SIZE][TILE_SIZE];
for(int i = 0; i < size/TILE_SIZE; i++){
share_a[threadIdx.y][threadIdx.x] = d_a[row * size + (i*TILE_SIZE + threadIdx.x)];
share_b[threadIdx.y][threadIdx.x] = d_b[(i*TILE_SIZE + threadIdx.x) * size + col];
__syncthreads();
for(int j = 0; j < TILE_SIZE; j++){
d_c[row * size + col] += share_a[threadIdx.y][j] * share_b[j][threadIdx.x];
}
__syncthreads();
}
}
int main(void){
const int size = 4;
float h_a[size][size];
float h_b[size][size];
float h_result[size][size];
float *d_a, *d_b, *d_result;
// Init array
for(int i=0; i < size; i++){
for(int j=0; j<size;j++){
h_a[i][j] = i;
h_b[i][j] = j;
}
}
cudaMalloc((void **)&d_a, size * size * sizeof(int));
cudaMalloc((void **)&d_b, size * size * sizeof(int));
cudaMalloc((void **)&d_result, size * size * sizeof(int));
cudaMemcpy(d_a, h_a, size * size * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, size * size * sizeof(int), cudaMemcpyHostToDevice);
dim3 dimGrid(size/TILE_SIZE, size/TILE_SIZE, 1);
dim3 dimBlock(TILE_SIZE, TILE_SIZE, 1);
// gpu_Matrix_Mul_nonshared << <dimGrid, dimBlock >> > (d_a, d_b, d_result, size);
gpu_Matrix_Mul_shared<<<dimGrid, dimBlock>>> (d_a, d_b, d_result,size);
cudaMemcpy(h_result, d_result, size*size*sizeof(int), cudaMemcpyDeviceToHost);
printf("The result of Matrix multiplication is: \n");
for (int i = 0; i< size; i++)
{
for (int j = 0; j < size; j++)
{
printf("%f ", h_result[i][j]);
}
printf("\n");
}
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_result);
return 0;
} | #include "stdio.h"
#include<iostream>
#include <hip/hip_runtime.h>
#include <math.h>
#define TILE_SIZE 2
__global__ void gpu_Matrix_Mul_nonshared(float *d_a, float *d_b, float *d_c, const int size)
{
int row, col;
col = TILE_SIZE * blockIdx.x + threadIdx.x;
row = TILE_SIZE * blockIdx.y + threadIdx.y;
for(int k = 0; k < size; k++){
d_c[row * size + col] += d_a[row * size + k] * d_b[k * size + col];
}
}
__global__ void gpu_Matrix_Mul_shared(float *d_a, float *d_b, float *d_c, const int size)
{
int row, col;
col = TILE_SIZE * blockIdx.x + threadIdx.x;
row = TILE_SIZE * blockIdx.y + threadIdx.y;
__shared__ float share_a[TILE_SIZE][TILE_SIZE];
__shared__ float share_b[TILE_SIZE][TILE_SIZE];
for(int i = 0; i < size/TILE_SIZE; i++){
share_a[threadIdx.y][threadIdx.x] = d_a[row * size + (i*TILE_SIZE + threadIdx.x)];
share_b[threadIdx.y][threadIdx.x] = d_b[(i*TILE_SIZE + threadIdx.x) * size + col];
__syncthreads();
for(int j = 0; j < TILE_SIZE; j++){
d_c[row * size + col] += share_a[threadIdx.y][j] * share_b[j][threadIdx.x];
}
__syncthreads();
}
}
int main(void){
const int size = 4;
float h_a[size][size];
float h_b[size][size];
float h_result[size][size];
float *d_a, *d_b, *d_result;
// Init array
for(int i=0; i < size; i++){
for(int j=0; j<size;j++){
h_a[i][j] = i;
h_b[i][j] = j;
}
}
hipMalloc((void **)&d_a, size * size * sizeof(int));
hipMalloc((void **)&d_b, size * size * sizeof(int));
hipMalloc((void **)&d_result, size * size * sizeof(int));
hipMemcpy(d_a, h_a, size * size * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, size * size * sizeof(int), hipMemcpyHostToDevice);
dim3 dimGrid(size/TILE_SIZE, size/TILE_SIZE, 1);
dim3 dimBlock(TILE_SIZE, TILE_SIZE, 1);
// gpu_Matrix_Mul_nonshared << <dimGrid, dimBlock >> > (d_a, d_b, d_result, size);
gpu_Matrix_Mul_shared<<<dimGrid, dimBlock>>> (d_a, d_b, d_result,size);
hipMemcpy(h_result, d_result, size*size*sizeof(int), hipMemcpyDeviceToHost);
printf("The result of Matrix multiplication is: \n");
for (int i = 0; i< size; i++)
{
for (int j = 0; j < size; j++)
{
printf("%f ", h_result[i][j]);
}
printf("\n");
}
hipFree(d_a);
hipFree(d_b);
hipFree(d_result);
return 0;
} |
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