system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include <stdio.h>
#include <time.h>
#include <stdlib.h>
#include <sys/time.h>
//Tamaño de matrices (cuadradas)
#define N 1024
//Kernel
__global__ void mul(int * A, int * B, int * C){
int i = blockIdx.x;
int j = threadIdx.x;
//TODO -> Calcular elemento C(i,j)
}
int main(){
struct timeval t1, t2;
int *hA, *hB, *hC, *hC2; //Host Matrix
int *dA, *dB, *dC; //Device Matrix
//Reserva de memoria Host
hA = (int*)malloc(N*N*sizeof(int));
hB = (int*)malloc(N*N*sizeof(int));
hC = (int*)malloc(N*N*sizeof(int));
hC2 = (int*)malloc(N*N*sizeof(int));
//Inicialización de matrices
srand(time(NULL));
for (int i = 0; i < N; i++){
for (int j = 0; j < N; j++){
hA[i*N+j] = rand();
hB[i*N+j] = rand();
}
}
//Reserva de memoria GPU
//TODO -> Reservar Memoria (dA, dB, dC)
//Copia Host -> GPU
//TODO -> Copiar hA a dA y hB a dB
gettimeofday(&t1, 0);
//Ejecución Kernel
mul<<<N, N>>>(dA, dB, dC);
cudaDeviceSynchronize();
gettimeofday(&t2, 0);
//Copia Device -> Host
//TODO -> Copiar dC a hC
//Multiplicación en Host
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
hC2[i*N + j] = 0;
for(int k = 0; k < N; k++){
hC2[i*N + j] += hA[i*N + k] * hB[k*N + j];
}
}
}
//Comprobación de errores
bool error = false;
for(int i = 0; i < N*N; i++){
if(hC[i] != hC2[i]){
error = true;
break;
}
}
if(error)
printf("La multiplicación de matrices ha fallado.\n");
else
printf("Multiplicación de matrices correcta.\n");
double time = (1000000.0*(t2.tv_sec-t1.tv_sec) + t2.tv_usec-t1.tv_usec)/1000.0;
printf("Tiempo: %f ms\n", time);
//Liberar memoria
free(hA);
free(hB);
free(hC);
//TODO -> Liberar dA, dB y dC
} | .file "tmpxft_000d3eff_00000000-6_ToDo_simpleMatrixMul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3mulPiS_S_PiS_S_
.type _Z26__device_stub__Z3mulPiS_S_PiS_S_, @function
_Z26__device_stub__Z3mulPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3mulPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3mulPiS_S_PiS_S_, .-_Z26__device_stub__Z3mulPiS_S_PiS_S_
.globl _Z3mulPiS_S_
.type _Z3mulPiS_S_, @function
_Z3mulPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3mulPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3mulPiS_S_, .-_Z3mulPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Tiempo: %f ms\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "La multiplicaci\303\263n de matrices ha fallado.\n"
.align 8
.LC4:
.string "Multiplicaci\303\263n de matrices correcta.\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %r13
movl $4194304, %edi
call malloc@PLT
movq %rax, %r14
movl $4194304, %edi
call malloc@PLT
movq %rax, (%rsp)
movl $4194304, %edi
call malloc@PLT
movq %rax, 8(%rsp)
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
leaq 4194304(%r13), %r15
movq %r14, %r12
movq %r13, %rbp
.L12:
movl $0, %ebx
.L13:
call rand@PLT
movl %eax, 0(%rbp,%rbx)
call rand@PLT
movl %eax, (%r12,%rbx)
addq $4, %rbx
cmpq $4096, %rbx
jne .L13
addq $4096, %rbp
addq $4096, %r12
cmpq %r15, %rbp
jne .L12
leaq 32(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $1024, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L15:
call cudaDeviceSynchronize@PLT
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 8(%rsp), %rbp
movl $0, %ebx
jmp .L16
.L32:
movl $0, %edx
movl $0, %esi
movl $0, %edi
call _Z26__device_stub__Z3mulPiS_S_PiS_S_
jmp .L15
.L34:
movl %esi, (%r10)
addl $1, %r8d
addq $4, %r9
addq $4, %rdi
cmpl $1024, %r8d
je .L33
.L18:
movq %r9, %r10
leaq -4194304(%rdi), %rax
movq %r11, %rcx
movl $0, %esi
.L17:
movl (%rcx), %edx
imull (%rax), %edx
addl %edx, %esi
addq $4, %rcx
addq $4096, %rax
cmpq %rdi, %rax
jne .L17
jmp .L34
.L33:
addq $1, %rbx
addq $4096, %rbp
cmpq $1024, %rbx
je .L24
.L16:
leaq 4194304(%r14), %rdi
movq %rbx, %r11
salq $12, %r11
addq %r13, %r11
movq %rbp, %r9
movl $0, %r8d
jmp .L18
.L24:
movl $0, %eax
.L19:
movq (%rsp), %rbx
movq 8(%rsp), %rsi
movl (%rsi,%rax), %esi
cmpl %esi, (%rbx,%rax)
jne .L20
addq $4, %rax
cmpq $4194304, %rax
jne .L19
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L22
.L20:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L22:
movq 48(%rsp), %rax
subq 32(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 56(%rsp), %xmm1
addsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 40(%rsp), %xmm1
subsd %xmm1, %xmm0
divsd .LC1(%rip), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z3mulPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z3mulPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.align 8
.LC1:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <stdio.h>
#include <time.h>
#include <stdlib.h>
#include <sys/time.h>
//Tamaño de matrices (cuadradas)
#define N 1024
//Kernel
__global__ void mul(int * A, int * B, int * C){
int i = blockIdx.x;
int j = threadIdx.x;
//TODO -> Calcular elemento C(i,j)
}
int main(){
struct timeval t1, t2;
int *hA, *hB, *hC, *hC2; //Host Matrix
int *dA, *dB, *dC; //Device Matrix
//Reserva de memoria Host
hA = (int*)malloc(N*N*sizeof(int));
hB = (int*)malloc(N*N*sizeof(int));
hC = (int*)malloc(N*N*sizeof(int));
hC2 = (int*)malloc(N*N*sizeof(int));
//Inicialización de matrices
srand(time(NULL));
for (int i = 0; i < N; i++){
for (int j = 0; j < N; j++){
hA[i*N+j] = rand();
hB[i*N+j] = rand();
}
}
//Reserva de memoria GPU
//TODO -> Reservar Memoria (dA, dB, dC)
//Copia Host -> GPU
//TODO -> Copiar hA a dA y hB a dB
gettimeofday(&t1, 0);
//Ejecución Kernel
mul<<<N, N>>>(dA, dB, dC);
cudaDeviceSynchronize();
gettimeofday(&t2, 0);
//Copia Device -> Host
//TODO -> Copiar dC a hC
//Multiplicación en Host
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
hC2[i*N + j] = 0;
for(int k = 0; k < N; k++){
hC2[i*N + j] += hA[i*N + k] * hB[k*N + j];
}
}
}
//Comprobación de errores
bool error = false;
for(int i = 0; i < N*N; i++){
if(hC[i] != hC2[i]){
error = true;
break;
}
}
if(error)
printf("La multiplicación de matrices ha fallado.\n");
else
printf("Multiplicación de matrices correcta.\n");
double time = (1000000.0*(t2.tv_sec-t1.tv_sec) + t2.tv_usec-t1.tv_usec)/1000.0;
printf("Tiempo: %f ms\n", time);
//Liberar memoria
free(hA);
free(hB);
free(hC);
//TODO -> Liberar dA, dB y dC
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
#include <stdlib.h>
#include <sys/time.h>
//Tamaño de matrices (cuadradas)
#define N 1024
//Kernel
__global__ void mul(int * A, int * B, int * C){
int i = blockIdx.x;
int j = threadIdx.x;
//TODO -> Calcular elemento C(i,j)
}
int main(){
struct timeval t1, t2;
int *hA, *hB, *hC, *hC2; //Host Matrix
int *dA, *dB, *dC; //Device Matrix
//Reserva de memoria Host
hA = (int*)malloc(N*N*sizeof(int));
hB = (int*)malloc(N*N*sizeof(int));
hC = (int*)malloc(N*N*sizeof(int));
hC2 = (int*)malloc(N*N*sizeof(int));
//Inicialización de matrices
srand(time(NULL));
for (int i = 0; i < N; i++){
for (int j = 0; j < N; j++){
hA[i*N+j] = rand();
hB[i*N+j] = rand();
}
}
//Reserva de memoria GPU
//TODO -> Reservar Memoria (dA, dB, dC)
//Copia Host -> GPU
//TODO -> Copiar hA a dA y hB a dB
gettimeofday(&t1, 0);
//Ejecución Kernel
mul<<<N, N>>>(dA, dB, dC);
hipDeviceSynchronize();
gettimeofday(&t2, 0);
//Copia Device -> Host
//TODO -> Copiar dC a hC
//Multiplicación en Host
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
hC2[i*N + j] = 0;
for(int k = 0; k < N; k++){
hC2[i*N + j] += hA[i*N + k] * hB[k*N + j];
}
}
}
//Comprobación de errores
bool error = false;
for(int i = 0; i < N*N; i++){
if(hC[i] != hC2[i]){
error = true;
break;
}
}
if(error)
printf("La multiplicación de matrices ha fallado.\n");
else
printf("Multiplicación de matrices correcta.\n");
double time = (1000000.0*(t2.tv_sec-t1.tv_sec) + t2.tv_usec-t1.tv_usec)/1000.0;
printf("Tiempo: %f ms\n", time);
//Liberar memoria
free(hA);
free(hB);
free(hC);
//TODO -> Liberar dA, dB y dC
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
#include <stdlib.h>
#include <sys/time.h>
//Tamaño de matrices (cuadradas)
#define N 1024
//Kernel
__global__ void mul(int * A, int * B, int * C){
int i = blockIdx.x;
int j = threadIdx.x;
//TODO -> Calcular elemento C(i,j)
}
int main(){
struct timeval t1, t2;
int *hA, *hB, *hC, *hC2; //Host Matrix
int *dA, *dB, *dC; //Device Matrix
//Reserva de memoria Host
hA = (int*)malloc(N*N*sizeof(int));
hB = (int*)malloc(N*N*sizeof(int));
hC = (int*)malloc(N*N*sizeof(int));
hC2 = (int*)malloc(N*N*sizeof(int));
//Inicialización de matrices
srand(time(NULL));
for (int i = 0; i < N; i++){
for (int j = 0; j < N; j++){
hA[i*N+j] = rand();
hB[i*N+j] = rand();
}
}
//Reserva de memoria GPU
//TODO -> Reservar Memoria (dA, dB, dC)
//Copia Host -> GPU
//TODO -> Copiar hA a dA y hB a dB
gettimeofday(&t1, 0);
//Ejecución Kernel
mul<<<N, N>>>(dA, dB, dC);
hipDeviceSynchronize();
gettimeofday(&t2, 0);
//Copia Device -> Host
//TODO -> Copiar dC a hC
//Multiplicación en Host
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
hC2[i*N + j] = 0;
for(int k = 0; k < N; k++){
hC2[i*N + j] += hA[i*N + k] * hB[k*N + j];
}
}
}
//Comprobación de errores
bool error = false;
for(int i = 0; i < N*N; i++){
if(hC[i] != hC2[i]){
error = true;
break;
}
}
if(error)
printf("La multiplicación de matrices ha fallado.\n");
else
printf("Multiplicación de matrices correcta.\n");
double time = (1000000.0*(t2.tv_sec-t1.tv_sec) + t2.tv_usec-t1.tv_usec)/1000.0;
printf("Tiempo: %f ms\n", time);
//Liberar memoria
free(hA);
free(hB);
free(hC);
//TODO -> Liberar dA, dB y dC
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3mulPiS_S_
.globl _Z3mulPiS_S_
.p2align 8
.type _Z3mulPiS_S_,@function
_Z3mulPiS_S_:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3mulPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3mulPiS_S_, .Lfunc_end0-_Z3mulPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3mulPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z3mulPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
#include <stdlib.h>
#include <sys/time.h>
//Tamaño de matrices (cuadradas)
#define N 1024
//Kernel
__global__ void mul(int * A, int * B, int * C){
int i = blockIdx.x;
int j = threadIdx.x;
//TODO -> Calcular elemento C(i,j)
}
int main(){
struct timeval t1, t2;
int *hA, *hB, *hC, *hC2; //Host Matrix
int *dA, *dB, *dC; //Device Matrix
//Reserva de memoria Host
hA = (int*)malloc(N*N*sizeof(int));
hB = (int*)malloc(N*N*sizeof(int));
hC = (int*)malloc(N*N*sizeof(int));
hC2 = (int*)malloc(N*N*sizeof(int));
//Inicialización de matrices
srand(time(NULL));
for (int i = 0; i < N; i++){
for (int j = 0; j < N; j++){
hA[i*N+j] = rand();
hB[i*N+j] = rand();
}
}
//Reserva de memoria GPU
//TODO -> Reservar Memoria (dA, dB, dC)
//Copia Host -> GPU
//TODO -> Copiar hA a dA y hB a dB
gettimeofday(&t1, 0);
//Ejecución Kernel
mul<<<N, N>>>(dA, dB, dC);
hipDeviceSynchronize();
gettimeofday(&t2, 0);
//Copia Device -> Host
//TODO -> Copiar dC a hC
//Multiplicación en Host
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
hC2[i*N + j] = 0;
for(int k = 0; k < N; k++){
hC2[i*N + j] += hA[i*N + k] * hB[k*N + j];
}
}
}
//Comprobación de errores
bool error = false;
for(int i = 0; i < N*N; i++){
if(hC[i] != hC2[i]){
error = true;
break;
}
}
if(error)
printf("La multiplicación de matrices ha fallado.\n");
else
printf("Multiplicación de matrices correcta.\n");
double time = (1000000.0*(t2.tv_sec-t1.tv_sec) + t2.tv_usec-t1.tv_usec)/1000.0;
printf("Tiempo: %f ms\n", time);
//Liberar memoria
free(hA);
free(hB);
free(hC);
//TODO -> Liberar dA, dB y dC
} | .text
.file "ToDo_simpleMatrixMul.hip"
.globl _Z18__device_stub__mulPiS_S_ # -- Begin function _Z18__device_stub__mulPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__mulPiS_S_,@function
_Z18__device_stub__mulPiS_S_: # @_Z18__device_stub__mulPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3mulPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__mulPiS_S_, .Lfunc_end0-_Z18__device_stub__mulPiS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI1_1:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbp
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, 32(%rsp) # 8-byte Spill
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r12
xorl %r13d, %r13d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movq %rbp, 40(%rsp) # 8-byte Spill
movq %rbx, %r14
.p2align 4, 0x90
.LBB1_1: # %.preheader56
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movl %eax, (%rbp,%r15,4)
callq rand
movl %eax, (%r14,%r15,4)
incq %r15
cmpq $1024, %r15 # imm = 0x400
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %r13
addq $4096, %r14 # imm = 0x1000
addq $4096, %rbp # imm = 0x1000
cmpq $1024, %r13 # imm = 0x400
jne .LBB1_1
# %bb.4:
leaq 96(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movabsq $4294968320, %rdi # imm = 0x100000400
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
leaq 128(%rsp), %rax
movq %rax, (%rsp)
leaq 120(%rsp), %rax
movq %rax, 8(%rsp)
leaq 112(%rsp), %rax
movq %rax, 16(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movq %rsp, %r9
movl $_Z3mulPiS_S_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
callq hipDeviceSynchronize
xorl %r13d, %r13d
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq 40(%rsp), %r14 # 8-byte Reload
movq %r14, %rax
movq 32(%rsp), %r15 # 8-byte Reload
.p2align 4, 0x90
.LBB1_7: # %.preheader55
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
# Child Loop BB1_9 Depth 3
movq %r13, %rcx
shlq $10, %rcx
movq %rbx, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_9 Depth 3
movq %rsi, %rdi
orq %rcx, %rdi
movl $0, (%r12,%rdi,4)
xorl %r8d, %r8d
movq %rdx, %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB1_9: # Parent Loop BB1_7 Depth=1
# Parent Loop BB1_8 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r9), %r11d
imull (%rax,%r8,4), %r11d
addl %r11d, %r10d
incq %r8
addq $4096, %r9 # imm = 0x1000
cmpq $1024, %r8 # imm = 0x400
jne .LBB1_9
# %bb.10: # in Loop: Header=BB1_8 Depth=2
movl %r10d, (%r12,%rdi,4)
incq %rsi
addq $4, %rdx
cmpq $1024, %rsi # imm = 0x400
jne .LBB1_8
# %bb.11: # in Loop: Header=BB1_7 Depth=1
incq %r13
addq $4096, %rax # imm = 0x1000
cmpq $1024, %r13 # imm = 0x400
jne .LBB1_7
# %bb.12: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_13: # %.preheader
# =>This Inner Loop Header: Depth=1
movl (%r15,%rax,4), %ecx
cmpl (%r12,%rax,4), %ecx
jne .LBB1_16
# %bb.14: # in Loop: Header=BB1_13 Depth=1
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_13
# %bb.15:
movl $.Lstr, %edi
jmp .LBB1_17
.LBB1_16:
movl $.Lstr.1, %edi
.LBB1_17: # %.critedge
callq puts@PLT
movq (%rsp), %rax
subq 96(%rsp), %rax
cvtsi2sd %rax, %xmm1
mulsd .LCPI1_0(%rip), %xmm1
cvtsi2sdq 8(%rsp), %xmm0
cvtsi2sdq 104(%rsp), %xmm2
addsd %xmm1, %xmm0
subsd %xmm2, %xmm0
divsd .LCPI1_1(%rip), %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq %r14, %rdi
callq free
movq %rbx, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3mulPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3mulPiS_S_,@object # @_Z3mulPiS_S_
.section .rodata,"a",@progbits
.globl _Z3mulPiS_S_
.p2align 3, 0x0
_Z3mulPiS_S_:
.quad _Z18__device_stub__mulPiS_S_
.size _Z3mulPiS_S_, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Tiempo: %f ms\n"
.size .L.str.2, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3mulPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Multiplicaci\303\263n de matrices correcta."
.size .Lstr, 38
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "La multiplicaci\303\263n de matrices ha fallado."
.size .Lstr.1, 43
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__mulPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3mulPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3mulPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3mulPiS_S_
.globl _Z3mulPiS_S_
.p2align 8
.type _Z3mulPiS_S_,@function
_Z3mulPiS_S_:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3mulPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3mulPiS_S_, .Lfunc_end0-_Z3mulPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3mulPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z3mulPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d3eff_00000000-6_ToDo_simpleMatrixMul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3mulPiS_S_PiS_S_
.type _Z26__device_stub__Z3mulPiS_S_PiS_S_, @function
_Z26__device_stub__Z3mulPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3mulPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3mulPiS_S_PiS_S_, .-_Z26__device_stub__Z3mulPiS_S_PiS_S_
.globl _Z3mulPiS_S_
.type _Z3mulPiS_S_, @function
_Z3mulPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3mulPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3mulPiS_S_, .-_Z3mulPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Tiempo: %f ms\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "La multiplicaci\303\263n de matrices ha fallado.\n"
.align 8
.LC4:
.string "Multiplicaci\303\263n de matrices correcta.\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %r13
movl $4194304, %edi
call malloc@PLT
movq %rax, %r14
movl $4194304, %edi
call malloc@PLT
movq %rax, (%rsp)
movl $4194304, %edi
call malloc@PLT
movq %rax, 8(%rsp)
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
leaq 4194304(%r13), %r15
movq %r14, %r12
movq %r13, %rbp
.L12:
movl $0, %ebx
.L13:
call rand@PLT
movl %eax, 0(%rbp,%rbx)
call rand@PLT
movl %eax, (%r12,%rbx)
addq $4, %rbx
cmpq $4096, %rbx
jne .L13
addq $4096, %rbp
addq $4096, %r12
cmpq %r15, %rbp
jne .L12
leaq 32(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $1024, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L15:
call cudaDeviceSynchronize@PLT
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 8(%rsp), %rbp
movl $0, %ebx
jmp .L16
.L32:
movl $0, %edx
movl $0, %esi
movl $0, %edi
call _Z26__device_stub__Z3mulPiS_S_PiS_S_
jmp .L15
.L34:
movl %esi, (%r10)
addl $1, %r8d
addq $4, %r9
addq $4, %rdi
cmpl $1024, %r8d
je .L33
.L18:
movq %r9, %r10
leaq -4194304(%rdi), %rax
movq %r11, %rcx
movl $0, %esi
.L17:
movl (%rcx), %edx
imull (%rax), %edx
addl %edx, %esi
addq $4, %rcx
addq $4096, %rax
cmpq %rdi, %rax
jne .L17
jmp .L34
.L33:
addq $1, %rbx
addq $4096, %rbp
cmpq $1024, %rbx
je .L24
.L16:
leaq 4194304(%r14), %rdi
movq %rbx, %r11
salq $12, %r11
addq %r13, %r11
movq %rbp, %r9
movl $0, %r8d
jmp .L18
.L24:
movl $0, %eax
.L19:
movq (%rsp), %rbx
movq 8(%rsp), %rsi
movl (%rsi,%rax), %esi
cmpl %esi, (%rbx,%rax)
jne .L20
addq $4, %rax
cmpq $4194304, %rax
jne .L19
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L22
.L20:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L22:
movq 48(%rsp), %rax
subq 32(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 56(%rsp), %xmm1
addsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 40(%rsp), %xmm1
subsd %xmm1, %xmm0
divsd .LC1(%rip), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z3mulPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z3mulPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.align 8
.LC1:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ToDo_simpleMatrixMul.hip"
.globl _Z18__device_stub__mulPiS_S_ # -- Begin function _Z18__device_stub__mulPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__mulPiS_S_,@function
_Z18__device_stub__mulPiS_S_: # @_Z18__device_stub__mulPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3mulPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__mulPiS_S_, .Lfunc_end0-_Z18__device_stub__mulPiS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI1_1:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbp
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, 32(%rsp) # 8-byte Spill
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r12
xorl %r13d, %r13d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movq %rbp, 40(%rsp) # 8-byte Spill
movq %rbx, %r14
.p2align 4, 0x90
.LBB1_1: # %.preheader56
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movl %eax, (%rbp,%r15,4)
callq rand
movl %eax, (%r14,%r15,4)
incq %r15
cmpq $1024, %r15 # imm = 0x400
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %r13
addq $4096, %r14 # imm = 0x1000
addq $4096, %rbp # imm = 0x1000
cmpq $1024, %r13 # imm = 0x400
jne .LBB1_1
# %bb.4:
leaq 96(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movabsq $4294968320, %rdi # imm = 0x100000400
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
leaq 128(%rsp), %rax
movq %rax, (%rsp)
leaq 120(%rsp), %rax
movq %rax, 8(%rsp)
leaq 112(%rsp), %rax
movq %rax, 16(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movq %rsp, %r9
movl $_Z3mulPiS_S_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
callq hipDeviceSynchronize
xorl %r13d, %r13d
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq 40(%rsp), %r14 # 8-byte Reload
movq %r14, %rax
movq 32(%rsp), %r15 # 8-byte Reload
.p2align 4, 0x90
.LBB1_7: # %.preheader55
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
# Child Loop BB1_9 Depth 3
movq %r13, %rcx
shlq $10, %rcx
movq %rbx, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_9 Depth 3
movq %rsi, %rdi
orq %rcx, %rdi
movl $0, (%r12,%rdi,4)
xorl %r8d, %r8d
movq %rdx, %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB1_9: # Parent Loop BB1_7 Depth=1
# Parent Loop BB1_8 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r9), %r11d
imull (%rax,%r8,4), %r11d
addl %r11d, %r10d
incq %r8
addq $4096, %r9 # imm = 0x1000
cmpq $1024, %r8 # imm = 0x400
jne .LBB1_9
# %bb.10: # in Loop: Header=BB1_8 Depth=2
movl %r10d, (%r12,%rdi,4)
incq %rsi
addq $4, %rdx
cmpq $1024, %rsi # imm = 0x400
jne .LBB1_8
# %bb.11: # in Loop: Header=BB1_7 Depth=1
incq %r13
addq $4096, %rax # imm = 0x1000
cmpq $1024, %r13 # imm = 0x400
jne .LBB1_7
# %bb.12: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_13: # %.preheader
# =>This Inner Loop Header: Depth=1
movl (%r15,%rax,4), %ecx
cmpl (%r12,%rax,4), %ecx
jne .LBB1_16
# %bb.14: # in Loop: Header=BB1_13 Depth=1
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_13
# %bb.15:
movl $.Lstr, %edi
jmp .LBB1_17
.LBB1_16:
movl $.Lstr.1, %edi
.LBB1_17: # %.critedge
callq puts@PLT
movq (%rsp), %rax
subq 96(%rsp), %rax
cvtsi2sd %rax, %xmm1
mulsd .LCPI1_0(%rip), %xmm1
cvtsi2sdq 8(%rsp), %xmm0
cvtsi2sdq 104(%rsp), %xmm2
addsd %xmm1, %xmm0
subsd %xmm2, %xmm0
divsd .LCPI1_1(%rip), %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq %r14, %rdi
callq free
movq %rbx, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3mulPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3mulPiS_S_,@object # @_Z3mulPiS_S_
.section .rodata,"a",@progbits
.globl _Z3mulPiS_S_
.p2align 3, 0x0
_Z3mulPiS_S_:
.quad _Z18__device_stub__mulPiS_S_
.size _Z3mulPiS_S_, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Tiempo: %f ms\n"
.size .L.str.2, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3mulPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Multiplicaci\303\263n de matrices correcta."
.size .Lstr, 38
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "La multiplicaci\303\263n de matrices ha fallado."
.size .Lstr.1, 43
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__mulPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3mulPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void dyadicAdd(int * counter, const int length, const int shift)
{
if (shift > 0) {
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
int adds = 2*shift;
int Index = adds*(xIndex+1)-1;
if (Index < length) {
counter[Index] = counter[Index] + counter[Index-shift];
}
}
} | code for sm_80
Function : _Z9dyadicAddPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0070*/ LEA R0, R0, 0x2, 0x1 ; /* 0x0000000200007811 */
/* 0x000fca00078e08ff */
/*0080*/ IMAD R0, R0, R5, -0x1 ; /* 0xffffffff00007424 */
/* 0x000fca00078e0205 */
/*0090*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*00c0*/ IADD3 R4, R0, -c[0x0][0x16c], RZ ; /* 0x80005b0000047a10 */
/* 0x000fe20007ffe0ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00e0*/ IMAD.WIDE R4, R4, R3, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0203 */
/*00f0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fe400078e0203 */
/*0100*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea4000c1e1900 */
/*0120*/ IADD3 R7, R4, R7, RZ ; /* 0x0000000704077210 */
/* 0x004fca0007ffe0ff */
/*0130*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void dyadicAdd(int * counter, const int length, const int shift)
{
if (shift > 0) {
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
int adds = 2*shift;
int Index = adds*(xIndex+1)-1;
if (Index < length) {
counter[Index] = counter[Index] + counter[Index-shift];
}
}
} | .file "tmpxft_001ab3bf_00000000-6_dyadicAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9dyadicAddPiiiPiii
.type _Z30__device_stub__Z9dyadicAddPiiiPiii, @function
_Z30__device_stub__Z9dyadicAddPiiiPiii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9dyadicAddPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z9dyadicAddPiiiPiii, .-_Z30__device_stub__Z9dyadicAddPiiiPiii
.globl _Z9dyadicAddPiii
.type _Z9dyadicAddPiii, @function
_Z9dyadicAddPiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9dyadicAddPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9dyadicAddPiii, .-_Z9dyadicAddPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9dyadicAddPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9dyadicAddPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void dyadicAdd(int * counter, const int length, const int shift)
{
if (shift > 0) {
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
int adds = 2*shift;
int Index = adds*(xIndex+1)-1;
if (Index < length) {
counter[Index] = counter[Index] + counter[Index-shift];
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void dyadicAdd(int * counter, const int length, const int shift)
{
if (shift > 0) {
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
int adds = 2*shift;
int Index = adds*(xIndex+1)-1;
if (Index < length) {
counter[Index] = counter[Index] + counter[Index-shift];
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void dyadicAdd(int * counter, const int length, const int shift)
{
if (shift > 0) {
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
int adds = 2*shift;
int Index = adds*(xIndex+1)-1;
if (Index < length) {
counter[Index] = counter[Index] + counter[Index-shift];
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9dyadicAddPiii
.globl _Z9dyadicAddPiii
.p2align 8
.type _Z9dyadicAddPiii,@function
_Z9dyadicAddPiii:
s_load_b32 s2, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, s2, v1, s[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v0, v2, 1, -1
v_cmp_gt_i32_e32 vcc_lo, s3, v0
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x0
v_subrev_nc_u32_e32 v2, s2, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_load_b32 v4, v[0:1], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v2, v4
global_store_b32 v[0:1], v2, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9dyadicAddPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9dyadicAddPiii, .Lfunc_end0-_Z9dyadicAddPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9dyadicAddPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9dyadicAddPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void dyadicAdd(int * counter, const int length, const int shift)
{
if (shift > 0) {
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
int adds = 2*shift;
int Index = adds*(xIndex+1)-1;
if (Index < length) {
counter[Index] = counter[Index] + counter[Index-shift];
}
}
} | .text
.file "dyadicAdd.hip"
.globl _Z24__device_stub__dyadicAddPiii # -- Begin function _Z24__device_stub__dyadicAddPiii
.p2align 4, 0x90
.type _Z24__device_stub__dyadicAddPiii,@function
_Z24__device_stub__dyadicAddPiii: # @_Z24__device_stub__dyadicAddPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9dyadicAddPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__dyadicAddPiii, .Lfunc_end0-_Z24__device_stub__dyadicAddPiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9dyadicAddPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9dyadicAddPiii,@object # @_Z9dyadicAddPiii
.section .rodata,"a",@progbits
.globl _Z9dyadicAddPiii
.p2align 3, 0x0
_Z9dyadicAddPiii:
.quad _Z24__device_stub__dyadicAddPiii
.size _Z9dyadicAddPiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9dyadicAddPiii"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__dyadicAddPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9dyadicAddPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9dyadicAddPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0070*/ LEA R0, R0, 0x2, 0x1 ; /* 0x0000000200007811 */
/* 0x000fca00078e08ff */
/*0080*/ IMAD R0, R0, R5, -0x1 ; /* 0xffffffff00007424 */
/* 0x000fca00078e0205 */
/*0090*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*00c0*/ IADD3 R4, R0, -c[0x0][0x16c], RZ ; /* 0x80005b0000047a10 */
/* 0x000fe20007ffe0ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00e0*/ IMAD.WIDE R4, R4, R3, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0203 */
/*00f0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fe400078e0203 */
/*0100*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea4000c1e1900 */
/*0120*/ IADD3 R7, R4, R7, RZ ; /* 0x0000000704077210 */
/* 0x004fca0007ffe0ff */
/*0130*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9dyadicAddPiii
.globl _Z9dyadicAddPiii
.p2align 8
.type _Z9dyadicAddPiii,@function
_Z9dyadicAddPiii:
s_load_b32 s2, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, s2, v1, s[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v0, v2, 1, -1
v_cmp_gt_i32_e32 vcc_lo, s3, v0
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x0
v_subrev_nc_u32_e32 v2, s2, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_load_b32 v4, v[0:1], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v2, v4
global_store_b32 v[0:1], v2, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9dyadicAddPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9dyadicAddPiii, .Lfunc_end0-_Z9dyadicAddPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9dyadicAddPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9dyadicAddPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001ab3bf_00000000-6_dyadicAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9dyadicAddPiiiPiii
.type _Z30__device_stub__Z9dyadicAddPiiiPiii, @function
_Z30__device_stub__Z9dyadicAddPiiiPiii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9dyadicAddPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z9dyadicAddPiiiPiii, .-_Z30__device_stub__Z9dyadicAddPiiiPiii
.globl _Z9dyadicAddPiii
.type _Z9dyadicAddPiii, @function
_Z9dyadicAddPiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9dyadicAddPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9dyadicAddPiii, .-_Z9dyadicAddPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9dyadicAddPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9dyadicAddPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "dyadicAdd.hip"
.globl _Z24__device_stub__dyadicAddPiii # -- Begin function _Z24__device_stub__dyadicAddPiii
.p2align 4, 0x90
.type _Z24__device_stub__dyadicAddPiii,@function
_Z24__device_stub__dyadicAddPiii: # @_Z24__device_stub__dyadicAddPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9dyadicAddPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__dyadicAddPiii, .Lfunc_end0-_Z24__device_stub__dyadicAddPiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9dyadicAddPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9dyadicAddPiii,@object # @_Z9dyadicAddPiii
.section .rodata,"a",@progbits
.globl _Z9dyadicAddPiii
.p2align 3, 0x0
_Z9dyadicAddPiii:
.quad _Z24__device_stub__dyadicAddPiii
.size _Z9dyadicAddPiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9dyadicAddPiii"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__dyadicAddPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9dyadicAddPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void prefixSumForward(float* arr,int step){
int bx = blockIdx.x;
int tx = threadIdx.x;
int BX = blockDim.x;
int i = bx*BX+tx;
int ii = i+1;
if( ii <= n && ii > n/float(step)) return;
arr[ii*step-1] += arr[ii*step-step/2-1];
if(step==n && n-1 == ii*step-1) {
arr[ii*step] = arr[ii*step-1];
arr[ii*step-1]= 0;
}
} | code for sm_80
Function : _Z16prefixSumForwardPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x1b0 ; /* 0x0000017000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GT.AND P0, PT, R0.reuse, 0xfff, PT ; /* 0x00000fff0000780c */
/* 0x040fe40003f04270 */
/*0070*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fd60007ffe0ff */
/*0080*/ @P0 BRA 0x1a0 ; /* 0x0000011000000947 */
/* 0x000fea0003800000 */
/*0090*/ I2F R3, c[0x0][0x168] ; /* 0x00005a0000037b06 */
/* 0x000e220000201400 */
/*00a0*/ UMOV UR4, 0x45800000 ; /* 0x4580000000047882 */
/* 0x000fe40000000000 */
/*00b0*/ IMAD.U32 R8, RZ, RZ, UR4 ; /* 0x00000004ff087e24 */
/* 0x000fca000f8e00ff */
/*00c0*/ I2F R2, R0 ; /* 0x0000000000027306 */
/* 0x000ff00000201400 */
/*00d0*/ MUFU.RCP R4, R3 ; /* 0x0000000300047308 */
/* 0x001e300000001000 */
/*00e0*/ FCHK P0, R8, R3 ; /* 0x0000000308007302 */
/* 0x000e620000000000 */
/*00f0*/ FFMA R5, -R3, R4, 1 ; /* 0x3f80000003057423 */
/* 0x001fc80000000104 */
/*0100*/ FFMA R5, R4, R5, R4 ; /* 0x0000000504057223 */
/* 0x000fc80000000004 */
/*0110*/ FFMA R4, R5, 4096, RZ ; /* 0x4580000005047823 */
/* 0x000fc800000000ff */
/*0120*/ FFMA R6, -R3, R4, 4096 ; /* 0x4580000003067423 */
/* 0x000fc80000000104 */
/*0130*/ FFMA R5, R5, R6, R4 ; /* 0x0000000605057223 */
/* 0x000fe20000000004 */
/*0140*/ @!P0 BRA 0x180 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*0150*/ MOV R4, 0x170 ; /* 0x0000017000047802 */
/* 0x000fe40000000f00 */
/*0160*/ CALL.REL.NOINC 0x330 ; /* 0x000001c000007944 */
/* 0x000fea0003c00000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x001fca00078e0007 */
/*0180*/ FSETP.GEU.AND P0, PT, R5, R2, PT ; /* 0x000000020500720b */
/* 0x000fda0003f0e000 */
/*0190*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*01a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01b0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff097624 */
/* 0x000fe400078e00ff */
/*01c0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe400078e00ff */
/*01d0*/ IMAD R6, R0, R9, -0x1 ; /* 0xffffffff00067424 */
/* 0x000fe200078e0209 */
/*01e0*/ LEA.HI R2, R9, c[0x0][0x168], RZ, 0x1 ; /* 0x00005a0009027a11 */
/* 0x000fc600078f08ff */
/*01f0*/ IMAD.WIDE R4, R6, R11, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x000fe200078e020b */
/*0200*/ SHF.R.S32.HI R2, RZ, 0x1, R2 ; /* 0x00000001ff027819 */
/* 0x000fc80000011402 */
/*0210*/ LOP3.LUT R3, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff037212 */
/* 0x000fe200078e33ff */
/*0220*/ LDG.E R7, [R4.64] ; /* 0x0000000604077981 */
/* 0x000ea8000c1e1900 */
/*0230*/ IMAD R3, R0, c[0x0][0x168], R3 ; /* 0x00005a0000037a24 */
/* 0x000fc800078e0203 */
/*0240*/ IMAD.WIDE R2, R3, R11, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fcc00078e020b */
/*0250*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*0260*/ ISETP.NE.AND P0, PT, R6, 0xfff, PT ; /* 0x00000fff0600780c */
/* 0x000fc80003f05270 */
/*0270*/ ISETP.NE.OR P0, PT, R9, 0x1000, P0 ; /* 0x000010000900780c */
/* 0x000fe20000705670 */
/*0280*/ FADD R7, R7, R2 ; /* 0x0000000207077221 */
/* 0x004fca0000000000 */
/*0290*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001ee000c101906 */
/*02a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02b0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x001fe400078e00ff */
/*02c0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fca00078e00ff */
/*02d0*/ LDG.E R5, [R4.64+0x3ffc] ; /* 0x003ffc0604057981 */
/* 0x000ea2000c1e1900 */
/*02e0*/ IMAD.SHL.U32 R2, R0, 0x1000, RZ ; /* 0x0000100000027824 */
/* 0x000fc800078e00ff */
/*02f0*/ IMAD.WIDE R2, R2, R11, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e020b */
/*0300*/ STG.E [R2.64+-0x4], RZ ; /* 0xfffffcff02007986 */
/* 0x000fe8000c101906 */
/*0310*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101906 */
/*0320*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0330*/ SHF.R.U32.HI R5, RZ, 0x17, R3.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011603 */
/*0340*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x000fc600078e0003 */
/*0350*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fc800078ec0ff */
/*0360*/ IADD3 R8, R5, -0x1, RZ ; /* 0xffffffff05087810 */
/* 0x000fc80007ffe0ff */
/*0370*/ ISETP.GT.U32.AND P0, PT, R8, 0xfd, PT ; /* 0x000000fd0800780c */
/* 0x000fda0003f04070 */
/*0380*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff068224 */
/* 0x000fe200078e00ff */
/*0390*/ @!P0 BRA 0x490 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*03a0*/ FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fda0003f1c200 */
/*03b0*/ @P0 BRA 0x860 ; /* 0x000004a000000947 */
/* 0x000fea0003800000 */
/*03c0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x45800000 ; /* 0x45800000ff067424 */
/* 0x000fca00078e00ff */
/*03d0*/ LOP3.LUT P0, RZ, R7, 0x7fffffff, R6, 0xc8, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fda000780c806 */
/*03e0*/ @!P0 BRA 0x840 ; /* 0x0000045000008947 */
/* 0x000fea0003800000 */
/*03f0*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fe40003f1d200 */
/*0400*/ LOP3.LUT P1, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000782c0ff */
/*0410*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0420*/ @P0 BRA 0x820 ; /* 0x000003f000000947 */
/* 0x000fea0003800000 */
/*0430*/ LOP3.LUT P0, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fda000780c0ff */
/*0440*/ @!P0 BRA 0x7f0 ; /* 0x000003a000008947 */
/* 0x000fea0003800000 */
/*0450*/ ISETP.GE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f06270 */
/*0460*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fd800078e00ff */
/*0470*/ @!P0 FFMA R7, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003078823 */
/* 0x000fe200000000ff */
/*0480*/ @!P0 IADD3 R6, R6, 0x40, RZ ; /* 0x0000004006068810 */
/* 0x000fe40007ffe0ff */
/*0490*/ LEA R8, R5, 0xc0800000, 0x17 ; /* 0xc080000005087811 */
/* 0x000fe200078eb8ff */
/*04a0*/ UMOV UR4, 0x45800000 ; /* 0x4580000000047882 */
/* 0x000fe20000000000 */
/*04b0*/ IADD3 R6, R6, 0x8b, -R5 ; /* 0x0000008b06067810 */
/* 0x000fe20007ffe805 */
/*04c0*/ UIADD3 UR4, UR4, -0x6000000, URZ ; /* 0xfa00000004047890 */
/* 0x000fe4000fffe03f */
/*04d0*/ IMAD.IADD R8, R7, 0x1, -R8 ; /* 0x0000000107087824 */
/* 0x000fc800078e0a08 */
/*04e0*/ MUFU.RCP R3, R8 ; /* 0x0000000800037308 */
/* 0x000e220000001000 */
/*04f0*/ FADD.FTZ R10, -R8, -RZ ; /* 0x800000ff080a7221 */
/* 0x000fc80000010100 */
/*0500*/ FFMA R12, R3, R10, 1 ; /* 0x3f800000030c7423 */
/* 0x001fc8000000000a */
/*0510*/ FFMA R9, R3, R12, R3 ; /* 0x0000000c03097223 */
/* 0x000fc80000000003 */
/*0520*/ FFMA R3, R9, UR4, RZ ; /* 0x0000000409037c23 */
/* 0x000fc800080000ff */
/*0530*/ FFMA R12, R10, R3, UR4 ; /* 0x000000040a0c7e23 */
/* 0x000fc80008000003 */
/*0540*/ FFMA R12, R9, R12, R3 ; /* 0x0000000c090c7223 */
/* 0x000fc80000000003 */
/*0550*/ FFMA R10, R10, R12, UR4 ; /* 0x000000040a0a7e23 */
/* 0x000fc8000800000c */
/*0560*/ FFMA R7, R9, R10, R12 ; /* 0x0000000a09077223 */
/* 0x000fca000000000c */
/*0570*/ SHF.R.U32.HI R3, RZ, 0x17, R7 ; /* 0x00000017ff037819 */
/* 0x000fc80000011607 */
/*0580*/ LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03037812 */
/* 0x000fca00078ec0ff */
/*0590*/ IMAD.IADD R11, R3, 0x1, R6 ; /* 0x00000001030b7824 */
/* 0x000fca00078e0206 */
/*05a0*/ IADD3 R3, R11, -0x1, RZ ; /* 0xffffffff0b037810 */
/* 0x000fc80007ffe0ff */
/*05b0*/ ISETP.GE.U32.AND P0, PT, R3, 0xfe, PT ; /* 0x000000fe0300780c */
/* 0x000fda0003f06070 */
/*05c0*/ @!P0 BRA 0x7d0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*05d0*/ ISETP.GT.AND P0, PT, R11, 0xfe, PT ; /* 0x000000fe0b00780c */
/* 0x000fda0003f04270 */
/*05e0*/ @P0 BRA 0x7a0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*05f0*/ ISETP.GE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fda0003f06270 */
/*0600*/ @P0 BRA 0x870 ; /* 0x0000026000000947 */
/* 0x000fea0003800000 */
/*0610*/ ISETP.GE.AND P0, PT, R11, -0x18, PT ; /* 0xffffffe80b00780c */
/* 0x000fe40003f06270 */
/*0620*/ LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fd600078ec0ff */
/*0630*/ @!P0 BRA 0x870 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*0640*/ FFMA.RZ R3, R9, R10.reuse, R12.reuse ; /* 0x0000000a09037223 */
/* 0x180fe2000000c00c */
/*0650*/ IADD3 R8, R11, 0x20, RZ ; /* 0x000000200b087810 */
/* 0x000fe20007ffe0ff */
/*0660*/ FFMA.RM R6, R9, R10.reuse, R12.reuse ; /* 0x0000000a09067223 */
/* 0x180fe2000000400c */
/*0670*/ ISETP.NE.AND P2, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f45270 */
/*0680*/ LOP3.LUT R5, R3, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff03057812 */
/* 0x000fe200078ec0ff */
/*0690*/ FFMA.RP R3, R9, R10, R12 ; /* 0x0000000a09037223 */
/* 0x000fe2000000800c */
/*06a0*/ ISETP.NE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f25270 */
/*06b0*/ IMAD.MOV R9, RZ, RZ, -R11 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a0b */
/*06c0*/ LOP3.LUT R5, R5, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000005057812 */
/* 0x000fe400078efcff */
/*06d0*/ FSETP.NEU.FTZ.AND P0, PT, R3, R6, PT ; /* 0x000000060300720b */
/* 0x000fc40003f1d000 */
/*06e0*/ SHF.L.U32 R8, R5, R8, RZ ; /* 0x0000000805087219 */
/* 0x000fe400000006ff */
/*06f0*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*0700*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*0710*/ SHF.R.U32.HI R6, RZ, R6, R5 ; /* 0x00000006ff067219 */
/* 0x000fe40000011605 */
/*0720*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0730*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*0740*/ SEL R3, RZ, 0x1, !P0 ; /* 0x00000001ff037807 */
/* 0x000fc80004000000 */
/*0750*/ LOP3.LUT R3, R3, 0x1, R8, 0xf8, !PT ; /* 0x0000000103037812 */
/* 0x000fc800078ef808 */
/*0760*/ LOP3.LUT R3, R3, R6, RZ, 0xc0, !PT ; /* 0x0000000603037212 */
/* 0x000fca00078ec0ff */
/*0770*/ IMAD.IADD R8, R8, 0x1, R3 ; /* 0x0000000108087824 */
/* 0x000fca00078e0203 */
/*0780*/ LOP3.LUT R7, R8, R7, RZ, 0xfc, !PT ; /* 0x0000000708077212 */
/* 0x000fe200078efcff */
/*0790*/ BRA 0x870 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*07a0*/ LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fc800078ec0ff */
/*07b0*/ LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000007077812 */
/* 0x000fe200078efcff */
/*07c0*/ BRA 0x870 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*07d0*/ IMAD R7, R6, 0x800000, R7 ; /* 0x0080000006077824 */
/* 0x000fe200078e0207 */
/*07e0*/ BRA 0x870 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*07f0*/ LOP3.LUT R7, R7, 0x80000000, R6, 0x48, !PT ; /* 0x8000000007077812 */
/* 0x000fc800078e4806 */
/*0800*/ LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000007077812 */
/* 0x000fe200078efcff */
/*0810*/ BRA 0x870 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0820*/ LOP3.LUT R7, R7, 0x80000000, R6, 0x48, !PT ; /* 0x8000000007077812 */
/* 0x000fe200078e4806 */
/*0830*/ BRA 0x870 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0840*/ MUFU.RSQ R7, -QNAN ; /* 0xffc0000000077908 */
/* 0x000e220000001400 */
/*0850*/ BRA 0x870 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0860*/ FADD.FTZ R7, R3, 4096 ; /* 0x4580000003077421 */
/* 0x000fe40000010000 */
/*0870*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0880*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff77004007950 */
/* 0x000fea0003c3ffff */
/*0890*/ BRA 0x890; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void prefixSumForward(float* arr,int step){
int bx = blockIdx.x;
int tx = threadIdx.x;
int BX = blockDim.x;
int i = bx*BX+tx;
int ii = i+1;
if( ii <= n && ii > n/float(step)) return;
arr[ii*step-1] += arr[ii*step-step/2-1];
if(step==n && n-1 == ii*step-1) {
arr[ii*step] = arr[ii*step-1];
arr[ii*step-1]= 0;
}
} | .file "tmpxft_0010befd_00000000-6_prefixSumForward.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z16prefixSumForwardPfiPfi
.type _Z37__device_stub__Z16prefixSumForwardPfiPfi, @function
_Z37__device_stub__Z16prefixSumForwardPfiPfi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16prefixSumForwardPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z16prefixSumForwardPfiPfi, .-_Z37__device_stub__Z16prefixSumForwardPfiPfi
.globl _Z16prefixSumForwardPfi
.type _Z16prefixSumForwardPfi, @function
_Z16prefixSumForwardPfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z16prefixSumForwardPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16prefixSumForwardPfi, .-_Z16prefixSumForwardPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16prefixSumForwardPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16prefixSumForwardPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void prefixSumForward(float* arr,int step){
int bx = blockIdx.x;
int tx = threadIdx.x;
int BX = blockDim.x;
int i = bx*BX+tx;
int ii = i+1;
if( ii <= n && ii > n/float(step)) return;
arr[ii*step-1] += arr[ii*step-step/2-1];
if(step==n && n-1 == ii*step-1) {
arr[ii*step] = arr[ii*step-1];
arr[ii*step-1]= 0;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void prefixSumForward(float* arr,int step){
int bx = blockIdx.x;
int tx = threadIdx.x;
int BX = blockDim.x;
int i = bx*BX+tx;
int ii = i+1;
if( ii <= n && ii > n/float(step)) return;
arr[ii*step-1] += arr[ii*step-step/2-1];
if(step==n && n-1 == ii*step-1) {
arr[ii*step] = arr[ii*step-1];
arr[ii*step-1]= 0;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void prefixSumForward(float* arr,int step){
int bx = blockIdx.x;
int tx = threadIdx.x;
int BX = blockDim.x;
int i = bx*BX+tx;
int ii = i+1;
if( ii <= n && ii > n/float(step)) return;
arr[ii*step-1] += arr[ii*step-step/2-1];
if(step==n && n-1 == ii*step-1) {
arr[ii*step] = arr[ii*step-1];
arr[ii*step-1]= 0;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16prefixSumForwardPfi
.globl _Z16prefixSumForwardPfi
.p2align 8
.type _Z16prefixSumForwardPfi,@function
_Z16prefixSumForwardPfi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x8
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
v_add_nc_u32_e32 v0, 1, v1
v_cmp_lt_i32_e64 s3, 0xfff, v1
v_cmpx_gt_i32_e32 0x1000, v1
s_cbranch_execz .LBB0_2
v_cvt_f32_i32_e32 v1, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_not1_b32 s3, s3, exec_lo
v_div_scale_f32 v2, null, v1, v1, 0x45800000
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_fma_f32 v4, -v2, v3, 1.0
v_fmac_f32_e32 v3, v4, v3
v_div_scale_f32 v4, vcc_lo, 0x45800000, v1, 0x45800000
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v4, v3
v_fma_f32 v6, -v2, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v3
v_fma_f32 v2, -v2, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v2, v2, v3, v5
v_cvt_f32_i32_e32 v3, v0
v_div_fixup_f32 v1, v2, v1, 0x45800000
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_nlt_f32_e32 vcc_lo, v1, v3
s_and_b32 s5, vcc_lo, exec_lo
s_or_b32 s3, s3, s5
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_delay_alu instid0(VALU_DEP_2)
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB0_5
v_mul_lo_u32 v0, v0, s2
s_lshr_b32 s3, s2, 31
s_load_b64 s[0:1], s[0:1], 0x0
s_add_i32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_ashr_i32 s3, s3, 1
s_cmpk_eq_i32 s2, 0x1000
s_cselect_b32 s2, -1, 0
v_subrev_nc_u32_e32 v1, s3, v0
v_add_nc_u32_e32 v4, -1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_lshlrev_b64 v[5:6], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v6, vcc_lo
s_clause 0x1
global_load_b32 v1, v[7:8], off offset:-4
global_load_b32 v5, v[2:3], off
v_cmp_eq_u32_e32 vcc_lo, 0xfff, v4
s_and_b32 s2, s2, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v1, v5
global_store_b32 v[2:3], v4, off
s_and_b32 exec_lo, exec_lo, s2
v_ashrrev_i32_e32 v1, 31, v0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_clause 0x1
global_store_b32 v[0:1], v4, off
global_store_b32 v[2:3], v5, off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16prefixSumForwardPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16prefixSumForwardPfi, .Lfunc_end0-_Z16prefixSumForwardPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16prefixSumForwardPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16prefixSumForwardPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void prefixSumForward(float* arr,int step){
int bx = blockIdx.x;
int tx = threadIdx.x;
int BX = blockDim.x;
int i = bx*BX+tx;
int ii = i+1;
if( ii <= n && ii > n/float(step)) return;
arr[ii*step-1] += arr[ii*step-step/2-1];
if(step==n && n-1 == ii*step-1) {
arr[ii*step] = arr[ii*step-1];
arr[ii*step-1]= 0;
}
} | .text
.file "prefixSumForward.hip"
.globl _Z31__device_stub__prefixSumForwardPfi # -- Begin function _Z31__device_stub__prefixSumForwardPfi
.p2align 4, 0x90
.type _Z31__device_stub__prefixSumForwardPfi,@function
_Z31__device_stub__prefixSumForwardPfi: # @_Z31__device_stub__prefixSumForwardPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16prefixSumForwardPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z31__device_stub__prefixSumForwardPfi, .Lfunc_end0-_Z31__device_stub__prefixSumForwardPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16prefixSumForwardPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16prefixSumForwardPfi,@object # @_Z16prefixSumForwardPfi
.section .rodata,"a",@progbits
.globl _Z16prefixSumForwardPfi
.p2align 3, 0x0
_Z16prefixSumForwardPfi:
.quad _Z31__device_stub__prefixSumForwardPfi
.size _Z16prefixSumForwardPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16prefixSumForwardPfi"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__prefixSumForwardPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16prefixSumForwardPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16prefixSumForwardPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x1b0 ; /* 0x0000017000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GT.AND P0, PT, R0.reuse, 0xfff, PT ; /* 0x00000fff0000780c */
/* 0x040fe40003f04270 */
/*0070*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fd60007ffe0ff */
/*0080*/ @P0 BRA 0x1a0 ; /* 0x0000011000000947 */
/* 0x000fea0003800000 */
/*0090*/ I2F R3, c[0x0][0x168] ; /* 0x00005a0000037b06 */
/* 0x000e220000201400 */
/*00a0*/ UMOV UR4, 0x45800000 ; /* 0x4580000000047882 */
/* 0x000fe40000000000 */
/*00b0*/ IMAD.U32 R8, RZ, RZ, UR4 ; /* 0x00000004ff087e24 */
/* 0x000fca000f8e00ff */
/*00c0*/ I2F R2, R0 ; /* 0x0000000000027306 */
/* 0x000ff00000201400 */
/*00d0*/ MUFU.RCP R4, R3 ; /* 0x0000000300047308 */
/* 0x001e300000001000 */
/*00e0*/ FCHK P0, R8, R3 ; /* 0x0000000308007302 */
/* 0x000e620000000000 */
/*00f0*/ FFMA R5, -R3, R4, 1 ; /* 0x3f80000003057423 */
/* 0x001fc80000000104 */
/*0100*/ FFMA R5, R4, R5, R4 ; /* 0x0000000504057223 */
/* 0x000fc80000000004 */
/*0110*/ FFMA R4, R5, 4096, RZ ; /* 0x4580000005047823 */
/* 0x000fc800000000ff */
/*0120*/ FFMA R6, -R3, R4, 4096 ; /* 0x4580000003067423 */
/* 0x000fc80000000104 */
/*0130*/ FFMA R5, R5, R6, R4 ; /* 0x0000000605057223 */
/* 0x000fe20000000004 */
/*0140*/ @!P0 BRA 0x180 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*0150*/ MOV R4, 0x170 ; /* 0x0000017000047802 */
/* 0x000fe40000000f00 */
/*0160*/ CALL.REL.NOINC 0x330 ; /* 0x000001c000007944 */
/* 0x000fea0003c00000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x001fca00078e0007 */
/*0180*/ FSETP.GEU.AND P0, PT, R5, R2, PT ; /* 0x000000020500720b */
/* 0x000fda0003f0e000 */
/*0190*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*01a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01b0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff097624 */
/* 0x000fe400078e00ff */
/*01c0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe400078e00ff */
/*01d0*/ IMAD R6, R0, R9, -0x1 ; /* 0xffffffff00067424 */
/* 0x000fe200078e0209 */
/*01e0*/ LEA.HI R2, R9, c[0x0][0x168], RZ, 0x1 ; /* 0x00005a0009027a11 */
/* 0x000fc600078f08ff */
/*01f0*/ IMAD.WIDE R4, R6, R11, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x000fe200078e020b */
/*0200*/ SHF.R.S32.HI R2, RZ, 0x1, R2 ; /* 0x00000001ff027819 */
/* 0x000fc80000011402 */
/*0210*/ LOP3.LUT R3, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff037212 */
/* 0x000fe200078e33ff */
/*0220*/ LDG.E R7, [R4.64] ; /* 0x0000000604077981 */
/* 0x000ea8000c1e1900 */
/*0230*/ IMAD R3, R0, c[0x0][0x168], R3 ; /* 0x00005a0000037a24 */
/* 0x000fc800078e0203 */
/*0240*/ IMAD.WIDE R2, R3, R11, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fcc00078e020b */
/*0250*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*0260*/ ISETP.NE.AND P0, PT, R6, 0xfff, PT ; /* 0x00000fff0600780c */
/* 0x000fc80003f05270 */
/*0270*/ ISETP.NE.OR P0, PT, R9, 0x1000, P0 ; /* 0x000010000900780c */
/* 0x000fe20000705670 */
/*0280*/ FADD R7, R7, R2 ; /* 0x0000000207077221 */
/* 0x004fca0000000000 */
/*0290*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001ee000c101906 */
/*02a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02b0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x001fe400078e00ff */
/*02c0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fca00078e00ff */
/*02d0*/ LDG.E R5, [R4.64+0x3ffc] ; /* 0x003ffc0604057981 */
/* 0x000ea2000c1e1900 */
/*02e0*/ IMAD.SHL.U32 R2, R0, 0x1000, RZ ; /* 0x0000100000027824 */
/* 0x000fc800078e00ff */
/*02f0*/ IMAD.WIDE R2, R2, R11, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e020b */
/*0300*/ STG.E [R2.64+-0x4], RZ ; /* 0xfffffcff02007986 */
/* 0x000fe8000c101906 */
/*0310*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101906 */
/*0320*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0330*/ SHF.R.U32.HI R5, RZ, 0x17, R3.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011603 */
/*0340*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x000fc600078e0003 */
/*0350*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fc800078ec0ff */
/*0360*/ IADD3 R8, R5, -0x1, RZ ; /* 0xffffffff05087810 */
/* 0x000fc80007ffe0ff */
/*0370*/ ISETP.GT.U32.AND P0, PT, R8, 0xfd, PT ; /* 0x000000fd0800780c */
/* 0x000fda0003f04070 */
/*0380*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff068224 */
/* 0x000fe200078e00ff */
/*0390*/ @!P0 BRA 0x490 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*03a0*/ FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fda0003f1c200 */
/*03b0*/ @P0 BRA 0x860 ; /* 0x000004a000000947 */
/* 0x000fea0003800000 */
/*03c0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x45800000 ; /* 0x45800000ff067424 */
/* 0x000fca00078e00ff */
/*03d0*/ LOP3.LUT P0, RZ, R7, 0x7fffffff, R6, 0xc8, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fda000780c806 */
/*03e0*/ @!P0 BRA 0x840 ; /* 0x0000045000008947 */
/* 0x000fea0003800000 */
/*03f0*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fe40003f1d200 */
/*0400*/ LOP3.LUT P1, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000782c0ff */
/*0410*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0420*/ @P0 BRA 0x820 ; /* 0x000003f000000947 */
/* 0x000fea0003800000 */
/*0430*/ LOP3.LUT P0, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fda000780c0ff */
/*0440*/ @!P0 BRA 0x7f0 ; /* 0x000003a000008947 */
/* 0x000fea0003800000 */
/*0450*/ ISETP.GE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f06270 */
/*0460*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fd800078e00ff */
/*0470*/ @!P0 FFMA R7, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003078823 */
/* 0x000fe200000000ff */
/*0480*/ @!P0 IADD3 R6, R6, 0x40, RZ ; /* 0x0000004006068810 */
/* 0x000fe40007ffe0ff */
/*0490*/ LEA R8, R5, 0xc0800000, 0x17 ; /* 0xc080000005087811 */
/* 0x000fe200078eb8ff */
/*04a0*/ UMOV UR4, 0x45800000 ; /* 0x4580000000047882 */
/* 0x000fe20000000000 */
/*04b0*/ IADD3 R6, R6, 0x8b, -R5 ; /* 0x0000008b06067810 */
/* 0x000fe20007ffe805 */
/*04c0*/ UIADD3 UR4, UR4, -0x6000000, URZ ; /* 0xfa00000004047890 */
/* 0x000fe4000fffe03f */
/*04d0*/ IMAD.IADD R8, R7, 0x1, -R8 ; /* 0x0000000107087824 */
/* 0x000fc800078e0a08 */
/*04e0*/ MUFU.RCP R3, R8 ; /* 0x0000000800037308 */
/* 0x000e220000001000 */
/*04f0*/ FADD.FTZ R10, -R8, -RZ ; /* 0x800000ff080a7221 */
/* 0x000fc80000010100 */
/*0500*/ FFMA R12, R3, R10, 1 ; /* 0x3f800000030c7423 */
/* 0x001fc8000000000a */
/*0510*/ FFMA R9, R3, R12, R3 ; /* 0x0000000c03097223 */
/* 0x000fc80000000003 */
/*0520*/ FFMA R3, R9, UR4, RZ ; /* 0x0000000409037c23 */
/* 0x000fc800080000ff */
/*0530*/ FFMA R12, R10, R3, UR4 ; /* 0x000000040a0c7e23 */
/* 0x000fc80008000003 */
/*0540*/ FFMA R12, R9, R12, R3 ; /* 0x0000000c090c7223 */
/* 0x000fc80000000003 */
/*0550*/ FFMA R10, R10, R12, UR4 ; /* 0x000000040a0a7e23 */
/* 0x000fc8000800000c */
/*0560*/ FFMA R7, R9, R10, R12 ; /* 0x0000000a09077223 */
/* 0x000fca000000000c */
/*0570*/ SHF.R.U32.HI R3, RZ, 0x17, R7 ; /* 0x00000017ff037819 */
/* 0x000fc80000011607 */
/*0580*/ LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03037812 */
/* 0x000fca00078ec0ff */
/*0590*/ IMAD.IADD R11, R3, 0x1, R6 ; /* 0x00000001030b7824 */
/* 0x000fca00078e0206 */
/*05a0*/ IADD3 R3, R11, -0x1, RZ ; /* 0xffffffff0b037810 */
/* 0x000fc80007ffe0ff */
/*05b0*/ ISETP.GE.U32.AND P0, PT, R3, 0xfe, PT ; /* 0x000000fe0300780c */
/* 0x000fda0003f06070 */
/*05c0*/ @!P0 BRA 0x7d0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*05d0*/ ISETP.GT.AND P0, PT, R11, 0xfe, PT ; /* 0x000000fe0b00780c */
/* 0x000fda0003f04270 */
/*05e0*/ @P0 BRA 0x7a0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*05f0*/ ISETP.GE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fda0003f06270 */
/*0600*/ @P0 BRA 0x870 ; /* 0x0000026000000947 */
/* 0x000fea0003800000 */
/*0610*/ ISETP.GE.AND P0, PT, R11, -0x18, PT ; /* 0xffffffe80b00780c */
/* 0x000fe40003f06270 */
/*0620*/ LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fd600078ec0ff */
/*0630*/ @!P0 BRA 0x870 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*0640*/ FFMA.RZ R3, R9, R10.reuse, R12.reuse ; /* 0x0000000a09037223 */
/* 0x180fe2000000c00c */
/*0650*/ IADD3 R8, R11, 0x20, RZ ; /* 0x000000200b087810 */
/* 0x000fe20007ffe0ff */
/*0660*/ FFMA.RM R6, R9, R10.reuse, R12.reuse ; /* 0x0000000a09067223 */
/* 0x180fe2000000400c */
/*0670*/ ISETP.NE.AND P2, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f45270 */
/*0680*/ LOP3.LUT R5, R3, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff03057812 */
/* 0x000fe200078ec0ff */
/*0690*/ FFMA.RP R3, R9, R10, R12 ; /* 0x0000000a09037223 */
/* 0x000fe2000000800c */
/*06a0*/ ISETP.NE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f25270 */
/*06b0*/ IMAD.MOV R9, RZ, RZ, -R11 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a0b */
/*06c0*/ LOP3.LUT R5, R5, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000005057812 */
/* 0x000fe400078efcff */
/*06d0*/ FSETP.NEU.FTZ.AND P0, PT, R3, R6, PT ; /* 0x000000060300720b */
/* 0x000fc40003f1d000 */
/*06e0*/ SHF.L.U32 R8, R5, R8, RZ ; /* 0x0000000805087219 */
/* 0x000fe400000006ff */
/*06f0*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*0700*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*0710*/ SHF.R.U32.HI R6, RZ, R6, R5 ; /* 0x00000006ff067219 */
/* 0x000fe40000011605 */
/*0720*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0730*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*0740*/ SEL R3, RZ, 0x1, !P0 ; /* 0x00000001ff037807 */
/* 0x000fc80004000000 */
/*0750*/ LOP3.LUT R3, R3, 0x1, R8, 0xf8, !PT ; /* 0x0000000103037812 */
/* 0x000fc800078ef808 */
/*0760*/ LOP3.LUT R3, R3, R6, RZ, 0xc0, !PT ; /* 0x0000000603037212 */
/* 0x000fca00078ec0ff */
/*0770*/ IMAD.IADD R8, R8, 0x1, R3 ; /* 0x0000000108087824 */
/* 0x000fca00078e0203 */
/*0780*/ LOP3.LUT R7, R8, R7, RZ, 0xfc, !PT ; /* 0x0000000708077212 */
/* 0x000fe200078efcff */
/*0790*/ BRA 0x870 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*07a0*/ LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fc800078ec0ff */
/*07b0*/ LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000007077812 */
/* 0x000fe200078efcff */
/*07c0*/ BRA 0x870 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*07d0*/ IMAD R7, R6, 0x800000, R7 ; /* 0x0080000006077824 */
/* 0x000fe200078e0207 */
/*07e0*/ BRA 0x870 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*07f0*/ LOP3.LUT R7, R7, 0x80000000, R6, 0x48, !PT ; /* 0x8000000007077812 */
/* 0x000fc800078e4806 */
/*0800*/ LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000007077812 */
/* 0x000fe200078efcff */
/*0810*/ BRA 0x870 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0820*/ LOP3.LUT R7, R7, 0x80000000, R6, 0x48, !PT ; /* 0x8000000007077812 */
/* 0x000fe200078e4806 */
/*0830*/ BRA 0x870 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0840*/ MUFU.RSQ R7, -QNAN ; /* 0xffc0000000077908 */
/* 0x000e220000001400 */
/*0850*/ BRA 0x870 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0860*/ FADD.FTZ R7, R3, 4096 ; /* 0x4580000003077421 */
/* 0x000fe40000010000 */
/*0870*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0880*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff77004007950 */
/* 0x000fea0003c3ffff */
/*0890*/ BRA 0x890; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16prefixSumForwardPfi
.globl _Z16prefixSumForwardPfi
.p2align 8
.type _Z16prefixSumForwardPfi,@function
_Z16prefixSumForwardPfi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x8
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
v_add_nc_u32_e32 v0, 1, v1
v_cmp_lt_i32_e64 s3, 0xfff, v1
v_cmpx_gt_i32_e32 0x1000, v1
s_cbranch_execz .LBB0_2
v_cvt_f32_i32_e32 v1, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_not1_b32 s3, s3, exec_lo
v_div_scale_f32 v2, null, v1, v1, 0x45800000
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_fma_f32 v4, -v2, v3, 1.0
v_fmac_f32_e32 v3, v4, v3
v_div_scale_f32 v4, vcc_lo, 0x45800000, v1, 0x45800000
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v4, v3
v_fma_f32 v6, -v2, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v3
v_fma_f32 v2, -v2, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v2, v2, v3, v5
v_cvt_f32_i32_e32 v3, v0
v_div_fixup_f32 v1, v2, v1, 0x45800000
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_nlt_f32_e32 vcc_lo, v1, v3
s_and_b32 s5, vcc_lo, exec_lo
s_or_b32 s3, s3, s5
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_delay_alu instid0(VALU_DEP_2)
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB0_5
v_mul_lo_u32 v0, v0, s2
s_lshr_b32 s3, s2, 31
s_load_b64 s[0:1], s[0:1], 0x0
s_add_i32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_ashr_i32 s3, s3, 1
s_cmpk_eq_i32 s2, 0x1000
s_cselect_b32 s2, -1, 0
v_subrev_nc_u32_e32 v1, s3, v0
v_add_nc_u32_e32 v4, -1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_lshlrev_b64 v[5:6], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v6, vcc_lo
s_clause 0x1
global_load_b32 v1, v[7:8], off offset:-4
global_load_b32 v5, v[2:3], off
v_cmp_eq_u32_e32 vcc_lo, 0xfff, v4
s_and_b32 s2, s2, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v1, v5
global_store_b32 v[2:3], v4, off
s_and_b32 exec_lo, exec_lo, s2
v_ashrrev_i32_e32 v1, 31, v0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_clause 0x1
global_store_b32 v[0:1], v4, off
global_store_b32 v[2:3], v5, off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16prefixSumForwardPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16prefixSumForwardPfi, .Lfunc_end0-_Z16prefixSumForwardPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16prefixSumForwardPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16prefixSumForwardPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010befd_00000000-6_prefixSumForward.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z16prefixSumForwardPfiPfi
.type _Z37__device_stub__Z16prefixSumForwardPfiPfi, @function
_Z37__device_stub__Z16prefixSumForwardPfiPfi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16prefixSumForwardPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z16prefixSumForwardPfiPfi, .-_Z37__device_stub__Z16prefixSumForwardPfiPfi
.globl _Z16prefixSumForwardPfi
.type _Z16prefixSumForwardPfi, @function
_Z16prefixSumForwardPfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z16prefixSumForwardPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16prefixSumForwardPfi, .-_Z16prefixSumForwardPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16prefixSumForwardPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16prefixSumForwardPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "prefixSumForward.hip"
.globl _Z31__device_stub__prefixSumForwardPfi # -- Begin function _Z31__device_stub__prefixSumForwardPfi
.p2align 4, 0x90
.type _Z31__device_stub__prefixSumForwardPfi,@function
_Z31__device_stub__prefixSumForwardPfi: # @_Z31__device_stub__prefixSumForwardPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16prefixSumForwardPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z31__device_stub__prefixSumForwardPfi, .Lfunc_end0-_Z31__device_stub__prefixSumForwardPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16prefixSumForwardPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16prefixSumForwardPfi,@object # @_Z16prefixSumForwardPfi
.section .rodata,"a",@progbits
.globl _Z16prefixSumForwardPfi
.p2align 3, 0x0
_Z16prefixSumForwardPfi:
.quad _Z31__device_stub__prefixSumForwardPfi
.size _Z16prefixSumForwardPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16prefixSumForwardPfi"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__prefixSumForwardPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16prefixSumForwardPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
============================================================================
Name : lab.cu
Author :
Version :
Copyright : Your copyright notice
Description : CUDA compute reciprocals
============================================================================
*/
#include <iostream>
#include <numeric>
#include <stdlib.h>
#include <fstream>
//#include <stdio.h>
static void CheckCudaErrorAux (const char *, unsigned, const char *, cudaError_t);
#define CUDA_CHECK_RETURN(value) CheckCudaErrorAux(__FILE__,__LINE__, #value, value)
struct Params
{
int length;
int time;
float dx;
float dt;
float startT;
float endT;
};
void initialize(float **data, Params inParam)
{
for (unsigned i = 0; i < inParam.time; ++i)
data[i] = new float[inParam.length];
}
/**
* CUDA kernel that computes reciprocal values for a given vector
*/
__global__ void reciprocalKernel(float *OldData,float *NewData, Params inParams) {
unsigned idx = blockIdx.x*blockDim.x+threadIdx.x;
if(idx == 0)
NewData[idx] = inParams.startT;
else if (idx == inParams.length - 1 )
NewData[idx] = inParams.endT * inParams.dt + OldData[idx];
else
{
NewData[idx] = ((OldData[idx+1] - 2 * OldData[idx] + OldData[idx-1])* inParams.dt)/inParams.dx * inParams.dx + OldData[idx];
}
}
/**
* Host function that copies the data and launches the work on GPU
*/
void gpuReciprocal(float *data, Params inParams)
{
float *rc = new float[inParams.length];
float *gpuOldData;
float *gpuNewData;
cudaEvent_t GPUstart, GPUstop;
float GPUtime = 0.0f;
cudaEventCreate(&GPUstart);
cudaEventCreate(&GPUstop);
CUDA_CHECK_RETURN(cudaMalloc((void **)&gpuOldData, sizeof(float)*inParams.length));
CUDA_CHECK_RETURN(cudaMemcpy(gpuOldData, rc, sizeof(float)*inParams.length, cudaMemcpyHostToDevice));
CUDA_CHECK_RETURN(cudaMalloc((void **)&gpuNewData, sizeof(float)*inParams.length));
CUDA_CHECK_RETURN(cudaMemcpy(gpuNewData, data, sizeof(float)*inParams.length, cudaMemcpyHostToDevice));
static const int BLOCK_SIZE = 26;
const int blockCount = 1;
for(int i = 0; i < inParams.time; ++i)
{
cudaEventRecord(GPUstart, 0);
if (i % 2 == 0)
{
reciprocalKernel<<<blockCount, BLOCK_SIZE>>> (gpuOldData, gpuNewData, inParams);
cudaEventRecord(GPUstop, 0);
CUDA_CHECK_RETURN(cudaMemcpy(rc, gpuNewData, sizeof(float)*inParams.length, cudaMemcpyDeviceToHost));
}
else
{
reciprocalKernel<<<blockCount, BLOCK_SIZE>>> (gpuNewData, gpuOldData, inParams);
cudaEventRecord(GPUstop, 0);
CUDA_CHECK_RETURN(cudaMemcpy(rc, gpuOldData, sizeof(float)*inParams.length, cudaMemcpyDeviceToHost));
}
cudaEventSynchronize(GPUstop);
std::cout << i <<": ";
for(int i =0; i < inParams.length; ++i)
std::cout << rc[i] << " ";
std::cout << std::endl;
float temp;
cudaEventElapsedTime(&temp,GPUstart, GPUstop);
GPUtime += temp;
}
printf("GPU time = %.3f ms\n",GPUtime);
}
void initializeData(float* data, unsigned size, float defaultValue)
{
for(int i = 0; i < size; ++i)
data[i] = defaultValue;
}
void print(float **a, unsigned h, unsigned w)
{
for(int i = 0; i < h; ++i)
{
std::cout << i << ": ";
for(int j = 0; j < w; ++j)
std::cout << a[i][j] << " ";
std::cout << std::endl;
}
}
float **cpuReciprocal(float **data,Params inParams)
{
float CPUstart, CPUstop;
float CPUtime = 0.0f;
float **cpuResult = new float*[inParams.time];
initialize(cpuResult, inParams);
float * currentData = cpuResult[0];
initializeData(currentData, inParams.length, 0);
currentData[0] = inParams.startT;
for(int i =1; i < inParams.time; ++i)
{
cpuResult[i][0] = inParams.startT;
for(int j = 1; j < inParams.length - 1; ++j)
{
cpuResult[i][j] = ((cpuResult[i-1][j+1] - 2 * cpuResult[i-1][j] + cpuResult[i-1][j-1])* inParams.dt)/inParams.dx * inParams.dx + cpuResult[i-1][j];
}
cpuResult[i][inParams.length-1] = inParams.endT * inParams.dt + cpuResult[i-1][inParams.length-1];
}
return cpuResult;
}
int main(void)
{
Params mainParams;
mainParams.length = 13;
mainParams.time = 20;
mainParams.dx = 0.5;
mainParams.dt = 0.1;
mainParams.startT = 0.0;
mainParams.endT = 5.0;
float **data;
data = new float*[mainParams.time];
initialize(data, mainParams);
std::cout << "CPU" << std::endl;
float **recCpu = cpuReciprocal(data, mainParams);
print(recCpu, mainParams.time, mainParams.length);
std::cout << "GPU" << std::endl;
float *dataTwo;
dataTwo = new float[mainParams.length];
gpuReciprocal(dataTwo, mainParams);
//print(recGpu, mainParams.time, mainParams.length);
// float cpuSum = std::accumulate (recCpu, recCpu+WORK_SIZE, 0.0);
// float gpuSum = std::accumulate (recGpu, recGpu+WORK_SIZE, 0.0);
/* Verify the results */
//std::cout<<"gpuSum = "<<gpuSum<< " cpuSum = " <<cpuSum<<std::endl;
/* Free memory */
//delete[] data;
//delete[] recCpu;
//delete[] recGpu;
return 0;
}
/**
* Check the return value of the CUDA runtime API call and exit
* the application if the call has failed.
*/
static void CheckCudaErrorAux (const char *file, unsigned line, const char *statement, cudaError_t err)
{
if (err == cudaSuccess)
return;
std::cerr << statement<<" returned " << cudaGetErrorString(err) << "("<<err<< ") at "<<file<<":"<<line << std::endl;
exit (1);
} | code for sm_80
Function : _Z16reciprocalKernelPfS_6Params
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0050*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0060*/ @!P0 BRA 0x2f0 ; /* 0x0000028000008947 */
/* 0x000fea0003800000 */
/*0070*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000800 */
/*0080*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0090*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fc6000fffe03f */
/*00a0*/ IMAD.WIDE.U32 R4, R0, R9, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc600078e0009 */
/*00b0*/ ISETP.NE.AND P0, PT, R0.reuse, UR4, PT ; /* 0x0000000400007c0c */
/* 0x040fe2000bf05270 */
/*00c0*/ IMAD.WIDE.U32 R2, R0, R9, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fd800078e0009 */
/*00d0*/ @!P0 BRA 0x2a0 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*00e0*/ IADD3 R6, R0.reuse, 0x1, RZ ; /* 0x0000000100067810 */
/* 0x040fe40007ffe0ff */
/*00f0*/ IADD3 R8, R0, -0x1, RZ ; /* 0xffffffff00087810 */
/* 0x000fe40007ffe0ff */
/*0100*/ LDG.E R0, [R4.64] ; /* 0x0000000604007981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE.U32 R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0009 */
/*0120*/ IMAD.WIDE.U32 R8, R8, R9, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fe400078e0009 */
/*0130*/ LDG.E R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ee8000c1e1900 */
/*0140*/ LDG.E R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000f22000c1e1900 */
/*0150*/ MUFU.RCP R10, c[0x0][0x178] ; /* 0x00005e00000a7b08 */
/* 0x000e220000001000 */
/*0160*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff0d7624 */
/* 0x000fe200078e00ff */
/*0170*/ BSSY B0, 0x270 ; /* 0x000000f000007945 */
/* 0x000fe60003800000 */
/*0180*/ FFMA R13, R10, -R13, 1 ; /* 0x3f8000000a0d7423 */
/* 0x001fc8000000080d */
/*0190*/ FFMA R10, R10, R13, R10 ; /* 0x0000000d0a0a7223 */
/* 0x000fe4000000000a */
/*01a0*/ FADD R11, R0, R0 ; /* 0x00000000000b7221 */
/* 0x004fc80000000000 */
/*01b0*/ FADD R11, R6, -R11 ; /* 0x8000000b060b7221 */
/* 0x008fc80000000000 */
/*01c0*/ FADD R11, R11, R8 ; /* 0x000000080b0b7221 */
/* 0x010fc80000000000 */
/*01d0*/ FMUL R11, R11, c[0x0][0x17c] ; /* 0x00005f000b0b7a20 */
/* 0x000fc80000400000 */
/*01e0*/ FCHK P0, R11, c[0x0][0x178] ; /* 0x00005e000b007b02 */
/* 0x000e220000000000 */
/*01f0*/ FFMA R4, R11, R10, RZ ; /* 0x0000000a0b047223 */
/* 0x000fc800000000ff */
/*0200*/ FFMA R5, R4, -c[0x0][0x178], R11 ; /* 0x80005e0004057a23 */
/* 0x000fc8000000000b */
/*0210*/ FFMA R5, R10, R5, R4 ; /* 0x000000050a057223 */
/* 0x000fe20000000004 */
/*0220*/ @!P0 BRA 0x260 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*0230*/ MOV R4, 0x250 ; /* 0x0000025000047802 */
/* 0x000fe40000000f00 */
/*0240*/ CALL.REL.NOINC 0x340 ; /* 0x000000f000007944 */
/* 0x000fea0003c00000 */
/*0250*/ IMAD.MOV.U32 R5, RZ, RZ, R6 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0006 */
/*0260*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0270*/ FFMA R5, R5, c[0x0][0x178], R0 ; /* 0x00005e0005057a23 */
/* 0x000fca0000000000 */
/*0280*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101906 */
/*0290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02a0*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1900 */
/*02b0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff077624 */
/* 0x000fc800078e00ff */
/*02c0*/ FFMA R7, R7, c[0x0][0x17c], R4 ; /* 0x00005f0007077a23 */
/* 0x004fca0000000004 */
/*02d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101906 */
/*02e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02f0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff057624 */
/* 0x000fe400078e00ff */
/*0300*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe400078e00ff */
/*0310*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fca00078e00ff */
/*0320*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101906 */
/*0330*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0340*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff0d7624 */
/* 0x000fe200078e00ff */
/*0350*/ SHF.R.U32.HI R5, RZ, 0x17, R11.reuse ; /* 0x00000017ff057819 */
/* 0x100fe2000001160b */
/*0360*/ BSSY B1, 0x9b0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0370*/ IMAD.MOV.U32 R7, RZ, RZ, R11 ; /* 0x000000ffff077224 */
/* 0x000fe400078e000b */
/*0380*/ SHF.R.U32.HI R6, RZ, 0x17, R13 ; /* 0x00000017ff067819 */
/* 0x000fe2000001160d */
/*0390*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff087624 */
/* 0x000fe200078e00ff */
/*03a0*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe400078ec0ff */
/*03b0*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fc400078ec0ff */
/*03c0*/ IADD3 R10, R5, -0x1, RZ ; /* 0xffffffff050a7810 */
/* 0x000fe40007ffe0ff */
/*03d0*/ IADD3 R12, R6, -0x1, RZ ; /* 0xffffffff060c7810 */
/* 0x000fc80007ffe0ff */
/*03e0*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fc80003f04070 */
/*03f0*/ ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; /* 0x000000fd0a00780c */
/* 0x000fda0000704470 */
/*0400*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*0410*/ @!P0 BRA 0x590 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0420*/ FSETP.GTU.FTZ.AND P1, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fe40003f3c200 */
/*0430*/ FSETP.GTU.FTZ.AND P0, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fc80003f1c200 */
/*0440*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0450*/ @P0 BRA 0x990 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0460*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c807 */
/*0470*/ @!P0 BRA 0x970 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0480*/ FSETP.NEU.FTZ.AND P2, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fe40003f5d200 */
/*0490*/ FSETP.NEU.FTZ.AND P1, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fe40003f3d200 */
/*04a0*/ FSETP.NEU.FTZ.AND P0, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fd60003f1d200 */
/*04b0*/ @!P1 BRA !P2, 0x970 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*04c0*/ LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000784c0ff */
/*04d0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*04e0*/ @P1 BRA 0x950 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*04f0*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*0500*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0510*/ @P0 BRA 0x920 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0520*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f06270 */
/*0530*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*0540*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*0550*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*0560*/ @!P0 FFMA R7, R11, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000b078823 */
/* 0x000fe400000000ff */
/*0570*/ @!P1 FFMA R8, R13, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000d089823 */
/* 0x000fe200000000ff */
/*0580*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*0590*/ LEA R11, R6, 0xc0800000, 0x17 ; /* 0xc0800000060b7811 */
/* 0x000fe200078eb8ff */
/*05a0*/ BSSY B2, 0x910 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*05b0*/ IMAD.IADD R11, R8, 0x1, -R11 ; /* 0x00000001080b7824 */
/* 0x000fe200078e0a0b */
/*05c0*/ IADD3 R8, R5, -0x7f, RZ ; /* 0xffffff8105087810 */
/* 0x000fc60007ffe0ff */
/*05d0*/ MUFU.RCP R10, R11 ; /* 0x0000000b000a7308 */
/* 0x000e220000001000 */
/*05e0*/ FADD.FTZ R12, -R11, -RZ ; /* 0x800000ff0b0c7221 */
/* 0x000fe40000010100 */
/*05f0*/ IMAD R7, R8.reuse, -0x800000, R7 ; /* 0xff80000008077824 */
/* 0x040fe200078e0207 */
/*0600*/ IADD3 R8, R8, 0x7f, -R6 ; /* 0x0000007f08087810 */
/* 0x000fca0007ffe806 */
/*0610*/ IMAD.IADD R8, R8, 0x1, R9 ; /* 0x0000000108087824 */
/* 0x000fe400078e0209 */
/*0620*/ FFMA R5, R10, R12, 1 ; /* 0x3f8000000a057423 */
/* 0x001fc8000000000c */
/*0630*/ FFMA R14, R10, R5, R10 ; /* 0x000000050a0e7223 */
/* 0x000fc8000000000a */
/*0640*/ FFMA R5, R7, R14, RZ ; /* 0x0000000e07057223 */
/* 0x000fc800000000ff */
/*0650*/ FFMA R10, R12, R5, R7 ; /* 0x000000050c0a7223 */
/* 0x000fc80000000007 */
/*0660*/ FFMA R13, R14, R10, R5 ; /* 0x0000000a0e0d7223 */
/* 0x000fc80000000005 */
/*0670*/ FFMA R7, R12, R13, R7 ; /* 0x0000000d0c077223 */
/* 0x000fc80000000007 */
/*0680*/ FFMA R5, R14, R7, R13 ; /* 0x000000070e057223 */
/* 0x000fca000000000d */
/*0690*/ SHF.R.U32.HI R6, RZ, 0x17, R5 ; /* 0x00000017ff067819 */
/* 0x000fc80000011605 */
/*06a0*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fca00078ec0ff */
/*06b0*/ IMAD.IADD R10, R6, 0x1, R8 ; /* 0x00000001060a7824 */
/* 0x000fca00078e0208 */
/*06c0*/ IADD3 R6, R10, -0x1, RZ ; /* 0xffffffff0a067810 */
/* 0x000fc80007ffe0ff */
/*06d0*/ ISETP.GE.U32.AND P0, PT, R6, 0xfe, PT ; /* 0x000000fe0600780c */
/* 0x000fda0003f06070 */
/*06e0*/ @!P0 BRA 0x8f0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*06f0*/ ISETP.GT.AND P0, PT, R10, 0xfe, PT ; /* 0x000000fe0a00780c */
/* 0x000fda0003f04270 */
/*0700*/ @P0 BRA 0x8c0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0710*/ ISETP.GE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fda0003f06270 */
/*0720*/ @P0 BRA 0x900 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0730*/ ISETP.GE.AND P0, PT, R10, -0x18, PT ; /* 0xffffffe80a00780c */
/* 0x000fe40003f06270 */
/*0740*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fd600078ec0ff */
/*0750*/ @!P0 BRA 0x900 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0760*/ FFMA.RZ R6, R14, R7.reuse, R13.reuse ; /* 0x000000070e067223 */
/* 0x180fe2000000c00d */
/*0770*/ IADD3 R9, R10.reuse, 0x20, RZ ; /* 0x000000200a097810 */
/* 0x040fe40007ffe0ff */
/*0780*/ ISETP.NE.AND P2, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f45270 */
/*0790*/ LOP3.LUT R8, R6, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff06087812 */
/* 0x000fe200078ec0ff */
/*07a0*/ FFMA.RP R6, R14, R7.reuse, R13.reuse ; /* 0x000000070e067223 */
/* 0x180fe2000000800d */
/*07b0*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f25270 */
/*07c0*/ FFMA.RM R7, R14, R7, R13 ; /* 0x000000070e077223 */
/* 0x000fe2000000400d */
/*07d0*/ LOP3.LUT R8, R8, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000008087812 */
/* 0x000fe200078efcff */
/*07e0*/ IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0a7224 */
/* 0x000fc600078e0a0a */
/*07f0*/ SHF.L.U32 R9, R8, R9, RZ ; /* 0x0000000908097219 */
/* 0x000fe400000006ff */
/*0800*/ FSETP.NEU.FTZ.AND P0, PT, R6, R7, PT ; /* 0x000000070600720b */
/* 0x000fe40003f1d000 */
/*0810*/ SEL R7, R10, RZ, P2 ; /* 0x000000ff0a077207 */
/* 0x000fe40001000000 */
/*0820*/ ISETP.NE.AND P1, PT, R9, RZ, P1 ; /* 0x000000ff0900720c */
/* 0x000fe40000f25270 */
/*0830*/ SHF.R.U32.HI R7, RZ, R7, R8 ; /* 0x00000007ff077219 */
/* 0x000fe40000011608 */
/*0840*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0850*/ SHF.R.U32.HI R9, RZ, 0x1, R7 ; /* 0x00000001ff097819 */
/* 0x000fe40000011607 */
/*0860*/ SEL R6, RZ, 0x1, !P0 ; /* 0x00000001ff067807 */
/* 0x000fc80004000000 */
/*0870*/ LOP3.LUT R6, R6, 0x1, R9, 0xf8, !PT ; /* 0x0000000106067812 */
/* 0x000fc800078ef809 */
/*0880*/ LOP3.LUT R6, R6, R7, RZ, 0xc0, !PT ; /* 0x0000000706067212 */
/* 0x000fca00078ec0ff */
/*0890*/ IMAD.IADD R6, R9, 0x1, R6 ; /* 0x0000000109067824 */
/* 0x000fca00078e0206 */
/*08a0*/ LOP3.LUT R5, R6, R5, RZ, 0xfc, !PT ; /* 0x0000000506057212 */
/* 0x000fe200078efcff */
/*08b0*/ BRA 0x900 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*08c0*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fc800078ec0ff */
/*08d0*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*08e0*/ BRA 0x900 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*08f0*/ IMAD R5, R8, 0x800000, R5 ; /* 0x0080000008057824 */
/* 0x000fe400078e0205 */
/*0900*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0910*/ BRA 0x9a0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0920*/ LOP3.LUT R5, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008057812 */
/* 0x000fc800078e4807 */
/*0930*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*0940*/ BRA 0x9a0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0950*/ LOP3.LUT R5, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008057812 */
/* 0x000fe200078e4807 */
/*0960*/ BRA 0x9a0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0970*/ MUFU.RSQ R5, -QNAN ; /* 0xffc0000000057908 */
/* 0x000e220000001400 */
/*0980*/ BRA 0x9a0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0990*/ FADD.FTZ R5, R11, c[0x0][0x178] ; /* 0x00005e000b057621 */
/* 0x000fe40000010000 */
/*09a0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*09b0*/ IMAD.MOV.U32 R6, RZ, RZ, R5 ; /* 0x000000ffff067224 */
/* 0x001fe400078e0005 */
/*09c0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*09d0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff62004007950 */
/* 0x000fea0003c3ffff */
/*09e0*/ BRA 0x9e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
============================================================================
Name : lab.cu
Author :
Version :
Copyright : Your copyright notice
Description : CUDA compute reciprocals
============================================================================
*/
#include <iostream>
#include <numeric>
#include <stdlib.h>
#include <fstream>
//#include <stdio.h>
static void CheckCudaErrorAux (const char *, unsigned, const char *, cudaError_t);
#define CUDA_CHECK_RETURN(value) CheckCudaErrorAux(__FILE__,__LINE__, #value, value)
struct Params
{
int length;
int time;
float dx;
float dt;
float startT;
float endT;
};
void initialize(float **data, Params inParam)
{
for (unsigned i = 0; i < inParam.time; ++i)
data[i] = new float[inParam.length];
}
/**
* CUDA kernel that computes reciprocal values for a given vector
*/
__global__ void reciprocalKernel(float *OldData,float *NewData, Params inParams) {
unsigned idx = blockIdx.x*blockDim.x+threadIdx.x;
if(idx == 0)
NewData[idx] = inParams.startT;
else if (idx == inParams.length - 1 )
NewData[idx] = inParams.endT * inParams.dt + OldData[idx];
else
{
NewData[idx] = ((OldData[idx+1] - 2 * OldData[idx] + OldData[idx-1])* inParams.dt)/inParams.dx * inParams.dx + OldData[idx];
}
}
/**
* Host function that copies the data and launches the work on GPU
*/
void gpuReciprocal(float *data, Params inParams)
{
float *rc = new float[inParams.length];
float *gpuOldData;
float *gpuNewData;
cudaEvent_t GPUstart, GPUstop;
float GPUtime = 0.0f;
cudaEventCreate(&GPUstart);
cudaEventCreate(&GPUstop);
CUDA_CHECK_RETURN(cudaMalloc((void **)&gpuOldData, sizeof(float)*inParams.length));
CUDA_CHECK_RETURN(cudaMemcpy(gpuOldData, rc, sizeof(float)*inParams.length, cudaMemcpyHostToDevice));
CUDA_CHECK_RETURN(cudaMalloc((void **)&gpuNewData, sizeof(float)*inParams.length));
CUDA_CHECK_RETURN(cudaMemcpy(gpuNewData, data, sizeof(float)*inParams.length, cudaMemcpyHostToDevice));
static const int BLOCK_SIZE = 26;
const int blockCount = 1;
for(int i = 0; i < inParams.time; ++i)
{
cudaEventRecord(GPUstart, 0);
if (i % 2 == 0)
{
reciprocalKernel<<<blockCount, BLOCK_SIZE>>> (gpuOldData, gpuNewData, inParams);
cudaEventRecord(GPUstop, 0);
CUDA_CHECK_RETURN(cudaMemcpy(rc, gpuNewData, sizeof(float)*inParams.length, cudaMemcpyDeviceToHost));
}
else
{
reciprocalKernel<<<blockCount, BLOCK_SIZE>>> (gpuNewData, gpuOldData, inParams);
cudaEventRecord(GPUstop, 0);
CUDA_CHECK_RETURN(cudaMemcpy(rc, gpuOldData, sizeof(float)*inParams.length, cudaMemcpyDeviceToHost));
}
cudaEventSynchronize(GPUstop);
std::cout << i <<": ";
for(int i =0; i < inParams.length; ++i)
std::cout << rc[i] << " ";
std::cout << std::endl;
float temp;
cudaEventElapsedTime(&temp,GPUstart, GPUstop);
GPUtime += temp;
}
printf("GPU time = %.3f ms\n",GPUtime);
}
void initializeData(float* data, unsigned size, float defaultValue)
{
for(int i = 0; i < size; ++i)
data[i] = defaultValue;
}
void print(float **a, unsigned h, unsigned w)
{
for(int i = 0; i < h; ++i)
{
std::cout << i << ": ";
for(int j = 0; j < w; ++j)
std::cout << a[i][j] << " ";
std::cout << std::endl;
}
}
float **cpuReciprocal(float **data,Params inParams)
{
float CPUstart, CPUstop;
float CPUtime = 0.0f;
float **cpuResult = new float*[inParams.time];
initialize(cpuResult, inParams);
float * currentData = cpuResult[0];
initializeData(currentData, inParams.length, 0);
currentData[0] = inParams.startT;
for(int i =1; i < inParams.time; ++i)
{
cpuResult[i][0] = inParams.startT;
for(int j = 1; j < inParams.length - 1; ++j)
{
cpuResult[i][j] = ((cpuResult[i-1][j+1] - 2 * cpuResult[i-1][j] + cpuResult[i-1][j-1])* inParams.dt)/inParams.dx * inParams.dx + cpuResult[i-1][j];
}
cpuResult[i][inParams.length-1] = inParams.endT * inParams.dt + cpuResult[i-1][inParams.length-1];
}
return cpuResult;
}
int main(void)
{
Params mainParams;
mainParams.length = 13;
mainParams.time = 20;
mainParams.dx = 0.5;
mainParams.dt = 0.1;
mainParams.startT = 0.0;
mainParams.endT = 5.0;
float **data;
data = new float*[mainParams.time];
initialize(data, mainParams);
std::cout << "CPU" << std::endl;
float **recCpu = cpuReciprocal(data, mainParams);
print(recCpu, mainParams.time, mainParams.length);
std::cout << "GPU" << std::endl;
float *dataTwo;
dataTwo = new float[mainParams.length];
gpuReciprocal(dataTwo, mainParams);
//print(recGpu, mainParams.time, mainParams.length);
// float cpuSum = std::accumulate (recCpu, recCpu+WORK_SIZE, 0.0);
// float gpuSum = std::accumulate (recGpu, recGpu+WORK_SIZE, 0.0);
/* Verify the results */
//std::cout<<"gpuSum = "<<gpuSum<< " cpuSum = " <<cpuSum<<std::endl;
/* Free memory */
//delete[] data;
//delete[] recCpu;
//delete[] recGpu;
return 0;
}
/**
* Check the return value of the CUDA runtime API call and exit
* the application if the call has failed.
*/
static void CheckCudaErrorAux (const char *file, unsigned line, const char *statement, cudaError_t err)
{
if (err == cudaSuccess)
return;
std::cerr << statement<<" returned " << cudaGetErrorString(err) << "("<<err<< ") at "<<file<<":"<<line << std::endl;
exit (1);
} | .file "tmpxft_00177b93_00000000-6_lab.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " returned "
.LC1:
.string "("
.LC2:
.string ") at "
.LC3:
.string ":"
#NO_APP
.text
.type _ZL17CheckCudaErrorAuxPKcjS0_9cudaError, @function
_ZL17CheckCudaErrorAuxPKcjS0_9cudaError:
.LFB3845:
.cfi_startproc
testl %ecx, %ecx
jne .L7
ret
.L7:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movl %esi, %r12d
movl %ecx, %ebx
movq %rdx, %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %r13
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r12d, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3845:
.size _ZL17CheckCudaErrorAuxPKcjS0_9cudaError, .-_ZL17CheckCudaErrorAuxPKcjS0_9cudaError
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3848:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3848:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10initializePPf6Params
.type _Z10initializePPf6Params, @function
_Z10initializePPf6Params:
.LFB3839:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl 36(%rsp), %eax
testl %eax, %eax
je .L10
movq %rdi, %rbx
leal -1(%rax), %eax
leaq 8(%rdi,%rax,8), %r12
movabsq $2305843009213693950, %rbp
.L13:
movslq 32(%rsp), %rdi
cmpq %rdi, %rbp
jb .L12
salq $2, %rdi
call _Znam@PLT
movq %rax, (%rbx)
addq $8, %rbx
cmpq %r12, %rbx
jne .L13
.L10:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
call __cxa_throw_bad_array_new_length@PLT
.cfi_endproc
.LFE3839:
.size _Z10initializePPf6Params, .-_Z10initializePPf6Params
.globl _Z14initializeDataPfjf
.type _Z14initializeDataPfjf, @function
_Z14initializeDataPfjf:
.LFB3841:
.cfi_startproc
endbr64
testl %esi, %esi
je .L16
movq %rdi, %rax
movl %esi, %esi
leaq (%rdi,%rsi,4), %rdx
.L18:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L18
.L16:
ret
.cfi_endproc
.LFE3841:
.size _Z14initializeDataPfjf, .-_Z14initializeDataPfjf
.section .rodata.str1.1
.LC4:
.string ": "
.LC5:
.string " "
.text
.globl _Z5printPPfjj
.type _Z5printPPfjj, @function
_Z5printPPfjj:
.LFB3842:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %esi, 8(%rsp)
movl %edx, 12(%rsp)
testl %esi, %esi
je .L20
movq %rdi, %r12
movl %edx, %r13d
salq $2, %r13
movl $0, %r15d
leaq _ZSt4cout(%rip), %rbp
leaq .LC5(%rip), %r14
jmp .L27
.L31:
call _ZSt16__throw_bad_castv@PLT
.L25:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L26:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %r15d
addq $8, %r12
movl 8(%rsp), %eax
cmpl %eax, %r15d
je .L20
.L27:
movl %r15d, %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $2, %edx
leaq .LC4(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
cmpl $0, 12(%rsp)
je .L22
movl $0, %ebx
.L23:
movq (%r12), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r14, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbx, %r13
jne .L23
.L22:
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L31
cmpb $0, 56(%rbx)
je .L25
movzbl 67(%rbx), %esi
jmp .L26
.L20:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3842:
.size _Z5printPPfjj, .-_Z5printPPfjj
.globl _Z13cpuReciprocalPPf6Params
.type _Z13cpuReciprocalPPf6Params, @function
_Z13cpuReciprocalPPf6Params:
.LFB3843:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $16, %rsp
.cfi_def_cfa_offset 64
movl 64(%rsp), %ebx
movl 68(%rsp), %r13d
movss 72(%rsp), %xmm7
movss %xmm7, 12(%rsp)
movss 76(%rsp), %xmm7
movss %xmm7, 8(%rsp)
movl 80(%rsp), %ebp
movslq %r13d, %rax
movq %rax, %rdi
shrq $60, %rdi
jne .L33
leaq 0(,%rax,8), %rdi
call _Znam@PLT
movq %rax, %r12
subq $32, %rsp
.cfi_def_cfa_offset 96
movdqu 96(%rsp), %xmm7
movups %xmm7, (%rsp)
movq 112(%rsp), %rax
movq %rax, 16(%rsp)
movq %r12, %rdi
call _Z10initializePPf6Params
movq (%r12), %r14
addq $32, %rsp
.cfi_def_cfa_offset 64
pxor %xmm0, %xmm0
movl %ebx, %esi
movq %r14, %rdi
call _Z14initializeDataPfjf
movl %ebp, (%r14)
cmpl $1, %r13d
jle .L32
movss 8(%rsp), %xmm4
mulss 84(%rsp), %xmm4
movslq %ebx, %rax
leaq -4(,%rax,4), %r8
leaq 8(%r12), %rdi
leal -2(%r13), %eax
leaq 16(%r12,%rax,8), %r9
leal -3(%rbx), %eax
leaq 12(,%rax,4), %rsi
.L38:
movq %rdi, %rdx
movq (%rdi), %rax
movl %ebp, (%rax)
cmpl $2, %ebx
jle .L36
movl $8, %eax
.L37:
movq -8(%rdx), %r10
movss -4(%r10,%rax), %xmm2
movq (%rdx), %rcx
movaps %xmm2, %xmm3
addss %xmm2, %xmm3
movss (%r10,%rax), %xmm1
subss %xmm3, %xmm1
movaps %xmm1, %xmm0
addss -8(%r10,%rax), %xmm0
mulss 8(%rsp), %xmm0
movss 12(%rsp), %xmm5
divss %xmm5, %xmm0
mulss %xmm5, %xmm0
addss %xmm2, %xmm0
movss %xmm0, -4(%rcx,%rax)
addq $4, %rax
cmpq %rsi, %rax
jne .L37
.L36:
movq (%rdx), %rax
movq -8(%rdx), %rdx
movaps %xmm4, %xmm0
addss (%rdx,%r8), %xmm0
movss %xmm0, (%rax,%r8)
addq $8, %rdi
cmpq %r9, %rdi
jne .L38
.L32:
movq %r12, %rax
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
call __cxa_throw_bad_array_new_length@PLT
.cfi_endproc
.LFE3843:
.size _Z13cpuReciprocalPPf6Params, .-_Z13cpuReciprocalPPf6Params
.globl _Z45__device_stub__Z16reciprocalKernelPfS_6ParamsPfS_R6Params
.type _Z45__device_stub__Z16reciprocalKernelPfS_6ParamsPfS_R6Params, @function
_Z45__device_stub__Z16reciprocalKernelPfS_6ParamsPfS_R6Params:
.LFB3870:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movq %rdx, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L46
.L42:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L47
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16reciprocalKernelPfS_6Params(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L42
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3870:
.size _Z45__device_stub__Z16reciprocalKernelPfS_6ParamsPfS_R6Params, .-_Z45__device_stub__Z16reciprocalKernelPfS_6ParamsPfS_R6Params
.globl _Z16reciprocalKernelPfS_6Params
.type _Z16reciprocalKernelPfS_6Params, @function
_Z16reciprocalKernelPfS_6Params:
.LFB3871:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq 16(%rsp), %rdx
call _Z45__device_stub__Z16reciprocalKernelPfS_6ParamsPfS_R6Params
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3871:
.size _Z16reciprocalKernelPfS_6Params, .-_Z16reciprocalKernelPfS_6Params
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "cudaMalloc((void **)&gpuOldData, sizeof(float)*inParams.length)"
.align 8
.LC8:
.string "/home/ubuntu/Datasets/stackv2/train-structured/sudoHackIn/CUDA/master/lab.cu"
.align 8
.LC9:
.string "cudaMemcpy(gpuOldData, rc, sizeof(float)*inParams.length, cudaMemcpyHostToDevice)"
.align 8
.LC10:
.string "cudaMalloc((void **)&gpuNewData, sizeof(float)*inParams.length)"
.align 8
.LC11:
.string "cudaMemcpy(gpuNewData, data, sizeof(float)*inParams.length, cudaMemcpyHostToDevice)"
.align 8
.LC12:
.string "cudaMemcpy(rc, gpuNewData, sizeof(float)*inParams.length, cudaMemcpyDeviceToHost)"
.align 8
.LC13:
.string "cudaMemcpy(rc, gpuOldData, sizeof(float)*inParams.length, cudaMemcpyDeviceToHost)"
.section .rodata.str1.1
.LC14:
.string "GPU time = %.3f ms\n"
.text
.globl _Z13gpuReciprocalPf6Params
.type _Z13gpuReciprocalPf6Params, @function
_Z13gpuReciprocalPf6Params:
.LFB3840:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl 192(%rsp), %r15d
movl 196(%rsp), %r12d
movl %r12d, 20(%rsp)
movslq %r15d, %rax
movabsq $2305843009213693950, %rdx
cmpq %rax, %rdx
jb .L51
movq %rdi, %rbp
leaq 0(,%rax,4), %r14
movq %r14, 24(%rsp)
movq %r14, %rdi
call _Znam@PLT
movq %rax, %r13
movq %rax, 8(%rsp)
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %ecx
leaq .LC7(%rip), %rdx
movl $69, %esi
leaq .LC8(%rip), %rbx
movq %rbx, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
movl $1, %ecx
movq %r14, %rdx
movq %r13, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ecx
leaq .LC9(%rip), %rdx
movl $70, %esi
movq %rbx, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
leaq 48(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %ecx
leaq .LC10(%rip), %rdx
movl $71, %esi
movq %rbx, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
movl $1, %ecx
movq %r14, %rdx
movq %rbp, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ecx
leaq .LC11(%rip), %rdx
movl $72, %esi
movq %rbx, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
addq %r13, %r14
movl $0, %r13d
movl $0x00000000, 16(%rsp)
leaq _ZSt4cout(%rip), %rbp
testl %r12d, %r12d
jg .L65
.L53:
pxor %xmm0, %xmm0
cvtss2sd 16(%rsp), %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L72
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
movq 120(%rsp), %rax
subq %fs:40, %rax
je .L54
call __stack_chk_fail@PLT
.L54:
call __cxa_throw_bad_array_new_length@PLT
.L56:
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq 24(%rsp), %rdx
movq 48(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ecx
leaq .LC12(%rip), %rdx
movl $83, %esi
leaq .LC8(%rip), %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
.L57:
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
movl %r13d, %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $2, %edx
leaq .LC4(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
testl %r15d, %r15d
jle .L59
movq 8(%rsp), %rbx
leaq .LC5(%rip), %r12
.L60:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r14, %rbx
jne .L60
.L59:
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L73
cmpb $0, 56(%rbx)
je .L63
movzbl 67(%rbx), %esi
.L64:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq 96(%rsp), %rdi
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 16(%rsp), %xmm1
addss 96(%rsp), %xmm1
movss %xmm1, 16(%rsp)
addl $1, %r13d
cmpl %r13d, 20(%rsp)
je .L53
.L65:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
testb $1, %r13b
jne .L55
movl $26, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movl $1, %ecx
movq 72(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L56
movl %r15d, 192(%rsp)
movl 20(%rsp), %eax
movl %eax, 196(%rsp)
movdqu 192(%rsp), %xmm2
movaps %xmm2, 96(%rsp)
movq 208(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z45__device_stub__Z16reciprocalKernelPfS_6ParamsPfS_R6Params
jmp .L56
.L55:
movl $26, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movl $1, %ecx
movq 72(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L74
.L58:
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq 24(%rsp), %rdx
movq 40(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ecx
leaq .LC13(%rip), %rdx
movl $91, %esi
leaq .LC8(%rip), %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
jmp .L57
.L74:
movl %r15d, 192(%rsp)
movl 20(%rsp), %eax
movl %eax, 196(%rsp)
movdqu 192(%rsp), %xmm3
movaps %xmm3, 96(%rsp)
movq 208(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rdx
movq 40(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z45__device_stub__Z16reciprocalKernelPfS_6ParamsPfS_R6Params
jmp .L58
.L73:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L75
call _ZSt16__throw_bad_castv@PLT
.L75:
call __stack_chk_fail@PLT
.L63:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L64
.L72:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3840:
.size _Z13gpuReciprocalPf6Params, .-_Z13gpuReciprocalPf6Params
.section .rodata.str1.1
.LC18:
.string "CPU"
.LC19:
.string "GPU"
.text
.globl main
.type main, @function
main:
.LFB3844:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movl $0x3f000000, 8(%rsp)
movl $0x3dcccccd, 12(%rsp)
movl $0x00000000, 16(%rsp)
movl $0x40a00000, 20(%rsp)
movl $160, %edi
call _Znam@PLT
movq %rax, %rbx
movl $13, (%rsp)
movl $20, 4(%rsp)
subq $32, %rsp
.cfi_def_cfa_offset 96
movdqa 32(%rsp), %xmm0
movups %xmm0, (%rsp)
movq 48(%rsp), %rax
movq %rax, 16(%rsp)
movq %rbx, %rdi
call _Z10initializePPf6Params
addq $32, %rsp
.cfi_def_cfa_offset 64
leaq .LC18(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
subq $32, %rsp
.cfi_def_cfa_offset 96
movdqa 32(%rsp), %xmm1
movups %xmm1, (%rsp)
movq 48(%rsp), %rax
movq %rax, 16(%rsp)
movq %rbx, %rdi
call _Z13cpuReciprocalPPf6Params
movq %rax, %rdi
addq $32, %rsp
.cfi_def_cfa_offset 64
movl $13, %edx
movl $20, %esi
call _Z5printPPfjj
leaq .LC19(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $52, %edi
call _Znam@PLT
movq %rax, %rdi
subq $32, %rsp
.cfi_def_cfa_offset 96
movdqa 32(%rsp), %xmm2
movups %xmm2, (%rsp)
movq 48(%rsp), %rax
movq %rax, 16(%rsp)
call _Z13gpuReciprocalPf6Params
movl $0, %eax
addq $72, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3844:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC20:
.string "_Z16reciprocalKernelPfS_6Params"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3873:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z16reciprocalKernelPfS_6Params(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3873:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
============================================================================
Name : lab.cu
Author :
Version :
Copyright : Your copyright notice
Description : CUDA compute reciprocals
============================================================================
*/
#include <iostream>
#include <numeric>
#include <stdlib.h>
#include <fstream>
//#include <stdio.h>
static void CheckCudaErrorAux (const char *, unsigned, const char *, cudaError_t);
#define CUDA_CHECK_RETURN(value) CheckCudaErrorAux(__FILE__,__LINE__, #value, value)
struct Params
{
int length;
int time;
float dx;
float dt;
float startT;
float endT;
};
void initialize(float **data, Params inParam)
{
for (unsigned i = 0; i < inParam.time; ++i)
data[i] = new float[inParam.length];
}
/**
* CUDA kernel that computes reciprocal values for a given vector
*/
__global__ void reciprocalKernel(float *OldData,float *NewData, Params inParams) {
unsigned idx = blockIdx.x*blockDim.x+threadIdx.x;
if(idx == 0)
NewData[idx] = inParams.startT;
else if (idx == inParams.length - 1 )
NewData[idx] = inParams.endT * inParams.dt + OldData[idx];
else
{
NewData[idx] = ((OldData[idx+1] - 2 * OldData[idx] + OldData[idx-1])* inParams.dt)/inParams.dx * inParams.dx + OldData[idx];
}
}
/**
* Host function that copies the data and launches the work on GPU
*/
void gpuReciprocal(float *data, Params inParams)
{
float *rc = new float[inParams.length];
float *gpuOldData;
float *gpuNewData;
cudaEvent_t GPUstart, GPUstop;
float GPUtime = 0.0f;
cudaEventCreate(&GPUstart);
cudaEventCreate(&GPUstop);
CUDA_CHECK_RETURN(cudaMalloc((void **)&gpuOldData, sizeof(float)*inParams.length));
CUDA_CHECK_RETURN(cudaMemcpy(gpuOldData, rc, sizeof(float)*inParams.length, cudaMemcpyHostToDevice));
CUDA_CHECK_RETURN(cudaMalloc((void **)&gpuNewData, sizeof(float)*inParams.length));
CUDA_CHECK_RETURN(cudaMemcpy(gpuNewData, data, sizeof(float)*inParams.length, cudaMemcpyHostToDevice));
static const int BLOCK_SIZE = 26;
const int blockCount = 1;
for(int i = 0; i < inParams.time; ++i)
{
cudaEventRecord(GPUstart, 0);
if (i % 2 == 0)
{
reciprocalKernel<<<blockCount, BLOCK_SIZE>>> (gpuOldData, gpuNewData, inParams);
cudaEventRecord(GPUstop, 0);
CUDA_CHECK_RETURN(cudaMemcpy(rc, gpuNewData, sizeof(float)*inParams.length, cudaMemcpyDeviceToHost));
}
else
{
reciprocalKernel<<<blockCount, BLOCK_SIZE>>> (gpuNewData, gpuOldData, inParams);
cudaEventRecord(GPUstop, 0);
CUDA_CHECK_RETURN(cudaMemcpy(rc, gpuOldData, sizeof(float)*inParams.length, cudaMemcpyDeviceToHost));
}
cudaEventSynchronize(GPUstop);
std::cout << i <<": ";
for(int i =0; i < inParams.length; ++i)
std::cout << rc[i] << " ";
std::cout << std::endl;
float temp;
cudaEventElapsedTime(&temp,GPUstart, GPUstop);
GPUtime += temp;
}
printf("GPU time = %.3f ms\n",GPUtime);
}
void initializeData(float* data, unsigned size, float defaultValue)
{
for(int i = 0; i < size; ++i)
data[i] = defaultValue;
}
void print(float **a, unsigned h, unsigned w)
{
for(int i = 0; i < h; ++i)
{
std::cout << i << ": ";
for(int j = 0; j < w; ++j)
std::cout << a[i][j] << " ";
std::cout << std::endl;
}
}
float **cpuReciprocal(float **data,Params inParams)
{
float CPUstart, CPUstop;
float CPUtime = 0.0f;
float **cpuResult = new float*[inParams.time];
initialize(cpuResult, inParams);
float * currentData = cpuResult[0];
initializeData(currentData, inParams.length, 0);
currentData[0] = inParams.startT;
for(int i =1; i < inParams.time; ++i)
{
cpuResult[i][0] = inParams.startT;
for(int j = 1; j < inParams.length - 1; ++j)
{
cpuResult[i][j] = ((cpuResult[i-1][j+1] - 2 * cpuResult[i-1][j] + cpuResult[i-1][j-1])* inParams.dt)/inParams.dx * inParams.dx + cpuResult[i-1][j];
}
cpuResult[i][inParams.length-1] = inParams.endT * inParams.dt + cpuResult[i-1][inParams.length-1];
}
return cpuResult;
}
int main(void)
{
Params mainParams;
mainParams.length = 13;
mainParams.time = 20;
mainParams.dx = 0.5;
mainParams.dt = 0.1;
mainParams.startT = 0.0;
mainParams.endT = 5.0;
float **data;
data = new float*[mainParams.time];
initialize(data, mainParams);
std::cout << "CPU" << std::endl;
float **recCpu = cpuReciprocal(data, mainParams);
print(recCpu, mainParams.time, mainParams.length);
std::cout << "GPU" << std::endl;
float *dataTwo;
dataTwo = new float[mainParams.length];
gpuReciprocal(dataTwo, mainParams);
//print(recGpu, mainParams.time, mainParams.length);
// float cpuSum = std::accumulate (recCpu, recCpu+WORK_SIZE, 0.0);
// float gpuSum = std::accumulate (recGpu, recGpu+WORK_SIZE, 0.0);
/* Verify the results */
//std::cout<<"gpuSum = "<<gpuSum<< " cpuSum = " <<cpuSum<<std::endl;
/* Free memory */
//delete[] data;
//delete[] recCpu;
//delete[] recGpu;
return 0;
}
/**
* Check the return value of the CUDA runtime API call and exit
* the application if the call has failed.
*/
static void CheckCudaErrorAux (const char *file, unsigned line, const char *statement, cudaError_t err)
{
if (err == cudaSuccess)
return;
std::cerr << statement<<" returned " << cudaGetErrorString(err) << "("<<err<< ") at "<<file<<":"<<line << std::endl;
exit (1);
} | /*
============================================================================
Name : lab.cu
Author :
Version :
Copyright : Your copyright notice
Description : CUDA compute reciprocals
============================================================================
*/
#include <hip/hip_runtime.h>
#include <iostream>
#include <numeric>
#include <stdlib.h>
#include <fstream>
//#include <stdio.h>
static void CheckCudaErrorAux (const char *, unsigned, const char *, hipError_t);
#define CUDA_CHECK_RETURN(value) CheckCudaErrorAux(__FILE__,__LINE__, #value, value)
struct Params
{
int length;
int time;
float dx;
float dt;
float startT;
float endT;
};
void initialize(float **data, Params inParam)
{
for (unsigned i = 0; i < inParam.time; ++i)
data[i] = new float[inParam.length];
}
/**
* CUDA kernel that computes reciprocal values for a given vector
*/
__global__ void reciprocalKernel(float *OldData,float *NewData, Params inParams) {
unsigned idx = blockIdx.x*blockDim.x+threadIdx.x;
if(idx == 0)
NewData[idx] = inParams.startT;
else if (idx == inParams.length - 1 )
NewData[idx] = inParams.endT * inParams.dt + OldData[idx];
else
{
NewData[idx] = ((OldData[idx+1] - 2 * OldData[idx] + OldData[idx-1])* inParams.dt)/inParams.dx * inParams.dx + OldData[idx];
}
}
/**
* Host function that copies the data and launches the work on GPU
*/
void gpuReciprocal(float *data, Params inParams)
{
float *rc = new float[inParams.length];
float *gpuOldData;
float *gpuNewData;
hipEvent_t GPUstart, GPUstop;
float GPUtime = 0.0f;
hipEventCreate(&GPUstart);
hipEventCreate(&GPUstop);
CUDA_CHECK_RETURN(hipMalloc((void **)&gpuOldData, sizeof(float)*inParams.length));
CUDA_CHECK_RETURN(hipMemcpy(gpuOldData, rc, sizeof(float)*inParams.length, hipMemcpyHostToDevice));
CUDA_CHECK_RETURN(hipMalloc((void **)&gpuNewData, sizeof(float)*inParams.length));
CUDA_CHECK_RETURN(hipMemcpy(gpuNewData, data, sizeof(float)*inParams.length, hipMemcpyHostToDevice));
static const int BLOCK_SIZE = 26;
const int blockCount = 1;
for(int i = 0; i < inParams.time; ++i)
{
hipEventRecord(GPUstart, 0);
if (i % 2 == 0)
{
reciprocalKernel<<<blockCount, BLOCK_SIZE>>> (gpuOldData, gpuNewData, inParams);
hipEventRecord(GPUstop, 0);
CUDA_CHECK_RETURN(hipMemcpy(rc, gpuNewData, sizeof(float)*inParams.length, hipMemcpyDeviceToHost));
}
else
{
reciprocalKernel<<<blockCount, BLOCK_SIZE>>> (gpuNewData, gpuOldData, inParams);
hipEventRecord(GPUstop, 0);
CUDA_CHECK_RETURN(hipMemcpy(rc, gpuOldData, sizeof(float)*inParams.length, hipMemcpyDeviceToHost));
}
hipEventSynchronize(GPUstop);
std::cout << i <<": ";
for(int i =0; i < inParams.length; ++i)
std::cout << rc[i] << " ";
std::cout << std::endl;
float temp;
hipEventElapsedTime(&temp,GPUstart, GPUstop);
GPUtime += temp;
}
printf("GPU time = %.3f ms\n",GPUtime);
}
void initializeData(float* data, unsigned size, float defaultValue)
{
for(int i = 0; i < size; ++i)
data[i] = defaultValue;
}
void print(float **a, unsigned h, unsigned w)
{
for(int i = 0; i < h; ++i)
{
std::cout << i << ": ";
for(int j = 0; j < w; ++j)
std::cout << a[i][j] << " ";
std::cout << std::endl;
}
}
float **cpuReciprocal(float **data,Params inParams)
{
float CPUstart, CPUstop;
float CPUtime = 0.0f;
float **cpuResult = new float*[inParams.time];
initialize(cpuResult, inParams);
float * currentData = cpuResult[0];
initializeData(currentData, inParams.length, 0);
currentData[0] = inParams.startT;
for(int i =1; i < inParams.time; ++i)
{
cpuResult[i][0] = inParams.startT;
for(int j = 1; j < inParams.length - 1; ++j)
{
cpuResult[i][j] = ((cpuResult[i-1][j+1] - 2 * cpuResult[i-1][j] + cpuResult[i-1][j-1])* inParams.dt)/inParams.dx * inParams.dx + cpuResult[i-1][j];
}
cpuResult[i][inParams.length-1] = inParams.endT * inParams.dt + cpuResult[i-1][inParams.length-1];
}
return cpuResult;
}
int main(void)
{
Params mainParams;
mainParams.length = 13;
mainParams.time = 20;
mainParams.dx = 0.5;
mainParams.dt = 0.1;
mainParams.startT = 0.0;
mainParams.endT = 5.0;
float **data;
data = new float*[mainParams.time];
initialize(data, mainParams);
std::cout << "CPU" << std::endl;
float **recCpu = cpuReciprocal(data, mainParams);
print(recCpu, mainParams.time, mainParams.length);
std::cout << "GPU" << std::endl;
float *dataTwo;
dataTwo = new float[mainParams.length];
gpuReciprocal(dataTwo, mainParams);
//print(recGpu, mainParams.time, mainParams.length);
// float cpuSum = std::accumulate (recCpu, recCpu+WORK_SIZE, 0.0);
// float gpuSum = std::accumulate (recGpu, recGpu+WORK_SIZE, 0.0);
/* Verify the results */
//std::cout<<"gpuSum = "<<gpuSum<< " cpuSum = " <<cpuSum<<std::endl;
/* Free memory */
//delete[] data;
//delete[] recCpu;
//delete[] recGpu;
return 0;
}
/**
* Check the return value of the CUDA runtime API call and exit
* the application if the call has failed.
*/
static void CheckCudaErrorAux (const char *file, unsigned line, const char *statement, hipError_t err)
{
if (err == hipSuccess)
return;
std::cerr << statement<<" returned " << hipGetErrorString(err) << "("<<err<< ") at "<<file<<":"<<line << std::endl;
exit (1);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
============================================================================
Name : lab.cu
Author :
Version :
Copyright : Your copyright notice
Description : CUDA compute reciprocals
============================================================================
*/
#include <hip/hip_runtime.h>
#include <iostream>
#include <numeric>
#include <stdlib.h>
#include <fstream>
//#include <stdio.h>
static void CheckCudaErrorAux (const char *, unsigned, const char *, hipError_t);
#define CUDA_CHECK_RETURN(value) CheckCudaErrorAux(__FILE__,__LINE__, #value, value)
struct Params
{
int length;
int time;
float dx;
float dt;
float startT;
float endT;
};
void initialize(float **data, Params inParam)
{
for (unsigned i = 0; i < inParam.time; ++i)
data[i] = new float[inParam.length];
}
/**
* CUDA kernel that computes reciprocal values for a given vector
*/
__global__ void reciprocalKernel(float *OldData,float *NewData, Params inParams) {
unsigned idx = blockIdx.x*blockDim.x+threadIdx.x;
if(idx == 0)
NewData[idx] = inParams.startT;
else if (idx == inParams.length - 1 )
NewData[idx] = inParams.endT * inParams.dt + OldData[idx];
else
{
NewData[idx] = ((OldData[idx+1] - 2 * OldData[idx] + OldData[idx-1])* inParams.dt)/inParams.dx * inParams.dx + OldData[idx];
}
}
/**
* Host function that copies the data and launches the work on GPU
*/
void gpuReciprocal(float *data, Params inParams)
{
float *rc = new float[inParams.length];
float *gpuOldData;
float *gpuNewData;
hipEvent_t GPUstart, GPUstop;
float GPUtime = 0.0f;
hipEventCreate(&GPUstart);
hipEventCreate(&GPUstop);
CUDA_CHECK_RETURN(hipMalloc((void **)&gpuOldData, sizeof(float)*inParams.length));
CUDA_CHECK_RETURN(hipMemcpy(gpuOldData, rc, sizeof(float)*inParams.length, hipMemcpyHostToDevice));
CUDA_CHECK_RETURN(hipMalloc((void **)&gpuNewData, sizeof(float)*inParams.length));
CUDA_CHECK_RETURN(hipMemcpy(gpuNewData, data, sizeof(float)*inParams.length, hipMemcpyHostToDevice));
static const int BLOCK_SIZE = 26;
const int blockCount = 1;
for(int i = 0; i < inParams.time; ++i)
{
hipEventRecord(GPUstart, 0);
if (i % 2 == 0)
{
reciprocalKernel<<<blockCount, BLOCK_SIZE>>> (gpuOldData, gpuNewData, inParams);
hipEventRecord(GPUstop, 0);
CUDA_CHECK_RETURN(hipMemcpy(rc, gpuNewData, sizeof(float)*inParams.length, hipMemcpyDeviceToHost));
}
else
{
reciprocalKernel<<<blockCount, BLOCK_SIZE>>> (gpuNewData, gpuOldData, inParams);
hipEventRecord(GPUstop, 0);
CUDA_CHECK_RETURN(hipMemcpy(rc, gpuOldData, sizeof(float)*inParams.length, hipMemcpyDeviceToHost));
}
hipEventSynchronize(GPUstop);
std::cout << i <<": ";
for(int i =0; i < inParams.length; ++i)
std::cout << rc[i] << " ";
std::cout << std::endl;
float temp;
hipEventElapsedTime(&temp,GPUstart, GPUstop);
GPUtime += temp;
}
printf("GPU time = %.3f ms\n",GPUtime);
}
void initializeData(float* data, unsigned size, float defaultValue)
{
for(int i = 0; i < size; ++i)
data[i] = defaultValue;
}
void print(float **a, unsigned h, unsigned w)
{
for(int i = 0; i < h; ++i)
{
std::cout << i << ": ";
for(int j = 0; j < w; ++j)
std::cout << a[i][j] << " ";
std::cout << std::endl;
}
}
float **cpuReciprocal(float **data,Params inParams)
{
float CPUstart, CPUstop;
float CPUtime = 0.0f;
float **cpuResult = new float*[inParams.time];
initialize(cpuResult, inParams);
float * currentData = cpuResult[0];
initializeData(currentData, inParams.length, 0);
currentData[0] = inParams.startT;
for(int i =1; i < inParams.time; ++i)
{
cpuResult[i][0] = inParams.startT;
for(int j = 1; j < inParams.length - 1; ++j)
{
cpuResult[i][j] = ((cpuResult[i-1][j+1] - 2 * cpuResult[i-1][j] + cpuResult[i-1][j-1])* inParams.dt)/inParams.dx * inParams.dx + cpuResult[i-1][j];
}
cpuResult[i][inParams.length-1] = inParams.endT * inParams.dt + cpuResult[i-1][inParams.length-1];
}
return cpuResult;
}
int main(void)
{
Params mainParams;
mainParams.length = 13;
mainParams.time = 20;
mainParams.dx = 0.5;
mainParams.dt = 0.1;
mainParams.startT = 0.0;
mainParams.endT = 5.0;
float **data;
data = new float*[mainParams.time];
initialize(data, mainParams);
std::cout << "CPU" << std::endl;
float **recCpu = cpuReciprocal(data, mainParams);
print(recCpu, mainParams.time, mainParams.length);
std::cout << "GPU" << std::endl;
float *dataTwo;
dataTwo = new float[mainParams.length];
gpuReciprocal(dataTwo, mainParams);
//print(recGpu, mainParams.time, mainParams.length);
// float cpuSum = std::accumulate (recCpu, recCpu+WORK_SIZE, 0.0);
// float gpuSum = std::accumulate (recGpu, recGpu+WORK_SIZE, 0.0);
/* Verify the results */
//std::cout<<"gpuSum = "<<gpuSum<< " cpuSum = " <<cpuSum<<std::endl;
/* Free memory */
//delete[] data;
//delete[] recCpu;
//delete[] recGpu;
return 0;
}
/**
* Check the return value of the CUDA runtime API call and exit
* the application if the call has failed.
*/
static void CheckCudaErrorAux (const char *file, unsigned line, const char *statement, hipError_t err)
{
if (err == hipSuccess)
return;
std::cerr << statement<<" returned " << hipGetErrorString(err) << "("<<err<< ") at "<<file<<":"<<line << std::endl;
exit (1);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16reciprocalKernelPfS_6Params
.globl _Z16reciprocalKernelPfS_6Params
.p2align 8
.type _Z16reciprocalKernelPfS_6Params,@function
_Z16reciprocalKernelPfS_6Params:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_mov_b32 s4, exec_lo
v_cmpx_ne_u32_e32 0, v1
s_xor_b32 s8, exec_lo, s4
s_cbranch_execnz .LBB0_3
s_and_not1_saveexec_b32 s4, s8
s_cbranch_execnz .LBB0_8
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_3:
s_clause 0x2
s_load_b32 s10, s[0:1], 0x10
s_load_b64 s[6:7], s[0:1], 0x0
s_load_b32 s9, s[0:1], 0x1c
s_add_u32 s4, s0, 16
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_add_i32 s10, s10, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ne_u32_e32 vcc_lo, s10, v1
s_and_saveexec_b32 s10, vcc_lo
s_xor_b32 s10, exec_lo, s10
s_cbranch_execz .LBB0_5
v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, 1, v1
s_load_b32 s11, s[4:5], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v2, v4
v_lshlrev_b64 v[5:6], 2, v[3:4]
v_add_nc_u32_e32 v3, -1, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v6, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_clause 0x2
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[6:7], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_fmac_f32_e32 v4, -2.0, v5
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v2, v4
v_mul_f32_e32 v2, s9, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v3, null, s11, s11, v2
v_div_scale_f32 v7, vcc_lo, v2, s11, v2
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v3, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v6, v4
v_mul_f32_e32 v6, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v3, v6, v7
v_fmac_f32_e32 v6, v8, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v6, v7
v_div_fmas_f32 v3, v3, v4, v6
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v2, v3, s11, v2
v_fmac_f32_e32 v5, s11, v2
global_store_b32 v[0:1], v5, off
.LBB0_5:
s_and_not1_saveexec_b32 s10, s10
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v2, 0
s_load_b32 s4, s[4:5], 0x14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e64 v2, s9, s4
global_store_b32 v[0:1], v2, off
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s10
s_and_not1_saveexec_b32 s4, s8
s_cbranch_execz .LBB0_2
.LBB0_8:
s_load_b32 s0, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16reciprocalKernelPfS_6Params
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16reciprocalKernelPfS_6Params, .Lfunc_end0-_Z16reciprocalKernelPfS_6Params
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 24
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16reciprocalKernelPfS_6Params
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16reciprocalKernelPfS_6Params.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
============================================================================
Name : lab.cu
Author :
Version :
Copyright : Your copyright notice
Description : CUDA compute reciprocals
============================================================================
*/
#include <hip/hip_runtime.h>
#include <iostream>
#include <numeric>
#include <stdlib.h>
#include <fstream>
//#include <stdio.h>
static void CheckCudaErrorAux (const char *, unsigned, const char *, hipError_t);
#define CUDA_CHECK_RETURN(value) CheckCudaErrorAux(__FILE__,__LINE__, #value, value)
struct Params
{
int length;
int time;
float dx;
float dt;
float startT;
float endT;
};
void initialize(float **data, Params inParam)
{
for (unsigned i = 0; i < inParam.time; ++i)
data[i] = new float[inParam.length];
}
/**
* CUDA kernel that computes reciprocal values for a given vector
*/
__global__ void reciprocalKernel(float *OldData,float *NewData, Params inParams) {
unsigned idx = blockIdx.x*blockDim.x+threadIdx.x;
if(idx == 0)
NewData[idx] = inParams.startT;
else if (idx == inParams.length - 1 )
NewData[idx] = inParams.endT * inParams.dt + OldData[idx];
else
{
NewData[idx] = ((OldData[idx+1] - 2 * OldData[idx] + OldData[idx-1])* inParams.dt)/inParams.dx * inParams.dx + OldData[idx];
}
}
/**
* Host function that copies the data and launches the work on GPU
*/
void gpuReciprocal(float *data, Params inParams)
{
float *rc = new float[inParams.length];
float *gpuOldData;
float *gpuNewData;
hipEvent_t GPUstart, GPUstop;
float GPUtime = 0.0f;
hipEventCreate(&GPUstart);
hipEventCreate(&GPUstop);
CUDA_CHECK_RETURN(hipMalloc((void **)&gpuOldData, sizeof(float)*inParams.length));
CUDA_CHECK_RETURN(hipMemcpy(gpuOldData, rc, sizeof(float)*inParams.length, hipMemcpyHostToDevice));
CUDA_CHECK_RETURN(hipMalloc((void **)&gpuNewData, sizeof(float)*inParams.length));
CUDA_CHECK_RETURN(hipMemcpy(gpuNewData, data, sizeof(float)*inParams.length, hipMemcpyHostToDevice));
static const int BLOCK_SIZE = 26;
const int blockCount = 1;
for(int i = 0; i < inParams.time; ++i)
{
hipEventRecord(GPUstart, 0);
if (i % 2 == 0)
{
reciprocalKernel<<<blockCount, BLOCK_SIZE>>> (gpuOldData, gpuNewData, inParams);
hipEventRecord(GPUstop, 0);
CUDA_CHECK_RETURN(hipMemcpy(rc, gpuNewData, sizeof(float)*inParams.length, hipMemcpyDeviceToHost));
}
else
{
reciprocalKernel<<<blockCount, BLOCK_SIZE>>> (gpuNewData, gpuOldData, inParams);
hipEventRecord(GPUstop, 0);
CUDA_CHECK_RETURN(hipMemcpy(rc, gpuOldData, sizeof(float)*inParams.length, hipMemcpyDeviceToHost));
}
hipEventSynchronize(GPUstop);
std::cout << i <<": ";
for(int i =0; i < inParams.length; ++i)
std::cout << rc[i] << " ";
std::cout << std::endl;
float temp;
hipEventElapsedTime(&temp,GPUstart, GPUstop);
GPUtime += temp;
}
printf("GPU time = %.3f ms\n",GPUtime);
}
void initializeData(float* data, unsigned size, float defaultValue)
{
for(int i = 0; i < size; ++i)
data[i] = defaultValue;
}
void print(float **a, unsigned h, unsigned w)
{
for(int i = 0; i < h; ++i)
{
std::cout << i << ": ";
for(int j = 0; j < w; ++j)
std::cout << a[i][j] << " ";
std::cout << std::endl;
}
}
float **cpuReciprocal(float **data,Params inParams)
{
float CPUstart, CPUstop;
float CPUtime = 0.0f;
float **cpuResult = new float*[inParams.time];
initialize(cpuResult, inParams);
float * currentData = cpuResult[0];
initializeData(currentData, inParams.length, 0);
currentData[0] = inParams.startT;
for(int i =1; i < inParams.time; ++i)
{
cpuResult[i][0] = inParams.startT;
for(int j = 1; j < inParams.length - 1; ++j)
{
cpuResult[i][j] = ((cpuResult[i-1][j+1] - 2 * cpuResult[i-1][j] + cpuResult[i-1][j-1])* inParams.dt)/inParams.dx * inParams.dx + cpuResult[i-1][j];
}
cpuResult[i][inParams.length-1] = inParams.endT * inParams.dt + cpuResult[i-1][inParams.length-1];
}
return cpuResult;
}
int main(void)
{
Params mainParams;
mainParams.length = 13;
mainParams.time = 20;
mainParams.dx = 0.5;
mainParams.dt = 0.1;
mainParams.startT = 0.0;
mainParams.endT = 5.0;
float **data;
data = new float*[mainParams.time];
initialize(data, mainParams);
std::cout << "CPU" << std::endl;
float **recCpu = cpuReciprocal(data, mainParams);
print(recCpu, mainParams.time, mainParams.length);
std::cout << "GPU" << std::endl;
float *dataTwo;
dataTwo = new float[mainParams.length];
gpuReciprocal(dataTwo, mainParams);
//print(recGpu, mainParams.time, mainParams.length);
// float cpuSum = std::accumulate (recCpu, recCpu+WORK_SIZE, 0.0);
// float gpuSum = std::accumulate (recGpu, recGpu+WORK_SIZE, 0.0);
/* Verify the results */
//std::cout<<"gpuSum = "<<gpuSum<< " cpuSum = " <<cpuSum<<std::endl;
/* Free memory */
//delete[] data;
//delete[] recCpu;
//delete[] recGpu;
return 0;
}
/**
* Check the return value of the CUDA runtime API call and exit
* the application if the call has failed.
*/
static void CheckCudaErrorAux (const char *file, unsigned line, const char *statement, hipError_t err)
{
if (err == hipSuccess)
return;
std::cerr << statement<<" returned " << hipGetErrorString(err) << "("<<err<< ") at "<<file<<":"<<line << std::endl;
exit (1);
} | .text
.file "lab.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z10initializePPf6Params # -- Begin function _Z10initializePPf6Params
.p2align 4, 0x90
.type _Z10initializePPf6Params,@function
_Z10initializePPf6Params: # @_Z10initializePPf6Params
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl 52(%rsp), %r15d
testq %r15, %r15
je .LBB0_3
# %bb.1: # %.lr.ph
movq %rdi, %rbx
leaq 48(%rsp), %rax
movslq (%rax), %rax
leaq (,%rax,4), %rcx
testq %rax, %rax
movq $-1, %r14
cmovnsq %rcx, %r14
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_2: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
callq _Znam
movq %rax, (%rbx,%r12,8)
incq %r12
cmpq %r12, %r15
jne .LBB0_2
.LBB0_3: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z10initializePPf6Params, .Lfunc_end0-_Z10initializePPf6Params
.cfi_endproc
# -- End function
.globl _Z31__device_stub__reciprocalKernelPfS_6Params # -- Begin function _Z31__device_stub__reciprocalKernelPfS_6Params
.p2align 4, 0x90
.type _Z31__device_stub__reciprocalKernelPfS_6Params,@function
_Z31__device_stub__reciprocalKernelPfS_6Params: # @_Z31__device_stub__reciprocalKernelPfS_6Params
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 96(%rsp), %rax
movq %rax, 80(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16reciprocalKernelPfS_6Params, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z31__device_stub__reciprocalKernelPfS_6Params, .Lfunc_end1-_Z31__device_stub__reciprocalKernelPfS_6Params
.cfi_endproc
# -- End function
.globl _Z13gpuReciprocalPf6Params # -- Begin function _Z13gpuReciprocalPf6Params
.p2align 4, 0x90
.type _Z13gpuReciprocalPf6Params,@function
_Z13gpuReciprocalPf6Params: # @_Z13gpuReciprocalPf6Params
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %r15
movslq 224(%rsp), %rbx
leaq (,%rbx,4), %r12
testq %rbx, %rbx
movq $-1, %rdi
cmovnsq %r12, %rdi
callq _Znam
movq %rax, %r14
leaq 136(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movl $.L.str.1, %esi
movl $71, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movq 16(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl $.L.str.2, %esi
movl $72, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movl $.L.str.3, %esi
movl $73, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movq 8(%rsp), %rdi
movq %r15, %rsi
movq %r12, 128(%rsp) # 8-byte Spill
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl $.L.str.4, %esi
movl $74, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movl 228(%rsp), %ebp
testl %ebp, %ebp
jle .LBB2_1
# %bb.4: # %.lr.ph42
movl %ebx, %ebx
xorl %r15d, %r15d
xorps %xmm0, %xmm0
movabsq $4294967297, %rax # imm = 0x100000001
leaq 25(%rax), %r13
jmp .LBB2_5
.p2align 4, 0x90
.LBB2_18: # in Loop: Header=BB2_5 Depth=1
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_19: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB2_5 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 136(%rsp), %rsi
movq (%rsp), %rdx
leaq 96(%rsp), %rdi
callq hipEventElapsedTime
movss 92(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
addss 96(%rsp), %xmm0
incl %r15d
cmpl %ebp, %r15d
je .LBB2_2
.LBB2_5: # =>This Loop Header: Depth=1
# Child Loop BB2_14 Depth 2
movss %xmm0, 92(%rsp) # 4-byte Spill
movq 136(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testb $1, %r15b
jne .LBB2_9
# %bb.6: # in Loop: Header=BB2_5 Depth=1
testl %eax, %eax
jne .LBB2_8
# %bb.7: # in Loop: Header=BB2_5 Depth=1
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
leaq 224(%rsp), %rsi
movq 16(%rsi), %rdx
movq %rdx, 160(%rsp)
movups (%rsi), %xmm0
movaps %xmm0, 144(%rsp)
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 144(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z16reciprocalKernelPfS_6Params, %edi
leaq 96(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8: # in Loop: Header=BB2_5 Depth=1
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rsi
movq %r14, %rdi
movq 128(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movl $.L.str.5, %esi
movl $85, %edi
jmp .LBB2_12
.p2align 4, 0x90
.LBB2_9: # in Loop: Header=BB2_5 Depth=1
testl %eax, %eax
jne .LBB2_11
# %bb.10: # in Loop: Header=BB2_5 Depth=1
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
leaq 224(%rsp), %rsi
movq 16(%rsi), %rdx
movq %rdx, 160(%rsp)
movups (%rsi), %xmm0
movaps %xmm0, 144(%rsp)
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 144(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z16reciprocalKernelPfS_6Params, %edi
leaq 96(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_11: # in Loop: Header=BB2_5 Depth=1
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rsi
movq %r14, %rdi
movq 128(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movl $.L.str.6, %esi
movl $93, %edi
.LBB2_12: # in Loop: Header=BB2_5 Depth=1
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movq (%rsp), %rdi
callq hipEventSynchronize
movl $_ZSt4cout, %edi
movl %r15d, %esi
callq _ZNSolsEi
movl $.L.str.7, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
testl %ebx, %ebx
jle .LBB2_15
# %bb.13: # %.lr.ph.preheader
# in Loop: Header=BB2_5 Depth=1
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_14: # %.lr.ph
# Parent Loop BB2_5 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.8, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r12
cmpq %r12, %rbx
jne .LBB2_14
.LBB2_15: # %._crit_edge
# in Loop: Header=BB2_5 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB2_20
# %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB2_5 Depth=1
cmpb $0, 56(%r12)
je .LBB2_18
# %bb.17: # in Loop: Header=BB2_5 Depth=1
movzbl 67(%r12), %eax
jmp .LBB2_19
.LBB2_2: # %._crit_edge43.loopexit
cvtss2sd %xmm0, %xmm0
jmp .LBB2_3
.LBB2_1:
xorps %xmm0, %xmm0
.LBB2_3: # %._crit_edge43
movl $.L.str.9, %edi
movb $1, %al
callq printf
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_20:
.cfi_def_cfa_offset 224
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size _Z13gpuReciprocalPf6Params, .Lfunc_end2-_Z13gpuReciprocalPf6Params
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
.type _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t,@function
_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t: # @_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
.cfi_startproc
# %bb.0:
testl %edx, %edx
jne .LBB3_2
# %bb.1:
retq
.LBB3_2:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %edi, %ebx
movl $_ZSt4cerr, %edi
movl %edx, %ebp
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.12, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebp, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.13, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebp, %esi
callq _ZNSolsEi
movl $.L.str.14, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.15, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebx, %esi
callq _ZNSolsEj
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end3:
.size _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t, .Lfunc_end3-_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
.cfi_endproc
# -- End function
.globl _Z14initializeDataPfjf # -- Begin function _Z14initializeDataPfjf
.p2align 4, 0x90
.type _Z14initializeDataPfjf,@function
_Z14initializeDataPfjf: # @_Z14initializeDataPfjf
.cfi_startproc
# %bb.0:
testl %esi, %esi
je .LBB4_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss %xmm0, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB4_2
.LBB4_3: # %._crit_edge
retq
.Lfunc_end4:
.size _Z14initializeDataPfjf, .Lfunc_end4-_Z14initializeDataPfjf
.cfi_endproc
# -- End function
.globl _Z5printPPfjj # -- Begin function _Z5printPPfjj
.p2align 4, 0x90
.type _Z5printPPfjj,@function
_Z5printPPfjj: # @_Z5printPPfjj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
testl %esi, %esi
je .LBB5_10
# %bb.1: # %.lr.ph13
movl %edx, %ebx
movq %rdi, %r14
movl %esi, %r13d
movl %edx, %ebp
xorl %r15d, %r15d
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_8: # in Loop: Header=BB5_2 Depth=1
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB5_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB5_2 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r15
cmpq %r13, %r15
je .LBB5_10
.LBB5_2: # =>This Loop Header: Depth=1
# Child Loop BB5_4 Depth 2
movl $_ZSt4cout, %edi
movl %r15d, %esi
callq _ZNSolsEi
movl $.L.str.7, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
testl %ebx, %ebx
je .LBB5_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB5_2 Depth=1
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_4: # Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
movq (%r14,%r15,8), %rax
movss (%rax,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.8, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r12
cmpq %r12, %rbp
jne .LBB5_4
.LBB5_5: # %._crit_edge
# in Loop: Header=BB5_2 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB5_11
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB5_2 Depth=1
cmpb $0, 56(%r12)
je .LBB5_8
# %bb.7: # in Loop: Header=BB5_2 Depth=1
movzbl 67(%r12), %eax
jmp .LBB5_9
.LBB5_10: # %._crit_edge14
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_11:
.cfi_def_cfa_offset 64
callq _ZSt16__throw_bad_castv
.Lfunc_end5:
.size _Z5printPPfjj, .Lfunc_end5-_Z5printPPfjj
.cfi_endproc
# -- End function
.globl _Z13cpuReciprocalPPf6Params # -- Begin function _Z13cpuReciprocalPPf6Params
.p2align 4, 0x90
.type _Z13cpuReciprocalPPf6Params,@function
_Z13cpuReciprocalPPf6Params: # @_Z13cpuReciprocalPPf6Params
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movslq 68(%rsp), %r14
leaq (,%r14,8), %rdi
testq %r14, %r14
movq $-1, %rbp
cmovsq %rbp, %rdi
callq _Znam
movq %rax, %rbx
movl %r14d, %r15d
movslq 64(%rsp), %r12
movl %r12d, %r13d
testq %r14, %r14
je .LBB6_3
# %bb.1: # %.lr.ph.i
leaq (,%r12,4), %r14
testl %r12d, %r12d
cmovsq %rbp, %r14
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB6_2: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
callq _Znam
movq %rax, (%rbx,%rbp,8)
incq %rbp
cmpq %rbp, %r15
jne .LBB6_2
.LBB6_3: # %_Z10initializePPf6Params.exit
leaq 64(%rsp), %rbp
movq (%rbx), %r14
testq %r13, %r13
je .LBB6_5
# %bb.4: # %.lr.ph.preheader.i
leaq (,%r13,4), %rdx
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
.LBB6_5: # %_Z14initializeDataPfjf.exit
movss 16(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%r14)
cmpl $2, %r15d
jl .LBB6_11
# %bb.6: # %.lr.ph40
decl %r13d
movss 8(%rbp), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss 12(%rbp), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss 20(%rbp), %xmm3 # xmm3 = mem[0],zero,zero,zero
mulss %xmm2, %xmm3
movslq %r13d, %rax
movl $1, %ecx
jmp .LBB6_7
.p2align 4, 0x90
.LBB6_10: # %._crit_edge
# in Loop: Header=BB6_7 Depth=1
movq -8(%rbx,%rcx,8), %rsi
movss (%rsi,%rax,4), %xmm4 # xmm4 = mem[0],zero,zero,zero
addss %xmm3, %xmm4
movss %xmm4, (%rdx,%rax,4)
incq %rcx
cmpq %r15, %rcx
je .LBB6_11
.LBB6_7: # =>This Loop Header: Depth=1
# Child Loop BB6_9 Depth 2
movq (%rbx,%rcx,8), %rdx
movss %xmm0, (%rdx)
cmpl $3, %r12d
jl .LBB6_10
# %bb.8: # %.lr.ph
# in Loop: Header=BB6_7 Depth=1
movq -8(%rbx,%rcx,8), %rsi
movl $1, %edi
.p2align 4, 0x90
.LBB6_9: # Parent Loop BB6_7 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rsi,%rdi,4), %xmm4 # xmm4 = mem[0],zero,zero,zero
movss 4(%rsi,%rdi,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
movaps %xmm4, %xmm6
addss %xmm4, %xmm6
subss %xmm6, %xmm5
addss -4(%rsi,%rdi,4), %xmm5
mulss %xmm2, %xmm5
divss %xmm1, %xmm5
mulss %xmm1, %xmm5
addss %xmm4, %xmm5
movss %xmm5, (%rdx,%rdi,4)
leaq 1(%rdi), %r8
movq %r8, %rdi
cmpq %r8, %r13
jne .LBB6_9
jmp .LBB6_10
.LBB6_11: # %._crit_edge41
movq %rbx, %rax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z13cpuReciprocalPPf6Params, .Lfunc_end6-_Z13cpuReciprocalPPf6Params
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI7_0:
.long 0x3f000000 # float 0.5
.long 0x3dcccccd # float 0.100000001
.long 0x00000000 # float 0
.long 0x40a00000 # float 5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0: # %.lr.ph.i
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $72, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $20, %eax
.p2align 4, 0x90
.LBB7_1: # =>This Inner Loop Header: Depth=1
decq %rax
jne .LBB7_1
# %bb.2: # %_Z10initializePPf6Params.exit
movl $_ZSt4cout, %edi
movl $.L.str.10, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB7_11
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB7_5
# %bb.4:
movzbl 67(%rbx), %eax
jmp .LBB7_6
.LBB7_5:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB7_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movabsq $85899345933, %r14 # imm = 0x140000000D
movq %r14, 48(%rsp)
movaps .LCPI7_0(%rip), %xmm0 # xmm0 = [5.0E-1,1.00000001E-1,0.0E+0,5.0E+0]
movups %xmm0, 56(%rsp)
movq 64(%rsp), %rax
movq %rax, 16(%rsp)
movups 48(%rsp), %xmm0
movups %xmm0, (%rsp)
callq _Z13cpuReciprocalPPf6Params
movq %rax, %rdi
movl $20, %esi
movl $13, %edx
callq _Z5printPPfjj
movl $_ZSt4cout, %edi
movl $.L.str.11, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB7_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i29
cmpb $0, 56(%rbx)
je .LBB7_9
# %bb.8:
movzbl 67(%rbx), %eax
jmp .LBB7_10
.LBB7_9:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB7_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit32
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $52, %edi
callq _Znam
movq %r14, 24(%rsp)
movaps .LCPI7_0(%rip), %xmm0 # xmm0 = [5.0E-1,1.00000001E-1,0.0E+0,5.0E+0]
movups %xmm0, 32(%rsp)
movq 40(%rsp), %rcx
movq %rcx, 16(%rsp)
movups 24(%rsp), %xmm0
movups %xmm0, (%rsp)
movq %rax, %rdi
callq _Z13gpuReciprocalPf6Params
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB7_11:
.cfi_def_cfa_offset 96
callq _ZSt16__throw_bad_castv
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16reciprocalKernelPfS_6Params, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16reciprocalKernelPfS_6Params,@object # @_Z16reciprocalKernelPfS_6Params
.section .rodata,"a",@progbits
.globl _Z16reciprocalKernelPfS_6Params
.p2align 3, 0x0
_Z16reciprocalKernelPfS_6Params:
.quad _Z31__device_stub__reciprocalKernelPfS_6Params
.size _Z16reciprocalKernelPfS_6Params, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/sudoHackIn/CUDA/master/lab.hip"
.size .L.str, 88
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "hipMalloc((void **)&gpuOldData, sizeof(float)*inParams.length)"
.size .L.str.1, 63
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "hipMemcpy(gpuOldData, rc, sizeof(float)*inParams.length, hipMemcpyHostToDevice)"
.size .L.str.2, 80
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipMalloc((void **)&gpuNewData, sizeof(float)*inParams.length)"
.size .L.str.3, 63
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipMemcpy(gpuNewData, data, sizeof(float)*inParams.length, hipMemcpyHostToDevice)"
.size .L.str.4, 82
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipMemcpy(rc, gpuNewData, sizeof(float)*inParams.length, hipMemcpyDeviceToHost)"
.size .L.str.5, 80
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipMemcpy(rc, gpuOldData, sizeof(float)*inParams.length, hipMemcpyDeviceToHost)"
.size .L.str.6, 80
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz ": "
.size .L.str.7, 3
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz " "
.size .L.str.8, 2
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "GPU time = %.3f ms\n"
.size .L.str.9, 20
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "CPU"
.size .L.str.10, 4
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "GPU"
.size .L.str.11, 4
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz " returned "
.size .L.str.12, 11
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "("
.size .L.str.13, 2
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz ") at "
.size .L.str.14, 6
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz ":"
.size .L.str.15, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16reciprocalKernelPfS_6Params"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__reciprocalKernelPfS_6Params
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16reciprocalKernelPfS_6Params
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16reciprocalKernelPfS_6Params
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0050*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0060*/ @!P0 BRA 0x2f0 ; /* 0x0000028000008947 */
/* 0x000fea0003800000 */
/*0070*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000800 */
/*0080*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0090*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fc6000fffe03f */
/*00a0*/ IMAD.WIDE.U32 R4, R0, R9, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc600078e0009 */
/*00b0*/ ISETP.NE.AND P0, PT, R0.reuse, UR4, PT ; /* 0x0000000400007c0c */
/* 0x040fe2000bf05270 */
/*00c0*/ IMAD.WIDE.U32 R2, R0, R9, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fd800078e0009 */
/*00d0*/ @!P0 BRA 0x2a0 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*00e0*/ IADD3 R6, R0.reuse, 0x1, RZ ; /* 0x0000000100067810 */
/* 0x040fe40007ffe0ff */
/*00f0*/ IADD3 R8, R0, -0x1, RZ ; /* 0xffffffff00087810 */
/* 0x000fe40007ffe0ff */
/*0100*/ LDG.E R0, [R4.64] ; /* 0x0000000604007981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE.U32 R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0009 */
/*0120*/ IMAD.WIDE.U32 R8, R8, R9, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fe400078e0009 */
/*0130*/ LDG.E R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ee8000c1e1900 */
/*0140*/ LDG.E R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000f22000c1e1900 */
/*0150*/ MUFU.RCP R10, c[0x0][0x178] ; /* 0x00005e00000a7b08 */
/* 0x000e220000001000 */
/*0160*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff0d7624 */
/* 0x000fe200078e00ff */
/*0170*/ BSSY B0, 0x270 ; /* 0x000000f000007945 */
/* 0x000fe60003800000 */
/*0180*/ FFMA R13, R10, -R13, 1 ; /* 0x3f8000000a0d7423 */
/* 0x001fc8000000080d */
/*0190*/ FFMA R10, R10, R13, R10 ; /* 0x0000000d0a0a7223 */
/* 0x000fe4000000000a */
/*01a0*/ FADD R11, R0, R0 ; /* 0x00000000000b7221 */
/* 0x004fc80000000000 */
/*01b0*/ FADD R11, R6, -R11 ; /* 0x8000000b060b7221 */
/* 0x008fc80000000000 */
/*01c0*/ FADD R11, R11, R8 ; /* 0x000000080b0b7221 */
/* 0x010fc80000000000 */
/*01d0*/ FMUL R11, R11, c[0x0][0x17c] ; /* 0x00005f000b0b7a20 */
/* 0x000fc80000400000 */
/*01e0*/ FCHK P0, R11, c[0x0][0x178] ; /* 0x00005e000b007b02 */
/* 0x000e220000000000 */
/*01f0*/ FFMA R4, R11, R10, RZ ; /* 0x0000000a0b047223 */
/* 0x000fc800000000ff */
/*0200*/ FFMA R5, R4, -c[0x0][0x178], R11 ; /* 0x80005e0004057a23 */
/* 0x000fc8000000000b */
/*0210*/ FFMA R5, R10, R5, R4 ; /* 0x000000050a057223 */
/* 0x000fe20000000004 */
/*0220*/ @!P0 BRA 0x260 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*0230*/ MOV R4, 0x250 ; /* 0x0000025000047802 */
/* 0x000fe40000000f00 */
/*0240*/ CALL.REL.NOINC 0x340 ; /* 0x000000f000007944 */
/* 0x000fea0003c00000 */
/*0250*/ IMAD.MOV.U32 R5, RZ, RZ, R6 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0006 */
/*0260*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0270*/ FFMA R5, R5, c[0x0][0x178], R0 ; /* 0x00005e0005057a23 */
/* 0x000fca0000000000 */
/*0280*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101906 */
/*0290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02a0*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1900 */
/*02b0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff077624 */
/* 0x000fc800078e00ff */
/*02c0*/ FFMA R7, R7, c[0x0][0x17c], R4 ; /* 0x00005f0007077a23 */
/* 0x004fca0000000004 */
/*02d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101906 */
/*02e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02f0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff057624 */
/* 0x000fe400078e00ff */
/*0300*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe400078e00ff */
/*0310*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fca00078e00ff */
/*0320*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101906 */
/*0330*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0340*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff0d7624 */
/* 0x000fe200078e00ff */
/*0350*/ SHF.R.U32.HI R5, RZ, 0x17, R11.reuse ; /* 0x00000017ff057819 */
/* 0x100fe2000001160b */
/*0360*/ BSSY B1, 0x9b0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0370*/ IMAD.MOV.U32 R7, RZ, RZ, R11 ; /* 0x000000ffff077224 */
/* 0x000fe400078e000b */
/*0380*/ SHF.R.U32.HI R6, RZ, 0x17, R13 ; /* 0x00000017ff067819 */
/* 0x000fe2000001160d */
/*0390*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff087624 */
/* 0x000fe200078e00ff */
/*03a0*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe400078ec0ff */
/*03b0*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fc400078ec0ff */
/*03c0*/ IADD3 R10, R5, -0x1, RZ ; /* 0xffffffff050a7810 */
/* 0x000fe40007ffe0ff */
/*03d0*/ IADD3 R12, R6, -0x1, RZ ; /* 0xffffffff060c7810 */
/* 0x000fc80007ffe0ff */
/*03e0*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fc80003f04070 */
/*03f0*/ ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; /* 0x000000fd0a00780c */
/* 0x000fda0000704470 */
/*0400*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*0410*/ @!P0 BRA 0x590 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0420*/ FSETP.GTU.FTZ.AND P1, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fe40003f3c200 */
/*0430*/ FSETP.GTU.FTZ.AND P0, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fc80003f1c200 */
/*0440*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0450*/ @P0 BRA 0x990 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0460*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c807 */
/*0470*/ @!P0 BRA 0x970 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0480*/ FSETP.NEU.FTZ.AND P2, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fe40003f5d200 */
/*0490*/ FSETP.NEU.FTZ.AND P1, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fe40003f3d200 */
/*04a0*/ FSETP.NEU.FTZ.AND P0, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fd60003f1d200 */
/*04b0*/ @!P1 BRA !P2, 0x970 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*04c0*/ LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000784c0ff */
/*04d0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*04e0*/ @P1 BRA 0x950 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*04f0*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*0500*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0510*/ @P0 BRA 0x920 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0520*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f06270 */
/*0530*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*0540*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*0550*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*0560*/ @!P0 FFMA R7, R11, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000b078823 */
/* 0x000fe400000000ff */
/*0570*/ @!P1 FFMA R8, R13, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000d089823 */
/* 0x000fe200000000ff */
/*0580*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*0590*/ LEA R11, R6, 0xc0800000, 0x17 ; /* 0xc0800000060b7811 */
/* 0x000fe200078eb8ff */
/*05a0*/ BSSY B2, 0x910 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*05b0*/ IMAD.IADD R11, R8, 0x1, -R11 ; /* 0x00000001080b7824 */
/* 0x000fe200078e0a0b */
/*05c0*/ IADD3 R8, R5, -0x7f, RZ ; /* 0xffffff8105087810 */
/* 0x000fc60007ffe0ff */
/*05d0*/ MUFU.RCP R10, R11 ; /* 0x0000000b000a7308 */
/* 0x000e220000001000 */
/*05e0*/ FADD.FTZ R12, -R11, -RZ ; /* 0x800000ff0b0c7221 */
/* 0x000fe40000010100 */
/*05f0*/ IMAD R7, R8.reuse, -0x800000, R7 ; /* 0xff80000008077824 */
/* 0x040fe200078e0207 */
/*0600*/ IADD3 R8, R8, 0x7f, -R6 ; /* 0x0000007f08087810 */
/* 0x000fca0007ffe806 */
/*0610*/ IMAD.IADD R8, R8, 0x1, R9 ; /* 0x0000000108087824 */
/* 0x000fe400078e0209 */
/*0620*/ FFMA R5, R10, R12, 1 ; /* 0x3f8000000a057423 */
/* 0x001fc8000000000c */
/*0630*/ FFMA R14, R10, R5, R10 ; /* 0x000000050a0e7223 */
/* 0x000fc8000000000a */
/*0640*/ FFMA R5, R7, R14, RZ ; /* 0x0000000e07057223 */
/* 0x000fc800000000ff */
/*0650*/ FFMA R10, R12, R5, R7 ; /* 0x000000050c0a7223 */
/* 0x000fc80000000007 */
/*0660*/ FFMA R13, R14, R10, R5 ; /* 0x0000000a0e0d7223 */
/* 0x000fc80000000005 */
/*0670*/ FFMA R7, R12, R13, R7 ; /* 0x0000000d0c077223 */
/* 0x000fc80000000007 */
/*0680*/ FFMA R5, R14, R7, R13 ; /* 0x000000070e057223 */
/* 0x000fca000000000d */
/*0690*/ SHF.R.U32.HI R6, RZ, 0x17, R5 ; /* 0x00000017ff067819 */
/* 0x000fc80000011605 */
/*06a0*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fca00078ec0ff */
/*06b0*/ IMAD.IADD R10, R6, 0x1, R8 ; /* 0x00000001060a7824 */
/* 0x000fca00078e0208 */
/*06c0*/ IADD3 R6, R10, -0x1, RZ ; /* 0xffffffff0a067810 */
/* 0x000fc80007ffe0ff */
/*06d0*/ ISETP.GE.U32.AND P0, PT, R6, 0xfe, PT ; /* 0x000000fe0600780c */
/* 0x000fda0003f06070 */
/*06e0*/ @!P0 BRA 0x8f0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*06f0*/ ISETP.GT.AND P0, PT, R10, 0xfe, PT ; /* 0x000000fe0a00780c */
/* 0x000fda0003f04270 */
/*0700*/ @P0 BRA 0x8c0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0710*/ ISETP.GE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fda0003f06270 */
/*0720*/ @P0 BRA 0x900 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0730*/ ISETP.GE.AND P0, PT, R10, -0x18, PT ; /* 0xffffffe80a00780c */
/* 0x000fe40003f06270 */
/*0740*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fd600078ec0ff */
/*0750*/ @!P0 BRA 0x900 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0760*/ FFMA.RZ R6, R14, R7.reuse, R13.reuse ; /* 0x000000070e067223 */
/* 0x180fe2000000c00d */
/*0770*/ IADD3 R9, R10.reuse, 0x20, RZ ; /* 0x000000200a097810 */
/* 0x040fe40007ffe0ff */
/*0780*/ ISETP.NE.AND P2, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f45270 */
/*0790*/ LOP3.LUT R8, R6, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff06087812 */
/* 0x000fe200078ec0ff */
/*07a0*/ FFMA.RP R6, R14, R7.reuse, R13.reuse ; /* 0x000000070e067223 */
/* 0x180fe2000000800d */
/*07b0*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f25270 */
/*07c0*/ FFMA.RM R7, R14, R7, R13 ; /* 0x000000070e077223 */
/* 0x000fe2000000400d */
/*07d0*/ LOP3.LUT R8, R8, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000008087812 */
/* 0x000fe200078efcff */
/*07e0*/ IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0a7224 */
/* 0x000fc600078e0a0a */
/*07f0*/ SHF.L.U32 R9, R8, R9, RZ ; /* 0x0000000908097219 */
/* 0x000fe400000006ff */
/*0800*/ FSETP.NEU.FTZ.AND P0, PT, R6, R7, PT ; /* 0x000000070600720b */
/* 0x000fe40003f1d000 */
/*0810*/ SEL R7, R10, RZ, P2 ; /* 0x000000ff0a077207 */
/* 0x000fe40001000000 */
/*0820*/ ISETP.NE.AND P1, PT, R9, RZ, P1 ; /* 0x000000ff0900720c */
/* 0x000fe40000f25270 */
/*0830*/ SHF.R.U32.HI R7, RZ, R7, R8 ; /* 0x00000007ff077219 */
/* 0x000fe40000011608 */
/*0840*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0850*/ SHF.R.U32.HI R9, RZ, 0x1, R7 ; /* 0x00000001ff097819 */
/* 0x000fe40000011607 */
/*0860*/ SEL R6, RZ, 0x1, !P0 ; /* 0x00000001ff067807 */
/* 0x000fc80004000000 */
/*0870*/ LOP3.LUT R6, R6, 0x1, R9, 0xf8, !PT ; /* 0x0000000106067812 */
/* 0x000fc800078ef809 */
/*0880*/ LOP3.LUT R6, R6, R7, RZ, 0xc0, !PT ; /* 0x0000000706067212 */
/* 0x000fca00078ec0ff */
/*0890*/ IMAD.IADD R6, R9, 0x1, R6 ; /* 0x0000000109067824 */
/* 0x000fca00078e0206 */
/*08a0*/ LOP3.LUT R5, R6, R5, RZ, 0xfc, !PT ; /* 0x0000000506057212 */
/* 0x000fe200078efcff */
/*08b0*/ BRA 0x900 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*08c0*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fc800078ec0ff */
/*08d0*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*08e0*/ BRA 0x900 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*08f0*/ IMAD R5, R8, 0x800000, R5 ; /* 0x0080000008057824 */
/* 0x000fe400078e0205 */
/*0900*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0910*/ BRA 0x9a0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0920*/ LOP3.LUT R5, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008057812 */
/* 0x000fc800078e4807 */
/*0930*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*0940*/ BRA 0x9a0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0950*/ LOP3.LUT R5, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008057812 */
/* 0x000fe200078e4807 */
/*0960*/ BRA 0x9a0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0970*/ MUFU.RSQ R5, -QNAN ; /* 0xffc0000000057908 */
/* 0x000e220000001400 */
/*0980*/ BRA 0x9a0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0990*/ FADD.FTZ R5, R11, c[0x0][0x178] ; /* 0x00005e000b057621 */
/* 0x000fe40000010000 */
/*09a0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*09b0*/ IMAD.MOV.U32 R6, RZ, RZ, R5 ; /* 0x000000ffff067224 */
/* 0x001fe400078e0005 */
/*09c0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*09d0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff62004007950 */
/* 0x000fea0003c3ffff */
/*09e0*/ BRA 0x9e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16reciprocalKernelPfS_6Params
.globl _Z16reciprocalKernelPfS_6Params
.p2align 8
.type _Z16reciprocalKernelPfS_6Params,@function
_Z16reciprocalKernelPfS_6Params:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_mov_b32 s4, exec_lo
v_cmpx_ne_u32_e32 0, v1
s_xor_b32 s8, exec_lo, s4
s_cbranch_execnz .LBB0_3
s_and_not1_saveexec_b32 s4, s8
s_cbranch_execnz .LBB0_8
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_3:
s_clause 0x2
s_load_b32 s10, s[0:1], 0x10
s_load_b64 s[6:7], s[0:1], 0x0
s_load_b32 s9, s[0:1], 0x1c
s_add_u32 s4, s0, 16
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_add_i32 s10, s10, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ne_u32_e32 vcc_lo, s10, v1
s_and_saveexec_b32 s10, vcc_lo
s_xor_b32 s10, exec_lo, s10
s_cbranch_execz .LBB0_5
v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, 1, v1
s_load_b32 s11, s[4:5], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v2, v4
v_lshlrev_b64 v[5:6], 2, v[3:4]
v_add_nc_u32_e32 v3, -1, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v6, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_clause 0x2
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[6:7], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_fmac_f32_e32 v4, -2.0, v5
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v2, v4
v_mul_f32_e32 v2, s9, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v3, null, s11, s11, v2
v_div_scale_f32 v7, vcc_lo, v2, s11, v2
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v3, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v6, v4
v_mul_f32_e32 v6, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v3, v6, v7
v_fmac_f32_e32 v6, v8, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v6, v7
v_div_fmas_f32 v3, v3, v4, v6
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v2, v3, s11, v2
v_fmac_f32_e32 v5, s11, v2
global_store_b32 v[0:1], v5, off
.LBB0_5:
s_and_not1_saveexec_b32 s10, s10
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v2, 0
s_load_b32 s4, s[4:5], 0x14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e64 v2, s9, s4
global_store_b32 v[0:1], v2, off
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s10
s_and_not1_saveexec_b32 s4, s8
s_cbranch_execz .LBB0_2
.LBB0_8:
s_load_b32 s0, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16reciprocalKernelPfS_6Params
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16reciprocalKernelPfS_6Params, .Lfunc_end0-_Z16reciprocalKernelPfS_6Params
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 24
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16reciprocalKernelPfS_6Params
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16reciprocalKernelPfS_6Params.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00177b93_00000000-6_lab.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " returned "
.LC1:
.string "("
.LC2:
.string ") at "
.LC3:
.string ":"
#NO_APP
.text
.type _ZL17CheckCudaErrorAuxPKcjS0_9cudaError, @function
_ZL17CheckCudaErrorAuxPKcjS0_9cudaError:
.LFB3845:
.cfi_startproc
testl %ecx, %ecx
jne .L7
ret
.L7:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movl %esi, %r12d
movl %ecx, %ebx
movq %rdx, %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %r13
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r12d, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3845:
.size _ZL17CheckCudaErrorAuxPKcjS0_9cudaError, .-_ZL17CheckCudaErrorAuxPKcjS0_9cudaError
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3848:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3848:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10initializePPf6Params
.type _Z10initializePPf6Params, @function
_Z10initializePPf6Params:
.LFB3839:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl 36(%rsp), %eax
testl %eax, %eax
je .L10
movq %rdi, %rbx
leal -1(%rax), %eax
leaq 8(%rdi,%rax,8), %r12
movabsq $2305843009213693950, %rbp
.L13:
movslq 32(%rsp), %rdi
cmpq %rdi, %rbp
jb .L12
salq $2, %rdi
call _Znam@PLT
movq %rax, (%rbx)
addq $8, %rbx
cmpq %r12, %rbx
jne .L13
.L10:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
call __cxa_throw_bad_array_new_length@PLT
.cfi_endproc
.LFE3839:
.size _Z10initializePPf6Params, .-_Z10initializePPf6Params
.globl _Z14initializeDataPfjf
.type _Z14initializeDataPfjf, @function
_Z14initializeDataPfjf:
.LFB3841:
.cfi_startproc
endbr64
testl %esi, %esi
je .L16
movq %rdi, %rax
movl %esi, %esi
leaq (%rdi,%rsi,4), %rdx
.L18:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L18
.L16:
ret
.cfi_endproc
.LFE3841:
.size _Z14initializeDataPfjf, .-_Z14initializeDataPfjf
.section .rodata.str1.1
.LC4:
.string ": "
.LC5:
.string " "
.text
.globl _Z5printPPfjj
.type _Z5printPPfjj, @function
_Z5printPPfjj:
.LFB3842:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %esi, 8(%rsp)
movl %edx, 12(%rsp)
testl %esi, %esi
je .L20
movq %rdi, %r12
movl %edx, %r13d
salq $2, %r13
movl $0, %r15d
leaq _ZSt4cout(%rip), %rbp
leaq .LC5(%rip), %r14
jmp .L27
.L31:
call _ZSt16__throw_bad_castv@PLT
.L25:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L26:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %r15d
addq $8, %r12
movl 8(%rsp), %eax
cmpl %eax, %r15d
je .L20
.L27:
movl %r15d, %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $2, %edx
leaq .LC4(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
cmpl $0, 12(%rsp)
je .L22
movl $0, %ebx
.L23:
movq (%r12), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r14, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbx, %r13
jne .L23
.L22:
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L31
cmpb $0, 56(%rbx)
je .L25
movzbl 67(%rbx), %esi
jmp .L26
.L20:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3842:
.size _Z5printPPfjj, .-_Z5printPPfjj
.globl _Z13cpuReciprocalPPf6Params
.type _Z13cpuReciprocalPPf6Params, @function
_Z13cpuReciprocalPPf6Params:
.LFB3843:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $16, %rsp
.cfi_def_cfa_offset 64
movl 64(%rsp), %ebx
movl 68(%rsp), %r13d
movss 72(%rsp), %xmm7
movss %xmm7, 12(%rsp)
movss 76(%rsp), %xmm7
movss %xmm7, 8(%rsp)
movl 80(%rsp), %ebp
movslq %r13d, %rax
movq %rax, %rdi
shrq $60, %rdi
jne .L33
leaq 0(,%rax,8), %rdi
call _Znam@PLT
movq %rax, %r12
subq $32, %rsp
.cfi_def_cfa_offset 96
movdqu 96(%rsp), %xmm7
movups %xmm7, (%rsp)
movq 112(%rsp), %rax
movq %rax, 16(%rsp)
movq %r12, %rdi
call _Z10initializePPf6Params
movq (%r12), %r14
addq $32, %rsp
.cfi_def_cfa_offset 64
pxor %xmm0, %xmm0
movl %ebx, %esi
movq %r14, %rdi
call _Z14initializeDataPfjf
movl %ebp, (%r14)
cmpl $1, %r13d
jle .L32
movss 8(%rsp), %xmm4
mulss 84(%rsp), %xmm4
movslq %ebx, %rax
leaq -4(,%rax,4), %r8
leaq 8(%r12), %rdi
leal -2(%r13), %eax
leaq 16(%r12,%rax,8), %r9
leal -3(%rbx), %eax
leaq 12(,%rax,4), %rsi
.L38:
movq %rdi, %rdx
movq (%rdi), %rax
movl %ebp, (%rax)
cmpl $2, %ebx
jle .L36
movl $8, %eax
.L37:
movq -8(%rdx), %r10
movss -4(%r10,%rax), %xmm2
movq (%rdx), %rcx
movaps %xmm2, %xmm3
addss %xmm2, %xmm3
movss (%r10,%rax), %xmm1
subss %xmm3, %xmm1
movaps %xmm1, %xmm0
addss -8(%r10,%rax), %xmm0
mulss 8(%rsp), %xmm0
movss 12(%rsp), %xmm5
divss %xmm5, %xmm0
mulss %xmm5, %xmm0
addss %xmm2, %xmm0
movss %xmm0, -4(%rcx,%rax)
addq $4, %rax
cmpq %rsi, %rax
jne .L37
.L36:
movq (%rdx), %rax
movq -8(%rdx), %rdx
movaps %xmm4, %xmm0
addss (%rdx,%r8), %xmm0
movss %xmm0, (%rax,%r8)
addq $8, %rdi
cmpq %r9, %rdi
jne .L38
.L32:
movq %r12, %rax
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
call __cxa_throw_bad_array_new_length@PLT
.cfi_endproc
.LFE3843:
.size _Z13cpuReciprocalPPf6Params, .-_Z13cpuReciprocalPPf6Params
.globl _Z45__device_stub__Z16reciprocalKernelPfS_6ParamsPfS_R6Params
.type _Z45__device_stub__Z16reciprocalKernelPfS_6ParamsPfS_R6Params, @function
_Z45__device_stub__Z16reciprocalKernelPfS_6ParamsPfS_R6Params:
.LFB3870:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movq %rdx, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L46
.L42:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L47
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16reciprocalKernelPfS_6Params(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L42
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3870:
.size _Z45__device_stub__Z16reciprocalKernelPfS_6ParamsPfS_R6Params, .-_Z45__device_stub__Z16reciprocalKernelPfS_6ParamsPfS_R6Params
.globl _Z16reciprocalKernelPfS_6Params
.type _Z16reciprocalKernelPfS_6Params, @function
_Z16reciprocalKernelPfS_6Params:
.LFB3871:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq 16(%rsp), %rdx
call _Z45__device_stub__Z16reciprocalKernelPfS_6ParamsPfS_R6Params
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3871:
.size _Z16reciprocalKernelPfS_6Params, .-_Z16reciprocalKernelPfS_6Params
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "cudaMalloc((void **)&gpuOldData, sizeof(float)*inParams.length)"
.align 8
.LC8:
.string "/home/ubuntu/Datasets/stackv2/train-structured/sudoHackIn/CUDA/master/lab.cu"
.align 8
.LC9:
.string "cudaMemcpy(gpuOldData, rc, sizeof(float)*inParams.length, cudaMemcpyHostToDevice)"
.align 8
.LC10:
.string "cudaMalloc((void **)&gpuNewData, sizeof(float)*inParams.length)"
.align 8
.LC11:
.string "cudaMemcpy(gpuNewData, data, sizeof(float)*inParams.length, cudaMemcpyHostToDevice)"
.align 8
.LC12:
.string "cudaMemcpy(rc, gpuNewData, sizeof(float)*inParams.length, cudaMemcpyDeviceToHost)"
.align 8
.LC13:
.string "cudaMemcpy(rc, gpuOldData, sizeof(float)*inParams.length, cudaMemcpyDeviceToHost)"
.section .rodata.str1.1
.LC14:
.string "GPU time = %.3f ms\n"
.text
.globl _Z13gpuReciprocalPf6Params
.type _Z13gpuReciprocalPf6Params, @function
_Z13gpuReciprocalPf6Params:
.LFB3840:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl 192(%rsp), %r15d
movl 196(%rsp), %r12d
movl %r12d, 20(%rsp)
movslq %r15d, %rax
movabsq $2305843009213693950, %rdx
cmpq %rax, %rdx
jb .L51
movq %rdi, %rbp
leaq 0(,%rax,4), %r14
movq %r14, 24(%rsp)
movq %r14, %rdi
call _Znam@PLT
movq %rax, %r13
movq %rax, 8(%rsp)
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %ecx
leaq .LC7(%rip), %rdx
movl $69, %esi
leaq .LC8(%rip), %rbx
movq %rbx, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
movl $1, %ecx
movq %r14, %rdx
movq %r13, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ecx
leaq .LC9(%rip), %rdx
movl $70, %esi
movq %rbx, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
leaq 48(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %ecx
leaq .LC10(%rip), %rdx
movl $71, %esi
movq %rbx, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
movl $1, %ecx
movq %r14, %rdx
movq %rbp, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ecx
leaq .LC11(%rip), %rdx
movl $72, %esi
movq %rbx, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
addq %r13, %r14
movl $0, %r13d
movl $0x00000000, 16(%rsp)
leaq _ZSt4cout(%rip), %rbp
testl %r12d, %r12d
jg .L65
.L53:
pxor %xmm0, %xmm0
cvtss2sd 16(%rsp), %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L72
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
movq 120(%rsp), %rax
subq %fs:40, %rax
je .L54
call __stack_chk_fail@PLT
.L54:
call __cxa_throw_bad_array_new_length@PLT
.L56:
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq 24(%rsp), %rdx
movq 48(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ecx
leaq .LC12(%rip), %rdx
movl $83, %esi
leaq .LC8(%rip), %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
.L57:
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
movl %r13d, %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $2, %edx
leaq .LC4(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
testl %r15d, %r15d
jle .L59
movq 8(%rsp), %rbx
leaq .LC5(%rip), %r12
.L60:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r14, %rbx
jne .L60
.L59:
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L73
cmpb $0, 56(%rbx)
je .L63
movzbl 67(%rbx), %esi
.L64:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq 96(%rsp), %rdi
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 16(%rsp), %xmm1
addss 96(%rsp), %xmm1
movss %xmm1, 16(%rsp)
addl $1, %r13d
cmpl %r13d, 20(%rsp)
je .L53
.L65:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
testb $1, %r13b
jne .L55
movl $26, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movl $1, %ecx
movq 72(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L56
movl %r15d, 192(%rsp)
movl 20(%rsp), %eax
movl %eax, 196(%rsp)
movdqu 192(%rsp), %xmm2
movaps %xmm2, 96(%rsp)
movq 208(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z45__device_stub__Z16reciprocalKernelPfS_6ParamsPfS_R6Params
jmp .L56
.L55:
movl $26, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movl $1, %ecx
movq 72(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L74
.L58:
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq 24(%rsp), %rdx
movq 40(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ecx
leaq .LC13(%rip), %rdx
movl $91, %esi
leaq .LC8(%rip), %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
jmp .L57
.L74:
movl %r15d, 192(%rsp)
movl 20(%rsp), %eax
movl %eax, 196(%rsp)
movdqu 192(%rsp), %xmm3
movaps %xmm3, 96(%rsp)
movq 208(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rdx
movq 40(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z45__device_stub__Z16reciprocalKernelPfS_6ParamsPfS_R6Params
jmp .L58
.L73:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L75
call _ZSt16__throw_bad_castv@PLT
.L75:
call __stack_chk_fail@PLT
.L63:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L64
.L72:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3840:
.size _Z13gpuReciprocalPf6Params, .-_Z13gpuReciprocalPf6Params
.section .rodata.str1.1
.LC18:
.string "CPU"
.LC19:
.string "GPU"
.text
.globl main
.type main, @function
main:
.LFB3844:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movl $0x3f000000, 8(%rsp)
movl $0x3dcccccd, 12(%rsp)
movl $0x00000000, 16(%rsp)
movl $0x40a00000, 20(%rsp)
movl $160, %edi
call _Znam@PLT
movq %rax, %rbx
movl $13, (%rsp)
movl $20, 4(%rsp)
subq $32, %rsp
.cfi_def_cfa_offset 96
movdqa 32(%rsp), %xmm0
movups %xmm0, (%rsp)
movq 48(%rsp), %rax
movq %rax, 16(%rsp)
movq %rbx, %rdi
call _Z10initializePPf6Params
addq $32, %rsp
.cfi_def_cfa_offset 64
leaq .LC18(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
subq $32, %rsp
.cfi_def_cfa_offset 96
movdqa 32(%rsp), %xmm1
movups %xmm1, (%rsp)
movq 48(%rsp), %rax
movq %rax, 16(%rsp)
movq %rbx, %rdi
call _Z13cpuReciprocalPPf6Params
movq %rax, %rdi
addq $32, %rsp
.cfi_def_cfa_offset 64
movl $13, %edx
movl $20, %esi
call _Z5printPPfjj
leaq .LC19(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $52, %edi
call _Znam@PLT
movq %rax, %rdi
subq $32, %rsp
.cfi_def_cfa_offset 96
movdqa 32(%rsp), %xmm2
movups %xmm2, (%rsp)
movq 48(%rsp), %rax
movq %rax, 16(%rsp)
call _Z13gpuReciprocalPf6Params
movl $0, %eax
addq $72, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3844:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC20:
.string "_Z16reciprocalKernelPfS_6Params"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3873:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z16reciprocalKernelPfS_6Params(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3873:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "lab.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z10initializePPf6Params # -- Begin function _Z10initializePPf6Params
.p2align 4, 0x90
.type _Z10initializePPf6Params,@function
_Z10initializePPf6Params: # @_Z10initializePPf6Params
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl 52(%rsp), %r15d
testq %r15, %r15
je .LBB0_3
# %bb.1: # %.lr.ph
movq %rdi, %rbx
leaq 48(%rsp), %rax
movslq (%rax), %rax
leaq (,%rax,4), %rcx
testq %rax, %rax
movq $-1, %r14
cmovnsq %rcx, %r14
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_2: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
callq _Znam
movq %rax, (%rbx,%r12,8)
incq %r12
cmpq %r12, %r15
jne .LBB0_2
.LBB0_3: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z10initializePPf6Params, .Lfunc_end0-_Z10initializePPf6Params
.cfi_endproc
# -- End function
.globl _Z31__device_stub__reciprocalKernelPfS_6Params # -- Begin function _Z31__device_stub__reciprocalKernelPfS_6Params
.p2align 4, 0x90
.type _Z31__device_stub__reciprocalKernelPfS_6Params,@function
_Z31__device_stub__reciprocalKernelPfS_6Params: # @_Z31__device_stub__reciprocalKernelPfS_6Params
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 96(%rsp), %rax
movq %rax, 80(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16reciprocalKernelPfS_6Params, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z31__device_stub__reciprocalKernelPfS_6Params, .Lfunc_end1-_Z31__device_stub__reciprocalKernelPfS_6Params
.cfi_endproc
# -- End function
.globl _Z13gpuReciprocalPf6Params # -- Begin function _Z13gpuReciprocalPf6Params
.p2align 4, 0x90
.type _Z13gpuReciprocalPf6Params,@function
_Z13gpuReciprocalPf6Params: # @_Z13gpuReciprocalPf6Params
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %r15
movslq 224(%rsp), %rbx
leaq (,%rbx,4), %r12
testq %rbx, %rbx
movq $-1, %rdi
cmovnsq %r12, %rdi
callq _Znam
movq %rax, %r14
leaq 136(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movl $.L.str.1, %esi
movl $71, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movq 16(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl $.L.str.2, %esi
movl $72, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movl $.L.str.3, %esi
movl $73, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movq 8(%rsp), %rdi
movq %r15, %rsi
movq %r12, 128(%rsp) # 8-byte Spill
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl $.L.str.4, %esi
movl $74, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movl 228(%rsp), %ebp
testl %ebp, %ebp
jle .LBB2_1
# %bb.4: # %.lr.ph42
movl %ebx, %ebx
xorl %r15d, %r15d
xorps %xmm0, %xmm0
movabsq $4294967297, %rax # imm = 0x100000001
leaq 25(%rax), %r13
jmp .LBB2_5
.p2align 4, 0x90
.LBB2_18: # in Loop: Header=BB2_5 Depth=1
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_19: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB2_5 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 136(%rsp), %rsi
movq (%rsp), %rdx
leaq 96(%rsp), %rdi
callq hipEventElapsedTime
movss 92(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
addss 96(%rsp), %xmm0
incl %r15d
cmpl %ebp, %r15d
je .LBB2_2
.LBB2_5: # =>This Loop Header: Depth=1
# Child Loop BB2_14 Depth 2
movss %xmm0, 92(%rsp) # 4-byte Spill
movq 136(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testb $1, %r15b
jne .LBB2_9
# %bb.6: # in Loop: Header=BB2_5 Depth=1
testl %eax, %eax
jne .LBB2_8
# %bb.7: # in Loop: Header=BB2_5 Depth=1
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
leaq 224(%rsp), %rsi
movq 16(%rsi), %rdx
movq %rdx, 160(%rsp)
movups (%rsi), %xmm0
movaps %xmm0, 144(%rsp)
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 144(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z16reciprocalKernelPfS_6Params, %edi
leaq 96(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8: # in Loop: Header=BB2_5 Depth=1
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rsi
movq %r14, %rdi
movq 128(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movl $.L.str.5, %esi
movl $85, %edi
jmp .LBB2_12
.p2align 4, 0x90
.LBB2_9: # in Loop: Header=BB2_5 Depth=1
testl %eax, %eax
jne .LBB2_11
# %bb.10: # in Loop: Header=BB2_5 Depth=1
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
leaq 224(%rsp), %rsi
movq 16(%rsi), %rdx
movq %rdx, 160(%rsp)
movups (%rsi), %xmm0
movaps %xmm0, 144(%rsp)
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 144(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z16reciprocalKernelPfS_6Params, %edi
leaq 96(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_11: # in Loop: Header=BB2_5 Depth=1
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rsi
movq %r14, %rdi
movq 128(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movl $.L.str.6, %esi
movl $93, %edi
.LBB2_12: # in Loop: Header=BB2_5 Depth=1
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movq (%rsp), %rdi
callq hipEventSynchronize
movl $_ZSt4cout, %edi
movl %r15d, %esi
callq _ZNSolsEi
movl $.L.str.7, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
testl %ebx, %ebx
jle .LBB2_15
# %bb.13: # %.lr.ph.preheader
# in Loop: Header=BB2_5 Depth=1
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_14: # %.lr.ph
# Parent Loop BB2_5 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.8, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r12
cmpq %r12, %rbx
jne .LBB2_14
.LBB2_15: # %._crit_edge
# in Loop: Header=BB2_5 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB2_20
# %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB2_5 Depth=1
cmpb $0, 56(%r12)
je .LBB2_18
# %bb.17: # in Loop: Header=BB2_5 Depth=1
movzbl 67(%r12), %eax
jmp .LBB2_19
.LBB2_2: # %._crit_edge43.loopexit
cvtss2sd %xmm0, %xmm0
jmp .LBB2_3
.LBB2_1:
xorps %xmm0, %xmm0
.LBB2_3: # %._crit_edge43
movl $.L.str.9, %edi
movb $1, %al
callq printf
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_20:
.cfi_def_cfa_offset 224
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size _Z13gpuReciprocalPf6Params, .Lfunc_end2-_Z13gpuReciprocalPf6Params
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
.type _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t,@function
_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t: # @_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
.cfi_startproc
# %bb.0:
testl %edx, %edx
jne .LBB3_2
# %bb.1:
retq
.LBB3_2:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %edi, %ebx
movl $_ZSt4cerr, %edi
movl %edx, %ebp
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.12, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebp, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.13, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebp, %esi
callq _ZNSolsEi
movl $.L.str.14, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.15, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebx, %esi
callq _ZNSolsEj
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end3:
.size _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t, .Lfunc_end3-_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
.cfi_endproc
# -- End function
.globl _Z14initializeDataPfjf # -- Begin function _Z14initializeDataPfjf
.p2align 4, 0x90
.type _Z14initializeDataPfjf,@function
_Z14initializeDataPfjf: # @_Z14initializeDataPfjf
.cfi_startproc
# %bb.0:
testl %esi, %esi
je .LBB4_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss %xmm0, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB4_2
.LBB4_3: # %._crit_edge
retq
.Lfunc_end4:
.size _Z14initializeDataPfjf, .Lfunc_end4-_Z14initializeDataPfjf
.cfi_endproc
# -- End function
.globl _Z5printPPfjj # -- Begin function _Z5printPPfjj
.p2align 4, 0x90
.type _Z5printPPfjj,@function
_Z5printPPfjj: # @_Z5printPPfjj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
testl %esi, %esi
je .LBB5_10
# %bb.1: # %.lr.ph13
movl %edx, %ebx
movq %rdi, %r14
movl %esi, %r13d
movl %edx, %ebp
xorl %r15d, %r15d
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_8: # in Loop: Header=BB5_2 Depth=1
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB5_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB5_2 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r15
cmpq %r13, %r15
je .LBB5_10
.LBB5_2: # =>This Loop Header: Depth=1
# Child Loop BB5_4 Depth 2
movl $_ZSt4cout, %edi
movl %r15d, %esi
callq _ZNSolsEi
movl $.L.str.7, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
testl %ebx, %ebx
je .LBB5_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB5_2 Depth=1
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_4: # Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
movq (%r14,%r15,8), %rax
movss (%rax,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.8, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r12
cmpq %r12, %rbp
jne .LBB5_4
.LBB5_5: # %._crit_edge
# in Loop: Header=BB5_2 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB5_11
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB5_2 Depth=1
cmpb $0, 56(%r12)
je .LBB5_8
# %bb.7: # in Loop: Header=BB5_2 Depth=1
movzbl 67(%r12), %eax
jmp .LBB5_9
.LBB5_10: # %._crit_edge14
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_11:
.cfi_def_cfa_offset 64
callq _ZSt16__throw_bad_castv
.Lfunc_end5:
.size _Z5printPPfjj, .Lfunc_end5-_Z5printPPfjj
.cfi_endproc
# -- End function
.globl _Z13cpuReciprocalPPf6Params # -- Begin function _Z13cpuReciprocalPPf6Params
.p2align 4, 0x90
.type _Z13cpuReciprocalPPf6Params,@function
_Z13cpuReciprocalPPf6Params: # @_Z13cpuReciprocalPPf6Params
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movslq 68(%rsp), %r14
leaq (,%r14,8), %rdi
testq %r14, %r14
movq $-1, %rbp
cmovsq %rbp, %rdi
callq _Znam
movq %rax, %rbx
movl %r14d, %r15d
movslq 64(%rsp), %r12
movl %r12d, %r13d
testq %r14, %r14
je .LBB6_3
# %bb.1: # %.lr.ph.i
leaq (,%r12,4), %r14
testl %r12d, %r12d
cmovsq %rbp, %r14
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB6_2: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
callq _Znam
movq %rax, (%rbx,%rbp,8)
incq %rbp
cmpq %rbp, %r15
jne .LBB6_2
.LBB6_3: # %_Z10initializePPf6Params.exit
leaq 64(%rsp), %rbp
movq (%rbx), %r14
testq %r13, %r13
je .LBB6_5
# %bb.4: # %.lr.ph.preheader.i
leaq (,%r13,4), %rdx
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
.LBB6_5: # %_Z14initializeDataPfjf.exit
movss 16(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%r14)
cmpl $2, %r15d
jl .LBB6_11
# %bb.6: # %.lr.ph40
decl %r13d
movss 8(%rbp), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss 12(%rbp), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss 20(%rbp), %xmm3 # xmm3 = mem[0],zero,zero,zero
mulss %xmm2, %xmm3
movslq %r13d, %rax
movl $1, %ecx
jmp .LBB6_7
.p2align 4, 0x90
.LBB6_10: # %._crit_edge
# in Loop: Header=BB6_7 Depth=1
movq -8(%rbx,%rcx,8), %rsi
movss (%rsi,%rax,4), %xmm4 # xmm4 = mem[0],zero,zero,zero
addss %xmm3, %xmm4
movss %xmm4, (%rdx,%rax,4)
incq %rcx
cmpq %r15, %rcx
je .LBB6_11
.LBB6_7: # =>This Loop Header: Depth=1
# Child Loop BB6_9 Depth 2
movq (%rbx,%rcx,8), %rdx
movss %xmm0, (%rdx)
cmpl $3, %r12d
jl .LBB6_10
# %bb.8: # %.lr.ph
# in Loop: Header=BB6_7 Depth=1
movq -8(%rbx,%rcx,8), %rsi
movl $1, %edi
.p2align 4, 0x90
.LBB6_9: # Parent Loop BB6_7 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rsi,%rdi,4), %xmm4 # xmm4 = mem[0],zero,zero,zero
movss 4(%rsi,%rdi,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
movaps %xmm4, %xmm6
addss %xmm4, %xmm6
subss %xmm6, %xmm5
addss -4(%rsi,%rdi,4), %xmm5
mulss %xmm2, %xmm5
divss %xmm1, %xmm5
mulss %xmm1, %xmm5
addss %xmm4, %xmm5
movss %xmm5, (%rdx,%rdi,4)
leaq 1(%rdi), %r8
movq %r8, %rdi
cmpq %r8, %r13
jne .LBB6_9
jmp .LBB6_10
.LBB6_11: # %._crit_edge41
movq %rbx, %rax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z13cpuReciprocalPPf6Params, .Lfunc_end6-_Z13cpuReciprocalPPf6Params
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI7_0:
.long 0x3f000000 # float 0.5
.long 0x3dcccccd # float 0.100000001
.long 0x00000000 # float 0
.long 0x40a00000 # float 5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0: # %.lr.ph.i
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $72, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $20, %eax
.p2align 4, 0x90
.LBB7_1: # =>This Inner Loop Header: Depth=1
decq %rax
jne .LBB7_1
# %bb.2: # %_Z10initializePPf6Params.exit
movl $_ZSt4cout, %edi
movl $.L.str.10, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB7_11
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB7_5
# %bb.4:
movzbl 67(%rbx), %eax
jmp .LBB7_6
.LBB7_5:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB7_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movabsq $85899345933, %r14 # imm = 0x140000000D
movq %r14, 48(%rsp)
movaps .LCPI7_0(%rip), %xmm0 # xmm0 = [5.0E-1,1.00000001E-1,0.0E+0,5.0E+0]
movups %xmm0, 56(%rsp)
movq 64(%rsp), %rax
movq %rax, 16(%rsp)
movups 48(%rsp), %xmm0
movups %xmm0, (%rsp)
callq _Z13cpuReciprocalPPf6Params
movq %rax, %rdi
movl $20, %esi
movl $13, %edx
callq _Z5printPPfjj
movl $_ZSt4cout, %edi
movl $.L.str.11, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB7_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i29
cmpb $0, 56(%rbx)
je .LBB7_9
# %bb.8:
movzbl 67(%rbx), %eax
jmp .LBB7_10
.LBB7_9:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB7_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit32
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $52, %edi
callq _Znam
movq %r14, 24(%rsp)
movaps .LCPI7_0(%rip), %xmm0 # xmm0 = [5.0E-1,1.00000001E-1,0.0E+0,5.0E+0]
movups %xmm0, 32(%rsp)
movq 40(%rsp), %rcx
movq %rcx, 16(%rsp)
movups 24(%rsp), %xmm0
movups %xmm0, (%rsp)
movq %rax, %rdi
callq _Z13gpuReciprocalPf6Params
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB7_11:
.cfi_def_cfa_offset 96
callq _ZSt16__throw_bad_castv
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16reciprocalKernelPfS_6Params, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16reciprocalKernelPfS_6Params,@object # @_Z16reciprocalKernelPfS_6Params
.section .rodata,"a",@progbits
.globl _Z16reciprocalKernelPfS_6Params
.p2align 3, 0x0
_Z16reciprocalKernelPfS_6Params:
.quad _Z31__device_stub__reciprocalKernelPfS_6Params
.size _Z16reciprocalKernelPfS_6Params, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/sudoHackIn/CUDA/master/lab.hip"
.size .L.str, 88
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "hipMalloc((void **)&gpuOldData, sizeof(float)*inParams.length)"
.size .L.str.1, 63
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "hipMemcpy(gpuOldData, rc, sizeof(float)*inParams.length, hipMemcpyHostToDevice)"
.size .L.str.2, 80
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipMalloc((void **)&gpuNewData, sizeof(float)*inParams.length)"
.size .L.str.3, 63
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipMemcpy(gpuNewData, data, sizeof(float)*inParams.length, hipMemcpyHostToDevice)"
.size .L.str.4, 82
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipMemcpy(rc, gpuNewData, sizeof(float)*inParams.length, hipMemcpyDeviceToHost)"
.size .L.str.5, 80
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipMemcpy(rc, gpuOldData, sizeof(float)*inParams.length, hipMemcpyDeviceToHost)"
.size .L.str.6, 80
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz ": "
.size .L.str.7, 3
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz " "
.size .L.str.8, 2
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "GPU time = %.3f ms\n"
.size .L.str.9, 20
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "CPU"
.size .L.str.10, 4
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "GPU"
.size .L.str.11, 4
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz " returned "
.size .L.str.12, 11
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "("
.size .L.str.13, 2
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz ") at "
.size .L.str.14, 6
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz ":"
.size .L.str.15, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16reciprocalKernelPfS_6Params"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__reciprocalKernelPfS_6Params
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16reciprocalKernelPfS_6Params
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*************************************************************************************************************
* FILE: p2.cu
*
* AUTHOR: attiffan Aurora T. Tiffany-Davis
*
* DESCRIPTION: A CUDA program that calculates an approximate value for PI using Monte Carlo methods.
*
* TO RUN: srun -N1 -n1 -p opteron --pty /bin/bash
* make -f p2.Makefile
* ./p2 [number of iterations for Monte Carlo simulation]
*************************************************************************************************************/
// INCLUDES
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#include <curand.h>
#include <curand_kernel.h>
// DEFINES
#define N_NUM_BLOCKS 64
#define N_NUM_THREADS_PER_BLOCK 512
/*************************************************************************************************************
* FUNCTION: iterateMonteCarlo
*
* DESCRIPTION: GPU kernel that iterates through part of a Monte Carlo simulation for approximating PI.
*
* ARGUMENTS: nThreads - Number of threads which are participating in simulation
* nIterations - Total number of iterations to run
* aCounts - Pointer to an array of "raindrop" counts
*
* AUTHOR: attiffan Aurora T. Tiffany-Davis
*************************************************************************************************************/
__global__ void iterateMonteCarlo (int nThreads, int nIterations, int *aCounts) {
// Declare variables
int i;
int nThreadID;
int nCount;
double nX;
double nY;
double nZ;
curandState state;
// Initialize variables
nThreadID = threadIdx.x + blockIdx.x * blockDim.x;
nCount = 0;
// If this thread is meant to participate, proceed
if (nThreadID < nThreads) {
// Initialize random number generator
curand_init(clock64(), nThreadID, 0, &state);
// Iterate through part of a Monte Carlo simulation, counting how many "raindrops" land in circle
for (i = nThreadID; i < nIterations; i += nThreads) {
nX = (double) curand_uniform(&state);
nY = (double) curand_uniform(&state);
nZ = (nX * nX) + (nY * nY);
if (nZ <= 1) {
nCount++;
}
}
// Put your count in the counts array by thread index
aCounts[nThreadID] = nCount;
}
}
/*************************************************************************************************************
* FUNCTION: main
*
* DESCRIPTION: Calculate an approximate value for PI using Monte Carlo methods.
*
* ARGUMENTS: 0 - (as always, name of program)
* 1 - Number of iterations to run
*
* AUTHOR: attiffan Aurora T. Tiffany-Davis
*************************************************************************************************************/
int main(int argc, char** argv) {
// Declare variables (CPU)
double nPI;
int i;
int nTotalCount;
int nTotalThreads = N_NUM_BLOCKS * N_NUM_THREADS_PER_BLOCK;
int nIterations;
int aCounts_h[nTotalThreads];
// Declare variables (GPU)
int *aCounts_d;
// Initialize variables
nIterations = atoi(argv[1]);
nTotalCount = 0;
// Allocate memory (GPU)
cudaMalloc((void **) &aCounts_d, sizeof(int) * nTotalThreads);
// Run Monte Carlo simulation on GPU
iterateMonteCarlo <<< N_NUM_BLOCKS, N_NUM_THREADS_PER_BLOCK >>> (nTotalThreads, nIterations, aCounts_d);
// Copy back from GPU to CPU
cudaMemcpy(&aCounts_h, aCounts_d, sizeof(int) * nTotalThreads, cudaMemcpyDeviceToHost);
// Get total count of "raindrops" that fell within circle
for (i = 0; i < nTotalThreads; i++) {
nTotalCount += aCounts_h[i];
}
// Calculate approximate value of pi based on relationship between square and inscribed circle
nPI = (double) nTotalCount / nIterations * 4;
// Print results
printf("# of trials= %d, estimate of pi is %.16f \n", nIterations, nPI);
// Free memory (GPU)
cudaFree(aCounts_d);
} | .file "tmpxft_0014d6b2_00000000-6_p2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2274:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2274:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z17iterateMonteCarloiiPiiiPi
.type _Z39__device_stub__Z17iterateMonteCarloiiPiiiPi, @function
_Z39__device_stub__Z17iterateMonteCarloiiPiiiPi:
.LFB2296:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17iterateMonteCarloiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2296:
.size _Z39__device_stub__Z17iterateMonteCarloiiPiiiPi, .-_Z39__device_stub__Z17iterateMonteCarloiiPiiiPi
.globl _Z17iterateMonteCarloiiPi
.type _Z17iterateMonteCarloiiPi, @function
_Z17iterateMonteCarloiiPi:
.LFB2297:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z17iterateMonteCarloiiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2297:
.size _Z17iterateMonteCarloiiPi, .-_Z17iterateMonteCarloiiPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "# of trials= %d, estimate of pi is %.16f \n"
.text
.globl main
.type main, @function
main:
.LFB2271:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r13
pushq %r12
pushq %rbx
subq $56, %rsp
.cfi_offset 13, -24
.cfi_offset 12, -32
.cfi_offset 3, -40
movq %fs:40, %rax
movq %rax, -40(%rbp)
xorl %eax, %eax
leaq -131072(%rsp), %rax
.L12:
cmpq %rax, %rsp
je .L13
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L12
.L13:
movq %rsp, %r13
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %r12d
leaq -72(%rbp), %rdi
movl $131072, %esi
call cudaMalloc@PLT
movl $512, -52(%rbp)
movl $1, -48(%rbp)
movl $1, -44(%rbp)
movl $64, -64(%rbp)
movl $1, -60(%rbp)
movl $1, -56(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -52(%rbp), %rdx
movl $1, %ecx
movq -64(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L15
movq -72(%rbp), %rdx
movl %ebx, %esi
movl $32768, %edi
call _Z39__device_stub__Z17iterateMonteCarloiiPiiiPi
.L15:
movl $2, %ecx
movl $131072, %edx
movq -72(%rbp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %r13, %rax
leaq 131072(%r13), %rsi
movl $0, %ecx
.L16:
addl (%rax), %ecx
addq $4, %rax
cmpq %rsi, %rax
jne .L16
pxor %xmm0, %xmm0
cvtsi2sdl %ecx, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl %ebx, %xmm1
divsd %xmm1, %xmm0
mulsd .LC0(%rip), %xmm0
movl %r12d, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq -72(%rbp), %rdi
call cudaFree@PLT
movq -40(%rbp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
leaq -24(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L20:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2271:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z17iterateMonteCarloiiPi"
.LC3:
.string "precalc_xorwow_matrix"
.LC4:
.string "precalc_xorwow_offset_matrix"
.LC5:
.string "mrg32k3aM1"
.LC6:
.string "mrg32k3aM2"
.LC7:
.string "mrg32k3aM1SubSeq"
.LC8:
.string "mrg32k3aM2SubSeq"
.LC9:
.string "mrg32k3aM1Seq"
.LC10:
.string "mrg32k3aM2Seq"
.LC11:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2299:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z17iterateMonteCarloiiPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2299:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1074790400
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*************************************************************************************************************
* FILE: p2.cu
*
* AUTHOR: attiffan Aurora T. Tiffany-Davis
*
* DESCRIPTION: A CUDA program that calculates an approximate value for PI using Monte Carlo methods.
*
* TO RUN: srun -N1 -n1 -p opteron --pty /bin/bash
* make -f p2.Makefile
* ./p2 [number of iterations for Monte Carlo simulation]
*************************************************************************************************************/
// INCLUDES
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#include <curand.h>
#include <curand_kernel.h>
// DEFINES
#define N_NUM_BLOCKS 64
#define N_NUM_THREADS_PER_BLOCK 512
/*************************************************************************************************************
* FUNCTION: iterateMonteCarlo
*
* DESCRIPTION: GPU kernel that iterates through part of a Monte Carlo simulation for approximating PI.
*
* ARGUMENTS: nThreads - Number of threads which are participating in simulation
* nIterations - Total number of iterations to run
* aCounts - Pointer to an array of "raindrop" counts
*
* AUTHOR: attiffan Aurora T. Tiffany-Davis
*************************************************************************************************************/
__global__ void iterateMonteCarlo (int nThreads, int nIterations, int *aCounts) {
// Declare variables
int i;
int nThreadID;
int nCount;
double nX;
double nY;
double nZ;
curandState state;
// Initialize variables
nThreadID = threadIdx.x + blockIdx.x * blockDim.x;
nCount = 0;
// If this thread is meant to participate, proceed
if (nThreadID < nThreads) {
// Initialize random number generator
curand_init(clock64(), nThreadID, 0, &state);
// Iterate through part of a Monte Carlo simulation, counting how many "raindrops" land in circle
for (i = nThreadID; i < nIterations; i += nThreads) {
nX = (double) curand_uniform(&state);
nY = (double) curand_uniform(&state);
nZ = (nX * nX) + (nY * nY);
if (nZ <= 1) {
nCount++;
}
}
// Put your count in the counts array by thread index
aCounts[nThreadID] = nCount;
}
}
/*************************************************************************************************************
* FUNCTION: main
*
* DESCRIPTION: Calculate an approximate value for PI using Monte Carlo methods.
*
* ARGUMENTS: 0 - (as always, name of program)
* 1 - Number of iterations to run
*
* AUTHOR: attiffan Aurora T. Tiffany-Davis
*************************************************************************************************************/
int main(int argc, char** argv) {
// Declare variables (CPU)
double nPI;
int i;
int nTotalCount;
int nTotalThreads = N_NUM_BLOCKS * N_NUM_THREADS_PER_BLOCK;
int nIterations;
int aCounts_h[nTotalThreads];
// Declare variables (GPU)
int *aCounts_d;
// Initialize variables
nIterations = atoi(argv[1]);
nTotalCount = 0;
// Allocate memory (GPU)
cudaMalloc((void **) &aCounts_d, sizeof(int) * nTotalThreads);
// Run Monte Carlo simulation on GPU
iterateMonteCarlo <<< N_NUM_BLOCKS, N_NUM_THREADS_PER_BLOCK >>> (nTotalThreads, nIterations, aCounts_d);
// Copy back from GPU to CPU
cudaMemcpy(&aCounts_h, aCounts_d, sizeof(int) * nTotalThreads, cudaMemcpyDeviceToHost);
// Get total count of "raindrops" that fell within circle
for (i = 0; i < nTotalThreads; i++) {
nTotalCount += aCounts_h[i];
}
// Calculate approximate value of pi based on relationship between square and inscribed circle
nPI = (double) nTotalCount / nIterations * 4;
// Print results
printf("# of trials= %d, estimate of pi is %.16f \n", nIterations, nPI);
// Free memory (GPU)
cudaFree(aCounts_d);
} | /*************************************************************************************************************
* FILE: p2.cu
*
* AUTHOR: attiffan Aurora T. Tiffany-Davis
*
* DESCRIPTION: A CUDA program that calculates an approximate value for PI using Monte Carlo methods.
*
* TO RUN: srun -N1 -n1 -p opteron --pty /bin/bash
* make -f p2.Makefile
* ./p2 [number of iterations for Monte Carlo simulation]
*************************************************************************************************************/
// INCLUDES
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
// DEFINES
#define N_NUM_BLOCKS 64
#define N_NUM_THREADS_PER_BLOCK 512
/*************************************************************************************************************
* FUNCTION: iterateMonteCarlo
*
* DESCRIPTION: GPU kernel that iterates through part of a Monte Carlo simulation for approximating PI.
*
* ARGUMENTS: nThreads - Number of threads which are participating in simulation
* nIterations - Total number of iterations to run
* aCounts - Pointer to an array of "raindrop" counts
*
* AUTHOR: attiffan Aurora T. Tiffany-Davis
*************************************************************************************************************/
__global__ void iterateMonteCarlo (int nThreads, int nIterations, int *aCounts) {
// Declare variables
int i;
int nThreadID;
int nCount;
double nX;
double nY;
double nZ;
hiprandState state;
// Initialize variables
nThreadID = threadIdx.x + blockIdx.x * blockDim.x;
nCount = 0;
// If this thread is meant to participate, proceed
if (nThreadID < nThreads) {
// Initialize random number generator
hiprand_init(clock64(), nThreadID, 0, &state);
// Iterate through part of a Monte Carlo simulation, counting how many "raindrops" land in circle
for (i = nThreadID; i < nIterations; i += nThreads) {
nX = (double) hiprand_uniform(&state);
nY = (double) hiprand_uniform(&state);
nZ = (nX * nX) + (nY * nY);
if (nZ <= 1) {
nCount++;
}
}
// Put your count in the counts array by thread index
aCounts[nThreadID] = nCount;
}
}
/*************************************************************************************************************
* FUNCTION: main
*
* DESCRIPTION: Calculate an approximate value for PI using Monte Carlo methods.
*
* ARGUMENTS: 0 - (as always, name of program)
* 1 - Number of iterations to run
*
* AUTHOR: attiffan Aurora T. Tiffany-Davis
*************************************************************************************************************/
int main(int argc, char** argv) {
// Declare variables (CPU)
double nPI;
int i;
int nTotalCount;
int nTotalThreads = N_NUM_BLOCKS * N_NUM_THREADS_PER_BLOCK;
int nIterations;
int aCounts_h[nTotalThreads];
// Declare variables (GPU)
int *aCounts_d;
// Initialize variables
nIterations = atoi(argv[1]);
nTotalCount = 0;
// Allocate memory (GPU)
hipMalloc((void **) &aCounts_d, sizeof(int) * nTotalThreads);
// Run Monte Carlo simulation on GPU
iterateMonteCarlo <<< N_NUM_BLOCKS, N_NUM_THREADS_PER_BLOCK >>> (nTotalThreads, nIterations, aCounts_d);
// Copy back from GPU to CPU
hipMemcpy(&aCounts_h, aCounts_d, sizeof(int) * nTotalThreads, hipMemcpyDeviceToHost);
// Get total count of "raindrops" that fell within circle
for (i = 0; i < nTotalThreads; i++) {
nTotalCount += aCounts_h[i];
}
// Calculate approximate value of pi based on relationship between square and inscribed circle
nPI = (double) nTotalCount / nIterations * 4;
// Print results
printf("# of trials= %d, estimate of pi is %.16f \n", nIterations, nPI);
// Free memory (GPU)
hipFree(aCounts_d);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*************************************************************************************************************
* FILE: p2.cu
*
* AUTHOR: attiffan Aurora T. Tiffany-Davis
*
* DESCRIPTION: A CUDA program that calculates an approximate value for PI using Monte Carlo methods.
*
* TO RUN: srun -N1 -n1 -p opteron --pty /bin/bash
* make -f p2.Makefile
* ./p2 [number of iterations for Monte Carlo simulation]
*************************************************************************************************************/
// INCLUDES
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
// DEFINES
#define N_NUM_BLOCKS 64
#define N_NUM_THREADS_PER_BLOCK 512
/*************************************************************************************************************
* FUNCTION: iterateMonteCarlo
*
* DESCRIPTION: GPU kernel that iterates through part of a Monte Carlo simulation for approximating PI.
*
* ARGUMENTS: nThreads - Number of threads which are participating in simulation
* nIterations - Total number of iterations to run
* aCounts - Pointer to an array of "raindrop" counts
*
* AUTHOR: attiffan Aurora T. Tiffany-Davis
*************************************************************************************************************/
__global__ void iterateMonteCarlo (int nThreads, int nIterations, int *aCounts) {
// Declare variables
int i;
int nThreadID;
int nCount;
double nX;
double nY;
double nZ;
hiprandState state;
// Initialize variables
nThreadID = threadIdx.x + blockIdx.x * blockDim.x;
nCount = 0;
// If this thread is meant to participate, proceed
if (nThreadID < nThreads) {
// Initialize random number generator
hiprand_init(clock64(), nThreadID, 0, &state);
// Iterate through part of a Monte Carlo simulation, counting how many "raindrops" land in circle
for (i = nThreadID; i < nIterations; i += nThreads) {
nX = (double) hiprand_uniform(&state);
nY = (double) hiprand_uniform(&state);
nZ = (nX * nX) + (nY * nY);
if (nZ <= 1) {
nCount++;
}
}
// Put your count in the counts array by thread index
aCounts[nThreadID] = nCount;
}
}
/*************************************************************************************************************
* FUNCTION: main
*
* DESCRIPTION: Calculate an approximate value for PI using Monte Carlo methods.
*
* ARGUMENTS: 0 - (as always, name of program)
* 1 - Number of iterations to run
*
* AUTHOR: attiffan Aurora T. Tiffany-Davis
*************************************************************************************************************/
int main(int argc, char** argv) {
// Declare variables (CPU)
double nPI;
int i;
int nTotalCount;
int nTotalThreads = N_NUM_BLOCKS * N_NUM_THREADS_PER_BLOCK;
int nIterations;
int aCounts_h[nTotalThreads];
// Declare variables (GPU)
int *aCounts_d;
// Initialize variables
nIterations = atoi(argv[1]);
nTotalCount = 0;
// Allocate memory (GPU)
hipMalloc((void **) &aCounts_d, sizeof(int) * nTotalThreads);
// Run Monte Carlo simulation on GPU
iterateMonteCarlo <<< N_NUM_BLOCKS, N_NUM_THREADS_PER_BLOCK >>> (nTotalThreads, nIterations, aCounts_d);
// Copy back from GPU to CPU
hipMemcpy(&aCounts_h, aCounts_d, sizeof(int) * nTotalThreads, hipMemcpyDeviceToHost);
// Get total count of "raindrops" that fell within circle
for (i = 0; i < nTotalThreads; i++) {
nTotalCount += aCounts_h[i];
}
// Calculate approximate value of pi based on relationship between square and inscribed circle
nPI = (double) nTotalCount / nIterations * 4;
// Print results
printf("# of trials= %d, estimate of pi is %.16f \n", nIterations, nPI);
// Free memory (GPU)
hipFree(aCounts_d);
} | .text
.file "p2.hip"
.globl _Z32__device_stub__iterateMonteCarloiiPi # -- Begin function _Z32__device_stub__iterateMonteCarloiiPi
.p2align 4, 0x90
.type _Z32__device_stub__iterateMonteCarloiiPi,@function
_Z32__device_stub__iterateMonteCarloiiPi: # @_Z32__device_stub__iterateMonteCarloiiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z17iterateMonteCarloiiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z32__device_stub__iterateMonteCarloiiPi, .Lfunc_end0-_Z32__device_stub__iterateMonteCarloiiPi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x4010000000000000 # double 4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $131192, %rsp # imm = 0x20078
.cfi_def_cfa_offset 131216
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq 8(%rsi), %rdi
xorl %r14d, %r14d
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $131072, %esi # imm = 0x20000
callq hipMalloc
movabsq $4294967360, %rdi # imm = 0x100000040
leaq 448(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movl $32768, 20(%rsp) # imm = 0x8000
movl %ebx, 16(%rsp)
movq %rax, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17iterateMonteCarloiiPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 112(%rsp), %rdi
movl $131072, %edx # imm = 0x20000
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
addl 112(%rsp,%rax,4), %r14d
incq %rax
cmpq $32768, %rax # imm = 0x8000
jne .LBB1_3
# %bb.4:
cvtsi2sd %r14d, %xmm0
cvtsi2sd %ebx, %xmm1
divsd %xmm1, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
movl $.L.str, %edi
movl %ebx, %esi
movb $1, %al
callq printf
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $131192, %rsp # imm = 0x20078
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17iterateMonteCarloiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17iterateMonteCarloiiPi,@object # @_Z17iterateMonteCarloiiPi
.section .rodata,"a",@progbits
.globl _Z17iterateMonteCarloiiPi
.p2align 3, 0x0
_Z17iterateMonteCarloiiPi:
.quad _Z32__device_stub__iterateMonteCarloiiPi
.size _Z17iterateMonteCarloiiPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "# of trials= %d, estimate of pi is %.16f \n"
.size .L.str, 43
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z17iterateMonteCarloiiPi"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__iterateMonteCarloiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17iterateMonteCarloiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014d6b2_00000000-6_p2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2274:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2274:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z17iterateMonteCarloiiPiiiPi
.type _Z39__device_stub__Z17iterateMonteCarloiiPiiiPi, @function
_Z39__device_stub__Z17iterateMonteCarloiiPiiiPi:
.LFB2296:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17iterateMonteCarloiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2296:
.size _Z39__device_stub__Z17iterateMonteCarloiiPiiiPi, .-_Z39__device_stub__Z17iterateMonteCarloiiPiiiPi
.globl _Z17iterateMonteCarloiiPi
.type _Z17iterateMonteCarloiiPi, @function
_Z17iterateMonteCarloiiPi:
.LFB2297:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z17iterateMonteCarloiiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2297:
.size _Z17iterateMonteCarloiiPi, .-_Z17iterateMonteCarloiiPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "# of trials= %d, estimate of pi is %.16f \n"
.text
.globl main
.type main, @function
main:
.LFB2271:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r13
pushq %r12
pushq %rbx
subq $56, %rsp
.cfi_offset 13, -24
.cfi_offset 12, -32
.cfi_offset 3, -40
movq %fs:40, %rax
movq %rax, -40(%rbp)
xorl %eax, %eax
leaq -131072(%rsp), %rax
.L12:
cmpq %rax, %rsp
je .L13
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L12
.L13:
movq %rsp, %r13
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %r12d
leaq -72(%rbp), %rdi
movl $131072, %esi
call cudaMalloc@PLT
movl $512, -52(%rbp)
movl $1, -48(%rbp)
movl $1, -44(%rbp)
movl $64, -64(%rbp)
movl $1, -60(%rbp)
movl $1, -56(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -52(%rbp), %rdx
movl $1, %ecx
movq -64(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L15
movq -72(%rbp), %rdx
movl %ebx, %esi
movl $32768, %edi
call _Z39__device_stub__Z17iterateMonteCarloiiPiiiPi
.L15:
movl $2, %ecx
movl $131072, %edx
movq -72(%rbp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %r13, %rax
leaq 131072(%r13), %rsi
movl $0, %ecx
.L16:
addl (%rax), %ecx
addq $4, %rax
cmpq %rsi, %rax
jne .L16
pxor %xmm0, %xmm0
cvtsi2sdl %ecx, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl %ebx, %xmm1
divsd %xmm1, %xmm0
mulsd .LC0(%rip), %xmm0
movl %r12d, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq -72(%rbp), %rdi
call cudaFree@PLT
movq -40(%rbp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
leaq -24(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L20:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2271:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z17iterateMonteCarloiiPi"
.LC3:
.string "precalc_xorwow_matrix"
.LC4:
.string "precalc_xorwow_offset_matrix"
.LC5:
.string "mrg32k3aM1"
.LC6:
.string "mrg32k3aM2"
.LC7:
.string "mrg32k3aM1SubSeq"
.LC8:
.string "mrg32k3aM2SubSeq"
.LC9:
.string "mrg32k3aM1Seq"
.LC10:
.string "mrg32k3aM2Seq"
.LC11:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2299:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z17iterateMonteCarloiiPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2299:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1074790400
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "p2.hip"
.globl _Z32__device_stub__iterateMonteCarloiiPi # -- Begin function _Z32__device_stub__iterateMonteCarloiiPi
.p2align 4, 0x90
.type _Z32__device_stub__iterateMonteCarloiiPi,@function
_Z32__device_stub__iterateMonteCarloiiPi: # @_Z32__device_stub__iterateMonteCarloiiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z17iterateMonteCarloiiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z32__device_stub__iterateMonteCarloiiPi, .Lfunc_end0-_Z32__device_stub__iterateMonteCarloiiPi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x4010000000000000 # double 4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $131192, %rsp # imm = 0x20078
.cfi_def_cfa_offset 131216
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq 8(%rsi), %rdi
xorl %r14d, %r14d
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $131072, %esi # imm = 0x20000
callq hipMalloc
movabsq $4294967360, %rdi # imm = 0x100000040
leaq 448(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movl $32768, 20(%rsp) # imm = 0x8000
movl %ebx, 16(%rsp)
movq %rax, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17iterateMonteCarloiiPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 112(%rsp), %rdi
movl $131072, %edx # imm = 0x20000
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
addl 112(%rsp,%rax,4), %r14d
incq %rax
cmpq $32768, %rax # imm = 0x8000
jne .LBB1_3
# %bb.4:
cvtsi2sd %r14d, %xmm0
cvtsi2sd %ebx, %xmm1
divsd %xmm1, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
movl $.L.str, %edi
movl %ebx, %esi
movb $1, %al
callq printf
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $131192, %rsp # imm = 0x20078
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17iterateMonteCarloiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17iterateMonteCarloiiPi,@object # @_Z17iterateMonteCarloiiPi
.section .rodata,"a",@progbits
.globl _Z17iterateMonteCarloiiPi
.p2align 3, 0x0
_Z17iterateMonteCarloiiPi:
.quad _Z32__device_stub__iterateMonteCarloiiPi
.size _Z17iterateMonteCarloiiPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "# of trials= %d, estimate of pi is %.16f \n"
.size .L.str, 43
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z17iterateMonteCarloiiPi"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__iterateMonteCarloiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17iterateMonteCarloiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void MyKernel() {
}
__global__ void MyKernelFlops(float n, float a, float b, float c) {
int i =0;
while (i<n) {
a+=b*c;
i++;
}
}
__global__ void MyKernelIops(int n, int a, int b, int c) {
int i =0;
while (i<n) {
a+=b*c;
i++;
}
}
void measureInIops() {
int n = 1000000;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
MyKernelIops<<<2, 1024>>>(n, 2, 3, 6);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("\nTime in milliseconds : %f",milliseconds);
float giops = (n*1)/milliseconds/1e6;
printf("\nGIOPS : %f",giops);
}
void measureInFlops() {
int n = 1000000;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
MyKernelFlops<<<2, 1024>>>(n, 2.1f, 3.5f, 6.0f);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("\nTime in milliseconds : %f",milliseconds);
float gflops = (n*1)/milliseconds/1e6;
printf("\nGFLOPS : %f",gflops);
}
int main(void)
{
int n, type ;
float *d_a, *d_b;
printf("Please select from below options :\n1 -> Measure GPU Speed \n2 -> Measure memory bandwidth \n --> : ");
scanf("%d",&type);
if(type == 1) {
int m;
printf("Please select from below options :\n1 -> Measure in GIOPS \n2 -> Measure in GFLOPS \n --> : ");
scanf("%d",&m);
if(m==1) {
measureInIops();
} else if(m == 2) {
measureInFlops();
}
}else if(type == 2) {
printf("Enter Block size : ");
scanf("%d",&n);
cudaMalloc(&d_a, n);
cudaMalloc(&d_b, n);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaMemcpy(d_a, d_b, n, cudaMemcpyDeviceToDevice);
cudaEventRecord(start);
MyKernel<<<2, 1024>>>();
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("Bandwidth (GB/s): %fn", n*4/milliseconds/1e6);
}
} | code for sm_80
Function : _Z12MyKernelIopsiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13MyKernelFlopsffff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8MyKernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void MyKernel() {
}
__global__ void MyKernelFlops(float n, float a, float b, float c) {
int i =0;
while (i<n) {
a+=b*c;
i++;
}
}
__global__ void MyKernelIops(int n, int a, int b, int c) {
int i =0;
while (i<n) {
a+=b*c;
i++;
}
}
void measureInIops() {
int n = 1000000;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
MyKernelIops<<<2, 1024>>>(n, 2, 3, 6);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("\nTime in milliseconds : %f",milliseconds);
float giops = (n*1)/milliseconds/1e6;
printf("\nGIOPS : %f",giops);
}
void measureInFlops() {
int n = 1000000;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
MyKernelFlops<<<2, 1024>>>(n, 2.1f, 3.5f, 6.0f);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("\nTime in milliseconds : %f",milliseconds);
float gflops = (n*1)/milliseconds/1e6;
printf("\nGFLOPS : %f",gflops);
}
int main(void)
{
int n, type ;
float *d_a, *d_b;
printf("Please select from below options :\n1 -> Measure GPU Speed \n2 -> Measure memory bandwidth \n --> : ");
scanf("%d",&type);
if(type == 1) {
int m;
printf("Please select from below options :\n1 -> Measure in GIOPS \n2 -> Measure in GFLOPS \n --> : ");
scanf("%d",&m);
if(m==1) {
measureInIops();
} else if(m == 2) {
measureInFlops();
}
}else if(type == 2) {
printf("Enter Block size : ");
scanf("%d",&n);
cudaMalloc(&d_a, n);
cudaMalloc(&d_b, n);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaMemcpy(d_a, d_b, n, cudaMemcpyDeviceToDevice);
cudaEventRecord(start);
MyKernel<<<2, 1024>>>();
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("Bandwidth (GB/s): %fn", n*4/milliseconds/1e6);
}
} | .file "tmpxft_00192a52_00000000-6_Gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z8MyKernelvv
.type _Z26__device_stub__Z8MyKernelvv, @function
_Z26__device_stub__Z8MyKernelvv:
.LFB2084:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8MyKernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z26__device_stub__Z8MyKernelvv, .-_Z26__device_stub__Z8MyKernelvv
.globl _Z8MyKernelv
.type _Z8MyKernelv, @function
_Z8MyKernelv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8MyKernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z8MyKernelv, .-_Z8MyKernelv
.globl _Z35__device_stub__Z13MyKernelFlopsffffffff
.type _Z35__device_stub__Z13MyKernelFlopsffffffff, @function
_Z35__device_stub__Z13MyKernelFlopsffffffff:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
movss %xmm3, (%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 152
pushq 24(%rsp)
.cfi_def_cfa_offset 160
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13MyKernelFlopsffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z35__device_stub__Z13MyKernelFlopsffffffff, .-_Z35__device_stub__Z13MyKernelFlopsffffffff
.globl _Z13MyKernelFlopsffff
.type _Z13MyKernelFlopsffff, @function
_Z13MyKernelFlopsffff:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13MyKernelFlopsffffffff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z13MyKernelFlopsffff, .-_Z13MyKernelFlopsffff
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "\nTime in milliseconds : %f"
.LC6:
.string "\nGFLOPS : %f"
.text
.globl _Z14measureInFlopsv
.type _Z14measureInFlopsv, @function
_Z14measureInFlopsv:
.LFB2058:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
call cudaEventCreate@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq (%rsp), %rdi
call cudaEventRecord@PLT
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movq 8(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 28(%rsp)
leaq 28(%rsp), %rdi
movq 8(%rsp), %rdx
movq (%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 28(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss .LC3(%rip), %xmm1
movaps %xmm1, %xmm0
divss 28(%rsp), %xmm0
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movss .LC0(%rip), %xmm3
movss .LC1(%rip), %xmm2
movss .LC2(%rip), %xmm1
movss .LC3(%rip), %xmm0
call _Z35__device_stub__Z13MyKernelFlopsffffffff
jmp .L20
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z14measureInFlopsv, .-_Z14measureInFlopsv
.globl _Z34__device_stub__Z12MyKernelIopsiiiiiiii
.type _Z34__device_stub__Z12MyKernelIopsiiiiiiii, @function
_Z34__device_stub__Z12MyKernelIopsiiiiiiii:
.LFB2088:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 152
pushq 24(%rsp)
.cfi_def_cfa_offset 160
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12MyKernelIopsiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z34__device_stub__Z12MyKernelIopsiiiiiiii, .-_Z34__device_stub__Z12MyKernelIopsiiiiiiii
.globl _Z12MyKernelIopsiiii
.type _Z12MyKernelIopsiiii, @function
_Z12MyKernelIopsiiii:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z12MyKernelIopsiiiiiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z12MyKernelIopsiiii, .-_Z12MyKernelIopsiiii
.section .rodata.str1.1
.LC7:
.string "\nGIOPS : %f"
.text
.globl _Z13measureInIopsv
.type _Z13measureInIopsv, @function
_Z13measureInIopsv:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
call cudaEventCreate@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq (%rsp), %rdi
call cudaEventRecord@PLT
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L34:
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movq 8(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 28(%rsp)
leaq 28(%rsp), %rdi
movq 8(%rsp), %rdx
movq (%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 28(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss .LC3(%rip), %xmm1
movaps %xmm1, %xmm0
divss 28(%rsp), %xmm0
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
movl $6, %ecx
movl $3, %edx
movl $2, %esi
movl $1000000, %edi
call _Z34__device_stub__Z12MyKernelIopsiiiiiiii
jmp .L34
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z13measureInIopsv, .-_Z13measureInIopsv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "Please select from below options :\n1 -> Measure GPU Speed \n2 -> Measure memory bandwidth \n --> : "
.section .rodata.str1.1
.LC9:
.string "%d"
.section .rodata.str1.8
.align 8
.LC10:
.string "Please select from below options :\n1 -> Measure in GIOPS \n2 -> Measure in GFLOPS \n --> : "
.section .rodata.str1.1
.LC11:
.string "Enter Block size : "
.LC13:
.string "Bandwidth (GB/s): %fn"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq .LC8(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 12(%rsp), %rsi
leaq .LC9(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 12(%rsp), %eax
cmpl $1, %eax
je .L47
cmpl $2, %eax
je .L48
.L43:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L49
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 60(%rsp), %rsi
leaq .LC9(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 60(%rsp), %eax
cmpl $1, %eax
je .L50
cmpl $2, %eax
jne .L43
call _Z14measureInFlopsv
jmp .L43
.L50:
call _Z13measureInIopsv
jmp .L43
.L48:
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rsi
leaq .LC9(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movslq 8(%rsp), %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movslq 8(%rsp), %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movslq 8(%rsp), %rdx
movl $3, %ecx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $2, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L44:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 60(%rsp)
leaq 60(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl 8(%rsp), %eax
sall $2, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
divss 60(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LC12(%rip), %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L43
.L51:
call _Z26__device_stub__Z8MyKernelvv
jmp .L44
.L49:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC14:
.string "_Z12MyKernelIopsiiii"
.LC15:
.string "_Z13MyKernelFlopsffff"
.LC16:
.string "_Z8MyKernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z12MyKernelIopsiiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z13MyKernelFlopsffff(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z8MyKernelv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1086324736
.align 4
.LC1:
.long 1080033280
.align 4
.LC2:
.long 1074161254
.align 4
.LC3:
.long 1232348160
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC12:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void MyKernel() {
}
__global__ void MyKernelFlops(float n, float a, float b, float c) {
int i =0;
while (i<n) {
a+=b*c;
i++;
}
}
__global__ void MyKernelIops(int n, int a, int b, int c) {
int i =0;
while (i<n) {
a+=b*c;
i++;
}
}
void measureInIops() {
int n = 1000000;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
MyKernelIops<<<2, 1024>>>(n, 2, 3, 6);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("\nTime in milliseconds : %f",milliseconds);
float giops = (n*1)/milliseconds/1e6;
printf("\nGIOPS : %f",giops);
}
void measureInFlops() {
int n = 1000000;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
MyKernelFlops<<<2, 1024>>>(n, 2.1f, 3.5f, 6.0f);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("\nTime in milliseconds : %f",milliseconds);
float gflops = (n*1)/milliseconds/1e6;
printf("\nGFLOPS : %f",gflops);
}
int main(void)
{
int n, type ;
float *d_a, *d_b;
printf("Please select from below options :\n1 -> Measure GPU Speed \n2 -> Measure memory bandwidth \n --> : ");
scanf("%d",&type);
if(type == 1) {
int m;
printf("Please select from below options :\n1 -> Measure in GIOPS \n2 -> Measure in GFLOPS \n --> : ");
scanf("%d",&m);
if(m==1) {
measureInIops();
} else if(m == 2) {
measureInFlops();
}
}else if(type == 2) {
printf("Enter Block size : ");
scanf("%d",&n);
cudaMalloc(&d_a, n);
cudaMalloc(&d_b, n);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaMemcpy(d_a, d_b, n, cudaMemcpyDeviceToDevice);
cudaEventRecord(start);
MyKernel<<<2, 1024>>>();
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("Bandwidth (GB/s): %fn", n*4/milliseconds/1e6);
}
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void MyKernel() {
}
__global__ void MyKernelFlops(float n, float a, float b, float c) {
int i =0;
while (i<n) {
a+=b*c;
i++;
}
}
__global__ void MyKernelIops(int n, int a, int b, int c) {
int i =0;
while (i<n) {
a+=b*c;
i++;
}
}
void measureInIops() {
int n = 1000000;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
MyKernelIops<<<2, 1024>>>(n, 2, 3, 6);
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("\nTime in milliseconds : %f",milliseconds);
float giops = (n*1)/milliseconds/1e6;
printf("\nGIOPS : %f",giops);
}
void measureInFlops() {
int n = 1000000;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
MyKernelFlops<<<2, 1024>>>(n, 2.1f, 3.5f, 6.0f);
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("\nTime in milliseconds : %f",milliseconds);
float gflops = (n*1)/milliseconds/1e6;
printf("\nGFLOPS : %f",gflops);
}
int main(void)
{
int n, type ;
float *d_a, *d_b;
printf("Please select from below options :\n1 -> Measure GPU Speed \n2 -> Measure memory bandwidth \n --> : ");
scanf("%d",&type);
if(type == 1) {
int m;
printf("Please select from below options :\n1 -> Measure in GIOPS \n2 -> Measure in GFLOPS \n --> : ");
scanf("%d",&m);
if(m==1) {
measureInIops();
} else if(m == 2) {
measureInFlops();
}
}else if(type == 2) {
printf("Enter Block size : ");
scanf("%d",&n);
hipMalloc(&d_a, n);
hipMalloc(&d_b, n);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipMemcpy(d_a, d_b, n, hipMemcpyDeviceToDevice);
hipEventRecord(start);
MyKernel<<<2, 1024>>>();
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("Bandwidth (GB/s): %fn", n*4/milliseconds/1e6);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void MyKernel() {
}
__global__ void MyKernelFlops(float n, float a, float b, float c) {
int i =0;
while (i<n) {
a+=b*c;
i++;
}
}
__global__ void MyKernelIops(int n, int a, int b, int c) {
int i =0;
while (i<n) {
a+=b*c;
i++;
}
}
void measureInIops() {
int n = 1000000;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
MyKernelIops<<<2, 1024>>>(n, 2, 3, 6);
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("\nTime in milliseconds : %f",milliseconds);
float giops = (n*1)/milliseconds/1e6;
printf("\nGIOPS : %f",giops);
}
void measureInFlops() {
int n = 1000000;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
MyKernelFlops<<<2, 1024>>>(n, 2.1f, 3.5f, 6.0f);
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("\nTime in milliseconds : %f",milliseconds);
float gflops = (n*1)/milliseconds/1e6;
printf("\nGFLOPS : %f",gflops);
}
int main(void)
{
int n, type ;
float *d_a, *d_b;
printf("Please select from below options :\n1 -> Measure GPU Speed \n2 -> Measure memory bandwidth \n --> : ");
scanf("%d",&type);
if(type == 1) {
int m;
printf("Please select from below options :\n1 -> Measure in GIOPS \n2 -> Measure in GFLOPS \n --> : ");
scanf("%d",&m);
if(m==1) {
measureInIops();
} else if(m == 2) {
measureInFlops();
}
}else if(type == 2) {
printf("Enter Block size : ");
scanf("%d",&n);
hipMalloc(&d_a, n);
hipMalloc(&d_b, n);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipMemcpy(d_a, d_b, n, hipMemcpyDeviceToDevice);
hipEventRecord(start);
MyKernel<<<2, 1024>>>();
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("Bandwidth (GB/s): %fn", n*4/milliseconds/1e6);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8MyKernelv
.globl _Z8MyKernelv
.p2align 8
.type _Z8MyKernelv,@function
_Z8MyKernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8MyKernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8MyKernelv, .Lfunc_end0-_Z8MyKernelv
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13MyKernelFlopsffff
.globl _Z13MyKernelFlopsffff
.p2align 8
.type _Z13MyKernelFlopsffff,@function
_Z13MyKernelFlopsffff:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13MyKernelFlopsffff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13MyKernelFlopsffff, .Lfunc_end1-_Z13MyKernelFlopsffff
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12MyKernelIopsiiii
.globl _Z12MyKernelIopsiiii
.p2align 8
.type _Z12MyKernelIopsiiii,@function
_Z12MyKernelIopsiiii:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12MyKernelIopsiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z12MyKernelIopsiiii, .Lfunc_end2-_Z12MyKernelIopsiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8MyKernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z8MyKernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13MyKernelFlopsffff
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z13MyKernelFlopsffff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12MyKernelIopsiiii
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z12MyKernelIopsiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void MyKernel() {
}
__global__ void MyKernelFlops(float n, float a, float b, float c) {
int i =0;
while (i<n) {
a+=b*c;
i++;
}
}
__global__ void MyKernelIops(int n, int a, int b, int c) {
int i =0;
while (i<n) {
a+=b*c;
i++;
}
}
void measureInIops() {
int n = 1000000;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
MyKernelIops<<<2, 1024>>>(n, 2, 3, 6);
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("\nTime in milliseconds : %f",milliseconds);
float giops = (n*1)/milliseconds/1e6;
printf("\nGIOPS : %f",giops);
}
void measureInFlops() {
int n = 1000000;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
MyKernelFlops<<<2, 1024>>>(n, 2.1f, 3.5f, 6.0f);
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("\nTime in milliseconds : %f",milliseconds);
float gflops = (n*1)/milliseconds/1e6;
printf("\nGFLOPS : %f",gflops);
}
int main(void)
{
int n, type ;
float *d_a, *d_b;
printf("Please select from below options :\n1 -> Measure GPU Speed \n2 -> Measure memory bandwidth \n --> : ");
scanf("%d",&type);
if(type == 1) {
int m;
printf("Please select from below options :\n1 -> Measure in GIOPS \n2 -> Measure in GFLOPS \n --> : ");
scanf("%d",&m);
if(m==1) {
measureInIops();
} else if(m == 2) {
measureInFlops();
}
}else if(type == 2) {
printf("Enter Block size : ");
scanf("%d",&n);
hipMalloc(&d_a, n);
hipMalloc(&d_b, n);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipMemcpy(d_a, d_b, n, hipMemcpyDeviceToDevice);
hipEventRecord(start);
MyKernel<<<2, 1024>>>();
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("Bandwidth (GB/s): %fn", n*4/milliseconds/1e6);
}
} | .text
.file "Gpu.hip"
.globl _Z23__device_stub__MyKernelv # -- Begin function _Z23__device_stub__MyKernelv
.p2align 4, 0x90
.type _Z23__device_stub__MyKernelv,@function
_Z23__device_stub__MyKernelv: # @_Z23__device_stub__MyKernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8MyKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z23__device_stub__MyKernelv, .Lfunc_end0-_Z23__device_stub__MyKernelv
.cfi_endproc
# -- End function
.globl _Z28__device_stub__MyKernelFlopsffff # -- Begin function _Z28__device_stub__MyKernelFlopsffff
.p2align 4, 0x90
.type _Z28__device_stub__MyKernelFlopsffff,@function
_Z28__device_stub__MyKernelFlopsffff: # @_Z28__device_stub__MyKernelFlopsffff
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
movss %xmm3, (%rsp)
leaq 12(%rsp), %rax
movq %rax, 64(%rsp)
leaq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13MyKernelFlopsffff, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z28__device_stub__MyKernelFlopsffff, .Lfunc_end1-_Z28__device_stub__MyKernelFlopsffff
.cfi_endproc
# -- End function
.globl _Z27__device_stub__MyKernelIopsiiii # -- Begin function _Z27__device_stub__MyKernelIopsiiii
.p2align 4, 0x90
.type _Z27__device_stub__MyKernelIopsiiii,@function
_Z27__device_stub__MyKernelIopsiiii: # @_Z27__device_stub__MyKernelIopsiiii
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
leaq 12(%rsp), %rax
movq %rax, 64(%rsp)
leaq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12MyKernelIopsiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z27__device_stub__MyKernelIopsiiii, .Lfunc_end2-_Z27__device_stub__MyKernelIopsiiii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z13measureInIopsv
.LCPI3_0:
.long 0x49742400 # float 1.0E+6
.text
.globl _Z13measureInIopsv
.p2align 4, 0x90
.type _Z13measureInIopsv,@function
_Z13measureInIopsv: # @_Z13measureInIopsv
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
leaq 24(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 1022(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movl $1000000, 20(%rsp) # imm = 0xF4240
movl $2, 16(%rsp)
movl $3, 12(%rsp)
movl $6, 8(%rsp)
leaq 20(%rsp), %rax
movq %rax, 32(%rsp)
leaq 16(%rsp), %rax
movq %rax, 40(%rsp)
leaq 12(%rsp), %rax
movq %rax, 48(%rsp)
leaq 8(%rsp), %rax
movq %rax, 56(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z12MyKernelIopsiiii, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movl $0, 32(%rsp)
movq 24(%rsp), %rsi
movq (%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movss .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps %xmm0, %xmm1
divss 32(%rsp), %xmm1
divss %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
addq $120, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z13measureInIopsv, .Lfunc_end3-_Z13measureInIopsv
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z14measureInFlopsv
.LCPI4_0:
.long 0x49742400 # float 1.0E+6
.text
.globl _Z14measureInFlopsv
.p2align 4, 0x90
.type _Z14measureInFlopsv,@function
_Z14measureInFlopsv: # @_Z14measureInFlopsv
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
leaq 24(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 1022(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movl $1232348160, 20(%rsp) # imm = 0x49742400
movl $1074161254, 16(%rsp) # imm = 0x40066666
movl $1080033280, 12(%rsp) # imm = 0x40600000
movl $1086324736, 8(%rsp) # imm = 0x40C00000
leaq 20(%rsp), %rax
movq %rax, 32(%rsp)
leaq 16(%rsp), %rax
movq %rax, 40(%rsp)
leaq 12(%rsp), %rax
movq %rax, 48(%rsp)
leaq 8(%rsp), %rax
movq %rax, 56(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z13MyKernelFlopsffff, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movl $0, 32(%rsp)
movq 24(%rsp), %rsi
movq (%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movss .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps %xmm0, %xmm1
divss 32(%rsp), %xmm1
divss %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
addq $120, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z14measureInFlopsv, .Lfunc_end4-_Z14measureInFlopsv
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI5_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
leaq 36(%rsp), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 36(%rsp), %eax
cmpl $2, %eax
je .LBB5_6
# %bb.1:
cmpl $1, %eax
jne .LBB5_9
# %bb.2:
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
leaq 8(%rsp), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 8(%rsp), %eax
cmpl $2, %eax
je .LBB5_5
# %bb.3:
cmpl $1, %eax
jne .LBB5_9
# %bb.4:
callq _Z13measureInIopsv
jmp .LBB5_9
.LBB5_6:
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
leaq 4(%rsp), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 4(%rsp), %rsi
leaq 56(%rsp), %rdi
callq hipMalloc
movslq 4(%rsp), %rsi
leaq 48(%rsp), %rdi
callq hipMalloc
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq 56(%rsp), %rdi
movq 48(%rsp), %rsi
movslq 4(%rsp), %rdx
movl $3, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 1022(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_8
# %bb.7:
leaq 8(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8MyKernelv, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_8:
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movl $0, 8(%rsp)
movq 40(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 8(%rsp), %rdi
callq hipEventElapsedTime
movl 4(%rsp), %eax
shll $2, %eax
cvtsi2ss %eax, %xmm0
divss 8(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LCPI5_0(%rip), %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
jmp .LBB5_9
.LBB5_5:
callq _Z14measureInFlopsv
.LBB5_9:
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8MyKernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13MyKernelFlopsffff, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12MyKernelIopsiiii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8MyKernelv,@object # @_Z8MyKernelv
.section .rodata,"a",@progbits
.globl _Z8MyKernelv
.p2align 3, 0x0
_Z8MyKernelv:
.quad _Z23__device_stub__MyKernelv
.size _Z8MyKernelv, 8
.type _Z13MyKernelFlopsffff,@object # @_Z13MyKernelFlopsffff
.globl _Z13MyKernelFlopsffff
.p2align 3, 0x0
_Z13MyKernelFlopsffff:
.quad _Z28__device_stub__MyKernelFlopsffff
.size _Z13MyKernelFlopsffff, 8
.type _Z12MyKernelIopsiiii,@object # @_Z12MyKernelIopsiiii
.globl _Z12MyKernelIopsiiii
.p2align 3, 0x0
_Z12MyKernelIopsiiii:
.quad _Z27__device_stub__MyKernelIopsiiii
.size _Z12MyKernelIopsiiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nTime in milliseconds : %f"
.size .L.str, 27
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\nGIOPS : %f"
.size .L.str.1, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nGFLOPS : %f"
.size .L.str.2, 13
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Please select from below options :\n1 -> Measure GPU Speed \n2 -> Measure memory bandwidth \n --> : "
.size .L.str.3, 98
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d"
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Please select from below options :\n1 -> Measure in GIOPS \n2 -> Measure in GFLOPS \n --> : "
.size .L.str.5, 90
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Enter Block size : "
.size .L.str.6, 20
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Bandwidth (GB/s): %fn"
.size .L.str.7, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8MyKernelv"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13MyKernelFlopsffff"
.size .L__unnamed_2, 22
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z12MyKernelIopsiiii"
.size .L__unnamed_3, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__MyKernelv
.addrsig_sym _Z28__device_stub__MyKernelFlopsffff
.addrsig_sym _Z27__device_stub__MyKernelIopsiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8MyKernelv
.addrsig_sym _Z13MyKernelFlopsffff
.addrsig_sym _Z12MyKernelIopsiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12MyKernelIopsiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13MyKernelFlopsffff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8MyKernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8MyKernelv
.globl _Z8MyKernelv
.p2align 8
.type _Z8MyKernelv,@function
_Z8MyKernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8MyKernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8MyKernelv, .Lfunc_end0-_Z8MyKernelv
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13MyKernelFlopsffff
.globl _Z13MyKernelFlopsffff
.p2align 8
.type _Z13MyKernelFlopsffff,@function
_Z13MyKernelFlopsffff:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13MyKernelFlopsffff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13MyKernelFlopsffff, .Lfunc_end1-_Z13MyKernelFlopsffff
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12MyKernelIopsiiii
.globl _Z12MyKernelIopsiiii
.p2align 8
.type _Z12MyKernelIopsiiii,@function
_Z12MyKernelIopsiiii:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12MyKernelIopsiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z12MyKernelIopsiiii, .Lfunc_end2-_Z12MyKernelIopsiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8MyKernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z8MyKernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13MyKernelFlopsffff
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z13MyKernelFlopsffff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12MyKernelIopsiiii
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z12MyKernelIopsiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00192a52_00000000-6_Gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z8MyKernelvv
.type _Z26__device_stub__Z8MyKernelvv, @function
_Z26__device_stub__Z8MyKernelvv:
.LFB2084:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8MyKernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z26__device_stub__Z8MyKernelvv, .-_Z26__device_stub__Z8MyKernelvv
.globl _Z8MyKernelv
.type _Z8MyKernelv, @function
_Z8MyKernelv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8MyKernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z8MyKernelv, .-_Z8MyKernelv
.globl _Z35__device_stub__Z13MyKernelFlopsffffffff
.type _Z35__device_stub__Z13MyKernelFlopsffffffff, @function
_Z35__device_stub__Z13MyKernelFlopsffffffff:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
movss %xmm3, (%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 152
pushq 24(%rsp)
.cfi_def_cfa_offset 160
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13MyKernelFlopsffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z35__device_stub__Z13MyKernelFlopsffffffff, .-_Z35__device_stub__Z13MyKernelFlopsffffffff
.globl _Z13MyKernelFlopsffff
.type _Z13MyKernelFlopsffff, @function
_Z13MyKernelFlopsffff:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13MyKernelFlopsffffffff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z13MyKernelFlopsffff, .-_Z13MyKernelFlopsffff
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "\nTime in milliseconds : %f"
.LC6:
.string "\nGFLOPS : %f"
.text
.globl _Z14measureInFlopsv
.type _Z14measureInFlopsv, @function
_Z14measureInFlopsv:
.LFB2058:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
call cudaEventCreate@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq (%rsp), %rdi
call cudaEventRecord@PLT
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movq 8(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 28(%rsp)
leaq 28(%rsp), %rdi
movq 8(%rsp), %rdx
movq (%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 28(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss .LC3(%rip), %xmm1
movaps %xmm1, %xmm0
divss 28(%rsp), %xmm0
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movss .LC0(%rip), %xmm3
movss .LC1(%rip), %xmm2
movss .LC2(%rip), %xmm1
movss .LC3(%rip), %xmm0
call _Z35__device_stub__Z13MyKernelFlopsffffffff
jmp .L20
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z14measureInFlopsv, .-_Z14measureInFlopsv
.globl _Z34__device_stub__Z12MyKernelIopsiiiiiiii
.type _Z34__device_stub__Z12MyKernelIopsiiiiiiii, @function
_Z34__device_stub__Z12MyKernelIopsiiiiiiii:
.LFB2088:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 152
pushq 24(%rsp)
.cfi_def_cfa_offset 160
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12MyKernelIopsiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z34__device_stub__Z12MyKernelIopsiiiiiiii, .-_Z34__device_stub__Z12MyKernelIopsiiiiiiii
.globl _Z12MyKernelIopsiiii
.type _Z12MyKernelIopsiiii, @function
_Z12MyKernelIopsiiii:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z12MyKernelIopsiiiiiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z12MyKernelIopsiiii, .-_Z12MyKernelIopsiiii
.section .rodata.str1.1
.LC7:
.string "\nGIOPS : %f"
.text
.globl _Z13measureInIopsv
.type _Z13measureInIopsv, @function
_Z13measureInIopsv:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
call cudaEventCreate@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq (%rsp), %rdi
call cudaEventRecord@PLT
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L34:
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movq 8(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 28(%rsp)
leaq 28(%rsp), %rdi
movq 8(%rsp), %rdx
movq (%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 28(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss .LC3(%rip), %xmm1
movaps %xmm1, %xmm0
divss 28(%rsp), %xmm0
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
movl $6, %ecx
movl $3, %edx
movl $2, %esi
movl $1000000, %edi
call _Z34__device_stub__Z12MyKernelIopsiiiiiiii
jmp .L34
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z13measureInIopsv, .-_Z13measureInIopsv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "Please select from below options :\n1 -> Measure GPU Speed \n2 -> Measure memory bandwidth \n --> : "
.section .rodata.str1.1
.LC9:
.string "%d"
.section .rodata.str1.8
.align 8
.LC10:
.string "Please select from below options :\n1 -> Measure in GIOPS \n2 -> Measure in GFLOPS \n --> : "
.section .rodata.str1.1
.LC11:
.string "Enter Block size : "
.LC13:
.string "Bandwidth (GB/s): %fn"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq .LC8(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 12(%rsp), %rsi
leaq .LC9(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 12(%rsp), %eax
cmpl $1, %eax
je .L47
cmpl $2, %eax
je .L48
.L43:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L49
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 60(%rsp), %rsi
leaq .LC9(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 60(%rsp), %eax
cmpl $1, %eax
je .L50
cmpl $2, %eax
jne .L43
call _Z14measureInFlopsv
jmp .L43
.L50:
call _Z13measureInIopsv
jmp .L43
.L48:
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rsi
leaq .LC9(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movslq 8(%rsp), %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movslq 8(%rsp), %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movslq 8(%rsp), %rdx
movl $3, %ecx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $2, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L44:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 60(%rsp)
leaq 60(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl 8(%rsp), %eax
sall $2, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
divss 60(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LC12(%rip), %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L43
.L51:
call _Z26__device_stub__Z8MyKernelvv
jmp .L44
.L49:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC14:
.string "_Z12MyKernelIopsiiii"
.LC15:
.string "_Z13MyKernelFlopsffff"
.LC16:
.string "_Z8MyKernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z12MyKernelIopsiiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z13MyKernelFlopsffff(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z8MyKernelv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1086324736
.align 4
.LC1:
.long 1080033280
.align 4
.LC2:
.long 1074161254
.align 4
.LC3:
.long 1232348160
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC12:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Gpu.hip"
.globl _Z23__device_stub__MyKernelv # -- Begin function _Z23__device_stub__MyKernelv
.p2align 4, 0x90
.type _Z23__device_stub__MyKernelv,@function
_Z23__device_stub__MyKernelv: # @_Z23__device_stub__MyKernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8MyKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z23__device_stub__MyKernelv, .Lfunc_end0-_Z23__device_stub__MyKernelv
.cfi_endproc
# -- End function
.globl _Z28__device_stub__MyKernelFlopsffff # -- Begin function _Z28__device_stub__MyKernelFlopsffff
.p2align 4, 0x90
.type _Z28__device_stub__MyKernelFlopsffff,@function
_Z28__device_stub__MyKernelFlopsffff: # @_Z28__device_stub__MyKernelFlopsffff
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
movss %xmm3, (%rsp)
leaq 12(%rsp), %rax
movq %rax, 64(%rsp)
leaq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13MyKernelFlopsffff, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z28__device_stub__MyKernelFlopsffff, .Lfunc_end1-_Z28__device_stub__MyKernelFlopsffff
.cfi_endproc
# -- End function
.globl _Z27__device_stub__MyKernelIopsiiii # -- Begin function _Z27__device_stub__MyKernelIopsiiii
.p2align 4, 0x90
.type _Z27__device_stub__MyKernelIopsiiii,@function
_Z27__device_stub__MyKernelIopsiiii: # @_Z27__device_stub__MyKernelIopsiiii
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
leaq 12(%rsp), %rax
movq %rax, 64(%rsp)
leaq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12MyKernelIopsiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z27__device_stub__MyKernelIopsiiii, .Lfunc_end2-_Z27__device_stub__MyKernelIopsiiii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z13measureInIopsv
.LCPI3_0:
.long 0x49742400 # float 1.0E+6
.text
.globl _Z13measureInIopsv
.p2align 4, 0x90
.type _Z13measureInIopsv,@function
_Z13measureInIopsv: # @_Z13measureInIopsv
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
leaq 24(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 1022(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movl $1000000, 20(%rsp) # imm = 0xF4240
movl $2, 16(%rsp)
movl $3, 12(%rsp)
movl $6, 8(%rsp)
leaq 20(%rsp), %rax
movq %rax, 32(%rsp)
leaq 16(%rsp), %rax
movq %rax, 40(%rsp)
leaq 12(%rsp), %rax
movq %rax, 48(%rsp)
leaq 8(%rsp), %rax
movq %rax, 56(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z12MyKernelIopsiiii, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movl $0, 32(%rsp)
movq 24(%rsp), %rsi
movq (%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movss .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps %xmm0, %xmm1
divss 32(%rsp), %xmm1
divss %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
addq $120, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z13measureInIopsv, .Lfunc_end3-_Z13measureInIopsv
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z14measureInFlopsv
.LCPI4_0:
.long 0x49742400 # float 1.0E+6
.text
.globl _Z14measureInFlopsv
.p2align 4, 0x90
.type _Z14measureInFlopsv,@function
_Z14measureInFlopsv: # @_Z14measureInFlopsv
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
leaq 24(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 1022(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movl $1232348160, 20(%rsp) # imm = 0x49742400
movl $1074161254, 16(%rsp) # imm = 0x40066666
movl $1080033280, 12(%rsp) # imm = 0x40600000
movl $1086324736, 8(%rsp) # imm = 0x40C00000
leaq 20(%rsp), %rax
movq %rax, 32(%rsp)
leaq 16(%rsp), %rax
movq %rax, 40(%rsp)
leaq 12(%rsp), %rax
movq %rax, 48(%rsp)
leaq 8(%rsp), %rax
movq %rax, 56(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z13MyKernelFlopsffff, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movl $0, 32(%rsp)
movq 24(%rsp), %rsi
movq (%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movss .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps %xmm0, %xmm1
divss 32(%rsp), %xmm1
divss %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
addq $120, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z14measureInFlopsv, .Lfunc_end4-_Z14measureInFlopsv
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI5_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
leaq 36(%rsp), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 36(%rsp), %eax
cmpl $2, %eax
je .LBB5_6
# %bb.1:
cmpl $1, %eax
jne .LBB5_9
# %bb.2:
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
leaq 8(%rsp), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 8(%rsp), %eax
cmpl $2, %eax
je .LBB5_5
# %bb.3:
cmpl $1, %eax
jne .LBB5_9
# %bb.4:
callq _Z13measureInIopsv
jmp .LBB5_9
.LBB5_6:
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
leaq 4(%rsp), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 4(%rsp), %rsi
leaq 56(%rsp), %rdi
callq hipMalloc
movslq 4(%rsp), %rsi
leaq 48(%rsp), %rdi
callq hipMalloc
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq 56(%rsp), %rdi
movq 48(%rsp), %rsi
movslq 4(%rsp), %rdx
movl $3, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 1022(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_8
# %bb.7:
leaq 8(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8MyKernelv, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_8:
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movl $0, 8(%rsp)
movq 40(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 8(%rsp), %rdi
callq hipEventElapsedTime
movl 4(%rsp), %eax
shll $2, %eax
cvtsi2ss %eax, %xmm0
divss 8(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LCPI5_0(%rip), %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
jmp .LBB5_9
.LBB5_5:
callq _Z14measureInFlopsv
.LBB5_9:
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8MyKernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13MyKernelFlopsffff, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12MyKernelIopsiiii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8MyKernelv,@object # @_Z8MyKernelv
.section .rodata,"a",@progbits
.globl _Z8MyKernelv
.p2align 3, 0x0
_Z8MyKernelv:
.quad _Z23__device_stub__MyKernelv
.size _Z8MyKernelv, 8
.type _Z13MyKernelFlopsffff,@object # @_Z13MyKernelFlopsffff
.globl _Z13MyKernelFlopsffff
.p2align 3, 0x0
_Z13MyKernelFlopsffff:
.quad _Z28__device_stub__MyKernelFlopsffff
.size _Z13MyKernelFlopsffff, 8
.type _Z12MyKernelIopsiiii,@object # @_Z12MyKernelIopsiiii
.globl _Z12MyKernelIopsiiii
.p2align 3, 0x0
_Z12MyKernelIopsiiii:
.quad _Z27__device_stub__MyKernelIopsiiii
.size _Z12MyKernelIopsiiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nTime in milliseconds : %f"
.size .L.str, 27
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\nGIOPS : %f"
.size .L.str.1, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nGFLOPS : %f"
.size .L.str.2, 13
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Please select from below options :\n1 -> Measure GPU Speed \n2 -> Measure memory bandwidth \n --> : "
.size .L.str.3, 98
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d"
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Please select from below options :\n1 -> Measure in GIOPS \n2 -> Measure in GFLOPS \n --> : "
.size .L.str.5, 90
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Enter Block size : "
.size .L.str.6, 20
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Bandwidth (GB/s): %fn"
.size .L.str.7, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8MyKernelv"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13MyKernelFlopsffff"
.size .L__unnamed_2, 22
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z12MyKernelIopsiiii"
.size .L__unnamed_3, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__MyKernelv
.addrsig_sym _Z28__device_stub__MyKernelFlopsffff
.addrsig_sym _Z27__device_stub__MyKernelIopsiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8MyKernelv
.addrsig_sym _Z13MyKernelFlopsffff
.addrsig_sym _Z12MyKernelIopsiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define L2HYS_EPSILON 0.01f
#define L2HYS_EPSILONHYS 1.0f
#define L2HYS_CLIP 0.2f
#define data_h2y 30
//long h_windowx=Imagewidth/Windowx;
//long h_windowy=ImageHeight/Windowy;
//dim3 blocks(h_windowx,h_windowy);//h_windowx=ImageWidth/Windowx,h_windowy=ImageHeight/Windowy
//dim3 threads(Windowx,Windowy);//ÿһ¸öÏ߳̿é¼ÆËãÒ»¸öcellµÄÌØÕ÷Á¿
//dim3 block(18,7);//Ò»¸öcell·Ö18¸ö½Ç¶È·½Ïò,Ò»¸ö·½Ïò7¸öcell£¬
__global__ void smooth(float *in,float *out)
{
int k,j,i;
int m_nBIN=10;
float *m_pCellFeatures=in;
int t_nLineWidth=70;
float t_pTemp[10];
for ( k = 0; k < 18; ++k )//18
{
for ( j = 0; j < 7; ++j )//7
{
for ( i = 0; i< 10; ++i )//10
{
int t_nLeft;
int t_nRight;
t_nLeft = ( i - 1 + m_nBIN ) % m_nBIN;
t_nRight = ( i + 1 ) % m_nBIN;
t_pTemp[i] = m_pCellFeatures[k * t_nLineWidth + j * m_nBIN + i] * 0.8f
+ m_pCellFeatures[k * t_nLineWidth + j * m_nBIN + t_nLeft] * 0.1f
+ m_pCellFeatures[k * t_nLineWidth + j * m_nBIN + t_nRight] * 0.1f;
}
for ( i = 0; i < m_nBIN; ++i )
{
out[k * t_nLineWidth + j * m_nBIN + i] = t_pTemp[i];
}
}
}
} | code for sm_80
Function : _Z6smoothPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ UMOV UR4, 0x14 ; /* 0x0000001400047882 */
/* 0x000fe20000000000 */
/*0020*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ ULDC.64 UR8, c[0x0][0x168] ; /* 0x00005a0000087ab9 */
/* 0x000fe40000000a00 */
/*0050*/ UIADD3 UR6, UP0, UR4, UR6, URZ ; /* 0x0000000604067290 */
/* 0x000fe4000ff1e03f */
/*0060*/ UIADD3 UR4, UP1, UR4, UR8, URZ ; /* 0x0000000804047290 */
/* 0x000fe4000ff3e03f */
/*0070*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fc400087fe43f */
/*0080*/ UIADD3.X UR5, URZ, UR9, URZ, UP1, !UPT ; /* 0x000000093f057290 */
/* 0x000fc60008ffe43f */
/*0090*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe40000000a00 */
/*00a0*/ MOV R2, UR6 ; /* 0x0000000600027c02 */
/* 0x002fe20008000f00 */
/*00b0*/ IMAD R13, R0, 0x46, RZ ; /* 0x00000046000d7824 */
/* 0x000fe200078e02ff */
/*00c0*/ MOV R3, UR7 ; /* 0x0000000700037c02 */
/* 0x000fca0008000f00 */
/*00d0*/ IMAD.WIDE R2, R13, 0x4, R2 ; /* 0x000000040d027825 */
/* 0x000fca00078e0202 */
/*00e0*/ LDG.E R11, [R2.64+0x10] ; /* 0x00001008020b7981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ LDG.E R10, [R2.64+-0x14] ; /* 0xffffec08020a7981 */
/* 0x000ee8000c1e1900 */
/*0100*/ LDG.E R14, [R2.64+-0x10] ; /* 0xfffff008020e7981 */
/* 0x000f28000c1e1900 */
/*0110*/ LDG.E R19, [R2.64+-0xc] ; /* 0xfffff40802137981 */
/* 0x000f68000c1e1900 */
/*0120*/ LDG.E R21, [R2.64+-0x8] ; /* 0xfffff80802157981 */
/* 0x000f68000c1e1900 */
/*0130*/ LDG.E R12, [R2.64+-0x4] ; /* 0xfffffc08020c7981 */
/* 0x000f68000c1e1900 */
/*0140*/ LDG.E R9, [R2.64] ; /* 0x0000000802097981 */
/* 0x000f68000c1e1900 */
/*0150*/ LDG.E R6, [R2.64+0x8] ; /* 0x0000080802067981 */
/* 0x000f68000c1e1900 */
/*0160*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040802087981 */
/* 0x000f68000c1e1900 */
/*0170*/ LDG.E R7, [R2.64+0xc] ; /* 0x00000c0802077981 */
/* 0x000f62000c1e1900 */
/*0180*/ MOV R4, UR4 ; /* 0x0000000400047c02 */
/* 0x000fc40008000f00 */
/*0190*/ MOV R5, UR5 ; /* 0x0000000500057c02 */
/* 0x000fca0008000f00 */
/*01a0*/ IMAD.WIDE R4, R13, 0x4, R4 ; /* 0x000000040d047825 */
/* 0x000fe200078e0204 */
/*01b0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fc80007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P0, PT, R0, 0x12, PT ; /* 0x000000120000780c */
/* 0x000fe20003f06070 */
/*01d0*/ FMUL R15, R11, 0.10000000149011611938 ; /* 0x3dcccccd0b0f7820 */
/* 0x004fe40000400000 */
/*01e0*/ FMUL R17, R10.reuse, 0.10000000149011611938 ; /* 0x3dcccccd0a117820 */
/* 0x048fe40000400000 */
/*01f0*/ FFMA R15, R10, 0.80000001192092895508, R15 ; /* 0x3f4ccccd0a0f7823 */
/* 0x000fe4000000000f */
/*0200*/ FMUL R16, R14.reuse, 0.10000000149011611938 ; /* 0x3dcccccd0e107820 */
/* 0x050fe40000400000 */
/*0210*/ FFMA R17, R14, 0.80000001192092895508, R17 ; /* 0x3f4ccccd0e117823 */
/* 0x000fe40000000011 */
/*0220*/ FMUL R14, R19, 0.10000000149011611938 ; /* 0x3dcccccd130e7820 */
/* 0x020fc40000400000 */
/*0230*/ FADD R13, R15, R16.reuse ; /* 0x000000100f0d7221 */
/* 0x100fe40000000000 */
/*0240*/ FFMA R16, R19, 0.80000001192092895508, R16 ; /* 0x3f4ccccd13107823 */
/* 0x000fe40000000010 */
/*0250*/ FMUL R19, R21, 0.10000000149011611938 ; /* 0x3dcccccd15137820 */
/* 0x000fe40000400000 */
/*0260*/ FADD R15, R17, R14.reuse ; /* 0x0000000e110f7221 */
/* 0x100fe40000000000 */
/*0270*/ FFMA R14, R21, 0.80000001192092895508, R14 ; /* 0x3f4ccccd150e7823 */
/* 0x000fe4000000000e */
/*0280*/ FMUL R18, R12, 0.10000000149011611938 ; /* 0x3dcccccd0c127820 */
/* 0x000fc40000400000 */
/*0290*/ FFMA R12, R12, 0.80000001192092895508, R19.reuse ; /* 0x3f4ccccd0c0c7823 */
/* 0x100fe40000000013 */
/*02a0*/ FMUL R21, R9.reuse, 0.10000000149011611938 ; /* 0x3dcccccd09157820 */
/* 0x040fe40000400000 */
/*02b0*/ FADD R17, R16, R19 ; /* 0x0000001310117221 */
/* 0x000fe40000000000 */
/*02c0*/ FADD R19, R14, R18.reuse ; /* 0x000000120e137221 */
/* 0x100fe40000000000 */
/*02d0*/ FFMA R18, R9, 0.80000001192092895508, R18 ; /* 0x3f4ccccd09127823 */
/* 0x000fe40000000012 */
/*02e0*/ FADD R9, R12, R21 ; /* 0x000000150c097221 */
/* 0x000fc40000000000 */
/*02f0*/ FMUL R12, R6, 0.10000000149011611938 ; /* 0x3dcccccd060c7820 */
/* 0x000fe40000400000 */
/*0300*/ FMUL R23, R8.reuse, 0.10000000149011611938 ; /* 0x3dcccccd08177820 */
/* 0x040fe40000400000 */
/*0310*/ FMUL R14, R7.reuse, 0.10000000149011611938 ; /* 0x3dcccccd070e7820 */
/* 0x040fe40000400000 */
/*0320*/ FFMA R16, R7, 0.80000001192092895508, R12 ; /* 0x3f4ccccd07107823 */
/* 0x000fe4000000000c */
/*0330*/ FFMA R8, R8, 0.80000001192092895508, R21 ; /* 0x3f4ccccd08087823 */
/* 0x000fe40000000015 */
/*0340*/ FFMA R6, R6, 0.80000001192092895508, R23 ; /* 0x3f4ccccd06067823 */
/* 0x000fc40000000017 */
/*0350*/ FFMA R7, R11.reuse, 0.80000001192092895508, R14 ; /* 0x3f4ccccd0b077823 */
/* 0x040fe4000000000e */
/*0360*/ FADD R21, R18, R23 ; /* 0x0000001712157221 */
/* 0x000fe40000000000 */
/*0370*/ FADD R23, R8, R12 ; /* 0x0000000c08177221 */
/* 0x000fe40000000000 */
/*0380*/ FADD R25, R6, R14 ; /* 0x0000000e06197221 */
/* 0x000fe40000000000 */
/*0390*/ FFMA R11, R11, 0.10000000149011611938, R16 ; /* 0x3dcccccd0b0b7823 */
/* 0x000fe40000000010 */
/*03a0*/ FFMA R27, R10, 0.10000000149011611938, R7 ; /* 0x3dcccccd0a1b7823 */
/* 0x000fe20000000007 */
/*03b0*/ STG.E [R4.64+-0x10], R15 ; /* 0xfffff00f04007986 */
/* 0x000fe8000c101908 */
/*03c0*/ STG.E [R4.64+-0xc], R17 ; /* 0xfffff41104007986 */
/* 0x000fe8000c101908 */
/*03d0*/ STG.E [R4.64+-0x8], R19 ; /* 0xfffff81304007986 */
/* 0x000fe8000c101908 */
/*03e0*/ STG.E [R4.64+-0x4], R9 ; /* 0xfffffc0904007986 */
/* 0x000fe8000c101908 */
/*03f0*/ STG.E [R4.64], R21 ; /* 0x0000001504007986 */
/* 0x000fe8000c101908 */
/*0400*/ STG.E [R4.64+0x4], R23 ; /* 0x0000041704007986 */
/* 0x000fe8000c101908 */
/*0410*/ STG.E [R4.64+0x8], R25 ; /* 0x0000081904007986 */
/* 0x000fe8000c101908 */
/*0420*/ STG.E [R4.64+0xc], R11 ; /* 0x00000c0b04007986 */
/* 0x000fe8000c101908 */
/*0430*/ STG.E [R4.64+0x10], R27 ; /* 0x0000101b04007986 */
/* 0x000fe2000c101908 */
/*0440*/ IADD3 R10, P1, R2, 0x28, RZ ; /* 0x00000028020a7810 */
/* 0x000fc40007f3e0ff */
/*0450*/ IADD3 R7, P2, R4, 0x28, RZ ; /* 0x0000002804077810 */
/* 0x000fe20007f5e0ff */
/*0460*/ STG.E [R4.64+-0x14], R13 ; /* 0xffffec0d04007986 */
/* 0x0001e2000c101908 */
/*0470*/ MOV R6, 0x1 ; /* 0x0000000100067802 */
/* 0x000fe40000000f00 */
/*0480*/ IADD3.X R8, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff087210 */
/* 0x000fe400017fe4ff */
/*0490*/ IADD3.X R13, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff0d7210 */
/* 0x001fe40000ffe4ff */
/*04a0*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fe40000000f00 */
/*04b0*/ MOV R5, R13 ; /* 0x0000000d00057202 */
/* 0x000fca0000000f00 */
/*04c0*/ LDG.E R2, [R4.64+0x10] ; /* 0x0000100804027981 */
/* 0x002ea8000c1e1900 */
/*04d0*/ LDG.E R3, [R4.64+-0x14] ; /* 0xffffec0804037981 */
/* 0x000ee8000c1e1900 */
/*04e0*/ LDG.E R15, [R4.64+-0x10] ; /* 0xfffff008040f7981 */
/* 0x000f28000c1e1900 */
/*04f0*/ LDG.E R17, [R4.64+-0xc] ; /* 0xfffff40804117981 */
/* 0x000f68000c1e1900 */
/*0500*/ LDG.E R19, [R4.64+-0x8] ; /* 0xfffff80804137981 */
/* 0x000f68000c1e1900 */
/*0510*/ LDG.E R21, [R4.64+-0x4] ; /* 0xfffffc0804157981 */
/* 0x000f68000c1e1900 */
/*0520*/ LDG.E R12, [R4.64] ; /* 0x00000008040c7981 */
/* 0x000f68000c1e1900 */
/*0530*/ LDG.E R9, [R4.64+0x4] ; /* 0x0000040804097981 */
/* 0x000f68000c1e1900 */
/*0540*/ LDG.E R10, [R4.64+0x8] ; /* 0x00000808040a7981 */
/* 0x000f68000c1e1900 */
/*0550*/ LDG.E R11, [R4.64+0xc] ; /* 0x00000c08040b7981 */
/* 0x000f62000c1e1900 */
/*0560*/ FMUL R14, R2, 0.10000000149011611938 ; /* 0x3dcccccd020e7820 */
/* 0x004fc40000400000 */
/*0570*/ FMUL R18, R3.reuse, 0.10000000149011611938 ; /* 0x3dcccccd03127820 */
/* 0x048fe40000400000 */
/*0580*/ FFMA R13, R3, 0.80000001192092895508, R14 ; /* 0x3f4ccccd030d7823 */
/* 0x000fe4000000000e */
/*0590*/ FMUL R16, R15.reuse, 0.10000000149011611938 ; /* 0x3dcccccd0f107820 */
/* 0x050fe40000400000 */
/*05a0*/ FFMA R15, R15, 0.80000001192092895508, R18 ; /* 0x3f4ccccd0f0f7823 */
/* 0x000fe40000000012 */
/*05b0*/ FMUL R14, R17, 0.10000000149011611938 ; /* 0x3dcccccd110e7820 */
/* 0x020fe40000400000 */
/*05c0*/ FADD R13, R13, R16 ; /* 0x000000100d0d7221 */
/* 0x000fc40000000000 */
/*05d0*/ FFMA R17, R17, 0.80000001192092895508, R16 ; /* 0x3f4ccccd11117823 */
/* 0x000fe40000000010 */
/*05e0*/ FMUL R16, R19, 0.10000000149011611938 ; /* 0x3dcccccd13107820 */
/* 0x000fe40000400000 */
/*05f0*/ FADD R15, R15, R14.reuse ; /* 0x0000000e0f0f7221 */
/* 0x100fe40000000000 */
/*0600*/ FFMA R19, R19, 0.80000001192092895508, R14 ; /* 0x3f4ccccd13137823 */
/* 0x000fe4000000000e */
/*0610*/ FMUL R14, R21, 0.10000000149011611938 ; /* 0x3dcccccd150e7820 */
/* 0x000fe40000400000 */
/*0620*/ FADD R17, R17, R16 ; /* 0x0000001011117221 */
/* 0x000fc40000000000 */
/*0630*/ FFMA R21, R21, 0.80000001192092895508, R16 ; /* 0x3f4ccccd15157823 */
/* 0x000fe40000000010 */
/*0640*/ FMUL R16, R12.reuse, 0.10000000149011611938 ; /* 0x3dcccccd0c107820 */
/* 0x040fe40000400000 */
/*0650*/ FADD R19, R19, R14.reuse ; /* 0x0000000e13137221 */
/* 0x100fe40000000000 */
/*0660*/ FFMA R12, R12, 0.80000001192092895508, R14 ; /* 0x3f4ccccd0c0c7823 */
/* 0x000fe4000000000e */
/*0670*/ FMUL R23, R9, 0.10000000149011611938 ; /* 0x3dcccccd09177820 */
/* 0x000fe40000400000 */
/*0680*/ FMUL R14, R10, 0.10000000149011611938 ; /* 0x3dcccccd0a0e7820 */
/* 0x000fc40000400000 */
/*0690*/ FMUL R25, R11, 0.10000000149011611938 ; /* 0x3dcccccd0b197820 */
/* 0x000fe40000400000 */
/*06a0*/ FADD R21, R21, R16.reuse ; /* 0x0000001015157221 */
/* 0x100fe40000000000 */
/*06b0*/ FFMA R16, R9, 0.80000001192092895508, R16 ; /* 0x3f4ccccd09107823 */
/* 0x000fe40000000010 */
/*06c0*/ FADD R9, R12, R23.reuse ; /* 0x000000170c097221 */
/* 0x100fe40000000000 */
/*06d0*/ FFMA R10, R10, 0.80000001192092895508, R23 ; /* 0x3f4ccccd0a0a7823 */
/* 0x000fe40000000017 */
/*06e0*/ FFMA R23, R11, 0.80000001192092895508, R14 ; /* 0x3f4ccccd0b177823 */
/* 0x000fc4000000000e */
/*06f0*/ FFMA R12, R2.reuse, 0.80000001192092895508, R25 ; /* 0x3f4ccccd020c7823 */
/* 0x040fe40000000019 */
/*0700*/ FFMA R23, R2, 0.10000000149011611938, R23 ; /* 0x3dcccccd02177823 */
/* 0x000fe20000000017 */
/*0710*/ MOV R2, R7 ; /* 0x0000000700027202 */
/* 0x000fe20000000f00 */
/*0720*/ FFMA R27, R3, 0.10000000149011611938, R12 ; /* 0x3dcccccd031b7823 */
/* 0x000fe2000000000c */
/*0730*/ MOV R3, R8 ; /* 0x0000000800037202 */
/* 0x000fe20000000f00 */
/*0740*/ FADD R11, R16, R14 ; /* 0x0000000e100b7221 */
/* 0x000fe40000000000 */
/*0750*/ FADD R25, R10, R25 ; /* 0x000000190a197221 */
/* 0x000fe40000000000 */
/*0760*/ STG.E [R2.64+-0x14], R13 ; /* 0xffffec0d02007986 */
/* 0x000fe8000c101908 */
/*0770*/ STG.E [R2.64+-0x10], R15 ; /* 0xfffff00f02007986 */
/* 0x000fe8000c101908 */
/*0780*/ STG.E [R2.64+-0xc], R17 ; /* 0xfffff41102007986 */
/* 0x0001e8000c101908 */
/*0790*/ STG.E [R2.64+-0x8], R19 ; /* 0xfffff81302007986 */
/* 0x0003e8000c101908 */
/*07a0*/ STG.E [R2.64+-0x4], R21 ; /* 0xfffffc1502007986 */
/* 0x0005e8000c101908 */
/*07b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0007e8000c101908 */
/*07c0*/ STG.E [R2.64+0x4], R11 ; /* 0x0000040b02007986 */
/* 0x0009e8000c101908 */
/*07d0*/ STG.E [R2.64+0x8], R25 ; /* 0x0000081902007986 */
/* 0x000fe8000c101908 */
/*07e0*/ STG.E [R2.64+0xc], R23 ; /* 0x00000c1702007986 */
/* 0x000be8000c101908 */
/*07f0*/ STG.E [R2.64+0x10], R27 ; /* 0x0000101b02007986 */
/* 0x0001e8000c101908 */
/*0800*/ LDG.E R7, [R4.64+0x38] ; /* 0x0000380804077981 */
/* 0x000f68000c1e1900 */
/*0810*/ LDG.E R8, [R4.64+0x14] ; /* 0x0000140804087981 */
/* 0x000f68000c1e1900 */
/*0820*/ LDG.E R14, [R4.64+0x18] ; /* 0x00001808040e7981 */
/* 0x000f68000c1e1900 */
/*0830*/ LDG.E R17, [R4.64+0x1c] ; /* 0x00001c0804117981 */
/* 0x001f68000c1e1900 */
/*0840*/ LDG.E R19, [R4.64+0x20] ; /* 0x0000200804137981 */
/* 0x002f68000c1e1900 */
/*0850*/ LDG.E R21, [R4.64+0x24] ; /* 0x0000240804157981 */
/* 0x004ea8000c1e1900 */
/*0860*/ LDG.E R12, [R4.64+0x28] ; /* 0x00002808040c7981 */
/* 0x000ea8000c1e1900 */
/*0870*/ LDG.E R9, [R4.64+0x2c] ; /* 0x00002c0804097981 */
/* 0x008ee8000c1e1900 */
/*0880*/ LDG.E R10, [R4.64+0x30] ; /* 0x00003008040a7981 */
/* 0x000ee8000c1e1900 */
/*0890*/ LDG.E R11, [R4.64+0x34] ; /* 0x00003408040b7981 */
/* 0x010f22000c1e1900 */
/*08a0*/ FMUL R13, R7, 0.10000000149011611938 ; /* 0x3dcccccd070d7820 */
/* 0x020fc40000400000 */
/*08b0*/ FMUL R15, R8.reuse, 0.10000000149011611938 ; /* 0x3dcccccd080f7820 */
/* 0x040fe40000400000 */
/*08c0*/ FFMA R13, R8, 0.80000001192092895508, R13 ; /* 0x3f4ccccd080d7823 */
/* 0x000fe4000000000d */
/*08d0*/ FMUL R16, R14.reuse, 0.10000000149011611938 ; /* 0x3dcccccd0e107820 */
/* 0x040fe40000400000 */
/*08e0*/ FFMA R15, R14, 0.80000001192092895508, R15 ; /* 0x3f4ccccd0e0f7823 */
/* 0x000fe4000000000f */
/*08f0*/ FMUL R14, R17, 0.10000000149011611938 ; /* 0x3dcccccd110e7820 */
/* 0x000fe40000400000 */
/*0900*/ FADD R13, R13, R16 ; /* 0x000000100d0d7221 */
/* 0x000fc40000000000 */
/*0910*/ FFMA R17, R17, 0.80000001192092895508, R16 ; /* 0x3f4ccccd11117823 */
/* 0x000fe40000000010 */
/*0920*/ FMUL R16, R19, 0.10000000149011611938 ; /* 0x3dcccccd13107820 */
/* 0x000fe20000400000 */
/*0930*/ STG.E [R2.64+0x14], R13 ; /* 0x0000140d02007986 */
/* 0x000fe2000c101908 */
/*0940*/ FADD R15, R15, R14.reuse ; /* 0x0000000e0f0f7221 */
/* 0x100fe40000000000 */
/*0950*/ FFMA R19, R19, 0.80000001192092895508, R14 ; /* 0x3f4ccccd13137823 */
/* 0x000fe4000000000e */
/*0960*/ FMUL R14, R21, 0.10000000149011611938 ; /* 0x3dcccccd150e7820 */
/* 0x004fe20000400000 */
/*0970*/ STG.E [R2.64+0x18], R15 ; /* 0x0000180f02007986 */
/* 0x000fe2000c101908 */
/*0980*/ FADD R17, R17, R16 ; /* 0x0000001011117221 */
/* 0x000fc40000000000 */
/*0990*/ FFMA R21, R21, 0.80000001192092895508, R16 ; /* 0x3f4ccccd15157823 */
/* 0x000fe40000000010 */
/*09a0*/ FMUL R16, R12.reuse, 0.10000000149011611938 ; /* 0x3dcccccd0c107820 */
/* 0x040fe20000400000 */
/*09b0*/ STG.E [R2.64+0x1c], R17 ; /* 0x00001c1102007986 */
/* 0x0001e2000c101908 */
/*09c0*/ FADD R19, R19, R14.reuse ; /* 0x0000000e13137221 */
/* 0x100fe40000000000 */
/*09d0*/ FFMA R12, R12, 0.80000001192092895508, R14 ; /* 0x3f4ccccd0c0c7823 */
/* 0x000fe4000000000e */
/*09e0*/ FMUL R23, R9, 0.10000000149011611938 ; /* 0x3dcccccd09177820 */
/* 0x008fe20000400000 */
/*09f0*/ STG.E [R2.64+0x20], R19 ; /* 0x0000201302007986 */
/* 0x0003e2000c101908 */
/*0a00*/ FMUL R14, R10, 0.10000000149011611938 ; /* 0x3dcccccd0a0e7820 */
/* 0x000fc40000400000 */
/*0a10*/ FMUL R18, R11, 0.10000000149011611938 ; /* 0x3dcccccd0b127820 */
/* 0x010fe40000400000 */
/*0a20*/ FADD R21, R21, R16.reuse ; /* 0x0000001015157221 */
/* 0x100fe40000000000 */
/*0a30*/ FFMA R16, R9, 0.80000001192092895508, R16 ; /* 0x3f4ccccd09107823 */
/* 0x000fe40000000010 */
/*0a40*/ FADD R9, R12, R23.reuse ; /* 0x000000170c097221 */
/* 0x100fe20000000000 */
/*0a50*/ STG.E [R2.64+0x24], R21 ; /* 0x0000241502007986 */
/* 0x0005e2000c101908 */
/*0a60*/ FFMA R10, R10, 0.80000001192092895508, R23 ; /* 0x3f4ccccd0a0a7823 */
/* 0x000fe40000000017 */
/*0a70*/ FFMA R12, R11, 0.80000001192092895508, R14 ; /* 0x3f4ccccd0b0c7823 */
/* 0x000fe2000000000e */
/*0a80*/ STG.E [R2.64+0x28], R9 ; /* 0x0000280902007986 */
/* 0x0007e2000c101908 */
/*0a90*/ FFMA R27, R7, 0.80000001192092895508, R18 ; /* 0x3f4ccccd071b7823 */
/* 0x000fc40000000012 */
/*0aa0*/ FADD R11, R16, R14 ; /* 0x0000000e100b7221 */
/* 0x000fe40000000000 */
/*0ab0*/ FADD R23, R10, R18 ; /* 0x000000120a177221 */
/* 0x000fe40000000000 */
/*0ac0*/ FFMA R25, R7, 0.10000000149011611938, R12 ; /* 0x3dcccccd07197823 */
/* 0x000fe2000000000c */
/*0ad0*/ STG.E [R2.64+0x2c], R11 ; /* 0x00002c0b02007986 */
/* 0x0009e2000c101908 */
/*0ae0*/ FFMA R27, R8, 0.10000000149011611938, R27 ; /* 0x3dcccccd081b7823 */
/* 0x000fc6000000001b */
/*0af0*/ STG.E [R2.64+0x30], R23 ; /* 0x0000301702007986 */
/* 0x000be8000c101908 */
/*0b00*/ STG.E [R2.64+0x34], R25 ; /* 0x0000341902007986 */
/* 0x000fe8000c101908 */
/*0b10*/ STG.E [R2.64+0x38], R27 ; /* 0x0000381b02007986 */
/* 0x0001e8000c101908 */
/*0b20*/ LDG.E R7, [R4.64+0x60] ; /* 0x0000600804077981 */
/* 0x000f68000c1e1900 */
/*0b30*/ LDG.E R8, [R4.64+0x3c] ; /* 0x00003c0804087981 */
/* 0x000f68000c1e1900 */
/*0b40*/ LDG.E R14, [R4.64+0x40] ; /* 0x00004008040e7981 */
/* 0x000f68000c1e1900 */
/*0b50*/ LDG.E R17, [R4.64+0x44] ; /* 0x0000440804117981 */
/* 0x001f68000c1e1900 */
/*0b60*/ LDG.E R19, [R4.64+0x48] ; /* 0x0000480804137981 */
/* 0x002f68000c1e1900 */
/*0b70*/ LDG.E R21, [R4.64+0x4c] ; /* 0x00004c0804157981 */
/* 0x004ea8000c1e1900 */
/*0b80*/ LDG.E R12, [R4.64+0x50] ; /* 0x00005008040c7981 */
/* 0x000ea8000c1e1900 */
/*0b90*/ LDG.E R9, [R4.64+0x54] ; /* 0x0000540804097981 */
/* 0x008ee8000c1e1900 */
/*0ba0*/ LDG.E R10, [R4.64+0x58] ; /* 0x00005808040a7981 */
/* 0x000ee8000c1e1900 */
/*0bb0*/ LDG.E R11, [R4.64+0x5c] ; /* 0x00005c08040b7981 */
/* 0x010f22000c1e1900 */
/*0bc0*/ IADD3 R6, R6, 0x3, RZ ; /* 0x0000000306067810 */
/* 0x000fc80007ffe0ff */
/*0bd0*/ ISETP.NE.AND P1, PT, R6, 0x7, PT ; /* 0x000000070600780c */
/* 0x000fe20003f25270 */
/*0be0*/ FMUL R13, R7, 0.10000000149011611938 ; /* 0x3dcccccd070d7820 */
/* 0x020fe40000400000 */
/*0bf0*/ FMUL R15, R8.reuse, 0.10000000149011611938 ; /* 0x3dcccccd080f7820 */
/* 0x040fe40000400000 */
/*0c00*/ FFMA R13, R8, 0.80000001192092895508, R13 ; /* 0x3f4ccccd080d7823 */
/* 0x000fe4000000000d */
/*0c10*/ FMUL R16, R14.reuse, 0.10000000149011611938 ; /* 0x3dcccccd0e107820 */
/* 0x040fe40000400000 */
/*0c20*/ FFMA R15, R14, 0.80000001192092895508, R15 ; /* 0x3f4ccccd0e0f7823 */
/* 0x000fe4000000000f */
/*0c30*/ FMUL R14, R17, 0.10000000149011611938 ; /* 0x3dcccccd110e7820 */
/* 0x000fc40000400000 */
/*0c40*/ FADD R13, R13, R16.reuse ; /* 0x000000100d0d7221 */
/* 0x100fe40000000000 */
/*0c50*/ FFMA R17, R17, 0.80000001192092895508, R16 ; /* 0x3f4ccccd11117823 */
/* 0x000fe40000000010 */
/*0c60*/ FMUL R16, R19, 0.10000000149011611938 ; /* 0x3dcccccd13107820 */
/* 0x000fe20000400000 */
/*0c70*/ STG.E [R2.64+0x3c], R13 ; /* 0x00003c0d02007986 */
/* 0x0001e2000c101908 */
/*0c80*/ FADD R15, R15, R14.reuse ; /* 0x0000000e0f0f7221 */
/* 0x100fe40000000000 */
/*0c90*/ FFMA R19, R19, 0.80000001192092895508, R14 ; /* 0x3f4ccccd13137823 */
/* 0x000fe4000000000e */
/*0ca0*/ FMUL R14, R21, 0.10000000149011611938 ; /* 0x3dcccccd150e7820 */
/* 0x004fe20000400000 */
/*0cb0*/ STG.E [R2.64+0x40], R15 ; /* 0x0000400f02007986 */
/* 0x0003e2000c101908 */
/*0cc0*/ FADD R17, R17, R16 ; /* 0x0000001011117221 */
/* 0x000fc40000000000 */
/*0cd0*/ FFMA R21, R21, 0.80000001192092895508, R16 ; /* 0x3f4ccccd15157823 */
/* 0x000fe40000000010 */
/*0ce0*/ FMUL R16, R12.reuse, 0.10000000149011611938 ; /* 0x3dcccccd0c107820 */
/* 0x040fe20000400000 */
/*0cf0*/ STG.E [R2.64+0x44], R17 ; /* 0x0000441102007986 */
/* 0x0003e2000c101908 */
/*0d00*/ FADD R19, R19, R14.reuse ; /* 0x0000000e13137221 */
/* 0x100fe40000000000 */
/*0d10*/ FFMA R12, R12, 0.80000001192092895508, R14 ; /* 0x3f4ccccd0c0c7823 */
/* 0x000fe4000000000e */
/*0d20*/ FMUL R23, R9, 0.10000000149011611938 ; /* 0x3dcccccd09177820 */
/* 0x008fe20000400000 */
/*0d30*/ STG.E [R2.64+0x48], R19 ; /* 0x0000481302007986 */
/* 0x0003e2000c101908 */
/*0d40*/ FMUL R14, R10, 0.10000000149011611938 ; /* 0x3dcccccd0a0e7820 */
/* 0x000fc40000400000 */
/*0d50*/ FMUL R18, R11, 0.10000000149011611938 ; /* 0x3dcccccd0b127820 */
/* 0x010fe40000400000 */
/*0d60*/ FADD R21, R21, R16.reuse ; /* 0x0000001015157221 */
/* 0x100fe40000000000 */
/*0d70*/ FFMA R16, R9, 0.80000001192092895508, R16 ; /* 0x3f4ccccd09107823 */
/* 0x000fe40000000010 */
/*0d80*/ FADD R9, R12, R23.reuse ; /* 0x000000170c097221 */
/* 0x100fe20000000000 */
/*0d90*/ STG.E [R2.64+0x4c], R21 ; /* 0x00004c1502007986 */
/* 0x0003e2000c101908 */
/*0da0*/ FFMA R10, R10, 0.80000001192092895508, R23 ; /* 0x3f4ccccd0a0a7823 */
/* 0x000fe40000000017 */
/*0db0*/ FFMA R12, R11, 0.80000001192092895508, R14 ; /* 0x3f4ccccd0b0c7823 */
/* 0x000fe2000000000e */
/*0dc0*/ STG.E [R2.64+0x50], R9 ; /* 0x0000500902007986 */
/* 0x0003e2000c101908 */
/*0dd0*/ FFMA R27, R7, 0.80000001192092895508, R18 ; /* 0x3f4ccccd071b7823 */
/* 0x000fc40000000012 */
/*0de0*/ FADD R11, R16, R14 ; /* 0x0000000e100b7221 */
/* 0x000fe40000000000 */
/*0df0*/ FADD R23, R10, R18 ; /* 0x000000120a177221 */
/* 0x000fe20000000000 */
/*0e00*/ IADD3 R10, P2, R4, 0x78, RZ ; /* 0x00000078040a7810 */
/* 0x000fe20007f5e0ff */
/*0e10*/ FFMA R25, R7, 0.10000000149011611938, R12 ; /* 0x3dcccccd07197823 */
/* 0x000fe2000000000c */
/*0e20*/ IADD3 R7, P3, R2, 0x78, RZ ; /* 0x0000007802077810 */
/* 0x000fe20007f7e0ff */
/*0e30*/ FFMA R27, R8, 0.10000000149011611938, R27 ; /* 0x3dcccccd081b7823 */
/* 0x000fe2000000001b */
/*0e40*/ STG.E [R2.64+0x54], R11 ; /* 0x0000540b02007986 */
/* 0x0003e2000c101908 */
/*0e50*/ IADD3.X R13, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff0d7210 */
/* 0x001fe400017fe4ff */
/*0e60*/ IADD3.X R8, RZ, R3, RZ, P3, !PT ; /* 0x00000003ff087210 */
/* 0x000fe20001ffe4ff */
/*0e70*/ STG.E [R2.64+0x58], R23 ; /* 0x0000581702007986 */
/* 0x0003e8000c101908 */
/*0e80*/ STG.E [R2.64+0x5c], R25 ; /* 0x00005c1902007986 */
/* 0x0003e8000c101908 */
/*0e90*/ STG.E [R2.64+0x60], R27 ; /* 0x0000601b02007986 */
/* 0x0003e2000c101908 */
/*0ea0*/ @P1 BRA 0x4a0 ; /* 0xfffff5f000001947 */
/* 0x000fea000383ffff */
/*0eb0*/ @!P0 BRA 0xa0 ; /* 0xfffff1e000008947 */
/* 0x000fea000383ffff */
/*0ec0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ed0*/ BRA 0xed0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define L2HYS_EPSILON 0.01f
#define L2HYS_EPSILONHYS 1.0f
#define L2HYS_CLIP 0.2f
#define data_h2y 30
//long h_windowx=Imagewidth/Windowx;
//long h_windowy=ImageHeight/Windowy;
//dim3 blocks(h_windowx,h_windowy);//h_windowx=ImageWidth/Windowx,h_windowy=ImageHeight/Windowy
//dim3 threads(Windowx,Windowy);//ÿһ¸öÏ߳̿é¼ÆËãÒ»¸öcellµÄÌØÕ÷Á¿
//dim3 block(18,7);//Ò»¸öcell·Ö18¸ö½Ç¶È·½Ïò,Ò»¸ö·½Ïò7¸öcell£¬
__global__ void smooth(float *in,float *out)
{
int k,j,i;
int m_nBIN=10;
float *m_pCellFeatures=in;
int t_nLineWidth=70;
float t_pTemp[10];
for ( k = 0; k < 18; ++k )//18
{
for ( j = 0; j < 7; ++j )//7
{
for ( i = 0; i< 10; ++i )//10
{
int t_nLeft;
int t_nRight;
t_nLeft = ( i - 1 + m_nBIN ) % m_nBIN;
t_nRight = ( i + 1 ) % m_nBIN;
t_pTemp[i] = m_pCellFeatures[k * t_nLineWidth + j * m_nBIN + i] * 0.8f
+ m_pCellFeatures[k * t_nLineWidth + j * m_nBIN + t_nLeft] * 0.1f
+ m_pCellFeatures[k * t_nLineWidth + j * m_nBIN + t_nRight] * 0.1f;
}
for ( i = 0; i < m_nBIN; ++i )
{
out[k * t_nLineWidth + j * m_nBIN + i] = t_pTemp[i];
}
}
}
} | .file "tmpxft_0013e8eb_00000000-6_smooth.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6smoothPfS_PfS_
.type _Z27__device_stub__Z6smoothPfS_PfS_, @function
_Z27__device_stub__Z6smoothPfS_PfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6smoothPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z6smoothPfS_PfS_, .-_Z27__device_stub__Z6smoothPfS_PfS_
.globl _Z6smoothPfS_
.type _Z6smoothPfS_, @function
_Z6smoothPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6smoothPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6smoothPfS_, .-_Z6smoothPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6smoothPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6smoothPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define L2HYS_EPSILON 0.01f
#define L2HYS_EPSILONHYS 1.0f
#define L2HYS_CLIP 0.2f
#define data_h2y 30
//long h_windowx=Imagewidth/Windowx;
//long h_windowy=ImageHeight/Windowy;
//dim3 blocks(h_windowx,h_windowy);//h_windowx=ImageWidth/Windowx,h_windowy=ImageHeight/Windowy
//dim3 threads(Windowx,Windowy);//ÿһ¸öÏ߳̿é¼ÆËãÒ»¸öcellµÄÌØÕ÷Á¿
//dim3 block(18,7);//Ò»¸öcell·Ö18¸ö½Ç¶È·½Ïò,Ò»¸ö·½Ïò7¸öcell£¬
__global__ void smooth(float *in,float *out)
{
int k,j,i;
int m_nBIN=10;
float *m_pCellFeatures=in;
int t_nLineWidth=70;
float t_pTemp[10];
for ( k = 0; k < 18; ++k )//18
{
for ( j = 0; j < 7; ++j )//7
{
for ( i = 0; i< 10; ++i )//10
{
int t_nLeft;
int t_nRight;
t_nLeft = ( i - 1 + m_nBIN ) % m_nBIN;
t_nRight = ( i + 1 ) % m_nBIN;
t_pTemp[i] = m_pCellFeatures[k * t_nLineWidth + j * m_nBIN + i] * 0.8f
+ m_pCellFeatures[k * t_nLineWidth + j * m_nBIN + t_nLeft] * 0.1f
+ m_pCellFeatures[k * t_nLineWidth + j * m_nBIN + t_nRight] * 0.1f;
}
for ( i = 0; i < m_nBIN; ++i )
{
out[k * t_nLineWidth + j * m_nBIN + i] = t_pTemp[i];
}
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define L2HYS_EPSILON 0.01f
#define L2HYS_EPSILONHYS 1.0f
#define L2HYS_CLIP 0.2f
#define data_h2y 30
//long h_windowx=Imagewidth/Windowx;
//long h_windowy=ImageHeight/Windowy;
//dim3 blocks(h_windowx,h_windowy);//h_windowx=ImageWidth/Windowx,h_windowy=ImageHeight/Windowy
//dim3 threads(Windowx,Windowy);//ÿһ¸öÏ߳̿é¼ÆËãÒ»¸öcellµÄÌØÕ÷Á¿
//dim3 block(18,7);//Ò»¸öcell·Ö18¸ö½Ç¶È·½Ïò,Ò»¸ö·½Ïò7¸öcell£¬
__global__ void smooth(float *in,float *out)
{
int k,j,i;
int m_nBIN=10;
float *m_pCellFeatures=in;
int t_nLineWidth=70;
float t_pTemp[10];
for ( k = 0; k < 18; ++k )//18
{
for ( j = 0; j < 7; ++j )//7
{
for ( i = 0; i< 10; ++i )//10
{
int t_nLeft;
int t_nRight;
t_nLeft = ( i - 1 + m_nBIN ) % m_nBIN;
t_nRight = ( i + 1 ) % m_nBIN;
t_pTemp[i] = m_pCellFeatures[k * t_nLineWidth + j * m_nBIN + i] * 0.8f
+ m_pCellFeatures[k * t_nLineWidth + j * m_nBIN + t_nLeft] * 0.1f
+ m_pCellFeatures[k * t_nLineWidth + j * m_nBIN + t_nRight] * 0.1f;
}
for ( i = 0; i < m_nBIN; ++i )
{
out[k * t_nLineWidth + j * m_nBIN + i] = t_pTemp[i];
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define L2HYS_EPSILON 0.01f
#define L2HYS_EPSILONHYS 1.0f
#define L2HYS_CLIP 0.2f
#define data_h2y 30
//long h_windowx=Imagewidth/Windowx;
//long h_windowy=ImageHeight/Windowy;
//dim3 blocks(h_windowx,h_windowy);//h_windowx=ImageWidth/Windowx,h_windowy=ImageHeight/Windowy
//dim3 threads(Windowx,Windowy);//ÿһ¸öÏ߳̿é¼ÆËãÒ»¸öcellµÄÌØÕ÷Á¿
//dim3 block(18,7);//Ò»¸öcell·Ö18¸ö½Ç¶È·½Ïò,Ò»¸ö·½Ïò7¸öcell£¬
__global__ void smooth(float *in,float *out)
{
int k,j,i;
int m_nBIN=10;
float *m_pCellFeatures=in;
int t_nLineWidth=70;
float t_pTemp[10];
for ( k = 0; k < 18; ++k )//18
{
for ( j = 0; j < 7; ++j )//7
{
for ( i = 0; i< 10; ++i )//10
{
int t_nLeft;
int t_nRight;
t_nLeft = ( i - 1 + m_nBIN ) % m_nBIN;
t_nRight = ( i + 1 ) % m_nBIN;
t_pTemp[i] = m_pCellFeatures[k * t_nLineWidth + j * m_nBIN + i] * 0.8f
+ m_pCellFeatures[k * t_nLineWidth + j * m_nBIN + t_nLeft] * 0.1f
+ m_pCellFeatures[k * t_nLineWidth + j * m_nBIN + t_nRight] * 0.1f;
}
for ( i = 0; i < m_nBIN; ++i )
{
out[k * t_nLineWidth + j * m_nBIN + i] = t_pTemp[i];
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6smoothPfS_
.globl _Z6smoothPfS_
.p2align 8
.type _Z6smoothPfS_,@function
_Z6smoothPfS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v10, 0
s_mov_b32 s5, 0
s_mov_b32 s16, 9
s_mov_b32 s17, 0
s_waitcnt lgkmcnt(0)
s_mov_b64 s[6:7], s[0:1]
.LBB0_1:
s_mul_i32 s18, s17, 0x46
s_mov_b64 s[8:9], s[2:3]
s_mov_b32 s19, s16
s_mov_b64 s[10:11], s[6:7]
s_mov_b32 s20, s5
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s21, s20, 10
s_mov_b64 s[12:13], 0
s_add_i32 s21, s21, s18
s_mov_b32 s22, 9
s_mov_b64 s[14:15], s[10:11]
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_3:
s_mul_hi_u32 s4, s22, 0xcccccccd
s_mov_b32 m0, s12
s_lshr_b32 s4, s4, 3
global_load_b32 v12, v10, s[14:15]
s_mul_i32 s4, s4, 10
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s4, s19, s4
s_add_u32 s24, s12, 1
s_addc_u32 s25, s13, 0
s_cmp_lg_u32 s12, 9
s_cselect_b32 s13, s24, 0
s_add_i32 s4, s12, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[26:27], s[4:5], 2
s_add_u32 s26, s0, s26
s_addc_u32 s27, s1, s27
s_add_i32 s4, s13, s21
global_load_b32 v11, v10, s[26:27]
s_lshl_b64 s[26:27], s[4:5], 2
s_mov_b64 s[12:13], s[24:25]
s_add_u32 s26, s0, s26
s_addc_u32 s27, s1, s27
s_add_u32 s14, s14, 4
global_load_b32 v13, v10, s[26:27]
s_addc_u32 s15, s15, 0
s_add_i32 s22, s22, 1
s_cmp_eq_u32 s24, 10
s_waitcnt vmcnt(1)
v_mul_f32_e32 v11, 0x3dcccccd, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v11, 0x3f4ccccd, v12
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v11, 0x3dcccccd, v13
s_delay_alu instid0(VALU_DEP_1)
v_movreld_b32_e32 v0, v11
s_cbranch_scc0 .LBB0_3
s_set_inst_prefetch_distance 0x2
s_mov_b64 s[12:13], 0
s_mov_b64 s[14:15], s[8:9]
.LBB0_5:
s_mov_b32 m0, s12
s_add_u32 s12, s12, 1
v_movrels_b32_e32 v11, v0
s_addc_u32 s13, s13, 0
global_store_b32 v10, v11, s[14:15]
s_add_u32 s14, s14, 4
s_addc_u32 s15, s15, 0
s_cmp_lg_u32 s12, 10
s_cbranch_scc1 .LBB0_5
s_add_i32 s20, s20, 1
s_add_u32 s10, s10, 40
s_addc_u32 s11, s11, 0
s_add_i32 s19, s19, 10
s_add_u32 s8, s8, 40
s_addc_u32 s9, s9, 0
s_cmp_lg_u32 s20, 7
s_cbranch_scc1 .LBB0_2
s_add_i32 s17, s17, 1
s_add_u32 s6, s6, 0x118
s_addc_u32 s7, s7, 0
s_addk_i32 s16, 0x46
s_add_u32 s2, s2, 0x118
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s17, 18
s_cbranch_scc1 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6smoothPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 28
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6smoothPfS_, .Lfunc_end0-_Z6smoothPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6smoothPfS_
.private_segment_fixed_size: 0
.sgpr_count: 28
.sgpr_spill_count: 0
.symbol: _Z6smoothPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define L2HYS_EPSILON 0.01f
#define L2HYS_EPSILONHYS 1.0f
#define L2HYS_CLIP 0.2f
#define data_h2y 30
//long h_windowx=Imagewidth/Windowx;
//long h_windowy=ImageHeight/Windowy;
//dim3 blocks(h_windowx,h_windowy);//h_windowx=ImageWidth/Windowx,h_windowy=ImageHeight/Windowy
//dim3 threads(Windowx,Windowy);//ÿһ¸öÏ߳̿é¼ÆËãÒ»¸öcellµÄÌØÕ÷Á¿
//dim3 block(18,7);//Ò»¸öcell·Ö18¸ö½Ç¶È·½Ïò,Ò»¸ö·½Ïò7¸öcell£¬
__global__ void smooth(float *in,float *out)
{
int k,j,i;
int m_nBIN=10;
float *m_pCellFeatures=in;
int t_nLineWidth=70;
float t_pTemp[10];
for ( k = 0; k < 18; ++k )//18
{
for ( j = 0; j < 7; ++j )//7
{
for ( i = 0; i< 10; ++i )//10
{
int t_nLeft;
int t_nRight;
t_nLeft = ( i - 1 + m_nBIN ) % m_nBIN;
t_nRight = ( i + 1 ) % m_nBIN;
t_pTemp[i] = m_pCellFeatures[k * t_nLineWidth + j * m_nBIN + i] * 0.8f
+ m_pCellFeatures[k * t_nLineWidth + j * m_nBIN + t_nLeft] * 0.1f
+ m_pCellFeatures[k * t_nLineWidth + j * m_nBIN + t_nRight] * 0.1f;
}
for ( i = 0; i < m_nBIN; ++i )
{
out[k * t_nLineWidth + j * m_nBIN + i] = t_pTemp[i];
}
}
}
} | .text
.file "smooth.hip"
.globl _Z21__device_stub__smoothPfS_ # -- Begin function _Z21__device_stub__smoothPfS_
.p2align 4, 0x90
.type _Z21__device_stub__smoothPfS_,@function
_Z21__device_stub__smoothPfS_: # @_Z21__device_stub__smoothPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6smoothPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__smoothPfS_, .Lfunc_end0-_Z21__device_stub__smoothPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6smoothPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6smoothPfS_,@object # @_Z6smoothPfS_
.section .rodata,"a",@progbits
.globl _Z6smoothPfS_
.p2align 3, 0x0
_Z6smoothPfS_:
.quad _Z21__device_stub__smoothPfS_
.size _Z6smoothPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6smoothPfS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__smoothPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6smoothPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6smoothPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ UMOV UR4, 0x14 ; /* 0x0000001400047882 */
/* 0x000fe20000000000 */
/*0020*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ ULDC.64 UR8, c[0x0][0x168] ; /* 0x00005a0000087ab9 */
/* 0x000fe40000000a00 */
/*0050*/ UIADD3 UR6, UP0, UR4, UR6, URZ ; /* 0x0000000604067290 */
/* 0x000fe4000ff1e03f */
/*0060*/ UIADD3 UR4, UP1, UR4, UR8, URZ ; /* 0x0000000804047290 */
/* 0x000fe4000ff3e03f */
/*0070*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fc400087fe43f */
/*0080*/ UIADD3.X UR5, URZ, UR9, URZ, UP1, !UPT ; /* 0x000000093f057290 */
/* 0x000fc60008ffe43f */
/*0090*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe40000000a00 */
/*00a0*/ MOV R2, UR6 ; /* 0x0000000600027c02 */
/* 0x002fe20008000f00 */
/*00b0*/ IMAD R13, R0, 0x46, RZ ; /* 0x00000046000d7824 */
/* 0x000fe200078e02ff */
/*00c0*/ MOV R3, UR7 ; /* 0x0000000700037c02 */
/* 0x000fca0008000f00 */
/*00d0*/ IMAD.WIDE R2, R13, 0x4, R2 ; /* 0x000000040d027825 */
/* 0x000fca00078e0202 */
/*00e0*/ LDG.E R11, [R2.64+0x10] ; /* 0x00001008020b7981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ LDG.E R10, [R2.64+-0x14] ; /* 0xffffec08020a7981 */
/* 0x000ee8000c1e1900 */
/*0100*/ LDG.E R14, [R2.64+-0x10] ; /* 0xfffff008020e7981 */
/* 0x000f28000c1e1900 */
/*0110*/ LDG.E R19, [R2.64+-0xc] ; /* 0xfffff40802137981 */
/* 0x000f68000c1e1900 */
/*0120*/ LDG.E R21, [R2.64+-0x8] ; /* 0xfffff80802157981 */
/* 0x000f68000c1e1900 */
/*0130*/ LDG.E R12, [R2.64+-0x4] ; /* 0xfffffc08020c7981 */
/* 0x000f68000c1e1900 */
/*0140*/ LDG.E R9, [R2.64] ; /* 0x0000000802097981 */
/* 0x000f68000c1e1900 */
/*0150*/ LDG.E R6, [R2.64+0x8] ; /* 0x0000080802067981 */
/* 0x000f68000c1e1900 */
/*0160*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040802087981 */
/* 0x000f68000c1e1900 */
/*0170*/ LDG.E R7, [R2.64+0xc] ; /* 0x00000c0802077981 */
/* 0x000f62000c1e1900 */
/*0180*/ MOV R4, UR4 ; /* 0x0000000400047c02 */
/* 0x000fc40008000f00 */
/*0190*/ MOV R5, UR5 ; /* 0x0000000500057c02 */
/* 0x000fca0008000f00 */
/*01a0*/ IMAD.WIDE R4, R13, 0x4, R4 ; /* 0x000000040d047825 */
/* 0x000fe200078e0204 */
/*01b0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fc80007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P0, PT, R0, 0x12, PT ; /* 0x000000120000780c */
/* 0x000fe20003f06070 */
/*01d0*/ FMUL R15, R11, 0.10000000149011611938 ; /* 0x3dcccccd0b0f7820 */
/* 0x004fe40000400000 */
/*01e0*/ FMUL R17, R10.reuse, 0.10000000149011611938 ; /* 0x3dcccccd0a117820 */
/* 0x048fe40000400000 */
/*01f0*/ FFMA R15, R10, 0.80000001192092895508, R15 ; /* 0x3f4ccccd0a0f7823 */
/* 0x000fe4000000000f */
/*0200*/ FMUL R16, R14.reuse, 0.10000000149011611938 ; /* 0x3dcccccd0e107820 */
/* 0x050fe40000400000 */
/*0210*/ FFMA R17, R14, 0.80000001192092895508, R17 ; /* 0x3f4ccccd0e117823 */
/* 0x000fe40000000011 */
/*0220*/ FMUL R14, R19, 0.10000000149011611938 ; /* 0x3dcccccd130e7820 */
/* 0x020fc40000400000 */
/*0230*/ FADD R13, R15, R16.reuse ; /* 0x000000100f0d7221 */
/* 0x100fe40000000000 */
/*0240*/ FFMA R16, R19, 0.80000001192092895508, R16 ; /* 0x3f4ccccd13107823 */
/* 0x000fe40000000010 */
/*0250*/ FMUL R19, R21, 0.10000000149011611938 ; /* 0x3dcccccd15137820 */
/* 0x000fe40000400000 */
/*0260*/ FADD R15, R17, R14.reuse ; /* 0x0000000e110f7221 */
/* 0x100fe40000000000 */
/*0270*/ FFMA R14, R21, 0.80000001192092895508, R14 ; /* 0x3f4ccccd150e7823 */
/* 0x000fe4000000000e */
/*0280*/ FMUL R18, R12, 0.10000000149011611938 ; /* 0x3dcccccd0c127820 */
/* 0x000fc40000400000 */
/*0290*/ FFMA R12, R12, 0.80000001192092895508, R19.reuse ; /* 0x3f4ccccd0c0c7823 */
/* 0x100fe40000000013 */
/*02a0*/ FMUL R21, R9.reuse, 0.10000000149011611938 ; /* 0x3dcccccd09157820 */
/* 0x040fe40000400000 */
/*02b0*/ FADD R17, R16, R19 ; /* 0x0000001310117221 */
/* 0x000fe40000000000 */
/*02c0*/ FADD R19, R14, R18.reuse ; /* 0x000000120e137221 */
/* 0x100fe40000000000 */
/*02d0*/ FFMA R18, R9, 0.80000001192092895508, R18 ; /* 0x3f4ccccd09127823 */
/* 0x000fe40000000012 */
/*02e0*/ FADD R9, R12, R21 ; /* 0x000000150c097221 */
/* 0x000fc40000000000 */
/*02f0*/ FMUL R12, R6, 0.10000000149011611938 ; /* 0x3dcccccd060c7820 */
/* 0x000fe40000400000 */
/*0300*/ FMUL R23, R8.reuse, 0.10000000149011611938 ; /* 0x3dcccccd08177820 */
/* 0x040fe40000400000 */
/*0310*/ FMUL R14, R7.reuse, 0.10000000149011611938 ; /* 0x3dcccccd070e7820 */
/* 0x040fe40000400000 */
/*0320*/ FFMA R16, R7, 0.80000001192092895508, R12 ; /* 0x3f4ccccd07107823 */
/* 0x000fe4000000000c */
/*0330*/ FFMA R8, R8, 0.80000001192092895508, R21 ; /* 0x3f4ccccd08087823 */
/* 0x000fe40000000015 */
/*0340*/ FFMA R6, R6, 0.80000001192092895508, R23 ; /* 0x3f4ccccd06067823 */
/* 0x000fc40000000017 */
/*0350*/ FFMA R7, R11.reuse, 0.80000001192092895508, R14 ; /* 0x3f4ccccd0b077823 */
/* 0x040fe4000000000e */
/*0360*/ FADD R21, R18, R23 ; /* 0x0000001712157221 */
/* 0x000fe40000000000 */
/*0370*/ FADD R23, R8, R12 ; /* 0x0000000c08177221 */
/* 0x000fe40000000000 */
/*0380*/ FADD R25, R6, R14 ; /* 0x0000000e06197221 */
/* 0x000fe40000000000 */
/*0390*/ FFMA R11, R11, 0.10000000149011611938, R16 ; /* 0x3dcccccd0b0b7823 */
/* 0x000fe40000000010 */
/*03a0*/ FFMA R27, R10, 0.10000000149011611938, R7 ; /* 0x3dcccccd0a1b7823 */
/* 0x000fe20000000007 */
/*03b0*/ STG.E [R4.64+-0x10], R15 ; /* 0xfffff00f04007986 */
/* 0x000fe8000c101908 */
/*03c0*/ STG.E [R4.64+-0xc], R17 ; /* 0xfffff41104007986 */
/* 0x000fe8000c101908 */
/*03d0*/ STG.E [R4.64+-0x8], R19 ; /* 0xfffff81304007986 */
/* 0x000fe8000c101908 */
/*03e0*/ STG.E [R4.64+-0x4], R9 ; /* 0xfffffc0904007986 */
/* 0x000fe8000c101908 */
/*03f0*/ STG.E [R4.64], R21 ; /* 0x0000001504007986 */
/* 0x000fe8000c101908 */
/*0400*/ STG.E [R4.64+0x4], R23 ; /* 0x0000041704007986 */
/* 0x000fe8000c101908 */
/*0410*/ STG.E [R4.64+0x8], R25 ; /* 0x0000081904007986 */
/* 0x000fe8000c101908 */
/*0420*/ STG.E [R4.64+0xc], R11 ; /* 0x00000c0b04007986 */
/* 0x000fe8000c101908 */
/*0430*/ STG.E [R4.64+0x10], R27 ; /* 0x0000101b04007986 */
/* 0x000fe2000c101908 */
/*0440*/ IADD3 R10, P1, R2, 0x28, RZ ; /* 0x00000028020a7810 */
/* 0x000fc40007f3e0ff */
/*0450*/ IADD3 R7, P2, R4, 0x28, RZ ; /* 0x0000002804077810 */
/* 0x000fe20007f5e0ff */
/*0460*/ STG.E [R4.64+-0x14], R13 ; /* 0xffffec0d04007986 */
/* 0x0001e2000c101908 */
/*0470*/ MOV R6, 0x1 ; /* 0x0000000100067802 */
/* 0x000fe40000000f00 */
/*0480*/ IADD3.X R8, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff087210 */
/* 0x000fe400017fe4ff */
/*0490*/ IADD3.X R13, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff0d7210 */
/* 0x001fe40000ffe4ff */
/*04a0*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fe40000000f00 */
/*04b0*/ MOV R5, R13 ; /* 0x0000000d00057202 */
/* 0x000fca0000000f00 */
/*04c0*/ LDG.E R2, [R4.64+0x10] ; /* 0x0000100804027981 */
/* 0x002ea8000c1e1900 */
/*04d0*/ LDG.E R3, [R4.64+-0x14] ; /* 0xffffec0804037981 */
/* 0x000ee8000c1e1900 */
/*04e0*/ LDG.E R15, [R4.64+-0x10] ; /* 0xfffff008040f7981 */
/* 0x000f28000c1e1900 */
/*04f0*/ LDG.E R17, [R4.64+-0xc] ; /* 0xfffff40804117981 */
/* 0x000f68000c1e1900 */
/*0500*/ LDG.E R19, [R4.64+-0x8] ; /* 0xfffff80804137981 */
/* 0x000f68000c1e1900 */
/*0510*/ LDG.E R21, [R4.64+-0x4] ; /* 0xfffffc0804157981 */
/* 0x000f68000c1e1900 */
/*0520*/ LDG.E R12, [R4.64] ; /* 0x00000008040c7981 */
/* 0x000f68000c1e1900 */
/*0530*/ LDG.E R9, [R4.64+0x4] ; /* 0x0000040804097981 */
/* 0x000f68000c1e1900 */
/*0540*/ LDG.E R10, [R4.64+0x8] ; /* 0x00000808040a7981 */
/* 0x000f68000c1e1900 */
/*0550*/ LDG.E R11, [R4.64+0xc] ; /* 0x00000c08040b7981 */
/* 0x000f62000c1e1900 */
/*0560*/ FMUL R14, R2, 0.10000000149011611938 ; /* 0x3dcccccd020e7820 */
/* 0x004fc40000400000 */
/*0570*/ FMUL R18, R3.reuse, 0.10000000149011611938 ; /* 0x3dcccccd03127820 */
/* 0x048fe40000400000 */
/*0580*/ FFMA R13, R3, 0.80000001192092895508, R14 ; /* 0x3f4ccccd030d7823 */
/* 0x000fe4000000000e */
/*0590*/ FMUL R16, R15.reuse, 0.10000000149011611938 ; /* 0x3dcccccd0f107820 */
/* 0x050fe40000400000 */
/*05a0*/ FFMA R15, R15, 0.80000001192092895508, R18 ; /* 0x3f4ccccd0f0f7823 */
/* 0x000fe40000000012 */
/*05b0*/ FMUL R14, R17, 0.10000000149011611938 ; /* 0x3dcccccd110e7820 */
/* 0x020fe40000400000 */
/*05c0*/ FADD R13, R13, R16 ; /* 0x000000100d0d7221 */
/* 0x000fc40000000000 */
/*05d0*/ FFMA R17, R17, 0.80000001192092895508, R16 ; /* 0x3f4ccccd11117823 */
/* 0x000fe40000000010 */
/*05e0*/ FMUL R16, R19, 0.10000000149011611938 ; /* 0x3dcccccd13107820 */
/* 0x000fe40000400000 */
/*05f0*/ FADD R15, R15, R14.reuse ; /* 0x0000000e0f0f7221 */
/* 0x100fe40000000000 */
/*0600*/ FFMA R19, R19, 0.80000001192092895508, R14 ; /* 0x3f4ccccd13137823 */
/* 0x000fe4000000000e */
/*0610*/ FMUL R14, R21, 0.10000000149011611938 ; /* 0x3dcccccd150e7820 */
/* 0x000fe40000400000 */
/*0620*/ FADD R17, R17, R16 ; /* 0x0000001011117221 */
/* 0x000fc40000000000 */
/*0630*/ FFMA R21, R21, 0.80000001192092895508, R16 ; /* 0x3f4ccccd15157823 */
/* 0x000fe40000000010 */
/*0640*/ FMUL R16, R12.reuse, 0.10000000149011611938 ; /* 0x3dcccccd0c107820 */
/* 0x040fe40000400000 */
/*0650*/ FADD R19, R19, R14.reuse ; /* 0x0000000e13137221 */
/* 0x100fe40000000000 */
/*0660*/ FFMA R12, R12, 0.80000001192092895508, R14 ; /* 0x3f4ccccd0c0c7823 */
/* 0x000fe4000000000e */
/*0670*/ FMUL R23, R9, 0.10000000149011611938 ; /* 0x3dcccccd09177820 */
/* 0x000fe40000400000 */
/*0680*/ FMUL R14, R10, 0.10000000149011611938 ; /* 0x3dcccccd0a0e7820 */
/* 0x000fc40000400000 */
/*0690*/ FMUL R25, R11, 0.10000000149011611938 ; /* 0x3dcccccd0b197820 */
/* 0x000fe40000400000 */
/*06a0*/ FADD R21, R21, R16.reuse ; /* 0x0000001015157221 */
/* 0x100fe40000000000 */
/*06b0*/ FFMA R16, R9, 0.80000001192092895508, R16 ; /* 0x3f4ccccd09107823 */
/* 0x000fe40000000010 */
/*06c0*/ FADD R9, R12, R23.reuse ; /* 0x000000170c097221 */
/* 0x100fe40000000000 */
/*06d0*/ FFMA R10, R10, 0.80000001192092895508, R23 ; /* 0x3f4ccccd0a0a7823 */
/* 0x000fe40000000017 */
/*06e0*/ FFMA R23, R11, 0.80000001192092895508, R14 ; /* 0x3f4ccccd0b177823 */
/* 0x000fc4000000000e */
/*06f0*/ FFMA R12, R2.reuse, 0.80000001192092895508, R25 ; /* 0x3f4ccccd020c7823 */
/* 0x040fe40000000019 */
/*0700*/ FFMA R23, R2, 0.10000000149011611938, R23 ; /* 0x3dcccccd02177823 */
/* 0x000fe20000000017 */
/*0710*/ MOV R2, R7 ; /* 0x0000000700027202 */
/* 0x000fe20000000f00 */
/*0720*/ FFMA R27, R3, 0.10000000149011611938, R12 ; /* 0x3dcccccd031b7823 */
/* 0x000fe2000000000c */
/*0730*/ MOV R3, R8 ; /* 0x0000000800037202 */
/* 0x000fe20000000f00 */
/*0740*/ FADD R11, R16, R14 ; /* 0x0000000e100b7221 */
/* 0x000fe40000000000 */
/*0750*/ FADD R25, R10, R25 ; /* 0x000000190a197221 */
/* 0x000fe40000000000 */
/*0760*/ STG.E [R2.64+-0x14], R13 ; /* 0xffffec0d02007986 */
/* 0x000fe8000c101908 */
/*0770*/ STG.E [R2.64+-0x10], R15 ; /* 0xfffff00f02007986 */
/* 0x000fe8000c101908 */
/*0780*/ STG.E [R2.64+-0xc], R17 ; /* 0xfffff41102007986 */
/* 0x0001e8000c101908 */
/*0790*/ STG.E [R2.64+-0x8], R19 ; /* 0xfffff81302007986 */
/* 0x0003e8000c101908 */
/*07a0*/ STG.E [R2.64+-0x4], R21 ; /* 0xfffffc1502007986 */
/* 0x0005e8000c101908 */
/*07b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0007e8000c101908 */
/*07c0*/ STG.E [R2.64+0x4], R11 ; /* 0x0000040b02007986 */
/* 0x0009e8000c101908 */
/*07d0*/ STG.E [R2.64+0x8], R25 ; /* 0x0000081902007986 */
/* 0x000fe8000c101908 */
/*07e0*/ STG.E [R2.64+0xc], R23 ; /* 0x00000c1702007986 */
/* 0x000be8000c101908 */
/*07f0*/ STG.E [R2.64+0x10], R27 ; /* 0x0000101b02007986 */
/* 0x0001e8000c101908 */
/*0800*/ LDG.E R7, [R4.64+0x38] ; /* 0x0000380804077981 */
/* 0x000f68000c1e1900 */
/*0810*/ LDG.E R8, [R4.64+0x14] ; /* 0x0000140804087981 */
/* 0x000f68000c1e1900 */
/*0820*/ LDG.E R14, [R4.64+0x18] ; /* 0x00001808040e7981 */
/* 0x000f68000c1e1900 */
/*0830*/ LDG.E R17, [R4.64+0x1c] ; /* 0x00001c0804117981 */
/* 0x001f68000c1e1900 */
/*0840*/ LDG.E R19, [R4.64+0x20] ; /* 0x0000200804137981 */
/* 0x002f68000c1e1900 */
/*0850*/ LDG.E R21, [R4.64+0x24] ; /* 0x0000240804157981 */
/* 0x004ea8000c1e1900 */
/*0860*/ LDG.E R12, [R4.64+0x28] ; /* 0x00002808040c7981 */
/* 0x000ea8000c1e1900 */
/*0870*/ LDG.E R9, [R4.64+0x2c] ; /* 0x00002c0804097981 */
/* 0x008ee8000c1e1900 */
/*0880*/ LDG.E R10, [R4.64+0x30] ; /* 0x00003008040a7981 */
/* 0x000ee8000c1e1900 */
/*0890*/ LDG.E R11, [R4.64+0x34] ; /* 0x00003408040b7981 */
/* 0x010f22000c1e1900 */
/*08a0*/ FMUL R13, R7, 0.10000000149011611938 ; /* 0x3dcccccd070d7820 */
/* 0x020fc40000400000 */
/*08b0*/ FMUL R15, R8.reuse, 0.10000000149011611938 ; /* 0x3dcccccd080f7820 */
/* 0x040fe40000400000 */
/*08c0*/ FFMA R13, R8, 0.80000001192092895508, R13 ; /* 0x3f4ccccd080d7823 */
/* 0x000fe4000000000d */
/*08d0*/ FMUL R16, R14.reuse, 0.10000000149011611938 ; /* 0x3dcccccd0e107820 */
/* 0x040fe40000400000 */
/*08e0*/ FFMA R15, R14, 0.80000001192092895508, R15 ; /* 0x3f4ccccd0e0f7823 */
/* 0x000fe4000000000f */
/*08f0*/ FMUL R14, R17, 0.10000000149011611938 ; /* 0x3dcccccd110e7820 */
/* 0x000fe40000400000 */
/*0900*/ FADD R13, R13, R16 ; /* 0x000000100d0d7221 */
/* 0x000fc40000000000 */
/*0910*/ FFMA R17, R17, 0.80000001192092895508, R16 ; /* 0x3f4ccccd11117823 */
/* 0x000fe40000000010 */
/*0920*/ FMUL R16, R19, 0.10000000149011611938 ; /* 0x3dcccccd13107820 */
/* 0x000fe20000400000 */
/*0930*/ STG.E [R2.64+0x14], R13 ; /* 0x0000140d02007986 */
/* 0x000fe2000c101908 */
/*0940*/ FADD R15, R15, R14.reuse ; /* 0x0000000e0f0f7221 */
/* 0x100fe40000000000 */
/*0950*/ FFMA R19, R19, 0.80000001192092895508, R14 ; /* 0x3f4ccccd13137823 */
/* 0x000fe4000000000e */
/*0960*/ FMUL R14, R21, 0.10000000149011611938 ; /* 0x3dcccccd150e7820 */
/* 0x004fe20000400000 */
/*0970*/ STG.E [R2.64+0x18], R15 ; /* 0x0000180f02007986 */
/* 0x000fe2000c101908 */
/*0980*/ FADD R17, R17, R16 ; /* 0x0000001011117221 */
/* 0x000fc40000000000 */
/*0990*/ FFMA R21, R21, 0.80000001192092895508, R16 ; /* 0x3f4ccccd15157823 */
/* 0x000fe40000000010 */
/*09a0*/ FMUL R16, R12.reuse, 0.10000000149011611938 ; /* 0x3dcccccd0c107820 */
/* 0x040fe20000400000 */
/*09b0*/ STG.E [R2.64+0x1c], R17 ; /* 0x00001c1102007986 */
/* 0x0001e2000c101908 */
/*09c0*/ FADD R19, R19, R14.reuse ; /* 0x0000000e13137221 */
/* 0x100fe40000000000 */
/*09d0*/ FFMA R12, R12, 0.80000001192092895508, R14 ; /* 0x3f4ccccd0c0c7823 */
/* 0x000fe4000000000e */
/*09e0*/ FMUL R23, R9, 0.10000000149011611938 ; /* 0x3dcccccd09177820 */
/* 0x008fe20000400000 */
/*09f0*/ STG.E [R2.64+0x20], R19 ; /* 0x0000201302007986 */
/* 0x0003e2000c101908 */
/*0a00*/ FMUL R14, R10, 0.10000000149011611938 ; /* 0x3dcccccd0a0e7820 */
/* 0x000fc40000400000 */
/*0a10*/ FMUL R18, R11, 0.10000000149011611938 ; /* 0x3dcccccd0b127820 */
/* 0x010fe40000400000 */
/*0a20*/ FADD R21, R21, R16.reuse ; /* 0x0000001015157221 */
/* 0x100fe40000000000 */
/*0a30*/ FFMA R16, R9, 0.80000001192092895508, R16 ; /* 0x3f4ccccd09107823 */
/* 0x000fe40000000010 */
/*0a40*/ FADD R9, R12, R23.reuse ; /* 0x000000170c097221 */
/* 0x100fe20000000000 */
/*0a50*/ STG.E [R2.64+0x24], R21 ; /* 0x0000241502007986 */
/* 0x0005e2000c101908 */
/*0a60*/ FFMA R10, R10, 0.80000001192092895508, R23 ; /* 0x3f4ccccd0a0a7823 */
/* 0x000fe40000000017 */
/*0a70*/ FFMA R12, R11, 0.80000001192092895508, R14 ; /* 0x3f4ccccd0b0c7823 */
/* 0x000fe2000000000e */
/*0a80*/ STG.E [R2.64+0x28], R9 ; /* 0x0000280902007986 */
/* 0x0007e2000c101908 */
/*0a90*/ FFMA R27, R7, 0.80000001192092895508, R18 ; /* 0x3f4ccccd071b7823 */
/* 0x000fc40000000012 */
/*0aa0*/ FADD R11, R16, R14 ; /* 0x0000000e100b7221 */
/* 0x000fe40000000000 */
/*0ab0*/ FADD R23, R10, R18 ; /* 0x000000120a177221 */
/* 0x000fe40000000000 */
/*0ac0*/ FFMA R25, R7, 0.10000000149011611938, R12 ; /* 0x3dcccccd07197823 */
/* 0x000fe2000000000c */
/*0ad0*/ STG.E [R2.64+0x2c], R11 ; /* 0x00002c0b02007986 */
/* 0x0009e2000c101908 */
/*0ae0*/ FFMA R27, R8, 0.10000000149011611938, R27 ; /* 0x3dcccccd081b7823 */
/* 0x000fc6000000001b */
/*0af0*/ STG.E [R2.64+0x30], R23 ; /* 0x0000301702007986 */
/* 0x000be8000c101908 */
/*0b00*/ STG.E [R2.64+0x34], R25 ; /* 0x0000341902007986 */
/* 0x000fe8000c101908 */
/*0b10*/ STG.E [R2.64+0x38], R27 ; /* 0x0000381b02007986 */
/* 0x0001e8000c101908 */
/*0b20*/ LDG.E R7, [R4.64+0x60] ; /* 0x0000600804077981 */
/* 0x000f68000c1e1900 */
/*0b30*/ LDG.E R8, [R4.64+0x3c] ; /* 0x00003c0804087981 */
/* 0x000f68000c1e1900 */
/*0b40*/ LDG.E R14, [R4.64+0x40] ; /* 0x00004008040e7981 */
/* 0x000f68000c1e1900 */
/*0b50*/ LDG.E R17, [R4.64+0x44] ; /* 0x0000440804117981 */
/* 0x001f68000c1e1900 */
/*0b60*/ LDG.E R19, [R4.64+0x48] ; /* 0x0000480804137981 */
/* 0x002f68000c1e1900 */
/*0b70*/ LDG.E R21, [R4.64+0x4c] ; /* 0x00004c0804157981 */
/* 0x004ea8000c1e1900 */
/*0b80*/ LDG.E R12, [R4.64+0x50] ; /* 0x00005008040c7981 */
/* 0x000ea8000c1e1900 */
/*0b90*/ LDG.E R9, [R4.64+0x54] ; /* 0x0000540804097981 */
/* 0x008ee8000c1e1900 */
/*0ba0*/ LDG.E R10, [R4.64+0x58] ; /* 0x00005808040a7981 */
/* 0x000ee8000c1e1900 */
/*0bb0*/ LDG.E R11, [R4.64+0x5c] ; /* 0x00005c08040b7981 */
/* 0x010f22000c1e1900 */
/*0bc0*/ IADD3 R6, R6, 0x3, RZ ; /* 0x0000000306067810 */
/* 0x000fc80007ffe0ff */
/*0bd0*/ ISETP.NE.AND P1, PT, R6, 0x7, PT ; /* 0x000000070600780c */
/* 0x000fe20003f25270 */
/*0be0*/ FMUL R13, R7, 0.10000000149011611938 ; /* 0x3dcccccd070d7820 */
/* 0x020fe40000400000 */
/*0bf0*/ FMUL R15, R8.reuse, 0.10000000149011611938 ; /* 0x3dcccccd080f7820 */
/* 0x040fe40000400000 */
/*0c00*/ FFMA R13, R8, 0.80000001192092895508, R13 ; /* 0x3f4ccccd080d7823 */
/* 0x000fe4000000000d */
/*0c10*/ FMUL R16, R14.reuse, 0.10000000149011611938 ; /* 0x3dcccccd0e107820 */
/* 0x040fe40000400000 */
/*0c20*/ FFMA R15, R14, 0.80000001192092895508, R15 ; /* 0x3f4ccccd0e0f7823 */
/* 0x000fe4000000000f */
/*0c30*/ FMUL R14, R17, 0.10000000149011611938 ; /* 0x3dcccccd110e7820 */
/* 0x000fc40000400000 */
/*0c40*/ FADD R13, R13, R16.reuse ; /* 0x000000100d0d7221 */
/* 0x100fe40000000000 */
/*0c50*/ FFMA R17, R17, 0.80000001192092895508, R16 ; /* 0x3f4ccccd11117823 */
/* 0x000fe40000000010 */
/*0c60*/ FMUL R16, R19, 0.10000000149011611938 ; /* 0x3dcccccd13107820 */
/* 0x000fe20000400000 */
/*0c70*/ STG.E [R2.64+0x3c], R13 ; /* 0x00003c0d02007986 */
/* 0x0001e2000c101908 */
/*0c80*/ FADD R15, R15, R14.reuse ; /* 0x0000000e0f0f7221 */
/* 0x100fe40000000000 */
/*0c90*/ FFMA R19, R19, 0.80000001192092895508, R14 ; /* 0x3f4ccccd13137823 */
/* 0x000fe4000000000e */
/*0ca0*/ FMUL R14, R21, 0.10000000149011611938 ; /* 0x3dcccccd150e7820 */
/* 0x004fe20000400000 */
/*0cb0*/ STG.E [R2.64+0x40], R15 ; /* 0x0000400f02007986 */
/* 0x0003e2000c101908 */
/*0cc0*/ FADD R17, R17, R16 ; /* 0x0000001011117221 */
/* 0x000fc40000000000 */
/*0cd0*/ FFMA R21, R21, 0.80000001192092895508, R16 ; /* 0x3f4ccccd15157823 */
/* 0x000fe40000000010 */
/*0ce0*/ FMUL R16, R12.reuse, 0.10000000149011611938 ; /* 0x3dcccccd0c107820 */
/* 0x040fe20000400000 */
/*0cf0*/ STG.E [R2.64+0x44], R17 ; /* 0x0000441102007986 */
/* 0x0003e2000c101908 */
/*0d00*/ FADD R19, R19, R14.reuse ; /* 0x0000000e13137221 */
/* 0x100fe40000000000 */
/*0d10*/ FFMA R12, R12, 0.80000001192092895508, R14 ; /* 0x3f4ccccd0c0c7823 */
/* 0x000fe4000000000e */
/*0d20*/ FMUL R23, R9, 0.10000000149011611938 ; /* 0x3dcccccd09177820 */
/* 0x008fe20000400000 */
/*0d30*/ STG.E [R2.64+0x48], R19 ; /* 0x0000481302007986 */
/* 0x0003e2000c101908 */
/*0d40*/ FMUL R14, R10, 0.10000000149011611938 ; /* 0x3dcccccd0a0e7820 */
/* 0x000fc40000400000 */
/*0d50*/ FMUL R18, R11, 0.10000000149011611938 ; /* 0x3dcccccd0b127820 */
/* 0x010fe40000400000 */
/*0d60*/ FADD R21, R21, R16.reuse ; /* 0x0000001015157221 */
/* 0x100fe40000000000 */
/*0d70*/ FFMA R16, R9, 0.80000001192092895508, R16 ; /* 0x3f4ccccd09107823 */
/* 0x000fe40000000010 */
/*0d80*/ FADD R9, R12, R23.reuse ; /* 0x000000170c097221 */
/* 0x100fe20000000000 */
/*0d90*/ STG.E [R2.64+0x4c], R21 ; /* 0x00004c1502007986 */
/* 0x0003e2000c101908 */
/*0da0*/ FFMA R10, R10, 0.80000001192092895508, R23 ; /* 0x3f4ccccd0a0a7823 */
/* 0x000fe40000000017 */
/*0db0*/ FFMA R12, R11, 0.80000001192092895508, R14 ; /* 0x3f4ccccd0b0c7823 */
/* 0x000fe2000000000e */
/*0dc0*/ STG.E [R2.64+0x50], R9 ; /* 0x0000500902007986 */
/* 0x0003e2000c101908 */
/*0dd0*/ FFMA R27, R7, 0.80000001192092895508, R18 ; /* 0x3f4ccccd071b7823 */
/* 0x000fc40000000012 */
/*0de0*/ FADD R11, R16, R14 ; /* 0x0000000e100b7221 */
/* 0x000fe40000000000 */
/*0df0*/ FADD R23, R10, R18 ; /* 0x000000120a177221 */
/* 0x000fe20000000000 */
/*0e00*/ IADD3 R10, P2, R4, 0x78, RZ ; /* 0x00000078040a7810 */
/* 0x000fe20007f5e0ff */
/*0e10*/ FFMA R25, R7, 0.10000000149011611938, R12 ; /* 0x3dcccccd07197823 */
/* 0x000fe2000000000c */
/*0e20*/ IADD3 R7, P3, R2, 0x78, RZ ; /* 0x0000007802077810 */
/* 0x000fe20007f7e0ff */
/*0e30*/ FFMA R27, R8, 0.10000000149011611938, R27 ; /* 0x3dcccccd081b7823 */
/* 0x000fe2000000001b */
/*0e40*/ STG.E [R2.64+0x54], R11 ; /* 0x0000540b02007986 */
/* 0x0003e2000c101908 */
/*0e50*/ IADD3.X R13, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff0d7210 */
/* 0x001fe400017fe4ff */
/*0e60*/ IADD3.X R8, RZ, R3, RZ, P3, !PT ; /* 0x00000003ff087210 */
/* 0x000fe20001ffe4ff */
/*0e70*/ STG.E [R2.64+0x58], R23 ; /* 0x0000581702007986 */
/* 0x0003e8000c101908 */
/*0e80*/ STG.E [R2.64+0x5c], R25 ; /* 0x00005c1902007986 */
/* 0x0003e8000c101908 */
/*0e90*/ STG.E [R2.64+0x60], R27 ; /* 0x0000601b02007986 */
/* 0x0003e2000c101908 */
/*0ea0*/ @P1 BRA 0x4a0 ; /* 0xfffff5f000001947 */
/* 0x000fea000383ffff */
/*0eb0*/ @!P0 BRA 0xa0 ; /* 0xfffff1e000008947 */
/* 0x000fea000383ffff */
/*0ec0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ed0*/ BRA 0xed0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6smoothPfS_
.globl _Z6smoothPfS_
.p2align 8
.type _Z6smoothPfS_,@function
_Z6smoothPfS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v10, 0
s_mov_b32 s5, 0
s_mov_b32 s16, 9
s_mov_b32 s17, 0
s_waitcnt lgkmcnt(0)
s_mov_b64 s[6:7], s[0:1]
.LBB0_1:
s_mul_i32 s18, s17, 0x46
s_mov_b64 s[8:9], s[2:3]
s_mov_b32 s19, s16
s_mov_b64 s[10:11], s[6:7]
s_mov_b32 s20, s5
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s21, s20, 10
s_mov_b64 s[12:13], 0
s_add_i32 s21, s21, s18
s_mov_b32 s22, 9
s_mov_b64 s[14:15], s[10:11]
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_3:
s_mul_hi_u32 s4, s22, 0xcccccccd
s_mov_b32 m0, s12
s_lshr_b32 s4, s4, 3
global_load_b32 v12, v10, s[14:15]
s_mul_i32 s4, s4, 10
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s4, s19, s4
s_add_u32 s24, s12, 1
s_addc_u32 s25, s13, 0
s_cmp_lg_u32 s12, 9
s_cselect_b32 s13, s24, 0
s_add_i32 s4, s12, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[26:27], s[4:5], 2
s_add_u32 s26, s0, s26
s_addc_u32 s27, s1, s27
s_add_i32 s4, s13, s21
global_load_b32 v11, v10, s[26:27]
s_lshl_b64 s[26:27], s[4:5], 2
s_mov_b64 s[12:13], s[24:25]
s_add_u32 s26, s0, s26
s_addc_u32 s27, s1, s27
s_add_u32 s14, s14, 4
global_load_b32 v13, v10, s[26:27]
s_addc_u32 s15, s15, 0
s_add_i32 s22, s22, 1
s_cmp_eq_u32 s24, 10
s_waitcnt vmcnt(1)
v_mul_f32_e32 v11, 0x3dcccccd, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v11, 0x3f4ccccd, v12
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v11, 0x3dcccccd, v13
s_delay_alu instid0(VALU_DEP_1)
v_movreld_b32_e32 v0, v11
s_cbranch_scc0 .LBB0_3
s_set_inst_prefetch_distance 0x2
s_mov_b64 s[12:13], 0
s_mov_b64 s[14:15], s[8:9]
.LBB0_5:
s_mov_b32 m0, s12
s_add_u32 s12, s12, 1
v_movrels_b32_e32 v11, v0
s_addc_u32 s13, s13, 0
global_store_b32 v10, v11, s[14:15]
s_add_u32 s14, s14, 4
s_addc_u32 s15, s15, 0
s_cmp_lg_u32 s12, 10
s_cbranch_scc1 .LBB0_5
s_add_i32 s20, s20, 1
s_add_u32 s10, s10, 40
s_addc_u32 s11, s11, 0
s_add_i32 s19, s19, 10
s_add_u32 s8, s8, 40
s_addc_u32 s9, s9, 0
s_cmp_lg_u32 s20, 7
s_cbranch_scc1 .LBB0_2
s_add_i32 s17, s17, 1
s_add_u32 s6, s6, 0x118
s_addc_u32 s7, s7, 0
s_addk_i32 s16, 0x46
s_add_u32 s2, s2, 0x118
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s17, 18
s_cbranch_scc1 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6smoothPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 28
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6smoothPfS_, .Lfunc_end0-_Z6smoothPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6smoothPfS_
.private_segment_fixed_size: 0
.sgpr_count: 28
.sgpr_spill_count: 0
.symbol: _Z6smoothPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013e8eb_00000000-6_smooth.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6smoothPfS_PfS_
.type _Z27__device_stub__Z6smoothPfS_PfS_, @function
_Z27__device_stub__Z6smoothPfS_PfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6smoothPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z6smoothPfS_PfS_, .-_Z27__device_stub__Z6smoothPfS_PfS_
.globl _Z6smoothPfS_
.type _Z6smoothPfS_, @function
_Z6smoothPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6smoothPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6smoothPfS_, .-_Z6smoothPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6smoothPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6smoothPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "smooth.hip"
.globl _Z21__device_stub__smoothPfS_ # -- Begin function _Z21__device_stub__smoothPfS_
.p2align 4, 0x90
.type _Z21__device_stub__smoothPfS_,@function
_Z21__device_stub__smoothPfS_: # @_Z21__device_stub__smoothPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6smoothPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__smoothPfS_, .Lfunc_end0-_Z21__device_stub__smoothPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6smoothPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6smoothPfS_,@object # @_Z6smoothPfS_
.section .rodata,"a",@progbits
.globl _Z6smoothPfS_
.p2align 3, 0x0
_Z6smoothPfS_:
.quad _Z21__device_stub__smoothPfS_
.size _Z6smoothPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6smoothPfS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__smoothPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6smoothPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void dropout_test(float* data, int size, float probability)
{
int thread_index = threadIdx.x + blockIdx.x * blockDim.x;
int num_threads = blockDim.x * gridDim.x;
for(int i = 0; i < size; i += num_threads)
{
int index = i + thread_index;
if(index < size)
{
data[index] = data[index] * probability;
}
}
} | code for sm_80
Function : _Z12dropout_testPfif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R5, c[0x0][0x168] ; /* 0x00005a0000057a02 */
/* 0x000fc80000000f00 */
/*0020*/ ISETP.GE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*0070*/ I2F.U32.RP R4, R0 ; /* 0x0000000000047306 */
/* 0x000e220000209000 */
/*0080*/ IADD3 R7, RZ, -R0, RZ ; /* 0x80000000ff077210 */
/* 0x000fe40007ffe0ff */
/*0090*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fca0003f45070 */
/*00a0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*00b0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*00c0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00d0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00e0*/ IMAD R7, R7, R3, RZ ; /* 0x0000000307077224 */
/* 0x002fc800078e02ff */
/*00f0*/ IMAD.HI.U32 R6, R3, R7, R2 ; /* 0x0000000703067227 */
/* 0x000fe200078e0002 */
/*0100*/ IADD3 R3, R5, -0x1, RZ ; /* 0xffffffff05037810 */
/* 0x000fe20007ffe0ff */
/*0110*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0120*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fc600000001ff */
/*0130*/ IMAD.HI.U32 R6, R6, R3, RZ ; /* 0x0000000306067227 */
/* 0x000fca00078e00ff */
/*0140*/ IADD3 R5, -R6, RZ, RZ ; /* 0x000000ff06057210 */
/* 0x000fca0007ffe1ff */
/*0150*/ IMAD R3, R0, R5, R3 ; /* 0x0000000500037224 */
/* 0x000fca00078e0203 */
/*0160*/ ISETP.GE.U32.AND P0, PT, R3, R0, PT ; /* 0x000000000300720c */
/* 0x000fda0003f06070 */
/*0170*/ @P0 IMAD.IADD R3, R3, 0x1, -R0 ; /* 0x0000000103030824 */
/* 0x000fe200078e0a00 */
/*0180*/ @P0 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106060810 */
/* 0x000fc80007ffe0ff */
/*0190*/ ISETP.GE.U32.AND P1, PT, R3, R0, PT ; /* 0x000000000300720c */
/* 0x000fe40003f26070 */
/*01a0*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e760000002100 */
/*01b0*/ @P1 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106061810 */
/* 0x000fc40007ffe0ff */
/*01c0*/ @!P2 LOP3.LUT R6, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff06a212 */
/* 0x000fc800078e33ff */
/*01d0*/ ISETP.GE.U32.AND P0, PT, R6.reuse, 0x3, PT ; /* 0x000000030600780c */
/* 0x040fe40003f06070 */
/*01e0*/ IADD3 R5, R6, 0x1, RZ ; /* 0x0000000106057810 */
/* 0x000fc80007ffe0ff */
/*01f0*/ LOP3.LUT R4, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305047812 */
/* 0x000fce00078ec0ff */
/*0200*/ @!P0 BRA 0x1100 ; /* 0x00000ef000008947 */
/* 0x000fea0003800000 */
/*0210*/ IMAD.IADD R5, R5, 0x1, -R4 ; /* 0x0000000105057824 */
/* 0x003fe200078e0a04 */
/*0220*/ MOV R7, c[0x0][0xc] ; /* 0x0000030000077a02 */
/* 0x000fe20000000f00 */
/*0230*/ IMAD R15, R2.reuse, c[0x0][0x0], R3.reuse ; /* 0x00000000020f7a24 */
/* 0x140fe200078e0203 */
/*0240*/ IADD3 R10, R2, c[0x0][0xc], RZ ; /* 0x00000300020a7a10 */
/* 0x000fe40007ffe0ff */
/*0250*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f04270 */
/*0260*/ IMAD R6, R7.reuse, 0x3, R2.reuse ; /* 0x0000000307067824 */
/* 0x140fe400078e0202 */
/*0270*/ IMAD R8, R7, 0x2, R2 ; /* 0x0000000207087824 */
/* 0x000fe200078e0202 */
/*0280*/ MOV R7, RZ ; /* 0x000000ff00077202 */
/* 0x000fe20000000f00 */
/*0290*/ IMAD R13, R10, c[0x0][0x0], R3 ; /* 0x000000000a0d7a24 */
/* 0x000fc400078e0203 */
/*02a0*/ IMAD R9, R6, c[0x0][0x0], R3.reuse ; /* 0x0000000006097a24 */
/* 0x100fe400078e0203 */
/*02b0*/ IMAD R11, R8, c[0x0][0x0], R3 ; /* 0x00000000080b7a24 */
/* 0x000fc800078e0203 */
/*02c0*/ @!P0 BRA 0xef0 ; /* 0x00000c2000008947 */
/* 0x000fea0003800000 */
/*02d0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*02e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*02f0*/ @!P1 BRA 0xac0 ; /* 0x000007c000009947 */
/* 0x000fea0003800000 */
/*0300*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0310*/ ISETP.GE.AND P2, PT, R15, c[0x0][0x168], PT ; /* 0x00005a000f007a0c */
/* 0x000fda0003f46270 */
/*0320*/ @!P2 IMAD.MOV.U32 R20, RZ, RZ, 0x4 ; /* 0x00000004ff14a424 */
/* 0x000fc800078e00ff */
/*0330*/ @!P2 IMAD.WIDE R20, R15, R20, c[0x0][0x160] ; /* 0x000058000f14a625 */
/* 0x000fca00078e0214 */
/*0340*/ @!P2 LDG.E R6, [R20.64] ; /* 0x000000041406a981 */
/* 0x000ea2000c1e1900 */
/*0350*/ ISETP.GE.AND P1, PT, R13, c[0x0][0x168], PT ; /* 0x00005a000d007a0c */
/* 0x000fda0003f26270 */
/*0360*/ @!P1 MOV R16, 0x4 ; /* 0x0000000400109802 */
/* 0x000fca0000000f00 */
/*0370*/ @!P1 IMAD.WIDE R16, R13, R16, c[0x0][0x160] ; /* 0x000058000d109625 */
/* 0x000fc800078e0210 */
/*0380*/ @!P2 FMUL R23, R6, c[0x0][0x16c] ; /* 0x00005b000617aa20 */
/* 0x004fca0000400000 */
/*0390*/ @!P2 STG.E [R20.64], R23 ; /* 0x000000171400a986 */
/* 0x0001e8000c101904 */
/*03a0*/ @!P1 LDG.E R6, [R16.64] ; /* 0x0000000410069981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ ISETP.GE.AND P2, PT, R11, c[0x0][0x168], PT ; /* 0x00005a000b007a0c */
/* 0x000fda0003f46270 */
/*03c0*/ @!P2 IMAD.MOV.U32 R18, RZ, RZ, 0x4 ; /* 0x00000004ff12a424 */
/* 0x000fc800078e00ff */
/*03d0*/ @!P2 IMAD.WIDE R18, R11, R18, c[0x0][0x160] ; /* 0x000058000b12a625 */
/* 0x000fc800078e0212 */
/*03e0*/ @!P1 FMUL R25, R6, c[0x0][0x16c] ; /* 0x00005b0006199a20 */
/* 0x004fca0000400000 */
/*03f0*/ @!P1 STG.E [R16.64], R25 ; /* 0x0000001910009986 */
/* 0x0003e8000c101904 */
/*0400*/ @!P2 LDG.E R6, [R18.64] ; /* 0x000000041206a981 */
/* 0x000ea2000c1e1900 */
/*0410*/ ISETP.GE.AND P1, PT, R9, c[0x0][0x168], PT ; /* 0x00005a0009007a0c */
/* 0x000fda0003f26270 */
/*0420*/ @!P1 MOV R8, 0x4 ; /* 0x0000000400089802 */
/* 0x000fca0000000f00 */
/*0430*/ @!P1 IMAD.WIDE R20, R9, R8, c[0x0][0x160] ; /* 0x0000580009149625 */
/* 0x001fc800078e0208 */
/*0440*/ @!P2 FMUL R27, R6, c[0x0][0x16c] ; /* 0x00005b00061baa20 */
/* 0x004fca0000400000 */
/*0450*/ @!P2 STG.E [R18.64], R27 ; /* 0x0000001b1200a986 */
/* 0x0001e8000c101904 */
/*0460*/ @!P1 LDG.E R6, [R20.64] ; /* 0x0000000414069981 */
/* 0x000e62000c1e1900 */
/*0470*/ IMAD R23, R0, 0x4, R15 ; /* 0x0000000400177824 */
/* 0x000fca00078e020f */
/*0480*/ ISETP.GE.AND P2, PT, R23, c[0x0][0x168], PT ; /* 0x00005a0017007a0c */
/* 0x000fda0003f46270 */
/*0490*/ @!P2 MOV R14, 0x4 ; /* 0x00000004000ea802 */
/* 0x000fca0000000f00 */
/*04a0*/ @!P2 IMAD.WIDE R14, R23, R14, c[0x0][0x160] ; /* 0x00005800170ea625 */
/* 0x000fc800078e020e */
/*04b0*/ @!P1 FMUL R25, R6, c[0x0][0x16c] ; /* 0x00005b0006199a20 */
/* 0x002fca0000400000 */
/*04c0*/ @!P1 STG.E [R20.64], R25 ; /* 0x0000001914009986 */
/* 0x0003e8000c101904 */
/*04d0*/ @!P2 LDG.E R6, [R14.64] ; /* 0x000000040e06a981 */
/* 0x000e22000c1e1900 */
/*04e0*/ IMAD R17, R0, 0x4, R13 ; /* 0x0000000400117824 */
/* 0x000fca00078e020d */
/*04f0*/ ISETP.GE.AND P1, PT, R17, c[0x0][0x168], PT ; /* 0x00005a0011007a0c */
/* 0x000fda0003f26270 */
/*0500*/ @!P1 MOV R12, 0x4 ; /* 0x00000004000c9802 */
/* 0x000fca0000000f00 */
/*0510*/ @!P1 IMAD.WIDE R12, R17, R12, c[0x0][0x160] ; /* 0x00005800110c9625 */
/* 0x000fc800078e020c */
/*0520*/ @!P2 FMUL R27, R6, c[0x0][0x16c] ; /* 0x00005b00061baa20 */
/* 0x001fca0000400000 */
/*0530*/ @!P2 STG.E [R14.64], R27 ; /* 0x0000001b0e00a986 */
/* 0x0001e8000c101904 */
/*0540*/ @!P1 LDG.E R6, [R12.64] ; /* 0x000000040c069981 */
/* 0x000e62000c1e1900 */
/*0550*/ IMAD R19, R0, 0x4, R11 ; /* 0x0000000400137824 */
/* 0x000fca00078e020b */
/*0560*/ ISETP.GE.AND P2, PT, R19, c[0x0][0x168], PT ; /* 0x00005a0013007a0c */
/* 0x000fda0003f46270 */
/*0570*/ @!P2 MOV R10, 0x4 ; /* 0x00000004000aa802 */
/* 0x000fca0000000f00 */
/*0580*/ @!P2 IMAD.WIDE R10, R19, R10, c[0x0][0x160] ; /* 0x00005800130aa625 */
/* 0x000fc800078e020a */
/*0590*/ @!P1 FMUL R25, R6, c[0x0][0x16c] ; /* 0x00005b0006199a20 */
/* 0x002fca0000400000 */
/*05a0*/ @!P1 STG.E [R12.64], R25 ; /* 0x000000190c009986 */
/* 0x0003e8000c101904 */
/*05b0*/ @!P2 LDG.E R6, [R10.64] ; /* 0x000000040a06a981 */
/* 0x000e22000c1e1900 */
/*05c0*/ IMAD R21, R0, 0x4, R9 ; /* 0x0000000400157824 */
/* 0x000fca00078e0209 */
/*05d0*/ ISETP.GE.AND P1, PT, R21, c[0x0][0x168], PT ; /* 0x00005a0015007a0c */
/* 0x000fda0003f26270 */
/*05e0*/ @!P1 MOV R8, 0x4 ; /* 0x0000000400089802 */
/* 0x000fca0000000f00 */
/*05f0*/ @!P1 IMAD.WIDE R8, R21, R8, c[0x0][0x160] ; /* 0x0000580015089625 */
/* 0x000fc800078e0208 */
/*0600*/ @!P2 FMUL R15, R6, c[0x0][0x16c] ; /* 0x00005b00060faa20 */
/* 0x001fca0000400000 */
/*0610*/ @!P2 STG.E [R10.64], R15 ; /* 0x0000000f0a00a986 */
/* 0x0001e8000c101904 */
/*0620*/ @!P1 LDG.E R6, [R8.64] ; /* 0x0000000408069981 */
/* 0x000ea2000c1e1900 */
/*0630*/ IMAD R23, R0, 0x4, R23 ; /* 0x0000000400177824 */
/* 0x000fca00078e0217 */
/*0640*/ ISETP.GE.AND P2, PT, R23, c[0x0][0x168], PT ; /* 0x00005a0017007a0c */
/* 0x000fda0003f46270 */
/*0650*/ @!P2 MOV R12, 0x4 ; /* 0x00000004000ca802 */
/* 0x002fca0000000f00 */
/*0660*/ @!P2 IMAD.WIDE R12, R23, R12, c[0x0][0x160] ; /* 0x00005800170ca625 */
/* 0x000fc800078e020c */
/*0670*/ @!P1 FMUL R25, R6, c[0x0][0x16c] ; /* 0x00005b0006199a20 */
/* 0x004fca0000400000 */
/*0680*/ @!P1 STG.E [R8.64], R25 ; /* 0x0000001908009986 */
/* 0x0003e8000c101904 */
/*0690*/ @!P2 LDG.E R6, [R12.64] ; /* 0x000000040c06a981 */
/* 0x000ea2000c1e1900 */
/*06a0*/ IMAD R17, R0, 0x4, R17 ; /* 0x0000000400117824 */
/* 0x000fca00078e0211 */
/*06b0*/ ISETP.GE.AND P1, PT, R17, c[0x0][0x168], PT ; /* 0x00005a0011007a0c */
/* 0x000fda0003f26270 */
/*06c0*/ @!P1 MOV R10, 0x4 ; /* 0x00000004000a9802 */
/* 0x001fca0000000f00 */
/*06d0*/ @!P1 IMAD.WIDE R10, R17, R10, c[0x0][0x160] ; /* 0x00005800110a9625 */
/* 0x000fc800078e020a */
/*06e0*/ @!P2 FMUL R15, R6, c[0x0][0x16c] ; /* 0x00005b00060faa20 */
/* 0x004fca0000400000 */
/*06f0*/ @!P2 STG.E [R12.64], R15 ; /* 0x0000000f0c00a986 */
/* 0x0001e8000c101904 */
/*0700*/ @!P1 LDG.E R6, [R10.64] ; /* 0x000000040a069981 */
/* 0x000ea2000c1e1900 */
/*0710*/ IMAD R19, R0, 0x4, R19 ; /* 0x0000000400137824 */
/* 0x000fca00078e0213 */
/*0720*/ ISETP.GE.AND P2, PT, R19, c[0x0][0x168], PT ; /* 0x00005a0013007a0c */
/* 0x000fda0003f46270 */
/*0730*/ @!P2 MOV R8, 0x4 ; /* 0x000000040008a802 */
/* 0x002fca0000000f00 */
/*0740*/ @!P2 IMAD.WIDE R8, R19, R8, c[0x0][0x160] ; /* 0x000058001308a625 */
/* 0x000fc800078e0208 */
/*0750*/ @!P1 FMUL R25, R6, c[0x0][0x16c] ; /* 0x00005b0006199a20 */
/* 0x004fca0000400000 */
/*0760*/ @!P1 STG.E [R10.64], R25 ; /* 0x000000190a009986 */
/* 0x0003e8000c101904 */
/*0770*/ @!P2 LDG.E R6, [R8.64] ; /* 0x000000040806a981 */
/* 0x000ea2000c1e1900 */
/*0780*/ IMAD R21, R0, 0x4, R21 ; /* 0x0000000400157824 */
/* 0x000fca00078e0215 */
/*0790*/ ISETP.GE.AND P1, PT, R21, c[0x0][0x168], PT ; /* 0x00005a0015007a0c */
/* 0x000fda0003f26270 */
/*07a0*/ @!P1 MOV R12, 0x4 ; /* 0x00000004000c9802 */
/* 0x001fca0000000f00 */
/*07b0*/ @!P1 IMAD.WIDE R12, R21, R12, c[0x0][0x160] ; /* 0x00005800150c9625 */
/* 0x000fc800078e020c */
/*07c0*/ @!P2 FMUL R27, R6, c[0x0][0x16c] ; /* 0x00005b00061baa20 */
/* 0x004fca0000400000 */
/*07d0*/ @!P2 STG.E [R8.64], R27 ; /* 0x0000001b0800a986 */
/* 0x0001e8000c101904 */
/*07e0*/ @!P1 LDG.E R6, [R12.64] ; /* 0x000000040c069981 */
/* 0x000ea2000c1e1900 */
/*07f0*/ IMAD R15, R0, 0x4, R23 ; /* 0x00000004000f7824 */
/* 0x000fca00078e0217 */
/*0800*/ ISETP.GE.AND P2, PT, R15, c[0x0][0x168], PT ; /* 0x00005a000f007a0c */
/* 0x000fda0003f46270 */
/*0810*/ @!P2 MOV R10, 0x4 ; /* 0x00000004000aa802 */
/* 0x002fca0000000f00 */
/*0820*/ @!P2 IMAD.WIDE R10, R15, R10, c[0x0][0x160] ; /* 0x000058000f0aa625 */
/* 0x000fc800078e020a */
/*0830*/ @!P1 FMUL R25, R6, c[0x0][0x16c] ; /* 0x00005b0006199a20 */
/* 0x004fca0000400000 */
/*0840*/ @!P1 STG.E [R12.64], R25 ; /* 0x000000190c009986 */
/* 0x0003e8000c101904 */
/*0850*/ @!P2 LDG.E R6, [R10.64] ; /* 0x000000040a06a981 */
/* 0x000ea2000c1e1900 */
/*0860*/ IMAD R17, R0, 0x4, R17 ; /* 0x0000000400117824 */
/* 0x000fca00078e0211 */
/*0870*/ ISETP.GE.AND P1, PT, R17, c[0x0][0x168], PT ; /* 0x00005a0011007a0c */
/* 0x000fda0003f26270 */
/*0880*/ @!P1 MOV R8, 0x4 ; /* 0x0000000400089802 */
/* 0x001fca0000000f00 */
/*0890*/ @!P1 IMAD.WIDE R8, R17, R8, c[0x0][0x160] ; /* 0x0000580011089625 */
/* 0x000fc800078e0208 */
/*08a0*/ @!P2 FMUL R27, R6, c[0x0][0x16c] ; /* 0x00005b00061baa20 */
/* 0x004fca0000400000 */
/*08b0*/ @!P2 STG.E [R10.64], R27 ; /* 0x0000001b0a00a986 */
/* 0x0001e8000c101904 */
/*08c0*/ @!P1 LDG.E R6, [R8.64] ; /* 0x0000000408069981 */
/* 0x000ea2000c1e1900 */
/*08d0*/ IMAD R23, R0, 0x4, R19 ; /* 0x0000000400177824 */
/* 0x000fca00078e0213 */
/*08e0*/ ISETP.GE.AND P2, PT, R23, c[0x0][0x168], PT ; /* 0x00005a0017007a0c */
/* 0x000fda0003f46270 */
/*08f0*/ @!P2 MOV R12, 0x4 ; /* 0x00000004000ca802 */
/* 0x002fca0000000f00 */
/*0900*/ @!P2 IMAD.WIDE R12, R23, R12, c[0x0][0x160] ; /* 0x00005800170ca625 */
/* 0x000fc800078e020c */
/*0910*/ @!P1 FMUL R25, R6, c[0x0][0x16c] ; /* 0x00005b0006199a20 */
/* 0x004fca0000400000 */
/*0920*/ @!P1 STG.E [R8.64], R25 ; /* 0x0000001908009986 */
/* 0x0003e8000c101904 */
/*0930*/ @!P2 LDG.E R6, [R12.64] ; /* 0x000000040c06a981 */
/* 0x000e22000c1e1900 */
/*0940*/ IMAD R29, R0, 0x4, R21 ; /* 0x00000004001d7824 */
/* 0x000fca00078e0215 */
/*0950*/ ISETP.GE.AND P1, PT, R29, c[0x0][0x168], PT ; /* 0x00005a001d007a0c */
/* 0x000fda0003f26270 */
/*0960*/ @!P1 MOV R18, 0x4 ; /* 0x0000000400129802 */
/* 0x000fca0000000f00 */
/*0970*/ @!P1 IMAD.WIDE R18, R29, R18, c[0x0][0x160] ; /* 0x000058001d129625 */
/* 0x000fc800078e0212 */
/*0980*/ @!P2 FMUL R11, R6, c[0x0][0x16c] ; /* 0x00005b00060baa20 */
/* 0x001fca0000400000 */
/*0990*/ @!P2 STG.E [R12.64], R11 ; /* 0x0000000b0c00a986 */
/* 0x0001e8000c101904 */
/*09a0*/ @!P1 LDG.E R6, [R18.64] ; /* 0x0000000412069981 */
/* 0x000ea2000c1e1900 */
/*09b0*/ IADD3 R7, R0.reuse, R7, R0.reuse ; /* 0x0000000700077210 */
/* 0x140fe20007ffe000 */
/*09c0*/ IMAD R15, R0.reuse, 0x4, R15 ; /* 0x00000004000f7824 */
/* 0x040fe200078e020f */
/*09d0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fe40007ffe0ff */
/*09e0*/ IADD3 R7, R0.reuse, R7, R0.reuse ; /* 0x0000000700077210 */
/* 0x140fe40007ffe000 */
/*09f0*/ LEA R9, R0.reuse, R29, 0x2 ; /* 0x0000001d00097211 */
/* 0x042fe200078e10ff */
/*0a00*/ IMAD R11, R0.reuse, 0x4, R23 ; /* 0x00000004000b7824 */
/* 0x041fe200078e0217 */
/*0a10*/ IADD3 R7, R0, R7, R0 ; /* 0x0000000700077210 */
/* 0x000fc40007ffe000 */
/*0a20*/ LEA R13, R0.reuse, R17, 0x2 ; /* 0x00000011000d7211 */
/* 0x040fe400078e10ff */
/*0a30*/ IADD3 R7, R0, R7, R0 ; /* 0x0000000700077210 */
/* 0x000fc80007ffe000 */
/*0a40*/ IADD3 R7, R0, R7, R0 ; /* 0x0000000700077210 */
/* 0x000fc80007ffe000 */
/*0a50*/ IADD3 R7, R0, R7, R0 ; /* 0x0000000700077210 */
/* 0x000fc80007ffe000 */
/*0a60*/ IADD3 R7, R0, R7, R0 ; /* 0x0000000700077210 */
/* 0x000fc80007ffe000 */
/*0a70*/ IADD3 R7, R0, R7, R0 ; /* 0x0000000700077210 */
/* 0x000fe20007ffe000 */
/*0a80*/ @!P1 FMUL R21, R6, c[0x0][0x16c] ; /* 0x00005b0006159a20 */
/* 0x004fca0000400000 */
/*0a90*/ @!P1 STG.E [R18.64], R21 ; /* 0x0000001512009986 */
/* 0x0001e2000c101904 */
/*0aa0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fda0003f24270 */
/*0ab0*/ @P1 BRA 0x310 ; /* 0xfffff85000001947 */
/* 0x001fea000383ffff */
/*0ac0*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*0ad0*/ @!P1 BRA 0xed0 ; /* 0x000003f000009947 */
/* 0x000fea0003800000 */
/*0ae0*/ ISETP.GE.AND P0, PT, R15, c[0x0][0x168], PT ; /* 0x00005a000f007a0c */
/* 0x000fda0003f06270 */
/*0af0*/ @!P0 IMAD.MOV.U32 R20, RZ, RZ, 0x4 ; /* 0x00000004ff148424 */
/* 0x000fc800078e00ff */
/*0b00*/ @!P0 IMAD.WIDE R20, R15, R20, c[0x0][0x160] ; /* 0x000058000f148625 */
/* 0x000fca00078e0214 */
/*0b10*/ @!P0 LDG.E R6, [R20.64] ; /* 0x0000000414068981 */
/* 0x000ea2000c1e1900 */
/*0b20*/ ISETP.GE.AND P1, PT, R13, c[0x0][0x168], PT ; /* 0x00005a000d007a0c */
/* 0x000fda0003f26270 */
/*0b30*/ @!P1 MOV R16, 0x4 ; /* 0x0000000400109802 */
/* 0x000fca0000000f00 */
/*0b40*/ @!P1 IMAD.WIDE R16, R13, R16, c[0x0][0x160] ; /* 0x000058000d109625 */
/* 0x000fc800078e0210 */
/*0b50*/ @!P0 FMUL R23, R6, c[0x0][0x16c] ; /* 0x00005b0006178a20 */
/* 0x004fca0000400000 */
/*0b60*/ @!P0 STG.E [R20.64], R23 ; /* 0x0000001714008986 */
/* 0x0001e8000c101904 */
/*0b70*/ @!P1 LDG.E R6, [R16.64] ; /* 0x0000000410069981 */
/* 0x000ea2000c1e1900 */
/*0b80*/ ISETP.GE.AND P0, PT, R11, c[0x0][0x168], PT ; /* 0x00005a000b007a0c */
/* 0x000fda0003f06270 */
/*0b90*/ @!P0 IMAD.MOV.U32 R18, RZ, RZ, 0x4 ; /* 0x00000004ff128424 */
/* 0x000fc800078e00ff */
/*0ba0*/ @!P0 IMAD.WIDE R18, R11, R18, c[0x0][0x160] ; /* 0x000058000b128625 */
/* 0x000fc800078e0212 */
/*0bb0*/ @!P1 FMUL R25, R6, c[0x0][0x16c] ; /* 0x00005b0006199a20 */
/* 0x004fca0000400000 */
/*0bc0*/ @!P1 STG.E [R16.64], R25 ; /* 0x0000001910009986 */
/* 0x0003e8000c101904 */
/*0bd0*/ @!P0 LDG.E R6, [R18.64] ; /* 0x0000000412068981 */
/* 0x000ea2000c1e1900 */
/*0be0*/ ISETP.GE.AND P1, PT, R9, c[0x0][0x168], PT ; /* 0x00005a0009007a0c */
/* 0x000fda0003f26270 */
/*0bf0*/ @!P1 MOV R8, 0x4 ; /* 0x0000000400089802 */
/* 0x000fca0000000f00 */
/*0c00*/ @!P1 IMAD.WIDE R20, R9, R8, c[0x0][0x160] ; /* 0x0000580009149625 */
/* 0x001fc800078e0208 */
/*0c10*/ @!P0 FMUL R27, R6, c[0x0][0x16c] ; /* 0x00005b00061b8a20 */
/* 0x004fca0000400000 */
/*0c20*/ @!P0 STG.E [R18.64], R27 ; /* 0x0000001b12008986 */
/* 0x0001e8000c101904 */
/*0c30*/ @!P1 LDG.E R6, [R20.64] ; /* 0x0000000414069981 */
/* 0x000e62000c1e1900 */
/*0c40*/ IMAD R23, R0, 0x4, R15 ; /* 0x0000000400177824 */
/* 0x000fca00078e020f */
/*0c50*/ ISETP.GE.AND P0, PT, R23, c[0x0][0x168], PT ; /* 0x00005a0017007a0c */
/* 0x000fda0003f06270 */
/*0c60*/ @!P0 MOV R14, 0x4 ; /* 0x00000004000e8802 */
/* 0x000fca0000000f00 */
/*0c70*/ @!P0 IMAD.WIDE R14, R23, R14, c[0x0][0x160] ; /* 0x00005800170e8625 */
/* 0x000fc800078e020e */
/*0c80*/ @!P1 FMUL R25, R6, c[0x0][0x16c] ; /* 0x00005b0006199a20 */
/* 0x002fca0000400000 */
/*0c90*/ @!P1 STG.E [R20.64], R25 ; /* 0x0000001914009986 */
/* 0x0003e8000c101904 */
/*0ca0*/ @!P0 LDG.E R6, [R14.64] ; /* 0x000000040e068981 */
/* 0x000e22000c1e1900 */
/*0cb0*/ IMAD R17, R0, 0x4, R13 ; /* 0x0000000400117824 */
/* 0x000fca00078e020d */
/*0cc0*/ ISETP.GE.AND P1, PT, R17, c[0x0][0x168], PT ; /* 0x00005a0011007a0c */
/* 0x000fda0003f26270 */
/*0cd0*/ @!P1 MOV R12, 0x4 ; /* 0x00000004000c9802 */
/* 0x000fca0000000f00 */
/*0ce0*/ @!P1 IMAD.WIDE R12, R17, R12, c[0x0][0x160] ; /* 0x00005800110c9625 */
/* 0x000fc800078e020c */
/*0cf0*/ @!P0 FMUL R27, R6, c[0x0][0x16c] ; /* 0x00005b00061b8a20 */
/* 0x001fca0000400000 */
/*0d00*/ @!P0 STG.E [R14.64], R27 ; /* 0x0000001b0e008986 */
/* 0x0001e8000c101904 */
/*0d10*/ @!P1 LDG.E R6, [R12.64] ; /* 0x000000040c069981 */
/* 0x000e62000c1e1900 */
/*0d20*/ IMAD R19, R0, 0x4, R11 ; /* 0x0000000400137824 */
/* 0x000fca00078e020b */
/*0d30*/ ISETP.GE.AND P0, PT, R19, c[0x0][0x168], PT ; /* 0x00005a0013007a0c */
/* 0x000fda0003f06270 */
/*0d40*/ @!P0 MOV R10, 0x4 ; /* 0x00000004000a8802 */
/* 0x000fca0000000f00 */
/*0d50*/ @!P0 IMAD.WIDE R10, R19, R10, c[0x0][0x160] ; /* 0x00005800130a8625 */
/* 0x000fc800078e020a */
/*0d60*/ @!P1 FMUL R21, R6, c[0x0][0x16c] ; /* 0x00005b0006159a20 */
/* 0x002fca0000400000 */
/*0d70*/ @!P1 STG.E [R12.64], R21 ; /* 0x000000150c009986 */
/* 0x000fe8000c101904 */
/*0d80*/ @!P0 LDG.E R6, [R10.64] ; /* 0x000000040a068981 */
/* 0x000e22000c1e1900 */
/*0d90*/ IMAD R29, R0, 0x4, R9 ; /* 0x00000004001d7824 */
/* 0x000fca00078e0209 */
/*0da0*/ ISETP.GE.AND P1, PT, R29, c[0x0][0x168], PT ; /* 0x00005a001d007a0c */
/* 0x000fda0003f26270 */
/*0db0*/ @!P1 MOV R8, 0x4 ; /* 0x0000000400089802 */
/* 0x000fca0000000f00 */
/*0dc0*/ @!P1 IMAD.WIDE R8, R29, R8, c[0x0][0x160] ; /* 0x000058001d089625 */
/* 0x000fc800078e0208 */
/*0dd0*/ @!P0 FMUL R15, R6, c[0x0][0x16c] ; /* 0x00005b00060f8a20 */
/* 0x001fca0000400000 */
/*0de0*/ @!P0 STG.E [R10.64], R15 ; /* 0x0000000f0a008986 */
/* 0x0001e8000c101904 */
/*0df0*/ @!P1 LDG.E R6, [R8.64] ; /* 0x0000000408069981 */
/* 0x000ea2000c1e1900 */
/*0e00*/ IADD3 R7, R0.reuse, R7, R0.reuse ; /* 0x0000000700077210 */
/* 0x140fe40007ffe000 */
/*0e10*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fe40007ffe0ff */
/*0e20*/ IADD3 R7, R0.reuse, R7, R0.reuse ; /* 0x0000000700077210 */
/* 0x140fe40007ffe000 */
/*0e30*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0e40*/ IMAD R15, R0.reuse, 0x4, R23 ; /* 0x00000004000f7824 */
/* 0x041fe200078e0217 */
/*0e50*/ IADD3 R7, R0.reuse, R7, R0 ; /* 0x0000000700077210 */
/* 0x040fe20007ffe000 */
/*0e60*/ IMAD R11, R0, 0x4, R19 ; /* 0x00000004000b7824 */
/* 0x000fe200078e0213 */
/*0e70*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc40007ffe0ff */
/*0e80*/ IADD3 R7, R0.reuse, R7, R0 ; /* 0x0000000700077210 */
/* 0x040fe40007ffe000 */
/*0e90*/ LEA R13, R0, R17, 0x2 ; /* 0x00000011000d7211 */
/* 0x000fe200078e10ff */
/*0ea0*/ @!P1 FMUL R25, R6, c[0x0][0x16c] ; /* 0x00005b0006199a20 */
/* 0x004fca0000400000 */
/*0eb0*/ @!P1 STG.E [R8.64], R25 ; /* 0x0000001908009986 */
/* 0x0001e4000c101904 */
/*0ec0*/ LEA R9, R0, R29, 0x2 ; /* 0x0000001d00097211 */
/* 0x001fe400078e10ff */
/*0ed0*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0ee0*/ @!P0 BRA 0x1100 ; /* 0x0000021000008947 */
/* 0x000fea0003800000 */
/*0ef0*/ ISETP.GE.AND P0, PT, R15, c[0x0][0x168], PT ; /* 0x00005a000f007a0c */
/* 0x000fda0003f06270 */
/*0f00*/ @!P0 IMAD.MOV.U32 R20, RZ, RZ, 0x4 ; /* 0x00000004ff148424 */
/* 0x000fc800078e00ff */
/*0f10*/ @!P0 IMAD.WIDE R20, R15, R20, c[0x0][0x160] ; /* 0x000058000f148625 */
/* 0x000fca00078e0214 */
/*0f20*/ @!P0 LDG.E R6, [R20.64] ; /* 0x0000000414068981 */
/* 0x000ea2000c1e1900 */
/*0f30*/ ISETP.GE.AND P1, PT, R13, c[0x0][0x168], PT ; /* 0x00005a000d007a0c */
/* 0x000fda0003f26270 */
/*0f40*/ @!P1 MOV R16, 0x4 ; /* 0x0000000400109802 */
/* 0x000fca0000000f00 */
/*0f50*/ @!P1 IMAD.WIDE R16, R13, R16, c[0x0][0x160] ; /* 0x000058000d109625 */
/* 0x000fc800078e0210 */
/*0f60*/ @!P0 FMUL R23, R6, c[0x0][0x16c] ; /* 0x00005b0006178a20 */
/* 0x004fca0000400000 */
/*0f70*/ @!P0 STG.E [R20.64], R23 ; /* 0x0000001714008986 */
/* 0x0001e8000c101904 */
/*0f80*/ @!P1 LDG.E R6, [R16.64] ; /* 0x0000000410069981 */
/* 0x000ea2000c1e1900 */
/*0f90*/ ISETP.GE.AND P0, PT, R11, c[0x0][0x168], PT ; /* 0x00005a000b007a0c */
/* 0x000fda0003f06270 */
/*0fa0*/ @!P0 IMAD.MOV.U32 R18, RZ, RZ, 0x4 ; /* 0x00000004ff128424 */
/* 0x000fc800078e00ff */
/*0fb0*/ @!P0 IMAD.WIDE R18, R11, R18, c[0x0][0x160] ; /* 0x000058000b128625 */
/* 0x000fc800078e0212 */
/*0fc0*/ @!P1 FMUL R25, R6, c[0x0][0x16c] ; /* 0x00005b0006199a20 */
/* 0x004fca0000400000 */
/*0fd0*/ @!P1 STG.E [R16.64], R25 ; /* 0x0000001910009986 */
/* 0x0003e8000c101904 */
/*0fe0*/ @!P0 LDG.E R6, [R18.64] ; /* 0x0000000412068981 */
/* 0x000ea2000c1e1900 */
/*0ff0*/ ISETP.GE.AND P1, PT, R9, c[0x0][0x168], PT ; /* 0x00005a0009007a0c */
/* 0x000fda0003f26270 */
/*1000*/ @!P1 MOV R8, 0x4 ; /* 0x0000000400089802 */
/* 0x000fca0000000f00 */
/*1010*/ @!P1 IMAD.WIDE R20, R9, R8, c[0x0][0x160] ; /* 0x0000580009149625 */
/* 0x001fc800078e0208 */
/*1020*/ @!P0 FMUL R27, R6, c[0x0][0x16c] ; /* 0x00005b00061b8a20 */
/* 0x004fca0000400000 */
/*1030*/ @!P0 STG.E [R18.64], R27 ; /* 0x0000001b12008986 */
/* 0x0003e8000c101904 */
/*1040*/ @!P1 LDG.E R6, [R20.64] ; /* 0x0000000414069981 */
/* 0x000ea2000c1e1900 */
/*1050*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fe20007ffe0ff */
/*1060*/ IMAD R15, R0.reuse, 0x4, R15 ; /* 0x00000004000f7824 */
/* 0x040fe200078e020f */
/*1070*/ IADD3 R7, R0.reuse, R7, R0.reuse ; /* 0x0000000700077210 */
/* 0x140fe20007ffe000 */
/*1080*/ IMAD R11, R0.reuse, 0x4, R11 ; /* 0x00000004000b7824 */
/* 0x040fe200078e020b */
/*1090*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f05270 */
/*10a0*/ IADD3 R7, R0, R7, R0 ; /* 0x0000000700077210 */
/* 0x000fc40007ffe000 */
/*10b0*/ LEA R13, R0.reuse, R13, 0x2 ; /* 0x0000000d000d7211 */
/* 0x040fe400078e10ff */
/*10c0*/ LEA R9, R0, R9, 0x2 ; /* 0x0000000900097211 */
/* 0x000fe200078e10ff */
/*10d0*/ @!P1 FMUL R23, R6, c[0x0][0x16c] ; /* 0x00005b0006179a20 */
/* 0x004fca0000400000 */
/*10e0*/ @!P1 STG.E [R20.64], R23 ; /* 0x0000001714009986 */
/* 0x0003e4000c101904 */
/*10f0*/ @P0 BRA 0xef0 ; /* 0xfffffdf000000947 */
/* 0x002fea000383ffff */
/*1100*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x003fda0003f05270 */
/*1110*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*1120*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fe200000001ff */
/*1130*/ IMAD.IADD R3, R7, 0x1, R3 ; /* 0x0000000107037824 */
/* 0x000fc800078e0203 */
/*1140*/ IMAD R5, R2, c[0x0][0x0], R3 ; /* 0x0000000002057a24 */
/* 0x000fca00078e0203 */
/*1150*/ IMAD.WIDE R2, R5, R6, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fc800078e0206 */
/*1160*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fda0003f06270 */
/*1170*/ @!P0 LDG.E R6, [R2.64] ; /* 0x0000000402068981 */
/* 0x000ea2000c1e1900 */
/*1180*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*1190*/ IMAD.IADD R5, R0, 0x1, R5 ; /* 0x0000000100057824 */
/* 0x000fe400078e0205 */
/*11a0*/ @!P0 FMUL R7, R6, c[0x0][0x16c] ; /* 0x00005b0006078a20 */
/* 0x004fca0000400000 */
/*11b0*/ @!P0 STG.E [R2.64], R7 ; /* 0x0000000702008986 */
/* 0x0001e2000c101904 */
/*11c0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*11d0*/ IMAD.WIDE R2, R0, 0x4, R2 ; /* 0x0000000400027825 */
/* 0x001fd800078e0202 */
/*11e0*/ @P0 BRA 0x1160 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*11f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1200*/ BRA 0x1200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void dropout_test(float* data, int size, float probability)
{
int thread_index = threadIdx.x + blockIdx.x * blockDim.x;
int num_threads = blockDim.x * gridDim.x;
for(int i = 0; i < size; i += num_threads)
{
int index = i + thread_index;
if(index < size)
{
data[index] = data[index] * probability;
}
}
} | .file "tmpxft_00087e6f_00000000-6_dropout_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z12dropout_testPfifPfif
.type _Z34__device_stub__Z12dropout_testPfifPfif, @function
_Z34__device_stub__Z12dropout_testPfifPfif:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movss %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12dropout_testPfif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z12dropout_testPfifPfif, .-_Z34__device_stub__Z12dropout_testPfifPfif
.globl _Z12dropout_testPfif
.type _Z12dropout_testPfif, @function
_Z12dropout_testPfif:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z12dropout_testPfifPfif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12dropout_testPfif, .-_Z12dropout_testPfif
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12dropout_testPfif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12dropout_testPfif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void dropout_test(float* data, int size, float probability)
{
int thread_index = threadIdx.x + blockIdx.x * blockDim.x;
int num_threads = blockDim.x * gridDim.x;
for(int i = 0; i < size; i += num_threads)
{
int index = i + thread_index;
if(index < size)
{
data[index] = data[index] * probability;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void dropout_test(float* data, int size, float probability)
{
int thread_index = threadIdx.x + blockIdx.x * blockDim.x;
int num_threads = blockDim.x * gridDim.x;
for(int i = 0; i < size; i += num_threads)
{
int index = i + thread_index;
if(index < size)
{
data[index] = data[index] * probability;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void dropout_test(float* data, int size, float probability)
{
int thread_index = threadIdx.x + blockIdx.x * blockDim.x;
int num_threads = blockDim.x * gridDim.x;
for(int i = 0; i < size; i += num_threads)
{
int index = i + thread_index;
if(index < size)
{
data[index] = data[index] * probability;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12dropout_testPfif
.globl _Z12dropout_testPfif
.p2align 8
.type _Z12dropout_testPfif,@function
_Z12dropout_testPfif:
s_load_b32 s4, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_5
s_clause 0x2
s_load_b32 s5, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0xc
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
s_mul_i32 s3, s3, s5
s_mov_b32 s5, 0
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s6
s_add_i32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s5, s4
s_cbranch_scc1 .LBB0_5
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, s5, v1
s_mov_b32 s6, exec_lo
v_cmpx_gt_i32_e64 s4, v2
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v0, s2, v0
global_store_b32 v[2:3], v0, off
s_branch .LBB0_2
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12dropout_testPfif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12dropout_testPfif, .Lfunc_end0-_Z12dropout_testPfif
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12dropout_testPfif
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12dropout_testPfif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void dropout_test(float* data, int size, float probability)
{
int thread_index = threadIdx.x + blockIdx.x * blockDim.x;
int num_threads = blockDim.x * gridDim.x;
for(int i = 0; i < size; i += num_threads)
{
int index = i + thread_index;
if(index < size)
{
data[index] = data[index] * probability;
}
}
} | .text
.file "dropout_test.hip"
.globl _Z27__device_stub__dropout_testPfif # -- Begin function _Z27__device_stub__dropout_testPfif
.p2align 4, 0x90
.type _Z27__device_stub__dropout_testPfif,@function
_Z27__device_stub__dropout_testPfif: # @_Z27__device_stub__dropout_testPfif
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movss %xmm0, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12dropout_testPfif, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__dropout_testPfif, .Lfunc_end0-_Z27__device_stub__dropout_testPfif
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12dropout_testPfif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12dropout_testPfif,@object # @_Z12dropout_testPfif
.section .rodata,"a",@progbits
.globl _Z12dropout_testPfif
.p2align 3, 0x0
_Z12dropout_testPfif:
.quad _Z27__device_stub__dropout_testPfif
.size _Z12dropout_testPfif, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12dropout_testPfif"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__dropout_testPfif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12dropout_testPfif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00087e6f_00000000-6_dropout_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z12dropout_testPfifPfif
.type _Z34__device_stub__Z12dropout_testPfifPfif, @function
_Z34__device_stub__Z12dropout_testPfifPfif:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movss %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12dropout_testPfif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z12dropout_testPfifPfif, .-_Z34__device_stub__Z12dropout_testPfifPfif
.globl _Z12dropout_testPfif
.type _Z12dropout_testPfif, @function
_Z12dropout_testPfif:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z12dropout_testPfifPfif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12dropout_testPfif, .-_Z12dropout_testPfif
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12dropout_testPfif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12dropout_testPfif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "dropout_test.hip"
.globl _Z27__device_stub__dropout_testPfif # -- Begin function _Z27__device_stub__dropout_testPfif
.p2align 4, 0x90
.type _Z27__device_stub__dropout_testPfif,@function
_Z27__device_stub__dropout_testPfif: # @_Z27__device_stub__dropout_testPfif
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movss %xmm0, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12dropout_testPfif, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__dropout_testPfif, .Lfunc_end0-_Z27__device_stub__dropout_testPfif
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12dropout_testPfif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12dropout_testPfif,@object # @_Z12dropout_testPfif
.section .rodata,"a",@progbits
.globl _Z12dropout_testPfif
.p2align 3, 0x0
_Z12dropout_testPfif:
.quad _Z27__device_stub__dropout_testPfif
.size _Z12dropout_testPfif, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12dropout_testPfif"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__dropout_testPfif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12dropout_testPfif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C"
__global__ void calcDir(// Dots props
float* pX,
float* pY,
float* pZ,
//Tree specs
// per Block
//int* dotIndexes,
float* avgPX,
float* avgPY,
float* avgPZ,
int* idFurthest,
// per GPU Block
// output values, per block
float* dirX,
float* dirY,
float* dirZ,
float nBlocs
)
{
int idBloc = blockIdx.x*blockDim.x+threadIdx.x;
if (idBloc<nBlocs) {
int mx=avgPX[idBloc];
int my=avgPY[idBloc];
int mz=avgPZ[idBloc];
int idPtFurthest = idFurthest[idBloc];
float dx=pX[idPtFurthest]-mx;
float dy=pY[idPtFurthest]-my;
float dz=pZ[idPtFurthest]-mz;
float dist = sqrtf(dx*dx+dy*dy+dz*dz);
dirX[idBloc]=dx/dist;
dirY[idBloc]=dy/dist;
dirZ[idBloc]=dz/dist;
}
} | code for sm_80
Function : calcDir
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0040*/ I2F R2, R0 ; /* 0x0000000000027306 */
/* 0x000e240000201400 */
/*0050*/ FSETP.GEU.AND P0, PT, R2, c[0x0][0x1b0], PT ; /* 0x00006c0002007a0b */
/* 0x001fda0003f0e000 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ IMAD.WIDE R8, R0, R15, c[0x0][0x190] ; /* 0x0000640000087625 */
/* 0x000fcc00078e020f */
/*00a0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ IMAD.WIDE R4, R0, R15, c[0x0][0x180] ; /* 0x0000600000047625 */
/* 0x000fc800078e020f */
/*00c0*/ IMAD.WIDE R2, R0.reuse, R15.reuse, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x0c0fe400078e020f */
/*00d0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ee4000c1e1900 */
/*00e0*/ IMAD.WIDE R6, R0, R15.reuse, c[0x0][0x188] ; /* 0x0000620000067625 */
/* 0x080fe400078e020f */
/*00f0*/ LDG.E R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000f28000c1e1900 */
/*0100*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f62000c1e1900 */
/*0110*/ IMAD.WIDE R12, R8, R15, c[0x0][0x168] ; /* 0x00005a00080c7625 */
/* 0x004fc800078e020f */
/*0120*/ IMAD.WIDE R10, R8.reuse, R15.reuse, c[0x0][0x160] ; /* 0x00005800080a7625 */
/* 0x0c0fe400078e020f */
/*0130*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000ea4000c1e1900 */
/*0140*/ IMAD.WIDE R14, R8, R15, c[0x0][0x170] ; /* 0x00005c00080e7625 */
/* 0x000fe400078e020f */
/*0150*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ea8000c1e1900 */
/*0160*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea2000c1e1900 */
/*0170*/ F2I.TRUNC.NTZ R8, R5 ; /* 0x0000000500087305 */
/* 0x008e30000020f100 */
/*0180*/ F2I.TRUNC.NTZ R16, R16 ; /* 0x0000001000107305 */
/* 0x010e70000020f100 */
/*0190*/ F2I.TRUNC.NTZ R9, R6 ; /* 0x0000000600097305 */
/* 0x020ef0000020f100 */
/*01a0*/ I2F R2, R8 ; /* 0x0000000800027306 */
/* 0x001eb00000201400 */
/*01b0*/ I2F R4, R16 ; /* 0x0000001000047306 */
/* 0x002e300000201400 */
/*01c0*/ I2F R3, R9 ; /* 0x0000000900037306 */
/* 0x008e620000201400 */
/*01d0*/ BSSY B0, 0x300 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*01e0*/ FADD R2, -R2, R13 ; /* 0x0000000d02027221 */
/* 0x004fc40000000100 */
/*01f0*/ FADD R4, -R4, R11 ; /* 0x0000000b04047221 */
/* 0x001fe40000000100 */
/*0200*/ FMUL R7, R2, R2 ; /* 0x0000000202077220 */
/* 0x000fe40000400000 */
/*0210*/ FADD R3, -R3, R14 ; /* 0x0000000e03037221 */
/* 0x002fe40000000100 */
/*0220*/ FFMA R10, R4, R4, R7 ; /* 0x00000004040a7223 */
/* 0x000fc80000000007 */
/*0230*/ FFMA R10, R3, R3, R10 ; /* 0x00000003030a7223 */
/* 0x000fca000000000a */
/*0240*/ IADD3 R7, R10, -0xd000000, RZ ; /* 0xf30000000a077810 */
/* 0x000fe20007ffe0ff */
/*0250*/ MUFU.RSQ R5, R10 ; /* 0x0000000a00057308 */
/* 0x0000660000001400 */
/*0260*/ ISETP.GT.U32.AND P0, PT, R7, 0x727fffff, PT ; /* 0x727fffff0700780c */
/* 0x000fda0003f04070 */
/*0270*/ @!P0 BRA 0x2b0 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0280*/ MOV R11, 0x2a0 ; /* 0x000002a0000b7802 */
/* 0x003fe40000000f00 */
/*0290*/ CALL.REL.NOINC 0x620 ; /* 0x0000038000007944 */
/* 0x000fea0003c00000 */
/*02a0*/ BRA 0x2f0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*02b0*/ FMUL.FTZ R7, R10, R5 ; /* 0x000000050a077220 */
/* 0x003fe40000410000 */
/*02c0*/ FMUL.FTZ R5, R5, 0.5 ; /* 0x3f00000005057820 */
/* 0x000fe40000410000 */
/*02d0*/ FFMA R10, -R7, R7, R10 ; /* 0x00000007070a7223 */
/* 0x000fc8000000010a */
/*02e0*/ FFMA R5, R10, R5, R7 ; /* 0x000000050a057223 */
/* 0x000fe40000000007 */
/*02f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0300*/ MUFU.RCP R6, R5 ; /* 0x0000000500067308 */
/* 0x000e220000001000 */
/*0310*/ BSSY B0, 0x3d0 ; /* 0x000000b000007945 */
/* 0x000fee0003800000 */
/*0320*/ FCHK P0, R4, R5 ; /* 0x0000000504007302 */
/* 0x000e620000000000 */
/*0330*/ FFMA R7, R6, -R5, 1 ; /* 0x3f80000006077423 */
/* 0x001fc80000000805 */
/*0340*/ FFMA R7, R6, R7, R6 ; /* 0x0000000706077223 */
/* 0x000fc80000000006 */
/*0350*/ FFMA R6, R4, R7, RZ ; /* 0x0000000704067223 */
/* 0x000fc800000000ff */
/*0360*/ FFMA R8, R6, -R5, R4 ; /* 0x8000000506087223 */
/* 0x000fc80000000004 */
/*0370*/ FFMA R9, R7, R8, R6 ; /* 0x0000000807097223 */
/* 0x000fe20000000006 */
/*0380*/ @!P0 BRA 0x3c0 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*0390*/ MOV R9, R4 ; /* 0x0000000400097202 */
/* 0x000fe40000000f00 */
/*03a0*/ MOV R4, 0x3c0 ; /* 0x000003c000047802 */
/* 0x000fe40000000f00 */
/*03b0*/ CALL.REL.NOINC 0x780 ; /* 0x000003c000007944 */
/* 0x000fea0003c00000 */
/*03c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03d0*/ MUFU.RCP R4, R5 ; /* 0x0000000500047308 */
/* 0x000e220000001000 */
/*03e0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*03f0*/ BSSY B0, 0x4e0 ; /* 0x000000e000007945 */
/* 0x000fe60003800000 */
/*0400*/ IMAD.WIDE R6, R0, R7, c[0x0][0x198] ; /* 0x0000660000067625 */
/* 0x000fc600078e0207 */
/*0410*/ FCHK P0, R2, R5 ; /* 0x0000000502007302 */
/* 0x000e640000000000 */
/*0420*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0005e2000c101904 */
/*0430*/ FFMA R11, R4, -R5, 1 ; /* 0x3f800000040b7423 */
/* 0x001fc80000000805 */
/*0440*/ FFMA R13, R4, R11, R4 ; /* 0x0000000b040d7223 */
/* 0x000fc80000000004 */
/*0450*/ FFMA R4, R2, R13, RZ ; /* 0x0000000d02047223 */
/* 0x000fc800000000ff */
/*0460*/ FFMA R11, R4, -R5, R2 ; /* 0x80000005040b7223 */
/* 0x000fc80000000002 */
/*0470*/ FFMA R11, R13, R11, R4 ; /* 0x0000000b0d0b7223 */
/* 0x000fe20000000004 */
/*0480*/ @!P0 BRA 0x4d0 ; /* 0x0000004000008947 */
/* 0x002fea0003800000 */
/*0490*/ IMAD.MOV.U32 R9, RZ, RZ, R2 ; /* 0x000000ffff097224 */
/* 0x004fe200078e0002 */
/*04a0*/ MOV R4, 0x4c0 ; /* 0x000004c000047802 */
/* 0x000fe40000000f00 */
/*04b0*/ CALL.REL.NOINC 0x780 ; /* 0x000002c000007944 */
/* 0x000fea0003c00000 */
/*04c0*/ MOV R11, R9 ; /* 0x00000009000b7202 */
/* 0x000fe40000000f00 */
/*04d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x004fea0003800000 */
/*04e0*/ MUFU.RCP R2, R5 ; /* 0x0000000500027308 */
/* 0x000e220000001000 */
/*04f0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0500*/ BSSY B0, 0x5e0 ; /* 0x000000d000007945 */
/* 0x000fe60003800000 */
/*0510*/ IMAD.WIDE R6, R0, R7, c[0x0][0x1a0] ; /* 0x0000680000067625 */
/* 0x000fc600078e0207 */
/*0520*/ FCHK P0, R3, R5 ; /* 0x0000000503007302 */
/* 0x000e640000000000 */
/*0530*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0005e2000c101904 */
/*0540*/ FFMA R9, R2, -R5, 1 ; /* 0x3f80000002097423 */
/* 0x001fc80000000805 */
/*0550*/ FFMA R4, R2, R9, R2 ; /* 0x0000000902047223 */
/* 0x000fc80000000002 */
/*0560*/ FFMA R2, R3, R4, RZ ; /* 0x0000000403027223 */
/* 0x000fc800000000ff */
/*0570*/ FFMA R9, R2, -R5, R3 ; /* 0x8000000502097223 */
/* 0x000fc80000000003 */
/*0580*/ FFMA R9, R4, R9, R2 ; /* 0x0000000904097223 */
/* 0x000fe20000000002 */
/*0590*/ @!P0 BRA 0x5d0 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*05a0*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x004fe200078e0003 */
/*05b0*/ MOV R4, 0x5d0 ; /* 0x000005d000047802 */
/* 0x000fe40000000f00 */
/*05c0*/ CALL.REL.NOINC 0x780 ; /* 0x000001b000007944 */
/* 0x000fea0003c00000 */
/*05d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x004fea0003800000 */
/*05e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*05f0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x1a8] ; /* 0x00006a0000027625 */
/* 0x000fca00078e0203 */
/*0600*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*0610*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0620*/ LOP3.LUT P0, RZ, R10, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0aff7812 */
/* 0x000fda000780c0ff */
/*0630*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff058224 */
/* 0x000fe200078e000a */
/*0640*/ @!P0 BRA 0x750 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0650*/ FSETP.GEU.FTZ.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720b */
/* 0x000fda0003f1e000 */
/*0660*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, 0x7fffffff ; /* 0x7fffffffff058424 */
/* 0x000fe200078e00ff */
/*0670*/ @!P0 BRA 0x750 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0680*/ FSETP.GTU.FTZ.AND P0, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fda0003f1c200 */
/*0690*/ @P0 FADD.FTZ R5, R10, 1 ; /* 0x3f8000000a050421 */
/* 0x000fe20000010000 */
/*06a0*/ @P0 BRA 0x750 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*06b0*/ FSETP.NEU.FTZ.AND P0, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fda0003f1d200 */
/*06c0*/ @P0 FFMA R6, R10, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000a060823 */
/* 0x000fc800000000ff */
/*06d0*/ @P0 MUFU.RSQ R5, R6 ; /* 0x0000000600050308 */
/* 0x000e240000001400 */
/*06e0*/ @P0 FMUL.FTZ R7, R6, R5 ; /* 0x0000000506070220 */
/* 0x001fe40000410000 */
/*06f0*/ @P0 FMUL.FTZ R9, R5, 0.5 ; /* 0x3f00000005090820 */
/* 0x000fe20000410000 */
/*0700*/ @!P0 MOV R5, R10 ; /* 0x0000000a00058202 */
/* 0x000fe20000000f00 */
/*0710*/ @P0 FADD.FTZ R8, -R7, -RZ ; /* 0x800000ff07080221 */
/* 0x000fc80000010100 */
/*0720*/ @P0 FFMA R8, R7, R8, R6 ; /* 0x0000000807080223 */
/* 0x000fc80000000006 */
/*0730*/ @P0 FFMA R8, R8, R9, R7 ; /* 0x0000000908080223 */
/* 0x000fc80000000007 */
/*0740*/ @P0 FMUL.FTZ R5, R8, 2.3283064365386962891e-10 ; /* 0x2f80000008050820 */
/* 0x000fe40000410000 */
/*0750*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*0760*/ IMAD.MOV.U32 R6, RZ, RZ, R11 ; /* 0x000000ffff067224 */
/* 0x000fca00078e000b */
/*0770*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff88006007950 */
/* 0x000fea0003c3ffff */
/*0780*/ SHF.R.U32.HI R7, RZ, 0x17, R5 ; /* 0x00000017ff077819 */
/* 0x000fe20000011605 */
/*0790*/ BSSY B1, 0xde0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*07a0*/ SHF.R.U32.HI R6, RZ, 0x17, R9.reuse ; /* 0x00000017ff067819 */
/* 0x100fe40000011609 */
/*07b0*/ LOP3.LUT R14, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff070e7812 */
/* 0x000fe400078ec0ff */
/*07c0*/ LOP3.LUT R12, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff060c7812 */
/* 0x000fe200078ec0ff */
/*07d0*/ IMAD.MOV.U32 R6, RZ, RZ, R9 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0009 */
/*07e0*/ IADD3 R11, R14, -0x1, RZ ; /* 0xffffffff0e0b7810 */
/* 0x000fe40007ffe0ff */
/*07f0*/ IADD3 R10, R12, -0x1, RZ ; /* 0xffffffff0c0a7810 */
/* 0x000fc40007ffe0ff */
/*0800*/ ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; /* 0x000000fd0b00780c */
/* 0x000fe40003f04070 */
/*0810*/ MOV R7, R5 ; /* 0x0000000500077202 */
/* 0x000fe40000000f00 */
/*0820*/ ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; /* 0x000000fd0a00780c */
/* 0x000fda0000704470 */
/*0830*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff088224 */
/* 0x000fe200078e00ff */
/*0840*/ @!P0 BRA 0x9c0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0850*/ FSETP.GTU.FTZ.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fe40003f1c200 */
/*0860*/ FSETP.GTU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fc80003f3c200 */
/*0870*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0880*/ @P0 BRA 0xdc0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0890*/ LOP3.LUT P0, RZ, R7, 0x7fffffff, R6, 0xc8, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fda000780c806 */
/*08a0*/ @!P0 BRA 0xda0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*08b0*/ FSETP.NEU.FTZ.AND P2, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fe40003f5d200 */
/*08c0*/ FSETP.NEU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fe40003f3d200 */
/*08d0*/ FSETP.NEU.FTZ.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fd60003f1d200 */
/*08e0*/ @!P1 BRA !P2, 0xda0 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*08f0*/ LOP3.LUT P2, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000784c0ff */
/*0900*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0910*/ @P1 BRA 0xd80 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0920*/ LOP3.LUT P1, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000782c0ff */
/*0930*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0940*/ @P0 BRA 0xd50 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0950*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f06270 */
/*0960*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f26270 */
/*0970*/ @P0 MOV R8, RZ ; /* 0x000000ff00080202 */
/* 0x000fe20000000f00 */
/*0980*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, -0x40 ; /* 0xffffffc0ff088424 */
/* 0x000fe400078e00ff */
/*0990*/ @!P0 FFMA R6, R9, 1.84467440737095516160e+19, RZ ; /* 0x5f80000009068823 */
/* 0x000fe400000000ff */
/*09a0*/ @!P1 FFMA R7, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005079823 */
/* 0x000fe200000000ff */
/*09b0*/ @!P1 IADD3 R8, R8, 0x40, RZ ; /* 0x0000004008089810 */
/* 0x000fe40007ffe0ff */
/*09c0*/ LEA R10, R14, 0xc0800000, 0x17 ; /* 0xc08000000e0a7811 */
/* 0x000fe200078eb8ff */
/*09d0*/ BSSY B2, 0xd40 ; /* 0x0000036000027945 */
/* 0x000fe60003800000 */
/*09e0*/ IADD3 R10, -R10, R7, RZ ; /* 0x000000070a0a7210 */
/* 0x000fc40007ffe1ff */
/*09f0*/ IADD3 R7, R12, -0x7f, RZ ; /* 0xffffff810c077810 */
/* 0x000fe40007ffe0ff */
/*0a00*/ MUFU.RCP R9, R10 ; /* 0x0000000a00097308 */
/* 0x000e220000001000 */
/*0a10*/ FADD.FTZ R11, -R10, -RZ ; /* 0x800000ff0a0b7221 */
/* 0x000fe40000010100 */
/*0a20*/ IMAD R6, R7, -0x800000, R6 ; /* 0xff80000007067824 */
/* 0x000fe400078e0206 */
/*0a30*/ FFMA R12, R9, R11, 1 ; /* 0x3f800000090c7423 */
/* 0x001fc8000000000b */
/*0a40*/ FFMA R13, R9, R12, R9 ; /* 0x0000000c090d7223 */
/* 0x000fc80000000009 */
/*0a50*/ FFMA R9, R6, R13, RZ ; /* 0x0000000d06097223 */
/* 0x000fc800000000ff */
/*0a60*/ FFMA R12, R11, R9, R6 ; /* 0x000000090b0c7223 */
/* 0x000fc80000000006 */
/*0a70*/ FFMA R12, R13, R12, R9 ; /* 0x0000000c0d0c7223 */
/* 0x000fe20000000009 */
/*0a80*/ IADD3 R9, R7, 0x7f, -R14 ; /* 0x0000007f07097810 */
/* 0x000fc60007ffe80e */
/*0a90*/ FFMA R11, R11, R12, R6 ; /* 0x0000000c0b0b7223 */
/* 0x000fe40000000006 */
/*0aa0*/ IMAD.IADD R9, R9, 0x1, R8 ; /* 0x0000000109097824 */
/* 0x000fe400078e0208 */
/*0ab0*/ FFMA R6, R13, R11, R12 ; /* 0x0000000b0d067223 */
/* 0x000fca000000000c */
/*0ac0*/ SHF.R.U32.HI R7, RZ, 0x17, R6 ; /* 0x00000017ff077819 */
/* 0x000fc80000011606 */
/*0ad0*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fc800078ec0ff */
/*0ae0*/ IADD3 R14, R7, R9, RZ ; /* 0x00000009070e7210 */
/* 0x000fc80007ffe0ff */
/*0af0*/ IADD3 R7, R14, -0x1, RZ ; /* 0xffffffff0e077810 */
/* 0x000fc80007ffe0ff */
/*0b00*/ ISETP.GE.U32.AND P0, PT, R7, 0xfe, PT ; /* 0x000000fe0700780c */
/* 0x000fda0003f06070 */
/*0b10*/ @!P0 BRA 0xd20 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0b20*/ ISETP.GT.AND P0, PT, R14, 0xfe, PT ; /* 0x000000fe0e00780c */
/* 0x000fda0003f04270 */
/*0b30*/ @P0 BRA 0xcf0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0b40*/ ISETP.GE.AND P0, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fda0003f06270 */
/*0b50*/ @P0 BRA 0xd30 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0b60*/ ISETP.GE.AND P0, PT, R14, -0x18, PT ; /* 0xffffffe80e00780c */
/* 0x000fe40003f06270 */
/*0b70*/ LOP3.LUT R6, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000006067812 */
/* 0x000fd600078ec0ff */
/*0b80*/ @!P0 BRA 0xd30 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0b90*/ FFMA.RZ R7, R13.reuse, R11.reuse, R12.reuse ; /* 0x0000000b0d077223 */
/* 0x1c0fe2000000c00c */
/*0ba0*/ IADD3 R10, R14.reuse, 0x20, RZ ; /* 0x000000200e0a7810 */
/* 0x040fe20007ffe0ff */
/*0bb0*/ FFMA.RM R8, R13, R11.reuse, R12.reuse ; /* 0x0000000b0d087223 */
/* 0x180fe2000000400c */
/*0bc0*/ ISETP.NE.AND P2, PT, R14.reuse, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x040fe40003f45270 */
/*0bd0*/ LOP3.LUT R9, R7, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff07097812 */
/* 0x000fe200078ec0ff */
/*0be0*/ FFMA.RP R7, R13, R11, R12 ; /* 0x0000000b0d077223 */
/* 0x000fe2000000800c */
/*0bf0*/ ISETP.NE.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe20003f25270 */
/*0c00*/ IMAD.MOV R11, RZ, RZ, -R14 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a0e */
/*0c10*/ LOP3.LUT R9, R9, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000009097812 */
/* 0x000fe400078efcff */
/*0c20*/ FSETP.NEU.FTZ.AND P0, PT, R7, R8, PT ; /* 0x000000080700720b */
/* 0x000fc40003f1d000 */
/*0c30*/ SHF.L.U32 R10, R9, R10, RZ ; /* 0x0000000a090a7219 */
/* 0x000fe400000006ff */
/*0c40*/ SEL R8, R11, RZ, P2 ; /* 0x000000ff0b087207 */
/* 0x000fe40001000000 */
/*0c50*/ ISETP.NE.AND P1, PT, R10, RZ, P1 ; /* 0x000000ff0a00720c */
/* 0x000fe40000f25270 */
/*0c60*/ SHF.R.U32.HI R8, RZ, R8, R9 ; /* 0x00000008ff087219 */
/* 0x000fe40000011609 */
/*0c70*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0c80*/ SHF.R.U32.HI R10, RZ, 0x1, R8 ; /* 0x00000001ff0a7819 */
/* 0x000fc40000011608 */
/*0c90*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fc80004000000 */
/*0ca0*/ LOP3.LUT R7, R7, 0x1, R10, 0xf8, !PT ; /* 0x0000000107077812 */
/* 0x000fc800078ef80a */
/*0cb0*/ LOP3.LUT R7, R7, R8, RZ, 0xc0, !PT ; /* 0x0000000807077212 */
/* 0x000fc800078ec0ff */
/*0cc0*/ IADD3 R7, R10, R7, RZ ; /* 0x000000070a077210 */
/* 0x000fc80007ffe0ff */
/*0cd0*/ LOP3.LUT R6, R7, R6, RZ, 0xfc, !PT ; /* 0x0000000607067212 */
/* 0x000fe200078efcff */
/*0ce0*/ BRA 0xd30 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0cf0*/ LOP3.LUT R6, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000006067812 */
/* 0x000fc800078ec0ff */
/*0d00*/ LOP3.LUT R6, R6, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000006067812 */
/* 0x000fe200078efcff */
/*0d10*/ BRA 0xd30 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0d20*/ IMAD R6, R9, 0x800000, R6 ; /* 0x0080000009067824 */
/* 0x000fe400078e0206 */
/*0d30*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0d40*/ BRA 0xdd0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0d50*/ LOP3.LUT R6, R7, 0x80000000, R6, 0x48, !PT ; /* 0x8000000007067812 */
/* 0x000fc800078e4806 */
/*0d60*/ LOP3.LUT R6, R6, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000006067812 */
/* 0x000fe200078efcff */
/*0d70*/ BRA 0xdd0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0d80*/ LOP3.LUT R6, R7, 0x80000000, R6, 0x48, !PT ; /* 0x8000000007067812 */
/* 0x000fe200078e4806 */
/*0d90*/ BRA 0xdd0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0da0*/ MUFU.RSQ R6, -QNAN ; /* 0xffc0000000067908 */
/* 0x000e220000001400 */
/*0db0*/ BRA 0xdd0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0dc0*/ FADD.FTZ R6, R9, R5 ; /* 0x0000000509067221 */
/* 0x000fe40000010000 */
/*0dd0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0de0*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*0df0*/ MOV R9, R6 ; /* 0x0000000600097202 */
/* 0x001fe20000000f00 */
/*0e00*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0004 */
/*0e10*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff1e006007950 */
/* 0x000fea0003c3ffff */
/*0e20*/ BRA 0xe20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C"
__global__ void calcDir(// Dots props
float* pX,
float* pY,
float* pZ,
//Tree specs
// per Block
//int* dotIndexes,
float* avgPX,
float* avgPY,
float* avgPZ,
int* idFurthest,
// per GPU Block
// output values, per block
float* dirX,
float* dirY,
float* dirZ,
float nBlocs
)
{
int idBloc = blockIdx.x*blockDim.x+threadIdx.x;
if (idBloc<nBlocs) {
int mx=avgPX[idBloc];
int my=avgPY[idBloc];
int mz=avgPZ[idBloc];
int idPtFurthest = idFurthest[idBloc];
float dx=pX[idPtFurthest]-mx;
float dy=pY[idPtFurthest]-my;
float dz=pZ[idPtFurthest]-mz;
float dist = sqrtf(dx*dx+dy*dy+dz*dz);
dirX[idBloc]=dx/dist;
dirY[idBloc]=dy/dist;
dirZ[idBloc]=dz/dist;
}
} | .file "tmpxft_000c628e_00000000-6_gpuCalcDir.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z7calcDirPfS_S_S_S_S_PiS_S_S_fPfS_S_S_S_S_PiS_S_S_f
.type _Z45__device_stub__Z7calcDirPfS_S_S_S_S_PiS_S_S_fPfS_S_S_S_S_PiS_S_S_f, @function
_Z45__device_stub__Z7calcDirPfS_S_S_S_S_PiS_S_S_fPfS_S_S_S_S_PiS_S_S_f:
.LFB2051:
.cfi_startproc
endbr64
subq $264, %rsp
.cfi_def_cfa_offset 272
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
movss %xmm0, 12(%rsp)
movq 272(%rsp), %rax
movq %rax, 40(%rsp)
movq 280(%rsp), %rax
movq %rax, 32(%rsp)
movq 288(%rsp), %rax
movq %rax, 24(%rsp)
movq 296(%rsp), %rax
movq %rax, 16(%rsp)
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 80(%rsp), %rax
movq %rax, 168(%rsp)
leaq 72(%rsp), %rax
movq %rax, 176(%rsp)
leaq 64(%rsp), %rax
movq %rax, 184(%rsp)
leaq 56(%rsp), %rax
movq %rax, 192(%rsp)
leaq 48(%rsp), %rax
movq %rax, 200(%rsp)
leaq 40(%rsp), %rax
movq %rax, 208(%rsp)
leaq 32(%rsp), %rax
movq %rax, 216(%rsp)
leaq 24(%rsp), %rax
movq %rax, 224(%rsp)
leaq 16(%rsp), %rax
movq %rax, 232(%rsp)
leaq 12(%rsp), %rax
movq %rax, 240(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
leaq 104(%rsp), %rcx
leaq 96(%rsp), %rdx
leaq 124(%rsp), %rsi
leaq 112(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 280
pushq 104(%rsp)
.cfi_def_cfa_offset 288
leaq 176(%rsp), %r9
movq 140(%rsp), %rcx
movl 148(%rsp), %r8d
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
leaq calcDir(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 272
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z7calcDirPfS_S_S_S_S_PiS_S_S_fPfS_S_S_S_S_PiS_S_S_f, .-_Z45__device_stub__Z7calcDirPfS_S_S_S_S_PiS_S_S_fPfS_S_S_S_S_PiS_S_S_f
.globl calcDir
.type calcDir, @function
calcDir:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 40(%rsp)
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z45__device_stub__Z7calcDirPfS_S_S_S_S_PiS_S_S_fPfS_S_S_S_S_PiS_S_S_f
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size calcDir, .-calcDir
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "calcDir"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq calcDir(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C"
__global__ void calcDir(// Dots props
float* pX,
float* pY,
float* pZ,
//Tree specs
// per Block
//int* dotIndexes,
float* avgPX,
float* avgPY,
float* avgPZ,
int* idFurthest,
// per GPU Block
// output values, per block
float* dirX,
float* dirY,
float* dirZ,
float nBlocs
)
{
int idBloc = blockIdx.x*blockDim.x+threadIdx.x;
if (idBloc<nBlocs) {
int mx=avgPX[idBloc];
int my=avgPY[idBloc];
int mz=avgPZ[idBloc];
int idPtFurthest = idFurthest[idBloc];
float dx=pX[idPtFurthest]-mx;
float dy=pY[idPtFurthest]-my;
float dz=pZ[idPtFurthest]-mz;
float dist = sqrtf(dx*dx+dy*dy+dz*dz);
dirX[idBloc]=dx/dist;
dirY[idBloc]=dy/dist;
dirZ[idBloc]=dz/dist;
}
} | #include <hip/hip_runtime.h>
extern "C"
__global__ void calcDir(// Dots props
float* pX,
float* pY,
float* pZ,
//Tree specs
// per Block
//int* dotIndexes,
float* avgPX,
float* avgPY,
float* avgPZ,
int* idFurthest,
// per GPU Block
// output values, per block
float* dirX,
float* dirY,
float* dirZ,
float nBlocs
)
{
int idBloc = blockIdx.x*blockDim.x+threadIdx.x;
if (idBloc<nBlocs) {
int mx=avgPX[idBloc];
int my=avgPY[idBloc];
int mz=avgPZ[idBloc];
int idPtFurthest = idFurthest[idBloc];
float dx=pX[idPtFurthest]-mx;
float dy=pY[idPtFurthest]-my;
float dz=pZ[idPtFurthest]-mz;
float dist = sqrtf(dx*dx+dy*dy+dz*dz);
dirX[idBloc]=dx/dist;
dirY[idBloc]=dy/dist;
dirZ[idBloc]=dz/dist;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__ void calcDir(// Dots props
float* pX,
float* pY,
float* pZ,
//Tree specs
// per Block
//int* dotIndexes,
float* avgPX,
float* avgPY,
float* avgPZ,
int* idFurthest,
// per GPU Block
// output values, per block
float* dirX,
float* dirY,
float* dirZ,
float nBlocs
)
{
int idBloc = blockIdx.x*blockDim.x+threadIdx.x;
if (idBloc<nBlocs) {
int mx=avgPX[idBloc];
int my=avgPY[idBloc];
int mz=avgPZ[idBloc];
int idPtFurthest = idFurthest[idBloc];
float dx=pX[idPtFurthest]-mx;
float dy=pY[idPtFurthest]-my;
float dz=pZ[idPtFurthest]-mz;
float dist = sqrtf(dx*dx+dy*dy+dz*dz);
dirX[idBloc]=dx/dist;
dirY[idBloc]=dy/dist;
dirZ[idBloc]=dz/dist;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected calcDir
.globl calcDir
.p2align 8
.type calcDir,@function
calcDir:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x64
s_load_b32 s3, s[0:1], 0x50
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cvt_f32_i32_e32 v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_f32_e32 s3, v0
s_cbranch_execz .LBB0_2
s_load_b256 s[4:11], s[0:1], 0x20
v_ashrrev_i32_e32 v2, 31, v1
s_load_b256 s[12:19], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s18, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s19, v1, vcc_lo
global_load_b32 v2, v[2:3], off
v_add_co_u32 v6, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v1, vcc_lo
global_load_b32 v10, v[4:5], off
global_load_b32 v11, v[6:7], off
global_load_b32 v8, v[8:9], off
s_load_b128 s[4:7], s[0:1], 0x40
s_waitcnt vmcnt(3)
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s14, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s15, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s12, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s13, v3, vcc_lo
global_load_b32 v4, v[4:5], off
v_add_co_u32 v2, vcc_lo, s16, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s17, v3, vcc_lo
global_load_b32 v5, v[6:7], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(4)
v_cvt_i32_f32_e32 v3, v11
v_cvt_i32_f32_e32 v6, v10
s_waitcnt vmcnt(3)
v_cvt_i32_f32_e32 v7, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f32_i32_e32 v3, v3
v_cvt_f32_i32_e32 v6, v6
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v4, v3
v_cvt_f32_i32_e32 v3, v7
v_mul_f32_e32 v4, v8, v8
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v6, v5, v6 :: v_dual_sub_f32 v7, v2, v3
v_fmac_f32_e32 v4, v6, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v7, v7
v_mul_f32_e32 v2, 0x4f800000, v4
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v4, v2, vcc_lo
v_sqrt_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v4, -1, v3
v_add_nc_u32_e32 v5, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v9, -v4, v3, v2
v_fma_f32 v10, -v5, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s2, 0, v9
v_cndmask_b32_e64 v3, v3, v4, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s2, 0, v10
v_cndmask_b32_e64 v3, v3, v5, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, 0x37800000, v3
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v2, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v9, v3, v2, vcc_lo
v_div_scale_f32 v4, null, v9, v9, v6
v_div_scale_f32 v5, null, v9, v9, v8
v_div_scale_f32 v10, null, v9, v9, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v11, v4
v_rcp_f32_e32 v12, v5
v_div_scale_f32 v14, vcc_lo, v6, v9, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(TRANS32_DEP_3)
v_rcp_f32_e32 v13, v10
v_div_scale_f32 v15, s2, v8, v9, v8
v_div_scale_f32 v17, s3, v7, v9, v7
v_fma_f32 v2, -v4, v11, 1.0
s_waitcnt_depctr 0xfff
v_fma_f32 v3, -v5, v12, 1.0
v_fma_f32 v16, -v10, v13, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmac_f32 v11, v2, v11 :: v_dual_fmac_f32 v12, v3, v12
v_dual_fmac_f32 v13, v16, v13 :: v_dual_mul_f32 v16, v14, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mul_f32 v18, v15, v12 :: v_dual_mul_f32 v19, v17, v13
v_fma_f32 v2, -v4, v16, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v3, -v5, v18, v15
v_fma_f32 v20, -v10, v19, v17
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v16, v2, v11
v_fmac_f32_e32 v18, v3, v12
v_add_co_u32 v2, s0, s10, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fmac_f32_e32 v19, v20, v13
v_fma_f32 v4, -v4, v16, v14
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_fma_f32 v5, -v5, v18, v15
v_add_co_ci_u32_e64 v3, s0, s11, v1, s0
v_fma_f32 v10, -v10, v19, v17
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_div_fmas_f32 v11, v4, v11, v16
s_mov_b32 vcc_lo, s2
v_div_fmas_f32 v12, v5, v12, v18
s_mov_b32 vcc_lo, s3
v_div_fixup_f32 v6, v11, v9, v6
v_div_fmas_f32 v10, v10, v13, v19
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_div_fixup_f32 v8, v12, v9, v8
v_div_fixup_f32 v7, v10, v9, v7
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_store_b32 v[2:3], v6, off
global_store_b32 v[4:5], v8, off
global_store_b32 v[0:1], v7, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel calcDir
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 344
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size calcDir, .Lfunc_end0-calcDir
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .offset: 80
.size: 4
.value_kind: by_value
- .offset: 88
.size: 4
.value_kind: hidden_block_count_x
- .offset: 92
.size: 4
.value_kind: hidden_block_count_y
- .offset: 96
.size: 4
.value_kind: hidden_block_count_z
- .offset: 100
.size: 2
.value_kind: hidden_group_size_x
- .offset: 102
.size: 2
.value_kind: hidden_group_size_y
- .offset: 104
.size: 2
.value_kind: hidden_group_size_z
- .offset: 106
.size: 2
.value_kind: hidden_remainder_x
- .offset: 108
.size: 2
.value_kind: hidden_remainder_y
- .offset: 110
.size: 2
.value_kind: hidden_remainder_z
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 144
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 152
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 344
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: calcDir
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: calcDir.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__ void calcDir(// Dots props
float* pX,
float* pY,
float* pZ,
//Tree specs
// per Block
//int* dotIndexes,
float* avgPX,
float* avgPY,
float* avgPZ,
int* idFurthest,
// per GPU Block
// output values, per block
float* dirX,
float* dirY,
float* dirZ,
float nBlocs
)
{
int idBloc = blockIdx.x*blockDim.x+threadIdx.x;
if (idBloc<nBlocs) {
int mx=avgPX[idBloc];
int my=avgPY[idBloc];
int mz=avgPZ[idBloc];
int idPtFurthest = idFurthest[idBloc];
float dx=pX[idPtFurthest]-mx;
float dy=pY[idPtFurthest]-my;
float dz=pZ[idPtFurthest]-mz;
float dist = sqrtf(dx*dx+dy*dy+dz*dz);
dirX[idBloc]=dx/dist;
dirY[idBloc]=dy/dist;
dirZ[idBloc]=dz/dist;
}
} | .text
.file "gpuCalcDir.hip"
.globl __device_stub__calcDir # -- Begin function __device_stub__calcDir
.p2align 4, 0x90
.type __device_stub__calcDir,@function
__device_stub__calcDir: # @__device_stub__calcDir
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movss %xmm0, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 232(%rsp), %rax
movq %rax, 184(%rsp)
leaq 12(%rsp), %rax
movq %rax, 192(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $calcDir, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size __device_stub__calcDir, .Lfunc_end0-__device_stub__calcDir
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $calcDir, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type calcDir,@object # @calcDir
.section .rodata,"a",@progbits
.globl calcDir
.p2align 3, 0x0
calcDir:
.quad __device_stub__calcDir
.size calcDir, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "calcDir"
.size .L__unnamed_1, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__calcDir
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym calcDir
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : calcDir
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0040*/ I2F R2, R0 ; /* 0x0000000000027306 */
/* 0x000e240000201400 */
/*0050*/ FSETP.GEU.AND P0, PT, R2, c[0x0][0x1b0], PT ; /* 0x00006c0002007a0b */
/* 0x001fda0003f0e000 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ IMAD.WIDE R8, R0, R15, c[0x0][0x190] ; /* 0x0000640000087625 */
/* 0x000fcc00078e020f */
/*00a0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ IMAD.WIDE R4, R0, R15, c[0x0][0x180] ; /* 0x0000600000047625 */
/* 0x000fc800078e020f */
/*00c0*/ IMAD.WIDE R2, R0.reuse, R15.reuse, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x0c0fe400078e020f */
/*00d0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ee4000c1e1900 */
/*00e0*/ IMAD.WIDE R6, R0, R15.reuse, c[0x0][0x188] ; /* 0x0000620000067625 */
/* 0x080fe400078e020f */
/*00f0*/ LDG.E R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000f28000c1e1900 */
/*0100*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f62000c1e1900 */
/*0110*/ IMAD.WIDE R12, R8, R15, c[0x0][0x168] ; /* 0x00005a00080c7625 */
/* 0x004fc800078e020f */
/*0120*/ IMAD.WIDE R10, R8.reuse, R15.reuse, c[0x0][0x160] ; /* 0x00005800080a7625 */
/* 0x0c0fe400078e020f */
/*0130*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000ea4000c1e1900 */
/*0140*/ IMAD.WIDE R14, R8, R15, c[0x0][0x170] ; /* 0x00005c00080e7625 */
/* 0x000fe400078e020f */
/*0150*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ea8000c1e1900 */
/*0160*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea2000c1e1900 */
/*0170*/ F2I.TRUNC.NTZ R8, R5 ; /* 0x0000000500087305 */
/* 0x008e30000020f100 */
/*0180*/ F2I.TRUNC.NTZ R16, R16 ; /* 0x0000001000107305 */
/* 0x010e70000020f100 */
/*0190*/ F2I.TRUNC.NTZ R9, R6 ; /* 0x0000000600097305 */
/* 0x020ef0000020f100 */
/*01a0*/ I2F R2, R8 ; /* 0x0000000800027306 */
/* 0x001eb00000201400 */
/*01b0*/ I2F R4, R16 ; /* 0x0000001000047306 */
/* 0x002e300000201400 */
/*01c0*/ I2F R3, R9 ; /* 0x0000000900037306 */
/* 0x008e620000201400 */
/*01d0*/ BSSY B0, 0x300 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*01e0*/ FADD R2, -R2, R13 ; /* 0x0000000d02027221 */
/* 0x004fc40000000100 */
/*01f0*/ FADD R4, -R4, R11 ; /* 0x0000000b04047221 */
/* 0x001fe40000000100 */
/*0200*/ FMUL R7, R2, R2 ; /* 0x0000000202077220 */
/* 0x000fe40000400000 */
/*0210*/ FADD R3, -R3, R14 ; /* 0x0000000e03037221 */
/* 0x002fe40000000100 */
/*0220*/ FFMA R10, R4, R4, R7 ; /* 0x00000004040a7223 */
/* 0x000fc80000000007 */
/*0230*/ FFMA R10, R3, R3, R10 ; /* 0x00000003030a7223 */
/* 0x000fca000000000a */
/*0240*/ IADD3 R7, R10, -0xd000000, RZ ; /* 0xf30000000a077810 */
/* 0x000fe20007ffe0ff */
/*0250*/ MUFU.RSQ R5, R10 ; /* 0x0000000a00057308 */
/* 0x0000660000001400 */
/*0260*/ ISETP.GT.U32.AND P0, PT, R7, 0x727fffff, PT ; /* 0x727fffff0700780c */
/* 0x000fda0003f04070 */
/*0270*/ @!P0 BRA 0x2b0 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0280*/ MOV R11, 0x2a0 ; /* 0x000002a0000b7802 */
/* 0x003fe40000000f00 */
/*0290*/ CALL.REL.NOINC 0x620 ; /* 0x0000038000007944 */
/* 0x000fea0003c00000 */
/*02a0*/ BRA 0x2f0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*02b0*/ FMUL.FTZ R7, R10, R5 ; /* 0x000000050a077220 */
/* 0x003fe40000410000 */
/*02c0*/ FMUL.FTZ R5, R5, 0.5 ; /* 0x3f00000005057820 */
/* 0x000fe40000410000 */
/*02d0*/ FFMA R10, -R7, R7, R10 ; /* 0x00000007070a7223 */
/* 0x000fc8000000010a */
/*02e0*/ FFMA R5, R10, R5, R7 ; /* 0x000000050a057223 */
/* 0x000fe40000000007 */
/*02f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0300*/ MUFU.RCP R6, R5 ; /* 0x0000000500067308 */
/* 0x000e220000001000 */
/*0310*/ BSSY B0, 0x3d0 ; /* 0x000000b000007945 */
/* 0x000fee0003800000 */
/*0320*/ FCHK P0, R4, R5 ; /* 0x0000000504007302 */
/* 0x000e620000000000 */
/*0330*/ FFMA R7, R6, -R5, 1 ; /* 0x3f80000006077423 */
/* 0x001fc80000000805 */
/*0340*/ FFMA R7, R6, R7, R6 ; /* 0x0000000706077223 */
/* 0x000fc80000000006 */
/*0350*/ FFMA R6, R4, R7, RZ ; /* 0x0000000704067223 */
/* 0x000fc800000000ff */
/*0360*/ FFMA R8, R6, -R5, R4 ; /* 0x8000000506087223 */
/* 0x000fc80000000004 */
/*0370*/ FFMA R9, R7, R8, R6 ; /* 0x0000000807097223 */
/* 0x000fe20000000006 */
/*0380*/ @!P0 BRA 0x3c0 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*0390*/ MOV R9, R4 ; /* 0x0000000400097202 */
/* 0x000fe40000000f00 */
/*03a0*/ MOV R4, 0x3c0 ; /* 0x000003c000047802 */
/* 0x000fe40000000f00 */
/*03b0*/ CALL.REL.NOINC 0x780 ; /* 0x000003c000007944 */
/* 0x000fea0003c00000 */
/*03c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03d0*/ MUFU.RCP R4, R5 ; /* 0x0000000500047308 */
/* 0x000e220000001000 */
/*03e0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*03f0*/ BSSY B0, 0x4e0 ; /* 0x000000e000007945 */
/* 0x000fe60003800000 */
/*0400*/ IMAD.WIDE R6, R0, R7, c[0x0][0x198] ; /* 0x0000660000067625 */
/* 0x000fc600078e0207 */
/*0410*/ FCHK P0, R2, R5 ; /* 0x0000000502007302 */
/* 0x000e640000000000 */
/*0420*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0005e2000c101904 */
/*0430*/ FFMA R11, R4, -R5, 1 ; /* 0x3f800000040b7423 */
/* 0x001fc80000000805 */
/*0440*/ FFMA R13, R4, R11, R4 ; /* 0x0000000b040d7223 */
/* 0x000fc80000000004 */
/*0450*/ FFMA R4, R2, R13, RZ ; /* 0x0000000d02047223 */
/* 0x000fc800000000ff */
/*0460*/ FFMA R11, R4, -R5, R2 ; /* 0x80000005040b7223 */
/* 0x000fc80000000002 */
/*0470*/ FFMA R11, R13, R11, R4 ; /* 0x0000000b0d0b7223 */
/* 0x000fe20000000004 */
/*0480*/ @!P0 BRA 0x4d0 ; /* 0x0000004000008947 */
/* 0x002fea0003800000 */
/*0490*/ IMAD.MOV.U32 R9, RZ, RZ, R2 ; /* 0x000000ffff097224 */
/* 0x004fe200078e0002 */
/*04a0*/ MOV R4, 0x4c0 ; /* 0x000004c000047802 */
/* 0x000fe40000000f00 */
/*04b0*/ CALL.REL.NOINC 0x780 ; /* 0x000002c000007944 */
/* 0x000fea0003c00000 */
/*04c0*/ MOV R11, R9 ; /* 0x00000009000b7202 */
/* 0x000fe40000000f00 */
/*04d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x004fea0003800000 */
/*04e0*/ MUFU.RCP R2, R5 ; /* 0x0000000500027308 */
/* 0x000e220000001000 */
/*04f0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0500*/ BSSY B0, 0x5e0 ; /* 0x000000d000007945 */
/* 0x000fe60003800000 */
/*0510*/ IMAD.WIDE R6, R0, R7, c[0x0][0x1a0] ; /* 0x0000680000067625 */
/* 0x000fc600078e0207 */
/*0520*/ FCHK P0, R3, R5 ; /* 0x0000000503007302 */
/* 0x000e640000000000 */
/*0530*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0005e2000c101904 */
/*0540*/ FFMA R9, R2, -R5, 1 ; /* 0x3f80000002097423 */
/* 0x001fc80000000805 */
/*0550*/ FFMA R4, R2, R9, R2 ; /* 0x0000000902047223 */
/* 0x000fc80000000002 */
/*0560*/ FFMA R2, R3, R4, RZ ; /* 0x0000000403027223 */
/* 0x000fc800000000ff */
/*0570*/ FFMA R9, R2, -R5, R3 ; /* 0x8000000502097223 */
/* 0x000fc80000000003 */
/*0580*/ FFMA R9, R4, R9, R2 ; /* 0x0000000904097223 */
/* 0x000fe20000000002 */
/*0590*/ @!P0 BRA 0x5d0 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*05a0*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x004fe200078e0003 */
/*05b0*/ MOV R4, 0x5d0 ; /* 0x000005d000047802 */
/* 0x000fe40000000f00 */
/*05c0*/ CALL.REL.NOINC 0x780 ; /* 0x000001b000007944 */
/* 0x000fea0003c00000 */
/*05d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x004fea0003800000 */
/*05e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*05f0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x1a8] ; /* 0x00006a0000027625 */
/* 0x000fca00078e0203 */
/*0600*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*0610*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0620*/ LOP3.LUT P0, RZ, R10, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0aff7812 */
/* 0x000fda000780c0ff */
/*0630*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff058224 */
/* 0x000fe200078e000a */
/*0640*/ @!P0 BRA 0x750 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0650*/ FSETP.GEU.FTZ.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720b */
/* 0x000fda0003f1e000 */
/*0660*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, 0x7fffffff ; /* 0x7fffffffff058424 */
/* 0x000fe200078e00ff */
/*0670*/ @!P0 BRA 0x750 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0680*/ FSETP.GTU.FTZ.AND P0, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fda0003f1c200 */
/*0690*/ @P0 FADD.FTZ R5, R10, 1 ; /* 0x3f8000000a050421 */
/* 0x000fe20000010000 */
/*06a0*/ @P0 BRA 0x750 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*06b0*/ FSETP.NEU.FTZ.AND P0, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fda0003f1d200 */
/*06c0*/ @P0 FFMA R6, R10, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000a060823 */
/* 0x000fc800000000ff */
/*06d0*/ @P0 MUFU.RSQ R5, R6 ; /* 0x0000000600050308 */
/* 0x000e240000001400 */
/*06e0*/ @P0 FMUL.FTZ R7, R6, R5 ; /* 0x0000000506070220 */
/* 0x001fe40000410000 */
/*06f0*/ @P0 FMUL.FTZ R9, R5, 0.5 ; /* 0x3f00000005090820 */
/* 0x000fe20000410000 */
/*0700*/ @!P0 MOV R5, R10 ; /* 0x0000000a00058202 */
/* 0x000fe20000000f00 */
/*0710*/ @P0 FADD.FTZ R8, -R7, -RZ ; /* 0x800000ff07080221 */
/* 0x000fc80000010100 */
/*0720*/ @P0 FFMA R8, R7, R8, R6 ; /* 0x0000000807080223 */
/* 0x000fc80000000006 */
/*0730*/ @P0 FFMA R8, R8, R9, R7 ; /* 0x0000000908080223 */
/* 0x000fc80000000007 */
/*0740*/ @P0 FMUL.FTZ R5, R8, 2.3283064365386962891e-10 ; /* 0x2f80000008050820 */
/* 0x000fe40000410000 */
/*0750*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*0760*/ IMAD.MOV.U32 R6, RZ, RZ, R11 ; /* 0x000000ffff067224 */
/* 0x000fca00078e000b */
/*0770*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff88006007950 */
/* 0x000fea0003c3ffff */
/*0780*/ SHF.R.U32.HI R7, RZ, 0x17, R5 ; /* 0x00000017ff077819 */
/* 0x000fe20000011605 */
/*0790*/ BSSY B1, 0xde0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*07a0*/ SHF.R.U32.HI R6, RZ, 0x17, R9.reuse ; /* 0x00000017ff067819 */
/* 0x100fe40000011609 */
/*07b0*/ LOP3.LUT R14, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff070e7812 */
/* 0x000fe400078ec0ff */
/*07c0*/ LOP3.LUT R12, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff060c7812 */
/* 0x000fe200078ec0ff */
/*07d0*/ IMAD.MOV.U32 R6, RZ, RZ, R9 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0009 */
/*07e0*/ IADD3 R11, R14, -0x1, RZ ; /* 0xffffffff0e0b7810 */
/* 0x000fe40007ffe0ff */
/*07f0*/ IADD3 R10, R12, -0x1, RZ ; /* 0xffffffff0c0a7810 */
/* 0x000fc40007ffe0ff */
/*0800*/ ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; /* 0x000000fd0b00780c */
/* 0x000fe40003f04070 */
/*0810*/ MOV R7, R5 ; /* 0x0000000500077202 */
/* 0x000fe40000000f00 */
/*0820*/ ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; /* 0x000000fd0a00780c */
/* 0x000fda0000704470 */
/*0830*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff088224 */
/* 0x000fe200078e00ff */
/*0840*/ @!P0 BRA 0x9c0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0850*/ FSETP.GTU.FTZ.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fe40003f1c200 */
/*0860*/ FSETP.GTU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fc80003f3c200 */
/*0870*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0880*/ @P0 BRA 0xdc0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0890*/ LOP3.LUT P0, RZ, R7, 0x7fffffff, R6, 0xc8, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fda000780c806 */
/*08a0*/ @!P0 BRA 0xda0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*08b0*/ FSETP.NEU.FTZ.AND P2, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fe40003f5d200 */
/*08c0*/ FSETP.NEU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fe40003f3d200 */
/*08d0*/ FSETP.NEU.FTZ.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fd60003f1d200 */
/*08e0*/ @!P1 BRA !P2, 0xda0 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*08f0*/ LOP3.LUT P2, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000784c0ff */
/*0900*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0910*/ @P1 BRA 0xd80 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0920*/ LOP3.LUT P1, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000782c0ff */
/*0930*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0940*/ @P0 BRA 0xd50 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0950*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f06270 */
/*0960*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f26270 */
/*0970*/ @P0 MOV R8, RZ ; /* 0x000000ff00080202 */
/* 0x000fe20000000f00 */
/*0980*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, -0x40 ; /* 0xffffffc0ff088424 */
/* 0x000fe400078e00ff */
/*0990*/ @!P0 FFMA R6, R9, 1.84467440737095516160e+19, RZ ; /* 0x5f80000009068823 */
/* 0x000fe400000000ff */
/*09a0*/ @!P1 FFMA R7, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005079823 */
/* 0x000fe200000000ff */
/*09b0*/ @!P1 IADD3 R8, R8, 0x40, RZ ; /* 0x0000004008089810 */
/* 0x000fe40007ffe0ff */
/*09c0*/ LEA R10, R14, 0xc0800000, 0x17 ; /* 0xc08000000e0a7811 */
/* 0x000fe200078eb8ff */
/*09d0*/ BSSY B2, 0xd40 ; /* 0x0000036000027945 */
/* 0x000fe60003800000 */
/*09e0*/ IADD3 R10, -R10, R7, RZ ; /* 0x000000070a0a7210 */
/* 0x000fc40007ffe1ff */
/*09f0*/ IADD3 R7, R12, -0x7f, RZ ; /* 0xffffff810c077810 */
/* 0x000fe40007ffe0ff */
/*0a00*/ MUFU.RCP R9, R10 ; /* 0x0000000a00097308 */
/* 0x000e220000001000 */
/*0a10*/ FADD.FTZ R11, -R10, -RZ ; /* 0x800000ff0a0b7221 */
/* 0x000fe40000010100 */
/*0a20*/ IMAD R6, R7, -0x800000, R6 ; /* 0xff80000007067824 */
/* 0x000fe400078e0206 */
/*0a30*/ FFMA R12, R9, R11, 1 ; /* 0x3f800000090c7423 */
/* 0x001fc8000000000b */
/*0a40*/ FFMA R13, R9, R12, R9 ; /* 0x0000000c090d7223 */
/* 0x000fc80000000009 */
/*0a50*/ FFMA R9, R6, R13, RZ ; /* 0x0000000d06097223 */
/* 0x000fc800000000ff */
/*0a60*/ FFMA R12, R11, R9, R6 ; /* 0x000000090b0c7223 */
/* 0x000fc80000000006 */
/*0a70*/ FFMA R12, R13, R12, R9 ; /* 0x0000000c0d0c7223 */
/* 0x000fe20000000009 */
/*0a80*/ IADD3 R9, R7, 0x7f, -R14 ; /* 0x0000007f07097810 */
/* 0x000fc60007ffe80e */
/*0a90*/ FFMA R11, R11, R12, R6 ; /* 0x0000000c0b0b7223 */
/* 0x000fe40000000006 */
/*0aa0*/ IMAD.IADD R9, R9, 0x1, R8 ; /* 0x0000000109097824 */
/* 0x000fe400078e0208 */
/*0ab0*/ FFMA R6, R13, R11, R12 ; /* 0x0000000b0d067223 */
/* 0x000fca000000000c */
/*0ac0*/ SHF.R.U32.HI R7, RZ, 0x17, R6 ; /* 0x00000017ff077819 */
/* 0x000fc80000011606 */
/*0ad0*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fc800078ec0ff */
/*0ae0*/ IADD3 R14, R7, R9, RZ ; /* 0x00000009070e7210 */
/* 0x000fc80007ffe0ff */
/*0af0*/ IADD3 R7, R14, -0x1, RZ ; /* 0xffffffff0e077810 */
/* 0x000fc80007ffe0ff */
/*0b00*/ ISETP.GE.U32.AND P0, PT, R7, 0xfe, PT ; /* 0x000000fe0700780c */
/* 0x000fda0003f06070 */
/*0b10*/ @!P0 BRA 0xd20 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0b20*/ ISETP.GT.AND P0, PT, R14, 0xfe, PT ; /* 0x000000fe0e00780c */
/* 0x000fda0003f04270 */
/*0b30*/ @P0 BRA 0xcf0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0b40*/ ISETP.GE.AND P0, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fda0003f06270 */
/*0b50*/ @P0 BRA 0xd30 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0b60*/ ISETP.GE.AND P0, PT, R14, -0x18, PT ; /* 0xffffffe80e00780c */
/* 0x000fe40003f06270 */
/*0b70*/ LOP3.LUT R6, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000006067812 */
/* 0x000fd600078ec0ff */
/*0b80*/ @!P0 BRA 0xd30 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0b90*/ FFMA.RZ R7, R13.reuse, R11.reuse, R12.reuse ; /* 0x0000000b0d077223 */
/* 0x1c0fe2000000c00c */
/*0ba0*/ IADD3 R10, R14.reuse, 0x20, RZ ; /* 0x000000200e0a7810 */
/* 0x040fe20007ffe0ff */
/*0bb0*/ FFMA.RM R8, R13, R11.reuse, R12.reuse ; /* 0x0000000b0d087223 */
/* 0x180fe2000000400c */
/*0bc0*/ ISETP.NE.AND P2, PT, R14.reuse, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x040fe40003f45270 */
/*0bd0*/ LOP3.LUT R9, R7, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff07097812 */
/* 0x000fe200078ec0ff */
/*0be0*/ FFMA.RP R7, R13, R11, R12 ; /* 0x0000000b0d077223 */
/* 0x000fe2000000800c */
/*0bf0*/ ISETP.NE.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe20003f25270 */
/*0c00*/ IMAD.MOV R11, RZ, RZ, -R14 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a0e */
/*0c10*/ LOP3.LUT R9, R9, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000009097812 */
/* 0x000fe400078efcff */
/*0c20*/ FSETP.NEU.FTZ.AND P0, PT, R7, R8, PT ; /* 0x000000080700720b */
/* 0x000fc40003f1d000 */
/*0c30*/ SHF.L.U32 R10, R9, R10, RZ ; /* 0x0000000a090a7219 */
/* 0x000fe400000006ff */
/*0c40*/ SEL R8, R11, RZ, P2 ; /* 0x000000ff0b087207 */
/* 0x000fe40001000000 */
/*0c50*/ ISETP.NE.AND P1, PT, R10, RZ, P1 ; /* 0x000000ff0a00720c */
/* 0x000fe40000f25270 */
/*0c60*/ SHF.R.U32.HI R8, RZ, R8, R9 ; /* 0x00000008ff087219 */
/* 0x000fe40000011609 */
/*0c70*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0c80*/ SHF.R.U32.HI R10, RZ, 0x1, R8 ; /* 0x00000001ff0a7819 */
/* 0x000fc40000011608 */
/*0c90*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fc80004000000 */
/*0ca0*/ LOP3.LUT R7, R7, 0x1, R10, 0xf8, !PT ; /* 0x0000000107077812 */
/* 0x000fc800078ef80a */
/*0cb0*/ LOP3.LUT R7, R7, R8, RZ, 0xc0, !PT ; /* 0x0000000807077212 */
/* 0x000fc800078ec0ff */
/*0cc0*/ IADD3 R7, R10, R7, RZ ; /* 0x000000070a077210 */
/* 0x000fc80007ffe0ff */
/*0cd0*/ LOP3.LUT R6, R7, R6, RZ, 0xfc, !PT ; /* 0x0000000607067212 */
/* 0x000fe200078efcff */
/*0ce0*/ BRA 0xd30 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0cf0*/ LOP3.LUT R6, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000006067812 */
/* 0x000fc800078ec0ff */
/*0d00*/ LOP3.LUT R6, R6, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000006067812 */
/* 0x000fe200078efcff */
/*0d10*/ BRA 0xd30 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0d20*/ IMAD R6, R9, 0x800000, R6 ; /* 0x0080000009067824 */
/* 0x000fe400078e0206 */
/*0d30*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0d40*/ BRA 0xdd0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0d50*/ LOP3.LUT R6, R7, 0x80000000, R6, 0x48, !PT ; /* 0x8000000007067812 */
/* 0x000fc800078e4806 */
/*0d60*/ LOP3.LUT R6, R6, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000006067812 */
/* 0x000fe200078efcff */
/*0d70*/ BRA 0xdd0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0d80*/ LOP3.LUT R6, R7, 0x80000000, R6, 0x48, !PT ; /* 0x8000000007067812 */
/* 0x000fe200078e4806 */
/*0d90*/ BRA 0xdd0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0da0*/ MUFU.RSQ R6, -QNAN ; /* 0xffc0000000067908 */
/* 0x000e220000001400 */
/*0db0*/ BRA 0xdd0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0dc0*/ FADD.FTZ R6, R9, R5 ; /* 0x0000000509067221 */
/* 0x000fe40000010000 */
/*0dd0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0de0*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*0df0*/ MOV R9, R6 ; /* 0x0000000600097202 */
/* 0x001fe20000000f00 */
/*0e00*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0004 */
/*0e10*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff1e006007950 */
/* 0x000fea0003c3ffff */
/*0e20*/ BRA 0xe20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected calcDir
.globl calcDir
.p2align 8
.type calcDir,@function
calcDir:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x64
s_load_b32 s3, s[0:1], 0x50
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cvt_f32_i32_e32 v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_f32_e32 s3, v0
s_cbranch_execz .LBB0_2
s_load_b256 s[4:11], s[0:1], 0x20
v_ashrrev_i32_e32 v2, 31, v1
s_load_b256 s[12:19], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s18, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s19, v1, vcc_lo
global_load_b32 v2, v[2:3], off
v_add_co_u32 v6, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v1, vcc_lo
global_load_b32 v10, v[4:5], off
global_load_b32 v11, v[6:7], off
global_load_b32 v8, v[8:9], off
s_load_b128 s[4:7], s[0:1], 0x40
s_waitcnt vmcnt(3)
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s14, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s15, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s12, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s13, v3, vcc_lo
global_load_b32 v4, v[4:5], off
v_add_co_u32 v2, vcc_lo, s16, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s17, v3, vcc_lo
global_load_b32 v5, v[6:7], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(4)
v_cvt_i32_f32_e32 v3, v11
v_cvt_i32_f32_e32 v6, v10
s_waitcnt vmcnt(3)
v_cvt_i32_f32_e32 v7, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f32_i32_e32 v3, v3
v_cvt_f32_i32_e32 v6, v6
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v4, v3
v_cvt_f32_i32_e32 v3, v7
v_mul_f32_e32 v4, v8, v8
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v6, v5, v6 :: v_dual_sub_f32 v7, v2, v3
v_fmac_f32_e32 v4, v6, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v7, v7
v_mul_f32_e32 v2, 0x4f800000, v4
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v4, v2, vcc_lo
v_sqrt_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v4, -1, v3
v_add_nc_u32_e32 v5, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v9, -v4, v3, v2
v_fma_f32 v10, -v5, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s2, 0, v9
v_cndmask_b32_e64 v3, v3, v4, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s2, 0, v10
v_cndmask_b32_e64 v3, v3, v5, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, 0x37800000, v3
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v2, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v9, v3, v2, vcc_lo
v_div_scale_f32 v4, null, v9, v9, v6
v_div_scale_f32 v5, null, v9, v9, v8
v_div_scale_f32 v10, null, v9, v9, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v11, v4
v_rcp_f32_e32 v12, v5
v_div_scale_f32 v14, vcc_lo, v6, v9, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(TRANS32_DEP_3)
v_rcp_f32_e32 v13, v10
v_div_scale_f32 v15, s2, v8, v9, v8
v_div_scale_f32 v17, s3, v7, v9, v7
v_fma_f32 v2, -v4, v11, 1.0
s_waitcnt_depctr 0xfff
v_fma_f32 v3, -v5, v12, 1.0
v_fma_f32 v16, -v10, v13, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmac_f32 v11, v2, v11 :: v_dual_fmac_f32 v12, v3, v12
v_dual_fmac_f32 v13, v16, v13 :: v_dual_mul_f32 v16, v14, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mul_f32 v18, v15, v12 :: v_dual_mul_f32 v19, v17, v13
v_fma_f32 v2, -v4, v16, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v3, -v5, v18, v15
v_fma_f32 v20, -v10, v19, v17
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v16, v2, v11
v_fmac_f32_e32 v18, v3, v12
v_add_co_u32 v2, s0, s10, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fmac_f32_e32 v19, v20, v13
v_fma_f32 v4, -v4, v16, v14
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_fma_f32 v5, -v5, v18, v15
v_add_co_ci_u32_e64 v3, s0, s11, v1, s0
v_fma_f32 v10, -v10, v19, v17
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_div_fmas_f32 v11, v4, v11, v16
s_mov_b32 vcc_lo, s2
v_div_fmas_f32 v12, v5, v12, v18
s_mov_b32 vcc_lo, s3
v_div_fixup_f32 v6, v11, v9, v6
v_div_fmas_f32 v10, v10, v13, v19
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_div_fixup_f32 v8, v12, v9, v8
v_div_fixup_f32 v7, v10, v9, v7
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_store_b32 v[2:3], v6, off
global_store_b32 v[4:5], v8, off
global_store_b32 v[0:1], v7, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel calcDir
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 344
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size calcDir, .Lfunc_end0-calcDir
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .offset: 80
.size: 4
.value_kind: by_value
- .offset: 88
.size: 4
.value_kind: hidden_block_count_x
- .offset: 92
.size: 4
.value_kind: hidden_block_count_y
- .offset: 96
.size: 4
.value_kind: hidden_block_count_z
- .offset: 100
.size: 2
.value_kind: hidden_group_size_x
- .offset: 102
.size: 2
.value_kind: hidden_group_size_y
- .offset: 104
.size: 2
.value_kind: hidden_group_size_z
- .offset: 106
.size: 2
.value_kind: hidden_remainder_x
- .offset: 108
.size: 2
.value_kind: hidden_remainder_y
- .offset: 110
.size: 2
.value_kind: hidden_remainder_z
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 144
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 152
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 344
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: calcDir
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: calcDir.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c628e_00000000-6_gpuCalcDir.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z7calcDirPfS_S_S_S_S_PiS_S_S_fPfS_S_S_S_S_PiS_S_S_f
.type _Z45__device_stub__Z7calcDirPfS_S_S_S_S_PiS_S_S_fPfS_S_S_S_S_PiS_S_S_f, @function
_Z45__device_stub__Z7calcDirPfS_S_S_S_S_PiS_S_S_fPfS_S_S_S_S_PiS_S_S_f:
.LFB2051:
.cfi_startproc
endbr64
subq $264, %rsp
.cfi_def_cfa_offset 272
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
movss %xmm0, 12(%rsp)
movq 272(%rsp), %rax
movq %rax, 40(%rsp)
movq 280(%rsp), %rax
movq %rax, 32(%rsp)
movq 288(%rsp), %rax
movq %rax, 24(%rsp)
movq 296(%rsp), %rax
movq %rax, 16(%rsp)
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 80(%rsp), %rax
movq %rax, 168(%rsp)
leaq 72(%rsp), %rax
movq %rax, 176(%rsp)
leaq 64(%rsp), %rax
movq %rax, 184(%rsp)
leaq 56(%rsp), %rax
movq %rax, 192(%rsp)
leaq 48(%rsp), %rax
movq %rax, 200(%rsp)
leaq 40(%rsp), %rax
movq %rax, 208(%rsp)
leaq 32(%rsp), %rax
movq %rax, 216(%rsp)
leaq 24(%rsp), %rax
movq %rax, 224(%rsp)
leaq 16(%rsp), %rax
movq %rax, 232(%rsp)
leaq 12(%rsp), %rax
movq %rax, 240(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
leaq 104(%rsp), %rcx
leaq 96(%rsp), %rdx
leaq 124(%rsp), %rsi
leaq 112(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 280
pushq 104(%rsp)
.cfi_def_cfa_offset 288
leaq 176(%rsp), %r9
movq 140(%rsp), %rcx
movl 148(%rsp), %r8d
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
leaq calcDir(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 272
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z7calcDirPfS_S_S_S_S_PiS_S_S_fPfS_S_S_S_S_PiS_S_S_f, .-_Z45__device_stub__Z7calcDirPfS_S_S_S_S_PiS_S_S_fPfS_S_S_S_S_PiS_S_S_f
.globl calcDir
.type calcDir, @function
calcDir:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 40(%rsp)
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z45__device_stub__Z7calcDirPfS_S_S_S_S_PiS_S_S_fPfS_S_S_S_S_PiS_S_S_f
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size calcDir, .-calcDir
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "calcDir"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq calcDir(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpuCalcDir.hip"
.globl __device_stub__calcDir # -- Begin function __device_stub__calcDir
.p2align 4, 0x90
.type __device_stub__calcDir,@function
__device_stub__calcDir: # @__device_stub__calcDir
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movss %xmm0, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 232(%rsp), %rax
movq %rax, 184(%rsp)
leaq 12(%rsp), %rax
movq %rax, 192(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $calcDir, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size __device_stub__calcDir, .Lfunc_end0-__device_stub__calcDir
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $calcDir, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type calcDir,@object # @calcDir
.section .rodata,"a",@progbits
.globl calcDir
.p2align 3, 0x0
calcDir:
.quad __device_stub__calcDir
.size calcDir, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "calcDir"
.size .L__unnamed_1, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__calcDir
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym calcDir
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void zeroFillingKernel(float* idata, int row, int length, int height)
{
int tidx = blockIdx.x * blockDim.x + threadIdx.x;
int tidy = blockIdx.y * blockDim.y;
if(tidx < length && tidy < height)
{
//printf("idata[%d][%d]: = %f\n", (row+tidy), tidx,idata[tidx + (row+tidy) *length]);
idata[tidx + (row+tidy) *length] = 0;
idata[tidx + (row-tidy) *length] = 0;
//printf("idata[%d][%d]: = %f\n", (row+tidy), tidx,idata[tidx + (row+tidy) *length]);
}
} | code for sm_80
Function : _Z17zeroFillingKernelPfiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002600 */
/*0020*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R2, R2, c[0x0][0x4], RZ ; /* 0x0000010002027a24 */
/* 0x001fca00078e02ff */
/*0050*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fe20003f06270 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*0070*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x16c], P0 ; /* 0x00005b0000007a0c */
/* 0x000fda0000706670 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*00a0*/ IADD3 R3, R2.reuse, c[0x0][0x168], RZ ; /* 0x00005a0002037a10 */
/* 0x040fe20007ffe0ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IADD3 R5, -R2, c[0x0][0x168], RZ ; /* 0x00005a0002057a10 */
/* 0x000fc60007ffe1ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x16c], R0.reuse ; /* 0x00005b0003037a24 */
/* 0x100fe400078e0200 */
/*00e0*/ IMAD R5, R5, c[0x0][0x16c], R0 ; /* 0x00005b0005057a24 */
/* 0x000fe400078e0200 */
/*00f0*/ IMAD.WIDE R2, R3, R4, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fc800078e0204 */
/*0100*/ IMAD.WIDE R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fe200078e0204 */
/*0110*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe8000c101904 */
/*0120*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void zeroFillingKernel(float* idata, int row, int length, int height)
{
int tidx = blockIdx.x * blockDim.x + threadIdx.x;
int tidy = blockIdx.y * blockDim.y;
if(tidx < length && tidy < height)
{
//printf("idata[%d][%d]: = %f\n", (row+tidy), tidx,idata[tidx + (row+tidy) *length]);
idata[tidx + (row+tidy) *length] = 0;
idata[tidx + (row-tidy) *length] = 0;
//printf("idata[%d][%d]: = %f\n", (row+tidy), tidx,idata[tidx + (row+tidy) *length]);
}
} | .file "tmpxft_00160257_00000000-6_zeroFillingKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z17zeroFillingKernelPfiiiPfiii
.type _Z40__device_stub__Z17zeroFillingKernelPfiiiPfiii, @function
_Z40__device_stub__Z17zeroFillingKernelPfiiiPfiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17zeroFillingKernelPfiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z17zeroFillingKernelPfiiiPfiii, .-_Z40__device_stub__Z17zeroFillingKernelPfiiiPfiii
.globl _Z17zeroFillingKernelPfiii
.type _Z17zeroFillingKernelPfiii, @function
_Z17zeroFillingKernelPfiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z17zeroFillingKernelPfiiiPfiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17zeroFillingKernelPfiii, .-_Z17zeroFillingKernelPfiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17zeroFillingKernelPfiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17zeroFillingKernelPfiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void zeroFillingKernel(float* idata, int row, int length, int height)
{
int tidx = blockIdx.x * blockDim.x + threadIdx.x;
int tidy = blockIdx.y * blockDim.y;
if(tidx < length && tidy < height)
{
//printf("idata[%d][%d]: = %f\n", (row+tidy), tidx,idata[tidx + (row+tidy) *length]);
idata[tidx + (row+tidy) *length] = 0;
idata[tidx + (row-tidy) *length] = 0;
//printf("idata[%d][%d]: = %f\n", (row+tidy), tidx,idata[tidx + (row+tidy) *length]);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void zeroFillingKernel(float* idata, int row, int length, int height)
{
int tidx = blockIdx.x * blockDim.x + threadIdx.x;
int tidy = blockIdx.y * blockDim.y;
if(tidx < length && tidy < height)
{
//printf("idata[%d][%d]: = %f\n", (row+tidy), tidx,idata[tidx + (row+tidy) *length]);
idata[tidx + (row+tidy) *length] = 0;
idata[tidx + (row-tidy) *length] = 0;
//printf("idata[%d][%d]: = %f\n", (row+tidy), tidx,idata[tidx + (row+tidy) *length]);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void zeroFillingKernel(float* idata, int row, int length, int height)
{
int tidx = blockIdx.x * blockDim.x + threadIdx.x;
int tidy = blockIdx.y * blockDim.y;
if(tidx < length && tidy < height)
{
//printf("idata[%d][%d]: = %f\n", (row+tidy), tidx,idata[tidx + (row+tidy) *length]);
idata[tidx + (row+tidy) *length] = 0;
idata[tidx + (row-tidy) *length] = 0;
//printf("idata[%d][%d]: = %f\n", (row+tidy), tidx,idata[tidx + (row+tidy) *length]);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17zeroFillingKernelPfiii
.globl _Z17zeroFillingKernelPfiii
.p2align 8
.type _Z17zeroFillingKernelPfiii,@function
_Z17zeroFillingKernelPfiii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
v_mad_u64_u32 v[1:2], null, s14, s5, v[0:1]
s_mul_i32 s4, s15, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_cmp_lt_i32 s4, s3
s_cselect_b32 s3, -1, 0
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_b32 s3, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s3
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b32 s3, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v6, 0
s_waitcnt lgkmcnt(0)
s_add_i32 s5, s4, s3
s_sub_i32 s3, s3, s4
v_mad_u64_u32 v[2:3], null, s5, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, s3, s2, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[2:3], 2, v[4:5]
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_store_b32 v[0:1], v6, off
global_store_b32 v[2:3], v6, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17zeroFillingKernelPfiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17zeroFillingKernelPfiii, .Lfunc_end0-_Z17zeroFillingKernelPfiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17zeroFillingKernelPfiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17zeroFillingKernelPfiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void zeroFillingKernel(float* idata, int row, int length, int height)
{
int tidx = blockIdx.x * blockDim.x + threadIdx.x;
int tidy = blockIdx.y * blockDim.y;
if(tidx < length && tidy < height)
{
//printf("idata[%d][%d]: = %f\n", (row+tidy), tidx,idata[tidx + (row+tidy) *length]);
idata[tidx + (row+tidy) *length] = 0;
idata[tidx + (row-tidy) *length] = 0;
//printf("idata[%d][%d]: = %f\n", (row+tidy), tidx,idata[tidx + (row+tidy) *length]);
}
} | .text
.file "zeroFillingKernel.hip"
.globl _Z32__device_stub__zeroFillingKernelPfiii # -- Begin function _Z32__device_stub__zeroFillingKernelPfiii
.p2align 4, 0x90
.type _Z32__device_stub__zeroFillingKernelPfiii,@function
_Z32__device_stub__zeroFillingKernelPfiii: # @_Z32__device_stub__zeroFillingKernelPfiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17zeroFillingKernelPfiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__zeroFillingKernelPfiii, .Lfunc_end0-_Z32__device_stub__zeroFillingKernelPfiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17zeroFillingKernelPfiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17zeroFillingKernelPfiii,@object # @_Z17zeroFillingKernelPfiii
.section .rodata,"a",@progbits
.globl _Z17zeroFillingKernelPfiii
.p2align 3, 0x0
_Z17zeroFillingKernelPfiii:
.quad _Z32__device_stub__zeroFillingKernelPfiii
.size _Z17zeroFillingKernelPfiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17zeroFillingKernelPfiii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__zeroFillingKernelPfiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17zeroFillingKernelPfiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17zeroFillingKernelPfiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002600 */
/*0020*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R2, R2, c[0x0][0x4], RZ ; /* 0x0000010002027a24 */
/* 0x001fca00078e02ff */
/*0050*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fe20003f06270 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*0070*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x16c], P0 ; /* 0x00005b0000007a0c */
/* 0x000fda0000706670 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*00a0*/ IADD3 R3, R2.reuse, c[0x0][0x168], RZ ; /* 0x00005a0002037a10 */
/* 0x040fe20007ffe0ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IADD3 R5, -R2, c[0x0][0x168], RZ ; /* 0x00005a0002057a10 */
/* 0x000fc60007ffe1ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x16c], R0.reuse ; /* 0x00005b0003037a24 */
/* 0x100fe400078e0200 */
/*00e0*/ IMAD R5, R5, c[0x0][0x16c], R0 ; /* 0x00005b0005057a24 */
/* 0x000fe400078e0200 */
/*00f0*/ IMAD.WIDE R2, R3, R4, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fc800078e0204 */
/*0100*/ IMAD.WIDE R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fe200078e0204 */
/*0110*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe8000c101904 */
/*0120*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17zeroFillingKernelPfiii
.globl _Z17zeroFillingKernelPfiii
.p2align 8
.type _Z17zeroFillingKernelPfiii,@function
_Z17zeroFillingKernelPfiii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
v_mad_u64_u32 v[1:2], null, s14, s5, v[0:1]
s_mul_i32 s4, s15, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_cmp_lt_i32 s4, s3
s_cselect_b32 s3, -1, 0
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_b32 s3, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s3
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b32 s3, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v6, 0
s_waitcnt lgkmcnt(0)
s_add_i32 s5, s4, s3
s_sub_i32 s3, s3, s4
v_mad_u64_u32 v[2:3], null, s5, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, s3, s2, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[2:3], 2, v[4:5]
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_store_b32 v[0:1], v6, off
global_store_b32 v[2:3], v6, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17zeroFillingKernelPfiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17zeroFillingKernelPfiii, .Lfunc_end0-_Z17zeroFillingKernelPfiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17zeroFillingKernelPfiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17zeroFillingKernelPfiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00160257_00000000-6_zeroFillingKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z17zeroFillingKernelPfiiiPfiii
.type _Z40__device_stub__Z17zeroFillingKernelPfiiiPfiii, @function
_Z40__device_stub__Z17zeroFillingKernelPfiiiPfiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17zeroFillingKernelPfiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z17zeroFillingKernelPfiiiPfiii, .-_Z40__device_stub__Z17zeroFillingKernelPfiiiPfiii
.globl _Z17zeroFillingKernelPfiii
.type _Z17zeroFillingKernelPfiii, @function
_Z17zeroFillingKernelPfiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z17zeroFillingKernelPfiiiPfiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17zeroFillingKernelPfiii, .-_Z17zeroFillingKernelPfiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17zeroFillingKernelPfiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17zeroFillingKernelPfiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "zeroFillingKernel.hip"
.globl _Z32__device_stub__zeroFillingKernelPfiii # -- Begin function _Z32__device_stub__zeroFillingKernelPfiii
.p2align 4, 0x90
.type _Z32__device_stub__zeroFillingKernelPfiii,@function
_Z32__device_stub__zeroFillingKernelPfiii: # @_Z32__device_stub__zeroFillingKernelPfiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17zeroFillingKernelPfiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__zeroFillingKernelPfiii, .Lfunc_end0-_Z32__device_stub__zeroFillingKernelPfiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17zeroFillingKernelPfiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17zeroFillingKernelPfiii,@object # @_Z17zeroFillingKernelPfiii
.section .rodata,"a",@progbits
.globl _Z17zeroFillingKernelPfiii
.p2align 3, 0x0
_Z17zeroFillingKernelPfiii:
.quad _Z32__device_stub__zeroFillingKernelPfiii
.size _Z17zeroFillingKernelPfiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17zeroFillingKernelPfiii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__zeroFillingKernelPfiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17zeroFillingKernelPfiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
void print_caps(const cudaDeviceProp* props);
int main()
{
cudaDeviceProp props;
cudaGetDeviceProperties(&props, 0);
//printf("%d\n", props.maxThreadsPerBlock);
print_caps(&props);
}
void print_caps(const cudaDeviceProp* props)
{
printf("name: %s\n", props->name);
printf("shared memory per block: %.2fKB\n", (float)props->sharedMemPerBlock / 1024);
printf("total global memory: %.2fMB\n", (float)props->totalGlobalMem / 1048576);
printf("regs per block: %d\n", props->regsPerBlock);
printf("Warp size: %d\n", props->warpSize);
printf("Max threads per block: %d\n", props->maxThreadsPerBlock);
printf("max thread dimention: %dx%dx%d\n", props->maxThreadsDim[0], props->maxThreadsDim[1], props->maxThreadsDim[2]);
printf("max grid size: %dx%dx%d\n", props->maxThreadsDim[0], props->maxThreadsDim[1], props->maxThreadsDim[2]);
printf("clock rate: %dKHz\n", props->clockRate);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
void print_caps(const cudaDeviceProp* props);
int main()
{
cudaDeviceProp props;
cudaGetDeviceProperties(&props, 0);
//printf("%d\n", props.maxThreadsPerBlock);
print_caps(&props);
}
void print_caps(const cudaDeviceProp* props)
{
printf("name: %s\n", props->name);
printf("shared memory per block: %.2fKB\n", (float)props->sharedMemPerBlock / 1024);
printf("total global memory: %.2fMB\n", (float)props->totalGlobalMem / 1048576);
printf("regs per block: %d\n", props->regsPerBlock);
printf("Warp size: %d\n", props->warpSize);
printf("Max threads per block: %d\n", props->maxThreadsPerBlock);
printf("max thread dimention: %dx%dx%d\n", props->maxThreadsDim[0], props->maxThreadsDim[1], props->maxThreadsDim[2]);
printf("max grid size: %dx%dx%d\n", props->maxThreadsDim[0], props->maxThreadsDim[1], props->maxThreadsDim[2]);
printf("clock rate: %dKHz\n", props->clockRate);
} | .file "tmpxft_000e9164_00000000-6_cuda_info.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "name: %s\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "shared memory per block: %.2fKB\n"
.section .rodata.str1.1
.LC4:
.string "total global memory: %.2fMB\n"
.LC5:
.string "regs per block: %d\n"
.LC6:
.string "Warp size: %d\n"
.LC7:
.string "Max threads per block: %d\n"
.section .rodata.str1.8
.align 8
.LC8:
.string "max thread dimention: %dx%dx%d\n"
.section .rodata.str1.1
.LC9:
.string "max grid size: %dx%dx%d\n"
.LC10:
.string "clock rate: %dKHz\n"
.text
.globl _Z10print_capsPK14cudaDeviceProp
.type _Z10print_capsPK14cudaDeviceProp, @function
_Z10print_capsPK14cudaDeviceProp:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq %rdi, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 296(%rbx), %rax
testq %rax, %rax
js .L4
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
.L5:
mulss .LC1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 288(%rbx), %rax
testq %rax, %rax
js .L6
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
.L7:
mulss .LC3(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 304(%rbx), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 308(%rbx), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 320(%rbx), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 328(%rbx), %ecx
movl 324(%rbx), %edx
movl 332(%rbx), %r8d
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 328(%rbx), %ecx
movl 324(%rbx), %edx
movl 332(%rbx), %r8d
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rbx), %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L4:
.cfi_restore_state
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
addss %xmm0, %xmm0
jmp .L5
.L6:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
addss %xmm0, %xmm0
jmp .L7
.cfi_endproc
.LFE2058:
.size _Z10print_capsPK14cudaDeviceProp, .-_Z10print_capsPK14cudaDeviceProp
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1040, %rsp
.cfi_def_cfa_offset 1056
movq %fs:40, %rax
movq %rax, 1032(%rsp)
xorl %eax, %eax
movq %rsp, %rbx
movl $0, %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbx, %rdi
call _Z10print_capsPK14cudaDeviceProp
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L12
movl $0, %eax
addq $1040, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 981467136
.align 4
.LC3:
.long 897581056
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
void print_caps(const cudaDeviceProp* props);
int main()
{
cudaDeviceProp props;
cudaGetDeviceProperties(&props, 0);
//printf("%d\n", props.maxThreadsPerBlock);
print_caps(&props);
}
void print_caps(const cudaDeviceProp* props)
{
printf("name: %s\n", props->name);
printf("shared memory per block: %.2fKB\n", (float)props->sharedMemPerBlock / 1024);
printf("total global memory: %.2fMB\n", (float)props->totalGlobalMem / 1048576);
printf("regs per block: %d\n", props->regsPerBlock);
printf("Warp size: %d\n", props->warpSize);
printf("Max threads per block: %d\n", props->maxThreadsPerBlock);
printf("max thread dimention: %dx%dx%d\n", props->maxThreadsDim[0], props->maxThreadsDim[1], props->maxThreadsDim[2]);
printf("max grid size: %dx%dx%d\n", props->maxThreadsDim[0], props->maxThreadsDim[1], props->maxThreadsDim[2]);
printf("clock rate: %dKHz\n", props->clockRate);
} | #include <stdio.h>
#include <hip/hip_runtime.h>
void print_caps(const hipDeviceProp_t* props);
int main()
{
hipDeviceProp_t props;
hipGetDeviceProperties(&props, 0);
//printf("%d\n", props.maxThreadsPerBlock);
print_caps(&props);
}
void print_caps(const hipDeviceProp_t* props)
{
printf("name: %s\n", props->name);
printf("shared memory per block: %.2fKB\n", (float)props->sharedMemPerBlock / 1024);
printf("total global memory: %.2fMB\n", (float)props->totalGlobalMem / 1048576);
printf("regs per block: %d\n", props->regsPerBlock);
printf("Warp size: %d\n", props->warpSize);
printf("Max threads per block: %d\n", props->maxThreadsPerBlock);
printf("max thread dimention: %dx%dx%d\n", props->maxThreadsDim[0], props->maxThreadsDim[1], props->maxThreadsDim[2]);
printf("max grid size: %dx%dx%d\n", props->maxThreadsDim[0], props->maxThreadsDim[1], props->maxThreadsDim[2]);
printf("clock rate: %dKHz\n", props->clockRate);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
void print_caps(const hipDeviceProp_t* props);
int main()
{
hipDeviceProp_t props;
hipGetDeviceProperties(&props, 0);
//printf("%d\n", props.maxThreadsPerBlock);
print_caps(&props);
}
void print_caps(const hipDeviceProp_t* props)
{
printf("name: %s\n", props->name);
printf("shared memory per block: %.2fKB\n", (float)props->sharedMemPerBlock / 1024);
printf("total global memory: %.2fMB\n", (float)props->totalGlobalMem / 1048576);
printf("regs per block: %d\n", props->regsPerBlock);
printf("Warp size: %d\n", props->warpSize);
printf("Max threads per block: %d\n", props->maxThreadsPerBlock);
printf("max thread dimention: %dx%dx%d\n", props->maxThreadsDim[0], props->maxThreadsDim[1], props->maxThreadsDim[2]);
printf("max grid size: %dx%dx%d\n", props->maxThreadsDim[0], props->maxThreadsDim[1], props->maxThreadsDim[2]);
printf("clock rate: %dKHz\n", props->clockRate);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
void print_caps(const hipDeviceProp_t* props);
int main()
{
hipDeviceProp_t props;
hipGetDeviceProperties(&props, 0);
//printf("%d\n", props.maxThreadsPerBlock);
print_caps(&props);
}
void print_caps(const hipDeviceProp_t* props)
{
printf("name: %s\n", props->name);
printf("shared memory per block: %.2fKB\n", (float)props->sharedMemPerBlock / 1024);
printf("total global memory: %.2fMB\n", (float)props->totalGlobalMem / 1048576);
printf("regs per block: %d\n", props->regsPerBlock);
printf("Warp size: %d\n", props->warpSize);
printf("Max threads per block: %d\n", props->maxThreadsPerBlock);
printf("max thread dimention: %dx%dx%d\n", props->maxThreadsDim[0], props->maxThreadsDim[1], props->maxThreadsDim[2]);
printf("max grid size: %dx%dx%d\n", props->maxThreadsDim[0], props->maxThreadsDim[1], props->maxThreadsDim[2]);
printf("clock rate: %dKHz\n", props->clockRate);
} | .text
.file "cuda_info.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1472, %rsp # imm = 0x5C0
.cfi_def_cfa_offset 1488
.cfi_offset %rbx, -16
movq %rsp, %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movq %rbx, %rdi
callq _Z10print_capsPK20hipDeviceProp_tR0600
xorl %eax, %eax
addq $1472, %rsp # imm = 0x5C0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z10print_capsPK20hipDeviceProp_tR0600
.LCPI1_0:
.long 0x3a800000 # float 9.765625E-4
.LCPI1_1:
.long 0x35800000 # float 9.53674316E-7
.text
.globl _Z10print_capsPK20hipDeviceProp_tR0600
.p2align 4, 0x90
.type _Z10print_capsPK20hipDeviceProp_tR0600,@function
_Z10print_capsPK20hipDeviceProp_tR0600: # @_Z10print_capsPK20hipDeviceProp_tR0600
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movl $.L.str, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movq 296(%rbx), %rax
testq %rax, %rax
js .LBB1_1
# %bb.2:
cvtsi2ss %rax, %xmm0
jmp .LBB1_3
.LBB1_1:
movq %rax, %rcx
shrq %rcx
andl $1, %eax
orq %rcx, %rax
cvtsi2ss %rax, %xmm0
addss %xmm0, %xmm0
.LBB1_3:
mulss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 288(%rbx), %rax
testq %rax, %rax
js .LBB1_4
# %bb.5:
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
jmp .LBB1_6
.LBB1_4:
movq %rax, %rcx
shrq %rcx
andl $1, %eax
orq %rcx, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
addss %xmm0, %xmm0
.LBB1_6:
mulss .LCPI1_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movl 304(%rbx), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl 308(%rbx), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl 320(%rbx), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 324(%rbx), %esi
movl 328(%rbx), %edx
movl 332(%rbx), %ecx
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl 324(%rbx), %esi
movl 328(%rbx), %edx
movl 332(%rbx), %ecx
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 348(%rbx), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.Lfunc_end1:
.size _Z10print_capsPK20hipDeviceProp_tR0600, .Lfunc_end1-_Z10print_capsPK20hipDeviceProp_tR0600
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "name: %s\n"
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "shared memory per block: %.2fKB\n"
.size .L.str.1, 33
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "total global memory: %.2fMB\n"
.size .L.str.2, 29
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "regs per block: %d\n"
.size .L.str.3, 20
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Warp size: %d\n"
.size .L.str.4, 15
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Max threads per block: %d\n"
.size .L.str.5, 27
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "max thread dimention: %dx%dx%d\n"
.size .L.str.6, 32
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "max grid size: %dx%dx%d\n"
.size .L.str.7, 25
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "clock rate: %dKHz\n"
.size .L.str.8, 19
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e9164_00000000-6_cuda_info.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "name: %s\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "shared memory per block: %.2fKB\n"
.section .rodata.str1.1
.LC4:
.string "total global memory: %.2fMB\n"
.LC5:
.string "regs per block: %d\n"
.LC6:
.string "Warp size: %d\n"
.LC7:
.string "Max threads per block: %d\n"
.section .rodata.str1.8
.align 8
.LC8:
.string "max thread dimention: %dx%dx%d\n"
.section .rodata.str1.1
.LC9:
.string "max grid size: %dx%dx%d\n"
.LC10:
.string "clock rate: %dKHz\n"
.text
.globl _Z10print_capsPK14cudaDeviceProp
.type _Z10print_capsPK14cudaDeviceProp, @function
_Z10print_capsPK14cudaDeviceProp:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq %rdi, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 296(%rbx), %rax
testq %rax, %rax
js .L4
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
.L5:
mulss .LC1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 288(%rbx), %rax
testq %rax, %rax
js .L6
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
.L7:
mulss .LC3(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 304(%rbx), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 308(%rbx), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 320(%rbx), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 328(%rbx), %ecx
movl 324(%rbx), %edx
movl 332(%rbx), %r8d
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 328(%rbx), %ecx
movl 324(%rbx), %edx
movl 332(%rbx), %r8d
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rbx), %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L4:
.cfi_restore_state
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
addss %xmm0, %xmm0
jmp .L5
.L6:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
addss %xmm0, %xmm0
jmp .L7
.cfi_endproc
.LFE2058:
.size _Z10print_capsPK14cudaDeviceProp, .-_Z10print_capsPK14cudaDeviceProp
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1040, %rsp
.cfi_def_cfa_offset 1056
movq %fs:40, %rax
movq %rax, 1032(%rsp)
xorl %eax, %eax
movq %rsp, %rbx
movl $0, %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbx, %rdi
call _Z10print_capsPK14cudaDeviceProp
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L12
movl $0, %eax
addq $1040, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 981467136
.align 4
.LC3:
.long 897581056
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_info.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1472, %rsp # imm = 0x5C0
.cfi_def_cfa_offset 1488
.cfi_offset %rbx, -16
movq %rsp, %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movq %rbx, %rdi
callq _Z10print_capsPK20hipDeviceProp_tR0600
xorl %eax, %eax
addq $1472, %rsp # imm = 0x5C0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z10print_capsPK20hipDeviceProp_tR0600
.LCPI1_0:
.long 0x3a800000 # float 9.765625E-4
.LCPI1_1:
.long 0x35800000 # float 9.53674316E-7
.text
.globl _Z10print_capsPK20hipDeviceProp_tR0600
.p2align 4, 0x90
.type _Z10print_capsPK20hipDeviceProp_tR0600,@function
_Z10print_capsPK20hipDeviceProp_tR0600: # @_Z10print_capsPK20hipDeviceProp_tR0600
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movl $.L.str, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movq 296(%rbx), %rax
testq %rax, %rax
js .LBB1_1
# %bb.2:
cvtsi2ss %rax, %xmm0
jmp .LBB1_3
.LBB1_1:
movq %rax, %rcx
shrq %rcx
andl $1, %eax
orq %rcx, %rax
cvtsi2ss %rax, %xmm0
addss %xmm0, %xmm0
.LBB1_3:
mulss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 288(%rbx), %rax
testq %rax, %rax
js .LBB1_4
# %bb.5:
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
jmp .LBB1_6
.LBB1_4:
movq %rax, %rcx
shrq %rcx
andl $1, %eax
orq %rcx, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
addss %xmm0, %xmm0
.LBB1_6:
mulss .LCPI1_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movl 304(%rbx), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl 308(%rbx), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl 320(%rbx), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 324(%rbx), %esi
movl 328(%rbx), %edx
movl 332(%rbx), %ecx
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl 324(%rbx), %esi
movl 328(%rbx), %edx
movl 332(%rbx), %ecx
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 348(%rbx), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.Lfunc_end1:
.size _Z10print_capsPK20hipDeviceProp_tR0600, .Lfunc_end1-_Z10print_capsPK20hipDeviceProp_tR0600
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "name: %s\n"
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "shared memory per block: %.2fKB\n"
.size .L.str.1, 33
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "total global memory: %.2fMB\n"
.size .L.str.2, 29
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "regs per block: %d\n"
.size .L.str.3, 20
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Warp size: %d\n"
.size .L.str.4, 15
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Max threads per block: %d\n"
.size .L.str.5, 27
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "max thread dimention: %dx%dx%d\n"
.size .L.str.6, 32
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "max grid size: %dx%dx%d\n"
.size .L.str.7, 25
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "clock rate: %dKHz\n"
.size .L.str.8, 19
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void hello() {
printf("Hello, CUDA! Thread [%d] in block [%d]\n", threadIdx.x, blockIdx.x);
}
int main( int argc, char** argv ) {
hello<<<1,1>>>(); // asynchronous call!
cudaDeviceSynchronize(); // wait for all operations on the GPU to finish
return 0;
} | code for sm_80
Function : _Z5hellov
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0060*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0080*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a60000000a00 */
/*0090*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*00a0*/ STL.64 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0013e80000100a00 */
/*00b0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x002fc60000000000 */
/*00c0*/ MOV R11, 0x130 ; /* 0x00000130000b7802 */
/* 0x000fe40000000f00 */
/*00d0*/ MOV R20, 0xb0 ; /* 0x000000b000147802 */
/* 0x000fc40000000f00 */
/*00e0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0100*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0110*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0120*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x004fea0003c00000 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void hello() {
printf("Hello, CUDA! Thread [%d] in block [%d]\n", threadIdx.x, blockIdx.x);
}
int main( int argc, char** argv ) {
hello<<<1,1>>>(); // asynchronous call!
cudaDeviceSynchronize(); // wait for all operations on the GPU to finish
return 0;
} | .file "tmpxft_000254d3_00000000-6_lab0b.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z5hellovv
.type _Z23__device_stub__Z5hellovv, @function
_Z23__device_stub__Z5hellovv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z5hellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z23__device_stub__Z5hellovv, .-_Z23__device_stub__Z5hellovv
.globl _Z5hellov
.type _Z5hellov, @function
_Z5hellov:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z5hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5hellov, .-_Z5hellov
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z23__device_stub__Z5hellovv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5hellov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5hellov(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void hello() {
printf("Hello, CUDA! Thread [%d] in block [%d]\n", threadIdx.x, blockIdx.x);
}
int main( int argc, char** argv ) {
hello<<<1,1>>>(); // asynchronous call!
cudaDeviceSynchronize(); // wait for all operations on the GPU to finish
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void hello() {
printf("Hello, CUDA! Thread [%d] in block [%d]\n", threadIdx.x, blockIdx.x);
}
int main( int argc, char** argv ) {
hello<<<1,1>>>(); // asynchronous call!
hipDeviceSynchronize(); // wait for all operations on the GPU to finish
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void hello() {
printf("Hello, CUDA! Thread [%d] in block [%d]\n", threadIdx.x, blockIdx.x);
}
int main( int argc, char** argv ) {
hello<<<1,1>>>(); // asynchronous call!
hipDeviceSynchronize(); // wait for all operations on the GPU to finish
return 0;
} | .text
.file "lab0b.hip"
.globl _Z20__device_stub__hellov # -- Begin function _Z20__device_stub__hellov
.p2align 4, 0x90
.type _Z20__device_stub__hellov,@function
_Z20__device_stub__hellov: # @_Z20__device_stub__hellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z20__device_stub__hellov, .Lfunc_end0-_Z20__device_stub__hellov
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5hellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5hellov,@object # @_Z5hellov
.section .rodata,"a",@progbits
.globl _Z5hellov
.p2align 3, 0x0
_Z5hellov:
.quad _Z20__device_stub__hellov
.size _Z5hellov, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5hellov"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__hellov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5hellov
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000254d3_00000000-6_lab0b.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z5hellovv
.type _Z23__device_stub__Z5hellovv, @function
_Z23__device_stub__Z5hellovv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z5hellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z23__device_stub__Z5hellovv, .-_Z23__device_stub__Z5hellovv
.globl _Z5hellov
.type _Z5hellov, @function
_Z5hellov:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z5hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5hellov, .-_Z5hellov
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z23__device_stub__Z5hellovv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5hellov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5hellov(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "lab0b.hip"
.globl _Z20__device_stub__hellov # -- Begin function _Z20__device_stub__hellov
.p2align 4, 0x90
.type _Z20__device_stub__hellov,@function
_Z20__device_stub__hellov: # @_Z20__device_stub__hellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z20__device_stub__hellov, .Lfunc_end0-_Z20__device_stub__hellov
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5hellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5hellov,@object # @_Z5hellov
.section .rodata,"a",@progbits
.globl _Z5hellov
.p2align 3, 0x0
_Z5hellov:
.quad _Z20__device_stub__hellov
.size _Z5hellov, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5hellov"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__hellov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5hellov
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void mysgemmNT( const float *A, int lda, const float *B, int ldb, float* C, int ldc, int k, float alpha, float beta )
{
float c = 0.0f;
int m = blockIdx.x * blockDim.x + threadIdx.x;
int n = blockIdx.y * blockDim.y + threadIdx.y;
for (int i = 0; i < k; ++i) {
float a = A[m + i * lda];
float b = B[n + i * ldb];
c += a * b;
}
C[m+n*ldc] = C[m+n*ldc] * beta + alpha * c;
} | code for sm_80
Function : _Z9mysgemmNTPKfiS0_iPfiiff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R4, c[0x0][0x18c] ; /* 0x0000630000047a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R10, -RZ, RZ, 0, 0 ; /* 0x00000000ff0a7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0080*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*00a0*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fc600078e0205 */
/*00b0*/ @!P0 BRA 0xc80 ; /* 0x00000bc000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R4, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x000fe40007ffe0ff */
/*00d0*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fe40000000f00 */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*00f0*/ LOP3.LUT R2, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304027812 */
/* 0x000fe400078ec0ff */
/*0100*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0110*/ @!P0 BRA 0xb90 ; /* 0x00000a7000008947 */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R5, -R2, c[0x0][0x18c], RZ ; /* 0x0000630002057a10 */
/* 0x000fe20007ffe1ff */
/*0130*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fe200000001ff */
/*0140*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fe20000000f00 */
/*0150*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*0160*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fce0003f04270 */
/*0170*/ IMAD.WIDE R14, R3, R6, c[0x0][0x170] ; /* 0x00005c00030e7625 */
/* 0x000fc800078e0206 */
/*0180*/ IMAD.WIDE R16, R0, R6, c[0x0][0x160] ; /* 0x0000580000107625 */
/* 0x000fe400078e0206 */
/*0190*/ @!P0 BRA 0xa10 ; /* 0x0000087000008947 */
/* 0x000fea0003800000 */
/*01a0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01c0*/ @!P1 BRA 0x720 ; /* 0x0000055000009947 */
/* 0x000fea0003800000 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01e0*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x0000a8000c1e1900 */
/*01f0*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x0002a2000c1e1900 */
/*0200*/ IMAD.WIDE R22, R6, c[0x0][0x178], R14 ; /* 0x00005e0006167a25 */
/* 0x000fc800078e020e */
/*0210*/ IMAD.WIDE R26, R6.reuse, c[0x0][0x168], R16 ; /* 0x00005a00061a7a25 */
/* 0x040fe200078e0210 */
/*0220*/ LDG.E R11, [R22.64] ; /* 0x00000004160b7981 */
/* 0x000728000c1e1900 */
/*0230*/ LDG.E R24, [R26.64] ; /* 0x000000041a187981 */
/* 0x000b22000c1e1900 */
/*0240*/ IMAD.WIDE R22, R6, c[0x0][0x178], R22 ; /* 0x00005e0006167a25 */
/* 0x008fc800078e0216 */
/*0250*/ IMAD.WIDE R26, R6.reuse, c[0x0][0x168], R26 ; /* 0x00005a00061a7a25 */
/* 0x060fe200078e021a */
/*0260*/ LDG.E R19, [R22.64] ; /* 0x0000000416137981 */
/* 0x000766000c1e1900 */
/*0270*/ IMAD.WIDE R14, R6.reuse, c[0x0][0x178], R22 ; /* 0x00005e00060e7a25 */
/* 0x041fe200078e0216 */
/*0280*/ LDG.E R18, [R26.64] ; /* 0x000000041a127981 */
/* 0x000166000c1e1900 */
/*0290*/ IMAD.WIDE R12, R6.reuse, c[0x0][0x168], R26 ; /* 0x00005a00060c7a25 */
/* 0x040fe200078e021a */
/*02a0*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x002368000c1e1900 */
/*02b0*/ LDG.E R25, [R12.64] ; /* 0x000000040c197981 */
/* 0x000162000c1e1900 */
/*02c0*/ IMAD.WIDE R28, R6, c[0x0][0x168], R12 ; /* 0x00005a00061c7a25 */
/* 0x000fc800078e020c */
/*02d0*/ IMAD.WIDE R14, R6.reuse, c[0x0][0x178], R14 ; /* 0x00005e00060e7a25 */
/* 0x042fe200078e020e */
/*02e0*/ LDG.E R17, [R28.64] ; /* 0x000000041c117981 */
/* 0x000368000c1e1900 */
/*02f0*/ LDG.E R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x008762000c1e1900 */
/*0300*/ IMAD.WIDE R26, R6, c[0x0][0x178], R14 ; /* 0x00005e00061a7a25 */
/* 0x001fc800078e020e */
/*0310*/ IMAD.WIDE R28, R6.reuse, c[0x0][0x168], R28 ; /* 0x00005a00061c7a25 */
/* 0x042fe200078e021c */
/*0320*/ LDG.E R23, [R26.64] ; /* 0x000000041a177981 */
/* 0x00016a000c1e1900 */
/*0330*/ IMAD.WIDE R12, R6.reuse, c[0x0][0x168], R28 ; /* 0x00005a00060c7a25 */
/* 0x040fe400078e021c */
/*0340*/ LDG.E R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000564000c1e1900 */
/*0350*/ IMAD.WIDE R26, R6, c[0x0][0x178], R26 ; /* 0x00005e00061a7a25 */
/* 0x001fc400078e021a */
/*0360*/ LDG.E R7, [R12.64] ; /* 0x000000040c077981 */
/* 0x000168000c1e1900 */
/*0370*/ LDG.E R8, [R26.64] ; /* 0x000000041a087981 */
/* 0x000362000c1e1900 */
/*0380*/ IMAD.WIDE R14, R6, c[0x0][0x178], R26 ; /* 0x00005e00060e7a25 */
/* 0x008fc800078e021a */
/*0390*/ IMAD.WIDE R12, R6, c[0x0][0x168], R12 ; /* 0x00005a00060c7a25 */
/* 0x001fc800078e020c */
/*03a0*/ FFMA R29, R20, R9, R10 ; /* 0x00000009141d7223 */
/* 0x004fe4000000000a */
/*03b0*/ LDG.E R9, [R12.64] ; /* 0x000000040c097981 */
/* 0x0000a8000c1e1900 */
/*03c0*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x0006a2000c1e1900 */
/*03d0*/ IMAD.WIDE R20, R6, c[0x0][0x168], R12 ; /* 0x00005a0006147a25 */
/* 0x000fc800078e020c */
/*03e0*/ FFMA R29, R11, R24, R29 ; /* 0x000000180b1d7223 */
/* 0x010fe4000000001d */
/*03f0*/ LDG.E R24, [R20.64] ; /* 0x0000000414187981 */
/* 0x0008a2000c1e1900 */
/*0400*/ IMAD.WIDE R14, R6, c[0x0][0x178], R14 ; /* 0x00005e00060e7a25 */
/* 0x008fca00078e020e */
/*0410*/ LDG.E R11, [R14.64] ; /* 0x000000040e0b7981 */
/* 0x0006a2000c1e1900 */
/*0420*/ IMAD.WIDE R26, R6, c[0x0][0x168], R20 ; /* 0x00005a00061a7a25 */
/* 0x002fc800078e0214 */
/*0430*/ FFMA R29, R19, R18, R29 ; /* 0x00000012131d7223 */
/* 0x020fe4000000001d */
/*0440*/ IMAD.WIDE R18, R6, c[0x0][0x178], R14 ; /* 0x00005e0006127a25 */
/* 0x000fc800078e020e */
/*0450*/ FFMA R16, R16, R25, R29 ; /* 0x0000001910107223 */
/* 0x000fe4000000001d */
/*0460*/ LDG.E R25, [R18.64] ; /* 0x0000000412197981 */
/* 0x000362000c1e1900 */
/*0470*/ IMAD.WIDE R12, R6, c[0x0][0x168], R26 ; /* 0x00005a00060c7a25 */
/* 0x001fc600078e021a */
/*0480*/ LDG.E R26, [R26.64] ; /* 0x000000041a1a7981 */
/* 0x000162000c1e1900 */
/*0490*/ IMAD.WIDE R18, R6, c[0x0][0x178], R18 ; /* 0x00005e0006127a25 */
/* 0x002fc800078e0212 */
/*04a0*/ FFMA R22, R22, R17, R16 ; /* 0x0000001116167223 */
/* 0x000fe20000000010 */
/*04b0*/ LDG.E R27, [R18.64] ; /* 0x00000004121b7981 */
/* 0x001162000c1e1900 */
/*04c0*/ IMAD.WIDE R14, R6, c[0x0][0x168], R12 ; /* 0x00005a00060e7a25 */
/* 0x008fc600078e020c */
/*04d0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x0004e2000c1e1900 */
/*04e0*/ IMAD.WIDE R16, R6, c[0x0][0x178], R18 ; /* 0x00005e0006107a25 */
/* 0x000fc600078e0212 */
/*04f0*/ LDG.E R29, [R14.64] ; /* 0x000000040e1d7981 */
/* 0x0002e2000c1e1900 */
/*0500*/ FFMA R28, R23, R28, R22 ; /* 0x0000001c171c7223 */
/* 0x000fe40000000016 */
/*0510*/ IMAD.WIDE R20, R6, c[0x0][0x168], R14 ; /* 0x00005a0006147a25 */
/* 0x010fc800078e020e */
/*0520*/ IMAD.WIDE R22, R6, c[0x0][0x178], R16 ; /* 0x00005e0006167a25 */
/* 0x000fe400078e0210 */
/*0530*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008e4000c1e1900 */
/*0540*/ FFMA R8, R8, R7, R28 ; /* 0x0000000708087223 */
/* 0x000fe4000000001c */
/*0550*/ IMAD.WIDE R14, R6.reuse, c[0x0][0x168], R20 ; /* 0x00005a00060e7a25 */
/* 0x042fe200078e0214 */
/*0560*/ LDG.E R7, [R22.64] ; /* 0x0000000416077981 */
/* 0x0002e6000c1e1900 */
/*0570*/ IMAD.WIDE R18, R6, c[0x0][0x178], R22 ; /* 0x00005e0006127a25 */
/* 0x001fe200078e0216 */
/*0580*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ee6000c1e1900 */
/*0590*/ FFMA R13, R10, R9, R8 ; /* 0x000000090a0d7223 */
/* 0x004fc40000000008 */
/*05a0*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x0000a2000c1e1900 */
/*05b0*/ IMAD.WIDE R8, R6, c[0x0][0x168], R14 ; /* 0x00005a0006087a25 */
/* 0x000fc600078e020e */
/*05c0*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000ea8000c1e1900 */
/*05d0*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x0108a2000c1e1900 */
/*05e0*/ IMAD.WIDE R18, R6, c[0x0][0x178], R18 ; /* 0x00005e0006127a25 */
/* 0x001fca00078e0212 */
/*05f0*/ LDG.E R28, [R18.64] ; /* 0x00000004121c7981 */
/* 0x000ea2000c1e1900 */
/*0600*/ IMAD.WIDE R22, R6, c[0x0][0x178], R18 ; /* 0x00005e0006167a25 */
/* 0x002fc800078e0212 */
/*0610*/ IMAD.WIDE R8, R6, c[0x0][0x168], R8 ; /* 0x00005a0006087a25 */
/* 0x010fc800078e0208 */
/*0620*/ FFMA R13, R11, R24, R13 ; /* 0x000000180b0d7223 */
/* 0x000fe4000000000d */
/*0630*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000f28000c1e1900 */
/*0640*/ LDG.E R11, [R22.64] ; /* 0x00000004160b7981 */
/* 0x000f22000c1e1900 */
/*0650*/ FFMA R13, R25, R26, R13 ; /* 0x0000001a190d7223 */
/* 0x020fe2000000000d */
/*0660*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc80007ffe0ff */
/*0670*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe20003f24270 */
/*0680*/ FFMA R12, R27, R12, R13 ; /* 0x0000000c1b0c7223 */
/* 0x008fc8000000000d */
/*0690*/ FFMA R12, R16, R29, R12 ; /* 0x0000001d100c7223 */
/* 0x000fc8000000000c */
/*06a0*/ FFMA R7, R7, R20, R12 ; /* 0x0000001407077223 */
/* 0x000fe2000000000c */
/*06b0*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*06c0*/ FFMA R7, R10, R15, R7 ; /* 0x0000000f0a077223 */
/* 0x004fe40000000007 */
/*06d0*/ IMAD.WIDE R14, R6, c[0x0][0x178], R22 ; /* 0x00005e00060e7a25 */
/* 0x000fc800078e0216 */
/*06e0*/ FFMA R7, R28, R17, R7 ; /* 0x000000111c077223 */
/* 0x000fe40000000007 */
/*06f0*/ IMAD.WIDE R16, R6, c[0x0][0x168], R8 ; /* 0x00005a0006107a25 */
/* 0x000fc800078e0208 */
/*0700*/ FFMA R10, R11, R24, R7 ; /* 0x000000180b0a7223 */
/* 0x010fe20000000007 */
/*0710*/ @P1 BRA 0x1e0 ; /* 0xfffffac000001947 */
/* 0x000fea000383ffff */
/*0720*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*0730*/ @!P1 BRA 0x9f0 ; /* 0x000002b000009947 */
/* 0x000fea0003800000 */
/*0740*/ LDG.E R27, [R14.64] ; /* 0x000000040e1b7981 */
/* 0x0000a8000c1e1900 */
/*0750*/ LDG.E R28, [R16.64] ; /* 0x00000004101c7981 */
/* 0x0002a2000c1e1900 */
/*0760*/ IMAD.WIDE R8, R6, c[0x0][0x168], R16 ; /* 0x00005a0006087a25 */
/* 0x000fc800078e0210 */
/*0770*/ IMAD.WIDE R12, R6, c[0x0][0x178], R14 ; /* 0x00005e00060c7a25 */
/* 0x000fc800078e020e */
/*0780*/ IMAD.WIDE R14, R6.reuse, c[0x0][0x168], R8 ; /* 0x00005a00060e7a25 */
/* 0x041fe200078e0208 */
/*0790*/ LDG.E R7, [R12.64] ; /* 0x000000040c077981 */
/* 0x0000e6000c1e1900 */
/*07a0*/ IMAD.WIDE R18, R6.reuse, c[0x0][0x178], R12 ; /* 0x00005e0006127a25 */
/* 0x040fe200078e020c */
/*07b0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x0008e6000c1e1900 */
/*07c0*/ IMAD.WIDE R16, R6.reuse, c[0x0][0x168], R14 ; /* 0x00005a0006107a25 */
/* 0x042fe200078e020e */
/*07d0*/ LDG.E R25, [R18.64] ; /* 0x0000000412197981 */
/* 0x000366000c1e1900 */
/*07e0*/ IMAD.WIDE R20, R6.reuse, c[0x0][0x178], R18 ; /* 0x00005e0006147a25 */
/* 0x040fe200078e0212 */
/*07f0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000366000c1e1900 */
/*0800*/ IMAD.WIDE R12, R6.reuse, c[0x0][0x168], R16 ; /* 0x00005a00060c7a25 */
/* 0x041fe200078e0210 */
/*0810*/ LDG.E R24, [R16.64] ; /* 0x0000000410187981 */
/* 0x000166000c1e1900 */
/*0820*/ IMAD.WIDE R22, R6, c[0x0][0x178], R20 ; /* 0x00005e0006167a25 */
/* 0x000fc400078e0214 */
/*0830*/ LDG.E R21, [R20.64] ; /* 0x0000000414157981 */
/* 0x000964000c1e1900 */
/*0840*/ IMAD.WIDE R14, R6.reuse, c[0x0][0x168], R12 ; /* 0x00005a00060e7a25 */
/* 0x042fe400078e020c */
/*0850*/ LDG.E R11, [R22.64] ; /* 0x00000004160b7981 */
/* 0x000364000c1e1900 */
/*0860*/ IMAD.WIDE R16, R6.reuse, c[0x0][0x178], R22 ; /* 0x00005e0006107a25 */
/* 0x041fe400078e0216 */
/*0870*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x010128000c1e1900 */
/*0880*/ IMAD.WIDE R18, R6.reuse, c[0x0][0x178], R16 ; /* 0x00005e0006127a25 */
/* 0x040fe200078e0210 */
/*0890*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000326000c1e1900 */
/*08a0*/ IMAD.WIDE R12, R6, c[0x0][0x168], R14 ; /* 0x00005a00060c7a25 */
/* 0x001fc400078e020e */
/*08b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f28000c1e1900 */
/*08c0*/ LDG.E R16, [R18.64] ; /* 0x0000000412107981 */
/* 0x002122000c1e1900 */
/*08d0*/ IMAD.WIDE R22, R6, c[0x0][0x168], R12 ; /* 0x00005a0006167a25 */
/* 0x000fc600078e020c */
/*08e0*/ LDG.E R29, [R12.64] ; /* 0x000000040c1d7981 */
/* 0x000f22000c1e1900 */
/*08f0*/ IMAD.WIDE R18, R6, c[0x0][0x178], R18 ; /* 0x00005e0006127a25 */
/* 0x001fc800078e0212 */
/*0900*/ FFMA R28, R27, R28, R10 ; /* 0x0000001c1b1c7223 */
/* 0x004fe4000000000a */
/*0910*/ LDG.E R27, [R22.64] ; /* 0x00000004161b7981 */
/* 0x000ea8000c1e1900 */
/*0920*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x000ea2000c1e1900 */
/*0930*/ FFMA R7, R7, R8, R28 ; /* 0x0000000807077223 */
/* 0x008fc8000000001c */
/*0940*/ FFMA R7, R25, R26, R7 ; /* 0x0000001a19077223 */
/* 0x020fc80000000007 */
/*0950*/ FFMA R7, R21, R24, R7 ; /* 0x0000001815077223 */
/* 0x000fc80000000007 */
/*0960*/ FFMA R7, R11, R20, R7 ; /* 0x000000140b077223 */
/* 0x010fe20000000007 */
/*0970*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0980*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe20007ffe0ff */
/*0990*/ FFMA R7, R9, R14, R7 ; /* 0x0000000e09077223 */
/* 0x000fe20000000007 */
/*09a0*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*09b0*/ IMAD.WIDE R14, R6, c[0x0][0x178], R18 ; /* 0x00005e00060e7a25 */
/* 0x000fc800078e0212 */
/*09c0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fe40000000007 */
/*09d0*/ IMAD.WIDE R16, R6, c[0x0][0x168], R22 ; /* 0x00005a0006107a25 */
/* 0x000fc800078e0216 */
/*09e0*/ FFMA R10, R10, R27, R7 ; /* 0x0000001b0a0a7223 */
/* 0x004fe40000000007 */
/*09f0*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0a00*/ @!P0 BRA 0xb90 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0a10*/ IMAD.WIDE R8, R6.reuse, c[0x0][0x168], R16 ; /* 0x00005a0006087a25 */
/* 0x040fe400078e0210 */
/*0a20*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea4000c1e1900 */
/*0a30*/ IMAD.WIDE R12, R6.reuse, c[0x0][0x178], R14 ; /* 0x00005e00060c7a25 */
/* 0x040fe400078e020e */
/*0a40*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x0000a4000c1e1900 */
/*0a50*/ IMAD.WIDE R22, R6.reuse, c[0x0][0x168], R8 ; /* 0x00005a0006167a25 */
/* 0x040fe400078e0208 */
/*0a60*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee4000c1e1900 */
/*0a70*/ IMAD.WIDE R18, R6, c[0x0][0x178], R12 ; /* 0x00005e0006127a25 */
/* 0x000fc400078e020c */
/*0a80*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee4000c1e1900 */
/*0a90*/ IMAD.WIDE R20, R6.reuse, c[0x0][0x168], R22 ; /* 0x00005a0006147a25 */
/* 0x040fe400078e0216 */
/*0aa0*/ LDG.E R7, [R22.64] ; /* 0x0000000416077981 */
/* 0x000f24000c1e1900 */
/*0ab0*/ IMAD.WIDE R24, R6, c[0x0][0x178], R18 ; /* 0x00005e0006187a25 */
/* 0x000fe400078e0212 */
/*0ac0*/ LDG.E R26, [R18.64] ; /* 0x00000004121a7981 */
/* 0x000f28000c1e1900 */
/*0ad0*/ LDG.E R11, [R20.64] ; /* 0x00000004140b7981 */
/* 0x000f68000c1e1900 */
/*0ae0*/ LDG.E R14, [R24.64] ; /* 0x00000004180e7981 */
/* 0x001f62000c1e1900 */
/*0af0*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f05270 */
/*0b10*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fe20007ffe0ff */
/*0b20*/ FFMA R15, R15, R16, R10 ; /* 0x000000100f0f7223 */
/* 0x004fc8000000000a */
/*0b30*/ FFMA R15, R12, R8, R15 ; /* 0x000000080c0f7223 */
/* 0x008fe4000000000f */
/*0b40*/ IMAD.WIDE R16, R6, c[0x0][0x168], R20 ; /* 0x00005a0006107a25 */
/* 0x000fc800078e0214 */
/*0b50*/ FFMA R7, R26, R7, R15 ; /* 0x000000071a077223 */
/* 0x010fc8000000000f */
/*0b60*/ FFMA R10, R14, R11, R7 ; /* 0x0000000b0e0a7223 */
/* 0x020fe40000000007 */
/*0b70*/ IMAD.WIDE R14, R6, c[0x0][0x178], R24 ; /* 0x00005e00060e7a25 */
/* 0x000fe200078e0218 */
/*0b80*/ @P0 BRA 0xa10 ; /* 0xfffffe8000000947 */
/* 0x000fea000383ffff */
/*0b90*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*0ba0*/ @!P0 BRA 0xc80 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0bb0*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*0bc0*/ IMAD R5, R4.reuse, c[0x0][0x178], R3 ; /* 0x00005e0004057a24 */
/* 0x040fe400078e0203 */
/*0bd0*/ IMAD R6, R4, c[0x0][0x168], R0 ; /* 0x00005a0004067a24 */
/* 0x000fce00078e0200 */
/*0be0*/ IMAD.WIDE R4, R5, R11, c[0x0][0x170] ; /* 0x00005c0005047625 */
/* 0x000fc800078e020b */
/*0bf0*/ IMAD.WIDE R6, R6, R11, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e020b */
/*0c00*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x0000a8000c1e1900 */
/*0c10*/ LDG.E R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x0002a2000c1e1900 */
/*0c20*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fc80007ffe0ff */
/*0c30*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0c40*/ IMAD.WIDE R4, R11, c[0x0][0x178], R4 ; /* 0x00005e000b047a25 */
/* 0x001fc800078e0204 */
/*0c50*/ IMAD.WIDE R6, R11, c[0x0][0x168], R6 ; /* 0x00005a000b067a25 */
/* 0x002fc800078e0206 */
/*0c60*/ FFMA R10, R9, R8, R10 ; /* 0x00000008090a7223 */
/* 0x004fc8000000000a */
/*0c70*/ @P0 BRA 0xc00 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*0c80*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0c90*/ IMAD R3, R3, c[0x0][0x188], R0 ; /* 0x0000620003037a24 */
/* 0x000fc800078e0200 */
/*0ca0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x180] ; /* 0x0000600003027625 */
/* 0x000fca00078e0202 */
/*0cb0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0cc0*/ FMUL R5, R0, c[0x0][0x194] ; /* 0x0000650000057a20 */
/* 0x004fc80000400000 */
/*0cd0*/ FFMA R5, R10, c[0x0][0x190], R5 ; /* 0x000064000a057a23 */
/* 0x000fca0000000005 */
/*0ce0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0cf0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d00*/ BRA 0xd00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void mysgemmNT( const float *A, int lda, const float *B, int ldb, float* C, int ldc, int k, float alpha, float beta )
{
float c = 0.0f;
int m = blockIdx.x * blockDim.x + threadIdx.x;
int n = blockIdx.y * blockDim.y + threadIdx.y;
for (int i = 0; i < k; ++i) {
float a = A[m + i * lda];
float b = B[n + i * ldb];
c += a * b;
}
C[m+n*ldc] = C[m+n*ldc] * beta + alpha * c;
} | .file "tmpxft_00185712_00000000-6_mysgemmNT.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z9mysgemmNTPKfiS0_iPfiiffPKfiS0_iPfiiff
.type _Z40__device_stub__Z9mysgemmNTPKfiS0_iPfiiffPKfiS0_iPfiiff, @function
_Z40__device_stub__Z9mysgemmNTPKfiS0_iPfiiffPKfiS0_iPfiiff:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 32(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm1, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 4(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9mysgemmNTPKfiS0_iPfiiff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z9mysgemmNTPKfiS0_iPfiiffPKfiS0_iPfiiff, .-_Z40__device_stub__Z9mysgemmNTPKfiS0_iPfiiffPKfiS0_iPfiiff
.globl _Z9mysgemmNTPKfiS0_iPfiiff
.type _Z9mysgemmNTPKfiS0_iPfiiff, @function
_Z9mysgemmNTPKfiS0_iPfiiff:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z40__device_stub__Z9mysgemmNTPKfiS0_iPfiiffPKfiS0_iPfiiff
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9mysgemmNTPKfiS0_iPfiiff, .-_Z9mysgemmNTPKfiS0_iPfiiff
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9mysgemmNTPKfiS0_iPfiiff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9mysgemmNTPKfiS0_iPfiiff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void mysgemmNT( const float *A, int lda, const float *B, int ldb, float* C, int ldc, int k, float alpha, float beta )
{
float c = 0.0f;
int m = blockIdx.x * blockDim.x + threadIdx.x;
int n = blockIdx.y * blockDim.y + threadIdx.y;
for (int i = 0; i < k; ++i) {
float a = A[m + i * lda];
float b = B[n + i * ldb];
c += a * b;
}
C[m+n*ldc] = C[m+n*ldc] * beta + alpha * c;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void mysgemmNT( const float *A, int lda, const float *B, int ldb, float* C, int ldc, int k, float alpha, float beta )
{
float c = 0.0f;
int m = blockIdx.x * blockDim.x + threadIdx.x;
int n = blockIdx.y * blockDim.y + threadIdx.y;
for (int i = 0; i < k; ++i) {
float a = A[m + i * lda];
float b = B[n + i * ldb];
c += a * b;
}
C[m+n*ldc] = C[m+n*ldc] * beta + alpha * c;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void mysgemmNT( const float *A, int lda, const float *B, int ldb, float* C, int ldc, int k, float alpha, float beta )
{
float c = 0.0f;
int m = blockIdx.x * blockDim.x + threadIdx.x;
int n = blockIdx.y * blockDim.y + threadIdx.y;
for (int i = 0; i < k; ++i) {
float a = A[m + i * lda];
float b = B[n + i * ldb];
c += a * b;
}
C[m+n*ldc] = C[m+n*ldc] * beta + alpha * c;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9mysgemmNTPKfiS0_iPfiiff
.globl _Z9mysgemmNTPKfiS0_iPfiiff
.p2align 8
.type _Z9mysgemmNTPKfiS0_iPfiiff,@function
_Z9mysgemmNTPKfiS0_iPfiiff:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b32 s6, s[0:1], 0x2c
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB0_3
s_clause 0x3
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s7, s[0:1], 0x8
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b32 s8, s[0:1], 0x18
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v2, v0
v_mov_b32_e32 v4, v1
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s6, s6, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s6, 0
v_lshlrev_b64 v[7:8], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[9:10], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v4, s8, v4
v_add_nc_u32_e32 v2, s7, v2
v_add_co_u32 v7, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
v_add_co_u32 v9, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
global_load_b32 v3, v[7:8], off
global_load_b32 v5, v[9:10], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v3, v5
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x28
s_load_b64 s[2:3], s[0:1], 0x20
s_load_b64 s[0:1], s[0:1], 0x30
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s1, v2
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v2, s0, v6
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9mysgemmNTPKfiS0_iPfiiff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9mysgemmNTPKfiS0_iPfiiff, .Lfunc_end0-_Z9mysgemmNTPKfiS0_iPfiiff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9mysgemmNTPKfiS0_iPfiiff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9mysgemmNTPKfiS0_iPfiiff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void mysgemmNT( const float *A, int lda, const float *B, int ldb, float* C, int ldc, int k, float alpha, float beta )
{
float c = 0.0f;
int m = blockIdx.x * blockDim.x + threadIdx.x;
int n = blockIdx.y * blockDim.y + threadIdx.y;
for (int i = 0; i < k; ++i) {
float a = A[m + i * lda];
float b = B[n + i * ldb];
c += a * b;
}
C[m+n*ldc] = C[m+n*ldc] * beta + alpha * c;
} | .text
.file "mysgemmNT.hip"
.globl _Z24__device_stub__mysgemmNTPKfiS0_iPfiiff # -- Begin function _Z24__device_stub__mysgemmNTPKfiS0_iPfiiff
.p2align 4, 0x90
.type _Z24__device_stub__mysgemmNTPKfiS0_iPfiiff,@function
_Z24__device_stub__mysgemmNTPKfiS0_iPfiiff: # @_Z24__device_stub__mysgemmNTPKfiS0_iPfiiff
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 80(%rsp)
movl %ecx, 16(%rsp)
movq %r8, 72(%rsp)
movl %r9d, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm1, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 4(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9mysgemmNTPKfiS0_iPfiiff, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z24__device_stub__mysgemmNTPKfiS0_iPfiiff, .Lfunc_end0-_Z24__device_stub__mysgemmNTPKfiS0_iPfiiff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9mysgemmNTPKfiS0_iPfiiff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9mysgemmNTPKfiS0_iPfiiff,@object # @_Z9mysgemmNTPKfiS0_iPfiiff
.section .rodata,"a",@progbits
.globl _Z9mysgemmNTPKfiS0_iPfiiff
.p2align 3, 0x0
_Z9mysgemmNTPKfiS0_iPfiiff:
.quad _Z24__device_stub__mysgemmNTPKfiS0_iPfiiff
.size _Z9mysgemmNTPKfiS0_iPfiiff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9mysgemmNTPKfiS0_iPfiiff"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__mysgemmNTPKfiS0_iPfiiff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9mysgemmNTPKfiS0_iPfiiff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9mysgemmNTPKfiS0_iPfiiff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R4, c[0x0][0x18c] ; /* 0x0000630000047a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R10, -RZ, RZ, 0, 0 ; /* 0x00000000ff0a7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0080*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*00a0*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fc600078e0205 */
/*00b0*/ @!P0 BRA 0xc80 ; /* 0x00000bc000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R4, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x000fe40007ffe0ff */
/*00d0*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fe40000000f00 */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*00f0*/ LOP3.LUT R2, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304027812 */
/* 0x000fe400078ec0ff */
/*0100*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0110*/ @!P0 BRA 0xb90 ; /* 0x00000a7000008947 */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R5, -R2, c[0x0][0x18c], RZ ; /* 0x0000630002057a10 */
/* 0x000fe20007ffe1ff */
/*0130*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fe200000001ff */
/*0140*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fe20000000f00 */
/*0150*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*0160*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fce0003f04270 */
/*0170*/ IMAD.WIDE R14, R3, R6, c[0x0][0x170] ; /* 0x00005c00030e7625 */
/* 0x000fc800078e0206 */
/*0180*/ IMAD.WIDE R16, R0, R6, c[0x0][0x160] ; /* 0x0000580000107625 */
/* 0x000fe400078e0206 */
/*0190*/ @!P0 BRA 0xa10 ; /* 0x0000087000008947 */
/* 0x000fea0003800000 */
/*01a0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01c0*/ @!P1 BRA 0x720 ; /* 0x0000055000009947 */
/* 0x000fea0003800000 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01e0*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x0000a8000c1e1900 */
/*01f0*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x0002a2000c1e1900 */
/*0200*/ IMAD.WIDE R22, R6, c[0x0][0x178], R14 ; /* 0x00005e0006167a25 */
/* 0x000fc800078e020e */
/*0210*/ IMAD.WIDE R26, R6.reuse, c[0x0][0x168], R16 ; /* 0x00005a00061a7a25 */
/* 0x040fe200078e0210 */
/*0220*/ LDG.E R11, [R22.64] ; /* 0x00000004160b7981 */
/* 0x000728000c1e1900 */
/*0230*/ LDG.E R24, [R26.64] ; /* 0x000000041a187981 */
/* 0x000b22000c1e1900 */
/*0240*/ IMAD.WIDE R22, R6, c[0x0][0x178], R22 ; /* 0x00005e0006167a25 */
/* 0x008fc800078e0216 */
/*0250*/ IMAD.WIDE R26, R6.reuse, c[0x0][0x168], R26 ; /* 0x00005a00061a7a25 */
/* 0x060fe200078e021a */
/*0260*/ LDG.E R19, [R22.64] ; /* 0x0000000416137981 */
/* 0x000766000c1e1900 */
/*0270*/ IMAD.WIDE R14, R6.reuse, c[0x0][0x178], R22 ; /* 0x00005e00060e7a25 */
/* 0x041fe200078e0216 */
/*0280*/ LDG.E R18, [R26.64] ; /* 0x000000041a127981 */
/* 0x000166000c1e1900 */
/*0290*/ IMAD.WIDE R12, R6.reuse, c[0x0][0x168], R26 ; /* 0x00005a00060c7a25 */
/* 0x040fe200078e021a */
/*02a0*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x002368000c1e1900 */
/*02b0*/ LDG.E R25, [R12.64] ; /* 0x000000040c197981 */
/* 0x000162000c1e1900 */
/*02c0*/ IMAD.WIDE R28, R6, c[0x0][0x168], R12 ; /* 0x00005a00061c7a25 */
/* 0x000fc800078e020c */
/*02d0*/ IMAD.WIDE R14, R6.reuse, c[0x0][0x178], R14 ; /* 0x00005e00060e7a25 */
/* 0x042fe200078e020e */
/*02e0*/ LDG.E R17, [R28.64] ; /* 0x000000041c117981 */
/* 0x000368000c1e1900 */
/*02f0*/ LDG.E R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x008762000c1e1900 */
/*0300*/ IMAD.WIDE R26, R6, c[0x0][0x178], R14 ; /* 0x00005e00061a7a25 */
/* 0x001fc800078e020e */
/*0310*/ IMAD.WIDE R28, R6.reuse, c[0x0][0x168], R28 ; /* 0x00005a00061c7a25 */
/* 0x042fe200078e021c */
/*0320*/ LDG.E R23, [R26.64] ; /* 0x000000041a177981 */
/* 0x00016a000c1e1900 */
/*0330*/ IMAD.WIDE R12, R6.reuse, c[0x0][0x168], R28 ; /* 0x00005a00060c7a25 */
/* 0x040fe400078e021c */
/*0340*/ LDG.E R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000564000c1e1900 */
/*0350*/ IMAD.WIDE R26, R6, c[0x0][0x178], R26 ; /* 0x00005e00061a7a25 */
/* 0x001fc400078e021a */
/*0360*/ LDG.E R7, [R12.64] ; /* 0x000000040c077981 */
/* 0x000168000c1e1900 */
/*0370*/ LDG.E R8, [R26.64] ; /* 0x000000041a087981 */
/* 0x000362000c1e1900 */
/*0380*/ IMAD.WIDE R14, R6, c[0x0][0x178], R26 ; /* 0x00005e00060e7a25 */
/* 0x008fc800078e021a */
/*0390*/ IMAD.WIDE R12, R6, c[0x0][0x168], R12 ; /* 0x00005a00060c7a25 */
/* 0x001fc800078e020c */
/*03a0*/ FFMA R29, R20, R9, R10 ; /* 0x00000009141d7223 */
/* 0x004fe4000000000a */
/*03b0*/ LDG.E R9, [R12.64] ; /* 0x000000040c097981 */
/* 0x0000a8000c1e1900 */
/*03c0*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x0006a2000c1e1900 */
/*03d0*/ IMAD.WIDE R20, R6, c[0x0][0x168], R12 ; /* 0x00005a0006147a25 */
/* 0x000fc800078e020c */
/*03e0*/ FFMA R29, R11, R24, R29 ; /* 0x000000180b1d7223 */
/* 0x010fe4000000001d */
/*03f0*/ LDG.E R24, [R20.64] ; /* 0x0000000414187981 */
/* 0x0008a2000c1e1900 */
/*0400*/ IMAD.WIDE R14, R6, c[0x0][0x178], R14 ; /* 0x00005e00060e7a25 */
/* 0x008fca00078e020e */
/*0410*/ LDG.E R11, [R14.64] ; /* 0x000000040e0b7981 */
/* 0x0006a2000c1e1900 */
/*0420*/ IMAD.WIDE R26, R6, c[0x0][0x168], R20 ; /* 0x00005a00061a7a25 */
/* 0x002fc800078e0214 */
/*0430*/ FFMA R29, R19, R18, R29 ; /* 0x00000012131d7223 */
/* 0x020fe4000000001d */
/*0440*/ IMAD.WIDE R18, R6, c[0x0][0x178], R14 ; /* 0x00005e0006127a25 */
/* 0x000fc800078e020e */
/*0450*/ FFMA R16, R16, R25, R29 ; /* 0x0000001910107223 */
/* 0x000fe4000000001d */
/*0460*/ LDG.E R25, [R18.64] ; /* 0x0000000412197981 */
/* 0x000362000c1e1900 */
/*0470*/ IMAD.WIDE R12, R6, c[0x0][0x168], R26 ; /* 0x00005a00060c7a25 */
/* 0x001fc600078e021a */
/*0480*/ LDG.E R26, [R26.64] ; /* 0x000000041a1a7981 */
/* 0x000162000c1e1900 */
/*0490*/ IMAD.WIDE R18, R6, c[0x0][0x178], R18 ; /* 0x00005e0006127a25 */
/* 0x002fc800078e0212 */
/*04a0*/ FFMA R22, R22, R17, R16 ; /* 0x0000001116167223 */
/* 0x000fe20000000010 */
/*04b0*/ LDG.E R27, [R18.64] ; /* 0x00000004121b7981 */
/* 0x001162000c1e1900 */
/*04c0*/ IMAD.WIDE R14, R6, c[0x0][0x168], R12 ; /* 0x00005a00060e7a25 */
/* 0x008fc600078e020c */
/*04d0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x0004e2000c1e1900 */
/*04e0*/ IMAD.WIDE R16, R6, c[0x0][0x178], R18 ; /* 0x00005e0006107a25 */
/* 0x000fc600078e0212 */
/*04f0*/ LDG.E R29, [R14.64] ; /* 0x000000040e1d7981 */
/* 0x0002e2000c1e1900 */
/*0500*/ FFMA R28, R23, R28, R22 ; /* 0x0000001c171c7223 */
/* 0x000fe40000000016 */
/*0510*/ IMAD.WIDE R20, R6, c[0x0][0x168], R14 ; /* 0x00005a0006147a25 */
/* 0x010fc800078e020e */
/*0520*/ IMAD.WIDE R22, R6, c[0x0][0x178], R16 ; /* 0x00005e0006167a25 */
/* 0x000fe400078e0210 */
/*0530*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008e4000c1e1900 */
/*0540*/ FFMA R8, R8, R7, R28 ; /* 0x0000000708087223 */
/* 0x000fe4000000001c */
/*0550*/ IMAD.WIDE R14, R6.reuse, c[0x0][0x168], R20 ; /* 0x00005a00060e7a25 */
/* 0x042fe200078e0214 */
/*0560*/ LDG.E R7, [R22.64] ; /* 0x0000000416077981 */
/* 0x0002e6000c1e1900 */
/*0570*/ IMAD.WIDE R18, R6, c[0x0][0x178], R22 ; /* 0x00005e0006127a25 */
/* 0x001fe200078e0216 */
/*0580*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ee6000c1e1900 */
/*0590*/ FFMA R13, R10, R9, R8 ; /* 0x000000090a0d7223 */
/* 0x004fc40000000008 */
/*05a0*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x0000a2000c1e1900 */
/*05b0*/ IMAD.WIDE R8, R6, c[0x0][0x168], R14 ; /* 0x00005a0006087a25 */
/* 0x000fc600078e020e */
/*05c0*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000ea8000c1e1900 */
/*05d0*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x0108a2000c1e1900 */
/*05e0*/ IMAD.WIDE R18, R6, c[0x0][0x178], R18 ; /* 0x00005e0006127a25 */
/* 0x001fca00078e0212 */
/*05f0*/ LDG.E R28, [R18.64] ; /* 0x00000004121c7981 */
/* 0x000ea2000c1e1900 */
/*0600*/ IMAD.WIDE R22, R6, c[0x0][0x178], R18 ; /* 0x00005e0006167a25 */
/* 0x002fc800078e0212 */
/*0610*/ IMAD.WIDE R8, R6, c[0x0][0x168], R8 ; /* 0x00005a0006087a25 */
/* 0x010fc800078e0208 */
/*0620*/ FFMA R13, R11, R24, R13 ; /* 0x000000180b0d7223 */
/* 0x000fe4000000000d */
/*0630*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000f28000c1e1900 */
/*0640*/ LDG.E R11, [R22.64] ; /* 0x00000004160b7981 */
/* 0x000f22000c1e1900 */
/*0650*/ FFMA R13, R25, R26, R13 ; /* 0x0000001a190d7223 */
/* 0x020fe2000000000d */
/*0660*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc80007ffe0ff */
/*0670*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe20003f24270 */
/*0680*/ FFMA R12, R27, R12, R13 ; /* 0x0000000c1b0c7223 */
/* 0x008fc8000000000d */
/*0690*/ FFMA R12, R16, R29, R12 ; /* 0x0000001d100c7223 */
/* 0x000fc8000000000c */
/*06a0*/ FFMA R7, R7, R20, R12 ; /* 0x0000001407077223 */
/* 0x000fe2000000000c */
/*06b0*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*06c0*/ FFMA R7, R10, R15, R7 ; /* 0x0000000f0a077223 */
/* 0x004fe40000000007 */
/*06d0*/ IMAD.WIDE R14, R6, c[0x0][0x178], R22 ; /* 0x00005e00060e7a25 */
/* 0x000fc800078e0216 */
/*06e0*/ FFMA R7, R28, R17, R7 ; /* 0x000000111c077223 */
/* 0x000fe40000000007 */
/*06f0*/ IMAD.WIDE R16, R6, c[0x0][0x168], R8 ; /* 0x00005a0006107a25 */
/* 0x000fc800078e0208 */
/*0700*/ FFMA R10, R11, R24, R7 ; /* 0x000000180b0a7223 */
/* 0x010fe20000000007 */
/*0710*/ @P1 BRA 0x1e0 ; /* 0xfffffac000001947 */
/* 0x000fea000383ffff */
/*0720*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*0730*/ @!P1 BRA 0x9f0 ; /* 0x000002b000009947 */
/* 0x000fea0003800000 */
/*0740*/ LDG.E R27, [R14.64] ; /* 0x000000040e1b7981 */
/* 0x0000a8000c1e1900 */
/*0750*/ LDG.E R28, [R16.64] ; /* 0x00000004101c7981 */
/* 0x0002a2000c1e1900 */
/*0760*/ IMAD.WIDE R8, R6, c[0x0][0x168], R16 ; /* 0x00005a0006087a25 */
/* 0x000fc800078e0210 */
/*0770*/ IMAD.WIDE R12, R6, c[0x0][0x178], R14 ; /* 0x00005e00060c7a25 */
/* 0x000fc800078e020e */
/*0780*/ IMAD.WIDE R14, R6.reuse, c[0x0][0x168], R8 ; /* 0x00005a00060e7a25 */
/* 0x041fe200078e0208 */
/*0790*/ LDG.E R7, [R12.64] ; /* 0x000000040c077981 */
/* 0x0000e6000c1e1900 */
/*07a0*/ IMAD.WIDE R18, R6.reuse, c[0x0][0x178], R12 ; /* 0x00005e0006127a25 */
/* 0x040fe200078e020c */
/*07b0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x0008e6000c1e1900 */
/*07c0*/ IMAD.WIDE R16, R6.reuse, c[0x0][0x168], R14 ; /* 0x00005a0006107a25 */
/* 0x042fe200078e020e */
/*07d0*/ LDG.E R25, [R18.64] ; /* 0x0000000412197981 */
/* 0x000366000c1e1900 */
/*07e0*/ IMAD.WIDE R20, R6.reuse, c[0x0][0x178], R18 ; /* 0x00005e0006147a25 */
/* 0x040fe200078e0212 */
/*07f0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000366000c1e1900 */
/*0800*/ IMAD.WIDE R12, R6.reuse, c[0x0][0x168], R16 ; /* 0x00005a00060c7a25 */
/* 0x041fe200078e0210 */
/*0810*/ LDG.E R24, [R16.64] ; /* 0x0000000410187981 */
/* 0x000166000c1e1900 */
/*0820*/ IMAD.WIDE R22, R6, c[0x0][0x178], R20 ; /* 0x00005e0006167a25 */
/* 0x000fc400078e0214 */
/*0830*/ LDG.E R21, [R20.64] ; /* 0x0000000414157981 */
/* 0x000964000c1e1900 */
/*0840*/ IMAD.WIDE R14, R6.reuse, c[0x0][0x168], R12 ; /* 0x00005a00060e7a25 */
/* 0x042fe400078e020c */
/*0850*/ LDG.E R11, [R22.64] ; /* 0x00000004160b7981 */
/* 0x000364000c1e1900 */
/*0860*/ IMAD.WIDE R16, R6.reuse, c[0x0][0x178], R22 ; /* 0x00005e0006107a25 */
/* 0x041fe400078e0216 */
/*0870*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x010128000c1e1900 */
/*0880*/ IMAD.WIDE R18, R6.reuse, c[0x0][0x178], R16 ; /* 0x00005e0006127a25 */
/* 0x040fe200078e0210 */
/*0890*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000326000c1e1900 */
/*08a0*/ IMAD.WIDE R12, R6, c[0x0][0x168], R14 ; /* 0x00005a00060c7a25 */
/* 0x001fc400078e020e */
/*08b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f28000c1e1900 */
/*08c0*/ LDG.E R16, [R18.64] ; /* 0x0000000412107981 */
/* 0x002122000c1e1900 */
/*08d0*/ IMAD.WIDE R22, R6, c[0x0][0x168], R12 ; /* 0x00005a0006167a25 */
/* 0x000fc600078e020c */
/*08e0*/ LDG.E R29, [R12.64] ; /* 0x000000040c1d7981 */
/* 0x000f22000c1e1900 */
/*08f0*/ IMAD.WIDE R18, R6, c[0x0][0x178], R18 ; /* 0x00005e0006127a25 */
/* 0x001fc800078e0212 */
/*0900*/ FFMA R28, R27, R28, R10 ; /* 0x0000001c1b1c7223 */
/* 0x004fe4000000000a */
/*0910*/ LDG.E R27, [R22.64] ; /* 0x00000004161b7981 */
/* 0x000ea8000c1e1900 */
/*0920*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x000ea2000c1e1900 */
/*0930*/ FFMA R7, R7, R8, R28 ; /* 0x0000000807077223 */
/* 0x008fc8000000001c */
/*0940*/ FFMA R7, R25, R26, R7 ; /* 0x0000001a19077223 */
/* 0x020fc80000000007 */
/*0950*/ FFMA R7, R21, R24, R7 ; /* 0x0000001815077223 */
/* 0x000fc80000000007 */
/*0960*/ FFMA R7, R11, R20, R7 ; /* 0x000000140b077223 */
/* 0x010fe20000000007 */
/*0970*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0980*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe20007ffe0ff */
/*0990*/ FFMA R7, R9, R14, R7 ; /* 0x0000000e09077223 */
/* 0x000fe20000000007 */
/*09a0*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*09b0*/ IMAD.WIDE R14, R6, c[0x0][0x178], R18 ; /* 0x00005e00060e7a25 */
/* 0x000fc800078e0212 */
/*09c0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fe40000000007 */
/*09d0*/ IMAD.WIDE R16, R6, c[0x0][0x168], R22 ; /* 0x00005a0006107a25 */
/* 0x000fc800078e0216 */
/*09e0*/ FFMA R10, R10, R27, R7 ; /* 0x0000001b0a0a7223 */
/* 0x004fe40000000007 */
/*09f0*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0a00*/ @!P0 BRA 0xb90 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0a10*/ IMAD.WIDE R8, R6.reuse, c[0x0][0x168], R16 ; /* 0x00005a0006087a25 */
/* 0x040fe400078e0210 */
/*0a20*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea4000c1e1900 */
/*0a30*/ IMAD.WIDE R12, R6.reuse, c[0x0][0x178], R14 ; /* 0x00005e00060c7a25 */
/* 0x040fe400078e020e */
/*0a40*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x0000a4000c1e1900 */
/*0a50*/ IMAD.WIDE R22, R6.reuse, c[0x0][0x168], R8 ; /* 0x00005a0006167a25 */
/* 0x040fe400078e0208 */
/*0a60*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee4000c1e1900 */
/*0a70*/ IMAD.WIDE R18, R6, c[0x0][0x178], R12 ; /* 0x00005e0006127a25 */
/* 0x000fc400078e020c */
/*0a80*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee4000c1e1900 */
/*0a90*/ IMAD.WIDE R20, R6.reuse, c[0x0][0x168], R22 ; /* 0x00005a0006147a25 */
/* 0x040fe400078e0216 */
/*0aa0*/ LDG.E R7, [R22.64] ; /* 0x0000000416077981 */
/* 0x000f24000c1e1900 */
/*0ab0*/ IMAD.WIDE R24, R6, c[0x0][0x178], R18 ; /* 0x00005e0006187a25 */
/* 0x000fe400078e0212 */
/*0ac0*/ LDG.E R26, [R18.64] ; /* 0x00000004121a7981 */
/* 0x000f28000c1e1900 */
/*0ad0*/ LDG.E R11, [R20.64] ; /* 0x00000004140b7981 */
/* 0x000f68000c1e1900 */
/*0ae0*/ LDG.E R14, [R24.64] ; /* 0x00000004180e7981 */
/* 0x001f62000c1e1900 */
/*0af0*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f05270 */
/*0b10*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fe20007ffe0ff */
/*0b20*/ FFMA R15, R15, R16, R10 ; /* 0x000000100f0f7223 */
/* 0x004fc8000000000a */
/*0b30*/ FFMA R15, R12, R8, R15 ; /* 0x000000080c0f7223 */
/* 0x008fe4000000000f */
/*0b40*/ IMAD.WIDE R16, R6, c[0x0][0x168], R20 ; /* 0x00005a0006107a25 */
/* 0x000fc800078e0214 */
/*0b50*/ FFMA R7, R26, R7, R15 ; /* 0x000000071a077223 */
/* 0x010fc8000000000f */
/*0b60*/ FFMA R10, R14, R11, R7 ; /* 0x0000000b0e0a7223 */
/* 0x020fe40000000007 */
/*0b70*/ IMAD.WIDE R14, R6, c[0x0][0x178], R24 ; /* 0x00005e00060e7a25 */
/* 0x000fe200078e0218 */
/*0b80*/ @P0 BRA 0xa10 ; /* 0xfffffe8000000947 */
/* 0x000fea000383ffff */
/*0b90*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*0ba0*/ @!P0 BRA 0xc80 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0bb0*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*0bc0*/ IMAD R5, R4.reuse, c[0x0][0x178], R3 ; /* 0x00005e0004057a24 */
/* 0x040fe400078e0203 */
/*0bd0*/ IMAD R6, R4, c[0x0][0x168], R0 ; /* 0x00005a0004067a24 */
/* 0x000fce00078e0200 */
/*0be0*/ IMAD.WIDE R4, R5, R11, c[0x0][0x170] ; /* 0x00005c0005047625 */
/* 0x000fc800078e020b */
/*0bf0*/ IMAD.WIDE R6, R6, R11, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e020b */
/*0c00*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x0000a8000c1e1900 */
/*0c10*/ LDG.E R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x0002a2000c1e1900 */
/*0c20*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fc80007ffe0ff */
/*0c30*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0c40*/ IMAD.WIDE R4, R11, c[0x0][0x178], R4 ; /* 0x00005e000b047a25 */
/* 0x001fc800078e0204 */
/*0c50*/ IMAD.WIDE R6, R11, c[0x0][0x168], R6 ; /* 0x00005a000b067a25 */
/* 0x002fc800078e0206 */
/*0c60*/ FFMA R10, R9, R8, R10 ; /* 0x00000008090a7223 */
/* 0x004fc8000000000a */
/*0c70*/ @P0 BRA 0xc00 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*0c80*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0c90*/ IMAD R3, R3, c[0x0][0x188], R0 ; /* 0x0000620003037a24 */
/* 0x000fc800078e0200 */
/*0ca0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x180] ; /* 0x0000600003027625 */
/* 0x000fca00078e0202 */
/*0cb0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0cc0*/ FMUL R5, R0, c[0x0][0x194] ; /* 0x0000650000057a20 */
/* 0x004fc80000400000 */
/*0cd0*/ FFMA R5, R10, c[0x0][0x190], R5 ; /* 0x000064000a057a23 */
/* 0x000fca0000000005 */
/*0ce0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0cf0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d00*/ BRA 0xd00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9mysgemmNTPKfiS0_iPfiiff
.globl _Z9mysgemmNTPKfiS0_iPfiiff
.p2align 8
.type _Z9mysgemmNTPKfiS0_iPfiiff,@function
_Z9mysgemmNTPKfiS0_iPfiiff:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b32 s6, s[0:1], 0x2c
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB0_3
s_clause 0x3
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s7, s[0:1], 0x8
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b32 s8, s[0:1], 0x18
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v2, v0
v_mov_b32_e32 v4, v1
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s6, s6, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s6, 0
v_lshlrev_b64 v[7:8], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[9:10], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v4, s8, v4
v_add_nc_u32_e32 v2, s7, v2
v_add_co_u32 v7, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
v_add_co_u32 v9, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
global_load_b32 v3, v[7:8], off
global_load_b32 v5, v[9:10], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v3, v5
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x28
s_load_b64 s[2:3], s[0:1], 0x20
s_load_b64 s[0:1], s[0:1], 0x30
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s1, v2
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v2, s0, v6
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9mysgemmNTPKfiS0_iPfiiff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9mysgemmNTPKfiS0_iPfiiff, .Lfunc_end0-_Z9mysgemmNTPKfiS0_iPfiiff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9mysgemmNTPKfiS0_iPfiiff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9mysgemmNTPKfiS0_iPfiiff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00185712_00000000-6_mysgemmNT.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z9mysgemmNTPKfiS0_iPfiiffPKfiS0_iPfiiff
.type _Z40__device_stub__Z9mysgemmNTPKfiS0_iPfiiffPKfiS0_iPfiiff, @function
_Z40__device_stub__Z9mysgemmNTPKfiS0_iPfiiffPKfiS0_iPfiiff:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 32(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm1, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 4(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9mysgemmNTPKfiS0_iPfiiff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z9mysgemmNTPKfiS0_iPfiiffPKfiS0_iPfiiff, .-_Z40__device_stub__Z9mysgemmNTPKfiS0_iPfiiffPKfiS0_iPfiiff
.globl _Z9mysgemmNTPKfiS0_iPfiiff
.type _Z9mysgemmNTPKfiS0_iPfiiff, @function
_Z9mysgemmNTPKfiS0_iPfiiff:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z40__device_stub__Z9mysgemmNTPKfiS0_iPfiiffPKfiS0_iPfiiff
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9mysgemmNTPKfiS0_iPfiiff, .-_Z9mysgemmNTPKfiS0_iPfiiff
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9mysgemmNTPKfiS0_iPfiiff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9mysgemmNTPKfiS0_iPfiiff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mysgemmNT.hip"
.globl _Z24__device_stub__mysgemmNTPKfiS0_iPfiiff # -- Begin function _Z24__device_stub__mysgemmNTPKfiS0_iPfiiff
.p2align 4, 0x90
.type _Z24__device_stub__mysgemmNTPKfiS0_iPfiiff,@function
_Z24__device_stub__mysgemmNTPKfiS0_iPfiiff: # @_Z24__device_stub__mysgemmNTPKfiS0_iPfiiff
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 80(%rsp)
movl %ecx, 16(%rsp)
movq %r8, 72(%rsp)
movl %r9d, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm1, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 4(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9mysgemmNTPKfiS0_iPfiiff, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z24__device_stub__mysgemmNTPKfiS0_iPfiiff, .Lfunc_end0-_Z24__device_stub__mysgemmNTPKfiS0_iPfiiff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9mysgemmNTPKfiS0_iPfiiff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9mysgemmNTPKfiS0_iPfiiff,@object # @_Z9mysgemmNTPKfiS0_iPfiiff
.section .rodata,"a",@progbits
.globl _Z9mysgemmNTPKfiS0_iPfiiff
.p2align 3, 0x0
_Z9mysgemmNTPKfiS0_iPfiiff:
.quad _Z24__device_stub__mysgemmNTPKfiS0_iPfiiff
.size _Z9mysgemmNTPKfiS0_iPfiiff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9mysgemmNTPKfiS0_iPfiiff"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__mysgemmNTPKfiS0_iPfiiff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9mysgemmNTPKfiS0_iPfiiff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
// by lectures and "CUDA by Example" book
#define ind(i, j, cols) (i * cols + j)
struct dim2 {
int rows;
int cols;
};
// device code: matrices mult calculation
__global__ void mult_matrices_kernel(int* m1, int* m2, int* m3, dim2 m3_dims, int inner_dim) {
int rows = m3_dims.rows;
int cols = m3_dims.cols;
printf("blockId, threadId, dims: [%d, %d], [%d, %d], [%d, %d]\n",
blockIdx.y, blockIdx.x, threadIdx.y, threadIdx.x, rows, cols);
// row and col that correspond to current thread
// process all elements that correspond to current thread
for (int i = blockIdx.y * blockDim.y + threadIdx.y;
i < rows; i += blockDim.y * gridDim.y)
for (int j = blockIdx.x * blockDim.x + threadIdx.x;
j < cols; j += blockDim.x * gridDim.x) {
printf("blockId, threadId, pos: [%d, %d], [%d, %d], [%d, %d]\n",
blockIdx.y, blockIdx.x, threadIdx.y, threadIdx.x, i, j);
int index_3 = ind(i, j, cols);
m3[index_3] = 0;
// iterating over row and down column
for (int k = 0; k < inner_dim; k++) {
int index_1 = ind(i, k, inner_dim);
int index_2 = ind(k, j, cols);
m3[index_3] += m1[index_1] * m2[index_2];
}
}
}
int* cuda_copy_mat(int* host_m, dim2 m_dims) {
int* dev_m;
// size of memory to allocate on device for matrix
long mem_size = m_dims.rows * m_dims.cols * sizeof(int);
// device memory allocation
cudaMalloc((void**) &dev_m, mem_size);
// copying data from host to device
cudaMemcpy(dev_m, host_m, mem_size, cudaMemcpyHostToDevice);
// returning pointer
return dev_m;
}
// host code: preparation
void mult_matrices_gpu(int* host_m1, dim2 m1_dims,
int* host_m2, dim2 m2_dims,
int* host_m3, dim2 m3_dims) {
// Step 1: moving data on device
int* dev_m1 = cuda_copy_mat(host_m1, m1_dims);
int* dev_m2 = cuda_copy_mat(host_m2, m3_dims);
int* dev_m3 = cuda_copy_mat(host_m3, m3_dims);
// Step 2
// grid (of blocks) dimensions
dim3 grid_dim(3, 2, 1);
// block (of threads) dimensions
dim3 block_dim(2, 2, 1);
// running kernel multiplication code
mult_matrices_kernel<<<grid_dim, block_dim>>>(dev_m1, dev_m2, dev_m3, m3_dims, m1_dims.cols);
// Step 3
// copying result from device to host matrix
cudaMemcpy(host_m3, dev_m3, m3_dims.rows * m3_dims.cols * sizeof(int), cudaMemcpyDeviceToHost);
// freeing device memory
cudaFree(dev_m1);
cudaFree(dev_m2);
cudaFree(dev_m3);
}
void mult_matrices_cpu(int* m1, dim2 m1_dims,
int* m2, dim2 m2_dims,
int* m3, dim2 m3_dims) {
for (int i = 0; i < m1_dims.rows; i++)
for (int j = 0; j < m2_dims.cols; j++) {
int index_3 = ind(i, j, m3_dims.cols);
m3[index_3] = 0;
for (int k = 0; k < m1_dims.cols; k++) {
int index_1 = ind(i, k, m1_dims.cols);
int index_2 = ind(k, j, m2_dims.cols);
m3[index_3] += m1[index_1] * m2[index_2];
}
}
}
// create matrix (array representation)
int* create_mat(dim2 dims, int k) {
int rows = dims.rows;
int cols = dims.cols;
int* mat = (int*)malloc(rows * cols * sizeof(int));
for (int i = 0; i < rows; i++)
for (int j = 0; j < cols; j++)
mat[ind(i, j, cols)] = k * (ind(i, j, cols) + 1);
return mat;
}
// print matrix
void print_mat(const char* header, int* mat, dim2 dims) {
int rows = dims.rows;
int cols = dims.cols;
printf("%s (%d, %d):\n", header, rows, cols);
for (int i = 0; i < rows; i++)
for (int j = 0; j < cols; j++) {
printf("\t%d ", mat[ind(i, j, cols)]);
if (j == cols - 1)
printf("\n");
}
}
int main() {
// first matrix
struct dim2 m1_dims = {6, 4};
int* host_m1 = create_mat(m1_dims, 1);
print_mat("First matrix", host_m1, m1_dims);
// second matrix
struct dim2 m2_dims = {4, 8};
int* host_m2 = create_mat(m2_dims, 2);
print_mat("Second matrix", host_m2, m2_dims);
// dimensionality validation
if (m1_dims.cols != m2_dims.rows) {
printf("Error: Inner matrix dimensions does not match:\n"
"(%d, %d) and (%d, %d)",
m1_dims.rows, m1_dims.cols, m2_dims.rows, m2_dims.cols);
return 0;
}
// result matrix
struct dim2 m3_dims = {m1_dims.rows, m2_dims.cols};
int* host_m3 = create_mat(m3_dims, 0);
print_mat("Third matrix", host_m3, m3_dims);
// multiplication
mult_matrices_gpu(host_m1, m1_dims,
host_m2, m2_dims,
host_m3, m3_dims);
// showing result
print_mat("Result matrix", host_m3, m3_dims);
// multiplication
mult_matrices_cpu(host_m1, m1_dims,
host_m2, m2_dims,
host_m3, m3_dims);
// showing result
print_mat("Result matrix", host_m3, m3_dims);
return 0;
} | code for sm_80
Function : _Z20mult_matrices_kernelPiS_S_4dim2i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R23, SR_CTAID.X ; /* 0x0000000000177919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x18, RZ ; /* 0xffffffe801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff087624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R22, SR_CTAID.Y ; /* 0x0000000000167919 */
/* 0x000e220000002600 */
/*0060*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff097624 */
/* 0x000fe200078e00ff */
/*0070*/ IADD3 R26, P0, R1, c[0x0][0x20], RZ ; /* 0x00000800011a7a10 */
/* 0x000fe20007f1e0ff */
/*0080*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a20000000a00 */
/*0090*/ S2R R17, SR_TID.X ; /* 0x0000000000117919 */
/* 0x000ee20000002100 */
/*00a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*00b0*/ IADD3.X R27, RZ, c[0x0][0x24], RZ, P0, !PT ; /* 0x00000900ff1b7a10 */
/* 0x000fe200007fe4ff */
/*00c0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*00d0*/ S2R R16, SR_TID.Y ; /* 0x0000000000107919 */
/* 0x000ee20000002200 */
/*00e0*/ MOV R6, R26 ; /* 0x0000001a00067202 */
/* 0x000fc40000000f00 */
/*00f0*/ IMAD.MOV.U32 R7, RZ, RZ, R27 ; /* 0x000000ffff077224 */
/* 0x000fe200078e001b */
/*0100*/ STL.64 [R1+0x10], R8 ; /* 0x0000100801007387 */
/* 0x0003e80000100a00 */
/*0110*/ STL.64 [R1], R22 ; /* 0x0000001601007387 */
/* 0x0013e80000100a00 */
/*0120*/ STL.64 [R1+0x8], R16 ; /* 0x0000081001007387 */
/* 0x0083e40000100a00 */
/*0130*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x006fe20000000000 */
/*0140*/ MOV R11, 0x1b0 ; /* 0x000001b0000b7802 */
/* 0x000fc40000000f00 */
/*0150*/ MOV R20, 0x130 ; /* 0x0000013000147802 */
/* 0x000fe40000000f00 */
/*0160*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0170*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0180*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0190*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*01a0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*01b0*/ IMAD R24, R22, c[0x0][0x4], R16 ; /* 0x0000010016187a24 */
/* 0x000fca00078e0210 */
/*01c0*/ ISETP.GE.AND P0, PT, R24, c[0x0][0x178], PT ; /* 0x00005e0018007a0c */
/* 0x000fda0003f06270 */
/*01d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fe20003f01270 */
/*01f0*/ IMAD.MOV.U32 R30, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff1e7624 */
/* 0x000fe400078e00ff */
/*0200*/ IMAD R28, R23, c[0x0][0x0], R17 ; /* 0x00000000171c7a24 */
/* 0x000fe400078e0211 */
/*0210*/ IMAD R30, R30, c[0x0][0xc], RZ ; /* 0x000003001e1e7a24 */
/* 0x000fd000078e02ff */
/*0220*/ @P0 BRA 0x460 ; /* 0x0000023000000947 */
/* 0x000fea0003800000 */
/*0230*/ ISETP.GE.AND P0, PT, R28, c[0x0][0x17c], PT ; /* 0x00005f001c007a0c */
/* 0x000fe20003f06270 */
/*0240*/ BSSY B6, 0x410 ; /* 0x000001c000067945 */
/* 0x000fd80003800000 */
/*0250*/ @P0 BRA 0x400 ; /* 0x000001a000000947 */
/* 0x000fea0003800000 */
/*0260*/ MOV R25, R28 ; /* 0x0000001c00197202 */
/* 0x000fe40000000f00 */
/*0270*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x001fe20000000f00 */
/*0280*/ STL.64 [R1], R22 ; /* 0x0000001601007387 */
/* 0x0001e20000100a00 */
/*0290*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe200078e00ff */
/*02a0*/ MOV R6, R26 ; /* 0x0000001a00067202 */
/* 0x000fe20000000f00 */
/*02b0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe200078e00ff */
/*02c0*/ STL.64 [R1+0x8], R16 ; /* 0x0000081001007387 */
/* 0x0001e20000100a00 */
/*02d0*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e620000000a00 */
/*02e0*/ IMAD.MOV.U32 R7, RZ, RZ, R27 ; /* 0x000000ffff077224 */
/* 0x000fe400078e001b */
/*02f0*/ STL.64 [R1+0x10], R24 ; /* 0x0000101801007387 */
/* 0x0001ea0000100a00 */
/*0300*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe20000000000 */
/*0310*/ MOV R11, 0x380 ; /* 0x00000380000b7802 */
/* 0x000fc40000000f00 */
/*0320*/ MOV R20, 0x300 ; /* 0x0000030000147802 */
/* 0x000fe40000000f00 */
/*0330*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0340*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0350*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0360*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0370*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x003fea0003c00000 */
/*0380*/ IMAD R2, R24, c[0x0][0x17c], R25 ; /* 0x00005f0018027a24 */
/* 0x000fe200078e0219 */
/*0390*/ IADD3 R25, R30, R25, RZ ; /* 0x000000191e197210 */
/* 0x000fe20007ffe0ff */
/*03a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*03b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*03c0*/ ISETP.GE.AND P0, PT, R25, c[0x0][0x17c], PT ; /* 0x00005f0019007a0c */
/* 0x000fe20003f06270 */
/*03d0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*03e0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001ee000c101904 */
/*03f0*/ @!P0 BRA 0x270 ; /* 0xfffffe7000008947 */
/* 0x000fea000383ffff */
/*0400*/ BSYNC B6 ; /* 0x0000000000067941 */
/* 0x000fea0003800000 */
/*0410*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x4] ; /* 0x00000100ff037624 */
/* 0x001fc800078e00ff */
/*0420*/ IMAD R24, R3, c[0x0][0x10], R24 ; /* 0x0000040003187a24 */
/* 0x000fca00078e0218 */
/*0430*/ ISETP.GE.AND P0, PT, R24, c[0x0][0x178], PT ; /* 0x00005e0018007a0c */
/* 0x000fda0003f06270 */
/*0440*/ @!P0 BRA 0x230 ; /* 0xfffffde000008947 */
/* 0x000fea000383ffff */
/*0450*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0460*/ IMAD.MOV.U32 R29, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff1d7624 */
/* 0x000fca00078e00ff */
/*0470*/ LOP3.LUT R34, R29.reuse, 0x3, RZ, 0xc0, !PT ; /* 0x000000031d227812 */
/* 0x040fe400078ec0ff */
/*0480*/ IADD3 R29, R29, -0x1, RZ ; /* 0xffffffff1d1d7810 */
/* 0x000fe40007ffe0ff */
/*0490*/ IADD3 R31, -R34, c[0x0][0x180], RZ ; /* 0x00006000221f7a10 */
/* 0x000fe40007ffe1ff */
/*04a0*/ ISETP.GE.AND P0, PT, R28, c[0x0][0x17c], PT ; /* 0x00005f001c007a0c */
/* 0x000fe20003f06270 */
/*04b0*/ BSSY B6, 0xb30 ; /* 0x0000067000067945 */
/* 0x000fd80003800000 */
/*04c0*/ @P0 BRA 0xb20 ; /* 0x0000065000000947 */
/* 0x000fea0003800000 */
/*04d0*/ HFMA2.MMA R19, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff137435 */
/* 0x000fe200000001ff */
/*04e0*/ IMAD R32, R24, c[0x0][0x180], RZ ; /* 0x0000600018207a24 */
/* 0x000fe400078e02ff */
/*04f0*/ IMAD.MOV.U32 R33, RZ, RZ, RZ ; /* 0x000000ffff217224 */
/* 0x000fe400078e00ff */
/*0500*/ IMAD.MOV.U32 R25, RZ, RZ, R28 ; /* 0x000000ffff197224 */
/* 0x000fca00078e001c */
/*0510*/ IMAD.WIDE R18, R32, R19, c[0x0][0x160] ; /* 0x0000580020127625 */
/* 0x000fc800078e0213 */
/*0520*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x007fe20000000f00 */
/*0530*/ STL.64 [R1], R22 ; /* 0x0000001601007387 */
/* 0x0001e20000100a00 */
/*0540*/ MOV R4, c[0x4][0x10] ; /* 0x0100040000047a02 */
/* 0x000fe20000000f00 */
/*0550*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe200078e00ff */
/*0560*/ MOV R7, R27 ; /* 0x0000001b00077202 */
/* 0x000fe20000000f00 */
/*0570*/ STL.64 [R1+0x10], R24 ; /* 0x0000101801007387 */
/* 0x0001e20000100a00 */
/*0580*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e620000000a00 */
/*0590*/ IMAD.MOV.U32 R6, RZ, RZ, R26 ; /* 0x000000ffff067224 */
/* 0x000fe400078e001a */
/*05a0*/ STL.64 [R1+0x8], R16 ; /* 0x0000081001007387 */
/* 0x0001ea0000100a00 */
/*05b0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe20000000000 */
/*05c0*/ MOV R11, 0x630 ; /* 0x00000630000b7802 */
/* 0x000fc40000000f00 */
/*05d0*/ MOV R20, 0x5b0 ; /* 0x000005b000147802 */
/* 0x000fe40000000f00 */
/*05e0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*05f0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0600*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0610*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0620*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x003fea0003c00000 */
/*0630*/ ISETP.GE.U32.AND P1, PT, R29, 0x3, PT ; /* 0x000000031d00780c */
/* 0x000fe20003f26070 */
/*0640*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fe200078e00ff */
/*0650*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0660*/ IMAD R2, R24, c[0x0][0x17c], R25 ; /* 0x00005f0018027a24 */
/* 0x000fe200078e0219 */
/*0670*/ HFMA2.MMA R14, -RZ, RZ, 0, 0 ; /* 0x00000000ff0e7435 */
/* 0x000fe200000001ff */
/*0680*/ ISETP.NE.AND P0, PT, R34, RZ, PT ; /* 0x000000ff2200720c */
/* 0x000fe20003f05270 */
/*0690*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe400078e00ff */
/*06a0*/ IMAD.WIDE R2, R2, R15, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e020f */
/*06b0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e2000c101904 */
/*06c0*/ @!P1 BRA 0x920 ; /* 0x0000025000009947 */
/* 0x000fea0003800000 */
/*06d0*/ IMAD R6, R30, R33, R28 ; /* 0x000000211e067224 */
/* 0x000fe200078e021c */
/*06e0*/ BSSY B0, 0x920 ; /* 0x0000023000007945 */
/* 0x000fe20003800000 */
/*06f0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0700*/ MOV R5, R19 ; /* 0x0000001300057202 */
/* 0x000fe20000000f00 */
/*0710*/ IMAD.MOV.U32 R8, RZ, RZ, R18 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0012 */
/*0720*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e00ff */
/*0730*/ IMAD.MOV.U32 R0, RZ, RZ, R31 ; /* 0x000000ffff007224 */
/* 0x000fe400078e001f */
/*0740*/ IMAD.WIDE R6, R6, R15, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e020f */
/*0750*/ MOV R4, R8 ; /* 0x0000000800047202 */
/* 0x000fe20000000f00 */
/*0760*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc40000000a00 */
/*0770*/ LDG.E R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ea8000c1e1900 */
/*0780*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea4000c1e1900 */
/*0790*/ IMAD R21, R8, R10, R9 ; /* 0x0000000a08157224 */
/* 0x006fe400078e0209 */
/*07a0*/ IMAD.WIDE R8, R15, c[0x0][0x17c], R6 ; /* 0x00005f000f087a25 */
/* 0x000fc600078e0206 */
/*07b0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*07c0*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x000ea8000c1e1900 */
/*07d0*/ LDG.E R11, [R4.64+0x4] ; /* 0x00000404040b7981 */
/* 0x000ea4000c1e1900 */
/*07e0*/ IMAD R35, R10, R11, R21 ; /* 0x0000000b0a237224 */
/* 0x004fc400078e0215 */
/*07f0*/ IMAD.WIDE R10, R15, c[0x0][0x17c], R8 ; /* 0x00005f000f0a7a25 */
/* 0x000fc600078e0208 */
/*0800*/ STG.E [R2.64], R35 ; /* 0x0000002302007986 */
/* 0x0003e8000c101904 */
/*0810*/ LDG.E R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000ea8000c1e1900 */
/*0820*/ LDG.E R6, [R4.64+0x8] ; /* 0x0000080404067981 */
/* 0x000ea2000c1e1900 */
/*0830*/ IADD3 R0, R0, -0x4, RZ ; /* 0xfffffffc00007810 */
/* 0x000fe20007ffe0ff */
/*0840*/ IMAD R37, R12, R6, R35 ; /* 0x000000060c257224 */
/* 0x004fc400078e0223 */
/*0850*/ IMAD.WIDE R12, R15, c[0x0][0x17c], R10 ; /* 0x00005f000f0c7a25 */
/* 0x000fc600078e020a */
/*0860*/ STG.E [R2.64], R37 ; /* 0x0000002502007986 */
/* 0x0003e8000c101904 */
/*0870*/ LDG.E R6, [R12.64] ; /* 0x000000040c067981 */
/* 0x000ea8000c1e1900 */
/*0880*/ LDG.E R9, [R4.64+0xc] ; /* 0x00000c0404097981 */
/* 0x0006a2000c1e1900 */
/*0890*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f25270 */
/*08a0*/ IADD3 R8, P2, R4, 0x10, RZ ; /* 0x0000001004087810 */
/* 0x000fc40007f5e0ff */
/*08b0*/ IADD3 R14, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fc60007ffe0ff */
/*08c0*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x008fe400010e0605 */
/*08d0*/ IMAD R9, R6, R9, R37 ; /* 0x0000000906097224 */
/* 0x004fe400078e0225 */
/*08e0*/ IMAD.WIDE R6, R15, c[0x0][0x17c], R12 ; /* 0x00005f000f067a25 */
/* 0x000fc600078e020c */
/*08f0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e2000c101904 */
/*0900*/ @P1 BRA 0x750 ; /* 0xfffffe4000001947 */
/* 0x000fea000383ffff */
/*0910*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0920*/ @!P0 BRA 0xae0 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0930*/ IMAD R8, R14, c[0x0][0x17c], R25 ; /* 0x00005f000e087a24 */
/* 0x000fe200078e0219 */
/*0940*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0950*/ IMAD.IADD R4, R32, 0x1, R14 ; /* 0x0000000120047824 */
/* 0x000fe400078e020e */
/*0960*/ IMAD.WIDE R6, R8, R15, c[0x0][0x168] ; /* 0x00005a0008067625 */
/* 0x000fc800078e020f */
/*0970*/ IMAD.WIDE R4, R4, R15, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e020f */
/*0980*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*0990*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea2000c1e1900 */
/*09a0*/ ISETP.NE.AND P0, PT, R34, 0x1, PT ; /* 0x000000012200780c */
/* 0x000fe20003f05270 */
/*09b0*/ IMAD R11, R6, R0, R9 ; /* 0x00000000060b7224 */
/* 0x004fca00078e0209 */
/*09c0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005ee000c101904 */
/*09d0*/ @!P0 BRA 0xae0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*09e0*/ IADD3 R8, R8, c[0x0][0x17c], RZ ; /* 0x00005f0008087a10 */
/* 0x000fe20007ffe0ff */
/*09f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0a00*/ LDG.E R9, [R4.64+0x4] ; /* 0x0000040404097981 */
/* 0x002ee4000c1e1900 */
/*0a10*/ IMAD.WIDE R6, R8, R15, c[0x0][0x168] ; /* 0x00005a0008067625 */
/* 0x000fcc00078e020f */
/*0a20*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1900 */
/*0a30*/ ISETP.NE.AND P0, PT, R34, 0x2, PT ; /* 0x000000022200780c */
/* 0x000fe20003f05270 */
/*0a40*/ IMAD R9, R6, R9, R11 ; /* 0x0000000906097224 */
/* 0x008fca00078e020b */
/*0a50*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003ee000c101904 */
/*0a60*/ @!P0 BRA 0xae0 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*0a70*/ IADD3 R6, R8, c[0x0][0x17c], RZ ; /* 0x00005f0008067a10 */
/* 0x000fe20007ffe0ff */
/*0a80*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0a90*/ LDG.E R5, [R4.64+0x8] ; /* 0x0000080404057981 */
/* 0x000ee4000c1e1900 */
/*0aa0*/ IMAD.WIDE R6, R6, R15, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fcc00078e020f */
/*0ab0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee4000c1e1900 */
/*0ac0*/ IMAD R9, R6, R5, R9 ; /* 0x0000000506097224 */
/* 0x00afca00078e0209 */
/*0ad0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e4000c101904 */
/*0ae0*/ IADD3 R25, R30, R25, RZ ; /* 0x000000191e197210 */
/* 0x000fe40007ffe0ff */
/*0af0*/ IADD3 R33, R33, 0x1, RZ ; /* 0x0000000121217810 */
/* 0x000fe40007ffe0ff */
/*0b00*/ ISETP.GE.AND P0, PT, R25, c[0x0][0x17c], PT ; /* 0x00005f0019007a0c */
/* 0x000fda0003f06270 */
/*0b10*/ @!P0 BRA 0x520 ; /* 0xfffffa0000008947 */
/* 0x000fea000383ffff */
/*0b20*/ BSYNC B6 ; /* 0x0000000000067941 */
/* 0x000fea0003800000 */
/*0b30*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x4] ; /* 0x00000100ff037624 */
/* 0x007fc800078e00ff */
/*0b40*/ IMAD R24, R3, c[0x0][0x10], R24 ; /* 0x0000040003187a24 */
/* 0x000fca00078e0218 */
/*0b50*/ ISETP.GE.AND P0, PT, R24, c[0x0][0x178], PT ; /* 0x00005e0018007a0c */
/* 0x000fda0003f06270 */
/*0b60*/ @!P0 BRA 0x4a0 ; /* 0xfffff93000008947 */
/* 0x000fea000383ffff */
/*0b70*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b80*/ BRA 0xb80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
// by lectures and "CUDA by Example" book
#define ind(i, j, cols) (i * cols + j)
struct dim2 {
int rows;
int cols;
};
// device code: matrices mult calculation
__global__ void mult_matrices_kernel(int* m1, int* m2, int* m3, dim2 m3_dims, int inner_dim) {
int rows = m3_dims.rows;
int cols = m3_dims.cols;
printf("blockId, threadId, dims: [%d, %d], [%d, %d], [%d, %d]\n",
blockIdx.y, blockIdx.x, threadIdx.y, threadIdx.x, rows, cols);
// row and col that correspond to current thread
// process all elements that correspond to current thread
for (int i = blockIdx.y * blockDim.y + threadIdx.y;
i < rows; i += blockDim.y * gridDim.y)
for (int j = blockIdx.x * blockDim.x + threadIdx.x;
j < cols; j += blockDim.x * gridDim.x) {
printf("blockId, threadId, pos: [%d, %d], [%d, %d], [%d, %d]\n",
blockIdx.y, blockIdx.x, threadIdx.y, threadIdx.x, i, j);
int index_3 = ind(i, j, cols);
m3[index_3] = 0;
// iterating over row and down column
for (int k = 0; k < inner_dim; k++) {
int index_1 = ind(i, k, inner_dim);
int index_2 = ind(k, j, cols);
m3[index_3] += m1[index_1] * m2[index_2];
}
}
}
int* cuda_copy_mat(int* host_m, dim2 m_dims) {
int* dev_m;
// size of memory to allocate on device for matrix
long mem_size = m_dims.rows * m_dims.cols * sizeof(int);
// device memory allocation
cudaMalloc((void**) &dev_m, mem_size);
// copying data from host to device
cudaMemcpy(dev_m, host_m, mem_size, cudaMemcpyHostToDevice);
// returning pointer
return dev_m;
}
// host code: preparation
void mult_matrices_gpu(int* host_m1, dim2 m1_dims,
int* host_m2, dim2 m2_dims,
int* host_m3, dim2 m3_dims) {
// Step 1: moving data on device
int* dev_m1 = cuda_copy_mat(host_m1, m1_dims);
int* dev_m2 = cuda_copy_mat(host_m2, m3_dims);
int* dev_m3 = cuda_copy_mat(host_m3, m3_dims);
// Step 2
// grid (of blocks) dimensions
dim3 grid_dim(3, 2, 1);
// block (of threads) dimensions
dim3 block_dim(2, 2, 1);
// running kernel multiplication code
mult_matrices_kernel<<<grid_dim, block_dim>>>(dev_m1, dev_m2, dev_m3, m3_dims, m1_dims.cols);
// Step 3
// copying result from device to host matrix
cudaMemcpy(host_m3, dev_m3, m3_dims.rows * m3_dims.cols * sizeof(int), cudaMemcpyDeviceToHost);
// freeing device memory
cudaFree(dev_m1);
cudaFree(dev_m2);
cudaFree(dev_m3);
}
void mult_matrices_cpu(int* m1, dim2 m1_dims,
int* m2, dim2 m2_dims,
int* m3, dim2 m3_dims) {
for (int i = 0; i < m1_dims.rows; i++)
for (int j = 0; j < m2_dims.cols; j++) {
int index_3 = ind(i, j, m3_dims.cols);
m3[index_3] = 0;
for (int k = 0; k < m1_dims.cols; k++) {
int index_1 = ind(i, k, m1_dims.cols);
int index_2 = ind(k, j, m2_dims.cols);
m3[index_3] += m1[index_1] * m2[index_2];
}
}
}
// create matrix (array representation)
int* create_mat(dim2 dims, int k) {
int rows = dims.rows;
int cols = dims.cols;
int* mat = (int*)malloc(rows * cols * sizeof(int));
for (int i = 0; i < rows; i++)
for (int j = 0; j < cols; j++)
mat[ind(i, j, cols)] = k * (ind(i, j, cols) + 1);
return mat;
}
// print matrix
void print_mat(const char* header, int* mat, dim2 dims) {
int rows = dims.rows;
int cols = dims.cols;
printf("%s (%d, %d):\n", header, rows, cols);
for (int i = 0; i < rows; i++)
for (int j = 0; j < cols; j++) {
printf("\t%d ", mat[ind(i, j, cols)]);
if (j == cols - 1)
printf("\n");
}
}
int main() {
// first matrix
struct dim2 m1_dims = {6, 4};
int* host_m1 = create_mat(m1_dims, 1);
print_mat("First matrix", host_m1, m1_dims);
// second matrix
struct dim2 m2_dims = {4, 8};
int* host_m2 = create_mat(m2_dims, 2);
print_mat("Second matrix", host_m2, m2_dims);
// dimensionality validation
if (m1_dims.cols != m2_dims.rows) {
printf("Error: Inner matrix dimensions does not match:\n"
"(%d, %d) and (%d, %d)",
m1_dims.rows, m1_dims.cols, m2_dims.rows, m2_dims.cols);
return 0;
}
// result matrix
struct dim2 m3_dims = {m1_dims.rows, m2_dims.cols};
int* host_m3 = create_mat(m3_dims, 0);
print_mat("Third matrix", host_m3, m3_dims);
// multiplication
mult_matrices_gpu(host_m1, m1_dims,
host_m2, m2_dims,
host_m3, m3_dims);
// showing result
print_mat("Result matrix", host_m3, m3_dims);
// multiplication
mult_matrices_cpu(host_m1, m1_dims,
host_m2, m2_dims,
host_m3, m3_dims);
// showing result
print_mat("Result matrix", host_m3, m3_dims);
return 0;
} | .file "tmpxft_000b57a9_00000000-6_demo.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13cuda_copy_matPi4dim2
.type _Z13cuda_copy_matPi4dim2, @function
_Z13cuda_copy_matPi4dim2:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsi, %rbx
shrq $32, %rbx
imull %esi, %ebx
movslq %ebx, %rbx
salq $2, %rbx
movq %rsp, %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movq (%rsp), %rax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L6
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z13cuda_copy_matPi4dim2, .-_Z13cuda_copy_matPi4dim2
.globl _Z17mult_matrices_cpuPi4dim2S_S0_S_S0_
.type _Z17mult_matrices_cpuPi4dim2S_S0_S_S0_, @function
_Z17mult_matrices_cpuPi4dim2S_S0_S_S0_:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rsi, %rax
movq %rdx, -24(%rsp)
movq %r8, -16(%rsp)
movl %esi, %r15d
sarq $32, %rsi
sarq $32, %rcx
testl %eax, %eax
jle .L7
movq %rdi, %r14
movq %r9, %rdx
movl %esi, %ebp
movq %rcx, %r8
movl %ecx, %ebx
shrq $32, %rdx
movl %esi, -32(%rsp)
salq $2, %r8
movl $0, %r13d
movl $0, %esi
movl $0, %ecx
movslq %ebp, %rax
movq %rax, -8(%rsp)
movl %r15d, -28(%rsp)
movl %edx, %edi
movq %r14, %rdx
jmp .L9
.L13:
movslq %esi, %rax
movq -16(%rsp), %r15
leaq (%r15,%rax,4), %r11
movq -24(%rsp), %r14
movslq %r13d, %rax
leaq (%rdx,%rax,4), %r15
movq -8(%rsp), %r9
addq %r9, %rax
leaq (%rdx,%rax,4), %r10
movl $0, %r12d
movl %ecx, -40(%rsp)
movl %esi, -36(%rsp)
.L12:
movq %r11, %r9
movl $0, (%r11)
testl %ebp, %ebp
jle .L10
movq %r14, %rsi
movq %r15, %rax
.L11:
movl (%rax), %ecx
imull (%rsi), %ecx
addl %ecx, (%r9)
addq $4, %rax
addq %r8, %rsi
cmpq %r10, %rax
jne .L11
.L10:
addl $1, %r12d
addq $4, %r11
addq $4, %r14
cmpl %r12d, %ebx
jne .L12
movl -40(%rsp), %ecx
movl -36(%rsp), %esi
.L14:
addl $1, %ecx
addl %edi, %esi
movl -32(%rsp), %eax
addl %eax, %r13d
movl -28(%rsp), %eax
cmpl %eax, %ecx
je .L7
.L9:
testl %ebx, %ebx
jg .L13
jmp .L14
.L7:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z17mult_matrices_cpuPi4dim2S_S0_S_S0_, .-_Z17mult_matrices_cpuPi4dim2S_S0_S_S0_
.globl _Z10create_mat4dim2i
.type _Z10create_mat4dim2i, @function
_Z10create_mat4dim2i:
.LFB2060:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r14
movl %esi, %ebx
movl %edi, %r12d
movq %rdi, %r13
sarq $32, %r13
movl %r13d, %edi
imull %r14d, %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r9
testl %r14d, %r14d
jle .L18
movl %r13d, %ebp
movl %r13d, %r11d
movl %r13d, %r10d
imull %ebx, %r10d
movl %ebx, %r8d
movl $0, %edi
movl $0, %esi
movslq %r13d, %r13
jmp .L20
.L22:
movslq %edi, %rdx
leaq (%r9,%rdx,4), %rax
addq %r13, %rdx
leaq (%r9,%rdx,4), %rcx
movl %r8d, %edx
.L21:
movl %edx, (%rax)
addl %ebx, %edx
addq $4, %rax
cmpq %rcx, %rax
jne .L21
.L23:
addl $1, %esi
addl %r10d, %r8d
addl %r11d, %edi
cmpl %esi, %r12d
je .L18
.L20:
testl %ebp, %ebp
jg .L22
jmp .L23
.L18:
movq %r9, %rax
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z10create_mat4dim2i, .-_Z10create_mat4dim2i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s (%d, %d):\n"
.LC1:
.string "\t%d "
.LC2:
.string "\n"
.text
.globl _Z9print_matPKcPi4dim2
.type _Z9print_matPKcPi4dim2, @function
_Z9print_matPKcPi4dim2:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rsi, 24(%rsp)
movq %rdx, %rbx
movl %edx, %ecx
movl %edx, 16(%rsp)
movq %rdx, %rbp
sarq $32, %rbp
movl %ebp, %r8d
movq %rdi, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jle .L26
movl %ebp, %r15d
movl %ebp, 20(%rsp)
movl $0, %ecx
movl $0, %eax
movslq %ebp, %r14
leaq .LC1(%rip), %r13
jmp .L28
.L29:
addq $1, %rbx
cmpq %r14, %rbx
je .L35
.L30:
movl (%r12,%rbx,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl %ebx, %ebp
jne .L29
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L29
.L35:
movl %r15d, %eax
movl 8(%rsp), %r15d
movl 12(%rsp), %ecx
.L32:
addl $1, %eax
movl 20(%rsp), %esi
addl %esi, %ecx
cmpl %eax, 16(%rsp)
je .L26
.L28:
testl %r15d, %r15d
jle .L32
movslq %ecx, %rdx
movq 24(%rsp), %rsi
leaq (%rsi,%rdx,4), %r12
movl $0, %ebx
leal -1(%r15), %ebp
movl %r15d, 8(%rsp)
movl %eax, %r15d
movl %ecx, 12(%rsp)
jmp .L30
.L26:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z9print_matPKcPi4dim2, .-_Z9print_matPKcPi4dim2
.globl _Z50__device_stub__Z20mult_matrices_kernelPiS_S_4dim2iPiS_S_R4dim2i
.type _Z50__device_stub__Z20mult_matrices_kernelPiS_S_4dim2iPiS_S_R4dim2i, @function
_Z50__device_stub__Z20mult_matrices_kernelPiS_S_4dim2iPiS_S_R4dim2i:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rcx, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L40
.L36:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L41
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20mult_matrices_kernelPiS_S_4dim2i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L36
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z50__device_stub__Z20mult_matrices_kernelPiS_S_4dim2iPiS_S_R4dim2i, .-_Z50__device_stub__Z20mult_matrices_kernelPiS_S_4dim2iPiS_S_R4dim2i
.globl _Z20mult_matrices_kernelPiS_S_4dim2i
.type _Z20mult_matrices_kernelPiS_S_4dim2i, @function
_Z20mult_matrices_kernelPiS_S_4dim2i:
.LFB2088:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rcx, 8(%rsp)
leaq 8(%rsp), %rcx
call _Z50__device_stub__Z20mult_matrices_kernelPiS_S_4dim2iPiS_S_R4dim2i
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z20mult_matrices_kernelPiS_S_4dim2i, .-_Z20mult_matrices_kernelPiS_S_4dim2i
.globl _Z17mult_matrices_gpuPi4dim2S_S0_S_S0_
.type _Z17mult_matrices_gpuPi4dim2S_S0_S_S0_, @function
_Z17mult_matrices_gpuPi4dim2S_S0_S_S0_:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rsi, %r15
movq %rdx, %rbp
movq %r8, %r12
movq %r9, %rbx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
call _Z13cuda_copy_matPi4dim2
movq %rax, %r14
movq %rbx, %rsi
movq %rbp, %rdi
call _Z13cuda_copy_matPi4dim2
movq %rax, %r13
movq %rbx, %rsi
movq %r12, %rdi
call _Z13cuda_copy_matPi4dim2
movq %rax, %rbp
movl $3, 16(%rsp)
movl $2, 20(%rsp)
movl $2, 28(%rsp)
movl $2, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L48
.L45:
movq %rbx, %rax
sarq $32, %rax
imull %eax, %ebx
movslq %ebx, %rdx
salq $2, %rdx
movl $2, %ecx
movq %rbp, %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq %r14, %rdi
call cudaFree@PLT
movq %r13, %rdi
call cudaFree@PLT
movq %rbp, %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L49
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
movq %rbx, 8(%rsp)
leaq 8(%rsp), %rcx
shrq $32, %r15
movq %r15, %r8
movq %rbp, %rdx
movq %r13, %rsi
movq %r14, %rdi
call _Z50__device_stub__Z20mult_matrices_kernelPiS_S_4dim2iPiS_S_R4dim2i
jmp .L45
.L49:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z17mult_matrices_gpuPi4dim2S_S0_S_S0_, .-_Z17mult_matrices_gpuPi4dim2S_S0_S_S0_
.section .rodata.str1.1
.LC3:
.string "First matrix"
.LC4:
.string "Second matrix"
.LC5:
.string "Third matrix"
.LC6:
.string "Result matrix"
.text
.globl main
.type main, @function
main:
.LFB2062:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movabsq $17179869190, %r14
movl $1, %esi
movq %r14, %rdi
call _Z10create_mat4dim2i
movq %rax, %r12
movq %r14, %rdx
movq %rax, %rsi
leaq .LC3(%rip), %rdi
call _Z9print_matPKcPi4dim2
movabsq $34359738368, %rbx
movq %rbx, %r15
orq $4, %r15
movl $2, %esi
movq %r15, %rdi
call _Z10create_mat4dim2i
movq %rax, %r13
movq %r15, %rdx
movq %rax, %rsi
leaq .LC4(%rip), %rdi
call _Z9print_matPKcPi4dim2
orq $6, %rbx
movl $0, %esi
movq %rbx, %rdi
call _Z10create_mat4dim2i
movq %rax, %rbp
movq %rbx, %rdx
movq %rax, %rsi
leaq .LC5(%rip), %rdi
call _Z9print_matPKcPi4dim2
movq %rbx, %r9
movq %rbp, %r8
movq %r15, %rcx
movq %r13, %rdx
movq %r14, %rsi
movq %r12, %rdi
call _Z17mult_matrices_gpuPi4dim2S_S0_S_S0_
movq %rbx, %rdx
movq %rbp, %rsi
leaq .LC6(%rip), %rdi
call _Z9print_matPKcPi4dim2
movq %rbx, %r9
movq %rbp, %r8
movq %r15, %rcx
movq %r13, %rdx
movq %r14, %rsi
movq %r12, %rdi
call _Z17mult_matrices_cpuPi4dim2S_S0_S_S0_
movq %rbx, %rdx
movq %rbp, %rsi
leaq .LC6(%rip), %rdi
call _Z9print_matPKcPi4dim2
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "_Z20mult_matrices_kernelPiS_S_4dim2i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z20mult_matrices_kernelPiS_S_4dim2i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
// by lectures and "CUDA by Example" book
#define ind(i, j, cols) (i * cols + j)
struct dim2 {
int rows;
int cols;
};
// device code: matrices mult calculation
__global__ void mult_matrices_kernel(int* m1, int* m2, int* m3, dim2 m3_dims, int inner_dim) {
int rows = m3_dims.rows;
int cols = m3_dims.cols;
printf("blockId, threadId, dims: [%d, %d], [%d, %d], [%d, %d]\n",
blockIdx.y, blockIdx.x, threadIdx.y, threadIdx.x, rows, cols);
// row and col that correspond to current thread
// process all elements that correspond to current thread
for (int i = blockIdx.y * blockDim.y + threadIdx.y;
i < rows; i += blockDim.y * gridDim.y)
for (int j = blockIdx.x * blockDim.x + threadIdx.x;
j < cols; j += blockDim.x * gridDim.x) {
printf("blockId, threadId, pos: [%d, %d], [%d, %d], [%d, %d]\n",
blockIdx.y, blockIdx.x, threadIdx.y, threadIdx.x, i, j);
int index_3 = ind(i, j, cols);
m3[index_3] = 0;
// iterating over row and down column
for (int k = 0; k < inner_dim; k++) {
int index_1 = ind(i, k, inner_dim);
int index_2 = ind(k, j, cols);
m3[index_3] += m1[index_1] * m2[index_2];
}
}
}
int* cuda_copy_mat(int* host_m, dim2 m_dims) {
int* dev_m;
// size of memory to allocate on device for matrix
long mem_size = m_dims.rows * m_dims.cols * sizeof(int);
// device memory allocation
cudaMalloc((void**) &dev_m, mem_size);
// copying data from host to device
cudaMemcpy(dev_m, host_m, mem_size, cudaMemcpyHostToDevice);
// returning pointer
return dev_m;
}
// host code: preparation
void mult_matrices_gpu(int* host_m1, dim2 m1_dims,
int* host_m2, dim2 m2_dims,
int* host_m3, dim2 m3_dims) {
// Step 1: moving data on device
int* dev_m1 = cuda_copy_mat(host_m1, m1_dims);
int* dev_m2 = cuda_copy_mat(host_m2, m3_dims);
int* dev_m3 = cuda_copy_mat(host_m3, m3_dims);
// Step 2
// grid (of blocks) dimensions
dim3 grid_dim(3, 2, 1);
// block (of threads) dimensions
dim3 block_dim(2, 2, 1);
// running kernel multiplication code
mult_matrices_kernel<<<grid_dim, block_dim>>>(dev_m1, dev_m2, dev_m3, m3_dims, m1_dims.cols);
// Step 3
// copying result from device to host matrix
cudaMemcpy(host_m3, dev_m3, m3_dims.rows * m3_dims.cols * sizeof(int), cudaMemcpyDeviceToHost);
// freeing device memory
cudaFree(dev_m1);
cudaFree(dev_m2);
cudaFree(dev_m3);
}
void mult_matrices_cpu(int* m1, dim2 m1_dims,
int* m2, dim2 m2_dims,
int* m3, dim2 m3_dims) {
for (int i = 0; i < m1_dims.rows; i++)
for (int j = 0; j < m2_dims.cols; j++) {
int index_3 = ind(i, j, m3_dims.cols);
m3[index_3] = 0;
for (int k = 0; k < m1_dims.cols; k++) {
int index_1 = ind(i, k, m1_dims.cols);
int index_2 = ind(k, j, m2_dims.cols);
m3[index_3] += m1[index_1] * m2[index_2];
}
}
}
// create matrix (array representation)
int* create_mat(dim2 dims, int k) {
int rows = dims.rows;
int cols = dims.cols;
int* mat = (int*)malloc(rows * cols * sizeof(int));
for (int i = 0; i < rows; i++)
for (int j = 0; j < cols; j++)
mat[ind(i, j, cols)] = k * (ind(i, j, cols) + 1);
return mat;
}
// print matrix
void print_mat(const char* header, int* mat, dim2 dims) {
int rows = dims.rows;
int cols = dims.cols;
printf("%s (%d, %d):\n", header, rows, cols);
for (int i = 0; i < rows; i++)
for (int j = 0; j < cols; j++) {
printf("\t%d ", mat[ind(i, j, cols)]);
if (j == cols - 1)
printf("\n");
}
}
int main() {
// first matrix
struct dim2 m1_dims = {6, 4};
int* host_m1 = create_mat(m1_dims, 1);
print_mat("First matrix", host_m1, m1_dims);
// second matrix
struct dim2 m2_dims = {4, 8};
int* host_m2 = create_mat(m2_dims, 2);
print_mat("Second matrix", host_m2, m2_dims);
// dimensionality validation
if (m1_dims.cols != m2_dims.rows) {
printf("Error: Inner matrix dimensions does not match:\n"
"(%d, %d) and (%d, %d)",
m1_dims.rows, m1_dims.cols, m2_dims.rows, m2_dims.cols);
return 0;
}
// result matrix
struct dim2 m3_dims = {m1_dims.rows, m2_dims.cols};
int* host_m3 = create_mat(m3_dims, 0);
print_mat("Third matrix", host_m3, m3_dims);
// multiplication
mult_matrices_gpu(host_m1, m1_dims,
host_m2, m2_dims,
host_m3, m3_dims);
// showing result
print_mat("Result matrix", host_m3, m3_dims);
// multiplication
mult_matrices_cpu(host_m1, m1_dims,
host_m2, m2_dims,
host_m3, m3_dims);
// showing result
print_mat("Result matrix", host_m3, m3_dims);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
// by lectures and "CUDA by Example" book
#define ind(i, j, cols) (i * cols + j)
struct dim2 {
int rows;
int cols;
};
// device code: matrices mult calculation
__global__ void mult_matrices_kernel(int* m1, int* m2, int* m3, dim2 m3_dims, int inner_dim) {
int rows = m3_dims.rows;
int cols = m3_dims.cols;
printf("blockId, threadId, dims: [%d, %d], [%d, %d], [%d, %d]\n",
blockIdx.y, blockIdx.x, threadIdx.y, threadIdx.x, rows, cols);
// row and col that correspond to current thread
// process all elements that correspond to current thread
for (int i = blockIdx.y * blockDim.y + threadIdx.y;
i < rows; i += blockDim.y * gridDim.y)
for (int j = blockIdx.x * blockDim.x + threadIdx.x;
j < cols; j += blockDim.x * gridDim.x) {
printf("blockId, threadId, pos: [%d, %d], [%d, %d], [%d, %d]\n",
blockIdx.y, blockIdx.x, threadIdx.y, threadIdx.x, i, j);
int index_3 = ind(i, j, cols);
m3[index_3] = 0;
// iterating over row and down column
for (int k = 0; k < inner_dim; k++) {
int index_1 = ind(i, k, inner_dim);
int index_2 = ind(k, j, cols);
m3[index_3] += m1[index_1] * m2[index_2];
}
}
}
int* cuda_copy_mat(int* host_m, dim2 m_dims) {
int* dev_m;
// size of memory to allocate on device for matrix
long mem_size = m_dims.rows * m_dims.cols * sizeof(int);
// device memory allocation
hipMalloc((void**) &dev_m, mem_size);
// copying data from host to device
hipMemcpy(dev_m, host_m, mem_size, hipMemcpyHostToDevice);
// returning pointer
return dev_m;
}
// host code: preparation
void mult_matrices_gpu(int* host_m1, dim2 m1_dims,
int* host_m2, dim2 m2_dims,
int* host_m3, dim2 m3_dims) {
// Step 1: moving data on device
int* dev_m1 = cuda_copy_mat(host_m1, m1_dims);
int* dev_m2 = cuda_copy_mat(host_m2, m3_dims);
int* dev_m3 = cuda_copy_mat(host_m3, m3_dims);
// Step 2
// grid (of blocks) dimensions
dim3 grid_dim(3, 2, 1);
// block (of threads) dimensions
dim3 block_dim(2, 2, 1);
// running kernel multiplication code
mult_matrices_kernel<<<grid_dim, block_dim>>>(dev_m1, dev_m2, dev_m3, m3_dims, m1_dims.cols);
// Step 3
// copying result from device to host matrix
hipMemcpy(host_m3, dev_m3, m3_dims.rows * m3_dims.cols * sizeof(int), hipMemcpyDeviceToHost);
// freeing device memory
hipFree(dev_m1);
hipFree(dev_m2);
hipFree(dev_m3);
}
void mult_matrices_cpu(int* m1, dim2 m1_dims,
int* m2, dim2 m2_dims,
int* m3, dim2 m3_dims) {
for (int i = 0; i < m1_dims.rows; i++)
for (int j = 0; j < m2_dims.cols; j++) {
int index_3 = ind(i, j, m3_dims.cols);
m3[index_3] = 0;
for (int k = 0; k < m1_dims.cols; k++) {
int index_1 = ind(i, k, m1_dims.cols);
int index_2 = ind(k, j, m2_dims.cols);
m3[index_3] += m1[index_1] * m2[index_2];
}
}
}
// create matrix (array representation)
int* create_mat(dim2 dims, int k) {
int rows = dims.rows;
int cols = dims.cols;
int* mat = (int*)malloc(rows * cols * sizeof(int));
for (int i = 0; i < rows; i++)
for (int j = 0; j < cols; j++)
mat[ind(i, j, cols)] = k * (ind(i, j, cols) + 1);
return mat;
}
// print matrix
void print_mat(const char* header, int* mat, dim2 dims) {
int rows = dims.rows;
int cols = dims.cols;
printf("%s (%d, %d):\n", header, rows, cols);
for (int i = 0; i < rows; i++)
for (int j = 0; j < cols; j++) {
printf("\t%d ", mat[ind(i, j, cols)]);
if (j == cols - 1)
printf("\n");
}
}
int main() {
// first matrix
struct dim2 m1_dims = {6, 4};
int* host_m1 = create_mat(m1_dims, 1);
print_mat("First matrix", host_m1, m1_dims);
// second matrix
struct dim2 m2_dims = {4, 8};
int* host_m2 = create_mat(m2_dims, 2);
print_mat("Second matrix", host_m2, m2_dims);
// dimensionality validation
if (m1_dims.cols != m2_dims.rows) {
printf("Error: Inner matrix dimensions does not match:\n"
"(%d, %d) and (%d, %d)",
m1_dims.rows, m1_dims.cols, m2_dims.rows, m2_dims.cols);
return 0;
}
// result matrix
struct dim2 m3_dims = {m1_dims.rows, m2_dims.cols};
int* host_m3 = create_mat(m3_dims, 0);
print_mat("Third matrix", host_m3, m3_dims);
// multiplication
mult_matrices_gpu(host_m1, m1_dims,
host_m2, m2_dims,
host_m3, m3_dims);
// showing result
print_mat("Result matrix", host_m3, m3_dims);
// multiplication
mult_matrices_cpu(host_m1, m1_dims,
host_m2, m2_dims,
host_m3, m3_dims);
// showing result
print_mat("Result matrix", host_m3, m3_dims);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
// by lectures and "CUDA by Example" book
#define ind(i, j, cols) (i * cols + j)
struct dim2 {
int rows;
int cols;
};
// device code: matrices mult calculation
__global__ void mult_matrices_kernel(int* m1, int* m2, int* m3, dim2 m3_dims, int inner_dim) {
int rows = m3_dims.rows;
int cols = m3_dims.cols;
printf("blockId, threadId, dims: [%d, %d], [%d, %d], [%d, %d]\n",
blockIdx.y, blockIdx.x, threadIdx.y, threadIdx.x, rows, cols);
// row and col that correspond to current thread
// process all elements that correspond to current thread
for (int i = blockIdx.y * blockDim.y + threadIdx.y;
i < rows; i += blockDim.y * gridDim.y)
for (int j = blockIdx.x * blockDim.x + threadIdx.x;
j < cols; j += blockDim.x * gridDim.x) {
printf("blockId, threadId, pos: [%d, %d], [%d, %d], [%d, %d]\n",
blockIdx.y, blockIdx.x, threadIdx.y, threadIdx.x, i, j);
int index_3 = ind(i, j, cols);
m3[index_3] = 0;
// iterating over row and down column
for (int k = 0; k < inner_dim; k++) {
int index_1 = ind(i, k, inner_dim);
int index_2 = ind(k, j, cols);
m3[index_3] += m1[index_1] * m2[index_2];
}
}
}
int* cuda_copy_mat(int* host_m, dim2 m_dims) {
int* dev_m;
// size of memory to allocate on device for matrix
long mem_size = m_dims.rows * m_dims.cols * sizeof(int);
// device memory allocation
hipMalloc((void**) &dev_m, mem_size);
// copying data from host to device
hipMemcpy(dev_m, host_m, mem_size, hipMemcpyHostToDevice);
// returning pointer
return dev_m;
}
// host code: preparation
void mult_matrices_gpu(int* host_m1, dim2 m1_dims,
int* host_m2, dim2 m2_dims,
int* host_m3, dim2 m3_dims) {
// Step 1: moving data on device
int* dev_m1 = cuda_copy_mat(host_m1, m1_dims);
int* dev_m2 = cuda_copy_mat(host_m2, m3_dims);
int* dev_m3 = cuda_copy_mat(host_m3, m3_dims);
// Step 2
// grid (of blocks) dimensions
dim3 grid_dim(3, 2, 1);
// block (of threads) dimensions
dim3 block_dim(2, 2, 1);
// running kernel multiplication code
mult_matrices_kernel<<<grid_dim, block_dim>>>(dev_m1, dev_m2, dev_m3, m3_dims, m1_dims.cols);
// Step 3
// copying result from device to host matrix
hipMemcpy(host_m3, dev_m3, m3_dims.rows * m3_dims.cols * sizeof(int), hipMemcpyDeviceToHost);
// freeing device memory
hipFree(dev_m1);
hipFree(dev_m2);
hipFree(dev_m3);
}
void mult_matrices_cpu(int* m1, dim2 m1_dims,
int* m2, dim2 m2_dims,
int* m3, dim2 m3_dims) {
for (int i = 0; i < m1_dims.rows; i++)
for (int j = 0; j < m2_dims.cols; j++) {
int index_3 = ind(i, j, m3_dims.cols);
m3[index_3] = 0;
for (int k = 0; k < m1_dims.cols; k++) {
int index_1 = ind(i, k, m1_dims.cols);
int index_2 = ind(k, j, m2_dims.cols);
m3[index_3] += m1[index_1] * m2[index_2];
}
}
}
// create matrix (array representation)
int* create_mat(dim2 dims, int k) {
int rows = dims.rows;
int cols = dims.cols;
int* mat = (int*)malloc(rows * cols * sizeof(int));
for (int i = 0; i < rows; i++)
for (int j = 0; j < cols; j++)
mat[ind(i, j, cols)] = k * (ind(i, j, cols) + 1);
return mat;
}
// print matrix
void print_mat(const char* header, int* mat, dim2 dims) {
int rows = dims.rows;
int cols = dims.cols;
printf("%s (%d, %d):\n", header, rows, cols);
for (int i = 0; i < rows; i++)
for (int j = 0; j < cols; j++) {
printf("\t%d ", mat[ind(i, j, cols)]);
if (j == cols - 1)
printf("\n");
}
}
int main() {
// first matrix
struct dim2 m1_dims = {6, 4};
int* host_m1 = create_mat(m1_dims, 1);
print_mat("First matrix", host_m1, m1_dims);
// second matrix
struct dim2 m2_dims = {4, 8};
int* host_m2 = create_mat(m2_dims, 2);
print_mat("Second matrix", host_m2, m2_dims);
// dimensionality validation
if (m1_dims.cols != m2_dims.rows) {
printf("Error: Inner matrix dimensions does not match:\n"
"(%d, %d) and (%d, %d)",
m1_dims.rows, m1_dims.cols, m2_dims.rows, m2_dims.cols);
return 0;
}
// result matrix
struct dim2 m3_dims = {m1_dims.rows, m2_dims.cols};
int* host_m3 = create_mat(m3_dims, 0);
print_mat("Third matrix", host_m3, m3_dims);
// multiplication
mult_matrices_gpu(host_m1, m1_dims,
host_m2, m2_dims,
host_m3, m3_dims);
// showing result
print_mat("Result matrix", host_m3, m3_dims);
// multiplication
mult_matrices_cpu(host_m1, m1_dims,
host_m2, m2_dims,
host_m3, m3_dims);
// showing result
print_mat("Result matrix", host_m3, m3_dims);
return 0;
} | .text
.file "demo.hip"
.globl _Z35__device_stub__mult_matrices_kernelPiS_S_4dim2i # -- Begin function _Z35__device_stub__mult_matrices_kernelPiS_S_4dim2i
.p2align 4, 0x90
.type _Z35__device_stub__mult_matrices_kernelPiS_S_4dim2i,@function
_Z35__device_stub__mult_matrices_kernelPiS_S_4dim2i: # @_Z35__device_stub__mult_matrices_kernelPiS_S_4dim2i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rcx, 88(%rsp)
movq %rdi, 80(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20mult_matrices_kernelPiS_S_4dim2i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z35__device_stub__mult_matrices_kernelPiS_S_4dim2i, .Lfunc_end0-_Z35__device_stub__mult_matrices_kernelPiS_S_4dim2i
.cfi_endproc
# -- End function
.globl _Z13cuda_copy_matPi4dim2 # -- Begin function _Z13cuda_copy_matPi4dim2
.p2align 4, 0x90
.type _Z13cuda_copy_matPi4dim2,@function
_Z13cuda_copy_matPi4dim2: # @_Z13cuda_copy_matPi4dim2
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
movq %rsi, %rax
shrq $32, %rax
imull %esi, %eax
movslq %eax, %r14
shlq $2, %r14
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
movq (%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z13cuda_copy_matPi4dim2, .Lfunc_end1-_Z13cuda_copy_matPi4dim2
.cfi_endproc
# -- End function
.globl _Z17mult_matrices_gpuPi4dim2S_S0_S_S0_ # -- Begin function _Z17mult_matrices_gpuPi4dim2S_S0_S_S0_
.p2align 4, 0x90
.type _Z17mult_matrices_gpuPi4dim2S_S0_S_S0_,@function
_Z17mult_matrices_gpuPi4dim2S_S0_S_S0_: # @_Z17mult_matrices_gpuPi4dim2S_S0_S_S0_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %r14
movq %r8, %r12
movq %rdx, (%rsp) # 8-byte Spill
movq %rdi, %r15
movq %rsi, %rbx
shrq $32, %rbx
movl %ebx, %eax
imull %esi, %eax
movslq %eax, %r13
shlq $2, %r13
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rax
movq %rax, 64(%rsp) # 8-byte Spill
movq %r14, %rbp
shrq $32, %rbp
movl %ebp, %eax
imull %r14d, %eax
movslq %eax, %r13
shlq $2, %r13
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq (%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %r15
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r12, (%rsp) # 8-byte Spill
movq %r12, %rsi
movq 64(%rsp), %r12 # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %r13
movabsq $8589934594, %rdx # imm = 0x200000002
leaq 1(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq %r14, 144(%rsp)
movq %r12, 136(%rsp)
movq %r15, 128(%rsp)
movq %r13, 120(%rsp)
movl %ebx, 12(%rsp)
leaq 136(%rsp), %rax
movq %rax, 16(%rsp)
leaq 128(%rsp), %rax
movq %rax, 24(%rsp)
leaq 120(%rsp), %rax
movq %rax, 32(%rsp)
leaq 144(%rsp), %rax
movq %rax, 40(%rsp)
leaq 12(%rsp), %rax
movq %rax, 48(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z20mult_matrices_kernelPiS_S_4dim2i, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
imull %ebp, %r14d
movslq %r14d, %rdx
shlq $2, %rdx
movq (%rsp), %rdi # 8-byte Reload
movq %r13, %rsi
movl $2, %ecx
callq hipMemcpy
movq %r12, %rdi
callq hipFree
movq %r15, %rdi
callq hipFree
movq %r13, %rdi
callq hipFree
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z17mult_matrices_gpuPi4dim2S_S0_S_S0_, .Lfunc_end2-_Z17mult_matrices_gpuPi4dim2S_S0_S_S0_
.cfi_endproc
# -- End function
.globl _Z17mult_matrices_cpuPi4dim2S_S0_S_S0_ # -- Begin function _Z17mult_matrices_cpuPi4dim2S_S0_S_S0_
.p2align 4, 0x90
.type _Z17mult_matrices_cpuPi4dim2S_S0_S_S0_,@function
_Z17mult_matrices_cpuPi4dim2S_S0_S_S0_: # @_Z17mult_matrices_cpuPi4dim2S_S0_S_S0_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, -8(%rsp) # 8-byte Spill
movq %rdx, -16(%rsp) # 8-byte Spill
movq %rdi, -24(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB3_9
# %bb.1: # %.preheader.lr.ph
movq %rsi, %rax
shrq $32, %rax
movq %rcx, %r10
shrq $32, %r10
sarq $32, %rcx
sarq $32, %r9
movl %esi, %edi
shlq $2, %rcx
xorl %r11d, %r11d
xorl %ebx, %ebx
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_8: # %._crit_edge29
# in Loop: Header=BB3_2 Depth=1
incq %rbx
addl %eax, %r11d
cmpq %rdi, %rbx
je .LBB3_9
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
# Child Loop BB3_6 Depth 3
testl %r10d, %r10d
jle .LBB3_8
# %bb.3: # %.lr.ph28
# in Loop: Header=BB3_2 Depth=1
movl %r11d, %edx
movq -24(%rsp), %rsi # 8-byte Reload
leaq (%rsi,%rdx,4), %r14
movq %rbx, %rdx
imulq %r9, %rdx
movq -8(%rsp), %rsi # 8-byte Reload
leaq (%rsi,%rdx,4), %r15
movq -16(%rsp), %rdx # 8-byte Reload
xorl %r13d, %r13d
jmp .LBB3_4
.p2align 4, 0x90
.LBB3_7: # %._crit_edge
# in Loop: Header=BB3_4 Depth=2
incq %r13
addq $4, %rdx
cmpq %r10, %r13
je .LBB3_8
.LBB3_4: # Parent Loop BB3_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_6 Depth 3
movl $0, (%r15,%r13,4)
testl %eax, %eax
jle .LBB3_7
# %bb.5: # %.lr.ph
# in Loop: Header=BB3_4 Depth=2
movl (%r15,%r13,4), %ebp
movq %rdx, %r12
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB3_6: # Parent Loop BB3_2 Depth=1
# Parent Loop BB3_4 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r12), %esi
imull (%r14,%r8,4), %esi
addl %esi, %ebp
movl %ebp, (%r15,%r13,4)
incq %r8
addq %rcx, %r12
cmpq %r8, %rax
jne .LBB3_6
jmp .LBB3_7
.LBB3_9: # %._crit_edge31
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z17mult_matrices_cpuPi4dim2S_S0_S_S0_, .Lfunc_end3-_Z17mult_matrices_cpuPi4dim2S_S0_S_S0_
.cfi_endproc
# -- End function
.globl _Z10create_mat4dim2i # -- Begin function _Z10create_mat4dim2i
.p2align 4, 0x90
.type _Z10create_mat4dim2i,@function
_Z10create_mat4dim2i: # @_Z10create_mat4dim2i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %ebx
movq %rdi, %r14
movq %rdi, %r15
shrq $32, %r15
movl %r15d, %eax
imull %r14d, %eax
movslq %eax, %rdi
shlq $2, %rdi
callq malloc
testl %r14d, %r14d
jle .LBB4_6
# %bb.1: # %.preheader.lr.ph
movl %r14d, %ecx
movl %ebx, %edx
imull %r15d, %edx
xorl %esi, %esi
movl %ebx, %edi
xorl %r8d, %r8d
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_5: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
incq %r8
addl %edx, %edi
addl %r15d, %esi
cmpq %rcx, %r8
je .LBB4_6
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_4 Depth 2
testl %r15d, %r15d
jle .LBB4_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB4_2 Depth=1
movl %esi, %r9d
leaq (%rax,%r9,4), %r9
movl %edi, %r10d
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB4_4: # Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movl %r10d, (%r9,%r11,4)
incq %r11
addl %ebx, %r10d
cmpq %r11, %r15
jne .LBB4_4
jmp .LBB4_5
.LBB4_6: # %._crit_edge19
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z10create_mat4dim2i, .Lfunc_end4-_Z10create_mat4dim2i
.cfi_endproc
# -- End function
.globl _Z9print_matPKcPi4dim2 # -- Begin function _Z9print_matPKcPi4dim2
.p2align 4, 0x90
.type _Z9print_matPKcPi4dim2,@function
_Z9print_matPKcPi4dim2: # @_Z9print_matPKcPi4dim2
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %r15
movq %rsi, 8(%rsp) # 8-byte Spill
movq %rdi, %rsi
movq %rdx, %r14
shrq $32, %r14
movl $.L.str, %edi
movl %r14d, %ecx
xorl %eax, %eax
callq printf
testl %r15d, %r15d
jle .LBB5_8
# %bb.1: # %.preheader.lr.ph
leal -1(%r14), %r12d
movl %r15d, %eax
movq %rax, 16(%rsp) # 8-byte Spill
xorl %ebp, %ebp
xorl %r13d, %r13d
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_7: # %._crit_edge
# in Loop: Header=BB5_2 Depth=1
incq %r13
addl %r14d, %ebp
cmpq 16(%rsp), %r13 # 8-byte Folded Reload
je .LBB5_8
.LBB5_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_4 Depth 2
testl %r14d, %r14d
jle .LBB5_7
# %bb.3: # %.lr.ph
# in Loop: Header=BB5_2 Depth=1
movl %ebp, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbx
xorl %r15d, %r15d
jmp .LBB5_4
.p2align 4, 0x90
.LBB5_6: # in Loop: Header=BB5_4 Depth=2
incq %r15
cmpq %r15, %r14
je .LBB5_7
.LBB5_4: # Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
cmpq %r15, %r12
jne .LBB5_6
# %bb.5: # in Loop: Header=BB5_4 Depth=2
movl $10, %edi
callq putchar@PLT
jmp .LBB5_6
.LBB5_8: # %._crit_edge17
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z9print_matPKcPi4dim2, .Lfunc_end5-_Z9print_matPKcPi4dim2
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $96, %edi
callq malloc
movq %rax, %rbx
movl $1, %eax
xorl %ecx, %ecx
movq %rbx, %rdx
.p2align 4, 0x90
.LBB6_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB6_2 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB6_2: # Parent Loop BB6_1 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rax,%rsi), %edi
movl %edi, (%rdx,%rsi,4)
incq %rsi
cmpq $4, %rsi
jne .LBB6_2
# %bb.3: # %._crit_edge.i
# in Loop: Header=BB6_1 Depth=1
incq %rcx
addq $16, %rdx
addq $4, %rax
cmpq $6, %rcx
jne .LBB6_1
# %bb.4: # %_Z10create_mat4dim2i.exit
movl $.L.str, %edi
movl $.L.str.3, %esi
movl $6, %edx
movl $4, %ecx
xorl %eax, %eax
callq printf
movq %rbx, %r14
xorl %r15d, %r15d
jmp .LBB6_5
.p2align 4, 0x90
.LBB6_9: # %._crit_edge.i114
# in Loop: Header=BB6_5 Depth=1
incq %r15
addq $16, %r14
cmpq $6, %r15
je .LBB6_10
.LBB6_5: # %.preheader.i110
# =>This Loop Header: Depth=1
# Child Loop BB6_6 Depth 2
xorl %r12d, %r12d
jmp .LBB6_6
.p2align 4, 0x90
.LBB6_8: # in Loop: Header=BB6_6 Depth=2
incq %r12
cmpq $4, %r12
je .LBB6_9
.LBB6_6: # Parent Loop BB6_5 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r12,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
cmpq $3, %r12
jne .LBB6_8
# %bb.7: # in Loop: Header=BB6_6 Depth=2
movl $10, %edi
callq putchar@PLT
jmp .LBB6_8
.LBB6_10: # %_Z9print_matPKcPi4dim2.exit
movl $128, %edi
callq malloc
movq %rax, %r14
movl $2, %eax
xorl %ecx, %ecx
movq %r14, %rdx
.p2align 4, 0x90
.LBB6_11: # %.preheader.i115
# =>This Loop Header: Depth=1
# Child Loop BB6_12 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB6_12: # Parent Loop BB6_11 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rax,%rsi), %edi
movl %edi, (%rdx,%rsi,2)
addq $2, %rsi
cmpq $16, %rsi
jne .LBB6_12
# %bb.13: # %._crit_edge.i120
# in Loop: Header=BB6_11 Depth=1
incq %rcx
addq $32, %rdx
addq $16, %rax
cmpq $4, %rcx
jne .LBB6_11
# %bb.14: # %_Z10create_mat4dim2i.exit123
movl $.L.str, %edi
movl $.L.str.4, %esi
movl $4, %edx
movl $8, %ecx
xorl %eax, %eax
callq printf
movq %r14, %r15
xorl %r12d, %r12d
jmp .LBB6_15
.p2align 4, 0x90
.LBB6_19: # %._crit_edge.i129
# in Loop: Header=BB6_15 Depth=1
incq %r12
addq $32, %r15
cmpq $4, %r12
je .LBB6_20
.LBB6_15: # %.preheader.i124
# =>This Loop Header: Depth=1
# Child Loop BB6_16 Depth 2
xorl %r13d, %r13d
jmp .LBB6_16
.p2align 4, 0x90
.LBB6_18: # in Loop: Header=BB6_16 Depth=2
incq %r13
cmpq $8, %r13
je .LBB6_19
.LBB6_16: # Parent Loop BB6_15 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r15,%r13,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
cmpq $7, %r13
jne .LBB6_18
# %bb.17: # in Loop: Header=BB6_16 Depth=2
movl $10, %edi
callq putchar@PLT
jmp .LBB6_18
.LBB6_20: # %_Z9print_matPKcPi4dim2.exit133
movl $192, %edi
callq malloc
movq %rax, %r15
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
movups %xmm0, 16(%rax)
movups %xmm0, 32(%rax)
movups %xmm0, 48(%rax)
movups %xmm0, 64(%rax)
movups %xmm0, 80(%rax)
movups %xmm0, 96(%rax)
movups %xmm0, 112(%rax)
movups %xmm0, 128(%rax)
movups %xmm0, 144(%rax)
movups %xmm0, 160(%rax)
movups %xmm0, 176(%rax)
movl $.L.str, %edi
movl $.L.str.6, %esi
movl $6, %edx
movl $8, %ecx
xorl %eax, %eax
callq printf
movq %r15, %r12
xorl %r13d, %r13d
jmp .LBB6_21
.p2align 4, 0x90
.LBB6_25: # %._crit_edge.i148
# in Loop: Header=BB6_21 Depth=1
incq %r13
addq $32, %r12
cmpq $6, %r13
je .LBB6_26
.LBB6_21: # %.preheader.i143
# =>This Loop Header: Depth=1
# Child Loop BB6_22 Depth 2
xorl %ebp, %ebp
jmp .LBB6_22
.p2align 4, 0x90
.LBB6_24: # in Loop: Header=BB6_22 Depth=2
incq %rbp
cmpq $8, %rbp
je .LBB6_25
.LBB6_22: # Parent Loop BB6_21 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r12,%rbp,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
cmpq $7, %rbp
jne .LBB6_24
# %bb.23: # in Loop: Header=BB6_22 Depth=2
movl $10, %edi
callq putchar@PLT
jmp .LBB6_24
.LBB6_26: # %_Z9print_matPKcPi4dim2.exit152
movabsq $17179869190, %rsi # imm = 0x400000006
movabsq $34359738374, %r9 # imm = 0x800000006
movq %rbx, %rdi
movq %r14, %rdx
movq %r15, %r8
callq _Z17mult_matrices_gpuPi4dim2S_S0_S_S0_
movl $.L.str, %edi
movl $.L.str.7, %esi
movl $6, %edx
movl $8, %ecx
xorl %eax, %eax
callq printf
movq %r15, %r12
xorl %r13d, %r13d
jmp .LBB6_27
.p2align 4, 0x90
.LBB6_31: # %._crit_edge.i158
# in Loop: Header=BB6_27 Depth=1
incq %r13
addq $32, %r12
cmpq $6, %r13
je .LBB6_32
.LBB6_27: # %.preheader.i153
# =>This Loop Header: Depth=1
# Child Loop BB6_28 Depth 2
xorl %ebp, %ebp
jmp .LBB6_28
.p2align 4, 0x90
.LBB6_30: # in Loop: Header=BB6_28 Depth=2
incq %rbp
cmpq $8, %rbp
je .LBB6_31
.LBB6_28: # Parent Loop BB6_27 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r12,%rbp,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
cmpq $7, %rbp
jne .LBB6_30
# %bb.29: # in Loop: Header=BB6_28 Depth=2
movl $10, %edi
callq putchar@PLT
jmp .LBB6_30
.LBB6_32: # %.preheader.i163.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB6_33: # %.preheader.i163
# =>This Loop Header: Depth=1
# Child Loop BB6_34 Depth 2
# Child Loop BB6_35 Depth 3
movq %rax, %rcx
shlq $5, %rcx
addq %r15, %rcx
movq %r14, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB6_34: # Parent Loop BB6_33 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_35 Depth 3
movl $0, (%rcx,%rsi,4)
xorl %edi, %edi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB6_35: # Parent Loop BB6_33 Depth=1
# Parent Loop BB6_34 Depth=2
# => This Inner Loop Header: Depth=3
movl (%rdx,%rdi,8), %r9d
imull (%rbx,%rdi), %r9d
addl %r9d, %r8d
addq $4, %rdi
cmpq $16, %rdi
jne .LBB6_35
# %bb.36: # %._crit_edge.i167
# in Loop: Header=BB6_34 Depth=2
movl %r8d, (%rcx,%rsi,4)
incq %rsi
addq $4, %rdx
cmpq $8, %rsi
jne .LBB6_34
# %bb.37: # %._crit_edge29.i
# in Loop: Header=BB6_33 Depth=1
incq %rax
addq $16, %rbx
cmpq $6, %rax
jne .LBB6_33
# %bb.38: # %_Z17mult_matrices_cpuPi4dim2S_S0_S_S0_.exit
movl $.L.str, %edi
movl $.L.str.7, %esi
movl $6, %edx
movl $8, %ecx
xorl %eax, %eax
callq printf
xorl %ebx, %ebx
jmp .LBB6_39
.p2align 4, 0x90
.LBB6_43: # %._crit_edge.i173
# in Loop: Header=BB6_39 Depth=1
incq %rbx
addq $32, %r15
cmpq $6, %rbx
je .LBB6_44
.LBB6_39: # %.preheader.i168
# =>This Loop Header: Depth=1
# Child Loop BB6_40 Depth 2
xorl %r14d, %r14d
jmp .LBB6_40
.p2align 4, 0x90
.LBB6_42: # in Loop: Header=BB6_40 Depth=2
incq %r14
cmpq $8, %r14
je .LBB6_43
.LBB6_40: # Parent Loop BB6_39 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r15,%r14,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
cmpq $7, %r14
jne .LBB6_42
# %bb.41: # in Loop: Header=BB6_40 Depth=2
movl $10, %edi
callq putchar@PLT
jmp .LBB6_42
.LBB6_44: # %_Z9print_matPKcPi4dim2.exit177
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20mult_matrices_kernelPiS_S_4dim2i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20mult_matrices_kernelPiS_S_4dim2i,@object # @_Z20mult_matrices_kernelPiS_S_4dim2i
.section .rodata,"a",@progbits
.globl _Z20mult_matrices_kernelPiS_S_4dim2i
.p2align 3, 0x0
_Z20mult_matrices_kernelPiS_S_4dim2i:
.quad _Z35__device_stub__mult_matrices_kernelPiS_S_4dim2i
.size _Z20mult_matrices_kernelPiS_S_4dim2i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s (%d, %d):\n"
.size .L.str, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\t%d "
.size .L.str.1, 5
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "First matrix"
.size .L.str.3, 13
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Second matrix"
.size .L.str.4, 14
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Third matrix"
.size .L.str.6, 13
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Result matrix"
.size .L.str.7, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20mult_matrices_kernelPiS_S_4dim2i"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__mult_matrices_kernelPiS_S_4dim2i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20mult_matrices_kernelPiS_S_4dim2i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b57a9_00000000-6_demo.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13cuda_copy_matPi4dim2
.type _Z13cuda_copy_matPi4dim2, @function
_Z13cuda_copy_matPi4dim2:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsi, %rbx
shrq $32, %rbx
imull %esi, %ebx
movslq %ebx, %rbx
salq $2, %rbx
movq %rsp, %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movq (%rsp), %rax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L6
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z13cuda_copy_matPi4dim2, .-_Z13cuda_copy_matPi4dim2
.globl _Z17mult_matrices_cpuPi4dim2S_S0_S_S0_
.type _Z17mult_matrices_cpuPi4dim2S_S0_S_S0_, @function
_Z17mult_matrices_cpuPi4dim2S_S0_S_S0_:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rsi, %rax
movq %rdx, -24(%rsp)
movq %r8, -16(%rsp)
movl %esi, %r15d
sarq $32, %rsi
sarq $32, %rcx
testl %eax, %eax
jle .L7
movq %rdi, %r14
movq %r9, %rdx
movl %esi, %ebp
movq %rcx, %r8
movl %ecx, %ebx
shrq $32, %rdx
movl %esi, -32(%rsp)
salq $2, %r8
movl $0, %r13d
movl $0, %esi
movl $0, %ecx
movslq %ebp, %rax
movq %rax, -8(%rsp)
movl %r15d, -28(%rsp)
movl %edx, %edi
movq %r14, %rdx
jmp .L9
.L13:
movslq %esi, %rax
movq -16(%rsp), %r15
leaq (%r15,%rax,4), %r11
movq -24(%rsp), %r14
movslq %r13d, %rax
leaq (%rdx,%rax,4), %r15
movq -8(%rsp), %r9
addq %r9, %rax
leaq (%rdx,%rax,4), %r10
movl $0, %r12d
movl %ecx, -40(%rsp)
movl %esi, -36(%rsp)
.L12:
movq %r11, %r9
movl $0, (%r11)
testl %ebp, %ebp
jle .L10
movq %r14, %rsi
movq %r15, %rax
.L11:
movl (%rax), %ecx
imull (%rsi), %ecx
addl %ecx, (%r9)
addq $4, %rax
addq %r8, %rsi
cmpq %r10, %rax
jne .L11
.L10:
addl $1, %r12d
addq $4, %r11
addq $4, %r14
cmpl %r12d, %ebx
jne .L12
movl -40(%rsp), %ecx
movl -36(%rsp), %esi
.L14:
addl $1, %ecx
addl %edi, %esi
movl -32(%rsp), %eax
addl %eax, %r13d
movl -28(%rsp), %eax
cmpl %eax, %ecx
je .L7
.L9:
testl %ebx, %ebx
jg .L13
jmp .L14
.L7:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z17mult_matrices_cpuPi4dim2S_S0_S_S0_, .-_Z17mult_matrices_cpuPi4dim2S_S0_S_S0_
.globl _Z10create_mat4dim2i
.type _Z10create_mat4dim2i, @function
_Z10create_mat4dim2i:
.LFB2060:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r14
movl %esi, %ebx
movl %edi, %r12d
movq %rdi, %r13
sarq $32, %r13
movl %r13d, %edi
imull %r14d, %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r9
testl %r14d, %r14d
jle .L18
movl %r13d, %ebp
movl %r13d, %r11d
movl %r13d, %r10d
imull %ebx, %r10d
movl %ebx, %r8d
movl $0, %edi
movl $0, %esi
movslq %r13d, %r13
jmp .L20
.L22:
movslq %edi, %rdx
leaq (%r9,%rdx,4), %rax
addq %r13, %rdx
leaq (%r9,%rdx,4), %rcx
movl %r8d, %edx
.L21:
movl %edx, (%rax)
addl %ebx, %edx
addq $4, %rax
cmpq %rcx, %rax
jne .L21
.L23:
addl $1, %esi
addl %r10d, %r8d
addl %r11d, %edi
cmpl %esi, %r12d
je .L18
.L20:
testl %ebp, %ebp
jg .L22
jmp .L23
.L18:
movq %r9, %rax
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z10create_mat4dim2i, .-_Z10create_mat4dim2i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s (%d, %d):\n"
.LC1:
.string "\t%d "
.LC2:
.string "\n"
.text
.globl _Z9print_matPKcPi4dim2
.type _Z9print_matPKcPi4dim2, @function
_Z9print_matPKcPi4dim2:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rsi, 24(%rsp)
movq %rdx, %rbx
movl %edx, %ecx
movl %edx, 16(%rsp)
movq %rdx, %rbp
sarq $32, %rbp
movl %ebp, %r8d
movq %rdi, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jle .L26
movl %ebp, %r15d
movl %ebp, 20(%rsp)
movl $0, %ecx
movl $0, %eax
movslq %ebp, %r14
leaq .LC1(%rip), %r13
jmp .L28
.L29:
addq $1, %rbx
cmpq %r14, %rbx
je .L35
.L30:
movl (%r12,%rbx,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl %ebx, %ebp
jne .L29
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L29
.L35:
movl %r15d, %eax
movl 8(%rsp), %r15d
movl 12(%rsp), %ecx
.L32:
addl $1, %eax
movl 20(%rsp), %esi
addl %esi, %ecx
cmpl %eax, 16(%rsp)
je .L26
.L28:
testl %r15d, %r15d
jle .L32
movslq %ecx, %rdx
movq 24(%rsp), %rsi
leaq (%rsi,%rdx,4), %r12
movl $0, %ebx
leal -1(%r15), %ebp
movl %r15d, 8(%rsp)
movl %eax, %r15d
movl %ecx, 12(%rsp)
jmp .L30
.L26:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z9print_matPKcPi4dim2, .-_Z9print_matPKcPi4dim2
.globl _Z50__device_stub__Z20mult_matrices_kernelPiS_S_4dim2iPiS_S_R4dim2i
.type _Z50__device_stub__Z20mult_matrices_kernelPiS_S_4dim2iPiS_S_R4dim2i, @function
_Z50__device_stub__Z20mult_matrices_kernelPiS_S_4dim2iPiS_S_R4dim2i:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rcx, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L40
.L36:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L41
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20mult_matrices_kernelPiS_S_4dim2i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L36
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z50__device_stub__Z20mult_matrices_kernelPiS_S_4dim2iPiS_S_R4dim2i, .-_Z50__device_stub__Z20mult_matrices_kernelPiS_S_4dim2iPiS_S_R4dim2i
.globl _Z20mult_matrices_kernelPiS_S_4dim2i
.type _Z20mult_matrices_kernelPiS_S_4dim2i, @function
_Z20mult_matrices_kernelPiS_S_4dim2i:
.LFB2088:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rcx, 8(%rsp)
leaq 8(%rsp), %rcx
call _Z50__device_stub__Z20mult_matrices_kernelPiS_S_4dim2iPiS_S_R4dim2i
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z20mult_matrices_kernelPiS_S_4dim2i, .-_Z20mult_matrices_kernelPiS_S_4dim2i
.globl _Z17mult_matrices_gpuPi4dim2S_S0_S_S0_
.type _Z17mult_matrices_gpuPi4dim2S_S0_S_S0_, @function
_Z17mult_matrices_gpuPi4dim2S_S0_S_S0_:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rsi, %r15
movq %rdx, %rbp
movq %r8, %r12
movq %r9, %rbx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
call _Z13cuda_copy_matPi4dim2
movq %rax, %r14
movq %rbx, %rsi
movq %rbp, %rdi
call _Z13cuda_copy_matPi4dim2
movq %rax, %r13
movq %rbx, %rsi
movq %r12, %rdi
call _Z13cuda_copy_matPi4dim2
movq %rax, %rbp
movl $3, 16(%rsp)
movl $2, 20(%rsp)
movl $2, 28(%rsp)
movl $2, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L48
.L45:
movq %rbx, %rax
sarq $32, %rax
imull %eax, %ebx
movslq %ebx, %rdx
salq $2, %rdx
movl $2, %ecx
movq %rbp, %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq %r14, %rdi
call cudaFree@PLT
movq %r13, %rdi
call cudaFree@PLT
movq %rbp, %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L49
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
movq %rbx, 8(%rsp)
leaq 8(%rsp), %rcx
shrq $32, %r15
movq %r15, %r8
movq %rbp, %rdx
movq %r13, %rsi
movq %r14, %rdi
call _Z50__device_stub__Z20mult_matrices_kernelPiS_S_4dim2iPiS_S_R4dim2i
jmp .L45
.L49:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z17mult_matrices_gpuPi4dim2S_S0_S_S0_, .-_Z17mult_matrices_gpuPi4dim2S_S0_S_S0_
.section .rodata.str1.1
.LC3:
.string "First matrix"
.LC4:
.string "Second matrix"
.LC5:
.string "Third matrix"
.LC6:
.string "Result matrix"
.text
.globl main
.type main, @function
main:
.LFB2062:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movabsq $17179869190, %r14
movl $1, %esi
movq %r14, %rdi
call _Z10create_mat4dim2i
movq %rax, %r12
movq %r14, %rdx
movq %rax, %rsi
leaq .LC3(%rip), %rdi
call _Z9print_matPKcPi4dim2
movabsq $34359738368, %rbx
movq %rbx, %r15
orq $4, %r15
movl $2, %esi
movq %r15, %rdi
call _Z10create_mat4dim2i
movq %rax, %r13
movq %r15, %rdx
movq %rax, %rsi
leaq .LC4(%rip), %rdi
call _Z9print_matPKcPi4dim2
orq $6, %rbx
movl $0, %esi
movq %rbx, %rdi
call _Z10create_mat4dim2i
movq %rax, %rbp
movq %rbx, %rdx
movq %rax, %rsi
leaq .LC5(%rip), %rdi
call _Z9print_matPKcPi4dim2
movq %rbx, %r9
movq %rbp, %r8
movq %r15, %rcx
movq %r13, %rdx
movq %r14, %rsi
movq %r12, %rdi
call _Z17mult_matrices_gpuPi4dim2S_S0_S_S0_
movq %rbx, %rdx
movq %rbp, %rsi
leaq .LC6(%rip), %rdi
call _Z9print_matPKcPi4dim2
movq %rbx, %r9
movq %rbp, %r8
movq %r15, %rcx
movq %r13, %rdx
movq %r14, %rsi
movq %r12, %rdi
call _Z17mult_matrices_cpuPi4dim2S_S0_S_S0_
movq %rbx, %rdx
movq %rbp, %rsi
leaq .LC6(%rip), %rdi
call _Z9print_matPKcPi4dim2
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "_Z20mult_matrices_kernelPiS_S_4dim2i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z20mult_matrices_kernelPiS_S_4dim2i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "demo.hip"
.globl _Z35__device_stub__mult_matrices_kernelPiS_S_4dim2i # -- Begin function _Z35__device_stub__mult_matrices_kernelPiS_S_4dim2i
.p2align 4, 0x90
.type _Z35__device_stub__mult_matrices_kernelPiS_S_4dim2i,@function
_Z35__device_stub__mult_matrices_kernelPiS_S_4dim2i: # @_Z35__device_stub__mult_matrices_kernelPiS_S_4dim2i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rcx, 88(%rsp)
movq %rdi, 80(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20mult_matrices_kernelPiS_S_4dim2i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z35__device_stub__mult_matrices_kernelPiS_S_4dim2i, .Lfunc_end0-_Z35__device_stub__mult_matrices_kernelPiS_S_4dim2i
.cfi_endproc
# -- End function
.globl _Z13cuda_copy_matPi4dim2 # -- Begin function _Z13cuda_copy_matPi4dim2
.p2align 4, 0x90
.type _Z13cuda_copy_matPi4dim2,@function
_Z13cuda_copy_matPi4dim2: # @_Z13cuda_copy_matPi4dim2
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
movq %rsi, %rax
shrq $32, %rax
imull %esi, %eax
movslq %eax, %r14
shlq $2, %r14
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
movq (%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z13cuda_copy_matPi4dim2, .Lfunc_end1-_Z13cuda_copy_matPi4dim2
.cfi_endproc
# -- End function
.globl _Z17mult_matrices_gpuPi4dim2S_S0_S_S0_ # -- Begin function _Z17mult_matrices_gpuPi4dim2S_S0_S_S0_
.p2align 4, 0x90
.type _Z17mult_matrices_gpuPi4dim2S_S0_S_S0_,@function
_Z17mult_matrices_gpuPi4dim2S_S0_S_S0_: # @_Z17mult_matrices_gpuPi4dim2S_S0_S_S0_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %r14
movq %r8, %r12
movq %rdx, (%rsp) # 8-byte Spill
movq %rdi, %r15
movq %rsi, %rbx
shrq $32, %rbx
movl %ebx, %eax
imull %esi, %eax
movslq %eax, %r13
shlq $2, %r13
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rax
movq %rax, 64(%rsp) # 8-byte Spill
movq %r14, %rbp
shrq $32, %rbp
movl %ebp, %eax
imull %r14d, %eax
movslq %eax, %r13
shlq $2, %r13
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq (%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %r15
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r12, (%rsp) # 8-byte Spill
movq %r12, %rsi
movq 64(%rsp), %r12 # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %r13
movabsq $8589934594, %rdx # imm = 0x200000002
leaq 1(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq %r14, 144(%rsp)
movq %r12, 136(%rsp)
movq %r15, 128(%rsp)
movq %r13, 120(%rsp)
movl %ebx, 12(%rsp)
leaq 136(%rsp), %rax
movq %rax, 16(%rsp)
leaq 128(%rsp), %rax
movq %rax, 24(%rsp)
leaq 120(%rsp), %rax
movq %rax, 32(%rsp)
leaq 144(%rsp), %rax
movq %rax, 40(%rsp)
leaq 12(%rsp), %rax
movq %rax, 48(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z20mult_matrices_kernelPiS_S_4dim2i, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
imull %ebp, %r14d
movslq %r14d, %rdx
shlq $2, %rdx
movq (%rsp), %rdi # 8-byte Reload
movq %r13, %rsi
movl $2, %ecx
callq hipMemcpy
movq %r12, %rdi
callq hipFree
movq %r15, %rdi
callq hipFree
movq %r13, %rdi
callq hipFree
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z17mult_matrices_gpuPi4dim2S_S0_S_S0_, .Lfunc_end2-_Z17mult_matrices_gpuPi4dim2S_S0_S_S0_
.cfi_endproc
# -- End function
.globl _Z17mult_matrices_cpuPi4dim2S_S0_S_S0_ # -- Begin function _Z17mult_matrices_cpuPi4dim2S_S0_S_S0_
.p2align 4, 0x90
.type _Z17mult_matrices_cpuPi4dim2S_S0_S_S0_,@function
_Z17mult_matrices_cpuPi4dim2S_S0_S_S0_: # @_Z17mult_matrices_cpuPi4dim2S_S0_S_S0_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, -8(%rsp) # 8-byte Spill
movq %rdx, -16(%rsp) # 8-byte Spill
movq %rdi, -24(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB3_9
# %bb.1: # %.preheader.lr.ph
movq %rsi, %rax
shrq $32, %rax
movq %rcx, %r10
shrq $32, %r10
sarq $32, %rcx
sarq $32, %r9
movl %esi, %edi
shlq $2, %rcx
xorl %r11d, %r11d
xorl %ebx, %ebx
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_8: # %._crit_edge29
# in Loop: Header=BB3_2 Depth=1
incq %rbx
addl %eax, %r11d
cmpq %rdi, %rbx
je .LBB3_9
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
# Child Loop BB3_6 Depth 3
testl %r10d, %r10d
jle .LBB3_8
# %bb.3: # %.lr.ph28
# in Loop: Header=BB3_2 Depth=1
movl %r11d, %edx
movq -24(%rsp), %rsi # 8-byte Reload
leaq (%rsi,%rdx,4), %r14
movq %rbx, %rdx
imulq %r9, %rdx
movq -8(%rsp), %rsi # 8-byte Reload
leaq (%rsi,%rdx,4), %r15
movq -16(%rsp), %rdx # 8-byte Reload
xorl %r13d, %r13d
jmp .LBB3_4
.p2align 4, 0x90
.LBB3_7: # %._crit_edge
# in Loop: Header=BB3_4 Depth=2
incq %r13
addq $4, %rdx
cmpq %r10, %r13
je .LBB3_8
.LBB3_4: # Parent Loop BB3_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_6 Depth 3
movl $0, (%r15,%r13,4)
testl %eax, %eax
jle .LBB3_7
# %bb.5: # %.lr.ph
# in Loop: Header=BB3_4 Depth=2
movl (%r15,%r13,4), %ebp
movq %rdx, %r12
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB3_6: # Parent Loop BB3_2 Depth=1
# Parent Loop BB3_4 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r12), %esi
imull (%r14,%r8,4), %esi
addl %esi, %ebp
movl %ebp, (%r15,%r13,4)
incq %r8
addq %rcx, %r12
cmpq %r8, %rax
jne .LBB3_6
jmp .LBB3_7
.LBB3_9: # %._crit_edge31
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z17mult_matrices_cpuPi4dim2S_S0_S_S0_, .Lfunc_end3-_Z17mult_matrices_cpuPi4dim2S_S0_S_S0_
.cfi_endproc
# -- End function
.globl _Z10create_mat4dim2i # -- Begin function _Z10create_mat4dim2i
.p2align 4, 0x90
.type _Z10create_mat4dim2i,@function
_Z10create_mat4dim2i: # @_Z10create_mat4dim2i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %ebx
movq %rdi, %r14
movq %rdi, %r15
shrq $32, %r15
movl %r15d, %eax
imull %r14d, %eax
movslq %eax, %rdi
shlq $2, %rdi
callq malloc
testl %r14d, %r14d
jle .LBB4_6
# %bb.1: # %.preheader.lr.ph
movl %r14d, %ecx
movl %ebx, %edx
imull %r15d, %edx
xorl %esi, %esi
movl %ebx, %edi
xorl %r8d, %r8d
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_5: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
incq %r8
addl %edx, %edi
addl %r15d, %esi
cmpq %rcx, %r8
je .LBB4_6
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_4 Depth 2
testl %r15d, %r15d
jle .LBB4_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB4_2 Depth=1
movl %esi, %r9d
leaq (%rax,%r9,4), %r9
movl %edi, %r10d
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB4_4: # Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movl %r10d, (%r9,%r11,4)
incq %r11
addl %ebx, %r10d
cmpq %r11, %r15
jne .LBB4_4
jmp .LBB4_5
.LBB4_6: # %._crit_edge19
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z10create_mat4dim2i, .Lfunc_end4-_Z10create_mat4dim2i
.cfi_endproc
# -- End function
.globl _Z9print_matPKcPi4dim2 # -- Begin function _Z9print_matPKcPi4dim2
.p2align 4, 0x90
.type _Z9print_matPKcPi4dim2,@function
_Z9print_matPKcPi4dim2: # @_Z9print_matPKcPi4dim2
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %r15
movq %rsi, 8(%rsp) # 8-byte Spill
movq %rdi, %rsi
movq %rdx, %r14
shrq $32, %r14
movl $.L.str, %edi
movl %r14d, %ecx
xorl %eax, %eax
callq printf
testl %r15d, %r15d
jle .LBB5_8
# %bb.1: # %.preheader.lr.ph
leal -1(%r14), %r12d
movl %r15d, %eax
movq %rax, 16(%rsp) # 8-byte Spill
xorl %ebp, %ebp
xorl %r13d, %r13d
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_7: # %._crit_edge
# in Loop: Header=BB5_2 Depth=1
incq %r13
addl %r14d, %ebp
cmpq 16(%rsp), %r13 # 8-byte Folded Reload
je .LBB5_8
.LBB5_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_4 Depth 2
testl %r14d, %r14d
jle .LBB5_7
# %bb.3: # %.lr.ph
# in Loop: Header=BB5_2 Depth=1
movl %ebp, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbx
xorl %r15d, %r15d
jmp .LBB5_4
.p2align 4, 0x90
.LBB5_6: # in Loop: Header=BB5_4 Depth=2
incq %r15
cmpq %r15, %r14
je .LBB5_7
.LBB5_4: # Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
cmpq %r15, %r12
jne .LBB5_6
# %bb.5: # in Loop: Header=BB5_4 Depth=2
movl $10, %edi
callq putchar@PLT
jmp .LBB5_6
.LBB5_8: # %._crit_edge17
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z9print_matPKcPi4dim2, .Lfunc_end5-_Z9print_matPKcPi4dim2
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $96, %edi
callq malloc
movq %rax, %rbx
movl $1, %eax
xorl %ecx, %ecx
movq %rbx, %rdx
.p2align 4, 0x90
.LBB6_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB6_2 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB6_2: # Parent Loop BB6_1 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rax,%rsi), %edi
movl %edi, (%rdx,%rsi,4)
incq %rsi
cmpq $4, %rsi
jne .LBB6_2
# %bb.3: # %._crit_edge.i
# in Loop: Header=BB6_1 Depth=1
incq %rcx
addq $16, %rdx
addq $4, %rax
cmpq $6, %rcx
jne .LBB6_1
# %bb.4: # %_Z10create_mat4dim2i.exit
movl $.L.str, %edi
movl $.L.str.3, %esi
movl $6, %edx
movl $4, %ecx
xorl %eax, %eax
callq printf
movq %rbx, %r14
xorl %r15d, %r15d
jmp .LBB6_5
.p2align 4, 0x90
.LBB6_9: # %._crit_edge.i114
# in Loop: Header=BB6_5 Depth=1
incq %r15
addq $16, %r14
cmpq $6, %r15
je .LBB6_10
.LBB6_5: # %.preheader.i110
# =>This Loop Header: Depth=1
# Child Loop BB6_6 Depth 2
xorl %r12d, %r12d
jmp .LBB6_6
.p2align 4, 0x90
.LBB6_8: # in Loop: Header=BB6_6 Depth=2
incq %r12
cmpq $4, %r12
je .LBB6_9
.LBB6_6: # Parent Loop BB6_5 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r12,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
cmpq $3, %r12
jne .LBB6_8
# %bb.7: # in Loop: Header=BB6_6 Depth=2
movl $10, %edi
callq putchar@PLT
jmp .LBB6_8
.LBB6_10: # %_Z9print_matPKcPi4dim2.exit
movl $128, %edi
callq malloc
movq %rax, %r14
movl $2, %eax
xorl %ecx, %ecx
movq %r14, %rdx
.p2align 4, 0x90
.LBB6_11: # %.preheader.i115
# =>This Loop Header: Depth=1
# Child Loop BB6_12 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB6_12: # Parent Loop BB6_11 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rax,%rsi), %edi
movl %edi, (%rdx,%rsi,2)
addq $2, %rsi
cmpq $16, %rsi
jne .LBB6_12
# %bb.13: # %._crit_edge.i120
# in Loop: Header=BB6_11 Depth=1
incq %rcx
addq $32, %rdx
addq $16, %rax
cmpq $4, %rcx
jne .LBB6_11
# %bb.14: # %_Z10create_mat4dim2i.exit123
movl $.L.str, %edi
movl $.L.str.4, %esi
movl $4, %edx
movl $8, %ecx
xorl %eax, %eax
callq printf
movq %r14, %r15
xorl %r12d, %r12d
jmp .LBB6_15
.p2align 4, 0x90
.LBB6_19: # %._crit_edge.i129
# in Loop: Header=BB6_15 Depth=1
incq %r12
addq $32, %r15
cmpq $4, %r12
je .LBB6_20
.LBB6_15: # %.preheader.i124
# =>This Loop Header: Depth=1
# Child Loop BB6_16 Depth 2
xorl %r13d, %r13d
jmp .LBB6_16
.p2align 4, 0x90
.LBB6_18: # in Loop: Header=BB6_16 Depth=2
incq %r13
cmpq $8, %r13
je .LBB6_19
.LBB6_16: # Parent Loop BB6_15 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r15,%r13,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
cmpq $7, %r13
jne .LBB6_18
# %bb.17: # in Loop: Header=BB6_16 Depth=2
movl $10, %edi
callq putchar@PLT
jmp .LBB6_18
.LBB6_20: # %_Z9print_matPKcPi4dim2.exit133
movl $192, %edi
callq malloc
movq %rax, %r15
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
movups %xmm0, 16(%rax)
movups %xmm0, 32(%rax)
movups %xmm0, 48(%rax)
movups %xmm0, 64(%rax)
movups %xmm0, 80(%rax)
movups %xmm0, 96(%rax)
movups %xmm0, 112(%rax)
movups %xmm0, 128(%rax)
movups %xmm0, 144(%rax)
movups %xmm0, 160(%rax)
movups %xmm0, 176(%rax)
movl $.L.str, %edi
movl $.L.str.6, %esi
movl $6, %edx
movl $8, %ecx
xorl %eax, %eax
callq printf
movq %r15, %r12
xorl %r13d, %r13d
jmp .LBB6_21
.p2align 4, 0x90
.LBB6_25: # %._crit_edge.i148
# in Loop: Header=BB6_21 Depth=1
incq %r13
addq $32, %r12
cmpq $6, %r13
je .LBB6_26
.LBB6_21: # %.preheader.i143
# =>This Loop Header: Depth=1
# Child Loop BB6_22 Depth 2
xorl %ebp, %ebp
jmp .LBB6_22
.p2align 4, 0x90
.LBB6_24: # in Loop: Header=BB6_22 Depth=2
incq %rbp
cmpq $8, %rbp
je .LBB6_25
.LBB6_22: # Parent Loop BB6_21 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r12,%rbp,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
cmpq $7, %rbp
jne .LBB6_24
# %bb.23: # in Loop: Header=BB6_22 Depth=2
movl $10, %edi
callq putchar@PLT
jmp .LBB6_24
.LBB6_26: # %_Z9print_matPKcPi4dim2.exit152
movabsq $17179869190, %rsi # imm = 0x400000006
movabsq $34359738374, %r9 # imm = 0x800000006
movq %rbx, %rdi
movq %r14, %rdx
movq %r15, %r8
callq _Z17mult_matrices_gpuPi4dim2S_S0_S_S0_
movl $.L.str, %edi
movl $.L.str.7, %esi
movl $6, %edx
movl $8, %ecx
xorl %eax, %eax
callq printf
movq %r15, %r12
xorl %r13d, %r13d
jmp .LBB6_27
.p2align 4, 0x90
.LBB6_31: # %._crit_edge.i158
# in Loop: Header=BB6_27 Depth=1
incq %r13
addq $32, %r12
cmpq $6, %r13
je .LBB6_32
.LBB6_27: # %.preheader.i153
# =>This Loop Header: Depth=1
# Child Loop BB6_28 Depth 2
xorl %ebp, %ebp
jmp .LBB6_28
.p2align 4, 0x90
.LBB6_30: # in Loop: Header=BB6_28 Depth=2
incq %rbp
cmpq $8, %rbp
je .LBB6_31
.LBB6_28: # Parent Loop BB6_27 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r12,%rbp,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
cmpq $7, %rbp
jne .LBB6_30
# %bb.29: # in Loop: Header=BB6_28 Depth=2
movl $10, %edi
callq putchar@PLT
jmp .LBB6_30
.LBB6_32: # %.preheader.i163.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB6_33: # %.preheader.i163
# =>This Loop Header: Depth=1
# Child Loop BB6_34 Depth 2
# Child Loop BB6_35 Depth 3
movq %rax, %rcx
shlq $5, %rcx
addq %r15, %rcx
movq %r14, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB6_34: # Parent Loop BB6_33 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_35 Depth 3
movl $0, (%rcx,%rsi,4)
xorl %edi, %edi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB6_35: # Parent Loop BB6_33 Depth=1
# Parent Loop BB6_34 Depth=2
# => This Inner Loop Header: Depth=3
movl (%rdx,%rdi,8), %r9d
imull (%rbx,%rdi), %r9d
addl %r9d, %r8d
addq $4, %rdi
cmpq $16, %rdi
jne .LBB6_35
# %bb.36: # %._crit_edge.i167
# in Loop: Header=BB6_34 Depth=2
movl %r8d, (%rcx,%rsi,4)
incq %rsi
addq $4, %rdx
cmpq $8, %rsi
jne .LBB6_34
# %bb.37: # %._crit_edge29.i
# in Loop: Header=BB6_33 Depth=1
incq %rax
addq $16, %rbx
cmpq $6, %rax
jne .LBB6_33
# %bb.38: # %_Z17mult_matrices_cpuPi4dim2S_S0_S_S0_.exit
movl $.L.str, %edi
movl $.L.str.7, %esi
movl $6, %edx
movl $8, %ecx
xorl %eax, %eax
callq printf
xorl %ebx, %ebx
jmp .LBB6_39
.p2align 4, 0x90
.LBB6_43: # %._crit_edge.i173
# in Loop: Header=BB6_39 Depth=1
incq %rbx
addq $32, %r15
cmpq $6, %rbx
je .LBB6_44
.LBB6_39: # %.preheader.i168
# =>This Loop Header: Depth=1
# Child Loop BB6_40 Depth 2
xorl %r14d, %r14d
jmp .LBB6_40
.p2align 4, 0x90
.LBB6_42: # in Loop: Header=BB6_40 Depth=2
incq %r14
cmpq $8, %r14
je .LBB6_43
.LBB6_40: # Parent Loop BB6_39 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r15,%r14,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
cmpq $7, %r14
jne .LBB6_42
# %bb.41: # in Loop: Header=BB6_40 Depth=2
movl $10, %edi
callq putchar@PLT
jmp .LBB6_42
.LBB6_44: # %_Z9print_matPKcPi4dim2.exit177
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20mult_matrices_kernelPiS_S_4dim2i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20mult_matrices_kernelPiS_S_4dim2i,@object # @_Z20mult_matrices_kernelPiS_S_4dim2i
.section .rodata,"a",@progbits
.globl _Z20mult_matrices_kernelPiS_S_4dim2i
.p2align 3, 0x0
_Z20mult_matrices_kernelPiS_S_4dim2i:
.quad _Z35__device_stub__mult_matrices_kernelPiS_S_4dim2i
.size _Z20mult_matrices_kernelPiS_S_4dim2i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s (%d, %d):\n"
.size .L.str, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\t%d "
.size .L.str.1, 5
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "First matrix"
.size .L.str.3, 13
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Second matrix"
.size .L.str.4, 14
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Third matrix"
.size .L.str.6, 13
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Result matrix"
.size .L.str.7, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20mult_matrices_kernelPiS_S_4dim2i"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__mult_matrices_kernelPiS_S_4dim2i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20mult_matrices_kernelPiS_S_4dim2i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#include <math.h>
__global__ void TwoDimPoisson(float *d_A, float *d_B, float *d_F, double dx, float* diff)
{
int threadId = threadIdx.x + (blockIdx.x * blockDim.x);
int threadAbove = threadId - blockDim.x;
int threadBelow = threadId + blockDim.x;
int N = gridDim.x * blockDim.x;
// Punt if this thread is a boundary point
if ((threadAbove <= 0) || (threadBelow >= N-1) ||
(threadId % (blockDim.x) == 0) ||
((threadId+1) % (blockDim.x) == 0))
return;
else
{
d_B[threadId] = (.25*(d_A[threadId+1] + d_A[threadId-1]
+ d_A[threadAbove] + d_A[threadBelow])
+ d_F[threadId]*pow(dx,2.0));
}
atomicAdd(diff,abs(d_B[threadId]-d_A[threadId])/(blockDim.x*gridDim.x));
}
int main(int argc, char** argv)
{
const int n = atoi(argv[1]);
int steps = 0;
const int BYTES = n*n * sizeof(float);
float* h_A = new float[n*n];
float* h_B = new float[n*n];
float* h_F = new float[n*n];
double dx = 0.1;
for (int i = 0; i < n; i++)
{
for (int j = 0; j < n; j++)
{
h_A[n*i + j] = 0;
h_B[n*i + j] = 0;
h_F[n*i + j] = 0;
if (j==0) h_A[n*i + j] = 1000;
if (j==n-1) h_F[n*i + j] = 5*i+20;
h_A[n*i + j]+=h_F[n*i + j];
}
}
//declare GPU memory pointers
float *d_A;
float *d_B;
float *d_F;
float *diff;
//allocate memory on the device
cudaMalloc((void **) &d_A, BYTES);
cudaMalloc((void **) &d_B, BYTES);
cudaMalloc((void **) &d_F, BYTES);
cudaMallocManaged(&diff, sizeof(float));
*diff = 0.0;
//transfer the array to the GPU
//destination, source, size, method
cudaMemcpy(d_B, h_B, BYTES, cudaMemcpyHostToDevice);
cudaMemcpy(d_A, h_A, BYTES, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, d_A, BYTES, cudaMemcpyDeviceToDevice);
cudaMemcpy(d_F, h_F, BYTES, cudaMemcpyHostToDevice);
//launch the kernel
while (true)
{
steps++;
*diff = 0.0;
TwoDimPoisson<<<n,n>>>(d_A, d_B, d_F, dx, diff);
cudaDeviceSynchronize();
cudaMemcpy(h_A, d_A, BYTES, cudaMemcpyDeviceToHost);
cudaMemcpy(h_B, d_B, BYTES, cudaMemcpyDeviceToHost);
cudaMemcpy(d_A, d_B, BYTES, cudaMemcpyDeviceToDevice);
if (*diff < 0.0001) break;
}
//copy the results back onto the device
//destination, source, size, method
cudaMemcpy(h_B, d_B, BYTES, cudaMemcpyDeviceToHost);
for (int i = 0; i < n; i++)
{
for (int j = 0; j < n; j++)
{
printf("%-10.3f ", h_B[i*n + j]);
}
printf("\n");
}
printf("\nSteps: %d \nn: %d\n",steps,n);
//free memory previously allocated on the device
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_F);
} | .file "tmpxft_001429c3_00000000-6_PoissonTwoDim.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z13TwoDimPoissonPfS_S_dS_PfS_S_dS_
.type _Z40__device_stub__Z13TwoDimPoissonPfS_S_dS_PfS_S_dS_, @function
_Z40__device_stub__Z13TwoDimPoissonPfS_S_dS_PfS_S_dS_:
.LFB2082:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movsd %xmm0, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13TwoDimPoissonPfS_S_dS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z40__device_stub__Z13TwoDimPoissonPfS_S_dS_PfS_S_dS_, .-_Z40__device_stub__Z13TwoDimPoissonPfS_S_dS_PfS_S_dS_
.globl _Z13TwoDimPoissonPfS_S_dS_
.type _Z13TwoDimPoissonPfS_S_dS_, @function
_Z13TwoDimPoissonPfS_S_dS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z13TwoDimPoissonPfS_S_dS_PfS_S_dS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z13TwoDimPoissonPfS_S_dS_, .-_Z13TwoDimPoissonPfS_S_dS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "%-10.3f "
.LC5:
.string "\n"
.LC6:
.string "\nSteps: %d \nn: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, 24(%rsp)
imull %eax, %eax
movslq %eax, %r13
leal 0(,%rax,4), %r14d
salq $2, %r13
movq %r13, %rdi
call _Znam@PLT
movq %rax, %r12
movq %r13, %rdi
call _Znam@PLT
movq %rax, %rbp
movq %r13, %rdi
call _Znam@PLT
movq %rax, 16(%rsp)
testl %ebx, %ebx
jle .L12
movq %rax, %r13
movslq %ebx, %r11
salq $2, %r11
movq %r12, %r8
movq %rbp, %rdi
leal 20(%rbx,%rbx,4), %r15d
movl $20, %esi
movl %ebx, %r10d
pxor %xmm1, %xmm1
movss .LC1(%rip), %xmm3
movl 24(%rsp), %eax
leal -1(%rax), %r9d
movl %r14d, 28(%rsp)
jmp .L13
.L14:
cmpl %r14d, %r9d
je .L15
movl $0x00000000, (%rcx)
.L16:
addss (%rcx), %xmm0
movss %xmm0, (%r8,%rax,4)
addq $1, %rax
addq $4, %rdx
cmpq %r10, %rax
je .L32
.L17:
movl $0x00000000, (%rdi,%rax,4)
movq %rdx, %rcx
movl %eax, %r14d
movaps %xmm1, %xmm0
testl %eax, %eax
jne .L14
movaps %xmm3, %xmm0
jmp .L14
.L15:
pxor %xmm2, %xmm2
cvtsi2ssl 12(%rsp), %xmm2
movss %xmm2, (%rcx)
jmp .L16
.L32:
addq %r11, %r8
addl $5, %esi
addq %r11, %r13
addq %r11, %rdi
cmpl %r15d, %esi
je .L29
.L13:
movq %r13, %rdx
movl $0, %eax
movl %esi, 12(%rsp)
jmp .L17
.L29:
movl 28(%rsp), %r14d
.L12:
movslq %r14d, %r13
leaq 32(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $1, %edx
movl $4, %esi
call cudaMallocManaged@PLT
movq 56(%rsp), %rax
movl $0x00000000, (%rax)
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $3, %ecx
movq %r13, %rdx
movq 32(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq 16(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %r14d
jmp .L19
.L18:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %r13, %rdx
movq 32(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %r13, %rdx
movq 40(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $3, %ecx
movq %r13, %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movq 56(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax), %xmm0
movsd .LC3(%rip), %xmm4
comisd %xmm0, %xmm4
ja .L33
.L19:
addl $1, %r14d
movq 56(%rsp), %rax
movl $0x00000000, (%rax)
movl %ebx, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl %ebx, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L18
movq 56(%rsp), %rcx
movsd .LC2(%rip), %xmm0
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z40__device_stub__Z13TwoDimPoissonPfS_S_dS_PfS_S_dS_
jmp .L18
.L33:
movl $2, %ecx
movq %r13, %rdx
movq 40(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %ebx, %ebx
jle .L21
movslq %ebx, %r15
salq $2, %r15
leal -1(%rbx), %eax
leaq 4(%rbp,%rax,4), %rbp
movl $0, %r13d
movl %ebx, %ebx
negq %rbx
leaq 0(,%rbx,4), %rax
leaq .LC4(%rip), %r12
movl %r14d, 12(%rsp)
movq %rax, %r14
.L22:
leaq (%r14,%rbp), %rbx
.L23:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L23
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addq %r15, %rbp
movl 24(%rsp), %eax
cmpl %eax, %r13d
jne .L22
movl 12(%rsp), %r14d
.L21:
movl 24(%rsp), %ecx
movl %r14d, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z13TwoDimPoissonPfS_S_dS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z13TwoDimPoissonPfS_S_dS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1148846080
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long -1717986918
.long 1069128089
.align 8
.LC3:
.long -350469331
.long 1058682594
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#include <math.h>
__global__ void TwoDimPoisson(float *d_A, float *d_B, float *d_F, double dx, float* diff)
{
int threadId = threadIdx.x + (blockIdx.x * blockDim.x);
int threadAbove = threadId - blockDim.x;
int threadBelow = threadId + blockDim.x;
int N = gridDim.x * blockDim.x;
// Punt if this thread is a boundary point
if ((threadAbove <= 0) || (threadBelow >= N-1) ||
(threadId % (blockDim.x) == 0) ||
((threadId+1) % (blockDim.x) == 0))
return;
else
{
d_B[threadId] = (.25*(d_A[threadId+1] + d_A[threadId-1]
+ d_A[threadAbove] + d_A[threadBelow])
+ d_F[threadId]*pow(dx,2.0));
}
atomicAdd(diff,abs(d_B[threadId]-d_A[threadId])/(blockDim.x*gridDim.x));
}
int main(int argc, char** argv)
{
const int n = atoi(argv[1]);
int steps = 0;
const int BYTES = n*n * sizeof(float);
float* h_A = new float[n*n];
float* h_B = new float[n*n];
float* h_F = new float[n*n];
double dx = 0.1;
for (int i = 0; i < n; i++)
{
for (int j = 0; j < n; j++)
{
h_A[n*i + j] = 0;
h_B[n*i + j] = 0;
h_F[n*i + j] = 0;
if (j==0) h_A[n*i + j] = 1000;
if (j==n-1) h_F[n*i + j] = 5*i+20;
h_A[n*i + j]+=h_F[n*i + j];
}
}
//declare GPU memory pointers
float *d_A;
float *d_B;
float *d_F;
float *diff;
//allocate memory on the device
cudaMalloc((void **) &d_A, BYTES);
cudaMalloc((void **) &d_B, BYTES);
cudaMalloc((void **) &d_F, BYTES);
cudaMallocManaged(&diff, sizeof(float));
*diff = 0.0;
//transfer the array to the GPU
//destination, source, size, method
cudaMemcpy(d_B, h_B, BYTES, cudaMemcpyHostToDevice);
cudaMemcpy(d_A, h_A, BYTES, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, d_A, BYTES, cudaMemcpyDeviceToDevice);
cudaMemcpy(d_F, h_F, BYTES, cudaMemcpyHostToDevice);
//launch the kernel
while (true)
{
steps++;
*diff = 0.0;
TwoDimPoisson<<<n,n>>>(d_A, d_B, d_F, dx, diff);
cudaDeviceSynchronize();
cudaMemcpy(h_A, d_A, BYTES, cudaMemcpyDeviceToHost);
cudaMemcpy(h_B, d_B, BYTES, cudaMemcpyDeviceToHost);
cudaMemcpy(d_A, d_B, BYTES, cudaMemcpyDeviceToDevice);
if (*diff < 0.0001) break;
}
//copy the results back onto the device
//destination, source, size, method
cudaMemcpy(h_B, d_B, BYTES, cudaMemcpyDeviceToHost);
for (int i = 0; i < n; i++)
{
for (int j = 0; j < n; j++)
{
printf("%-10.3f ", h_B[i*n + j]);
}
printf("\n");
}
printf("\nSteps: %d \nn: %d\n",steps,n);
//free memory previously allocated on the device
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_F);
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <math.h>
__global__ void TwoDimPoisson(float *d_A, float *d_B, float *d_F, double dx, float* diff)
{
int threadId = threadIdx.x + (blockIdx.x * blockDim.x);
int threadAbove = threadId - blockDim.x;
int threadBelow = threadId + blockDim.x;
int N = gridDim.x * blockDim.x;
// Punt if this thread is a boundary point
if ((threadAbove <= 0) || (threadBelow >= N-1) ||
(threadId % (blockDim.x) == 0) ||
((threadId+1) % (blockDim.x) == 0))
return;
else
{
d_B[threadId] = (.25*(d_A[threadId+1] + d_A[threadId-1]
+ d_A[threadAbove] + d_A[threadBelow])
+ d_F[threadId]*pow(dx,2.0));
}
atomicAdd(diff,abs(d_B[threadId]-d_A[threadId])/(blockDim.x*gridDim.x));
}
int main(int argc, char** argv)
{
const int n = atoi(argv[1]);
int steps = 0;
const int BYTES = n*n * sizeof(float);
float* h_A = new float[n*n];
float* h_B = new float[n*n];
float* h_F = new float[n*n];
double dx = 0.1;
for (int i = 0; i < n; i++)
{
for (int j = 0; j < n; j++)
{
h_A[n*i + j] = 0;
h_B[n*i + j] = 0;
h_F[n*i + j] = 0;
if (j==0) h_A[n*i + j] = 1000;
if (j==n-1) h_F[n*i + j] = 5*i+20;
h_A[n*i + j]+=h_F[n*i + j];
}
}
//declare GPU memory pointers
float *d_A;
float *d_B;
float *d_F;
float *diff;
//allocate memory on the device
hipMalloc((void **) &d_A, BYTES);
hipMalloc((void **) &d_B, BYTES);
hipMalloc((void **) &d_F, BYTES);
hipMallocManaged(&diff, sizeof(float));
*diff = 0.0;
//transfer the array to the GPU
//destination, source, size, method
hipMemcpy(d_B, h_B, BYTES, hipMemcpyHostToDevice);
hipMemcpy(d_A, h_A, BYTES, hipMemcpyHostToDevice);
hipMemcpy(d_B, d_A, BYTES, hipMemcpyDeviceToDevice);
hipMemcpy(d_F, h_F, BYTES, hipMemcpyHostToDevice);
//launch the kernel
while (true)
{
steps++;
*diff = 0.0;
TwoDimPoisson<<<n,n>>>(d_A, d_B, d_F, dx, diff);
hipDeviceSynchronize();
hipMemcpy(h_A, d_A, BYTES, hipMemcpyDeviceToHost);
hipMemcpy(h_B, d_B, BYTES, hipMemcpyDeviceToHost);
hipMemcpy(d_A, d_B, BYTES, hipMemcpyDeviceToDevice);
if (*diff < 0.0001) break;
}
//copy the results back onto the device
//destination, source, size, method
hipMemcpy(h_B, d_B, BYTES, hipMemcpyDeviceToHost);
for (int i = 0; i < n; i++)
{
for (int j = 0; j < n; j++)
{
printf("%-10.3f ", h_B[i*n + j]);
}
printf("\n");
}
printf("\nSteps: %d \nn: %d\n",steps,n);
//free memory previously allocated on the device
hipFree(d_A);
hipFree(d_B);
hipFree(d_F);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <math.h>
__global__ void TwoDimPoisson(float *d_A, float *d_B, float *d_F, double dx, float* diff)
{
int threadId = threadIdx.x + (blockIdx.x * blockDim.x);
int threadAbove = threadId - blockDim.x;
int threadBelow = threadId + blockDim.x;
int N = gridDim.x * blockDim.x;
// Punt if this thread is a boundary point
if ((threadAbove <= 0) || (threadBelow >= N-1) ||
(threadId % (blockDim.x) == 0) ||
((threadId+1) % (blockDim.x) == 0))
return;
else
{
d_B[threadId] = (.25*(d_A[threadId+1] + d_A[threadId-1]
+ d_A[threadAbove] + d_A[threadBelow])
+ d_F[threadId]*pow(dx,2.0));
}
atomicAdd(diff,abs(d_B[threadId]-d_A[threadId])/(blockDim.x*gridDim.x));
}
int main(int argc, char** argv)
{
const int n = atoi(argv[1]);
int steps = 0;
const int BYTES = n*n * sizeof(float);
float* h_A = new float[n*n];
float* h_B = new float[n*n];
float* h_F = new float[n*n];
double dx = 0.1;
for (int i = 0; i < n; i++)
{
for (int j = 0; j < n; j++)
{
h_A[n*i + j] = 0;
h_B[n*i + j] = 0;
h_F[n*i + j] = 0;
if (j==0) h_A[n*i + j] = 1000;
if (j==n-1) h_F[n*i + j] = 5*i+20;
h_A[n*i + j]+=h_F[n*i + j];
}
}
//declare GPU memory pointers
float *d_A;
float *d_B;
float *d_F;
float *diff;
//allocate memory on the device
hipMalloc((void **) &d_A, BYTES);
hipMalloc((void **) &d_B, BYTES);
hipMalloc((void **) &d_F, BYTES);
hipMallocManaged(&diff, sizeof(float));
*diff = 0.0;
//transfer the array to the GPU
//destination, source, size, method
hipMemcpy(d_B, h_B, BYTES, hipMemcpyHostToDevice);
hipMemcpy(d_A, h_A, BYTES, hipMemcpyHostToDevice);
hipMemcpy(d_B, d_A, BYTES, hipMemcpyDeviceToDevice);
hipMemcpy(d_F, h_F, BYTES, hipMemcpyHostToDevice);
//launch the kernel
while (true)
{
steps++;
*diff = 0.0;
TwoDimPoisson<<<n,n>>>(d_A, d_B, d_F, dx, diff);
hipDeviceSynchronize();
hipMemcpy(h_A, d_A, BYTES, hipMemcpyDeviceToHost);
hipMemcpy(h_B, d_B, BYTES, hipMemcpyDeviceToHost);
hipMemcpy(d_A, d_B, BYTES, hipMemcpyDeviceToDevice);
if (*diff < 0.0001) break;
}
//copy the results back onto the device
//destination, source, size, method
hipMemcpy(h_B, d_B, BYTES, hipMemcpyDeviceToHost);
for (int i = 0; i < n; i++)
{
for (int j = 0; j < n; j++)
{
printf("%-10.3f ", h_B[i*n + j]);
}
printf("\n");
}
printf("\nSteps: %d \nn: %d\n",steps,n);
//free memory previously allocated on the device
hipFree(d_A);
hipFree(d_B);
hipFree(d_F);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13TwoDimPoissonPfS_S_dS_
.globl _Z13TwoDimPoissonPfS_S_dS_
.p2align 8
.type _Z13TwoDimPoissonPfS_S_dS_,@function
_Z13TwoDimPoissonPfS_S_dS_:
s_load_b32 s4, s[0:1], 0x34
s_add_u32 s2, s0, 40
s_addc_u32 s3, s1, 0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s15, s4, v[0:1]
v_subrev_nc_u32_e32 v0, s4, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e32 0, v0
s_cbranch_execz .LBB0_9
s_load_b32 s14, s[2:3], 0x0
v_add_nc_u32_e32 v2, s4, v3
s_waitcnt lgkmcnt(0)
s_mul_i32 s14, s14, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s2, s14, -1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_9
v_cvt_f32_u32_e32 v1, s4
s_sub_i32 s2, 0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, s2, v1
v_mul_hi_u32 v4, v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v4
v_mul_hi_u32 v4, v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v4, s4
v_sub_nc_u32_e32 v4, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s4, v4
v_cmp_le_u32_e32 vcc_lo, s4, v4
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s4, v4
v_cmp_le_u32_e32 vcc_lo, s4, v4
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, 0, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_9
v_add_nc_u32_e32 v5, 1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v1, v5, v1
v_mul_lo_u32 v1, v1, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v1, v5, v1
v_subrev_nc_u32_e32 v4, s4, v1
v_cmp_le_u32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v1, v4, vcc_lo
v_subrev_nc_u32_e32 v4, s4, v1
v_cmp_le_u32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v1, v4, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v1
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_9
s_load_b256 s[4:11], s[0:1], 0x0
s_mov_b32 s3, 0x3fe55555
s_mov_b32 s2, 0x55555555
s_mov_b32 s13, 0x3fba6564
s_mov_b32 s12, 0x968915a9
s_mov_b32 s17, 0x3fbdee67
s_mov_b32 s16, 0x4222de17
s_mov_b32 s19, 0x3ff71547
s_mov_b32 s18, 0x652b82fe
v_ashrrev_i32_e32 v4, 31, v3
s_mov_b32 s15, exec_lo
s_waitcnt lgkmcnt(0)
v_frexp_mant_f64_e64 v[6:7], |s[10:11]|
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e32 vcc_lo, s[2:3], v[6:7]
v_cndmask_b32_e64 v1, 0, 1, vcc_lo
v_ldexp_f64 v[6:7], v[6:7], v1
v_frexp_exp_i32_f64_e32 v1, s[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[8:9], v[6:7], 1.0
v_add_f64 v[14:15], v[6:7], -1.0
v_subrev_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[10:11], v[8:9]
v_add_f64 v[16:17], v[8:9], -1.0
v_add_f64 v[6:7], v[6:7], -v[16:17]
s_waitcnt_depctr 0xfff
v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[12:13], v[10:11], v[10:11]
v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[12:13], v[10:11], v[10:11]
v_mul_f64 v[12:13], v[14:15], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[18:19], v[8:9], v[12:13]
v_fma_f64 v[8:9], v[12:13], v[8:9], -v[18:19]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[12:13], v[6:7], v[8:9]
v_add_f64 v[8:9], v[18:19], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[16:17], v[14:15], -v[8:9]
v_add_f64 v[18:19], v[8:9], -v[18:19]
v_add_f64 v[14:15], v[14:15], -v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[6:7], v[18:19], -v[6:7]
v_add_f64 v[8:9], v[14:15], -v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[6:7], v[6:7], v[8:9]
v_add_f64 v[6:7], v[16:17], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[6:7], v[10:11], v[6:7]
v_add_f64 v[8:9], v[12:13], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[10:11], v[8:9], -v[12:13]
v_mul_f64 v[12:13], v[8:9], v[8:9]
v_add_f64 v[6:7], v[6:7], -v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], v[8:9], v[8:9], -v[12:13]
v_add_f64 v[14:15], v[6:7], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[8:9], v[14:15], v[10:11]
v_add_f64 v[14:15], v[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[16:17], v[14:15], s[16:17], s[12:13]
s_mov_b32 s13, 0x3fbe25e4
s_mov_b32 s12, 0x3abe935a
v_add_f64 v[12:13], v[14:15], -v[12:13]
v_mul_f64 v[22:23], v[8:9], v[14:15]
s_mov_b32 s17, 0x3c7abc9e
s_mov_b32 s16, 0x3b39803f
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f64 v[16:17], v[14:15], v[16:17], s[12:13]
s_mov_b32 s13, 0x3fc110ef
s_mov_b32 s12, 0x47e6c9c2
v_add_f64 v[10:11], v[10:11], -v[12:13]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[16:17], v[14:15], v[16:17], s[12:13]
s_mov_b32 s13, 0x3fc3b13b
s_mov_b32 s12, 0xcfa74449
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[16:17], v[14:15], v[16:17], s[12:13]
s_mov_b32 s13, 0x3fc745d1
s_mov_b32 s12, 0x71bf3c30
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[16:17], v[14:15], v[16:17], s[12:13]
s_mov_b32 s13, 0x3fcc71c7
s_mov_b32 s12, 0x1c7792ce
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[16:17], v[14:15], v[16:17], s[12:13]
s_mov_b32 s13, 0x3fd24924
s_mov_b32 s12, 0x924920da
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[16:17], v[14:15], v[16:17], s[12:13]
s_mov_b32 s13, 0x3fd99999
s_mov_b32 s12, 0x9999999c
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[16:17], v[14:15], v[16:17], s[12:13]
s_mov_b32 s12, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[18:19], v[14:15], v[16:17]
v_fma_f64 v[12:13], v[14:15], v[16:17], -v[18:19]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[10:11], v[16:17], v[12:13]
v_add_f64 v[16:17], v[18:19], v[12:13]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[20:21], v[16:17], s[2:3]
v_add_f64 v[18:19], v[16:17], -v[18:19]
s_mov_b32 s3, 0xbfe55555
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_add_f64 v[24:25], v[20:21], s[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_add_f64 v[12:13], v[12:13], -v[18:19]
v_fma_f64 v[18:19], v[14:15], v[8:9], -v[22:23]
s_mov_b32 s3, 0x3c8543b0
s_mov_b32 s2, 0xd5df274d
v_add_f64 v[16:17], v[16:17], -v[24:25]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[12:13], v[12:13], s[2:3]
v_fma_f64 v[14:15], v[14:15], v[6:7], v[18:19]
s_mov_b32 s3, 0x3fe62e42
s_mov_b32 s2, 0xfefa39ef
v_ldexp_f64 v[6:7], v[6:7], 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[12:13], v[12:13], v[16:17]
v_fma_f64 v[10:11], v[10:11], v[8:9], v[14:15]
v_ldexp_f64 v[8:9], v[8:9], 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[14:15], v[20:21], v[12:13]
v_add_f64 v[16:17], v[22:23], v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[18:19], v[20:21], -v[14:15]
v_mul_f64 v[20:21], v[16:17], v[14:15]
v_add_f64 v[22:23], v[16:17], -v[22:23]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[12:13], v[12:13], v[18:19]
v_fma_f64 v[18:19], v[16:17], v[14:15], -v[20:21]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[10:11], v[10:11], -v[22:23]
v_fma_f64 v[12:13], v[16:17], v[12:13], v[18:19]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[10:11], v[14:15], v[12:13]
v_cvt_f64_i32_e32 v[14:15], v1
v_mov_b32_e32 v1, 0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[12:13], v[20:21], v[10:11]
v_add_f64 v[16:17], v[8:9], v[12:13]
v_add_f64 v[18:19], v[12:13], -v[20:21]
v_mul_f64 v[20:21], v[14:15], s[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[8:9], v[16:17], -v[8:9]
v_add_f64 v[10:11], v[10:11], -v[18:19]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_fma_f64 v[18:19], v[14:15], s[2:3], -v[20:21]
v_cmp_eq_f64_e64 s3, s[10:11], 1.0
v_add_f64 v[8:9], v[12:13], -v[8:9]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[6:7], v[6:7], v[10:11]
v_fma_f64 v[10:11], v[14:15], s[16:17], v[18:19]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
s_and_b32 s3, s3, exec_lo
s_cselect_b32 s13, 0x3ff00000, 2.0
s_mov_b32 s3, 0xbfe62e42
s_mov_b32 s17, 0xbc7abc9e
v_add_f64 v[6:7], v[6:7], v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[8:9], v[20:21], v[10:11]
v_add_f64 v[12:13], v[16:17], v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[20:21], v[8:9], -v[20:21]
v_add_f64 v[14:15], v[8:9], v[12:13]
v_add_f64 v[16:17], v[12:13], -v[16:17]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[10:11], v[10:11], -v[20:21]
v_add_f64 v[18:19], v[14:15], -v[8:9]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[6:7], v[6:7], -v[16:17]
v_add_f64 v[22:23], v[14:15], -v[18:19]
v_add_f64 v[12:13], v[12:13], -v[18:19]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[16:17], v[10:11], v[6:7]
v_add_f64 v[8:9], v[8:9], -v[22:23]
v_lshlrev_b64 v[22:23], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[8:9], v[12:13], v[8:9]
v_add_f64 v[12:13], v[16:17], -v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[8:9], v[16:17], v[8:9]
v_add_f64 v[16:17], v[16:17], -v[12:13]
v_add_f64 v[6:7], v[6:7], -v[12:13]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[18:19], v[14:15], v[8:9]
v_add_f64 v[10:11], v[10:11], -v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[12:13], v[18:19], -v[14:15]
v_add_f64 v[6:7], v[6:7], v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[8:9], v[8:9], -v[12:13]
v_add_f64 v[6:7], v[6:7], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[8:9], v[18:19], v[6:7]
v_add_f64 v[10:11], v[8:9], -v[18:19]
v_mul_f64 v[12:13], s[12:13], v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[6:7], v[6:7], -v[10:11]
v_fma_f64 v[8:9], s[12:13], v[8:9], -v[12:13]
v_cmp_class_f64_e64 vcc_lo, v[12:13], 0x204
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[7:8], s[12:13], v[6:7], v[8:9]
v_ashrrev_i32_e32 v6, 31, v5
v_add_f64 v[9:10], v[12:13], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v15, v10, v13 :: v_dual_cndmask_b32 v14, v9, v12
v_add_co_u32 v3, vcc_lo, s8, v22
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v23, vcc_lo
v_mul_f64 v[16:17], v[14:15], s[18:19]
global_load_b32 v26, v[3:4], off
v_lshlrev_b64 v[4:5], 2, v[5:6]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v24, vcc_lo, s4, v22
v_add_co_ci_u32_e32 v25, vcc_lo, s5, v23, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_clause 0x2
global_load_b32 v27, v[4:5], off
global_load_b32 v28, v[24:25], off offset:-4
global_load_b32 v29, v[0:1], off
v_mul_f64 v[4:5], s[12:13], 0.5
v_add_co_u32 v0, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo
v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[14:15]
global_load_b32 v30, v[0:1], off
v_rndne_f64_e32 v[16:17], v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_fma_f64 v[18:19], v[16:17], s[2:3], v[14:15]
s_mov_b32 s3, 0x3e928af3
s_mov_b32 s2, 0xfca7ab0c
v_cvt_i32_f64_e32 v2, v[16:17]
v_fma_f64 v[18:19], v[16:17], s[16:17], v[18:19]
s_mov_b32 s17, 0x3e5ade15
s_mov_b32 s16, 0x6a5dcb37
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[20:21], v[18:19], s[16:17], s[2:3]
s_mov_b32 s3, 0x3ec71dee
s_mov_b32 s2, 0x623fde64
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[20:21], v[18:19], v[20:21], s[2:3]
s_mov_b32 s3, 0x3efa0199
s_mov_b32 s2, 0x7c89e6b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[20:21], v[18:19], v[20:21], s[2:3]
s_mov_b32 s3, 0x3f2a01a0
s_mov_b32 s2, 0x14761f6e
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[20:21], v[18:19], v[20:21], s[2:3]
s_mov_b32 s3, 0x3f56c16c
s_mov_b32 s2, 0x1852b7b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[20:21], v[18:19], v[20:21], s[2:3]
s_mov_b32 s3, 0x3f811111
s_mov_b32 s2, 0x11122322
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[20:21], v[18:19], v[20:21], s[2:3]
s_mov_b32 s3, 0x3fa55555
s_mov_b32 s2, 0x555502a1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[20:21], v[18:19], v[20:21], s[2:3]
s_mov_b32 s3, 0x3fc55555
s_mov_b32 s2, 0x55555511
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[20:21], v[18:19], v[20:21], s[2:3]
s_mov_b32 s3, 0x3fe00000
s_mov_b32 s2, 11
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[20:21], v[18:19], v[20:21], s[2:3]
v_cmp_ngt_f64_e64 s2, 0xc090cc00, v[14:15]
v_cmp_neq_f64_e64 s3, 0x7ff00000, |v[14:15]|
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[0:1], v[18:19], v[20:21], 1.0
v_fma_f64 v[0:1], v[18:19], v[0:1], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ldexp_f64 v[0:1], v[0:1], v2
v_add_f64 v[2:3], v[9:10], -v[12:13]
v_cndmask_b32_e32 v10, 0x7ff00000, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2)
v_add_f64 v[1:2], v[7:8], -v[2:3]
v_trunc_f64_e32 v[6:7], s[12:13]
v_trunc_f64_e32 v[8:9], v[4:5]
v_readfirstlane_b32 s4, v0
v_cndmask_b32_e64 v3, 0, v10, s2
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_and_b32 s2, s2, exec_lo
s_cselect_b32 s4, s4, 0
v_cndmask_b32_e64 v11, 0, v2, s3
v_cndmask_b32_e64 v10, 0, v1, s3
v_mov_b32_e32 v2, s4
v_cmp_eq_f64_e64 s2, s[12:13], v[6:7]
v_cmp_neq_f64_e64 s3, v[8:9], v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[0:1], v[2:3], v[10:11], v[2:3]
v_cmp_class_f64_e64 vcc_lo, v[2:3], 0x204
v_readfirstlane_b32 s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
s_and_b32 s8, vcc_lo, exec_lo
v_cndmask_b32_e32 v0, v1, v3, vcc_lo
v_cmp_lt_f64_e64 vcc_lo, s[10:11], 0
v_cmp_eq_f64_e64 s8, s[10:11], 0
s_cselect_b32 s4, s4, s5
s_and_b32 s3, s2, s3
s_waitcnt vmcnt(2)
v_add_f32_e32 v3, v27, v28
s_and_b32 s5, s3, exec_lo
s_cselect_b32 s5, s11, 0x3ff00000
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_bfi_b32 v0, 0x7fffffff, v0, s5
v_cmp_class_f64_e64 s5, s[10:11], 0x204
s_waitcnt vmcnt(1)
v_add_f32_e32 v4, v3, v29
v_cndmask_b32_e64 v1, 0x7ff80000, v0, s2
s_and_b32 s2, s2, exec_lo
s_cselect_b32 s2, s4, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v4, v30
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f64_f32_e32 v[4:5], v4
s_and_b32 s9, vcc_lo, exec_lo
v_cndmask_b32_e32 v0, v0, v1, vcc_lo
s_cselect_b32 s4, s2, s4
s_or_b32 vcc_lo, s8, s5
s_and_b32 s2, s8, exec_lo
s_cselect_b32 s2, 0, 0x7ff00000
s_and_b32 s3, s3, exec_lo
s_cselect_b32 s3, s11, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mov_b32_e32 v1, s3
s_and_b32 s3, vcc_lo, exec_lo
s_cselect_b32 s3, 0, s4
v_bfi_b32 v1, 0x7fffffff, s2, v1
v_cmp_o_f64_e64 s2, s[10:11], s[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v0, v1, vcc_lo
v_cvt_f64_f32_e32 v[0:1], v26
v_cndmask_b32_e64 v3, 0x7ff80000, v2, s2
s_and_b32 s2, s2, exec_lo
s_cselect_b32 s2, s3, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v2, s2
v_mul_f64 v[0:1], v[2:3], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[0:1], v[4:5], 0x3fd00000, v[0:1]
v_cvt_f32_f64_e32 v2, v[0:1]
v_add_co_u32 v0, vcc_lo, s6, v22
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v23, vcc_lo
global_store_b32 v[0:1], v2, off
global_load_b32 v0, v[24:25], off
v_cvt_f32_u32_e32 v1, s14
s_waitcnt vmcnt(0)
v_sub_f32_e32 v0, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v2, 0x7fffffff, v0
v_div_scale_f32 v3, null, v1, v1, v2
v_div_scale_f32 v2, vcc_lo, v2, v1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
v_fmac_f32_e32 v4, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v2, v4
v_fma_f32 v6, -v3, v5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v4
v_fma_f32 v2, -v3, v5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v2, v2, v4, v5
v_div_fixup_f32 v0, v2, v1, |v0|
v_bfrev_b32_e32 v2, 1
.LBB0_5:
s_ctz_i32_b32 s2, s15
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_readlane_b32 s3, v0, s2
s_lshl_b32 s2, 1, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s15, s15, s2
s_cmp_lg_u32 s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v2, s3, v2
s_cbranch_scc1 .LBB0_5
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s2, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_9
s_load_b64 s[0:1], s[0:1], 0x20
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v3, s[0:1]
.LBB0_8:
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v1, v2
global_atomic_cmpswap_b32 v0, v3, v[0:1], s[0:1] glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v0, v1
v_mov_b32_e32 v1, v0
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_8
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13TwoDimPoissonPfS_S_dS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 31
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13TwoDimPoissonPfS_S_dS_, .Lfunc_end0-_Z13TwoDimPoissonPfS_S_dS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13TwoDimPoissonPfS_S_dS_
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z13TwoDimPoissonPfS_S_dS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 31
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <math.h>
__global__ void TwoDimPoisson(float *d_A, float *d_B, float *d_F, double dx, float* diff)
{
int threadId = threadIdx.x + (blockIdx.x * blockDim.x);
int threadAbove = threadId - blockDim.x;
int threadBelow = threadId + blockDim.x;
int N = gridDim.x * blockDim.x;
// Punt if this thread is a boundary point
if ((threadAbove <= 0) || (threadBelow >= N-1) ||
(threadId % (blockDim.x) == 0) ||
((threadId+1) % (blockDim.x) == 0))
return;
else
{
d_B[threadId] = (.25*(d_A[threadId+1] + d_A[threadId-1]
+ d_A[threadAbove] + d_A[threadBelow])
+ d_F[threadId]*pow(dx,2.0));
}
atomicAdd(diff,abs(d_B[threadId]-d_A[threadId])/(blockDim.x*gridDim.x));
}
int main(int argc, char** argv)
{
const int n = atoi(argv[1]);
int steps = 0;
const int BYTES = n*n * sizeof(float);
float* h_A = new float[n*n];
float* h_B = new float[n*n];
float* h_F = new float[n*n];
double dx = 0.1;
for (int i = 0; i < n; i++)
{
for (int j = 0; j < n; j++)
{
h_A[n*i + j] = 0;
h_B[n*i + j] = 0;
h_F[n*i + j] = 0;
if (j==0) h_A[n*i + j] = 1000;
if (j==n-1) h_F[n*i + j] = 5*i+20;
h_A[n*i + j]+=h_F[n*i + j];
}
}
//declare GPU memory pointers
float *d_A;
float *d_B;
float *d_F;
float *diff;
//allocate memory on the device
hipMalloc((void **) &d_A, BYTES);
hipMalloc((void **) &d_B, BYTES);
hipMalloc((void **) &d_F, BYTES);
hipMallocManaged(&diff, sizeof(float));
*diff = 0.0;
//transfer the array to the GPU
//destination, source, size, method
hipMemcpy(d_B, h_B, BYTES, hipMemcpyHostToDevice);
hipMemcpy(d_A, h_A, BYTES, hipMemcpyHostToDevice);
hipMemcpy(d_B, d_A, BYTES, hipMemcpyDeviceToDevice);
hipMemcpy(d_F, h_F, BYTES, hipMemcpyHostToDevice);
//launch the kernel
while (true)
{
steps++;
*diff = 0.0;
TwoDimPoisson<<<n,n>>>(d_A, d_B, d_F, dx, diff);
hipDeviceSynchronize();
hipMemcpy(h_A, d_A, BYTES, hipMemcpyDeviceToHost);
hipMemcpy(h_B, d_B, BYTES, hipMemcpyDeviceToHost);
hipMemcpy(d_A, d_B, BYTES, hipMemcpyDeviceToDevice);
if (*diff < 0.0001) break;
}
//copy the results back onto the device
//destination, source, size, method
hipMemcpy(h_B, d_B, BYTES, hipMemcpyDeviceToHost);
for (int i = 0; i < n; i++)
{
for (int j = 0; j < n; j++)
{
printf("%-10.3f ", h_B[i*n + j]);
}
printf("\n");
}
printf("\nSteps: %d \nn: %d\n",steps,n);
//free memory previously allocated on the device
hipFree(d_A);
hipFree(d_B);
hipFree(d_F);
} | .text
.file "PoissonTwoDim.hip"
.globl _Z28__device_stub__TwoDimPoissonPfS_S_dS_ # -- Begin function _Z28__device_stub__TwoDimPoissonPfS_S_dS_
.p2align 4, 0x90
.type _Z28__device_stub__TwoDimPoissonPfS_S_dS_,@function
_Z28__device_stub__TwoDimPoissonPfS_S_dS_: # @_Z28__device_stub__TwoDimPoissonPfS_S_dS_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movsd %xmm0, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13TwoDimPoissonPfS_S_dS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z28__device_stub__TwoDimPoissonPfS_S_dS_, .Lfunc_end0-_Z28__device_stub__TwoDimPoissonPfS_S_dS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3f1a36e2eb1c432d # double 1.0E-4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
imull %eax, %eax
leaq (,%rax,4), %r13
# kill: def $eax killed $eax killed $rax
shll $2, %eax
movl %eax, 56(%rsp) # 4-byte Spill
movq %r13, %rdi
callq _Znam
movq %rax, 72(%rsp) # 8-byte Spill
movq %r13, %rdi
callq _Znam
movq %rax, 24(%rsp) # 8-byte Spill
movq %r13, %rdi
callq _Znam
movq %rbx, %rcx
movq %rax, 64(%rsp) # 8-byte Spill
testl %ecx, %ecx
movq %rbx, 40(%rsp) # 8-byte Spill
jle .LBB1_9
# %bb.1: # %.preheader90.lr.ph
movl $4294967295, %eax # imm = 0xFFFFFFFF
leal (%rcx,%rax), %ebp
movl %ecx, %r14d
leaq (,%r14,4), %rax
movq %rax, 80(%rsp) # 8-byte Spill
xorl %r12d, %r12d
xorl %r15d, %r15d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_8: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %r15
movq 40(%rsp), %rcx # 8-byte Reload
addl %ecx, %r12d
cmpq %r14, %r15
je .LBB1_9
.LBB1_2: # %.preheader90
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movl %r12d, %eax
movq 64(%rsp), %rdx # 8-byte Reload
leaq (%rdx,%rax,4), %r13
movq 72(%rsp), %rdx # 8-byte Reload
leaq (%rdx,%rax,4), %rbx
movl %ecx, %edi
imull %r15d, %edi
shlq $2, %rdi
movabsq $17179869180, %rax # imm = 0x3FFFFFFFC
andq %rax, %rdi
addq 24(%rsp), %rdi # 8-byte Folded Reload
leal (%r15,%r15,4), %eax
addl $20, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, 60(%rsp) # 4-byte Spill
xorl %esi, %esi
movq 80(%rsp), %rdx # 8-byte Reload
callq memset@PLT
movss 60(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
xorl %eax, %eax
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_3 Depth=2
movss (%r13,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rbx,%rax,4), %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq %rax, %r14
je .LBB1_8
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $0, (%rbx,%rax,4)
movl $0, (%r13,%rax,4)
testq %rax, %rax
je .LBB1_4
# %bb.5: # in Loop: Header=BB1_3 Depth=2
cmpq %rax, %rbp
jne .LBB1_7
jmp .LBB1_6
.p2align 4, 0x90
.LBB1_4: # in Loop: Header=BB1_3 Depth=2
movl $1148846080, (%rbx,%rax,4) # imm = 0x447A0000
cmpq %rax, %rbp
jne .LBB1_7
.LBB1_6: # in Loop: Header=BB1_3 Depth=2
movss %xmm1, (%r13,%rax,4)
jmp .LBB1_7
.LBB1_9: # %._crit_edge93
movslq 56(%rsp), %r13 # 4-byte Folded Reload
leaq 16(%rsp), %rdi
movq %r13, %rsi
movq %rcx, %rbx
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movl $4, %esi
movl $1, %edx
callq hipMallocManaged
movq 32(%rsp), %rax
movl $0, (%rax)
movq 8(%rsp), %rdi
movq 24(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 72(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq 16(%rsp), %rsi
movq %r13, %rdx
movl $3, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq 64(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movl %ebx, %eax
movl $4294967295, %ecx # imm = 0xFFFFFFFF
leaq (%rcx,%rax), %rbp
incq %rbp
movabsq $4591870180066957722, %r15 # imm = 0x3FB999999999999A
leaq 168(%rsp), %r12
xorl %ebx, %ebx
jmp .LBB1_10
.p2align 4, 0x90
.LBB1_12: # in Loop: Header=BB1_10 Depth=1
callq hipDeviceSynchronize
movq 16(%rsp), %rsi
movq %r14, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi # 8-byte Reload
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
movq %r13, %rdx
movl $3, %ecx
callq hipMemcpy
movq 32(%rsp), %rax
movss (%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
incl %ebx
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
ucomisd %xmm0, %xmm1
ja .LBB1_13
.LBB1_10: # =>This Inner Loop Header: Depth=1
movq 32(%rsp), %rax
movl $0, (%rax)
movq %rbp, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_12
# %bb.11: # in Loop: Header=BB1_10 Depth=1
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 48(%rsp), %rdx
movq 32(%rsp), %rsi
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movq %r15, 144(%rsp)
movq %rsi, 136(%rsp)
movq %r12, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 144(%rsp), %rax
movq %rax, 200(%rsp)
leaq 136(%rsp), %rax
movq %rax, 208(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
movl $_Z13TwoDimPoissonPfS_S_dS_, %edi
leaq 176(%rsp), %r9
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_12
.LBB1_13:
movq %rbx, %rbp
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi # 8-byte Reload
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rdx # 8-byte Reload
testl %edx, %edx
jle .LBB1_18
# %bb.14: # %.preheader.lr.ph
movl %edx, %ebx
xorl %r14d, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_15: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_16 Depth 2
movl %r14d, %eax
movq 24(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_16: # Parent Loop BB1_15 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r13
cmpq %r13, %rbx
jne .LBB1_16
# %bb.17: # %._crit_edge96
# in Loop: Header=BB1_15 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
movq 40(%rsp), %rdx # 8-byte Reload
addl %edx, %r14d
cmpq %rbx, %r15
jne .LBB1_15
.LBB1_18: # %._crit_edge98
movl $.L.str.2, %edi
movl %ebp, %esi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13TwoDimPoissonPfS_S_dS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13TwoDimPoissonPfS_S_dS_,@object # @_Z13TwoDimPoissonPfS_S_dS_
.section .rodata,"a",@progbits
.globl _Z13TwoDimPoissonPfS_S_dS_
.p2align 3, 0x0
_Z13TwoDimPoissonPfS_S_dS_:
.quad _Z28__device_stub__TwoDimPoissonPfS_S_dS_
.size _Z13TwoDimPoissonPfS_S_dS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%-10.3f "
.size .L.str, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nSteps: %d \nn: %d\n"
.size .L.str.2, 19
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13TwoDimPoissonPfS_S_dS_"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__TwoDimPoissonPfS_S_dS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13TwoDimPoissonPfS_S_dS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001429c3_00000000-6_PoissonTwoDim.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z13TwoDimPoissonPfS_S_dS_PfS_S_dS_
.type _Z40__device_stub__Z13TwoDimPoissonPfS_S_dS_PfS_S_dS_, @function
_Z40__device_stub__Z13TwoDimPoissonPfS_S_dS_PfS_S_dS_:
.LFB2082:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movsd %xmm0, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13TwoDimPoissonPfS_S_dS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z40__device_stub__Z13TwoDimPoissonPfS_S_dS_PfS_S_dS_, .-_Z40__device_stub__Z13TwoDimPoissonPfS_S_dS_PfS_S_dS_
.globl _Z13TwoDimPoissonPfS_S_dS_
.type _Z13TwoDimPoissonPfS_S_dS_, @function
_Z13TwoDimPoissonPfS_S_dS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z13TwoDimPoissonPfS_S_dS_PfS_S_dS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z13TwoDimPoissonPfS_S_dS_, .-_Z13TwoDimPoissonPfS_S_dS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "%-10.3f "
.LC5:
.string "\n"
.LC6:
.string "\nSteps: %d \nn: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, 24(%rsp)
imull %eax, %eax
movslq %eax, %r13
leal 0(,%rax,4), %r14d
salq $2, %r13
movq %r13, %rdi
call _Znam@PLT
movq %rax, %r12
movq %r13, %rdi
call _Znam@PLT
movq %rax, %rbp
movq %r13, %rdi
call _Znam@PLT
movq %rax, 16(%rsp)
testl %ebx, %ebx
jle .L12
movq %rax, %r13
movslq %ebx, %r11
salq $2, %r11
movq %r12, %r8
movq %rbp, %rdi
leal 20(%rbx,%rbx,4), %r15d
movl $20, %esi
movl %ebx, %r10d
pxor %xmm1, %xmm1
movss .LC1(%rip), %xmm3
movl 24(%rsp), %eax
leal -1(%rax), %r9d
movl %r14d, 28(%rsp)
jmp .L13
.L14:
cmpl %r14d, %r9d
je .L15
movl $0x00000000, (%rcx)
.L16:
addss (%rcx), %xmm0
movss %xmm0, (%r8,%rax,4)
addq $1, %rax
addq $4, %rdx
cmpq %r10, %rax
je .L32
.L17:
movl $0x00000000, (%rdi,%rax,4)
movq %rdx, %rcx
movl %eax, %r14d
movaps %xmm1, %xmm0
testl %eax, %eax
jne .L14
movaps %xmm3, %xmm0
jmp .L14
.L15:
pxor %xmm2, %xmm2
cvtsi2ssl 12(%rsp), %xmm2
movss %xmm2, (%rcx)
jmp .L16
.L32:
addq %r11, %r8
addl $5, %esi
addq %r11, %r13
addq %r11, %rdi
cmpl %r15d, %esi
je .L29
.L13:
movq %r13, %rdx
movl $0, %eax
movl %esi, 12(%rsp)
jmp .L17
.L29:
movl 28(%rsp), %r14d
.L12:
movslq %r14d, %r13
leaq 32(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $1, %edx
movl $4, %esi
call cudaMallocManaged@PLT
movq 56(%rsp), %rax
movl $0x00000000, (%rax)
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $3, %ecx
movq %r13, %rdx
movq 32(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq 16(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %r14d
jmp .L19
.L18:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %r13, %rdx
movq 32(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %r13, %rdx
movq 40(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $3, %ecx
movq %r13, %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movq 56(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax), %xmm0
movsd .LC3(%rip), %xmm4
comisd %xmm0, %xmm4
ja .L33
.L19:
addl $1, %r14d
movq 56(%rsp), %rax
movl $0x00000000, (%rax)
movl %ebx, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl %ebx, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L18
movq 56(%rsp), %rcx
movsd .LC2(%rip), %xmm0
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z40__device_stub__Z13TwoDimPoissonPfS_S_dS_PfS_S_dS_
jmp .L18
.L33:
movl $2, %ecx
movq %r13, %rdx
movq 40(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %ebx, %ebx
jle .L21
movslq %ebx, %r15
salq $2, %r15
leal -1(%rbx), %eax
leaq 4(%rbp,%rax,4), %rbp
movl $0, %r13d
movl %ebx, %ebx
negq %rbx
leaq 0(,%rbx,4), %rax
leaq .LC4(%rip), %r12
movl %r14d, 12(%rsp)
movq %rax, %r14
.L22:
leaq (%r14,%rbp), %rbx
.L23:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L23
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addq %r15, %rbp
movl 24(%rsp), %eax
cmpl %eax, %r13d
jne .L22
movl 12(%rsp), %r14d
.L21:
movl 24(%rsp), %ecx
movl %r14d, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z13TwoDimPoissonPfS_S_dS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z13TwoDimPoissonPfS_S_dS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1148846080
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long -1717986918
.long 1069128089
.align 8
.LC3:
.long -350469331
.long 1058682594
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "PoissonTwoDim.hip"
.globl _Z28__device_stub__TwoDimPoissonPfS_S_dS_ # -- Begin function _Z28__device_stub__TwoDimPoissonPfS_S_dS_
.p2align 4, 0x90
.type _Z28__device_stub__TwoDimPoissonPfS_S_dS_,@function
_Z28__device_stub__TwoDimPoissonPfS_S_dS_: # @_Z28__device_stub__TwoDimPoissonPfS_S_dS_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movsd %xmm0, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13TwoDimPoissonPfS_S_dS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z28__device_stub__TwoDimPoissonPfS_S_dS_, .Lfunc_end0-_Z28__device_stub__TwoDimPoissonPfS_S_dS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3f1a36e2eb1c432d # double 1.0E-4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
imull %eax, %eax
leaq (,%rax,4), %r13
# kill: def $eax killed $eax killed $rax
shll $2, %eax
movl %eax, 56(%rsp) # 4-byte Spill
movq %r13, %rdi
callq _Znam
movq %rax, 72(%rsp) # 8-byte Spill
movq %r13, %rdi
callq _Znam
movq %rax, 24(%rsp) # 8-byte Spill
movq %r13, %rdi
callq _Znam
movq %rbx, %rcx
movq %rax, 64(%rsp) # 8-byte Spill
testl %ecx, %ecx
movq %rbx, 40(%rsp) # 8-byte Spill
jle .LBB1_9
# %bb.1: # %.preheader90.lr.ph
movl $4294967295, %eax # imm = 0xFFFFFFFF
leal (%rcx,%rax), %ebp
movl %ecx, %r14d
leaq (,%r14,4), %rax
movq %rax, 80(%rsp) # 8-byte Spill
xorl %r12d, %r12d
xorl %r15d, %r15d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_8: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %r15
movq 40(%rsp), %rcx # 8-byte Reload
addl %ecx, %r12d
cmpq %r14, %r15
je .LBB1_9
.LBB1_2: # %.preheader90
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movl %r12d, %eax
movq 64(%rsp), %rdx # 8-byte Reload
leaq (%rdx,%rax,4), %r13
movq 72(%rsp), %rdx # 8-byte Reload
leaq (%rdx,%rax,4), %rbx
movl %ecx, %edi
imull %r15d, %edi
shlq $2, %rdi
movabsq $17179869180, %rax # imm = 0x3FFFFFFFC
andq %rax, %rdi
addq 24(%rsp), %rdi # 8-byte Folded Reload
leal (%r15,%r15,4), %eax
addl $20, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, 60(%rsp) # 4-byte Spill
xorl %esi, %esi
movq 80(%rsp), %rdx # 8-byte Reload
callq memset@PLT
movss 60(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
xorl %eax, %eax
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_3 Depth=2
movss (%r13,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rbx,%rax,4), %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq %rax, %r14
je .LBB1_8
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $0, (%rbx,%rax,4)
movl $0, (%r13,%rax,4)
testq %rax, %rax
je .LBB1_4
# %bb.5: # in Loop: Header=BB1_3 Depth=2
cmpq %rax, %rbp
jne .LBB1_7
jmp .LBB1_6
.p2align 4, 0x90
.LBB1_4: # in Loop: Header=BB1_3 Depth=2
movl $1148846080, (%rbx,%rax,4) # imm = 0x447A0000
cmpq %rax, %rbp
jne .LBB1_7
.LBB1_6: # in Loop: Header=BB1_3 Depth=2
movss %xmm1, (%r13,%rax,4)
jmp .LBB1_7
.LBB1_9: # %._crit_edge93
movslq 56(%rsp), %r13 # 4-byte Folded Reload
leaq 16(%rsp), %rdi
movq %r13, %rsi
movq %rcx, %rbx
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movl $4, %esi
movl $1, %edx
callq hipMallocManaged
movq 32(%rsp), %rax
movl $0, (%rax)
movq 8(%rsp), %rdi
movq 24(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 72(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq 16(%rsp), %rsi
movq %r13, %rdx
movl $3, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq 64(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movl %ebx, %eax
movl $4294967295, %ecx # imm = 0xFFFFFFFF
leaq (%rcx,%rax), %rbp
incq %rbp
movabsq $4591870180066957722, %r15 # imm = 0x3FB999999999999A
leaq 168(%rsp), %r12
xorl %ebx, %ebx
jmp .LBB1_10
.p2align 4, 0x90
.LBB1_12: # in Loop: Header=BB1_10 Depth=1
callq hipDeviceSynchronize
movq 16(%rsp), %rsi
movq %r14, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi # 8-byte Reload
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
movq %r13, %rdx
movl $3, %ecx
callq hipMemcpy
movq 32(%rsp), %rax
movss (%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
incl %ebx
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
ucomisd %xmm0, %xmm1
ja .LBB1_13
.LBB1_10: # =>This Inner Loop Header: Depth=1
movq 32(%rsp), %rax
movl $0, (%rax)
movq %rbp, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_12
# %bb.11: # in Loop: Header=BB1_10 Depth=1
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 48(%rsp), %rdx
movq 32(%rsp), %rsi
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movq %r15, 144(%rsp)
movq %rsi, 136(%rsp)
movq %r12, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 144(%rsp), %rax
movq %rax, 200(%rsp)
leaq 136(%rsp), %rax
movq %rax, 208(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
movl $_Z13TwoDimPoissonPfS_S_dS_, %edi
leaq 176(%rsp), %r9
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_12
.LBB1_13:
movq %rbx, %rbp
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi # 8-byte Reload
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rdx # 8-byte Reload
testl %edx, %edx
jle .LBB1_18
# %bb.14: # %.preheader.lr.ph
movl %edx, %ebx
xorl %r14d, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_15: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_16 Depth 2
movl %r14d, %eax
movq 24(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_16: # Parent Loop BB1_15 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r13
cmpq %r13, %rbx
jne .LBB1_16
# %bb.17: # %._crit_edge96
# in Loop: Header=BB1_15 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
movq 40(%rsp), %rdx # 8-byte Reload
addl %edx, %r14d
cmpq %rbx, %r15
jne .LBB1_15
.LBB1_18: # %._crit_edge98
movl $.L.str.2, %edi
movl %ebp, %esi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13TwoDimPoissonPfS_S_dS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13TwoDimPoissonPfS_S_dS_,@object # @_Z13TwoDimPoissonPfS_S_dS_
.section .rodata,"a",@progbits
.globl _Z13TwoDimPoissonPfS_S_dS_
.p2align 3, 0x0
_Z13TwoDimPoissonPfS_S_dS_:
.quad _Z28__device_stub__TwoDimPoissonPfS_S_dS_
.size _Z13TwoDimPoissonPfS_S_dS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%-10.3f "
.size .L.str, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nSteps: %d \nn: %d\n"
.size .L.str.2, 19
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13TwoDimPoissonPfS_S_dS_"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__TwoDimPoissonPfS_S_dS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13TwoDimPoissonPfS_S_dS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
#include <time.h>
#define lim 99
#define threads 10
void print(int *w){
for(int i=0; i<lim; i++){
printf("%d\n", w[i]);
}
}
void fillVector(int *w){
for(int i=0; i<lim; i++){
w[i]=i;
}
}
__global__
void add(int *d_x, int *d_y, int *d_z){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<lim){
d_z[i] = d_x[i] + d_y[i];
}
}
int main(int argc, char const *argv[])
{
int *x = (int*)malloc(lim*sizeof(int));
int *y = (int*)malloc(lim*sizeof(int));
int *z = (int*)malloc(lim*sizeof(int));
fillVector(x);
fillVector(y);
int *d_x, *d_y, *d_z;
clock_t begin, end;
double time_spent;
begin = clock();
cudaMalloc((void**)&d_x, lim*sizeof(int));
cudaMalloc((void**)&d_y, lim*sizeof(int));
cudaMalloc((void**)&d_z, lim*sizeof(int));
cudaMemcpy(d_x, x, lim*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_y, y, lim*sizeof(int), cudaMemcpyHostToDevice);
int blocks = ceil((float)lim/threads);
//printf("%d",blocks);
add<<<blocks,threads>>>(d_x, d_y, d_z);
cudaMemcpy(z, d_z, lim*sizeof(int), cudaMemcpyDeviceToHost);
//print(z);
cudaFree(d_x);
cudaFree(d_y);
cudaFree(d_z);
end = clock();
time_spent = (double)(end - begin) / CLOCKS_PER_SEC;
printf("%lf\n", time_spent);
free(x);
free(y);
free(z);
return 0;
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R6, 0x62, PT ; /* 0x000000620600780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#include <time.h>
#define lim 99
#define threads 10
void print(int *w){
for(int i=0; i<lim; i++){
printf("%d\n", w[i]);
}
}
void fillVector(int *w){
for(int i=0; i<lim; i++){
w[i]=i;
}
}
__global__
void add(int *d_x, int *d_y, int *d_z){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<lim){
d_z[i] = d_x[i] + d_y[i];
}
}
int main(int argc, char const *argv[])
{
int *x = (int*)malloc(lim*sizeof(int));
int *y = (int*)malloc(lim*sizeof(int));
int *z = (int*)malloc(lim*sizeof(int));
fillVector(x);
fillVector(y);
int *d_x, *d_y, *d_z;
clock_t begin, end;
double time_spent;
begin = clock();
cudaMalloc((void**)&d_x, lim*sizeof(int));
cudaMalloc((void**)&d_y, lim*sizeof(int));
cudaMalloc((void**)&d_z, lim*sizeof(int));
cudaMemcpy(d_x, x, lim*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_y, y, lim*sizeof(int), cudaMemcpyHostToDevice);
int blocks = ceil((float)lim/threads);
//printf("%d",blocks);
add<<<blocks,threads>>>(d_x, d_y, d_z);
cudaMemcpy(z, d_z, lim*sizeof(int), cudaMemcpyDeviceToHost);
//print(z);
cudaFree(d_x);
cudaFree(d_y);
cudaFree(d_z);
end = clock();
time_spent = (double)(end - begin) / CLOCKS_PER_SEC;
printf("%lf\n", time_spent);
free(x);
free(y);
free(z);
return 0;
} | .file "tmpxft_0001ed39_00000000-6_threaded.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\n"
.text
.globl _Z5printPi
.type _Z5printPi, @function
_Z5printPi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
leaq 396(%rdi), %r12
leaq .LC0(%rip), %rbp
.L4:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L4
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z5printPi, .-_Z5printPi
.globl _Z10fillVectorPi
.type _Z10fillVectorPi, @function
_Z10fillVectorPi:
.LFB2058:
.cfi_startproc
endbr64
movl $0, %eax
.L8:
movl %eax, (%rdi,%rax,4)
addq $1, %rax
cmpq $99, %rax
jne .L8
ret
.cfi_endproc
.LFE2058:
.size _Z10fillVectorPi, .-_Z10fillVectorPi
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1
.LC2:
.string "%lf\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $396, %edi
call malloc@PLT
movq %rax, %rbp
movl $396, %edi
call malloc@PLT
movq %rax, %rbx
movl $396, %edi
call malloc@PLT
movq %rax, %r12
movq %rbp, %rdi
call _Z10fillVectorPi
movq %rbx, %rdi
call _Z10fillVectorPi
call clock@PLT
movq %rax, %r13
leaq 8(%rsp), %rdi
movl $396, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $396, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $396, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $396, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $396, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $10, 44(%rsp)
movl $1, 48(%rsp)
movl $10, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L19:
movl $2, %ecx
movl $396, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
call clock@PLT
subq %r13, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC1(%rip), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L19
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#include <time.h>
#define lim 99
#define threads 10
void print(int *w){
for(int i=0; i<lim; i++){
printf("%d\n", w[i]);
}
}
void fillVector(int *w){
for(int i=0; i<lim; i++){
w[i]=i;
}
}
__global__
void add(int *d_x, int *d_y, int *d_z){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<lim){
d_z[i] = d_x[i] + d_y[i];
}
}
int main(int argc, char const *argv[])
{
int *x = (int*)malloc(lim*sizeof(int));
int *y = (int*)malloc(lim*sizeof(int));
int *z = (int*)malloc(lim*sizeof(int));
fillVector(x);
fillVector(y);
int *d_x, *d_y, *d_z;
clock_t begin, end;
double time_spent;
begin = clock();
cudaMalloc((void**)&d_x, lim*sizeof(int));
cudaMalloc((void**)&d_y, lim*sizeof(int));
cudaMalloc((void**)&d_z, lim*sizeof(int));
cudaMemcpy(d_x, x, lim*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_y, y, lim*sizeof(int), cudaMemcpyHostToDevice);
int blocks = ceil((float)lim/threads);
//printf("%d",blocks);
add<<<blocks,threads>>>(d_x, d_y, d_z);
cudaMemcpy(z, d_z, lim*sizeof(int), cudaMemcpyDeviceToHost);
//print(z);
cudaFree(d_x);
cudaFree(d_y);
cudaFree(d_z);
end = clock();
time_spent = (double)(end - begin) / CLOCKS_PER_SEC;
printf("%lf\n", time_spent);
free(x);
free(y);
free(z);
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <time.h>
#define lim 99
#define threads 10
void print(int *w){
for(int i=0; i<lim; i++){
printf("%d\n", w[i]);
}
}
void fillVector(int *w){
for(int i=0; i<lim; i++){
w[i]=i;
}
}
__global__
void add(int *d_x, int *d_y, int *d_z){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<lim){
d_z[i] = d_x[i] + d_y[i];
}
}
int main(int argc, char const *argv[])
{
int *x = (int*)malloc(lim*sizeof(int));
int *y = (int*)malloc(lim*sizeof(int));
int *z = (int*)malloc(lim*sizeof(int));
fillVector(x);
fillVector(y);
int *d_x, *d_y, *d_z;
clock_t begin, end;
double time_spent;
begin = clock();
hipMalloc((void**)&d_x, lim*sizeof(int));
hipMalloc((void**)&d_y, lim*sizeof(int));
hipMalloc((void**)&d_z, lim*sizeof(int));
hipMemcpy(d_x, x, lim*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_y, y, lim*sizeof(int), hipMemcpyHostToDevice);
int blocks = ceil((float)lim/threads);
//printf("%d",blocks);
add<<<blocks,threads>>>(d_x, d_y, d_z);
hipMemcpy(z, d_z, lim*sizeof(int), hipMemcpyDeviceToHost);
//print(z);
hipFree(d_x);
hipFree(d_y);
hipFree(d_z);
end = clock();
time_spent = (double)(end - begin) / CLOCKS_PER_SEC;
printf("%lf\n", time_spent);
free(x);
free(y);
free(z);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <time.h>
#define lim 99
#define threads 10
void print(int *w){
for(int i=0; i<lim; i++){
printf("%d\n", w[i]);
}
}
void fillVector(int *w){
for(int i=0; i<lim; i++){
w[i]=i;
}
}
__global__
void add(int *d_x, int *d_y, int *d_z){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<lim){
d_z[i] = d_x[i] + d_y[i];
}
}
int main(int argc, char const *argv[])
{
int *x = (int*)malloc(lim*sizeof(int));
int *y = (int*)malloc(lim*sizeof(int));
int *z = (int*)malloc(lim*sizeof(int));
fillVector(x);
fillVector(y);
int *d_x, *d_y, *d_z;
clock_t begin, end;
double time_spent;
begin = clock();
hipMalloc((void**)&d_x, lim*sizeof(int));
hipMalloc((void**)&d_y, lim*sizeof(int));
hipMalloc((void**)&d_z, lim*sizeof(int));
hipMemcpy(d_x, x, lim*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_y, y, lim*sizeof(int), hipMemcpyHostToDevice);
int blocks = ceil((float)lim/threads);
//printf("%d",blocks);
add<<<blocks,threads>>>(d_x, d_y, d_z);
hipMemcpy(z, d_z, lim*sizeof(int), hipMemcpyDeviceToHost);
//print(z);
hipFree(d_x);
hipFree(d_y);
hipFree(d_z);
end = clock();
time_spent = (double)(end - begin) / CLOCKS_PER_SEC;
printf("%lf\n", time_spent);
free(x);
free(y);
free(z);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x63, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <time.h>
#define lim 99
#define threads 10
void print(int *w){
for(int i=0; i<lim; i++){
printf("%d\n", w[i]);
}
}
void fillVector(int *w){
for(int i=0; i<lim; i++){
w[i]=i;
}
}
__global__
void add(int *d_x, int *d_y, int *d_z){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<lim){
d_z[i] = d_x[i] + d_y[i];
}
}
int main(int argc, char const *argv[])
{
int *x = (int*)malloc(lim*sizeof(int));
int *y = (int*)malloc(lim*sizeof(int));
int *z = (int*)malloc(lim*sizeof(int));
fillVector(x);
fillVector(y);
int *d_x, *d_y, *d_z;
clock_t begin, end;
double time_spent;
begin = clock();
hipMalloc((void**)&d_x, lim*sizeof(int));
hipMalloc((void**)&d_y, lim*sizeof(int));
hipMalloc((void**)&d_z, lim*sizeof(int));
hipMemcpy(d_x, x, lim*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_y, y, lim*sizeof(int), hipMemcpyHostToDevice);
int blocks = ceil((float)lim/threads);
//printf("%d",blocks);
add<<<blocks,threads>>>(d_x, d_y, d_z);
hipMemcpy(z, d_z, lim*sizeof(int), hipMemcpyDeviceToHost);
//print(z);
hipFree(d_x);
hipFree(d_y);
hipFree(d_z);
end = clock();
time_spent = (double)(end - begin) / CLOCKS_PER_SEC;
printf("%lf\n", time_spent);
free(x);
free(y);
free(z);
return 0;
} | .text
.file "threaded.hip"
.globl _Z5printPi # -- Begin function _Z5printPi
.p2align 4, 0x90
.type _Z5printPi,@function
_Z5printPi: # @_Z5printPi
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $99, %r14
jne .LBB0_1
# %bb.2:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z5printPi, .Lfunc_end0-_Z5printPi
.cfi_endproc
# -- End function
.globl _Z10fillVectorPi # -- Begin function _Z10fillVectorPi
.p2align 4, 0x90
.type _Z10fillVectorPi,@function
_Z10fillVectorPi: # @_Z10fillVectorPi
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%rdi,%rax,4)
incq %rax
cmpq $99, %rax
jne .LBB1_1
# %bb.2:
retq
.Lfunc_end1:
.size _Z10fillVectorPi, .Lfunc_end1-_Z10fillVectorPi
.cfi_endproc
# -- End function
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end2-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $396, %edi # imm = 0x18C
callq malloc
movq %rax, %rbx
movl $396, %edi # imm = 0x18C
callq malloc
movq %rax, %r14
movl $396, %edi # imm = 0x18C
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rax,4)
incq %rax
cmpq $99, %rax
jne .LBB3_1
# %bb.2: # %_Z10fillVectorPi.exit.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_3: # %_Z10fillVectorPi.exit
# =>This Inner Loop Header: Depth=1
movl %eax, (%r14,%rax,4)
incq %rax
cmpq $99, %rax
jne .LBB3_3
# %bb.4: # %_Z10fillVectorPi.exit16
callq clock
movq %rax, %r12
leaq 16(%rsp), %rdi
movl $396, %esi # imm = 0x18C
callq hipMalloc
leaq 8(%rsp), %rdi
movl $396, %esi # imm = 0x18C
callq hipMalloc
movq %rsp, %rdi
movl $396, %esi # imm = 0x18C
callq hipMalloc
movq 16(%rsp), %rdi
movl $396, %edx # imm = 0x18C
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $396, %edx # imm = 0x18C
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967306, %rdi # imm = 0x10000000A
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
movq (%rsp), %rsi
movl $396, %edx # imm = 0x18C
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
callq clock
subq %r12, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI3_0(%rip), %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\n"
.size .L.str, 4
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%lf\n"
.size .L.str.1, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R6, 0x62, PT ; /* 0x000000620600780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x63, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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