system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001ed39_00000000-6_threaded.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\n"
.text
.globl _Z5printPi
.type _Z5printPi, @function
_Z5printPi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
leaq 396(%rdi), %r12
leaq .LC0(%rip), %rbp
.L4:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L4
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z5printPi, .-_Z5printPi
.globl _Z10fillVectorPi
.type _Z10fillVectorPi, @function
_Z10fillVectorPi:
.LFB2058:
.cfi_startproc
endbr64
movl $0, %eax
.L8:
movl %eax, (%rdi,%rax,4)
addq $1, %rax
cmpq $99, %rax
jne .L8
ret
.cfi_endproc
.LFE2058:
.size _Z10fillVectorPi, .-_Z10fillVectorPi
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1
.LC2:
.string "%lf\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $396, %edi
call malloc@PLT
movq %rax, %rbp
movl $396, %edi
call malloc@PLT
movq %rax, %rbx
movl $396, %edi
call malloc@PLT
movq %rax, %r12
movq %rbp, %rdi
call _Z10fillVectorPi
movq %rbx, %rdi
call _Z10fillVectorPi
call clock@PLT
movq %rax, %r13
leaq 8(%rsp), %rdi
movl $396, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $396, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $396, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $396, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $396, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $10, 44(%rsp)
movl $1, 48(%rsp)
movl $10, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L19:
movl $2, %ecx
movl $396, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
call clock@PLT
subq %r13, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC1(%rip), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L19
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "threaded.hip"
.globl _Z5printPi # -- Begin function _Z5printPi
.p2align 4, 0x90
.type _Z5printPi,@function
_Z5printPi: # @_Z5printPi
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $99, %r14
jne .LBB0_1
# %bb.2:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z5printPi, .Lfunc_end0-_Z5printPi
.cfi_endproc
# -- End function
.globl _Z10fillVectorPi # -- Begin function _Z10fillVectorPi
.p2align 4, 0x90
.type _Z10fillVectorPi,@function
_Z10fillVectorPi: # @_Z10fillVectorPi
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%rdi,%rax,4)
incq %rax
cmpq $99, %rax
jne .LBB1_1
# %bb.2:
retq
.Lfunc_end1:
.size _Z10fillVectorPi, .Lfunc_end1-_Z10fillVectorPi
.cfi_endproc
# -- End function
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end2-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $396, %edi # imm = 0x18C
callq malloc
movq %rax, %rbx
movl $396, %edi # imm = 0x18C
callq malloc
movq %rax, %r14
movl $396, %edi # imm = 0x18C
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rax,4)
incq %rax
cmpq $99, %rax
jne .LBB3_1
# %bb.2: # %_Z10fillVectorPi.exit.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_3: # %_Z10fillVectorPi.exit
# =>This Inner Loop Header: Depth=1
movl %eax, (%r14,%rax,4)
incq %rax
cmpq $99, %rax
jne .LBB3_3
# %bb.4: # %_Z10fillVectorPi.exit16
callq clock
movq %rax, %r12
leaq 16(%rsp), %rdi
movl $396, %esi # imm = 0x18C
callq hipMalloc
leaq 8(%rsp), %rdi
movl $396, %esi # imm = 0x18C
callq hipMalloc
movq %rsp, %rdi
movl $396, %esi # imm = 0x18C
callq hipMalloc
movq 16(%rsp), %rdi
movl $396, %edx # imm = 0x18C
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $396, %edx # imm = 0x18C
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967306, %rdi # imm = 0x10000000A
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
movq (%rsp), %rsi
movl $396, %edx # imm = 0x18C
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
callq clock
subq %r12, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI3_0(%rip), %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\n"
.size .L.str, 4
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%lf\n"
.size .L.str.1, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/* https://zxi.mytechroad.com/blog/dynamic-programming/leetcode-730-count-different-palindromic-subsequences/ */
long kMod = 1000000007;
__global__ void setData(int *dp, int n) {
for(int i = blockIdx.x * blockDim.x + threadIdx.x; i < n; i += blockDim.x * gridDim.x) {
dp[i * n + i] = 1;
}
} | code for sm_80
Function : _Z7setDataPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R7, 0x1 ; /* 0x0000000100077802 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ MOV R9, c[0x0][0x0] ; /* 0x0000000000097a02 */
/* 0x000fc60000000f00 */
/*00a0*/ IMAD R2, R0, c[0x0][0x168], R0.reuse ; /* 0x00005a0000027a24 */
/* 0x101fe400078e0200 */
/*00b0*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fe400078e0200 */
/*00c0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc600078e0205 */
/*00d0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe40003f06270 */
/*00e0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001f6000c101904 */
/*00f0*/ @!P0 BRA 0xa0 ; /* 0xffffffa000008947 */
/* 0x000fea000383ffff */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/* https://zxi.mytechroad.com/blog/dynamic-programming/leetcode-730-count-different-palindromic-subsequences/ */
long kMod = 1000000007;
__global__ void setData(int *dp, int n) {
for(int i = blockIdx.x * blockDim.x + threadIdx.x; i < n; i += blockDim.x * gridDim.x) {
dp[i * n + i] = 1;
}
} | .file "tmpxft_000bea59_00000000-6_setData.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z7setDataPiiPii
.type _Z27__device_stub__Z7setDataPiiPii, @function
_Z27__device_stub__Z7setDataPiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7setDataPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z7setDataPiiPii, .-_Z27__device_stub__Z7setDataPiiPii
.globl _Z7setDataPii
.type _Z7setDataPii, @function
_Z7setDataPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7setDataPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7setDataPii, .-_Z7setDataPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7setDataPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7setDataPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl kMod
.data
.align 8
.type kMod, @object
.size kMod, 8
kMod:
.quad 1000000007
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/* https://zxi.mytechroad.com/blog/dynamic-programming/leetcode-730-count-different-palindromic-subsequences/ */
long kMod = 1000000007;
__global__ void setData(int *dp, int n) {
for(int i = blockIdx.x * blockDim.x + threadIdx.x; i < n; i += blockDim.x * gridDim.x) {
dp[i * n + i] = 1;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
/* https://zxi.mytechroad.com/blog/dynamic-programming/leetcode-730-count-different-palindromic-subsequences/ */
long kMod = 1000000007;
__global__ void setData(int *dp, int n) {
for(int i = blockIdx.x * blockDim.x + threadIdx.x; i < n; i += blockDim.x * gridDim.x) {
dp[i * n + i] = 1;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/* https://zxi.mytechroad.com/blog/dynamic-programming/leetcode-730-count-different-palindromic-subsequences/ */
long kMod = 1000000007;
__global__ void setData(int *dp, int n) {
for(int i = blockIdx.x * blockDim.x + threadIdx.x; i < n; i += blockDim.x * gridDim.x) {
dp[i * n + i] = 1;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7setDataPii
.globl _Z7setDataPii
.p2align 8
.type _Z7setDataPii,@function
_Z7setDataPii:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x8
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_3
s_load_b32 s6, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, v1, s4, v[1:2]
v_mov_b32_e32 v0, 1
s_add_i32 s0, s4, 1
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s6, s5
s_mov_b32 s6, 0
s_mul_i32 s5, s1, s0
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_add_nc_u32_e32 v1, s1, v1
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cmp_le_i32_e32 vcc_lo, s4, v1
v_add_nc_u32_e32 v2, s5, v2
s_or_b32 s6, vcc_lo, s6
v_add_co_u32 v3, s0, s2, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s0, s3, v4, s0
global_store_b32 v[3:4], v0, off
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7setDataPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7setDataPii, .Lfunc_end0-_Z7setDataPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7setDataPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7setDataPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/* https://zxi.mytechroad.com/blog/dynamic-programming/leetcode-730-count-different-palindromic-subsequences/ */
long kMod = 1000000007;
__global__ void setData(int *dp, int n) {
for(int i = blockIdx.x * blockDim.x + threadIdx.x; i < n; i += blockDim.x * gridDim.x) {
dp[i * n + i] = 1;
}
} | .text
.file "setData.hip"
.globl _Z22__device_stub__setDataPii # -- Begin function _Z22__device_stub__setDataPii
.p2align 4, 0x90
.type _Z22__device_stub__setDataPii,@function
_Z22__device_stub__setDataPii: # @_Z22__device_stub__setDataPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7setDataPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__setDataPii, .Lfunc_end0-_Z22__device_stub__setDataPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7setDataPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type kMod,@object # @kMod
.data
.globl kMod
.p2align 3, 0x0
kMod:
.quad 1000000007 # 0x3b9aca07
.size kMod, 8
.type _Z7setDataPii,@object # @_Z7setDataPii
.section .rodata,"a",@progbits
.globl _Z7setDataPii
.p2align 3, 0x0
_Z7setDataPii:
.quad _Z22__device_stub__setDataPii
.size _Z7setDataPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7setDataPii"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__setDataPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7setDataPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7setDataPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R7, 0x1 ; /* 0x0000000100077802 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ MOV R9, c[0x0][0x0] ; /* 0x0000000000097a02 */
/* 0x000fc60000000f00 */
/*00a0*/ IMAD R2, R0, c[0x0][0x168], R0.reuse ; /* 0x00005a0000027a24 */
/* 0x101fe400078e0200 */
/*00b0*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fe400078e0200 */
/*00c0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc600078e0205 */
/*00d0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe40003f06270 */
/*00e0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001f6000c101904 */
/*00f0*/ @!P0 BRA 0xa0 ; /* 0xffffffa000008947 */
/* 0x000fea000383ffff */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7setDataPii
.globl _Z7setDataPii
.p2align 8
.type _Z7setDataPii,@function
_Z7setDataPii:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x8
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_3
s_load_b32 s6, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, v1, s4, v[1:2]
v_mov_b32_e32 v0, 1
s_add_i32 s0, s4, 1
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s6, s5
s_mov_b32 s6, 0
s_mul_i32 s5, s1, s0
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_add_nc_u32_e32 v1, s1, v1
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cmp_le_i32_e32 vcc_lo, s4, v1
v_add_nc_u32_e32 v2, s5, v2
s_or_b32 s6, vcc_lo, s6
v_add_co_u32 v3, s0, s2, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s0, s3, v4, s0
global_store_b32 v[3:4], v0, off
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7setDataPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7setDataPii, .Lfunc_end0-_Z7setDataPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7setDataPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7setDataPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000bea59_00000000-6_setData.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z7setDataPiiPii
.type _Z27__device_stub__Z7setDataPiiPii, @function
_Z27__device_stub__Z7setDataPiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7setDataPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z7setDataPiiPii, .-_Z27__device_stub__Z7setDataPiiPii
.globl _Z7setDataPii
.type _Z7setDataPii, @function
_Z7setDataPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7setDataPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7setDataPii, .-_Z7setDataPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7setDataPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7setDataPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl kMod
.data
.align 8
.type kMod, @object
.size kMod, 8
kMod:
.quad 1000000007
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "setData.hip"
.globl _Z22__device_stub__setDataPii # -- Begin function _Z22__device_stub__setDataPii
.p2align 4, 0x90
.type _Z22__device_stub__setDataPii,@function
_Z22__device_stub__setDataPii: # @_Z22__device_stub__setDataPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7setDataPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__setDataPii, .Lfunc_end0-_Z22__device_stub__setDataPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7setDataPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type kMod,@object # @kMod
.data
.globl kMod
.p2align 3, 0x0
kMod:
.quad 1000000007 # 0x3b9aca07
.size kMod, 8
.type _Z7setDataPii,@object # @_Z7setDataPii
.section .rodata,"a",@progbits
.globl _Z7setDataPii
.p2align 3, 0x0
_Z7setDataPii:
.quad _Z22__device_stub__setDataPii
.size _Z7setDataPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7setDataPii"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__setDataPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7setDataPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define BLOCK_SIZE 32
__device__ float deriv_error(float d_output, float d_actual, float d_weights )
{
//float de_dout = d_output - d_actual; //previous derivative error
//float dout_dnet = d_output[] * (1-output[i]);
//de_dout * dout_dnet; // * sum(weights);
return 1.0f;
}
__global__ void backPropagate(float *deriv_err, float *prev_deriv_err, float *wieghts, float *output)
{
//use map operation to multiply d_output[i]*(1-output[i])*prev_deriv_error[i]*weight[i]
//use gather operation to gather all these together.
} | code for sm_80
Function : _Z13backPropagatePfS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define BLOCK_SIZE 32
__device__ float deriv_error(float d_output, float d_actual, float d_weights )
{
//float de_dout = d_output - d_actual; //previous derivative error
//float dout_dnet = d_output[] * (1-output[i]);
//de_dout * dout_dnet; // * sum(weights);
return 1.0f;
}
__global__ void backPropagate(float *deriv_err, float *prev_deriv_err, float *wieghts, float *output)
{
//use map operation to multiply d_output[i]*(1-output[i])*prev_deriv_error[i]*weight[i]
//use gather operation to gather all these together.
} | .file "tmpxft_00150b8d_00000000-6_backPropagate.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11deriv_errorfff
.type _Z11deriv_errorfff, @function
_Z11deriv_errorfff:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z11deriv_errorfff, .-_Z11deriv_errorfff
.globl _Z39__device_stub__Z13backPropagatePfS_S_S_PfS_S_S_
.type _Z39__device_stub__Z13backPropagatePfS_S_S_PfS_S_S_, @function
_Z39__device_stub__Z13backPropagatePfS_S_S_PfS_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13backPropagatePfS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z39__device_stub__Z13backPropagatePfS_S_S_PfS_S_S_, .-_Z39__device_stub__Z13backPropagatePfS_S_S_PfS_S_S_
.globl _Z13backPropagatePfS_S_S_
.type _Z13backPropagatePfS_S_S_, @function
_Z13backPropagatePfS_S_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z13backPropagatePfS_S_S_PfS_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z13backPropagatePfS_S_S_, .-_Z13backPropagatePfS_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13backPropagatePfS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13backPropagatePfS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define BLOCK_SIZE 32
__device__ float deriv_error(float d_output, float d_actual, float d_weights )
{
//float de_dout = d_output - d_actual; //previous derivative error
//float dout_dnet = d_output[] * (1-output[i]);
//de_dout * dout_dnet; // * sum(weights);
return 1.0f;
}
__global__ void backPropagate(float *deriv_err, float *prev_deriv_err, float *wieghts, float *output)
{
//use map operation to multiply d_output[i]*(1-output[i])*prev_deriv_error[i]*weight[i]
//use gather operation to gather all these together.
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define BLOCK_SIZE 32
__device__ float deriv_error(float d_output, float d_actual, float d_weights )
{
//float de_dout = d_output - d_actual; //previous derivative error
//float dout_dnet = d_output[] * (1-output[i]);
//de_dout * dout_dnet; // * sum(weights);
return 1.0f;
}
__global__ void backPropagate(float *deriv_err, float *prev_deriv_err, float *wieghts, float *output)
{
//use map operation to multiply d_output[i]*(1-output[i])*prev_deriv_error[i]*weight[i]
//use gather operation to gather all these together.
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define BLOCK_SIZE 32
__device__ float deriv_error(float d_output, float d_actual, float d_weights )
{
//float de_dout = d_output - d_actual; //previous derivative error
//float dout_dnet = d_output[] * (1-output[i]);
//de_dout * dout_dnet; // * sum(weights);
return 1.0f;
}
__global__ void backPropagate(float *deriv_err, float *prev_deriv_err, float *wieghts, float *output)
{
//use map operation to multiply d_output[i]*(1-output[i])*prev_deriv_error[i]*weight[i]
//use gather operation to gather all these together.
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13backPropagatePfS_S_S_
.globl _Z13backPropagatePfS_S_S_
.p2align 8
.type _Z13backPropagatePfS_S_S_,@function
_Z13backPropagatePfS_S_S_:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13backPropagatePfS_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13backPropagatePfS_S_S_, .Lfunc_end0-_Z13backPropagatePfS_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13backPropagatePfS_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z13backPropagatePfS_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define BLOCK_SIZE 32
__device__ float deriv_error(float d_output, float d_actual, float d_weights )
{
//float de_dout = d_output - d_actual; //previous derivative error
//float dout_dnet = d_output[] * (1-output[i]);
//de_dout * dout_dnet; // * sum(weights);
return 1.0f;
}
__global__ void backPropagate(float *deriv_err, float *prev_deriv_err, float *wieghts, float *output)
{
//use map operation to multiply d_output[i]*(1-output[i])*prev_deriv_error[i]*weight[i]
//use gather operation to gather all these together.
} | .text
.file "backPropagate.hip"
.globl _Z28__device_stub__backPropagatePfS_S_S_ # -- Begin function _Z28__device_stub__backPropagatePfS_S_S_
.p2align 4, 0x90
.type _Z28__device_stub__backPropagatePfS_S_S_,@function
_Z28__device_stub__backPropagatePfS_S_S_: # @_Z28__device_stub__backPropagatePfS_S_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13backPropagatePfS_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__backPropagatePfS_S_S_, .Lfunc_end0-_Z28__device_stub__backPropagatePfS_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13backPropagatePfS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13backPropagatePfS_S_S_,@object # @_Z13backPropagatePfS_S_S_
.section .rodata,"a",@progbits
.globl _Z13backPropagatePfS_S_S_
.p2align 3, 0x0
_Z13backPropagatePfS_S_S_:
.quad _Z28__device_stub__backPropagatePfS_S_S_
.size _Z13backPropagatePfS_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13backPropagatePfS_S_S_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__backPropagatePfS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13backPropagatePfS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13backPropagatePfS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13backPropagatePfS_S_S_
.globl _Z13backPropagatePfS_S_S_
.p2align 8
.type _Z13backPropagatePfS_S_S_,@function
_Z13backPropagatePfS_S_S_:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13backPropagatePfS_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13backPropagatePfS_S_S_, .Lfunc_end0-_Z13backPropagatePfS_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13backPropagatePfS_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z13backPropagatePfS_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00150b8d_00000000-6_backPropagate.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11deriv_errorfff
.type _Z11deriv_errorfff, @function
_Z11deriv_errorfff:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z11deriv_errorfff, .-_Z11deriv_errorfff
.globl _Z39__device_stub__Z13backPropagatePfS_S_S_PfS_S_S_
.type _Z39__device_stub__Z13backPropagatePfS_S_S_PfS_S_S_, @function
_Z39__device_stub__Z13backPropagatePfS_S_S_PfS_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13backPropagatePfS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z39__device_stub__Z13backPropagatePfS_S_S_PfS_S_S_, .-_Z39__device_stub__Z13backPropagatePfS_S_S_PfS_S_S_
.globl _Z13backPropagatePfS_S_S_
.type _Z13backPropagatePfS_S_S_, @function
_Z13backPropagatePfS_S_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z13backPropagatePfS_S_S_PfS_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z13backPropagatePfS_S_S_, .-_Z13backPropagatePfS_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13backPropagatePfS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13backPropagatePfS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "backPropagate.hip"
.globl _Z28__device_stub__backPropagatePfS_S_S_ # -- Begin function _Z28__device_stub__backPropagatePfS_S_S_
.p2align 4, 0x90
.type _Z28__device_stub__backPropagatePfS_S_S_,@function
_Z28__device_stub__backPropagatePfS_S_S_: # @_Z28__device_stub__backPropagatePfS_S_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13backPropagatePfS_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__backPropagatePfS_S_S_, .Lfunc_end0-_Z28__device_stub__backPropagatePfS_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13backPropagatePfS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13backPropagatePfS_S_S_,@object # @_Z13backPropagatePfS_S_S_
.section .rodata,"a",@progbits
.globl _Z13backPropagatePfS_S_S_
.p2align 3, 0x0
_Z13backPropagatePfS_S_S_:
.quad _Z28__device_stub__backPropagatePfS_S_S_
.size _Z13backPropagatePfS_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13backPropagatePfS_S_S_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__backPropagatePfS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13backPropagatePfS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void diff_reduce(double *dev_w, double *feat, double *pos, int feat_dim, int pos_dim, int par0, int par1, int n_patch)
{
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
double feat_dist = 0.0; // running entry sum of d_ij
double pos_dist = 0.0; // running entry sum of f_ij
int feat_offi = i * feat_dim; // offset of x_i
int feat_offj = j * feat_dim; // offset of x_j
int pos_offi = i * pos_dim; // offset of p_i
int pos_offj = j * pos_dim; // offset of p_j
double feat_i, feat_j, pos_i, pos_j;
// temporary local variables for entry sum calculation
int k;
if (i == j || i >= n_patch || j >= n_patch)
return;
/* thread (i, j) computes W_ij */
// get the k-th element of difference vector d_ij
// and add it to feat_dist
for (k = 0; k < feat_dim; k++) {
feat_i = feat[feat_offi + k];
feat_j = feat[feat_offj + k];
feat_dist += (feat_i - feat_j) * (feat_i - feat_j);
}
// get the k-th element of difference vector f_ij
// and add it to pos_dist
for (k = 0; k < pos_dim; k++) {
pos_i = pos[pos_offi + k];
pos_j = pos[pos_offj + k];
pos_dist += (pos_i - pos_j) * (pos_i - pos_j);
}
dev_w[i + j * n_patch]
= exp( -feat_dist / (feat_dim * par0 * par0))
* exp( -pos_dist / (pos_dim * par1 * par1));
} | .file "tmpxft_0016b18a_00000000-6_diff_reduce.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z11diff_reducePdS_S_iiiiiPdS_S_iiiii
.type _Z40__device_stub__Z11diff_reducePdS_S_iiiiiPdS_S_iiiii, @function
_Z40__device_stub__Z11diff_reducePdS_S_iiiiiPdS_S_iiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11diff_reducePdS_S_iiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z11diff_reducePdS_S_iiiiiPdS_S_iiiii, .-_Z40__device_stub__Z11diff_reducePdS_S_iiiiiPdS_S_iiiii
.globl _Z11diff_reducePdS_S_iiiii
.type _Z11diff_reducePdS_S_iiiii, @function
_Z11diff_reducePdS_S_iiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z40__device_stub__Z11diff_reducePdS_S_iiiiiPdS_S_iiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11diff_reducePdS_S_iiiii, .-_Z11diff_reducePdS_S_iiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11diff_reducePdS_S_iiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11diff_reducePdS_S_iiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void diff_reduce(double *dev_w, double *feat, double *pos, int feat_dim, int pos_dim, int par0, int par1, int n_patch)
{
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
double feat_dist = 0.0; // running entry sum of d_ij
double pos_dist = 0.0; // running entry sum of f_ij
int feat_offi = i * feat_dim; // offset of x_i
int feat_offj = j * feat_dim; // offset of x_j
int pos_offi = i * pos_dim; // offset of p_i
int pos_offj = j * pos_dim; // offset of p_j
double feat_i, feat_j, pos_i, pos_j;
// temporary local variables for entry sum calculation
int k;
if (i == j || i >= n_patch || j >= n_patch)
return;
/* thread (i, j) computes W_ij */
// get the k-th element of difference vector d_ij
// and add it to feat_dist
for (k = 0; k < feat_dim; k++) {
feat_i = feat[feat_offi + k];
feat_j = feat[feat_offj + k];
feat_dist += (feat_i - feat_j) * (feat_i - feat_j);
}
// get the k-th element of difference vector f_ij
// and add it to pos_dist
for (k = 0; k < pos_dim; k++) {
pos_i = pos[pos_offi + k];
pos_j = pos[pos_offj + k];
pos_dist += (pos_i - pos_j) * (pos_i - pos_j);
}
dev_w[i + j * n_patch]
= exp( -feat_dist / (feat_dim * par0 * par0))
* exp( -pos_dist / (pos_dim * par1 * par1));
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void diff_reduce(double *dev_w, double *feat, double *pos, int feat_dim, int pos_dim, int par0, int par1, int n_patch)
{
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
double feat_dist = 0.0; // running entry sum of d_ij
double pos_dist = 0.0; // running entry sum of f_ij
int feat_offi = i * feat_dim; // offset of x_i
int feat_offj = j * feat_dim; // offset of x_j
int pos_offi = i * pos_dim; // offset of p_i
int pos_offj = j * pos_dim; // offset of p_j
double feat_i, feat_j, pos_i, pos_j;
// temporary local variables for entry sum calculation
int k;
if (i == j || i >= n_patch || j >= n_patch)
return;
/* thread (i, j) computes W_ij */
// get the k-th element of difference vector d_ij
// and add it to feat_dist
for (k = 0; k < feat_dim; k++) {
feat_i = feat[feat_offi + k];
feat_j = feat[feat_offj + k];
feat_dist += (feat_i - feat_j) * (feat_i - feat_j);
}
// get the k-th element of difference vector f_ij
// and add it to pos_dist
for (k = 0; k < pos_dim; k++) {
pos_i = pos[pos_offi + k];
pos_j = pos[pos_offj + k];
pos_dist += (pos_i - pos_j) * (pos_i - pos_j);
}
dev_w[i + j * n_patch]
= exp( -feat_dist / (feat_dim * par0 * par0))
* exp( -pos_dist / (pos_dim * par1 * par1));
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void diff_reduce(double *dev_w, double *feat, double *pos, int feat_dim, int pos_dim, int par0, int par1, int n_patch)
{
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
double feat_dist = 0.0; // running entry sum of d_ij
double pos_dist = 0.0; // running entry sum of f_ij
int feat_offi = i * feat_dim; // offset of x_i
int feat_offj = j * feat_dim; // offset of x_j
int pos_offi = i * pos_dim; // offset of p_i
int pos_offj = j * pos_dim; // offset of p_j
double feat_i, feat_j, pos_i, pos_j;
// temporary local variables for entry sum calculation
int k;
if (i == j || i >= n_patch || j >= n_patch)
return;
/* thread (i, j) computes W_ij */
// get the k-th element of difference vector d_ij
// and add it to feat_dist
for (k = 0; k < feat_dim; k++) {
feat_i = feat[feat_offi + k];
feat_j = feat[feat_offj + k];
feat_dist += (feat_i - feat_j) * (feat_i - feat_j);
}
// get the k-th element of difference vector f_ij
// and add it to pos_dist
for (k = 0; k < pos_dim; k++) {
pos_i = pos[pos_offi + k];
pos_j = pos[pos_offj + k];
pos_dist += (pos_i - pos_j) * (pos_i - pos_j);
}
dev_w[i + j * n_patch]
= exp( -feat_dist / (feat_dim * par0 * par0))
* exp( -pos_dist / (pos_dim * par1 * par1));
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11diff_reducePdS_S_iiiii
.globl _Z11diff_reducePdS_S_iiiii
.p2align 8
.type _Z11diff_reducePdS_S_iiiii,@function
_Z11diff_reducePdS_S_iiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s5, s[0:1], 0x28
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_max_i32_e32 v2, v0, v1
v_cmp_ne_u32_e32 vcc_lo, v0, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v2
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_10
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_4
s_load_b64 s[6:7], s[0:1], 0x8
v_mul_lo_u32 v2, v1, s3
v_mul_lo_u32 v4, v0, s3
s_mov_b32 s2, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 3, v[2:3]
v_lshlrev_b64 v[8:9], 3, v[4:5]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v7, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v9, vcc_lo
.p2align 6
.LBB0_3:
global_load_b64 v[8:9], v[6:7], off
global_load_b64 v[10:11], v[4:5], off
v_add_co_u32 v4, vcc_lo, v4, 8
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, v6, 8
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 0
s_waitcnt vmcnt(0)
v_add_f64 v[8:9], v[8:9], -v[10:11]
v_fma_f64 v[2:3], v[8:9], v[8:9], v[2:3]
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
.LBB0_5:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_8
s_load_b64 s[6:7], s[0:1], 0x10
v_mul_lo_u32 v4, v1, s2
v_mul_lo_u32 v6, v0, s2
s_mov_b32 s4, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[8:9], 3, v[4:5]
v_lshlrev_b64 v[10:11], 3, v[6:7]
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v9, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v10
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v11, vcc_lo
.p2align 6
.LBB0_7:
global_load_b64 v[10:11], v[8:9], off
global_load_b64 v[12:13], v[6:7], off
v_add_co_u32 v6, vcc_lo, v6, 8
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, v8, 8
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
s_add_i32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s4, 0
s_waitcnt vmcnt(0)
v_add_f64 v[10:11], v[10:11], -v[12:13]
v_fma_f64 v[4:5], v[10:11], v[10:11], v[4:5]
s_cbranch_scc1 .LBB0_7
s_branch .LBB0_9
.LBB0_8:
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
.LBB0_9:
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x20
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s6, s3
s_mul_i32 s2, s7, s2
s_mul_i32 s3, s3, s6
s_mul_i32 s2, s2, s7
v_cvt_f64_i32_e32 v[6:7], s3
v_cvt_f64_i32_e32 v[8:9], s2
s_mov_b32 s3, 0x3ff71547
s_mov_b32 s7, 0x3e5ade15
s_mov_b32 s6, 0x6a5dcb37
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_scale_f64 v[10:11], null, v[6:7], v[6:7], -v[2:3]
v_div_scale_f64 v[12:13], null, v[8:9], v[8:9], -v[4:5]
v_div_scale_f64 v[22:23], vcc_lo, -v[2:3], v[6:7], -v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f64_e32 v[14:15], v[10:11]
v_rcp_f64_e32 v[16:17], v[12:13]
s_waitcnt_depctr 0xfff
v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
v_div_scale_f64 v[18:19], s2, -v[4:5], v[8:9], -v[4:5]
v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[20:21], v[22:23], v[14:15]
v_mul_f64 v[24:25], v[18:19], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], -v[10:11], v[20:21], v[22:23]
v_fma_f64 v[12:13], -v[12:13], v[24:25], v[18:19]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[20:21]
s_mov_b32 vcc_lo, s2
s_mov_b32 s2, 0x652b82fe
v_div_fmas_f64 v[12:13], v[12:13], v[16:17], v[24:25]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f64 v[2:3], v[10:11], v[6:7], -v[2:3]
v_div_fixup_f64 v[4:5], v[12:13], v[8:9], -v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_f64 v[6:7], v[2:3], s[2:3]
v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[2:3]
v_mul_f64 v[8:9], v[4:5], s[2:3]
s_mov_b32 s3, 0xbfe62e42
s_mov_b32 s2, 0xfefa39ef
v_cmp_ngt_f64_e64 s4, 0xc090cc00, v[4:5]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_rndne_f64_e32 v[6:7], v[6:7]
v_rndne_f64_e32 v[8:9], v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[10:11], v[6:7], s[2:3], v[2:3]
v_cvt_i32_f64_e32 v18, v[6:7]
v_fma_f64 v[12:13], v[8:9], s[2:3], v[4:5]
s_mov_b32 s3, 0xbc7abc9e
s_mov_b32 s2, 0x3b39803f
s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
v_fma_f64 v[10:11], v[6:7], s[2:3], v[10:11]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[12:13], v[8:9], s[2:3], v[12:13]
s_mov_b32 s3, 0x3e928af3
s_mov_b32 s2, 0xfca7ab0c
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[10:11], s[6:7], s[2:3]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[16:17], v[12:13], s[6:7], s[2:3]
s_mov_b32 s3, 0x3ec71dee
s_mov_b32 s2, 0x623fde64
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[10:11], v[14:15], s[2:3]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[16:17], v[12:13], v[16:17], s[2:3]
s_mov_b32 s3, 0x3efa0199
s_mov_b32 s2, 0x7c89e6b0
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[10:11], v[14:15], s[2:3]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[16:17], v[12:13], v[16:17], s[2:3]
s_mov_b32 s3, 0x3f2a01a0
s_mov_b32 s2, 0x14761f6e
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[10:11], v[14:15], s[2:3]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[16:17], v[12:13], v[16:17], s[2:3]
s_mov_b32 s3, 0x3f56c16c
s_mov_b32 s2, 0x1852b7b0
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[10:11], v[14:15], s[2:3]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[16:17], v[12:13], v[16:17], s[2:3]
s_mov_b32 s3, 0x3f811111
s_mov_b32 s2, 0x11122322
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[10:11], v[14:15], s[2:3]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[16:17], v[12:13], v[16:17], s[2:3]
s_mov_b32 s3, 0x3fa55555
s_mov_b32 s2, 0x555502a1
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[10:11], v[14:15], s[2:3]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[16:17], v[12:13], v[16:17], s[2:3]
s_mov_b32 s3, 0x3fc55555
s_mov_b32 s2, 0x55555511
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[10:11], v[14:15], s[2:3]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[16:17], v[12:13], v[16:17], s[2:3]
s_mov_b32 s3, 0x3fe00000
s_mov_b32 s2, 11
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[10:11], v[14:15], s[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_fma_f64 v[16:17], v[12:13], v[16:17], s[2:3]
v_cmp_nlt_f64_e64 s3, 0x40900000, v[4:5]
v_cmp_ngt_f64_e64 s2, 0xc090cc00, v[2:3]
v_fma_f64 v[14:15], v[10:11], v[14:15], 1.0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[16:17], v[12:13], v[16:17], 1.0
v_fma_f64 v[6:7], v[10:11], v[14:15], 1.0
v_cvt_i32_f64_e32 v10, v[8:9]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[8:9], v[12:13], v[16:17], 1.0
v_ldexp_f64 v[6:7], v[6:7], v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ldexp_f64 v[8:9], v[8:9], v10
v_cndmask_b32_e32 v7, 0x7ff00000, v7, vcc_lo
s_and_b32 vcc_lo, s2, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v2, 0x7ff00000, v9, s3
v_cndmask_b32_e64 v3, 0, v7, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v5, 0, v2, s4
v_cndmask_b32_e32 v2, 0, v6, vcc_lo
s_and_b32 vcc_lo, s4, s3
v_cndmask_b32_e32 v4, 0, v8, vcc_lo
v_mul_f64 v[2:3], v[2:3], v[4:5]
v_mad_u64_u32 v[4:5], null, v1, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[0:1], 3, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11diff_reducePdS_S_iiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 26
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11diff_reducePdS_S_iiiii, .Lfunc_end0-_Z11diff_reducePdS_S_iiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11diff_reducePdS_S_iiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11diff_reducePdS_S_iiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 26
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void diff_reduce(double *dev_w, double *feat, double *pos, int feat_dim, int pos_dim, int par0, int par1, int n_patch)
{
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
double feat_dist = 0.0; // running entry sum of d_ij
double pos_dist = 0.0; // running entry sum of f_ij
int feat_offi = i * feat_dim; // offset of x_i
int feat_offj = j * feat_dim; // offset of x_j
int pos_offi = i * pos_dim; // offset of p_i
int pos_offj = j * pos_dim; // offset of p_j
double feat_i, feat_j, pos_i, pos_j;
// temporary local variables for entry sum calculation
int k;
if (i == j || i >= n_patch || j >= n_patch)
return;
/* thread (i, j) computes W_ij */
// get the k-th element of difference vector d_ij
// and add it to feat_dist
for (k = 0; k < feat_dim; k++) {
feat_i = feat[feat_offi + k];
feat_j = feat[feat_offj + k];
feat_dist += (feat_i - feat_j) * (feat_i - feat_j);
}
// get the k-th element of difference vector f_ij
// and add it to pos_dist
for (k = 0; k < pos_dim; k++) {
pos_i = pos[pos_offi + k];
pos_j = pos[pos_offj + k];
pos_dist += (pos_i - pos_j) * (pos_i - pos_j);
}
dev_w[i + j * n_patch]
= exp( -feat_dist / (feat_dim * par0 * par0))
* exp( -pos_dist / (pos_dim * par1 * par1));
} | .text
.file "diff_reduce.hip"
.globl _Z26__device_stub__diff_reducePdS_S_iiiii # -- Begin function _Z26__device_stub__diff_reducePdS_S_iiiii
.p2align 4, 0x90
.type _Z26__device_stub__diff_reducePdS_S_iiiii,@function
_Z26__device_stub__diff_reducePdS_S_iiiii: # @_Z26__device_stub__diff_reducePdS_S_iiiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11diff_reducePdS_S_iiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z26__device_stub__diff_reducePdS_S_iiiii, .Lfunc_end0-_Z26__device_stub__diff_reducePdS_S_iiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11diff_reducePdS_S_iiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11diff_reducePdS_S_iiiii,@object # @_Z11diff_reducePdS_S_iiiii
.section .rodata,"a",@progbits
.globl _Z11diff_reducePdS_S_iiiii
.p2align 3, 0x0
_Z11diff_reducePdS_S_iiiii:
.quad _Z26__device_stub__diff_reducePdS_S_iiiii
.size _Z11diff_reducePdS_S_iiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11diff_reducePdS_S_iiiii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__diff_reducePdS_S_iiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11diff_reducePdS_S_iiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016b18a_00000000-6_diff_reduce.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z11diff_reducePdS_S_iiiiiPdS_S_iiiii
.type _Z40__device_stub__Z11diff_reducePdS_S_iiiiiPdS_S_iiiii, @function
_Z40__device_stub__Z11diff_reducePdS_S_iiiiiPdS_S_iiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11diff_reducePdS_S_iiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z11diff_reducePdS_S_iiiiiPdS_S_iiiii, .-_Z40__device_stub__Z11diff_reducePdS_S_iiiiiPdS_S_iiiii
.globl _Z11diff_reducePdS_S_iiiii
.type _Z11diff_reducePdS_S_iiiii, @function
_Z11diff_reducePdS_S_iiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z40__device_stub__Z11diff_reducePdS_S_iiiiiPdS_S_iiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11diff_reducePdS_S_iiiii, .-_Z11diff_reducePdS_S_iiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11diff_reducePdS_S_iiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11diff_reducePdS_S_iiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "diff_reduce.hip"
.globl _Z26__device_stub__diff_reducePdS_S_iiiii # -- Begin function _Z26__device_stub__diff_reducePdS_S_iiiii
.p2align 4, 0x90
.type _Z26__device_stub__diff_reducePdS_S_iiiii,@function
_Z26__device_stub__diff_reducePdS_S_iiiii: # @_Z26__device_stub__diff_reducePdS_S_iiiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11diff_reducePdS_S_iiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z26__device_stub__diff_reducePdS_S_iiiii, .Lfunc_end0-_Z26__device_stub__diff_reducePdS_S_iiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11diff_reducePdS_S_iiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11diff_reducePdS_S_iiiii,@object # @_Z11diff_reducePdS_S_iiiii
.section .rodata,"a",@progbits
.globl _Z11diff_reducePdS_S_iiiii
.p2align 3, 0x0
_Z11diff_reducePdS_S_iiiii:
.quad _Z26__device_stub__diff_reducePdS_S_iiiii
.size _Z11diff_reducePdS_S_iiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11diff_reducePdS_S_iiiii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__diff_reducePdS_S_iiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11diff_reducePdS_S_iiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* declare a 1d array and find the maximum of each chunk using reduce method. No shared memory is used
*
*chunksize must be an exponential of 2
how to compile: nvcc para
when n is 600,000 or more, the results are not correct probably because there is not enough threads.
The 1d array used for testing is a sequence from 0 to n-1.
How to deal with the incomplete chunk:
if (tid < s && myId < n) { //myId >=n the incomplete chunk is less than blockDim.x/2)
float right_counterpart = (myId+s) >= n? 0:darr[myId+s]; //if the right_counterpart is missing, use 0
*/
#include <stdio.h>
#include <cuda.h>
float * serial_max_each_chunk(float maxarr[], float arr[], int chunkSize, int n);
__global__ void parallel_max_each_chunk(float *dmaxarr, float * darr, int chunkSize, int n);
int main(int argc, char **argv) {
//generate a 1d array
int n = atoi(argv[1]);
float *arr = (float*) malloc(n*sizeof(float));
int i;
for (i =0; i < n; i++) {
arr[i] = (float)i/2.0f;
}
const int chunkSize = 512;
int numChunk = (n + chunkSize -1)/chunkSize;
float *maxarr = (float *)malloc(numChunk * sizeof(float));
// declare GPU memory pointers
float *darr, * dmaxarr;
cudaMalloc((void **)&darr, n*sizeof(float));
cudaMalloc((void **)&dmaxarr, numChunk*sizeof(float));
cudaMemcpy(darr, arr, n*sizeof(float), cudaMemcpyHostToDevice);
dim3 dimGrid(numChunk,1);
dim3 dimBlock(chunkSize,1,1);
parallel_max_each_chunk<<<dimGrid,dimBlock>>>(dmaxarr, darr, chunkSize,n);
cudaThreadSynchronize();
cudaMemcpy(maxarr, dmaxarr, numChunk*sizeof(float), cudaMemcpyDeviceToHost);
for (i=0; i < numChunk; i++) {
printf("%d maximum: %f\n",i,maxarr[i]);
}
float * smaxarr = (float *) malloc(numChunk * sizeof(float));
printf("\nserial solution\n");
serial_max_each_chunk(smaxarr, arr, chunkSize, n);
bool judge = true;
for (i=0; i < numChunk; i++) {
printf("%d maximum: %f\n",i,smaxarr[i]);
judge = judge && (smaxarr[i] == maxarr[i]);
}
printf("\n--------correct or wrong---------\n");
printf(judge ? "right\n": "wrong\n");
// check the exit state of CUDA code
cudaError_t error = cudaGetLastError();
if (error !=cudaSuccess) {
printf("CUDA error: %s\n", cudaGetErrorString(error));
exit(-1);
}
return 0;
}
float * serial_max_each_chunk(float maxarr[], float arr[], int chunkSize, int n) {
int numChunk = (n + chunkSize - 1)/chunkSize;
int i,j;
for (i = 0; i < numChunk; i++){
maxarr[i] = -3.0;
for (j = i * chunkSize; j < (i+1)*chunkSize; j++) {
if (j >= n) { break;
} else {
if (maxarr[i] < arr[j]) { maxarr[i] = arr[j];}
}
}
}
return maxarr;
}
__global__ void parallel_max_each_chunk(float *dmaxarr, float * darr, int chunkSize, int n) {
int myId = blockIdx.x * blockDim.x + threadIdx.x;
int tid = threadIdx.x;
for (int s = blockDim.x/2; s > 0; s>>=1) {
if (tid < s && myId < n) { //myId >=n the incomplete chunk is less than blockDim.x/2)
float right_counterpart = (myId+s) >= n? 0:darr[myId+s]; //if the right_counterpart is missing, use 0
darr[myId]= right_counterpart > darr[myId]? right_counterpart : darr[myId];
}
__syncthreads();
}
if(tid == 0) {
dmaxarr[blockIdx.x] = darr[myId];
}
} | code for sm_80
Function : _Z23parallel_max_each_chunkPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0040*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*0050*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e220000002100 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*0070*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf05270 */
/*0080*/ IMAD R0, R8, c[0x0][0x0], R10 ; /* 0x0000000008007a24 */
/* 0x001fc800078e020a */
/*0090*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fd000078e0203 */
/*00a0*/ @!P0 BRA 0x1e0 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IMAD.U32 R7, RZ, RZ, UR4 ; /* 0x00000004ff077e24 */
/* 0x000fca000f8e00ff */
/*00c0*/ ISETP.GE.AND P0, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x000fe20003f06270 */
/*00d0*/ BSSY B0, 0x1a0 ; /* 0x000000c000007945 */
/* 0x000fe60003800000 */
/*00e0*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x174], P0 ; /* 0x00005d0000007a0c */
/* 0x000fda0000706670 */
/*00f0*/ @P0 BRA 0x190 ; /* 0x0000009000000947 */
/* 0x001fea0003800000 */
/*0100*/ IADD3 R4, R0, R7, RZ ; /* 0x0000000700047210 */
/* 0x000fe20007ffe0ff */
/*0110*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*0120*/ LDG.E R9, [R2.64] ; /* 0x0000000602097981 */
/* 0x000ea4000c1e1900 */
/*0130*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x174], PT ; /* 0x00005d0004007a0c */
/* 0x000fda0003f06270 */
/*0140*/ @!P0 IMAD.WIDE R4, R7, 0x4, R2 ; /* 0x0000000407048825 */
/* 0x000fca00078e0202 */
/*0150*/ @!P0 LDG.E R6, [R4.64] ; /* 0x0000000604068981 */
/* 0x000ea4000c1e1900 */
/*0160*/ FSETP.GT.AND P0, PT, R6, R9, PT ; /* 0x000000090600720b */
/* 0x004fc80003f04000 */
/*0170*/ FSEL R9, R6, R9, P0 ; /* 0x0000000906097208 */
/* 0x000fca0000000000 */
/*0180*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101906 */
/*0190*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01a0*/ SHF.R.U32.HI R7, RZ, 0x1, R7 ; /* 0x00000001ff077819 */
/* 0x000fe20000011607 */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*01c0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*01d0*/ @P0 BRA 0xc0 ; /* 0xfffffee000000947 */
/* 0x000fea000383ffff */
/*01e0*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f05270 */
/*01f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0200*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x001ea2000c1e1900 */
/*0210*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fd400000001ff */
/*0220*/ IMAD.WIDE.U32 R4, R8, R5, c[0x0][0x160] ; /* 0x0000580008047625 */
/* 0x000fca00078e0005 */
/*0230*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101906 */
/*0240*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0250*/ BRA 0x250; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* declare a 1d array and find the maximum of each chunk using reduce method. No shared memory is used
*
*chunksize must be an exponential of 2
how to compile: nvcc para
when n is 600,000 or more, the results are not correct probably because there is not enough threads.
The 1d array used for testing is a sequence from 0 to n-1.
How to deal with the incomplete chunk:
if (tid < s && myId < n) { //myId >=n the incomplete chunk is less than blockDim.x/2)
float right_counterpart = (myId+s) >= n? 0:darr[myId+s]; //if the right_counterpart is missing, use 0
*/
#include <stdio.h>
#include <cuda.h>
float * serial_max_each_chunk(float maxarr[], float arr[], int chunkSize, int n);
__global__ void parallel_max_each_chunk(float *dmaxarr, float * darr, int chunkSize, int n);
int main(int argc, char **argv) {
//generate a 1d array
int n = atoi(argv[1]);
float *arr = (float*) malloc(n*sizeof(float));
int i;
for (i =0; i < n; i++) {
arr[i] = (float)i/2.0f;
}
const int chunkSize = 512;
int numChunk = (n + chunkSize -1)/chunkSize;
float *maxarr = (float *)malloc(numChunk * sizeof(float));
// declare GPU memory pointers
float *darr, * dmaxarr;
cudaMalloc((void **)&darr, n*sizeof(float));
cudaMalloc((void **)&dmaxarr, numChunk*sizeof(float));
cudaMemcpy(darr, arr, n*sizeof(float), cudaMemcpyHostToDevice);
dim3 dimGrid(numChunk,1);
dim3 dimBlock(chunkSize,1,1);
parallel_max_each_chunk<<<dimGrid,dimBlock>>>(dmaxarr, darr, chunkSize,n);
cudaThreadSynchronize();
cudaMemcpy(maxarr, dmaxarr, numChunk*sizeof(float), cudaMemcpyDeviceToHost);
for (i=0; i < numChunk; i++) {
printf("%d maximum: %f\n",i,maxarr[i]);
}
float * smaxarr = (float *) malloc(numChunk * sizeof(float));
printf("\nserial solution\n");
serial_max_each_chunk(smaxarr, arr, chunkSize, n);
bool judge = true;
for (i=0; i < numChunk; i++) {
printf("%d maximum: %f\n",i,smaxarr[i]);
judge = judge && (smaxarr[i] == maxarr[i]);
}
printf("\n--------correct or wrong---------\n");
printf(judge ? "right\n": "wrong\n");
// check the exit state of CUDA code
cudaError_t error = cudaGetLastError();
if (error !=cudaSuccess) {
printf("CUDA error: %s\n", cudaGetErrorString(error));
exit(-1);
}
return 0;
}
float * serial_max_each_chunk(float maxarr[], float arr[], int chunkSize, int n) {
int numChunk = (n + chunkSize - 1)/chunkSize;
int i,j;
for (i = 0; i < numChunk; i++){
maxarr[i] = -3.0;
for (j = i * chunkSize; j < (i+1)*chunkSize; j++) {
if (j >= n) { break;
} else {
if (maxarr[i] < arr[j]) { maxarr[i] = arr[j];}
}
}
}
return maxarr;
}
__global__ void parallel_max_each_chunk(float *dmaxarr, float * darr, int chunkSize, int n) {
int myId = blockIdx.x * blockDim.x + threadIdx.x;
int tid = threadIdx.x;
for (int s = blockDim.x/2; s > 0; s>>=1) {
if (tid < s && myId < n) { //myId >=n the incomplete chunk is less than blockDim.x/2)
float right_counterpart = (myId+s) >= n? 0:darr[myId+s]; //if the right_counterpart is missing, use 0
darr[myId]= right_counterpart > darr[myId]? right_counterpart : darr[myId];
}
__syncthreads();
}
if(tid == 0) {
dmaxarr[blockIdx.x] = darr[myId];
}
} | .file "tmpxft_001244df_00000000-6_parallel_max_chunk.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z21serial_max_each_chunkPfS_ii
.type _Z21serial_max_each_chunkPfS_ii, @function
_Z21serial_max_each_chunkPfS_ii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r11
movl %edx, %ebx
leal -1(%rdx,%rcx), %eax
cltd
idivl %ebx
testl %eax, %eax
jle .L4
movl %ecx, %r10d
movq %rdi, %r8
movslq %ebx, %r12
cltq
leaq (%rdi,%rax,4), %rbp
movl $0, %r9d
movl $0, %edi
movss .LC0(%rip), %xmm1
jmp .L9
.L6:
addq $1, %rax
cmpl %eax, %ecx
jle .L5
.L8:
movss (%rsi,%rax,4), %xmm0
comiss (%rdx), %xmm0
jbe .L6
movss %xmm0, (%rdx)
jmp .L6
.L5:
addq $4, %r8
addq %r12, %r9
cmpq %rbp, %r8
je .L4
.L9:
movq %r8, %rdx
movss %xmm1, (%r8)
movl %edi, %eax
addl %ebx, %edi
cmpl %r10d, %edi
movl %r10d, %ecx
cmovle %edi, %ecx
cmpl %eax, %ecx
jle .L5
movq %r9, %rax
jmp .L8
.L4:
movq %r11, %rax
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z21serial_max_each_chunkPfS_ii, .-_Z21serial_max_each_chunkPfS_ii
.globl _Z47__device_stub__Z23parallel_max_each_chunkPfS_iiPfS_ii
.type _Z47__device_stub__Z23parallel_max_each_chunkPfS_iiPfS_ii, @function
_Z47__device_stub__Z23parallel_max_each_chunkPfS_iiPfS_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23parallel_max_each_chunkPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z47__device_stub__Z23parallel_max_each_chunkPfS_iiPfS_ii, .-_Z47__device_stub__Z23parallel_max_each_chunkPfS_iiPfS_ii
.globl _Z23parallel_max_each_chunkPfS_ii
.type _Z23parallel_max_each_chunkPfS_ii, @function
_Z23parallel_max_each_chunkPfS_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z23parallel_max_each_chunkPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z23parallel_max_each_chunkPfS_ii, .-_Z23parallel_max_each_chunkPfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "right\n"
.LC2:
.string "wrong\n"
.LC4:
.string "%d maximum: %f\n"
.LC5:
.string "\nserial solution\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "\n--------correct or wrong---------\n"
.section .rodata.str1.1
.LC7:
.string "CUDA error: %s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, 12(%rsp)
movslq %eax, %r15
salq $2, %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %r13
testl %ebx, %ebx
jle .L23
leal -1(%rbx), %ecx
movl $0, %eax
movss .LC3(%rip), %xmm1
.L24:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, 0(%r13,%rax,4)
movq %rax, %rdx
addq $1, %rax
cmpq %rcx, %rdx
jne .L24
.L23:
leal 1022(%rbx), %ebp
movl %ebx, %eax
addl $511, %eax
cmovns %eax, %ebp
sarl $9, %ebp
movslq %ebp, %r14
salq $2, %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %r12
leaq 16(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebp, 32(%rsp)
movl $1, 36(%rsp)
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L25:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %ebx, %ebx
jle .L26
movl $0, %ebx
leaq .LC4(%rip), %r15
.L27:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movl %ebx, %edx
movq %r15, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, %ebp
jg .L27
movq %r14, %rdi
call malloc@PLT
movq %rax, %r14
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 12(%rsp), %ecx
movl $512, %edx
movq %r13, %rsi
movq %r14, %rdi
call _Z21serial_max_each_chunkPfS_ii
movl $0, %ebx
movl $1, %r13d
leaq .LC4(%rip), %r15
jmp .L29
.L39:
movl 12(%rsp), %ecx
movl $512, %edx
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z47__device_stub__Z23parallel_max_each_chunkPfS_iiPfS_ii
jmp .L25
.L28:
addq $1, %rbx
cmpl %ebx, %ebp
jle .L40
.L29:
movss (%r14,%rbx,4), %xmm2
movss %xmm2, 12(%rsp)
pxor %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
movl %ebx, %edx
movq %r15, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
testb %r13b, %r13b
je .L28
movss 12(%rsp), %xmm2
ucomiss (%r12,%rbx,4), %xmm2
setnp %r13b
movl $0, %eax
cmovne %eax, %r13d
jmp .L28
.L40:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testb %r13b, %r13b
leaq .LC2(%rip), %rsi
leaq .LC1(%rip), %rax
cmovne %rax, %rsi
.L30:
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L41
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L42
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L26:
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 12(%rsp), %ecx
movl $512, %edx
movq %r13, %rsi
movq %rbx, %rdi
call _Z21serial_max_each_chunkPfS_ii
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
jmp .L30
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC8:
.string "_Z23parallel_max_each_chunkPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z23parallel_max_each_chunkPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long -1069547520
.align 4
.LC3:
.long 1056964608
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* declare a 1d array and find the maximum of each chunk using reduce method. No shared memory is used
*
*chunksize must be an exponential of 2
how to compile: nvcc para
when n is 600,000 or more, the results are not correct probably because there is not enough threads.
The 1d array used for testing is a sequence from 0 to n-1.
How to deal with the incomplete chunk:
if (tid < s && myId < n) { //myId >=n the incomplete chunk is less than blockDim.x/2)
float right_counterpart = (myId+s) >= n? 0:darr[myId+s]; //if the right_counterpart is missing, use 0
*/
#include <stdio.h>
#include <cuda.h>
float * serial_max_each_chunk(float maxarr[], float arr[], int chunkSize, int n);
__global__ void parallel_max_each_chunk(float *dmaxarr, float * darr, int chunkSize, int n);
int main(int argc, char **argv) {
//generate a 1d array
int n = atoi(argv[1]);
float *arr = (float*) malloc(n*sizeof(float));
int i;
for (i =0; i < n; i++) {
arr[i] = (float)i/2.0f;
}
const int chunkSize = 512;
int numChunk = (n + chunkSize -1)/chunkSize;
float *maxarr = (float *)malloc(numChunk * sizeof(float));
// declare GPU memory pointers
float *darr, * dmaxarr;
cudaMalloc((void **)&darr, n*sizeof(float));
cudaMalloc((void **)&dmaxarr, numChunk*sizeof(float));
cudaMemcpy(darr, arr, n*sizeof(float), cudaMemcpyHostToDevice);
dim3 dimGrid(numChunk,1);
dim3 dimBlock(chunkSize,1,1);
parallel_max_each_chunk<<<dimGrid,dimBlock>>>(dmaxarr, darr, chunkSize,n);
cudaThreadSynchronize();
cudaMemcpy(maxarr, dmaxarr, numChunk*sizeof(float), cudaMemcpyDeviceToHost);
for (i=0; i < numChunk; i++) {
printf("%d maximum: %f\n",i,maxarr[i]);
}
float * smaxarr = (float *) malloc(numChunk * sizeof(float));
printf("\nserial solution\n");
serial_max_each_chunk(smaxarr, arr, chunkSize, n);
bool judge = true;
for (i=0; i < numChunk; i++) {
printf("%d maximum: %f\n",i,smaxarr[i]);
judge = judge && (smaxarr[i] == maxarr[i]);
}
printf("\n--------correct or wrong---------\n");
printf(judge ? "right\n": "wrong\n");
// check the exit state of CUDA code
cudaError_t error = cudaGetLastError();
if (error !=cudaSuccess) {
printf("CUDA error: %s\n", cudaGetErrorString(error));
exit(-1);
}
return 0;
}
float * serial_max_each_chunk(float maxarr[], float arr[], int chunkSize, int n) {
int numChunk = (n + chunkSize - 1)/chunkSize;
int i,j;
for (i = 0; i < numChunk; i++){
maxarr[i] = -3.0;
for (j = i * chunkSize; j < (i+1)*chunkSize; j++) {
if (j >= n) { break;
} else {
if (maxarr[i] < arr[j]) { maxarr[i] = arr[j];}
}
}
}
return maxarr;
}
__global__ void parallel_max_each_chunk(float *dmaxarr, float * darr, int chunkSize, int n) {
int myId = blockIdx.x * blockDim.x + threadIdx.x;
int tid = threadIdx.x;
for (int s = blockDim.x/2; s > 0; s>>=1) {
if (tid < s && myId < n) { //myId >=n the incomplete chunk is less than blockDim.x/2)
float right_counterpart = (myId+s) >= n? 0:darr[myId+s]; //if the right_counterpart is missing, use 0
darr[myId]= right_counterpart > darr[myId]? right_counterpart : darr[myId];
}
__syncthreads();
}
if(tid == 0) {
dmaxarr[blockIdx.x] = darr[myId];
}
} | /* declare a 1d array and find the maximum of each chunk using reduce method. No shared memory is used
*
*chunksize must be an exponential of 2
how to compile: nvcc para
when n is 600,000 or more, the results are not correct probably because there is not enough threads.
The 1d array used for testing is a sequence from 0 to n-1.
How to deal with the incomplete chunk:
if (tid < s && myId < n) { //myId >=n the incomplete chunk is less than blockDim.x/2)
float right_counterpart = (myId+s) >= n? 0:darr[myId+s]; //if the right_counterpart is missing, use 0
*/
#include <stdio.h>
#include <hip/hip_runtime.h>
float * serial_max_each_chunk(float maxarr[], float arr[], int chunkSize, int n);
__global__ void parallel_max_each_chunk(float *dmaxarr, float * darr, int chunkSize, int n);
int main(int argc, char **argv) {
//generate a 1d array
int n = atoi(argv[1]);
float *arr = (float*) malloc(n*sizeof(float));
int i;
for (i =0; i < n; i++) {
arr[i] = (float)i/2.0f;
}
const int chunkSize = 512;
int numChunk = (n + chunkSize -1)/chunkSize;
float *maxarr = (float *)malloc(numChunk * sizeof(float));
// declare GPU memory pointers
float *darr, * dmaxarr;
hipMalloc((void **)&darr, n*sizeof(float));
hipMalloc((void **)&dmaxarr, numChunk*sizeof(float));
hipMemcpy(darr, arr, n*sizeof(float), hipMemcpyHostToDevice);
dim3 dimGrid(numChunk,1);
dim3 dimBlock(chunkSize,1,1);
parallel_max_each_chunk<<<dimGrid,dimBlock>>>(dmaxarr, darr, chunkSize,n);
hipDeviceSynchronize();
hipMemcpy(maxarr, dmaxarr, numChunk*sizeof(float), hipMemcpyDeviceToHost);
for (i=0; i < numChunk; i++) {
printf("%d maximum: %f\n",i,maxarr[i]);
}
float * smaxarr = (float *) malloc(numChunk * sizeof(float));
printf("\nserial solution\n");
serial_max_each_chunk(smaxarr, arr, chunkSize, n);
bool judge = true;
for (i=0; i < numChunk; i++) {
printf("%d maximum: %f\n",i,smaxarr[i]);
judge = judge && (smaxarr[i] == maxarr[i]);
}
printf("\n--------correct or wrong---------\n");
printf(judge ? "right\n": "wrong\n");
// check the exit state of CUDA code
hipError_t error = hipGetLastError();
if (error !=hipSuccess) {
printf("CUDA error: %s\n", hipGetErrorString(error));
exit(-1);
}
return 0;
}
float * serial_max_each_chunk(float maxarr[], float arr[], int chunkSize, int n) {
int numChunk = (n + chunkSize - 1)/chunkSize;
int i,j;
for (i = 0; i < numChunk; i++){
maxarr[i] = -3.0;
for (j = i * chunkSize; j < (i+1)*chunkSize; j++) {
if (j >= n) { break;
} else {
if (maxarr[i] < arr[j]) { maxarr[i] = arr[j];}
}
}
}
return maxarr;
}
__global__ void parallel_max_each_chunk(float *dmaxarr, float * darr, int chunkSize, int n) {
int myId = blockIdx.x * blockDim.x + threadIdx.x;
int tid = threadIdx.x;
for (int s = blockDim.x/2; s > 0; s>>=1) {
if (tid < s && myId < n) { //myId >=n the incomplete chunk is less than blockDim.x/2)
float right_counterpart = (myId+s) >= n? 0:darr[myId+s]; //if the right_counterpart is missing, use 0
darr[myId]= right_counterpart > darr[myId]? right_counterpart : darr[myId];
}
__syncthreads();
}
if(tid == 0) {
dmaxarr[blockIdx.x] = darr[myId];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* declare a 1d array and find the maximum of each chunk using reduce method. No shared memory is used
*
*chunksize must be an exponential of 2
how to compile: nvcc para
when n is 600,000 or more, the results are not correct probably because there is not enough threads.
The 1d array used for testing is a sequence from 0 to n-1.
How to deal with the incomplete chunk:
if (tid < s && myId < n) { //myId >=n the incomplete chunk is less than blockDim.x/2)
float right_counterpart = (myId+s) >= n? 0:darr[myId+s]; //if the right_counterpart is missing, use 0
*/
#include <stdio.h>
#include <hip/hip_runtime.h>
float * serial_max_each_chunk(float maxarr[], float arr[], int chunkSize, int n);
__global__ void parallel_max_each_chunk(float *dmaxarr, float * darr, int chunkSize, int n);
int main(int argc, char **argv) {
//generate a 1d array
int n = atoi(argv[1]);
float *arr = (float*) malloc(n*sizeof(float));
int i;
for (i =0; i < n; i++) {
arr[i] = (float)i/2.0f;
}
const int chunkSize = 512;
int numChunk = (n + chunkSize -1)/chunkSize;
float *maxarr = (float *)malloc(numChunk * sizeof(float));
// declare GPU memory pointers
float *darr, * dmaxarr;
hipMalloc((void **)&darr, n*sizeof(float));
hipMalloc((void **)&dmaxarr, numChunk*sizeof(float));
hipMemcpy(darr, arr, n*sizeof(float), hipMemcpyHostToDevice);
dim3 dimGrid(numChunk,1);
dim3 dimBlock(chunkSize,1,1);
parallel_max_each_chunk<<<dimGrid,dimBlock>>>(dmaxarr, darr, chunkSize,n);
hipDeviceSynchronize();
hipMemcpy(maxarr, dmaxarr, numChunk*sizeof(float), hipMemcpyDeviceToHost);
for (i=0; i < numChunk; i++) {
printf("%d maximum: %f\n",i,maxarr[i]);
}
float * smaxarr = (float *) malloc(numChunk * sizeof(float));
printf("\nserial solution\n");
serial_max_each_chunk(smaxarr, arr, chunkSize, n);
bool judge = true;
for (i=0; i < numChunk; i++) {
printf("%d maximum: %f\n",i,smaxarr[i]);
judge = judge && (smaxarr[i] == maxarr[i]);
}
printf("\n--------correct or wrong---------\n");
printf(judge ? "right\n": "wrong\n");
// check the exit state of CUDA code
hipError_t error = hipGetLastError();
if (error !=hipSuccess) {
printf("CUDA error: %s\n", hipGetErrorString(error));
exit(-1);
}
return 0;
}
float * serial_max_each_chunk(float maxarr[], float arr[], int chunkSize, int n) {
int numChunk = (n + chunkSize - 1)/chunkSize;
int i,j;
for (i = 0; i < numChunk; i++){
maxarr[i] = -3.0;
for (j = i * chunkSize; j < (i+1)*chunkSize; j++) {
if (j >= n) { break;
} else {
if (maxarr[i] < arr[j]) { maxarr[i] = arr[j];}
}
}
}
return maxarr;
}
__global__ void parallel_max_each_chunk(float *dmaxarr, float * darr, int chunkSize, int n) {
int myId = blockIdx.x * blockDim.x + threadIdx.x;
int tid = threadIdx.x;
for (int s = blockDim.x/2; s > 0; s>>=1) {
if (tid < s && myId < n) { //myId >=n the incomplete chunk is less than blockDim.x/2)
float right_counterpart = (myId+s) >= n? 0:darr[myId+s]; //if the right_counterpart is missing, use 0
darr[myId]= right_counterpart > darr[myId]? right_counterpart : darr[myId];
}
__syncthreads();
}
if(tid == 0) {
dmaxarr[blockIdx.x] = darr[myId];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23parallel_max_each_chunkPfS_ii
.globl _Z23parallel_max_each_chunkPfS_ii
.p2align 8
.type _Z23parallel_max_each_chunkPfS_ii,@function
_Z23parallel_max_each_chunkPfS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[6:7], s[0:1], 0x8
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s4, s3, v[0:1]
s_cmp_lt_u32 s3, 2
v_ashrrev_i32_e32 v2, 31, v1
s_cbranch_scc1 .LBB0_7
s_load_b32 s5, s[0:1], 0x14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, s2, s6, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s2, s7, v4, s2
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s5, v1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s10
global_load_b32 v5, v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_gt_f32_e64 s2, v6, v5
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v5, v5, v6, s2
global_store_b32 v[3:4], v5, off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s9
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s8
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
.LBB0_4:
s_lshr_b32 s8, s3, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s8, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s9, s2
s_cbranch_execz .LBB0_3
v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v5, s8, v1
s_mov_b32 s10, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s5, v5
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, s2, s6, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s2, s7, v6, s2
global_load_b32 v6, v[5:6], off
s_branch .LBB0_2
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s5, 0
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_9
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x0
s_lshl_b64 s[2:3], s[4:5], 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v0, v[0:1], off
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23parallel_max_each_chunkPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23parallel_max_each_chunkPfS_ii, .Lfunc_end0-_Z23parallel_max_each_chunkPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23parallel_max_each_chunkPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23parallel_max_each_chunkPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* declare a 1d array and find the maximum of each chunk using reduce method. No shared memory is used
*
*chunksize must be an exponential of 2
how to compile: nvcc para
when n is 600,000 or more, the results are not correct probably because there is not enough threads.
The 1d array used for testing is a sequence from 0 to n-1.
How to deal with the incomplete chunk:
if (tid < s && myId < n) { //myId >=n the incomplete chunk is less than blockDim.x/2)
float right_counterpart = (myId+s) >= n? 0:darr[myId+s]; //if the right_counterpart is missing, use 0
*/
#include <stdio.h>
#include <hip/hip_runtime.h>
float * serial_max_each_chunk(float maxarr[], float arr[], int chunkSize, int n);
__global__ void parallel_max_each_chunk(float *dmaxarr, float * darr, int chunkSize, int n);
int main(int argc, char **argv) {
//generate a 1d array
int n = atoi(argv[1]);
float *arr = (float*) malloc(n*sizeof(float));
int i;
for (i =0; i < n; i++) {
arr[i] = (float)i/2.0f;
}
const int chunkSize = 512;
int numChunk = (n + chunkSize -1)/chunkSize;
float *maxarr = (float *)malloc(numChunk * sizeof(float));
// declare GPU memory pointers
float *darr, * dmaxarr;
hipMalloc((void **)&darr, n*sizeof(float));
hipMalloc((void **)&dmaxarr, numChunk*sizeof(float));
hipMemcpy(darr, arr, n*sizeof(float), hipMemcpyHostToDevice);
dim3 dimGrid(numChunk,1);
dim3 dimBlock(chunkSize,1,1);
parallel_max_each_chunk<<<dimGrid,dimBlock>>>(dmaxarr, darr, chunkSize,n);
hipDeviceSynchronize();
hipMemcpy(maxarr, dmaxarr, numChunk*sizeof(float), hipMemcpyDeviceToHost);
for (i=0; i < numChunk; i++) {
printf("%d maximum: %f\n",i,maxarr[i]);
}
float * smaxarr = (float *) malloc(numChunk * sizeof(float));
printf("\nserial solution\n");
serial_max_each_chunk(smaxarr, arr, chunkSize, n);
bool judge = true;
for (i=0; i < numChunk; i++) {
printf("%d maximum: %f\n",i,smaxarr[i]);
judge = judge && (smaxarr[i] == maxarr[i]);
}
printf("\n--------correct or wrong---------\n");
printf(judge ? "right\n": "wrong\n");
// check the exit state of CUDA code
hipError_t error = hipGetLastError();
if (error !=hipSuccess) {
printf("CUDA error: %s\n", hipGetErrorString(error));
exit(-1);
}
return 0;
}
float * serial_max_each_chunk(float maxarr[], float arr[], int chunkSize, int n) {
int numChunk = (n + chunkSize - 1)/chunkSize;
int i,j;
for (i = 0; i < numChunk; i++){
maxarr[i] = -3.0;
for (j = i * chunkSize; j < (i+1)*chunkSize; j++) {
if (j >= n) { break;
} else {
if (maxarr[i] < arr[j]) { maxarr[i] = arr[j];}
}
}
}
return maxarr;
}
__global__ void parallel_max_each_chunk(float *dmaxarr, float * darr, int chunkSize, int n) {
int myId = blockIdx.x * blockDim.x + threadIdx.x;
int tid = threadIdx.x;
for (int s = blockDim.x/2; s > 0; s>>=1) {
if (tid < s && myId < n) { //myId >=n the incomplete chunk is less than blockDim.x/2)
float right_counterpart = (myId+s) >= n? 0:darr[myId+s]; //if the right_counterpart is missing, use 0
darr[myId]= right_counterpart > darr[myId]? right_counterpart : darr[myId];
}
__syncthreads();
}
if(tid == 0) {
dmaxarr[blockIdx.x] = darr[myId];
}
} | .text
.file "parallel_max_chunk.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x3f000000 # float 0.5
.LCPI0_1:
.long 0xc0400000 # float -3
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movslq %ebx, %r14
leaq (,%r14,4), %r13
movq %r13, %rdi
callq malloc
movq %rax, %r15
testl %r14d, %r14d
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %ebx, %eax
xorl %ecx, %ecx
movss .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2ss %ecx, %xmm1
mulss %xmm0, %xmm1
movss %xmm1, (%r15,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
leal 511(%rbx), %eax
leal 1022(%rbx), %ebp
testl %eax, %eax
cmovnsl %eax, %ebp
sarl $9, %ebp
movslq %ebp, %r12
shlq $2, %r12
movq %r12, %rdi
callq malloc
movq %rax, %r14
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r15, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967296, %rdx # imm = 0x100000000
leaq (%rdx,%rbp), %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_5
# %bb.4:
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $512, 12(%rsp) # imm = 0x200
movl %ebx, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z23parallel_max_each_chunkPfS_ii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_5:
callq hipDeviceSynchronize
movq 16(%rsp), %rsi
movq %r14, %rdi
movq %r12, (%rsp) # 8-byte Spill
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
testl %ebx, %ebx
jle .LBB0_8
# %bb.6: # %.lr.ph58.preheader
cmpl $2, %ebp
movl $1, %r12d
cmovgel %ebp, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_7: # %.lr.ph58
# =>This Inner Loop Header: Depth=1
movss (%r14,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movl %r13d, %esi
movb $1, %al
callq printf
incq %r13
cmpq %r13, %r12
jne .LBB0_7
.LBB0_8: # %._crit_edge59
movq (%rsp), %rdi # 8-byte Reload
callq malloc
movq %rax, %r12
movl $.Lstr, %edi
callq puts@PLT
testl %ebx, %ebx
jle .LBB0_16
# %bb.9: # %.lr.ph29.i.preheader
xorl %eax, %eax
movss .LCPI0_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
jmp .LBB0_11
.p2align 4, 0x90
.LBB0_10: # %.loopexit.i
# in Loop: Header=BB0_11 Depth=1
addq $512, %rcx # imm = 0x200
cmpq %rbp, %rax
je .LBB0_16
.LBB0_11: # %.lr.ph29.i
# =>This Loop Header: Depth=1
# Child Loop BB0_13 Depth 2
movq %rax, %rdx
movl $-1069547520, (%r12,%rax,4) # imm = 0xC0400000
movq %rax, %rdi
shlq $9, %rdi
incq %rax
movl %eax, %esi
shll $9, %esi
cmpl %ebx, %esi
cmovgel %ebx, %esi
movslq %esi, %rsi
cmpq %rsi, %rdi
jge .LBB0_10
# %bb.12: # %.lr.ph.i.preheader
# in Loop: Header=BB0_11 Depth=1
movq %rcx, %rdi
movaps %xmm0, %xmm1
jmp .LBB0_13
.p2align 4, 0x90
.LBB0_15: # in Loop: Header=BB0_13 Depth=2
incq %rdi
cmpq %rsi, %rdi
jge .LBB0_10
.LBB0_13: # %.lr.ph.i
# Parent Loop BB0_11 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15,%rdi,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm2
jbe .LBB0_15
# %bb.14: # in Loop: Header=BB0_13 Depth=2
movss %xmm2, (%r12,%rdx,4)
movaps %xmm2, %xmm1
jmp .LBB0_15
.LBB0_16: # %_Z21serial_max_each_chunkPfS_ii.exit
testl %ebx, %ebx
jle .LBB0_17
# %bb.18: # %.lr.ph62.preheader
cmpl $2, %ebp
movl $1, %r15d
cmovgel %ebp, %r15d
movb $1, %bpl
xorl %ebx, %ebx
jmp .LBB0_19
.p2align 4, 0x90
.LBB0_21: # in Loop: Header=BB0_19 Depth=1
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cmpeqss (%r14,%rbx,4), %xmm0
movd %xmm0, %ebp
andl $1, %ebp
.LBB0_22: # in Loop: Header=BB0_19 Depth=1
incq %rbx
cmpq %rbx, %r15
je .LBB0_23
.LBB0_19: # %.lr.ph62
# =>This Inner Loop Header: Depth=1
movss (%r12,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rsp) # 4-byte Spill
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movl %ebx, %esi
movb $1, %al
callq printf
testb $1, %bpl
jne .LBB0_21
# %bb.20: # in Loop: Header=BB0_19 Depth=1
xorl %ebp, %ebp
jmp .LBB0_22
.LBB0_23: # %._crit_edge63.loopexit
movl $.L.str.3, %eax
movl $.L.str.4, %ebx
testb %bpl, %bpl
cmovneq %rax, %rbx
jmp .LBB0_24
.LBB0_17:
movl $.L.str.3, %ebx
.LBB0_24: # %._crit_edge63
movl $.Lstr.1, %edi
callq puts@PLT
movq %rbx, %rdi
xorl %eax, %eax
callq printf
callq hipGetLastError
testl %eax, %eax
jne .LBB0_26
# %bb.25:
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_26:
.cfi_def_cfa_offset 192
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z38__device_stub__parallel_max_each_chunkPfS_ii # -- Begin function _Z38__device_stub__parallel_max_each_chunkPfS_ii
.p2align 4, 0x90
.type _Z38__device_stub__parallel_max_each_chunkPfS_ii,@function
_Z38__device_stub__parallel_max_each_chunkPfS_ii: # @_Z38__device_stub__parallel_max_each_chunkPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23parallel_max_each_chunkPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z38__device_stub__parallel_max_each_chunkPfS_ii, .Lfunc_end1-_Z38__device_stub__parallel_max_each_chunkPfS_ii
.cfi_endproc
# -- End function
.globl _Z21serial_max_each_chunkPfS_ii # -- Begin function _Z21serial_max_each_chunkPfS_ii
.p2align 4, 0x90
.type _Z21serial_max_each_chunkPfS_ii,@function
_Z21serial_max_each_chunkPfS_ii: # @_Z21serial_max_each_chunkPfS_ii
.cfi_startproc
# %bb.0:
# kill: def $ecx killed $ecx def $rcx
movl %edx, %r8d
leal (%r8,%rcx), %eax
decl %eax
cltd
idivl %r8d
testl %eax, %eax
jle .LBB2_9
# %bb.1: # %.lr.ph29.preheader
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movslq %r8d, %rdx
movl %eax, %eax
xorl %r10d, %r10d
xorl %r9d, %r9d
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_2: # %.loopexit
# in Loop: Header=BB2_3 Depth=1
addq %rdx, %r9
cmpq %rax, %r10
je .LBB2_8
.LBB2_3: # %.lr.ph29
# =>This Loop Header: Depth=1
# Child Loop BB2_5 Depth 2
movq %r10, %r11
movl $-1069547520, (%rdi,%r10,4) # imm = 0xC0400000
movq %r10, %r14
imulq %rdx, %r14
incq %r10
movl %r10d, %ebx
imull %r8d, %ebx
cmpl %ecx, %ebx
cmovgel %ecx, %ebx
movslq %ebx, %rbx
cmpq %rbx, %r14
jge .LBB2_2
# %bb.4: # %.lr.ph
# in Loop: Header=BB2_3 Depth=1
movss (%rdi,%r11,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %r9, %r14
jmp .LBB2_5
.p2align 4, 0x90
.LBB2_7: # in Loop: Header=BB2_5 Depth=2
incq %r14
cmpq %rbx, %r14
jge .LBB2_2
.LBB2_5: # Parent Loop BB2_3 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rsi,%r14,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
jbe .LBB2_7
# %bb.6: # in Loop: Header=BB2_5 Depth=2
movss %xmm1, (%rdi,%r11,4)
movaps %xmm1, %xmm0
jmp .LBB2_7
.LBB2_8:
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.LBB2_9: # %._crit_edge
movq %rdi, %rax
retq
.Lfunc_end2:
.size _Z21serial_max_each_chunkPfS_ii, .Lfunc_end2-_Z21serial_max_each_chunkPfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23parallel_max_each_chunkPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23parallel_max_each_chunkPfS_ii,@object # @_Z23parallel_max_each_chunkPfS_ii
.section .rodata,"a",@progbits
.globl _Z23parallel_max_each_chunkPfS_ii
.p2align 3, 0x0
_Z23parallel_max_each_chunkPfS_ii:
.quad _Z38__device_stub__parallel_max_each_chunkPfS_ii
.size _Z23parallel_max_each_chunkPfS_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d maximum: %f\n"
.size .L.str, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "right\n"
.size .L.str.3, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "wrong\n"
.size .L.str.4, 7
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "CUDA error: %s\n"
.size .L.str.5, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z23parallel_max_each_chunkPfS_ii"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nserial solution"
.size .Lstr, 17
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n--------correct or wrong---------"
.size .Lstr.1, 35
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__parallel_max_each_chunkPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23parallel_max_each_chunkPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z23parallel_max_each_chunkPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0040*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*0050*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e220000002100 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*0070*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf05270 */
/*0080*/ IMAD R0, R8, c[0x0][0x0], R10 ; /* 0x0000000008007a24 */
/* 0x001fc800078e020a */
/*0090*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fd000078e0203 */
/*00a0*/ @!P0 BRA 0x1e0 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IMAD.U32 R7, RZ, RZ, UR4 ; /* 0x00000004ff077e24 */
/* 0x000fca000f8e00ff */
/*00c0*/ ISETP.GE.AND P0, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x000fe20003f06270 */
/*00d0*/ BSSY B0, 0x1a0 ; /* 0x000000c000007945 */
/* 0x000fe60003800000 */
/*00e0*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x174], P0 ; /* 0x00005d0000007a0c */
/* 0x000fda0000706670 */
/*00f0*/ @P0 BRA 0x190 ; /* 0x0000009000000947 */
/* 0x001fea0003800000 */
/*0100*/ IADD3 R4, R0, R7, RZ ; /* 0x0000000700047210 */
/* 0x000fe20007ffe0ff */
/*0110*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*0120*/ LDG.E R9, [R2.64] ; /* 0x0000000602097981 */
/* 0x000ea4000c1e1900 */
/*0130*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x174], PT ; /* 0x00005d0004007a0c */
/* 0x000fda0003f06270 */
/*0140*/ @!P0 IMAD.WIDE R4, R7, 0x4, R2 ; /* 0x0000000407048825 */
/* 0x000fca00078e0202 */
/*0150*/ @!P0 LDG.E R6, [R4.64] ; /* 0x0000000604068981 */
/* 0x000ea4000c1e1900 */
/*0160*/ FSETP.GT.AND P0, PT, R6, R9, PT ; /* 0x000000090600720b */
/* 0x004fc80003f04000 */
/*0170*/ FSEL R9, R6, R9, P0 ; /* 0x0000000906097208 */
/* 0x000fca0000000000 */
/*0180*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101906 */
/*0190*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01a0*/ SHF.R.U32.HI R7, RZ, 0x1, R7 ; /* 0x00000001ff077819 */
/* 0x000fe20000011607 */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*01c0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*01d0*/ @P0 BRA 0xc0 ; /* 0xfffffee000000947 */
/* 0x000fea000383ffff */
/*01e0*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f05270 */
/*01f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0200*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x001ea2000c1e1900 */
/*0210*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fd400000001ff */
/*0220*/ IMAD.WIDE.U32 R4, R8, R5, c[0x0][0x160] ; /* 0x0000580008047625 */
/* 0x000fca00078e0005 */
/*0230*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101906 */
/*0240*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0250*/ BRA 0x250; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23parallel_max_each_chunkPfS_ii
.globl _Z23parallel_max_each_chunkPfS_ii
.p2align 8
.type _Z23parallel_max_each_chunkPfS_ii,@function
_Z23parallel_max_each_chunkPfS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[6:7], s[0:1], 0x8
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s4, s3, v[0:1]
s_cmp_lt_u32 s3, 2
v_ashrrev_i32_e32 v2, 31, v1
s_cbranch_scc1 .LBB0_7
s_load_b32 s5, s[0:1], 0x14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, s2, s6, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s2, s7, v4, s2
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s5, v1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s10
global_load_b32 v5, v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_gt_f32_e64 s2, v6, v5
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v5, v5, v6, s2
global_store_b32 v[3:4], v5, off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s9
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s8
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
.LBB0_4:
s_lshr_b32 s8, s3, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s8, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s9, s2
s_cbranch_execz .LBB0_3
v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v5, s8, v1
s_mov_b32 s10, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s5, v5
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, s2, s6, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s2, s7, v6, s2
global_load_b32 v6, v[5:6], off
s_branch .LBB0_2
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s5, 0
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_9
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x0
s_lshl_b64 s[2:3], s[4:5], 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v0, v[0:1], off
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23parallel_max_each_chunkPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23parallel_max_each_chunkPfS_ii, .Lfunc_end0-_Z23parallel_max_each_chunkPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23parallel_max_each_chunkPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23parallel_max_each_chunkPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001244df_00000000-6_parallel_max_chunk.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z21serial_max_each_chunkPfS_ii
.type _Z21serial_max_each_chunkPfS_ii, @function
_Z21serial_max_each_chunkPfS_ii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r11
movl %edx, %ebx
leal -1(%rdx,%rcx), %eax
cltd
idivl %ebx
testl %eax, %eax
jle .L4
movl %ecx, %r10d
movq %rdi, %r8
movslq %ebx, %r12
cltq
leaq (%rdi,%rax,4), %rbp
movl $0, %r9d
movl $0, %edi
movss .LC0(%rip), %xmm1
jmp .L9
.L6:
addq $1, %rax
cmpl %eax, %ecx
jle .L5
.L8:
movss (%rsi,%rax,4), %xmm0
comiss (%rdx), %xmm0
jbe .L6
movss %xmm0, (%rdx)
jmp .L6
.L5:
addq $4, %r8
addq %r12, %r9
cmpq %rbp, %r8
je .L4
.L9:
movq %r8, %rdx
movss %xmm1, (%r8)
movl %edi, %eax
addl %ebx, %edi
cmpl %r10d, %edi
movl %r10d, %ecx
cmovle %edi, %ecx
cmpl %eax, %ecx
jle .L5
movq %r9, %rax
jmp .L8
.L4:
movq %r11, %rax
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z21serial_max_each_chunkPfS_ii, .-_Z21serial_max_each_chunkPfS_ii
.globl _Z47__device_stub__Z23parallel_max_each_chunkPfS_iiPfS_ii
.type _Z47__device_stub__Z23parallel_max_each_chunkPfS_iiPfS_ii, @function
_Z47__device_stub__Z23parallel_max_each_chunkPfS_iiPfS_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23parallel_max_each_chunkPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z47__device_stub__Z23parallel_max_each_chunkPfS_iiPfS_ii, .-_Z47__device_stub__Z23parallel_max_each_chunkPfS_iiPfS_ii
.globl _Z23parallel_max_each_chunkPfS_ii
.type _Z23parallel_max_each_chunkPfS_ii, @function
_Z23parallel_max_each_chunkPfS_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z23parallel_max_each_chunkPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z23parallel_max_each_chunkPfS_ii, .-_Z23parallel_max_each_chunkPfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "right\n"
.LC2:
.string "wrong\n"
.LC4:
.string "%d maximum: %f\n"
.LC5:
.string "\nserial solution\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "\n--------correct or wrong---------\n"
.section .rodata.str1.1
.LC7:
.string "CUDA error: %s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, 12(%rsp)
movslq %eax, %r15
salq $2, %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %r13
testl %ebx, %ebx
jle .L23
leal -1(%rbx), %ecx
movl $0, %eax
movss .LC3(%rip), %xmm1
.L24:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, 0(%r13,%rax,4)
movq %rax, %rdx
addq $1, %rax
cmpq %rcx, %rdx
jne .L24
.L23:
leal 1022(%rbx), %ebp
movl %ebx, %eax
addl $511, %eax
cmovns %eax, %ebp
sarl $9, %ebp
movslq %ebp, %r14
salq $2, %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %r12
leaq 16(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebp, 32(%rsp)
movl $1, 36(%rsp)
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L25:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %ebx, %ebx
jle .L26
movl $0, %ebx
leaq .LC4(%rip), %r15
.L27:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movl %ebx, %edx
movq %r15, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, %ebp
jg .L27
movq %r14, %rdi
call malloc@PLT
movq %rax, %r14
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 12(%rsp), %ecx
movl $512, %edx
movq %r13, %rsi
movq %r14, %rdi
call _Z21serial_max_each_chunkPfS_ii
movl $0, %ebx
movl $1, %r13d
leaq .LC4(%rip), %r15
jmp .L29
.L39:
movl 12(%rsp), %ecx
movl $512, %edx
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z47__device_stub__Z23parallel_max_each_chunkPfS_iiPfS_ii
jmp .L25
.L28:
addq $1, %rbx
cmpl %ebx, %ebp
jle .L40
.L29:
movss (%r14,%rbx,4), %xmm2
movss %xmm2, 12(%rsp)
pxor %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
movl %ebx, %edx
movq %r15, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
testb %r13b, %r13b
je .L28
movss 12(%rsp), %xmm2
ucomiss (%r12,%rbx,4), %xmm2
setnp %r13b
movl $0, %eax
cmovne %eax, %r13d
jmp .L28
.L40:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testb %r13b, %r13b
leaq .LC2(%rip), %rsi
leaq .LC1(%rip), %rax
cmovne %rax, %rsi
.L30:
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L41
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L42
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L26:
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 12(%rsp), %ecx
movl $512, %edx
movq %r13, %rsi
movq %rbx, %rdi
call _Z21serial_max_each_chunkPfS_ii
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
jmp .L30
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC8:
.string "_Z23parallel_max_each_chunkPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z23parallel_max_each_chunkPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long -1069547520
.align 4
.LC3:
.long 1056964608
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "parallel_max_chunk.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x3f000000 # float 0.5
.LCPI0_1:
.long 0xc0400000 # float -3
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movslq %ebx, %r14
leaq (,%r14,4), %r13
movq %r13, %rdi
callq malloc
movq %rax, %r15
testl %r14d, %r14d
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %ebx, %eax
xorl %ecx, %ecx
movss .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2ss %ecx, %xmm1
mulss %xmm0, %xmm1
movss %xmm1, (%r15,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
leal 511(%rbx), %eax
leal 1022(%rbx), %ebp
testl %eax, %eax
cmovnsl %eax, %ebp
sarl $9, %ebp
movslq %ebp, %r12
shlq $2, %r12
movq %r12, %rdi
callq malloc
movq %rax, %r14
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r15, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967296, %rdx # imm = 0x100000000
leaq (%rdx,%rbp), %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_5
# %bb.4:
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $512, 12(%rsp) # imm = 0x200
movl %ebx, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z23parallel_max_each_chunkPfS_ii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_5:
callq hipDeviceSynchronize
movq 16(%rsp), %rsi
movq %r14, %rdi
movq %r12, (%rsp) # 8-byte Spill
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
testl %ebx, %ebx
jle .LBB0_8
# %bb.6: # %.lr.ph58.preheader
cmpl $2, %ebp
movl $1, %r12d
cmovgel %ebp, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_7: # %.lr.ph58
# =>This Inner Loop Header: Depth=1
movss (%r14,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movl %r13d, %esi
movb $1, %al
callq printf
incq %r13
cmpq %r13, %r12
jne .LBB0_7
.LBB0_8: # %._crit_edge59
movq (%rsp), %rdi # 8-byte Reload
callq malloc
movq %rax, %r12
movl $.Lstr, %edi
callq puts@PLT
testl %ebx, %ebx
jle .LBB0_16
# %bb.9: # %.lr.ph29.i.preheader
xorl %eax, %eax
movss .LCPI0_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
jmp .LBB0_11
.p2align 4, 0x90
.LBB0_10: # %.loopexit.i
# in Loop: Header=BB0_11 Depth=1
addq $512, %rcx # imm = 0x200
cmpq %rbp, %rax
je .LBB0_16
.LBB0_11: # %.lr.ph29.i
# =>This Loop Header: Depth=1
# Child Loop BB0_13 Depth 2
movq %rax, %rdx
movl $-1069547520, (%r12,%rax,4) # imm = 0xC0400000
movq %rax, %rdi
shlq $9, %rdi
incq %rax
movl %eax, %esi
shll $9, %esi
cmpl %ebx, %esi
cmovgel %ebx, %esi
movslq %esi, %rsi
cmpq %rsi, %rdi
jge .LBB0_10
# %bb.12: # %.lr.ph.i.preheader
# in Loop: Header=BB0_11 Depth=1
movq %rcx, %rdi
movaps %xmm0, %xmm1
jmp .LBB0_13
.p2align 4, 0x90
.LBB0_15: # in Loop: Header=BB0_13 Depth=2
incq %rdi
cmpq %rsi, %rdi
jge .LBB0_10
.LBB0_13: # %.lr.ph.i
# Parent Loop BB0_11 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15,%rdi,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm2
jbe .LBB0_15
# %bb.14: # in Loop: Header=BB0_13 Depth=2
movss %xmm2, (%r12,%rdx,4)
movaps %xmm2, %xmm1
jmp .LBB0_15
.LBB0_16: # %_Z21serial_max_each_chunkPfS_ii.exit
testl %ebx, %ebx
jle .LBB0_17
# %bb.18: # %.lr.ph62.preheader
cmpl $2, %ebp
movl $1, %r15d
cmovgel %ebp, %r15d
movb $1, %bpl
xorl %ebx, %ebx
jmp .LBB0_19
.p2align 4, 0x90
.LBB0_21: # in Loop: Header=BB0_19 Depth=1
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cmpeqss (%r14,%rbx,4), %xmm0
movd %xmm0, %ebp
andl $1, %ebp
.LBB0_22: # in Loop: Header=BB0_19 Depth=1
incq %rbx
cmpq %rbx, %r15
je .LBB0_23
.LBB0_19: # %.lr.ph62
# =>This Inner Loop Header: Depth=1
movss (%r12,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rsp) # 4-byte Spill
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movl %ebx, %esi
movb $1, %al
callq printf
testb $1, %bpl
jne .LBB0_21
# %bb.20: # in Loop: Header=BB0_19 Depth=1
xorl %ebp, %ebp
jmp .LBB0_22
.LBB0_23: # %._crit_edge63.loopexit
movl $.L.str.3, %eax
movl $.L.str.4, %ebx
testb %bpl, %bpl
cmovneq %rax, %rbx
jmp .LBB0_24
.LBB0_17:
movl $.L.str.3, %ebx
.LBB0_24: # %._crit_edge63
movl $.Lstr.1, %edi
callq puts@PLT
movq %rbx, %rdi
xorl %eax, %eax
callq printf
callq hipGetLastError
testl %eax, %eax
jne .LBB0_26
# %bb.25:
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_26:
.cfi_def_cfa_offset 192
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z38__device_stub__parallel_max_each_chunkPfS_ii # -- Begin function _Z38__device_stub__parallel_max_each_chunkPfS_ii
.p2align 4, 0x90
.type _Z38__device_stub__parallel_max_each_chunkPfS_ii,@function
_Z38__device_stub__parallel_max_each_chunkPfS_ii: # @_Z38__device_stub__parallel_max_each_chunkPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23parallel_max_each_chunkPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z38__device_stub__parallel_max_each_chunkPfS_ii, .Lfunc_end1-_Z38__device_stub__parallel_max_each_chunkPfS_ii
.cfi_endproc
# -- End function
.globl _Z21serial_max_each_chunkPfS_ii # -- Begin function _Z21serial_max_each_chunkPfS_ii
.p2align 4, 0x90
.type _Z21serial_max_each_chunkPfS_ii,@function
_Z21serial_max_each_chunkPfS_ii: # @_Z21serial_max_each_chunkPfS_ii
.cfi_startproc
# %bb.0:
# kill: def $ecx killed $ecx def $rcx
movl %edx, %r8d
leal (%r8,%rcx), %eax
decl %eax
cltd
idivl %r8d
testl %eax, %eax
jle .LBB2_9
# %bb.1: # %.lr.ph29.preheader
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movslq %r8d, %rdx
movl %eax, %eax
xorl %r10d, %r10d
xorl %r9d, %r9d
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_2: # %.loopexit
# in Loop: Header=BB2_3 Depth=1
addq %rdx, %r9
cmpq %rax, %r10
je .LBB2_8
.LBB2_3: # %.lr.ph29
# =>This Loop Header: Depth=1
# Child Loop BB2_5 Depth 2
movq %r10, %r11
movl $-1069547520, (%rdi,%r10,4) # imm = 0xC0400000
movq %r10, %r14
imulq %rdx, %r14
incq %r10
movl %r10d, %ebx
imull %r8d, %ebx
cmpl %ecx, %ebx
cmovgel %ecx, %ebx
movslq %ebx, %rbx
cmpq %rbx, %r14
jge .LBB2_2
# %bb.4: # %.lr.ph
# in Loop: Header=BB2_3 Depth=1
movss (%rdi,%r11,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %r9, %r14
jmp .LBB2_5
.p2align 4, 0x90
.LBB2_7: # in Loop: Header=BB2_5 Depth=2
incq %r14
cmpq %rbx, %r14
jge .LBB2_2
.LBB2_5: # Parent Loop BB2_3 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rsi,%r14,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
jbe .LBB2_7
# %bb.6: # in Loop: Header=BB2_5 Depth=2
movss %xmm1, (%rdi,%r11,4)
movaps %xmm1, %xmm0
jmp .LBB2_7
.LBB2_8:
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.LBB2_9: # %._crit_edge
movq %rdi, %rax
retq
.Lfunc_end2:
.size _Z21serial_max_each_chunkPfS_ii, .Lfunc_end2-_Z21serial_max_each_chunkPfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23parallel_max_each_chunkPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23parallel_max_each_chunkPfS_ii,@object # @_Z23parallel_max_each_chunkPfS_ii
.section .rodata,"a",@progbits
.globl _Z23parallel_max_each_chunkPfS_ii
.p2align 3, 0x0
_Z23parallel_max_each_chunkPfS_ii:
.quad _Z38__device_stub__parallel_max_each_chunkPfS_ii
.size _Z23parallel_max_each_chunkPfS_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d maximum: %f\n"
.size .L.str, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "right\n"
.size .L.str.3, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "wrong\n"
.size .L.str.4, 7
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "CUDA error: %s\n"
.size .L.str.5, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z23parallel_max_each_chunkPfS_ii"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nserial solution"
.size .Lstr, 17
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n--------correct or wrong---------"
.size .Lstr.1, 35
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__parallel_max_each_chunkPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23parallel_max_each_chunkPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // aslp-aslp-cudamatrix/cu-nnet-mpi-sync.cu
// Copyright 2016 ASLP (author: zhangbinbin)
// Created on 2016-02-24
#include "curand.h"
#ifdef CURAND_CHECK
#undef CURAND_CHECK
#endif
#define CURAND_CHECK(status) { curandAssert(status, __FILE__, __LINE__); }
#include "stdio.h"
inline void curandAssert(curandStatus_t status, const char *file, int line, bool abort=true) {
if (status != CURAND_STATUS_SUCCESS) {
printf("curandAssert: error code %d in file: %s line: %d\n", status, file, line);
if (abort) exit(status);
}
}
const int BLOCK1D = 512;
//const int BLOCK2D = 32;
inline int divup(int x, int y) { return (x + y - 1) / y; }
/// Average
template<typename Real>
__global__
static void cuda_average_kernel(Real *dst, const Real *src, int num) {
int tid = threadIdx.x + threadIdx.y * blockDim.x;
int bid = blockIdx.x + blockIdx.y * gridDim.x;
int step = blockDim.x * blockDim.y * gridDim.x * gridDim.y;
for (int i = tid + bid * blockDim.x * blockDim.y; i < num; i += step) {
dst[i] = (dst[i] + src[i]) / 2;
}
}
template<typename Real>
void cuda_average_impl(Real *dst, const Real *src, int num, cudaStream_t &stream) {
dim3 block(BLOCK1D);
dim3 grid(divup(num, BLOCK1D));
cuda_average_kernel<<<grid, block, 0, stream>>>(dst, src, num);
}
void cuda_average(float *dst, const float *src, int num, cudaStream_t &stream) {
cuda_average_impl(dst, src, num, stream);
}
void cuda_average(double *dst, const double *src, int num, cudaStream_t &stream) {
cuda_average_impl(dst, src, num, stream);
} | code for sm_80
Function : _Z19cuda_average_kernelIdEvPT_PKS0_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0030*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e680000002200 */
/*0040*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000ea20000002100 */
/*0050*/ IMAD R0, R2, c[0x0][0xc], R5 ; /* 0x0000030002007a24 */
/* 0x001fc800078e0205 */
/*0060*/ IMAD R0, R0, c[0x0][0x4], R7 ; /* 0x0000010000007a24 */
/* 0x002fc800078e0207 */
/*0070*/ IMAD R4, R0, c[0x0][0x0], R9 ; /* 0x0000000000047a24 */
/* 0x004fca00078e0209 */
/*0080*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R0, c[0x0][0x4] ; /* 0x0000010000007a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IADD3 R2, R2, c[0x0][0x10], RZ ; /* 0x0000040002027a10 */
/* 0x000fe20007ffe0ff */
/*00d0*/ BSSY B0, 0x3e0 ; /* 0x0000030000007945 */
/* 0x000fe40003800000 */
/*00e0*/ IMAD R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a24 */
/* 0x000fe400078e02ff */
/*00f0*/ IMAD R2, R2, c[0x0][0xc], R5 ; /* 0x0000030002027a24 */
/* 0x000fe400078e0205 */
/*0100*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fe400078e02ff */
/*0110*/ IMAD R2, R2, c[0x0][0x4], R7 ; /* 0x0000010002027a24 */
/* 0x000fc400078e0207 */
/*0120*/ IMAD R0, R0, c[0x0][0x10], RZ ; /* 0x0000040000007a24 */
/* 0x000fe400078e02ff */
/*0130*/ IMAD R2, R2, c[0x0][0x0], R9 ; /* 0x0000000002027a24 */
/* 0x000fe400078e0209 */
/*0140*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*0150*/ IADD3 R5, RZ, -R0, RZ ; /* 0x80000000ff057210 */
/* 0x000fe40007ffe0ff */
/*0160*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc60003f45070 */
/*0170*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0005 */
/*0180*/ LOP3.LUT R5, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff057212 */
/* 0x000fe200078e33ff */
/*0190*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fc600000001ff */
/*01a0*/ IADD3 R5, R5, c[0x0][0x170], R0 ; /* 0x00005c0005057a10 */
/* 0x000fe20007ffe000 */
/*01b0*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*01c0*/ IADD3 R3, R6, 0xffffffe, RZ ; /* 0x0ffffffe06037810 */
/* 0x001fcc0007ffe0ff */
/*01d0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e24000021f000 */
/*01e0*/ IMAD R7, R7, R3, RZ ; /* 0x0000000307077224 */
/* 0x001fc800078e02ff */
/*01f0*/ IMAD.HI.U32 R2, R3, R7, R2 ; /* 0x0000000703027227 */
/* 0x000fcc00078e0002 */
/*0200*/ IMAD.HI.U32 R2, R2, R5, RZ ; /* 0x0000000502027227 */
/* 0x000fca00078e00ff */
/*0210*/ IADD3 R3, -R2, RZ, RZ ; /* 0x000000ff02037210 */
/* 0x000fca0007ffe1ff */
/*0220*/ IMAD R5, R0, R3, R5 ; /* 0x0000000300057224 */
/* 0x000fca00078e0205 */
/*0230*/ ISETP.GE.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f06070 */
/*0240*/ @P0 IMAD.IADD R5, R5, 0x1, -R0 ; /* 0x0000000105050824 */
/* 0x000fe200078e0a00 */
/*0250*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fc80007ffe0ff */
/*0260*/ ISETP.GE.U32.AND P1, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f26070 */
/*0270*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*0280*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*0290*/ IADD3 R3, R2.reuse, 0x1, RZ ; /* 0x0000000102037810 */
/* 0x040fe40007ffe0ff */
/*02a0*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*02b0*/ LOP3.LUT P0, R5, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303057812 */
/* 0x000fe4000780c0ff */
/*02c0*/ MOV R3, R4 ; /* 0x0000000400037202 */
/* 0x000fd60000000f00 */
/*02d0*/ @!P0 BRA 0x3d0 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*02e0*/ MOV R6, 0x8 ; /* 0x0000000800067802 */
/* 0x000fe20000000f00 */
/*02f0*/ IMAD.MOV.U32 R2, RZ, RZ, R5 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0005 */
/*0300*/ IMAD.WIDE R4, R3, R6, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc800078e0206 */
/*0310*/ IMAD.WIDE R6, R3, R6, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fc800078e0206 */
/*0320*/ LDG.E.64 R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x0000a8000c1e1b00 */
/*0330*/ LDG.E.64 R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x000ea2000c1e1b00 */
/*0340*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*0350*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0360*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0370*/ IMAD.WIDE R4, R0, 0x8, R4 ; /* 0x0000000800047825 */
/* 0x001fe200078e0204 */
/*0380*/ DADD R8, R8, R10 ; /* 0x0000000008087229 */
/* 0x004e0c000000000a */
/*0390*/ DMUL R8, R8, 0.5 ; /* 0x3fe0000008087828 */
/* 0x001e0e0000000000 */
/*03a0*/ STG.E.64 [R6.64], R8 ; /* 0x0000000806007986 */
/* 0x0011e4000c101b04 */
/*03b0*/ IMAD.WIDE R6, R0, 0x8, R6 ; /* 0x0000000800067825 */
/* 0x001fe200078e0206 */
/*03c0*/ @P0 BRA 0x320 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*03d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03e0*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*03f0*/ MOV R4, 0x8 ; /* 0x0000000800047802 */
/* 0x002fca0000000f00 */
/*0400*/ IMAD.WIDE R6, R3, R4, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0204 */
/*0410*/ IMAD.WIDE R4, R3, R4, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fe200078e0204 */
/*0420*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ea8000c1e1b00 */
/*0430*/ LDG.E.64 R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea2000c1e1b00 */
/*0440*/ IMAD.WIDE R12, R0, 0x8, R6 ; /* 0x00000008000c7825 */
/* 0x000fe200078e0206 */
/*0450*/ DADD R8, R8, R10 ; /* 0x0000000008087229 */
/* 0x004046000000000a */
/*0460*/ IMAD.WIDE R10, R0, 0x8, R4 ; /* 0x00000008000a7825 */
/* 0x001fc600078e0204 */
/*0470*/ DMUL R8, R8, 0.5 ; /* 0x3fe0000008087828 */
/* 0x002e0e0000000000 */
/*0480*/ STG.E.64 [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x0011e8000c101b04 */
/*0490*/ LDG.E.64 R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea8000c1e1b00 */
/*04a0*/ LDG.E.64 R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x000ea2000c1e1b00 */
/*04b0*/ IMAD.WIDE R6, R0, 0x8, R10 ; /* 0x0000000800067825 */
/* 0x000fe200078e020a */
/*04c0*/ DADD R14, R14, R16 ; /* 0x000000000e0e7229 */
/* 0x0042860000000010 */
/*04d0*/ IMAD.WIDE R16, R0, 0x8, R12 ; /* 0x0000000800107825 */
/* 0x002fc600078e020c */
/*04e0*/ DMUL R14, R14, 0.5 ; /* 0x3fe000000e0e7828 */
/* 0x004e4e0000000000 */
/*04f0*/ STG.E.64 [R10.64], R14 ; /* 0x0000000e0a007986 */
/* 0x0023e8000c101b04 */
/*0500*/ LDG.E.64 R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1b00 */
/*0510*/ LDG.E.64 R20, [R6.64] ; /* 0x0000000406147981 */
/* 0x000ea2000c1e1b00 */
/*0520*/ IMAD.WIDE R8, R0, 0x8, R16 ; /* 0x0000000800087825 */
/* 0x001fc800078e0210 */
/*0530*/ IMAD.WIDE R4, R0, 0x8, R6 ; /* 0x0000000800047825 */
/* 0x000fe200078e0206 */
/*0540*/ DADD R18, R18, R20 ; /* 0x0000000012127229 */
/* 0x004e0c0000000014 */
/*0550*/ DMUL R18, R18, 0.5 ; /* 0x3fe0000012127828 */
/* 0x001e0e0000000000 */
/*0560*/ STG.E.64 [R6.64], R18 ; /* 0x0000001206007986 */
/* 0x0013e8000c101b04 */
/*0570*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1b00 */
/*0580*/ LDG.E.64 R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea2000c1e1b00 */
/*0590*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*05a0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*05b0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fe20003f06270 */
/*05c0*/ DADD R12, R8, R12 ; /* 0x00000000080c7229 */
/* 0x004e0c000000000c */
/*05d0*/ DMUL R12, R12, 0.5 ; /* 0x3fe000000c0c7828 */
/* 0x001e0e0000000000 */
/*05e0*/ STG.E.64 [R4.64], R12 ; /* 0x0000000c04007986 */
/* 0x0013e2000c101b04 */
/*05f0*/ @!P0 BRA 0x3f0 ; /* 0xfffffdf000008947 */
/* 0x000fea000383ffff */
/*0600*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0610*/ BRA 0x610; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z19cuda_average_kernelIfEvPT_PKS0_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0030*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e680000002200 */
/*0040*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000ea20000002100 */
/*0050*/ IMAD R0, R2, c[0x0][0xc], R5 ; /* 0x0000030002007a24 */
/* 0x001fc800078e0205 */
/*0060*/ IMAD R0, R0, c[0x0][0x4], R7 ; /* 0x0000010000007a24 */
/* 0x002fc800078e0207 */
/*0070*/ IMAD R4, R0, c[0x0][0x0], R9 ; /* 0x0000000000047a24 */
/* 0x004fca00078e0209 */
/*0080*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R0, c[0x0][0x4] ; /* 0x0000010000007a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IADD3 R2, R2, c[0x0][0x10], RZ ; /* 0x0000040002027a10 */
/* 0x000fe20007ffe0ff */
/*00d0*/ BSSY B0, 0x3e0 ; /* 0x0000030000007945 */
/* 0x000fe40003800000 */
/*00e0*/ IMAD R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a24 */
/* 0x000fe400078e02ff */
/*00f0*/ IMAD R2, R2, c[0x0][0xc], R5 ; /* 0x0000030002027a24 */
/* 0x000fe400078e0205 */
/*0100*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fe400078e02ff */
/*0110*/ IMAD R2, R2, c[0x0][0x4], R7 ; /* 0x0000010002027a24 */
/* 0x000fc400078e0207 */
/*0120*/ IMAD R0, R0, c[0x0][0x10], RZ ; /* 0x0000040000007a24 */
/* 0x000fe400078e02ff */
/*0130*/ IMAD R2, R2, c[0x0][0x0], R9 ; /* 0x0000000002027a24 */
/* 0x000fe400078e0209 */
/*0140*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*0150*/ IADD3 R5, RZ, -R0, RZ ; /* 0x80000000ff057210 */
/* 0x000fe40007ffe0ff */
/*0160*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*0170*/ MOV R7, R5 ; /* 0x0000000500077202 */
/* 0x000fe40000000f00 */
/*0180*/ LOP3.LUT R5, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff057212 */
/* 0x000fe200078e33ff */
/*0190*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fc600000001ff */
/*01a0*/ IADD3 R5, R5, c[0x0][0x170], R0 ; /* 0x00005c0005057a10 */
/* 0x000fe20007ffe000 */
/*01b0*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*01c0*/ IADD3 R3, R6, 0xffffffe, RZ ; /* 0x0ffffffe06037810 */
/* 0x001fcc0007ffe0ff */
/*01d0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e24000021f000 */
/*01e0*/ IMAD R7, R7, R3, RZ ; /* 0x0000000307077224 */
/* 0x001fc800078e02ff */
/*01f0*/ IMAD.HI.U32 R2, R3, R7, R2 ; /* 0x0000000703027227 */
/* 0x000fcc00078e0002 */
/*0200*/ IMAD.HI.U32 R2, R2, R5, RZ ; /* 0x0000000502027227 */
/* 0x000fca00078e00ff */
/*0210*/ IADD3 R3, -R2, RZ, RZ ; /* 0x000000ff02037210 */
/* 0x000fca0007ffe1ff */
/*0220*/ IMAD R5, R0, R3, R5 ; /* 0x0000000300057224 */
/* 0x000fca00078e0205 */
/*0230*/ ISETP.GE.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f06070 */
/*0240*/ @P0 IADD3 R5, -R0, R5, RZ ; /* 0x0000000500050210 */
/* 0x000fe40007ffe1ff */
/*0250*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*0260*/ ISETP.GE.U32.AND P1, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f26070 */
/*0270*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*0280*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*0290*/ IADD3 R3, R2.reuse, 0x1, RZ ; /* 0x0000000102037810 */
/* 0x040fe40007ffe0ff */
/*02a0*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*02b0*/ LOP3.LUT P0, R5, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303057812 */
/* 0x000fe4000780c0ff */
/*02c0*/ MOV R3, R4 ; /* 0x0000000400037202 */
/* 0x000fd60000000f00 */
/*02d0*/ @!P0 BRA 0x3d0 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*02e0*/ MOV R6, 0x4 ; /* 0x0000000400067802 */
/* 0x000fe40000000f00 */
/*02f0*/ MOV R2, R5 ; /* 0x0000000500027202 */
/* 0x000fc60000000f00 */
/*0300*/ IMAD.WIDE R4, R3, R6, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc800078e0206 */
/*0310*/ IMAD.WIDE R6, R3, R6, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fc800078e0206 */
/*0320*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x0000a8000c1e1900 */
/*0330*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000ea2000c1e1900 */
/*0340*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*0350*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0360*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0370*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fc800078e0204 */
/*0380*/ FADD R8, R8, R9 ; /* 0x0000000908087221 */
/* 0x004fc80000000000 */
/*0390*/ FMUL R9, R8, 0.5 ; /* 0x3f00000008097820 */
/* 0x000fca0000400000 */
/*03a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e4000c101904 */
/*03b0*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x001fe200078e0206 */
/*03c0*/ @P0 BRA 0x320 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*03d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03e0*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*03f0*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x002fd400000001ff */
/*0400*/ IMAD.WIDE R4, R3, R6, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fc800078e0206 */
/*0410*/ IMAD.WIDE R6, R3, R6, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fe200078e0206 */
/*0420*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea8000c1e1900 */
/*0430*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea2000c1e1900 */
/*0440*/ IMAD.WIDE R10, R0, 0x4, R6 ; /* 0x00000004000a7825 */
/* 0x000fc800078e0206 */
/*0450*/ FADD R2, R2, R9 ; /* 0x0000000902027221 */
/* 0x004fe40000000000 */
/*0460*/ IMAD.WIDE R8, R0, 0x4, R4 ; /* 0x0000000400087825 */
/* 0x000fc800078e0204 */
/*0470*/ FMUL R15, R2, 0.5 ; /* 0x3f000000020f7820 */
/* 0x000fca0000400000 */
/*0480*/ STG.E [R4.64], R15 ; /* 0x0000000f04007986 */
/* 0x0001e8000c101904 */
/*0490*/ LDG.E R2, [R10.64] ; /* 0x000000040a027981 */
/* 0x000ea8000c1e1900 */
/*04a0*/ LDG.E R13, [R8.64] ; /* 0x00000004080d7981 */
/* 0x000ea2000c1e1900 */
/*04b0*/ IMAD.WIDE R6, R0, 0x4, R8 ; /* 0x0000000400067825 */
/* 0x000fc800078e0208 */
/*04c0*/ FADD R2, R2, R13 ; /* 0x0000000d02027221 */
/* 0x004fe40000000000 */
/*04d0*/ IMAD.WIDE R12, R0, 0x4, R10 ; /* 0x00000004000c7825 */
/* 0x000fc800078e020a */
/*04e0*/ FMUL R17, R2, 0.5 ; /* 0x3f00000002117820 */
/* 0x000fca0000400000 */
/*04f0*/ STG.E [R8.64], R17 ; /* 0x0000001108007986 */
/* 0x0003e8000c101904 */
/*0500*/ LDG.E R2, [R12.64] ; /* 0x000000040c027981 */
/* 0x000ea8000c1e1900 */
/*0510*/ LDG.E R19, [R6.64] ; /* 0x0000000406137981 */
/* 0x000ea2000c1e1900 */
/*0520*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */
/* 0x000fc800078e020c */
/*0530*/ IMAD.WIDE R4, R0, 0x4, R6 ; /* 0x0000000400047825 */
/* 0x001fc800078e0206 */
/*0540*/ FADD R2, R2, R19 ; /* 0x0000001302027221 */
/* 0x004fc80000000000 */
/*0550*/ FMUL R15, R2, 0.5 ; /* 0x3f000000020f7820 */
/* 0x000fca0000400000 */
/*0560*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x0003e8000c101904 */
/*0570*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea8000c1e1900 */
/*0580*/ LDG.E R19, [R4.64] ; /* 0x0000000404137981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*05a0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*05b0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fe20003f06270 */
/*05c0*/ FADD R19, R10, R19 ; /* 0x000000130a137221 */
/* 0x004fc80000000000 */
/*05d0*/ FMUL R19, R19, 0.5 ; /* 0x3f00000013137820 */
/* 0x000fca0000400000 */
/*05e0*/ STG.E [R4.64], R19 ; /* 0x0000001304007986 */
/* 0x0003e6000c101904 */
/*05f0*/ @!P0 BRA 0x3f0 ; /* 0xfffffdf000008947 */
/* 0x000fea000383ffff */
/*0600*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0610*/ BRA 0x610; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // aslp-aslp-cudamatrix/cu-nnet-mpi-sync.cu
// Copyright 2016 ASLP (author: zhangbinbin)
// Created on 2016-02-24
#include "curand.h"
#ifdef CURAND_CHECK
#undef CURAND_CHECK
#endif
#define CURAND_CHECK(status) { curandAssert(status, __FILE__, __LINE__); }
#include "stdio.h"
inline void curandAssert(curandStatus_t status, const char *file, int line, bool abort=true) {
if (status != CURAND_STATUS_SUCCESS) {
printf("curandAssert: error code %d in file: %s line: %d\n", status, file, line);
if (abort) exit(status);
}
}
const int BLOCK1D = 512;
//const int BLOCK2D = 32;
inline int divup(int x, int y) { return (x + y - 1) / y; }
/// Average
template<typename Real>
__global__
static void cuda_average_kernel(Real *dst, const Real *src, int num) {
int tid = threadIdx.x + threadIdx.y * blockDim.x;
int bid = blockIdx.x + blockIdx.y * gridDim.x;
int step = blockDim.x * blockDim.y * gridDim.x * gridDim.y;
for (int i = tid + bid * blockDim.x * blockDim.y; i < num; i += step) {
dst[i] = (dst[i] + src[i]) / 2;
}
}
template<typename Real>
void cuda_average_impl(Real *dst, const Real *src, int num, cudaStream_t &stream) {
dim3 block(BLOCK1D);
dim3 grid(divup(num, BLOCK1D));
cuda_average_kernel<<<grid, block, 0, stream>>>(dst, src, num);
}
void cuda_average(float *dst, const float *src, int num, cudaStream_t &stream) {
cuda_average_impl(dst, src, num, stream);
}
void cuda_average(double *dst, const double *src, int num, cudaStream_t &stream) {
cuda_average_impl(dst, src, num, stream);
} | .file "tmpxft_00043f67_00000000-6_cu-nnet-mpi-sync.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL50__device_stub__Z19cuda_average_kernelIfEvPT_PKS0_iPfPKfi, @function
_ZL50__device_stub__Z19cuda_average_kernelIfEvPT_PKS0_iPfPKfi:
.LFB2088:
.cfi_startproc
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19cuda_average_kernelIfEvPT_PKS0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _ZL50__device_stub__Z19cuda_average_kernelIfEvPT_PKS0_iPfPKfi, .-_ZL50__device_stub__Z19cuda_average_kernelIfEvPT_PKS0_iPfPKfi
.type _Z19cuda_average_kernelIfEvPT_PKS0_i, @function
_Z19cuda_average_kernelIfEvPT_PKS0_i:
.LFB2141:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL50__device_stub__Z19cuda_average_kernelIfEvPT_PKS0_iPfPKfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2141:
.size _Z19cuda_average_kernelIfEvPT_PKS0_i, .-_Z19cuda_average_kernelIfEvPT_PKS0_i
.type _ZL50__device_stub__Z19cuda_average_kernelIdEvPT_PKS0_iPdPKdi, @function
_ZL50__device_stub__Z19cuda_average_kernelIdEvPT_PKS0_iPdPKdi:
.LFB2090:
.cfi_startproc
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19cuda_average_kernelIdEvPT_PKS0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _ZL50__device_stub__Z19cuda_average_kernelIdEvPT_PKS0_iPdPKdi, .-_ZL50__device_stub__Z19cuda_average_kernelIdEvPT_PKS0_iPdPKdi
.type _Z19cuda_average_kernelIdEvPT_PKS0_i, @function
_Z19cuda_average_kernelIdEvPT_PKS0_i:
.LFB2143:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL50__device_stub__Z19cuda_average_kernelIdEvPT_PKS0_iPdPKdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2143:
.size _Z19cuda_average_kernelIdEvPT_PKS0_i, .-_Z19cuda_average_kernelIdEvPT_PKS0_i
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12cuda_averagePfPKfiRP11CUstream_st
.type _Z12cuda_averagePfPKfiRP11CUstream_st, @function
_Z12cuda_averagePfPKfiRP11CUstream_st:
.LFB2062:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movq %rsi, %r12
movl %edx, %ebx
movl $512, 8(%rsp)
movl $1, 12(%rsp)
leal 1022(%rdx), %eax
addl $511, %edx
cmovns %edx, %eax
sarl $9, %eax
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movq (%rcx), %r9
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L19:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movl %ebx, %edx
movq %r12, %rsi
movq %rbp, %rdi
call _ZL50__device_stub__Z19cuda_average_kernelIfEvPT_PKS0_iPfPKfi
jmp .L19
.cfi_endproc
.LFE2062:
.size _Z12cuda_averagePfPKfiRP11CUstream_st, .-_Z12cuda_averagePfPKfiRP11CUstream_st
.globl _Z12cuda_averagePdPKdiRP11CUstream_st
.type _Z12cuda_averagePdPKdiRP11CUstream_st, @function
_Z12cuda_averagePdPKdiRP11CUstream_st:
.LFB2063:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movq %rsi, %r12
movl %edx, %ebx
movl $512, 8(%rsp)
movl $1, 12(%rsp)
leal 1022(%rdx), %eax
addl $511, %edx
cmovns %edx, %eax
sarl $9, %eax
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movq (%rcx), %r9
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L23:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movl %ebx, %edx
movq %r12, %rsi
movq %rbp, %rdi
call _ZL50__device_stub__Z19cuda_average_kernelIdEvPT_PKS0_iPdPKdi
jmp .L23
.cfi_endproc
.LFE2063:
.size _Z12cuda_averagePdPKdiRP11CUstream_st, .-_Z12cuda_averagePdPKdiRP11CUstream_st
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19cuda_average_kernelIdEvPT_PKS0_i"
.align 8
.LC1:
.string "_Z19cuda_average_kernelIfEvPT_PKS0_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2093:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19cuda_average_kernelIdEvPT_PKS0_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z19cuda_average_kernelIfEvPT_PKS0_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // aslp-aslp-cudamatrix/cu-nnet-mpi-sync.cu
// Copyright 2016 ASLP (author: zhangbinbin)
// Created on 2016-02-24
#include "curand.h"
#ifdef CURAND_CHECK
#undef CURAND_CHECK
#endif
#define CURAND_CHECK(status) { curandAssert(status, __FILE__, __LINE__); }
#include "stdio.h"
inline void curandAssert(curandStatus_t status, const char *file, int line, bool abort=true) {
if (status != CURAND_STATUS_SUCCESS) {
printf("curandAssert: error code %d in file: %s line: %d\n", status, file, line);
if (abort) exit(status);
}
}
const int BLOCK1D = 512;
//const int BLOCK2D = 32;
inline int divup(int x, int y) { return (x + y - 1) / y; }
/// Average
template<typename Real>
__global__
static void cuda_average_kernel(Real *dst, const Real *src, int num) {
int tid = threadIdx.x + threadIdx.y * blockDim.x;
int bid = blockIdx.x + blockIdx.y * gridDim.x;
int step = blockDim.x * blockDim.y * gridDim.x * gridDim.y;
for (int i = tid + bid * blockDim.x * blockDim.y; i < num; i += step) {
dst[i] = (dst[i] + src[i]) / 2;
}
}
template<typename Real>
void cuda_average_impl(Real *dst, const Real *src, int num, cudaStream_t &stream) {
dim3 block(BLOCK1D);
dim3 grid(divup(num, BLOCK1D));
cuda_average_kernel<<<grid, block, 0, stream>>>(dst, src, num);
}
void cuda_average(float *dst, const float *src, int num, cudaStream_t &stream) {
cuda_average_impl(dst, src, num, stream);
}
void cuda_average(double *dst, const double *src, int num, cudaStream_t &stream) {
cuda_average_impl(dst, src, num, stream);
} | // aslp-aslp-cudamatrix/cu-nnet-mpi-sync.cu
// Copyright 2016 ASLP (author: zhangbinbin)
// Created on 2016-02-24
#include <hip/hip_runtime.h>
#include "hiprand/hiprand.h"
#ifdef CURAND_CHECK
#undef CURAND_CHECK
#endif
#define CURAND_CHECK(status) { curandAssert(status, __FILE__, __LINE__); }
#include "stdio.h"
inline void curandAssert(hiprandStatus_t status, const char *file, int line, bool abort=true) {
if (status != HIPRAND_STATUS_SUCCESS) {
printf("curandAssert: error code %d in file: %s line: %d\n", status, file, line);
if (abort) exit(status);
}
}
const int BLOCK1D = 512;
//const int BLOCK2D = 32;
inline int divup(int x, int y) { return (x + y - 1) / y; }
/// Average
template<typename Real>
__global__
static void cuda_average_kernel(Real *dst, const Real *src, int num) {
int tid = threadIdx.x + threadIdx.y * blockDim.x;
int bid = blockIdx.x + blockIdx.y * gridDim.x;
int step = blockDim.x * blockDim.y * gridDim.x * gridDim.y;
for (int i = tid + bid * blockDim.x * blockDim.y; i < num; i += step) {
dst[i] = (dst[i] + src[i]) / 2;
}
}
template<typename Real>
void cuda_average_impl(Real *dst, const Real *src, int num, hipStream_t &stream) {
dim3 block(BLOCK1D);
dim3 grid(divup(num, BLOCK1D));
cuda_average_kernel<<<grid, block, 0, stream>>>(dst, src, num);
}
void cuda_average(float *dst, const float *src, int num, hipStream_t &stream) {
cuda_average_impl(dst, src, num, stream);
}
void cuda_average(double *dst, const double *src, int num, hipStream_t &stream) {
cuda_average_impl(dst, src, num, stream);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // aslp-aslp-cudamatrix/cu-nnet-mpi-sync.cu
// Copyright 2016 ASLP (author: zhangbinbin)
// Created on 2016-02-24
#include <hip/hip_runtime.h>
#include "hiprand/hiprand.h"
#ifdef CURAND_CHECK
#undef CURAND_CHECK
#endif
#define CURAND_CHECK(status) { curandAssert(status, __FILE__, __LINE__); }
#include "stdio.h"
inline void curandAssert(hiprandStatus_t status, const char *file, int line, bool abort=true) {
if (status != HIPRAND_STATUS_SUCCESS) {
printf("curandAssert: error code %d in file: %s line: %d\n", status, file, line);
if (abort) exit(status);
}
}
const int BLOCK1D = 512;
//const int BLOCK2D = 32;
inline int divup(int x, int y) { return (x + y - 1) / y; }
/// Average
template<typename Real>
__global__
static void cuda_average_kernel(Real *dst, const Real *src, int num) {
int tid = threadIdx.x + threadIdx.y * blockDim.x;
int bid = blockIdx.x + blockIdx.y * gridDim.x;
int step = blockDim.x * blockDim.y * gridDim.x * gridDim.y;
for (int i = tid + bid * blockDim.x * blockDim.y; i < num; i += step) {
dst[i] = (dst[i] + src[i]) / 2;
}
}
template<typename Real>
void cuda_average_impl(Real *dst, const Real *src, int num, hipStream_t &stream) {
dim3 block(BLOCK1D);
dim3 grid(divup(num, BLOCK1D));
cuda_average_kernel<<<grid, block, 0, stream>>>(dst, src, num);
}
void cuda_average(float *dst, const float *src, int num, hipStream_t &stream) {
cuda_average_impl(dst, src, num, stream);
}
void cuda_average(double *dst, const double *src, int num, hipStream_t &stream) {
cuda_average_impl(dst, src, num, stream);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL19cuda_average_kernelIfEvPT_PKS0_i,"axG",@progbits,_ZL19cuda_average_kernelIfEvPT_PKS0_i,comdat
.globl _ZL19cuda_average_kernelIfEvPT_PKS0_i
.p2align 8
.type _ZL19cuda_average_kernelIfEvPT_PKS0_i,@function
_ZL19cuda_average_kernelIfEvPT_PKS0_i:
s_clause 0x2
s_load_b32 s8, s[0:1], 0x18
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s5, s8, s15
s_lshr_b32 s9, s4, 16
s_add_i32 s5, s5, s14
s_and_b32 s11, s4, 0xffff
v_mad_u64_u32 v[2:3], null, s5, s9, v[1:2]
v_and_b32_e32 v3, 0x3ff, v0
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v2, s11, v[3:4]
v_cmpx_gt_i32_e64 s10, v0
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x4
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_mul_i32 s0, s9, s11
s_mov_b32 s1, 0
s_mul_i32 s0, s0, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s0, s2
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v3, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, s8
global_load_b32 v7, v[3:4], off
global_load_b32 v5, v[5:6], off
v_add_nc_u32_e32 v0, s2, v0
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v5, v7, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_i32_e64 s0, s10, v0
v_mul_f32_e32 v5, 0.5, v5
s_delay_alu instid0(VALU_DEP_2)
s_or_b32 s1, s0, s1
global_store_b32 v[3:4], v5, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL19cuda_average_kernelIfEvPT_PKS0_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL19cuda_average_kernelIfEvPT_PKS0_i,"axG",@progbits,_ZL19cuda_average_kernelIfEvPT_PKS0_i,comdat
.Lfunc_end0:
.size _ZL19cuda_average_kernelIfEvPT_PKS0_i, .Lfunc_end0-_ZL19cuda_average_kernelIfEvPT_PKS0_i
.section .AMDGPU.csdata,"",@progbits
.section .text._ZL19cuda_average_kernelIdEvPT_PKS0_i,"axG",@progbits,_ZL19cuda_average_kernelIdEvPT_PKS0_i,comdat
.globl _ZL19cuda_average_kernelIdEvPT_PKS0_i
.p2align 8
.type _ZL19cuda_average_kernelIdEvPT_PKS0_i,@function
_ZL19cuda_average_kernelIdEvPT_PKS0_i:
s_clause 0x2
s_load_b32 s8, s[0:1], 0x18
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s5, s8, s15
s_lshr_b32 s9, s4, 16
s_add_i32 s5, s5, s14
s_and_b32 s11, s4, 0xffff
v_mad_u64_u32 v[2:3], null, s5, s9, v[1:2]
v_and_b32_e32 v3, 0x3ff, v0
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v2, s11, v[3:4]
v_cmpx_gt_i32_e64 s10, v0
s_cbranch_execz .LBB1_3
s_load_b32 s2, s[2:3], 0x4
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_mul_i32 s0, s9, s11
s_mov_b32 s1, 0
s_mul_i32 s0, s0, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[1:2], 3, v[0:1]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s0, s2
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 3
.p2align 6
.LBB1_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v3, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
v_add_nc_u32_e32 v0, s2, v0
global_load_b64 v[7:8], v[3:4], off
global_load_b64 v[5:6], v[5:6], off
v_add_co_u32 v1, s0, v1, s8
v_cmp_le_i32_e32 vcc_lo, s10, v0
v_add_co_ci_u32_e64 v2, s0, s9, v2, s0
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_add_f64 v[5:6], v[7:8], v[5:6]
s_delay_alu instid0(VALU_DEP_1)
v_mul_f64 v[5:6], v[5:6], 0.5
global_store_b64 v[3:4], v[5:6], off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL19cuda_average_kernelIdEvPT_PKS0_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL19cuda_average_kernelIdEvPT_PKS0_i,"axG",@progbits,_ZL19cuda_average_kernelIdEvPT_PKS0_i,comdat
.Lfunc_end1:
.size _ZL19cuda_average_kernelIdEvPT_PKS0_i, .Lfunc_end1-_ZL19cuda_average_kernelIdEvPT_PKS0_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL19cuda_average_kernelIfEvPT_PKS0_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL19cuda_average_kernelIfEvPT_PKS0_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL19cuda_average_kernelIdEvPT_PKS0_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL19cuda_average_kernelIdEvPT_PKS0_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // aslp-aslp-cudamatrix/cu-nnet-mpi-sync.cu
// Copyright 2016 ASLP (author: zhangbinbin)
// Created on 2016-02-24
#include <hip/hip_runtime.h>
#include "hiprand/hiprand.h"
#ifdef CURAND_CHECK
#undef CURAND_CHECK
#endif
#define CURAND_CHECK(status) { curandAssert(status, __FILE__, __LINE__); }
#include "stdio.h"
inline void curandAssert(hiprandStatus_t status, const char *file, int line, bool abort=true) {
if (status != HIPRAND_STATUS_SUCCESS) {
printf("curandAssert: error code %d in file: %s line: %d\n", status, file, line);
if (abort) exit(status);
}
}
const int BLOCK1D = 512;
//const int BLOCK2D = 32;
inline int divup(int x, int y) { return (x + y - 1) / y; }
/// Average
template<typename Real>
__global__
static void cuda_average_kernel(Real *dst, const Real *src, int num) {
int tid = threadIdx.x + threadIdx.y * blockDim.x;
int bid = blockIdx.x + blockIdx.y * gridDim.x;
int step = blockDim.x * blockDim.y * gridDim.x * gridDim.y;
for (int i = tid + bid * blockDim.x * blockDim.y; i < num; i += step) {
dst[i] = (dst[i] + src[i]) / 2;
}
}
template<typename Real>
void cuda_average_impl(Real *dst, const Real *src, int num, hipStream_t &stream) {
dim3 block(BLOCK1D);
dim3 grid(divup(num, BLOCK1D));
cuda_average_kernel<<<grid, block, 0, stream>>>(dst, src, num);
}
void cuda_average(float *dst, const float *src, int num, hipStream_t &stream) {
cuda_average_impl(dst, src, num, stream);
}
void cuda_average(double *dst, const double *src, int num, hipStream_t &stream) {
cuda_average_impl(dst, src, num, stream);
} | .text
.file "cu-nnet-mpi-sync.hip"
.globl _Z12cuda_averagePfPKfiRP12ihipStream_t # -- Begin function _Z12cuda_averagePfPKfiRP12ihipStream_t
.p2align 4, 0x90
.type _Z12cuda_averagePfPKfiRP12ihipStream_t,@function
_Z12cuda_averagePfPKfiRP12ihipStream_t: # @_Z12cuda_averagePfPKfiRP12ihipStream_t
.cfi_startproc
# %bb.0:
jmp _Z17cuda_average_implIfEvPT_PKS0_iRP12ihipStream_t # TAILCALL
.Lfunc_end0:
.size _Z12cuda_averagePfPKfiRP12ihipStream_t, .Lfunc_end0-_Z12cuda_averagePfPKfiRP12ihipStream_t
.cfi_endproc
# -- End function
.section .text._Z17cuda_average_implIfEvPT_PKS0_iRP12ihipStream_t,"axG",@progbits,_Z17cuda_average_implIfEvPT_PKS0_iRP12ihipStream_t,comdat
.weak _Z17cuda_average_implIfEvPT_PKS0_iRP12ihipStream_t # -- Begin function _Z17cuda_average_implIfEvPT_PKS0_iRP12ihipStream_t
.p2align 4, 0x90
.type _Z17cuda_average_implIfEvPT_PKS0_iRP12ihipStream_t,@function
_Z17cuda_average_implIfEvPT_PKS0_iRP12ihipStream_t: # @_Z17cuda_average_implIfEvPT_PKS0_iRP12ihipStream_t
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %edx, %ebx
movq %rsi, %r14
movq %rdi, %r15
leal 511(%rbx), %eax
leal 1022(%rbx), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
movq (%rcx), %r9
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movl %ebx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL19cuda_average_kernelIfEvPT_PKS0_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z17cuda_average_implIfEvPT_PKS0_iRP12ihipStream_t, .Lfunc_end1-_Z17cuda_average_implIfEvPT_PKS0_iRP12ihipStream_t
.cfi_endproc
# -- End function
.text
.globl _Z12cuda_averagePdPKdiRP12ihipStream_t # -- Begin function _Z12cuda_averagePdPKdiRP12ihipStream_t
.p2align 4, 0x90
.type _Z12cuda_averagePdPKdiRP12ihipStream_t,@function
_Z12cuda_averagePdPKdiRP12ihipStream_t: # @_Z12cuda_averagePdPKdiRP12ihipStream_t
.cfi_startproc
# %bb.0:
jmp _Z17cuda_average_implIdEvPT_PKS0_iRP12ihipStream_t # TAILCALL
.Lfunc_end2:
.size _Z12cuda_averagePdPKdiRP12ihipStream_t, .Lfunc_end2-_Z12cuda_averagePdPKdiRP12ihipStream_t
.cfi_endproc
# -- End function
.section .text._Z17cuda_average_implIdEvPT_PKS0_iRP12ihipStream_t,"axG",@progbits,_Z17cuda_average_implIdEvPT_PKS0_iRP12ihipStream_t,comdat
.weak _Z17cuda_average_implIdEvPT_PKS0_iRP12ihipStream_t # -- Begin function _Z17cuda_average_implIdEvPT_PKS0_iRP12ihipStream_t
.p2align 4, 0x90
.type _Z17cuda_average_implIdEvPT_PKS0_iRP12ihipStream_t,@function
_Z17cuda_average_implIdEvPT_PKS0_iRP12ihipStream_t: # @_Z17cuda_average_implIdEvPT_PKS0_iRP12ihipStream_t
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %edx, %ebx
movq %rsi, %r14
movq %rdi, %r15
leal 511(%rbx), %eax
leal 1022(%rbx), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
movq (%rcx), %r9
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movl %ebx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL19cuda_average_kernelIdEvPT_PKS0_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z17cuda_average_implIdEvPT_PKS0_iRP12ihipStream_t, .Lfunc_end3-_Z17cuda_average_implIdEvPT_PKS0_iRP12ihipStream_t
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function _ZL34__device_stub__cuda_average_kernelIfEvPT_PKS0_i
.type _ZL34__device_stub__cuda_average_kernelIfEvPT_PKS0_i,@function
_ZL34__device_stub__cuda_average_kernelIfEvPT_PKS0_i: # @_ZL34__device_stub__cuda_average_kernelIfEvPT_PKS0_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL19cuda_average_kernelIfEvPT_PKS0_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size _ZL34__device_stub__cuda_average_kernelIfEvPT_PKS0_i, .Lfunc_end4-_ZL34__device_stub__cuda_average_kernelIfEvPT_PKS0_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL34__device_stub__cuda_average_kernelIdEvPT_PKS0_i
.type _ZL34__device_stub__cuda_average_kernelIdEvPT_PKS0_i,@function
_ZL34__device_stub__cuda_average_kernelIdEvPT_PKS0_i: # @_ZL34__device_stub__cuda_average_kernelIdEvPT_PKS0_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL19cuda_average_kernelIdEvPT_PKS0_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end5:
.size _ZL34__device_stub__cuda_average_kernelIdEvPT_PKS0_i, .Lfunc_end5-_ZL34__device_stub__cuda_average_kernelIdEvPT_PKS0_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL19cuda_average_kernelIfEvPT_PKS0_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL19cuda_average_kernelIdEvPT_PKS0_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _ZL19cuda_average_kernelIfEvPT_PKS0_i,@object # @_ZL19cuda_average_kernelIfEvPT_PKS0_i
.section .rodata,"a",@progbits
.p2align 3, 0x0
_ZL19cuda_average_kernelIfEvPT_PKS0_i:
.quad _ZL34__device_stub__cuda_average_kernelIfEvPT_PKS0_i
.size _ZL19cuda_average_kernelIfEvPT_PKS0_i, 8
.type _ZL19cuda_average_kernelIdEvPT_PKS0_i,@object # @_ZL19cuda_average_kernelIdEvPT_PKS0_i
.p2align 3, 0x0
_ZL19cuda_average_kernelIdEvPT_PKS0_i:
.quad _ZL34__device_stub__cuda_average_kernelIdEvPT_PKS0_i
.size _ZL19cuda_average_kernelIdEvPT_PKS0_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_ZL19cuda_average_kernelIfEvPT_PKS0_i"
.size .L__unnamed_1, 38
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_ZL19cuda_average_kernelIdEvPT_PKS0_i"
.size .L__unnamed_2, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZL34__device_stub__cuda_average_kernelIfEvPT_PKS0_i
.addrsig_sym _ZL34__device_stub__cuda_average_kernelIdEvPT_PKS0_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZL19cuda_average_kernelIfEvPT_PKS0_i
.addrsig_sym _ZL19cuda_average_kernelIdEvPT_PKS0_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19cuda_average_kernelIdEvPT_PKS0_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0030*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e680000002200 */
/*0040*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000ea20000002100 */
/*0050*/ IMAD R0, R2, c[0x0][0xc], R5 ; /* 0x0000030002007a24 */
/* 0x001fc800078e0205 */
/*0060*/ IMAD R0, R0, c[0x0][0x4], R7 ; /* 0x0000010000007a24 */
/* 0x002fc800078e0207 */
/*0070*/ IMAD R4, R0, c[0x0][0x0], R9 ; /* 0x0000000000047a24 */
/* 0x004fca00078e0209 */
/*0080*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R0, c[0x0][0x4] ; /* 0x0000010000007a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IADD3 R2, R2, c[0x0][0x10], RZ ; /* 0x0000040002027a10 */
/* 0x000fe20007ffe0ff */
/*00d0*/ BSSY B0, 0x3e0 ; /* 0x0000030000007945 */
/* 0x000fe40003800000 */
/*00e0*/ IMAD R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a24 */
/* 0x000fe400078e02ff */
/*00f0*/ IMAD R2, R2, c[0x0][0xc], R5 ; /* 0x0000030002027a24 */
/* 0x000fe400078e0205 */
/*0100*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fe400078e02ff */
/*0110*/ IMAD R2, R2, c[0x0][0x4], R7 ; /* 0x0000010002027a24 */
/* 0x000fc400078e0207 */
/*0120*/ IMAD R0, R0, c[0x0][0x10], RZ ; /* 0x0000040000007a24 */
/* 0x000fe400078e02ff */
/*0130*/ IMAD R2, R2, c[0x0][0x0], R9 ; /* 0x0000000002027a24 */
/* 0x000fe400078e0209 */
/*0140*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*0150*/ IADD3 R5, RZ, -R0, RZ ; /* 0x80000000ff057210 */
/* 0x000fe40007ffe0ff */
/*0160*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc60003f45070 */
/*0170*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0005 */
/*0180*/ LOP3.LUT R5, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff057212 */
/* 0x000fe200078e33ff */
/*0190*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fc600000001ff */
/*01a0*/ IADD3 R5, R5, c[0x0][0x170], R0 ; /* 0x00005c0005057a10 */
/* 0x000fe20007ffe000 */
/*01b0*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*01c0*/ IADD3 R3, R6, 0xffffffe, RZ ; /* 0x0ffffffe06037810 */
/* 0x001fcc0007ffe0ff */
/*01d0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e24000021f000 */
/*01e0*/ IMAD R7, R7, R3, RZ ; /* 0x0000000307077224 */
/* 0x001fc800078e02ff */
/*01f0*/ IMAD.HI.U32 R2, R3, R7, R2 ; /* 0x0000000703027227 */
/* 0x000fcc00078e0002 */
/*0200*/ IMAD.HI.U32 R2, R2, R5, RZ ; /* 0x0000000502027227 */
/* 0x000fca00078e00ff */
/*0210*/ IADD3 R3, -R2, RZ, RZ ; /* 0x000000ff02037210 */
/* 0x000fca0007ffe1ff */
/*0220*/ IMAD R5, R0, R3, R5 ; /* 0x0000000300057224 */
/* 0x000fca00078e0205 */
/*0230*/ ISETP.GE.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f06070 */
/*0240*/ @P0 IMAD.IADD R5, R5, 0x1, -R0 ; /* 0x0000000105050824 */
/* 0x000fe200078e0a00 */
/*0250*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fc80007ffe0ff */
/*0260*/ ISETP.GE.U32.AND P1, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f26070 */
/*0270*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*0280*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*0290*/ IADD3 R3, R2.reuse, 0x1, RZ ; /* 0x0000000102037810 */
/* 0x040fe40007ffe0ff */
/*02a0*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*02b0*/ LOP3.LUT P0, R5, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303057812 */
/* 0x000fe4000780c0ff */
/*02c0*/ MOV R3, R4 ; /* 0x0000000400037202 */
/* 0x000fd60000000f00 */
/*02d0*/ @!P0 BRA 0x3d0 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*02e0*/ MOV R6, 0x8 ; /* 0x0000000800067802 */
/* 0x000fe20000000f00 */
/*02f0*/ IMAD.MOV.U32 R2, RZ, RZ, R5 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0005 */
/*0300*/ IMAD.WIDE R4, R3, R6, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc800078e0206 */
/*0310*/ IMAD.WIDE R6, R3, R6, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fc800078e0206 */
/*0320*/ LDG.E.64 R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x0000a8000c1e1b00 */
/*0330*/ LDG.E.64 R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x000ea2000c1e1b00 */
/*0340*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*0350*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0360*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0370*/ IMAD.WIDE R4, R0, 0x8, R4 ; /* 0x0000000800047825 */
/* 0x001fe200078e0204 */
/*0380*/ DADD R8, R8, R10 ; /* 0x0000000008087229 */
/* 0x004e0c000000000a */
/*0390*/ DMUL R8, R8, 0.5 ; /* 0x3fe0000008087828 */
/* 0x001e0e0000000000 */
/*03a0*/ STG.E.64 [R6.64], R8 ; /* 0x0000000806007986 */
/* 0x0011e4000c101b04 */
/*03b0*/ IMAD.WIDE R6, R0, 0x8, R6 ; /* 0x0000000800067825 */
/* 0x001fe200078e0206 */
/*03c0*/ @P0 BRA 0x320 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*03d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03e0*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*03f0*/ MOV R4, 0x8 ; /* 0x0000000800047802 */
/* 0x002fca0000000f00 */
/*0400*/ IMAD.WIDE R6, R3, R4, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0204 */
/*0410*/ IMAD.WIDE R4, R3, R4, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fe200078e0204 */
/*0420*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ea8000c1e1b00 */
/*0430*/ LDG.E.64 R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea2000c1e1b00 */
/*0440*/ IMAD.WIDE R12, R0, 0x8, R6 ; /* 0x00000008000c7825 */
/* 0x000fe200078e0206 */
/*0450*/ DADD R8, R8, R10 ; /* 0x0000000008087229 */
/* 0x004046000000000a */
/*0460*/ IMAD.WIDE R10, R0, 0x8, R4 ; /* 0x00000008000a7825 */
/* 0x001fc600078e0204 */
/*0470*/ DMUL R8, R8, 0.5 ; /* 0x3fe0000008087828 */
/* 0x002e0e0000000000 */
/*0480*/ STG.E.64 [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x0011e8000c101b04 */
/*0490*/ LDG.E.64 R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea8000c1e1b00 */
/*04a0*/ LDG.E.64 R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x000ea2000c1e1b00 */
/*04b0*/ IMAD.WIDE R6, R0, 0x8, R10 ; /* 0x0000000800067825 */
/* 0x000fe200078e020a */
/*04c0*/ DADD R14, R14, R16 ; /* 0x000000000e0e7229 */
/* 0x0042860000000010 */
/*04d0*/ IMAD.WIDE R16, R0, 0x8, R12 ; /* 0x0000000800107825 */
/* 0x002fc600078e020c */
/*04e0*/ DMUL R14, R14, 0.5 ; /* 0x3fe000000e0e7828 */
/* 0x004e4e0000000000 */
/*04f0*/ STG.E.64 [R10.64], R14 ; /* 0x0000000e0a007986 */
/* 0x0023e8000c101b04 */
/*0500*/ LDG.E.64 R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1b00 */
/*0510*/ LDG.E.64 R20, [R6.64] ; /* 0x0000000406147981 */
/* 0x000ea2000c1e1b00 */
/*0520*/ IMAD.WIDE R8, R0, 0x8, R16 ; /* 0x0000000800087825 */
/* 0x001fc800078e0210 */
/*0530*/ IMAD.WIDE R4, R0, 0x8, R6 ; /* 0x0000000800047825 */
/* 0x000fe200078e0206 */
/*0540*/ DADD R18, R18, R20 ; /* 0x0000000012127229 */
/* 0x004e0c0000000014 */
/*0550*/ DMUL R18, R18, 0.5 ; /* 0x3fe0000012127828 */
/* 0x001e0e0000000000 */
/*0560*/ STG.E.64 [R6.64], R18 ; /* 0x0000001206007986 */
/* 0x0013e8000c101b04 */
/*0570*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1b00 */
/*0580*/ LDG.E.64 R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea2000c1e1b00 */
/*0590*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*05a0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*05b0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fe20003f06270 */
/*05c0*/ DADD R12, R8, R12 ; /* 0x00000000080c7229 */
/* 0x004e0c000000000c */
/*05d0*/ DMUL R12, R12, 0.5 ; /* 0x3fe000000c0c7828 */
/* 0x001e0e0000000000 */
/*05e0*/ STG.E.64 [R4.64], R12 ; /* 0x0000000c04007986 */
/* 0x0013e2000c101b04 */
/*05f0*/ @!P0 BRA 0x3f0 ; /* 0xfffffdf000008947 */
/* 0x000fea000383ffff */
/*0600*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0610*/ BRA 0x610; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z19cuda_average_kernelIfEvPT_PKS0_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0030*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e680000002200 */
/*0040*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000ea20000002100 */
/*0050*/ IMAD R0, R2, c[0x0][0xc], R5 ; /* 0x0000030002007a24 */
/* 0x001fc800078e0205 */
/*0060*/ IMAD R0, R0, c[0x0][0x4], R7 ; /* 0x0000010000007a24 */
/* 0x002fc800078e0207 */
/*0070*/ IMAD R4, R0, c[0x0][0x0], R9 ; /* 0x0000000000047a24 */
/* 0x004fca00078e0209 */
/*0080*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R0, c[0x0][0x4] ; /* 0x0000010000007a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IADD3 R2, R2, c[0x0][0x10], RZ ; /* 0x0000040002027a10 */
/* 0x000fe20007ffe0ff */
/*00d0*/ BSSY B0, 0x3e0 ; /* 0x0000030000007945 */
/* 0x000fe40003800000 */
/*00e0*/ IMAD R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a24 */
/* 0x000fe400078e02ff */
/*00f0*/ IMAD R2, R2, c[0x0][0xc], R5 ; /* 0x0000030002027a24 */
/* 0x000fe400078e0205 */
/*0100*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fe400078e02ff */
/*0110*/ IMAD R2, R2, c[0x0][0x4], R7 ; /* 0x0000010002027a24 */
/* 0x000fc400078e0207 */
/*0120*/ IMAD R0, R0, c[0x0][0x10], RZ ; /* 0x0000040000007a24 */
/* 0x000fe400078e02ff */
/*0130*/ IMAD R2, R2, c[0x0][0x0], R9 ; /* 0x0000000002027a24 */
/* 0x000fe400078e0209 */
/*0140*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*0150*/ IADD3 R5, RZ, -R0, RZ ; /* 0x80000000ff057210 */
/* 0x000fe40007ffe0ff */
/*0160*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*0170*/ MOV R7, R5 ; /* 0x0000000500077202 */
/* 0x000fe40000000f00 */
/*0180*/ LOP3.LUT R5, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff057212 */
/* 0x000fe200078e33ff */
/*0190*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fc600000001ff */
/*01a0*/ IADD3 R5, R5, c[0x0][0x170], R0 ; /* 0x00005c0005057a10 */
/* 0x000fe20007ffe000 */
/*01b0*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*01c0*/ IADD3 R3, R6, 0xffffffe, RZ ; /* 0x0ffffffe06037810 */
/* 0x001fcc0007ffe0ff */
/*01d0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e24000021f000 */
/*01e0*/ IMAD R7, R7, R3, RZ ; /* 0x0000000307077224 */
/* 0x001fc800078e02ff */
/*01f0*/ IMAD.HI.U32 R2, R3, R7, R2 ; /* 0x0000000703027227 */
/* 0x000fcc00078e0002 */
/*0200*/ IMAD.HI.U32 R2, R2, R5, RZ ; /* 0x0000000502027227 */
/* 0x000fca00078e00ff */
/*0210*/ IADD3 R3, -R2, RZ, RZ ; /* 0x000000ff02037210 */
/* 0x000fca0007ffe1ff */
/*0220*/ IMAD R5, R0, R3, R5 ; /* 0x0000000300057224 */
/* 0x000fca00078e0205 */
/*0230*/ ISETP.GE.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f06070 */
/*0240*/ @P0 IADD3 R5, -R0, R5, RZ ; /* 0x0000000500050210 */
/* 0x000fe40007ffe1ff */
/*0250*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*0260*/ ISETP.GE.U32.AND P1, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f26070 */
/*0270*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*0280*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*0290*/ IADD3 R3, R2.reuse, 0x1, RZ ; /* 0x0000000102037810 */
/* 0x040fe40007ffe0ff */
/*02a0*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*02b0*/ LOP3.LUT P0, R5, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303057812 */
/* 0x000fe4000780c0ff */
/*02c0*/ MOV R3, R4 ; /* 0x0000000400037202 */
/* 0x000fd60000000f00 */
/*02d0*/ @!P0 BRA 0x3d0 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*02e0*/ MOV R6, 0x4 ; /* 0x0000000400067802 */
/* 0x000fe40000000f00 */
/*02f0*/ MOV R2, R5 ; /* 0x0000000500027202 */
/* 0x000fc60000000f00 */
/*0300*/ IMAD.WIDE R4, R3, R6, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc800078e0206 */
/*0310*/ IMAD.WIDE R6, R3, R6, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fc800078e0206 */
/*0320*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x0000a8000c1e1900 */
/*0330*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000ea2000c1e1900 */
/*0340*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*0350*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0360*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0370*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fc800078e0204 */
/*0380*/ FADD R8, R8, R9 ; /* 0x0000000908087221 */
/* 0x004fc80000000000 */
/*0390*/ FMUL R9, R8, 0.5 ; /* 0x3f00000008097820 */
/* 0x000fca0000400000 */
/*03a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e4000c101904 */
/*03b0*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x001fe200078e0206 */
/*03c0*/ @P0 BRA 0x320 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*03d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03e0*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*03f0*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x002fd400000001ff */
/*0400*/ IMAD.WIDE R4, R3, R6, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fc800078e0206 */
/*0410*/ IMAD.WIDE R6, R3, R6, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fe200078e0206 */
/*0420*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea8000c1e1900 */
/*0430*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea2000c1e1900 */
/*0440*/ IMAD.WIDE R10, R0, 0x4, R6 ; /* 0x00000004000a7825 */
/* 0x000fc800078e0206 */
/*0450*/ FADD R2, R2, R9 ; /* 0x0000000902027221 */
/* 0x004fe40000000000 */
/*0460*/ IMAD.WIDE R8, R0, 0x4, R4 ; /* 0x0000000400087825 */
/* 0x000fc800078e0204 */
/*0470*/ FMUL R15, R2, 0.5 ; /* 0x3f000000020f7820 */
/* 0x000fca0000400000 */
/*0480*/ STG.E [R4.64], R15 ; /* 0x0000000f04007986 */
/* 0x0001e8000c101904 */
/*0490*/ LDG.E R2, [R10.64] ; /* 0x000000040a027981 */
/* 0x000ea8000c1e1900 */
/*04a0*/ LDG.E R13, [R8.64] ; /* 0x00000004080d7981 */
/* 0x000ea2000c1e1900 */
/*04b0*/ IMAD.WIDE R6, R0, 0x4, R8 ; /* 0x0000000400067825 */
/* 0x000fc800078e0208 */
/*04c0*/ FADD R2, R2, R13 ; /* 0x0000000d02027221 */
/* 0x004fe40000000000 */
/*04d0*/ IMAD.WIDE R12, R0, 0x4, R10 ; /* 0x00000004000c7825 */
/* 0x000fc800078e020a */
/*04e0*/ FMUL R17, R2, 0.5 ; /* 0x3f00000002117820 */
/* 0x000fca0000400000 */
/*04f0*/ STG.E [R8.64], R17 ; /* 0x0000001108007986 */
/* 0x0003e8000c101904 */
/*0500*/ LDG.E R2, [R12.64] ; /* 0x000000040c027981 */
/* 0x000ea8000c1e1900 */
/*0510*/ LDG.E R19, [R6.64] ; /* 0x0000000406137981 */
/* 0x000ea2000c1e1900 */
/*0520*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */
/* 0x000fc800078e020c */
/*0530*/ IMAD.WIDE R4, R0, 0x4, R6 ; /* 0x0000000400047825 */
/* 0x001fc800078e0206 */
/*0540*/ FADD R2, R2, R19 ; /* 0x0000001302027221 */
/* 0x004fc80000000000 */
/*0550*/ FMUL R15, R2, 0.5 ; /* 0x3f000000020f7820 */
/* 0x000fca0000400000 */
/*0560*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x0003e8000c101904 */
/*0570*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea8000c1e1900 */
/*0580*/ LDG.E R19, [R4.64] ; /* 0x0000000404137981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*05a0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*05b0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fe20003f06270 */
/*05c0*/ FADD R19, R10, R19 ; /* 0x000000130a137221 */
/* 0x004fc80000000000 */
/*05d0*/ FMUL R19, R19, 0.5 ; /* 0x3f00000013137820 */
/* 0x000fca0000400000 */
/*05e0*/ STG.E [R4.64], R19 ; /* 0x0000001304007986 */
/* 0x0003e6000c101904 */
/*05f0*/ @!P0 BRA 0x3f0 ; /* 0xfffffdf000008947 */
/* 0x000fea000383ffff */
/*0600*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0610*/ BRA 0x610; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL19cuda_average_kernelIfEvPT_PKS0_i,"axG",@progbits,_ZL19cuda_average_kernelIfEvPT_PKS0_i,comdat
.globl _ZL19cuda_average_kernelIfEvPT_PKS0_i
.p2align 8
.type _ZL19cuda_average_kernelIfEvPT_PKS0_i,@function
_ZL19cuda_average_kernelIfEvPT_PKS0_i:
s_clause 0x2
s_load_b32 s8, s[0:1], 0x18
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s5, s8, s15
s_lshr_b32 s9, s4, 16
s_add_i32 s5, s5, s14
s_and_b32 s11, s4, 0xffff
v_mad_u64_u32 v[2:3], null, s5, s9, v[1:2]
v_and_b32_e32 v3, 0x3ff, v0
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v2, s11, v[3:4]
v_cmpx_gt_i32_e64 s10, v0
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x4
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_mul_i32 s0, s9, s11
s_mov_b32 s1, 0
s_mul_i32 s0, s0, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s0, s2
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v3, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, s8
global_load_b32 v7, v[3:4], off
global_load_b32 v5, v[5:6], off
v_add_nc_u32_e32 v0, s2, v0
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v5, v7, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_i32_e64 s0, s10, v0
v_mul_f32_e32 v5, 0.5, v5
s_delay_alu instid0(VALU_DEP_2)
s_or_b32 s1, s0, s1
global_store_b32 v[3:4], v5, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL19cuda_average_kernelIfEvPT_PKS0_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL19cuda_average_kernelIfEvPT_PKS0_i,"axG",@progbits,_ZL19cuda_average_kernelIfEvPT_PKS0_i,comdat
.Lfunc_end0:
.size _ZL19cuda_average_kernelIfEvPT_PKS0_i, .Lfunc_end0-_ZL19cuda_average_kernelIfEvPT_PKS0_i
.section .AMDGPU.csdata,"",@progbits
.section .text._ZL19cuda_average_kernelIdEvPT_PKS0_i,"axG",@progbits,_ZL19cuda_average_kernelIdEvPT_PKS0_i,comdat
.globl _ZL19cuda_average_kernelIdEvPT_PKS0_i
.p2align 8
.type _ZL19cuda_average_kernelIdEvPT_PKS0_i,@function
_ZL19cuda_average_kernelIdEvPT_PKS0_i:
s_clause 0x2
s_load_b32 s8, s[0:1], 0x18
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s5, s8, s15
s_lshr_b32 s9, s4, 16
s_add_i32 s5, s5, s14
s_and_b32 s11, s4, 0xffff
v_mad_u64_u32 v[2:3], null, s5, s9, v[1:2]
v_and_b32_e32 v3, 0x3ff, v0
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v2, s11, v[3:4]
v_cmpx_gt_i32_e64 s10, v0
s_cbranch_execz .LBB1_3
s_load_b32 s2, s[2:3], 0x4
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_mul_i32 s0, s9, s11
s_mov_b32 s1, 0
s_mul_i32 s0, s0, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[1:2], 3, v[0:1]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s0, s2
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 3
.p2align 6
.LBB1_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v3, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
v_add_nc_u32_e32 v0, s2, v0
global_load_b64 v[7:8], v[3:4], off
global_load_b64 v[5:6], v[5:6], off
v_add_co_u32 v1, s0, v1, s8
v_cmp_le_i32_e32 vcc_lo, s10, v0
v_add_co_ci_u32_e64 v2, s0, s9, v2, s0
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_add_f64 v[5:6], v[7:8], v[5:6]
s_delay_alu instid0(VALU_DEP_1)
v_mul_f64 v[5:6], v[5:6], 0.5
global_store_b64 v[3:4], v[5:6], off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL19cuda_average_kernelIdEvPT_PKS0_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL19cuda_average_kernelIdEvPT_PKS0_i,"axG",@progbits,_ZL19cuda_average_kernelIdEvPT_PKS0_i,comdat
.Lfunc_end1:
.size _ZL19cuda_average_kernelIdEvPT_PKS0_i, .Lfunc_end1-_ZL19cuda_average_kernelIdEvPT_PKS0_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL19cuda_average_kernelIfEvPT_PKS0_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL19cuda_average_kernelIfEvPT_PKS0_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL19cuda_average_kernelIdEvPT_PKS0_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL19cuda_average_kernelIdEvPT_PKS0_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00043f67_00000000-6_cu-nnet-mpi-sync.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL50__device_stub__Z19cuda_average_kernelIfEvPT_PKS0_iPfPKfi, @function
_ZL50__device_stub__Z19cuda_average_kernelIfEvPT_PKS0_iPfPKfi:
.LFB2088:
.cfi_startproc
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19cuda_average_kernelIfEvPT_PKS0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _ZL50__device_stub__Z19cuda_average_kernelIfEvPT_PKS0_iPfPKfi, .-_ZL50__device_stub__Z19cuda_average_kernelIfEvPT_PKS0_iPfPKfi
.type _Z19cuda_average_kernelIfEvPT_PKS0_i, @function
_Z19cuda_average_kernelIfEvPT_PKS0_i:
.LFB2141:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL50__device_stub__Z19cuda_average_kernelIfEvPT_PKS0_iPfPKfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2141:
.size _Z19cuda_average_kernelIfEvPT_PKS0_i, .-_Z19cuda_average_kernelIfEvPT_PKS0_i
.type _ZL50__device_stub__Z19cuda_average_kernelIdEvPT_PKS0_iPdPKdi, @function
_ZL50__device_stub__Z19cuda_average_kernelIdEvPT_PKS0_iPdPKdi:
.LFB2090:
.cfi_startproc
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19cuda_average_kernelIdEvPT_PKS0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _ZL50__device_stub__Z19cuda_average_kernelIdEvPT_PKS0_iPdPKdi, .-_ZL50__device_stub__Z19cuda_average_kernelIdEvPT_PKS0_iPdPKdi
.type _Z19cuda_average_kernelIdEvPT_PKS0_i, @function
_Z19cuda_average_kernelIdEvPT_PKS0_i:
.LFB2143:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL50__device_stub__Z19cuda_average_kernelIdEvPT_PKS0_iPdPKdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2143:
.size _Z19cuda_average_kernelIdEvPT_PKS0_i, .-_Z19cuda_average_kernelIdEvPT_PKS0_i
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12cuda_averagePfPKfiRP11CUstream_st
.type _Z12cuda_averagePfPKfiRP11CUstream_st, @function
_Z12cuda_averagePfPKfiRP11CUstream_st:
.LFB2062:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movq %rsi, %r12
movl %edx, %ebx
movl $512, 8(%rsp)
movl $1, 12(%rsp)
leal 1022(%rdx), %eax
addl $511, %edx
cmovns %edx, %eax
sarl $9, %eax
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movq (%rcx), %r9
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L19:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movl %ebx, %edx
movq %r12, %rsi
movq %rbp, %rdi
call _ZL50__device_stub__Z19cuda_average_kernelIfEvPT_PKS0_iPfPKfi
jmp .L19
.cfi_endproc
.LFE2062:
.size _Z12cuda_averagePfPKfiRP11CUstream_st, .-_Z12cuda_averagePfPKfiRP11CUstream_st
.globl _Z12cuda_averagePdPKdiRP11CUstream_st
.type _Z12cuda_averagePdPKdiRP11CUstream_st, @function
_Z12cuda_averagePdPKdiRP11CUstream_st:
.LFB2063:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movq %rsi, %r12
movl %edx, %ebx
movl $512, 8(%rsp)
movl $1, 12(%rsp)
leal 1022(%rdx), %eax
addl $511, %edx
cmovns %edx, %eax
sarl $9, %eax
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movq (%rcx), %r9
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L23:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movl %ebx, %edx
movq %r12, %rsi
movq %rbp, %rdi
call _ZL50__device_stub__Z19cuda_average_kernelIdEvPT_PKS0_iPdPKdi
jmp .L23
.cfi_endproc
.LFE2063:
.size _Z12cuda_averagePdPKdiRP11CUstream_st, .-_Z12cuda_averagePdPKdiRP11CUstream_st
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19cuda_average_kernelIdEvPT_PKS0_i"
.align 8
.LC1:
.string "_Z19cuda_average_kernelIfEvPT_PKS0_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2093:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19cuda_average_kernelIdEvPT_PKS0_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z19cuda_average_kernelIfEvPT_PKS0_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cu-nnet-mpi-sync.hip"
.globl _Z12cuda_averagePfPKfiRP12ihipStream_t # -- Begin function _Z12cuda_averagePfPKfiRP12ihipStream_t
.p2align 4, 0x90
.type _Z12cuda_averagePfPKfiRP12ihipStream_t,@function
_Z12cuda_averagePfPKfiRP12ihipStream_t: # @_Z12cuda_averagePfPKfiRP12ihipStream_t
.cfi_startproc
# %bb.0:
jmp _Z17cuda_average_implIfEvPT_PKS0_iRP12ihipStream_t # TAILCALL
.Lfunc_end0:
.size _Z12cuda_averagePfPKfiRP12ihipStream_t, .Lfunc_end0-_Z12cuda_averagePfPKfiRP12ihipStream_t
.cfi_endproc
# -- End function
.section .text._Z17cuda_average_implIfEvPT_PKS0_iRP12ihipStream_t,"axG",@progbits,_Z17cuda_average_implIfEvPT_PKS0_iRP12ihipStream_t,comdat
.weak _Z17cuda_average_implIfEvPT_PKS0_iRP12ihipStream_t # -- Begin function _Z17cuda_average_implIfEvPT_PKS0_iRP12ihipStream_t
.p2align 4, 0x90
.type _Z17cuda_average_implIfEvPT_PKS0_iRP12ihipStream_t,@function
_Z17cuda_average_implIfEvPT_PKS0_iRP12ihipStream_t: # @_Z17cuda_average_implIfEvPT_PKS0_iRP12ihipStream_t
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %edx, %ebx
movq %rsi, %r14
movq %rdi, %r15
leal 511(%rbx), %eax
leal 1022(%rbx), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
movq (%rcx), %r9
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movl %ebx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL19cuda_average_kernelIfEvPT_PKS0_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z17cuda_average_implIfEvPT_PKS0_iRP12ihipStream_t, .Lfunc_end1-_Z17cuda_average_implIfEvPT_PKS0_iRP12ihipStream_t
.cfi_endproc
# -- End function
.text
.globl _Z12cuda_averagePdPKdiRP12ihipStream_t # -- Begin function _Z12cuda_averagePdPKdiRP12ihipStream_t
.p2align 4, 0x90
.type _Z12cuda_averagePdPKdiRP12ihipStream_t,@function
_Z12cuda_averagePdPKdiRP12ihipStream_t: # @_Z12cuda_averagePdPKdiRP12ihipStream_t
.cfi_startproc
# %bb.0:
jmp _Z17cuda_average_implIdEvPT_PKS0_iRP12ihipStream_t # TAILCALL
.Lfunc_end2:
.size _Z12cuda_averagePdPKdiRP12ihipStream_t, .Lfunc_end2-_Z12cuda_averagePdPKdiRP12ihipStream_t
.cfi_endproc
# -- End function
.section .text._Z17cuda_average_implIdEvPT_PKS0_iRP12ihipStream_t,"axG",@progbits,_Z17cuda_average_implIdEvPT_PKS0_iRP12ihipStream_t,comdat
.weak _Z17cuda_average_implIdEvPT_PKS0_iRP12ihipStream_t # -- Begin function _Z17cuda_average_implIdEvPT_PKS0_iRP12ihipStream_t
.p2align 4, 0x90
.type _Z17cuda_average_implIdEvPT_PKS0_iRP12ihipStream_t,@function
_Z17cuda_average_implIdEvPT_PKS0_iRP12ihipStream_t: # @_Z17cuda_average_implIdEvPT_PKS0_iRP12ihipStream_t
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %edx, %ebx
movq %rsi, %r14
movq %rdi, %r15
leal 511(%rbx), %eax
leal 1022(%rbx), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
movq (%rcx), %r9
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movl %ebx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL19cuda_average_kernelIdEvPT_PKS0_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z17cuda_average_implIdEvPT_PKS0_iRP12ihipStream_t, .Lfunc_end3-_Z17cuda_average_implIdEvPT_PKS0_iRP12ihipStream_t
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function _ZL34__device_stub__cuda_average_kernelIfEvPT_PKS0_i
.type _ZL34__device_stub__cuda_average_kernelIfEvPT_PKS0_i,@function
_ZL34__device_stub__cuda_average_kernelIfEvPT_PKS0_i: # @_ZL34__device_stub__cuda_average_kernelIfEvPT_PKS0_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL19cuda_average_kernelIfEvPT_PKS0_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size _ZL34__device_stub__cuda_average_kernelIfEvPT_PKS0_i, .Lfunc_end4-_ZL34__device_stub__cuda_average_kernelIfEvPT_PKS0_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL34__device_stub__cuda_average_kernelIdEvPT_PKS0_i
.type _ZL34__device_stub__cuda_average_kernelIdEvPT_PKS0_i,@function
_ZL34__device_stub__cuda_average_kernelIdEvPT_PKS0_i: # @_ZL34__device_stub__cuda_average_kernelIdEvPT_PKS0_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL19cuda_average_kernelIdEvPT_PKS0_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end5:
.size _ZL34__device_stub__cuda_average_kernelIdEvPT_PKS0_i, .Lfunc_end5-_ZL34__device_stub__cuda_average_kernelIdEvPT_PKS0_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL19cuda_average_kernelIfEvPT_PKS0_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL19cuda_average_kernelIdEvPT_PKS0_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _ZL19cuda_average_kernelIfEvPT_PKS0_i,@object # @_ZL19cuda_average_kernelIfEvPT_PKS0_i
.section .rodata,"a",@progbits
.p2align 3, 0x0
_ZL19cuda_average_kernelIfEvPT_PKS0_i:
.quad _ZL34__device_stub__cuda_average_kernelIfEvPT_PKS0_i
.size _ZL19cuda_average_kernelIfEvPT_PKS0_i, 8
.type _ZL19cuda_average_kernelIdEvPT_PKS0_i,@object # @_ZL19cuda_average_kernelIdEvPT_PKS0_i
.p2align 3, 0x0
_ZL19cuda_average_kernelIdEvPT_PKS0_i:
.quad _ZL34__device_stub__cuda_average_kernelIdEvPT_PKS0_i
.size _ZL19cuda_average_kernelIdEvPT_PKS0_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_ZL19cuda_average_kernelIfEvPT_PKS0_i"
.size .L__unnamed_1, 38
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_ZL19cuda_average_kernelIdEvPT_PKS0_i"
.size .L__unnamed_2, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZL34__device_stub__cuda_average_kernelIfEvPT_PKS0_i
.addrsig_sym _ZL34__device_stub__cuda_average_kernelIdEvPT_PKS0_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZL19cuda_average_kernelIfEvPT_PKS0_i
.addrsig_sym _ZL19cuda_average_kernelIdEvPT_PKS0_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <cuda_runtime.h>
#include <cufft.h>
#include "device_launch_parameters.h"
#include <complex>
#include <device_functions.h>
#include <cuComplex.h>
#include <chrono>
#include <iostream>
#pragma comment(lib,"cufft.lib")
using namespace std;
__global__
void Complex_mult(cufftComplex * c, const cufftComplex * a, const cufftComplex * b) {
int i = threadIdx.x + blockIdx.x * blockDim.x;
c[i].x = (a[i].x * b[i].x - a[i].y * (-b[i].y));
c[i].y = (a[i].x * (-b[i].y) + a[i].y * b[i].x);
}
std::chrono::time_point<std::chrono::high_resolution_clock> now()
{
return std::chrono::high_resolution_clock::now();
}
template <typename T>
double milliseconds(T t)
{
return (double) std::chrono::duration_cast<std::chrono::nanoseconds>(t).count() / 1000000;
}
extern "C"
cufftComplex* FFT_GPU(cufftComplex* signal1, cufftComplex* signal2, int len_c)
{
cufftComplex* GPU_data_first;
cufftComplex* GPU_data_second;
auto t1 = now();
cudaMalloc((void**)&GPU_data_first, len_c * sizeof(cufftComplex));
cudaMalloc((void**)&GPU_data_second, len_c * sizeof(cufftComplex));
cufftHandle plan1;
cufftPlan1d(&plan1, len_c, CUFFT_C2C, 1);
auto t2 = now();
cout<<"VIDEO MEM: "<< milliseconds(t2-t1)<<" ms"<<endl;
cudaMemcpy(GPU_data_first, signal1, len_c * sizeof(cufftComplex), cudaMemcpyHostToDevice);
cudaMemcpy(GPU_data_second, signal2, len_c * sizeof(cufftComplex), cudaMemcpyHostToDevice);
auto t3 = now();
cout<<"COPY DATA: "<< milliseconds(t3-t2)<<" ms"<<endl;
auto t3_1 = now();
//cudaDeviceSynchronize();
cufftExecC2C(plan1, (cufftComplex*)GPU_data_first, (cufftComplex*)GPU_data_first, CUFFT_FORWARD);
cufftExecC2C(plan1, (cufftComplex*)GPU_data_second, (cufftComplex*)GPU_data_second, CUFFT_FORWARD);
auto t4 = now();
cout<<"FFT: "<< milliseconds(t4-t3_1)<<" ms"<<endl;
//cufftDestroy(plan1); // освобождение памяти
cufftComplex* Mult_result;
cudaMalloc((void**)&Mult_result, len_c * sizeof(cufftComplex));
auto t6 = now();
Complex_mult <<<256, 192>>>(Mult_result, GPU_data_first, GPU_data_second);
auto t7 = now();
cout<<"cMULT: "<< milliseconds(t7-t6)<<" ms"<<endl;
cudaFree(GPU_data_first);
cudaFree(GPU_data_second);
cufftHandle plan3;
auto t8 = now();
// cufftPlan1d(&plan3, len_c, CUFFT_C2C, 1);
cufftExecC2C(plan1, (cufftComplex*)Mult_result, (cufftComplex*)Mult_result, CUFFT_INVERSE);
auto t9 = now();
cout<<"IFFT: "<< milliseconds(t9-t8)<<" ms"<<endl;
cufftComplex* result_of_IFFT = new cufftComplex[len_c];
auto t10 = now();
cudaMemcpy(result_of_IFFT, Mult_result, sizeof(cufftComplex) * (len_c), cudaMemcpyDeviceToHost);
auto t11 = now();
cout<<"COPY FROM VIDEO: "<< milliseconds(t11-t10)<<" ms"<<endl;
cudaFree(Mult_result);
return result_of_IFFT;
} | code for sm_80
Function : _Z12Complex_multP6float2PKS_S2_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x0c0fe200078e0207 */
/*0080*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea8000c1e1b00 */
/*0090*/ LDG.E.64 R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ FMUL R13, R9, R11 ; /* 0x0000000b090d7220 */
/* 0x004fc80000400000 */
/*00c0*/ FFMA R13, R8, R10, R13 ; /* 0x0000000a080d7223 */
/* 0x000fca000000000d */
/*00d0*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x000fe8000c101904 */
/*00e0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ee2000c1e1900 */
/*0100*/ FMUL R0, R11, R0 ; /* 0x000000000b007220 */
/* 0x004fc80000400000 */
/*0110*/ FFMA R9, R9, R8, -R0 ; /* 0x0000000809097223 */
/* 0x008fca0000000800 */
/*0120*/ STG.E [R6.64+0x4], R9 ; /* 0x0000040906007986 */
/* 0x000fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cuda_runtime.h>
#include <cufft.h>
#include "device_launch_parameters.h"
#include <complex>
#include <device_functions.h>
#include <cuComplex.h>
#include <chrono>
#include <iostream>
#pragma comment(lib,"cufft.lib")
using namespace std;
__global__
void Complex_mult(cufftComplex * c, const cufftComplex * a, const cufftComplex * b) {
int i = threadIdx.x + blockIdx.x * blockDim.x;
c[i].x = (a[i].x * b[i].x - a[i].y * (-b[i].y));
c[i].y = (a[i].x * (-b[i].y) + a[i].y * b[i].x);
}
std::chrono::time_point<std::chrono::high_resolution_clock> now()
{
return std::chrono::high_resolution_clock::now();
}
template <typename T>
double milliseconds(T t)
{
return (double) std::chrono::duration_cast<std::chrono::nanoseconds>(t).count() / 1000000;
}
extern "C"
cufftComplex* FFT_GPU(cufftComplex* signal1, cufftComplex* signal2, int len_c)
{
cufftComplex* GPU_data_first;
cufftComplex* GPU_data_second;
auto t1 = now();
cudaMalloc((void**)&GPU_data_first, len_c * sizeof(cufftComplex));
cudaMalloc((void**)&GPU_data_second, len_c * sizeof(cufftComplex));
cufftHandle plan1;
cufftPlan1d(&plan1, len_c, CUFFT_C2C, 1);
auto t2 = now();
cout<<"VIDEO MEM: "<< milliseconds(t2-t1)<<" ms"<<endl;
cudaMemcpy(GPU_data_first, signal1, len_c * sizeof(cufftComplex), cudaMemcpyHostToDevice);
cudaMemcpy(GPU_data_second, signal2, len_c * sizeof(cufftComplex), cudaMemcpyHostToDevice);
auto t3 = now();
cout<<"COPY DATA: "<< milliseconds(t3-t2)<<" ms"<<endl;
auto t3_1 = now();
//cudaDeviceSynchronize();
cufftExecC2C(plan1, (cufftComplex*)GPU_data_first, (cufftComplex*)GPU_data_first, CUFFT_FORWARD);
cufftExecC2C(plan1, (cufftComplex*)GPU_data_second, (cufftComplex*)GPU_data_second, CUFFT_FORWARD);
auto t4 = now();
cout<<"FFT: "<< milliseconds(t4-t3_1)<<" ms"<<endl;
//cufftDestroy(plan1); // освобождение памяти
cufftComplex* Mult_result;
cudaMalloc((void**)&Mult_result, len_c * sizeof(cufftComplex));
auto t6 = now();
Complex_mult <<<256, 192>>>(Mult_result, GPU_data_first, GPU_data_second);
auto t7 = now();
cout<<"cMULT: "<< milliseconds(t7-t6)<<" ms"<<endl;
cudaFree(GPU_data_first);
cudaFree(GPU_data_second);
cufftHandle plan3;
auto t8 = now();
// cufftPlan1d(&plan3, len_c, CUFFT_C2C, 1);
cufftExecC2C(plan1, (cufftComplex*)Mult_result, (cufftComplex*)Mult_result, CUFFT_INVERSE);
auto t9 = now();
cout<<"IFFT: "<< milliseconds(t9-t8)<<" ms"<<endl;
cufftComplex* result_of_IFFT = new cufftComplex[len_c];
auto t10 = now();
cudaMemcpy(result_of_IFFT, Mult_result, sizeof(cufftComplex) * (len_c), cudaMemcpyDeviceToHost);
auto t11 = now();
cout<<"COPY FROM VIDEO: "<< milliseconds(t11-t10)<<" ms"<<endl;
cudaFree(Mult_result);
return result_of_IFFT;
} | .file "tmpxft_000bcaa7_00000000-6_vectorAdd.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4099:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3nowv
.type _Z3nowv, @function
_Z3nowv:
.LFB4092:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4092:
.size _Z3nowv, .-_Z3nowv
.globl _Z45__device_stub__Z12Complex_multP6float2PKS_S2_P6float2PKS_S2_
.type _Z45__device_stub__Z12Complex_multP6float2PKS_S2_P6float2PKS_S2_, @function
_Z45__device_stub__Z12Complex_multP6float2PKS_S2_P6float2PKS_S2_:
.LFB4121:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12Complex_multP6float2PKS_S2_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4121:
.size _Z45__device_stub__Z12Complex_multP6float2PKS_S2_P6float2PKS_S2_, .-_Z45__device_stub__Z12Complex_multP6float2PKS_S2_P6float2PKS_S2_
.globl _Z12Complex_multP6float2PKS_S2_
.type _Z12Complex_multP6float2PKS_S2_, @function
_Z12Complex_multP6float2PKS_S2_:
.LFB4122:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z12Complex_multP6float2PKS_S2_P6float2PKS_S2_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4122:
.size _Z12Complex_multP6float2PKS_S2_, .-_Z12Complex_multP6float2PKS_S2_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "VIDEO MEM: "
.LC2:
.string " ms"
.LC3:
.string "COPY DATA: "
.LC4:
.string "FFT: "
.LC5:
.string "cMULT: "
.LC6:
.string "IFFT: "
.LC7:
.string "COPY FROM VIDEO: "
.text
.globl FFT_GPU
.type FFT_GPU, @function
FFT_GPU:
.LFB4094:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %r14
movq %rsi, 8(%rsp)
movl %edx, %r12d
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbp
movslq %r12d, %r15
leaq 0(,%r15,8), %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 20(%rsp), %rdi
movl $1, %ecx
movl $41, %edx
movl %r12d, %esi
call cufftPlan1d@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r12
movl $11, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %r12, %rax
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC1(%rip), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r13
testq %r13, %r13
je .L44
cmpb $0, 56(%r13)
je .L16
movzbl 67(%r13), %esi
.L17:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbp
movl $11, %edx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
subq %r12, %rbp
pxor %xmm0, %xmm0
cvtsi2sdq %rbp, %xmm0
divsd .LC1(%rip), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L45
cmpb $0, 56(%r12)
je .L20
movzbl 67(%r12), %esi
.L21:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r12
movq 24(%rsp), %rsi
movl $-1, %ecx
movq %rsi, %rdx
movl 20(%rsp), %edi
call cufftExecC2C@PLT
movq 32(%rsp), %rsi
movl $-1, %ecx
movq %rsi, %rdx
movl 20(%rsp), %edi
call cufftExecC2C@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbp
movl $5, %edx
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
subq %r12, %rbp
pxor %xmm0, %xmm0
cvtsi2sdq %rbp, %xmm0
divsd .LC1(%rip), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L46
cmpb $0, 56(%r12)
je .L24
movzbl 67(%r12), %esi
.L25:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r12
movl $192, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $256, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L47
.L26:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbp
movl $7, %edx
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
subq %r12, %rbp
pxor %xmm0, %xmm0
cvtsi2sdq %rbp, %xmm0
divsd .LC1(%rip), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L48
cmpb $0, 56(%r12)
je .L29
movzbl 67(%r12), %esi
.L30:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r12
movq 40(%rsp), %rsi
movl $1, %ecx
movq %rsi, %rdx
movl 20(%rsp), %edi
call cufftExecC2C@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbp
movl $6, %edx
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
subq %r12, %rbp
pxor %xmm0, %xmm0
cvtsi2sdq %rbp, %xmm0
divsd .LC1(%rip), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L49
cmpb $0, 56(%r12)
je .L33
movzbl 67(%r12), %esi
.L34:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
shrq $60, %r15
jne .L35
movq %rbx, %rdi
call _Znam@PLT
movq %rax, %rbp
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r12
movl $2, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movl $17, %edx
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
subq %r12, %rbx
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
divsd .LC1(%rip), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $3, %edx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L50
cmpb $0, 56(%r12)
je .L38
movzbl 67(%r12), %esi
.L39:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L51
movq %rbp, %rax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L52
call _ZSt16__throw_bad_castv@PLT
.L52:
call __stack_chk_fail@PLT
.L16:
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L17
.L45:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L53
call _ZSt16__throw_bad_castv@PLT
.L53:
call __stack_chk_fail@PLT
.L20:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L21
.L46:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L54
call _ZSt16__throw_bad_castv@PLT
.L54:
call __stack_chk_fail@PLT
.L24:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L25
.L47:
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z45__device_stub__Z12Complex_multP6float2PKS_S2_P6float2PKS_S2_
jmp .L26
.L48:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L55
call _ZSt16__throw_bad_castv@PLT
.L55:
call __stack_chk_fail@PLT
.L29:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L30
.L49:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L56
call _ZSt16__throw_bad_castv@PLT
.L56:
call __stack_chk_fail@PLT
.L33:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L34
.L50:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L57
call _ZSt16__throw_bad_castv@PLT
.L57:
call __stack_chk_fail@PLT
.L38:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L39
.L35:
movq 72(%rsp), %rax
subq %fs:40, %rax
je .L40
call __stack_chk_fail@PLT
.L40:
call __cxa_throw_bad_array_new_length@PLT
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4094:
.size FFT_GPU, .-FFT_GPU
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "_Z12Complex_multP6float2PKS_S2_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4124:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z12Complex_multP6float2PKS_S2_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4124:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cuda_runtime.h>
#include <cufft.h>
#include "device_launch_parameters.h"
#include <complex>
#include <device_functions.h>
#include <cuComplex.h>
#include <chrono>
#include <iostream>
#pragma comment(lib,"cufft.lib")
using namespace std;
__global__
void Complex_mult(cufftComplex * c, const cufftComplex * a, const cufftComplex * b) {
int i = threadIdx.x + blockIdx.x * blockDim.x;
c[i].x = (a[i].x * b[i].x - a[i].y * (-b[i].y));
c[i].y = (a[i].x * (-b[i].y) + a[i].y * b[i].x);
}
std::chrono::time_point<std::chrono::high_resolution_clock> now()
{
return std::chrono::high_resolution_clock::now();
}
template <typename T>
double milliseconds(T t)
{
return (double) std::chrono::duration_cast<std::chrono::nanoseconds>(t).count() / 1000000;
}
extern "C"
cufftComplex* FFT_GPU(cufftComplex* signal1, cufftComplex* signal2, int len_c)
{
cufftComplex* GPU_data_first;
cufftComplex* GPU_data_second;
auto t1 = now();
cudaMalloc((void**)&GPU_data_first, len_c * sizeof(cufftComplex));
cudaMalloc((void**)&GPU_data_second, len_c * sizeof(cufftComplex));
cufftHandle plan1;
cufftPlan1d(&plan1, len_c, CUFFT_C2C, 1);
auto t2 = now();
cout<<"VIDEO MEM: "<< milliseconds(t2-t1)<<" ms"<<endl;
cudaMemcpy(GPU_data_first, signal1, len_c * sizeof(cufftComplex), cudaMemcpyHostToDevice);
cudaMemcpy(GPU_data_second, signal2, len_c * sizeof(cufftComplex), cudaMemcpyHostToDevice);
auto t3 = now();
cout<<"COPY DATA: "<< milliseconds(t3-t2)<<" ms"<<endl;
auto t3_1 = now();
//cudaDeviceSynchronize();
cufftExecC2C(plan1, (cufftComplex*)GPU_data_first, (cufftComplex*)GPU_data_first, CUFFT_FORWARD);
cufftExecC2C(plan1, (cufftComplex*)GPU_data_second, (cufftComplex*)GPU_data_second, CUFFT_FORWARD);
auto t4 = now();
cout<<"FFT: "<< milliseconds(t4-t3_1)<<" ms"<<endl;
//cufftDestroy(plan1); // освобождение памяти
cufftComplex* Mult_result;
cudaMalloc((void**)&Mult_result, len_c * sizeof(cufftComplex));
auto t6 = now();
Complex_mult <<<256, 192>>>(Mult_result, GPU_data_first, GPU_data_second);
auto t7 = now();
cout<<"cMULT: "<< milliseconds(t7-t6)<<" ms"<<endl;
cudaFree(GPU_data_first);
cudaFree(GPU_data_second);
cufftHandle plan3;
auto t8 = now();
// cufftPlan1d(&plan3, len_c, CUFFT_C2C, 1);
cufftExecC2C(plan1, (cufftComplex*)Mult_result, (cufftComplex*)Mult_result, CUFFT_INVERSE);
auto t9 = now();
cout<<"IFFT: "<< milliseconds(t9-t8)<<" ms"<<endl;
cufftComplex* result_of_IFFT = new cufftComplex[len_c];
auto t10 = now();
cudaMemcpy(result_of_IFFT, Mult_result, sizeof(cufftComplex) * (len_c), cudaMemcpyDeviceToHost);
auto t11 = now();
cout<<"COPY FROM VIDEO: "<< milliseconds(t11-t10)<<" ms"<<endl;
cudaFree(Mult_result);
return result_of_IFFT;
} | #include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
#include <complex>
#include <hip/device_functions.h>
#include <hip/hip_complex.h>
#include <chrono>
#include <iostream>
#pragma comment(lib,"cufft.lib")
using namespace std;
__global__
void Complex_mult(hipfftComplex * c, const hipfftComplex * a, const hipfftComplex * b) {
int i = threadIdx.x + blockIdx.x * blockDim.x;
c[i].x = (a[i].x * b[i].x - a[i].y * (-b[i].y));
c[i].y = (a[i].x * (-b[i].y) + a[i].y * b[i].x);
}
std::chrono::time_point<std::chrono::high_resolution_clock> now()
{
return std::chrono::high_resolution_clock::now();
}
template <typename T>
double milliseconds(T t)
{
return (double) std::chrono::duration_cast<std::chrono::nanoseconds>(t).count() / 1000000;
}
extern "C"
hipfftComplex* FFT_GPU(hipfftComplex* signal1, hipfftComplex* signal2, int len_c)
{
hipfftComplex* GPU_data_first;
hipfftComplex* GPU_data_second;
auto t1 = now();
hipMalloc((void**)&GPU_data_first, len_c * sizeof(hipfftComplex));
hipMalloc((void**)&GPU_data_second, len_c * sizeof(hipfftComplex));
hipfftHandle plan1;
hipfftPlan1d(&plan1, len_c, HIPFFT_C2C, 1);
auto t2 = now();
cout<<"VIDEO MEM: "<< milliseconds(t2-t1)<<" ms"<<endl;
hipMemcpy(GPU_data_first, signal1, len_c * sizeof(hipfftComplex), hipMemcpyHostToDevice);
hipMemcpy(GPU_data_second, signal2, len_c * sizeof(hipfftComplex), hipMemcpyHostToDevice);
auto t3 = now();
cout<<"COPY DATA: "<< milliseconds(t3-t2)<<" ms"<<endl;
auto t3_1 = now();
//cudaDeviceSynchronize();
hipfftExecC2C(plan1, (hipfftComplex*)GPU_data_first, (hipfftComplex*)GPU_data_first, HIPFFT_FORWARD);
hipfftExecC2C(plan1, (hipfftComplex*)GPU_data_second, (hipfftComplex*)GPU_data_second, HIPFFT_FORWARD);
auto t4 = now();
cout<<"FFT: "<< milliseconds(t4-t3_1)<<" ms"<<endl;
//cufftDestroy(plan1); // освобождение памяти
hipfftComplex* Mult_result;
hipMalloc((void**)&Mult_result, len_c * sizeof(hipfftComplex));
auto t6 = now();
Complex_mult <<<256, 192>>>(Mult_result, GPU_data_first, GPU_data_second);
auto t7 = now();
cout<<"cMULT: "<< milliseconds(t7-t6)<<" ms"<<endl;
hipFree(GPU_data_first);
hipFree(GPU_data_second);
hipfftHandle plan3;
auto t8 = now();
// cufftPlan1d(&plan3, len_c, CUFFT_C2C, 1);
hipfftExecC2C(plan1, (hipfftComplex*)Mult_result, (hipfftComplex*)Mult_result, HIPFFT_BACKWARD);
auto t9 = now();
cout<<"IFFT: "<< milliseconds(t9-t8)<<" ms"<<endl;
hipfftComplex* result_of_IFFT = new hipfftComplex[len_c];
auto t10 = now();
hipMemcpy(result_of_IFFT, Mult_result, sizeof(hipfftComplex) * (len_c), hipMemcpyDeviceToHost);
auto t11 = now();
cout<<"COPY FROM VIDEO: "<< milliseconds(t11-t10)<<" ms"<<endl;
hipFree(Mult_result);
return result_of_IFFT;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
#include <complex>
#include <hip/device_functions.h>
#include <hip/hip_complex.h>
#include <chrono>
#include <iostream>
#pragma comment(lib,"cufft.lib")
using namespace std;
__global__
void Complex_mult(hipfftComplex * c, const hipfftComplex * a, const hipfftComplex * b) {
int i = threadIdx.x + blockIdx.x * blockDim.x;
c[i].x = (a[i].x * b[i].x - a[i].y * (-b[i].y));
c[i].y = (a[i].x * (-b[i].y) + a[i].y * b[i].x);
}
std::chrono::time_point<std::chrono::high_resolution_clock> now()
{
return std::chrono::high_resolution_clock::now();
}
template <typename T>
double milliseconds(T t)
{
return (double) std::chrono::duration_cast<std::chrono::nanoseconds>(t).count() / 1000000;
}
extern "C"
hipfftComplex* FFT_GPU(hipfftComplex* signal1, hipfftComplex* signal2, int len_c)
{
hipfftComplex* GPU_data_first;
hipfftComplex* GPU_data_second;
auto t1 = now();
hipMalloc((void**)&GPU_data_first, len_c * sizeof(hipfftComplex));
hipMalloc((void**)&GPU_data_second, len_c * sizeof(hipfftComplex));
hipfftHandle plan1;
hipfftPlan1d(&plan1, len_c, HIPFFT_C2C, 1);
auto t2 = now();
cout<<"VIDEO MEM: "<< milliseconds(t2-t1)<<" ms"<<endl;
hipMemcpy(GPU_data_first, signal1, len_c * sizeof(hipfftComplex), hipMemcpyHostToDevice);
hipMemcpy(GPU_data_second, signal2, len_c * sizeof(hipfftComplex), hipMemcpyHostToDevice);
auto t3 = now();
cout<<"COPY DATA: "<< milliseconds(t3-t2)<<" ms"<<endl;
auto t3_1 = now();
//cudaDeviceSynchronize();
hipfftExecC2C(plan1, (hipfftComplex*)GPU_data_first, (hipfftComplex*)GPU_data_first, HIPFFT_FORWARD);
hipfftExecC2C(plan1, (hipfftComplex*)GPU_data_second, (hipfftComplex*)GPU_data_second, HIPFFT_FORWARD);
auto t4 = now();
cout<<"FFT: "<< milliseconds(t4-t3_1)<<" ms"<<endl;
//cufftDestroy(plan1); // освобождение памяти
hipfftComplex* Mult_result;
hipMalloc((void**)&Mult_result, len_c * sizeof(hipfftComplex));
auto t6 = now();
Complex_mult <<<256, 192>>>(Mult_result, GPU_data_first, GPU_data_second);
auto t7 = now();
cout<<"cMULT: "<< milliseconds(t7-t6)<<" ms"<<endl;
hipFree(GPU_data_first);
hipFree(GPU_data_second);
hipfftHandle plan3;
auto t8 = now();
// cufftPlan1d(&plan3, len_c, CUFFT_C2C, 1);
hipfftExecC2C(plan1, (hipfftComplex*)Mult_result, (hipfftComplex*)Mult_result, HIPFFT_BACKWARD);
auto t9 = now();
cout<<"IFFT: "<< milliseconds(t9-t8)<<" ms"<<endl;
hipfftComplex* result_of_IFFT = new hipfftComplex[len_c];
auto t10 = now();
hipMemcpy(result_of_IFFT, Mult_result, sizeof(hipfftComplex) * (len_c), hipMemcpyDeviceToHost);
auto t11 = now();
cout<<"COPY FROM VIDEO: "<< milliseconds(t11-t10)<<" ms"<<endl;
hipFree(Mult_result);
return result_of_IFFT;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.globl _Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.p2align 8
.type _Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_,@function
_Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b32 v6, v[2:3], off offset:4
global_load_b32 v7, v[4:5], off offset:4
global_load_b32 v8, v[2:3], off
global_load_b32 v9, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(2)
v_mul_f32_e32 v6, v6, v7
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v6, v8, v9
global_store_b32 v[0:1], v6, off
global_load_b32 v6, v[4:5], off offset:4
s_clause 0x1
global_load_b32 v7, v[2:3], off
global_load_b32 v2, v[2:3], off offset:4
global_load_b32 v3, v[4:5], off
s_waitcnt vmcnt(2)
v_mul_f32_e32 v4, v7, v6
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v2, v2, v3, -v4
global_store_b32 v[0:1], v2, off offset:4
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_, .Lfunc_end0-_Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
#include <complex>
#include <hip/device_functions.h>
#include <hip/hip_complex.h>
#include <chrono>
#include <iostream>
#pragma comment(lib,"cufft.lib")
using namespace std;
__global__
void Complex_mult(hipfftComplex * c, const hipfftComplex * a, const hipfftComplex * b) {
int i = threadIdx.x + blockIdx.x * blockDim.x;
c[i].x = (a[i].x * b[i].x - a[i].y * (-b[i].y));
c[i].y = (a[i].x * (-b[i].y) + a[i].y * b[i].x);
}
std::chrono::time_point<std::chrono::high_resolution_clock> now()
{
return std::chrono::high_resolution_clock::now();
}
template <typename T>
double milliseconds(T t)
{
return (double) std::chrono::duration_cast<std::chrono::nanoseconds>(t).count() / 1000000;
}
extern "C"
hipfftComplex* FFT_GPU(hipfftComplex* signal1, hipfftComplex* signal2, int len_c)
{
hipfftComplex* GPU_data_first;
hipfftComplex* GPU_data_second;
auto t1 = now();
hipMalloc((void**)&GPU_data_first, len_c * sizeof(hipfftComplex));
hipMalloc((void**)&GPU_data_second, len_c * sizeof(hipfftComplex));
hipfftHandle plan1;
hipfftPlan1d(&plan1, len_c, HIPFFT_C2C, 1);
auto t2 = now();
cout<<"VIDEO MEM: "<< milliseconds(t2-t1)<<" ms"<<endl;
hipMemcpy(GPU_data_first, signal1, len_c * sizeof(hipfftComplex), hipMemcpyHostToDevice);
hipMemcpy(GPU_data_second, signal2, len_c * sizeof(hipfftComplex), hipMemcpyHostToDevice);
auto t3 = now();
cout<<"COPY DATA: "<< milliseconds(t3-t2)<<" ms"<<endl;
auto t3_1 = now();
//cudaDeviceSynchronize();
hipfftExecC2C(plan1, (hipfftComplex*)GPU_data_first, (hipfftComplex*)GPU_data_first, HIPFFT_FORWARD);
hipfftExecC2C(plan1, (hipfftComplex*)GPU_data_second, (hipfftComplex*)GPU_data_second, HIPFFT_FORWARD);
auto t4 = now();
cout<<"FFT: "<< milliseconds(t4-t3_1)<<" ms"<<endl;
//cufftDestroy(plan1); // освобождение памяти
hipfftComplex* Mult_result;
hipMalloc((void**)&Mult_result, len_c * sizeof(hipfftComplex));
auto t6 = now();
Complex_mult <<<256, 192>>>(Mult_result, GPU_data_first, GPU_data_second);
auto t7 = now();
cout<<"cMULT: "<< milliseconds(t7-t6)<<" ms"<<endl;
hipFree(GPU_data_first);
hipFree(GPU_data_second);
hipfftHandle plan3;
auto t8 = now();
// cufftPlan1d(&plan3, len_c, CUFFT_C2C, 1);
hipfftExecC2C(plan1, (hipfftComplex*)Mult_result, (hipfftComplex*)Mult_result, HIPFFT_BACKWARD);
auto t9 = now();
cout<<"IFFT: "<< milliseconds(t9-t8)<<" ms"<<endl;
hipfftComplex* result_of_IFFT = new hipfftComplex[len_c];
auto t10 = now();
hipMemcpy(result_of_IFFT, Mult_result, sizeof(hipfftComplex) * (len_c), hipMemcpyDeviceToHost);
auto t11 = now();
cout<<"COPY FROM VIDEO: "<< milliseconds(t11-t10)<<" ms"<<endl;
hipFree(Mult_result);
return result_of_IFFT;
} | .text
.file "vectorAdd.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_ # -- Begin function _Z27__device_stub__Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.p2align 4, 0x90
.type _Z27__device_stub__Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_,@function
_Z27__device_stub__Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_: # @_Z27__device_stub__Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_, .Lfunc_end0-_Z27__device_stub__Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.cfi_endproc
# -- End function
.globl _Z3nowv # -- Begin function _Z3nowv
.p2align 4, 0x90
.type _Z3nowv,@function
_Z3nowv: # @_Z3nowv
.cfi_startproc
# %bb.0:
jmp _ZNSt6chrono3_V212system_clock3nowEv # TAILCALL
.Lfunc_end1:
.size _Z3nowv, .Lfunc_end1-_Z3nowv
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function FFT_GPU
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl FFT_GPU
.p2align 4, 0x90
.type FFT_GPU,@function
FFT_GPU: # @FFT_GPU
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movq %rsi, %r14
movq %rdi, %r15
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r13
movl %ebx, 36(%rsp) # 4-byte Spill
movslq %ebx, %r12
leaq (,%r12,8), %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movl %r12d, %esi
movl $41, %edx
movl $1, %ecx
callq hipfftPlan1d
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r12
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r12, %rax
subq %r13, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r13
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r13), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %rbp
testq %rbp, %rbp
je .LBB2_27
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbp)
je .LBB2_3
# %bb.2:
movzbl 67(%rbp), %eax
jmp .LBB2_4
.LBB2_3:
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r13, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r14
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r12, %r14
xorps %xmm0, %xmm0
cvtsi2sd %r14, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB2_27
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i30
cmpb $0, 56(%r15)
je .LBB2_7
# %bb.6:
movzbl 67(%r15), %eax
jmp .LBB2_8
.LBB2_7:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit33
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r14
movq 24(%rsp), %rdi
movq 16(%rsp), %rdx
movq %rdx, %rsi
movl $-1, %ecx
callq hipfftExecC2C
movq 24(%rsp), %rdi
movq 8(%rsp), %rdx
movq %rdx, %rsi
movl $-1, %ecx
callq hipfftExecC2C
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r15
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r14, %r15
xorps %xmm0, %xmm0
cvtsi2sd %r15, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB2_27
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i35
cmpb $0, 56(%r15)
je .LBB2_11
# %bb.10:
movzbl 67(%r15), %eax
jmp .LBB2_12
.LBB2_11:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit38
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rsp, %rdi
movq %rbx, %rsi
callq hipMalloc
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r14
movabsq $4294967488, %rdx # imm = 0x1000000C0
leaq 64(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_14
# %bb.13:
movq (%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_14:
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r15
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r14, %r15
xorps %xmm0, %xmm0
cvtsi2sd %r15, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB2_27
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i40
cmpb $0, 56(%r15)
je .LBB2_17
# %bb.16:
movzbl 67(%r15), %eax
jmp .LBB2_18
.LBB2_17:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit43
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r14
movq 24(%rsp), %rdi
movq (%rsp), %rdx
movq %rdx, %rsi
movl $1, %ecx
callq hipfftExecC2C
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r15
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r14, %r15
xorps %xmm0, %xmm0
cvtsi2sd %r15, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB2_27
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i45
cmpb $0, 56(%r15)
je .LBB2_21
# %bb.20:
movzbl 67(%r15), %eax
jmp .LBB2_22
.LBB2_21:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit48
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cmpl $0, 36(%rsp) # 4-byte Folded Reload
movq $-1, %rdi
cmovnsq %rbx, %rdi
callq _Znam
movq %rax, %r14
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r15
movq (%rsp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %rbx
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r15, %rbx
xorps %xmm0, %xmm0
cvtsi2sd %rbx, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r15
testq %r15, %r15
je .LBB2_27
# %bb.23: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i50
cmpb $0, 56(%r15)
je .LBB2_25
# %bb.24:
movzbl 67(%r15), %eax
jmp .LBB2_26
.LBB2_25:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_26: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit53
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rsp), %rdi
callq hipFree
movq %r14, %rax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_27:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size FFT_GPU, .Lfunc_end2-FFT_GPU
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_,@object # @_Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.section .rodata,"a",@progbits
.globl _Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.p2align 3, 0x0
_Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_:
.quad _Z27__device_stub__Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.size _Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "VIDEO MEM: "
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " ms"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "COPY DATA: "
.size .L.str.2, 12
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "FFT: "
.size .L.str.3, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "cMULT: "
.size .L.str.4, 8
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "IFFT: "
.size .L.str.5, 7
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "COPY FROM VIDEO: "
.size .L.str.6, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_"
.size .L__unnamed_1, 50
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.section .deplibs,"MS",@llvm_dependent_libraries,1
.ascii "cufft.lib"
.byte 0
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12Complex_multP6float2PKS_S2_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x0c0fe200078e0207 */
/*0080*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea8000c1e1b00 */
/*0090*/ LDG.E.64 R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ FMUL R13, R9, R11 ; /* 0x0000000b090d7220 */
/* 0x004fc80000400000 */
/*00c0*/ FFMA R13, R8, R10, R13 ; /* 0x0000000a080d7223 */
/* 0x000fca000000000d */
/*00d0*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x000fe8000c101904 */
/*00e0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ee2000c1e1900 */
/*0100*/ FMUL R0, R11, R0 ; /* 0x000000000b007220 */
/* 0x004fc80000400000 */
/*0110*/ FFMA R9, R9, R8, -R0 ; /* 0x0000000809097223 */
/* 0x008fca0000000800 */
/*0120*/ STG.E [R6.64+0x4], R9 ; /* 0x0000040906007986 */
/* 0x000fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.globl _Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.p2align 8
.type _Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_,@function
_Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b32 v6, v[2:3], off offset:4
global_load_b32 v7, v[4:5], off offset:4
global_load_b32 v8, v[2:3], off
global_load_b32 v9, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(2)
v_mul_f32_e32 v6, v6, v7
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v6, v8, v9
global_store_b32 v[0:1], v6, off
global_load_b32 v6, v[4:5], off offset:4
s_clause 0x1
global_load_b32 v7, v[2:3], off
global_load_b32 v2, v[2:3], off offset:4
global_load_b32 v3, v[4:5], off
s_waitcnt vmcnt(2)
v_mul_f32_e32 v4, v7, v6
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v2, v2, v3, -v4
global_store_b32 v[0:1], v2, off offset:4
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_, .Lfunc_end0-_Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000bcaa7_00000000-6_vectorAdd.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4099:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3nowv
.type _Z3nowv, @function
_Z3nowv:
.LFB4092:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4092:
.size _Z3nowv, .-_Z3nowv
.globl _Z45__device_stub__Z12Complex_multP6float2PKS_S2_P6float2PKS_S2_
.type _Z45__device_stub__Z12Complex_multP6float2PKS_S2_P6float2PKS_S2_, @function
_Z45__device_stub__Z12Complex_multP6float2PKS_S2_P6float2PKS_S2_:
.LFB4121:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12Complex_multP6float2PKS_S2_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4121:
.size _Z45__device_stub__Z12Complex_multP6float2PKS_S2_P6float2PKS_S2_, .-_Z45__device_stub__Z12Complex_multP6float2PKS_S2_P6float2PKS_S2_
.globl _Z12Complex_multP6float2PKS_S2_
.type _Z12Complex_multP6float2PKS_S2_, @function
_Z12Complex_multP6float2PKS_S2_:
.LFB4122:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z12Complex_multP6float2PKS_S2_P6float2PKS_S2_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4122:
.size _Z12Complex_multP6float2PKS_S2_, .-_Z12Complex_multP6float2PKS_S2_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "VIDEO MEM: "
.LC2:
.string " ms"
.LC3:
.string "COPY DATA: "
.LC4:
.string "FFT: "
.LC5:
.string "cMULT: "
.LC6:
.string "IFFT: "
.LC7:
.string "COPY FROM VIDEO: "
.text
.globl FFT_GPU
.type FFT_GPU, @function
FFT_GPU:
.LFB4094:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %r14
movq %rsi, 8(%rsp)
movl %edx, %r12d
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbp
movslq %r12d, %r15
leaq 0(,%r15,8), %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 20(%rsp), %rdi
movl $1, %ecx
movl $41, %edx
movl %r12d, %esi
call cufftPlan1d@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r12
movl $11, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %r12, %rax
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC1(%rip), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r13
testq %r13, %r13
je .L44
cmpb $0, 56(%r13)
je .L16
movzbl 67(%r13), %esi
.L17:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbp
movl $11, %edx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
subq %r12, %rbp
pxor %xmm0, %xmm0
cvtsi2sdq %rbp, %xmm0
divsd .LC1(%rip), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L45
cmpb $0, 56(%r12)
je .L20
movzbl 67(%r12), %esi
.L21:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r12
movq 24(%rsp), %rsi
movl $-1, %ecx
movq %rsi, %rdx
movl 20(%rsp), %edi
call cufftExecC2C@PLT
movq 32(%rsp), %rsi
movl $-1, %ecx
movq %rsi, %rdx
movl 20(%rsp), %edi
call cufftExecC2C@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbp
movl $5, %edx
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
subq %r12, %rbp
pxor %xmm0, %xmm0
cvtsi2sdq %rbp, %xmm0
divsd .LC1(%rip), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L46
cmpb $0, 56(%r12)
je .L24
movzbl 67(%r12), %esi
.L25:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r12
movl $192, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $256, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L47
.L26:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbp
movl $7, %edx
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
subq %r12, %rbp
pxor %xmm0, %xmm0
cvtsi2sdq %rbp, %xmm0
divsd .LC1(%rip), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L48
cmpb $0, 56(%r12)
je .L29
movzbl 67(%r12), %esi
.L30:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r12
movq 40(%rsp), %rsi
movl $1, %ecx
movq %rsi, %rdx
movl 20(%rsp), %edi
call cufftExecC2C@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbp
movl $6, %edx
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
subq %r12, %rbp
pxor %xmm0, %xmm0
cvtsi2sdq %rbp, %xmm0
divsd .LC1(%rip), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L49
cmpb $0, 56(%r12)
je .L33
movzbl 67(%r12), %esi
.L34:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
shrq $60, %r15
jne .L35
movq %rbx, %rdi
call _Znam@PLT
movq %rax, %rbp
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r12
movl $2, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movl $17, %edx
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
subq %r12, %rbx
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
divsd .LC1(%rip), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $3, %edx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L50
cmpb $0, 56(%r12)
je .L38
movzbl 67(%r12), %esi
.L39:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L51
movq %rbp, %rax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L52
call _ZSt16__throw_bad_castv@PLT
.L52:
call __stack_chk_fail@PLT
.L16:
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L17
.L45:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L53
call _ZSt16__throw_bad_castv@PLT
.L53:
call __stack_chk_fail@PLT
.L20:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L21
.L46:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L54
call _ZSt16__throw_bad_castv@PLT
.L54:
call __stack_chk_fail@PLT
.L24:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L25
.L47:
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z45__device_stub__Z12Complex_multP6float2PKS_S2_P6float2PKS_S2_
jmp .L26
.L48:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L55
call _ZSt16__throw_bad_castv@PLT
.L55:
call __stack_chk_fail@PLT
.L29:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L30
.L49:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L56
call _ZSt16__throw_bad_castv@PLT
.L56:
call __stack_chk_fail@PLT
.L33:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L34
.L50:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L57
call _ZSt16__throw_bad_castv@PLT
.L57:
call __stack_chk_fail@PLT
.L38:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L39
.L35:
movq 72(%rsp), %rax
subq %fs:40, %rax
je .L40
call __stack_chk_fail@PLT
.L40:
call __cxa_throw_bad_array_new_length@PLT
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4094:
.size FFT_GPU, .-FFT_GPU
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "_Z12Complex_multP6float2PKS_S2_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4124:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z12Complex_multP6float2PKS_S2_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4124:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vectorAdd.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_ # -- Begin function _Z27__device_stub__Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.p2align 4, 0x90
.type _Z27__device_stub__Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_,@function
_Z27__device_stub__Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_: # @_Z27__device_stub__Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_, .Lfunc_end0-_Z27__device_stub__Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.cfi_endproc
# -- End function
.globl _Z3nowv # -- Begin function _Z3nowv
.p2align 4, 0x90
.type _Z3nowv,@function
_Z3nowv: # @_Z3nowv
.cfi_startproc
# %bb.0:
jmp _ZNSt6chrono3_V212system_clock3nowEv # TAILCALL
.Lfunc_end1:
.size _Z3nowv, .Lfunc_end1-_Z3nowv
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function FFT_GPU
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl FFT_GPU
.p2align 4, 0x90
.type FFT_GPU,@function
FFT_GPU: # @FFT_GPU
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movq %rsi, %r14
movq %rdi, %r15
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r13
movl %ebx, 36(%rsp) # 4-byte Spill
movslq %ebx, %r12
leaq (,%r12,8), %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movl %r12d, %esi
movl $41, %edx
movl $1, %ecx
callq hipfftPlan1d
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r12
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r12, %rax
subq %r13, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r13
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r13), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %rbp
testq %rbp, %rbp
je .LBB2_27
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbp)
je .LBB2_3
# %bb.2:
movzbl 67(%rbp), %eax
jmp .LBB2_4
.LBB2_3:
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r13, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r14
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r12, %r14
xorps %xmm0, %xmm0
cvtsi2sd %r14, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB2_27
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i30
cmpb $0, 56(%r15)
je .LBB2_7
# %bb.6:
movzbl 67(%r15), %eax
jmp .LBB2_8
.LBB2_7:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit33
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r14
movq 24(%rsp), %rdi
movq 16(%rsp), %rdx
movq %rdx, %rsi
movl $-1, %ecx
callq hipfftExecC2C
movq 24(%rsp), %rdi
movq 8(%rsp), %rdx
movq %rdx, %rsi
movl $-1, %ecx
callq hipfftExecC2C
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r15
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r14, %r15
xorps %xmm0, %xmm0
cvtsi2sd %r15, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB2_27
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i35
cmpb $0, 56(%r15)
je .LBB2_11
# %bb.10:
movzbl 67(%r15), %eax
jmp .LBB2_12
.LBB2_11:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit38
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rsp, %rdi
movq %rbx, %rsi
callq hipMalloc
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r14
movabsq $4294967488, %rdx # imm = 0x1000000C0
leaq 64(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_14
# %bb.13:
movq (%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_14:
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r15
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r14, %r15
xorps %xmm0, %xmm0
cvtsi2sd %r15, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB2_27
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i40
cmpb $0, 56(%r15)
je .LBB2_17
# %bb.16:
movzbl 67(%r15), %eax
jmp .LBB2_18
.LBB2_17:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit43
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r14
movq 24(%rsp), %rdi
movq (%rsp), %rdx
movq %rdx, %rsi
movl $1, %ecx
callq hipfftExecC2C
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r15
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r14, %r15
xorps %xmm0, %xmm0
cvtsi2sd %r15, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB2_27
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i45
cmpb $0, 56(%r15)
je .LBB2_21
# %bb.20:
movzbl 67(%r15), %eax
jmp .LBB2_22
.LBB2_21:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit48
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cmpl $0, 36(%rsp) # 4-byte Folded Reload
movq $-1, %rdi
cmovnsq %rbx, %rdi
callq _Znam
movq %rax, %r14
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r15
movq (%rsp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %rbx
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r15, %rbx
xorps %xmm0, %xmm0
cvtsi2sd %rbx, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r15
testq %r15, %r15
je .LBB2_27
# %bb.23: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i50
cmpb $0, 56(%r15)
je .LBB2_25
# %bb.24:
movzbl 67(%r15), %eax
jmp .LBB2_26
.LBB2_25:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_26: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit53
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rsp), %rdi
callq hipFree
movq %r14, %rax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_27:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size FFT_GPU, .Lfunc_end2-FFT_GPU
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_,@object # @_Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.section .rodata,"a",@progbits
.globl _Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.p2align 3, 0x0
_Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_:
.quad _Z27__device_stub__Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.size _Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "VIDEO MEM: "
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " ms"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "COPY DATA: "
.size .L.str.2, 12
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "FFT: "
.size .L.str.3, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "cMULT: "
.size .L.str.4, 8
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "IFFT: "
.size .L.str.5, 7
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "COPY FROM VIDEO: "
.size .L.str.6, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_"
.size .L__unnamed_1, 50
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.section .deplibs,"MS",@llvm_dependent_libraries,1
.ascii "cufft.lib"
.byte 0
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void IFD_boundary( int size, double *d_Price, double lambda_U, double lambda_L )
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i < size)
{
if (i == 0)//top condition
{
d_Price[i] = lambda_U;
}
else if (i == size - 1) //bottom condition
{
d_Price[i] = 0.0;
}
}
} | code for sm_80
Function : _Z12IFD_boundaryiPddd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fd80000000a00 */
/*0080*/ @!P0 BRA 0x110 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0090*/ ULDC UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe40000000800 */
/*00a0*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fcc000fffe03f */
/*00b0*/ ISETP.NE.AND P0, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x000fda000bf05270 */
/*00c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fc800078e00ff */
/*00e0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*00f0*/ STG.E.64 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101b06 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0120*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe200078e00ff */
/*0130*/ MOV R4, c[0x0][0x170] ; /* 0x00005c0000047a02 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R5, c[0x0][0x174] ; /* 0x00005d0000057a02 */
/* 0x000fca0000000f00 */
/*0150*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101b06 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void IFD_boundary( int size, double *d_Price, double lambda_U, double lambda_L )
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i < size)
{
if (i == 0)//top condition
{
d_Price[i] = lambda_U;
}
else if (i == size - 1) //bottom condition
{
d_Price[i] = 0.0;
}
}
} | .file "tmpxft_00097025_00000000-6_IFD_boundary.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z12IFD_boundaryiPdddiPddd
.type _Z35__device_stub__Z12IFD_boundaryiPdddiPddd, @function
_Z35__device_stub__Z12IFD_boundaryiPdddiPddd:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movsd %xmm0, 8(%rsp)
movsd %xmm1, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12IFD_boundaryiPddd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z12IFD_boundaryiPdddiPddd, .-_Z35__device_stub__Z12IFD_boundaryiPdddiPddd
.globl _Z12IFD_boundaryiPddd
.type _Z12IFD_boundaryiPddd, @function
_Z12IFD_boundaryiPddd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12IFD_boundaryiPdddiPddd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12IFD_boundaryiPddd, .-_Z12IFD_boundaryiPddd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12IFD_boundaryiPddd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12IFD_boundaryiPddd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void IFD_boundary( int size, double *d_Price, double lambda_U, double lambda_L )
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i < size)
{
if (i == 0)//top condition
{
d_Price[i] = lambda_U;
}
else if (i == size - 1) //bottom condition
{
d_Price[i] = 0.0;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void IFD_boundary( int size, double *d_Price, double lambda_U, double lambda_L )
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i < size)
{
if (i == 0)//top condition
{
d_Price[i] = lambda_U;
}
else if (i == size - 1) //bottom condition
{
d_Price[i] = 0.0;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void IFD_boundary( int size, double *d_Price, double lambda_U, double lambda_L )
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i < size)
{
if (i == 0)//top condition
{
d_Price[i] = lambda_U;
}
else if (i == size - 1) //bottom condition
{
d_Price[i] = 0.0;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12IFD_boundaryiPddd
.globl _Z12IFD_boundaryiPddd
.p2align 8
.type _Z12IFD_boundaryiPddd,@function
_Z12IFD_boundaryiPddd:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s5, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB0_7
s_load_b64 s[2:3], s[0:1], 0x8
s_mov_b32 s4, exec_lo
v_cmpx_ne_u32_e32 0, v1
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_5
s_add_i32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, s5, v1
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB0_4
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_and_not1_saveexec_b32 s4, s4
s_cbranch_execz .LBB0_7
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
global_store_b64 v2, v[0:1], s[2:3]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12IFD_boundaryiPddd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12IFD_boundaryiPddd, .Lfunc_end0-_Z12IFD_boundaryiPddd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12IFD_boundaryiPddd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12IFD_boundaryiPddd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void IFD_boundary( int size, double *d_Price, double lambda_U, double lambda_L )
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i < size)
{
if (i == 0)//top condition
{
d_Price[i] = lambda_U;
}
else if (i == size - 1) //bottom condition
{
d_Price[i] = 0.0;
}
}
} | .text
.file "IFD_boundary.hip"
.globl _Z27__device_stub__IFD_boundaryiPddd # -- Begin function _Z27__device_stub__IFD_boundaryiPddd
.p2align 4, 0x90
.type _Z27__device_stub__IFD_boundaryiPddd,@function
_Z27__device_stub__IFD_boundaryiPddd: # @_Z27__device_stub__IFD_boundaryiPddd
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movsd %xmm0, 64(%rsp)
movsd %xmm1, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12IFD_boundaryiPddd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__IFD_boundaryiPddd, .Lfunc_end0-_Z27__device_stub__IFD_boundaryiPddd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12IFD_boundaryiPddd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12IFD_boundaryiPddd,@object # @_Z12IFD_boundaryiPddd
.section .rodata,"a",@progbits
.globl _Z12IFD_boundaryiPddd
.p2align 3, 0x0
_Z12IFD_boundaryiPddd:
.quad _Z27__device_stub__IFD_boundaryiPddd
.size _Z12IFD_boundaryiPddd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12IFD_boundaryiPddd"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__IFD_boundaryiPddd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12IFD_boundaryiPddd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12IFD_boundaryiPddd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fd80000000a00 */
/*0080*/ @!P0 BRA 0x110 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0090*/ ULDC UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe40000000800 */
/*00a0*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fcc000fffe03f */
/*00b0*/ ISETP.NE.AND P0, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x000fda000bf05270 */
/*00c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fc800078e00ff */
/*00e0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*00f0*/ STG.E.64 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101b06 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0120*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe200078e00ff */
/*0130*/ MOV R4, c[0x0][0x170] ; /* 0x00005c0000047a02 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R5, c[0x0][0x174] ; /* 0x00005d0000057a02 */
/* 0x000fca0000000f00 */
/*0150*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101b06 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12IFD_boundaryiPddd
.globl _Z12IFD_boundaryiPddd
.p2align 8
.type _Z12IFD_boundaryiPddd,@function
_Z12IFD_boundaryiPddd:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s5, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB0_7
s_load_b64 s[2:3], s[0:1], 0x8
s_mov_b32 s4, exec_lo
v_cmpx_ne_u32_e32 0, v1
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_5
s_add_i32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, s5, v1
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB0_4
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_and_not1_saveexec_b32 s4, s4
s_cbranch_execz .LBB0_7
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
global_store_b64 v2, v[0:1], s[2:3]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12IFD_boundaryiPddd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12IFD_boundaryiPddd, .Lfunc_end0-_Z12IFD_boundaryiPddd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12IFD_boundaryiPddd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12IFD_boundaryiPddd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00097025_00000000-6_IFD_boundary.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z12IFD_boundaryiPdddiPddd
.type _Z35__device_stub__Z12IFD_boundaryiPdddiPddd, @function
_Z35__device_stub__Z12IFD_boundaryiPdddiPddd:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movsd %xmm0, 8(%rsp)
movsd %xmm1, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12IFD_boundaryiPddd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z12IFD_boundaryiPdddiPddd, .-_Z35__device_stub__Z12IFD_boundaryiPdddiPddd
.globl _Z12IFD_boundaryiPddd
.type _Z12IFD_boundaryiPddd, @function
_Z12IFD_boundaryiPddd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12IFD_boundaryiPdddiPddd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12IFD_boundaryiPddd, .-_Z12IFD_boundaryiPddd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12IFD_boundaryiPddd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12IFD_boundaryiPddd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "IFD_boundary.hip"
.globl _Z27__device_stub__IFD_boundaryiPddd # -- Begin function _Z27__device_stub__IFD_boundaryiPddd
.p2align 4, 0x90
.type _Z27__device_stub__IFD_boundaryiPddd,@function
_Z27__device_stub__IFD_boundaryiPddd: # @_Z27__device_stub__IFD_boundaryiPddd
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movsd %xmm0, 64(%rsp)
movsd %xmm1, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12IFD_boundaryiPddd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__IFD_boundaryiPddd, .Lfunc_end0-_Z27__device_stub__IFD_boundaryiPddd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12IFD_boundaryiPddd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12IFD_boundaryiPddd,@object # @_Z12IFD_boundaryiPddd
.section .rodata,"a",@progbits
.globl _Z12IFD_boundaryiPddd
.p2align 3, 0x0
_Z12IFD_boundaryiPddd:
.quad _Z27__device_stub__IFD_boundaryiPddd
.size _Z12IFD_boundaryiPddd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12IFD_boundaryiPddd"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__IFD_boundaryiPddd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12IFD_boundaryiPddd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/transform.h>
#include <thrust/copy.h>
struct function_object
{
__device__ float operator () (const float & x)
{
return 2.0 * x + 1.0;
}
};
int main()
{
/* 1) allcate */
thrust::host_vector < float > host_vec(3);
thrust::device_vector < float > device_input(3);
thrust::device_vector < float > device_output(3);
/* 2) initialize */
host_vec[0] = 1.1;
host_vec[1] = 3.3;
host_vec[2] = 2.2;
/* 3) copy host to device */
thrust::copy(host_vec.begin(), host_vec.end(), device_input.begin());
/* 4) transform devide_input to device_output */
thrust::transform(device_input.begin(), device_input.end(), device_output.begin(), function_object());
/* 5) copy device to host */
thrust::copy(device_output.begin(), device_output.end(), host_vec.begin());
std::cout << host_vec[0] << std::endl;
std::cout << host_vec[1] << std::endl;
std::cout << host_vec[2] << std::endl;
return 0;
} | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tElN6thrust20THRUST_200700_800_NS8cuda_cub11__transform17unary_transform_fINS7_6detail15normal_iteratorINS7_10device_ptrIfEEEESF_NS9_14no_stencil_tagE15function_objectNS9_21always_true_predicateEEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R0, P1, R2.reuse, R7, RZ ; /* 0x0000000702007210 */
/* 0x042fe40007f3e0ff */
/*0060*/ IADD3 R6, P0, -R2, c[0x0][0x160], RZ ; /* 0x0000580002067a10 */
/* 0x000fc60007f1e1ff */
/*0070*/ IMAD.X R5, RZ, RZ, R3, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0603 */
/*0080*/ IADD3.X R3, ~R3, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590003037a10 */
/* 0x000fe200007fe5ff */
/*0090*/ IMAD.SHL.U32 R2, R0, 0x4, RZ ; /* 0x0000000400027824 */
/* 0x000fe200078e00ff */
/*00a0*/ ISETP.GT.U32.AND P0, PT, R6, 0x1ff, PT ; /* 0x000001ff0600780c */
/* 0x000fe40003f04070 */
/*00b0*/ SHF.L.U64.HI R0, R0, 0x2, R5 ; /* 0x0000000200007819 */
/* 0x000fe40000010205 */
/*00c0*/ ISETP.GT.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fe40003f04300 */
/*00d0*/ IADD3 R4, P1, R2.reuse, c[0x0][0x168], RZ ; /* 0x00005a0002047a10 */
/* 0x040fe40007f3e0ff */
/*00e0*/ IADD3 R2, P2, R2, c[0x0][0x170], RZ ; /* 0x00005c0002027a10 */
/* 0x000fc40007f5e0ff */
/*00f0*/ IADD3.X R5, R0.reuse, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000057a10 */
/* 0x040fe40000ffe4ff */
/*0100*/ IADD3.X R3, R0, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0000037a10 */
/* 0x000fca00017fe4ff */
/*0110*/ @P0 BRA 0x2b0 ; /* 0x0000019000000947 */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R0, R7, 0x100, RZ ; /* 0x0000010007007810 */
/* 0x000fe20007ffe0ff */
/*0130*/ BSSY B0, 0x220 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0140*/ ISETP.GT.U32.AND P0, PT, R6.reuse, R7, PT ; /* 0x000000070600720c */
/* 0x040fe40003f04070 */
/*0150*/ SHF.R.S32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */
/* 0x000fe40000011406 */
/*0160*/ ISETP.GT.U32.AND P1, PT, R6, R0, PT ; /* 0x000000000600720c */
/* 0x000fe40003f24070 */
/*0170*/ ISETP.GT.AND.EX P0, PT, R7.reuse, RZ, PT, P0 ; /* 0x000000ff0700720c */
/* 0x040fe40003f04300 */
/*0180*/ ISETP.GT.AND.EX P1, PT, R7, RZ, PT, P1 ; /* 0x000000ff0700720c */
/* 0x000fd60003f24310 */
/*0190*/ @!P0 BRA 0x210 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*01a0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea2000c1e1900 */
/*01b0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; /* 0x00000000ff087424 */
/* 0x000fe400078e00ff */
/*01c0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x40000000 ; /* 0x40000000ff097424 */
/* 0x000fe200078e00ff */
/*01d0*/ F2F.F64.F32 R6, R0 ; /* 0x0000000000067310 */
/* 0x004e2a0000201800 */
/*01e0*/ DFMA R6, R6, R8, 1 ; /* 0x3ff000000606742b */
/* 0x001e140000000008 */
/*01f0*/ F2F.F32.F64 R7, R6 ; /* 0x0000000600077310 */
/* 0x001e240000301000 */
/*0200*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0011e4000c101904 */
/*0210*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0220*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0230*/ LDG.E R4, [R4.64+0x400] ; /* 0x0004000404047981 */
/* 0x000ea2000c1e1900 */
/*0240*/ IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; /* 0x00000000ff087424 */
/* 0x000fe400078e00ff */
/*0250*/ IMAD.MOV.U32 R9, RZ, RZ, 0x40000000 ; /* 0x40000000ff097424 */
/* 0x000fe200078e00ff */
/*0260*/ F2F.F64.F32 R6, R4 ; /* 0x0000000400067310 */
/* 0x005e2a0000201800 */
/*0270*/ DFMA R6, R6, R8, 1 ; /* 0x3ff000000606742b */
/* 0x001e140000000008 */
/*0280*/ F2F.F32.F64 R7, R6 ; /* 0x0000000600077310 */
/* 0x001e240000301000 */
/*0290*/ STG.E [R2.64+0x400], R7 ; /* 0x0004000702007986 */
/* 0x001fe2000c101904 */
/*02a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02b0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea2000c1e1900 */
/*02c0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a7424 */
/* 0x000fe400078e00ff */
/*02d0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x40000000 ; /* 0x40000000ff0b7424 */
/* 0x000fe200078e00ff */
/*02e0*/ F2F.F64.F32 R6, R0 ; /* 0x0000000000067310 */
/* 0x004e2a0000201800 */
/*02f0*/ DFMA R6, R6, R10, 1 ; /* 0x3ff000000606742b */
/* 0x001e14000000000a */
/*0300*/ F2F.F32.F64 R7, R6 ; /* 0x0000000600077310 */
/* 0x001e240000301000 */
/*0310*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe8000c101904 */
/*0320*/ LDG.E R12, [R4.64+0x400] ; /* 0x00040004040c7981 */
/* 0x000ea4000c1e1900 */
/*0330*/ F2F.F64.F32 R8, R12 ; /* 0x0000000c00087310 */
/* 0x004e240000201800 */
/*0340*/ DFMA R8, R8, R10, 1 ; /* 0x3ff000000808742b */
/* 0x001e14000000000a */
/*0350*/ F2F.F32.F64 R9, R8 ; /* 0x0000000800097310 */
/* 0x001e240000301000 */
/*0360*/ STG.E [R2.64+0x400], R9 ; /* 0x0004000902007986 */
/* 0x001fe2000c101904 */
/*0370*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0380*/ BRA 0x380; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIfEEfEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x040fe40007f3e1ff */
/*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */
/* 0x002fe40007f5e0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */
/* 0x000fe40003f04070 */
/*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */
/* 0x000fe20000ffe5ff */
/*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fe400078210ff */
/*00b0*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fc40003f04100 */
/*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */
/* 0x000fd600008f1403 */
/*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */
/* 0x000fe40000011404 */
/*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */
/* 0x000fca00078e00ff */
/*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e2000c101904 */
/*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fc80003f04070 */
/*0150*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x001fca00078e00ff */
/*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fca00078e00ff */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/transform.h>
#include <thrust/copy.h>
struct function_object
{
__device__ float operator () (const float & x)
{
return 2.0 * x + 1.0;
}
};
int main()
{
/* 1) allcate */
thrust::host_vector < float > host_vec(3);
thrust::device_vector < float > device_input(3);
thrust::device_vector < float > device_output(3);
/* 2) initialize */
host_vec[0] = 1.1;
host_vec[1] = 3.3;
host_vec[2] = 2.2;
/* 3) copy host to device */
thrust::copy(host_vec.begin(), host_vec.end(), device_input.begin());
/* 4) transform devide_input to device_output */
thrust::transform(device_input.begin(), device_input.end(), device_output.begin(), function_object());
/* 5) copy device to host */
thrust::copy(device_output.begin(), device_output.end(), host_vec.begin());
std::cout << host_vec[0] << std::endl;
std::cout << host_vec[1] << std::endl;
std::cout << host_vec[2] << std::endl;
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/transform.h>
#include <thrust/copy.h>
struct function_object
{
__device__ float operator () (const float & x)
{
return 2.0 * x + 1.0;
}
};
int main()
{
/* 1) allcate */
thrust::host_vector < float > host_vec(3);
thrust::device_vector < float > device_input(3);
thrust::device_vector < float > device_output(3);
/* 2) initialize */
host_vec[0] = 1.1;
host_vec[1] = 3.3;
host_vec[2] = 2.2;
/* 3) copy host to device */
thrust::copy(host_vec.begin(), host_vec.end(), device_input.begin());
/* 4) transform devide_input to device_output */
thrust::transform(device_input.begin(), device_input.end(), device_output.begin(), function_object());
/* 5) copy device to host */
thrust::copy(device_output.begin(), device_output.end(), host_vec.begin());
std::cout << host_vec[0] << std::endl;
std::cout << host_vec[1] << std::endl;
std::cout << host_vec[2] << std::endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/transform.h>
#include <thrust/copy.h>
struct function_object
{
__device__ float operator () (const float & x)
{
return 2.0 * x + 1.0;
}
};
int main()
{
/* 1) allcate */
thrust::host_vector < float > host_vec(3);
thrust::device_vector < float > device_input(3);
thrust::device_vector < float > device_output(3);
/* 2) initialize */
host_vec[0] = 1.1;
host_vec[1] = 3.3;
host_vec[2] = 2.2;
/* 3) copy host to device */
thrust::copy(host_vec.begin(), host_vec.end(), device_input.begin());
/* 4) transform devide_input to device_output */
thrust::transform(device_input.begin(), device_input.end(), device_output.begin(), function_object());
/* 5) copy device to host */
thrust::copy(device_output.begin(), device_output.end(), host_vec.begin());
std::cout << host_vec[0] << std::endl;
std::cout << host_vec[1] << std::endl;
std::cout << host_vec[2] << std::endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_:
s_load_b128 s[4:7], s[0:1], 0x10
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_mov_b32_e32 v2, s6
flat_store_b32 v[0:1], v2
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,comdat
.Lfunc_end0:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_, .Lfunc_end0-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_NS3_14no_stencil_tagE15function_objectNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_NS3_14no_stencil_tagE15function_objectNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_NS3_14no_stencil_tagE15function_objectNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_NS3_14no_stencil_tagE15function_objectNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_NS3_14no_stencil_tagE15function_objectNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_NS3_14no_stencil_tagE15function_objectNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_:
s_load_b128 s[4:7], s[0:1], 0x18
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_add_co_u32 v0, s0, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s3, 0, s0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
flat_load_b32 v2, v[2:3]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cvt_f64_f32_e32 v[2:3], v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[2:3], 2.0, 1.0
v_cvt_f32_f64_e32 v2, v[2:3]
flat_store_b32 v[0:1], v2
.LBB1_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_NS3_14no_stencil_tagE15function_objectNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_NS3_14no_stencil_tagE15function_objectNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_NS3_14no_stencil_tagE15function_objectNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,comdat
.Lfunc_end1:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_NS3_14no_stencil_tagE15function_objectNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_, .Lfunc_end1-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_NS3_14no_stencil_tagE15function_objectNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 24
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_NS3_14no_stencil_tagE15function_objectNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_NS3_14no_stencil_tagE15function_objectNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tElN6thrust20THRUST_200700_800_NS8cuda_cub11__transform17unary_transform_fINS7_6detail15normal_iteratorINS7_10device_ptrIfEEEESF_NS9_14no_stencil_tagE15function_objectNS9_21always_true_predicateEEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R0, P1, R2.reuse, R7, RZ ; /* 0x0000000702007210 */
/* 0x042fe40007f3e0ff */
/*0060*/ IADD3 R6, P0, -R2, c[0x0][0x160], RZ ; /* 0x0000580002067a10 */
/* 0x000fc60007f1e1ff */
/*0070*/ IMAD.X R5, RZ, RZ, R3, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0603 */
/*0080*/ IADD3.X R3, ~R3, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590003037a10 */
/* 0x000fe200007fe5ff */
/*0090*/ IMAD.SHL.U32 R2, R0, 0x4, RZ ; /* 0x0000000400027824 */
/* 0x000fe200078e00ff */
/*00a0*/ ISETP.GT.U32.AND P0, PT, R6, 0x1ff, PT ; /* 0x000001ff0600780c */
/* 0x000fe40003f04070 */
/*00b0*/ SHF.L.U64.HI R0, R0, 0x2, R5 ; /* 0x0000000200007819 */
/* 0x000fe40000010205 */
/*00c0*/ ISETP.GT.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fe40003f04300 */
/*00d0*/ IADD3 R4, P1, R2.reuse, c[0x0][0x168], RZ ; /* 0x00005a0002047a10 */
/* 0x040fe40007f3e0ff */
/*00e0*/ IADD3 R2, P2, R2, c[0x0][0x170], RZ ; /* 0x00005c0002027a10 */
/* 0x000fc40007f5e0ff */
/*00f0*/ IADD3.X R5, R0.reuse, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000057a10 */
/* 0x040fe40000ffe4ff */
/*0100*/ IADD3.X R3, R0, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0000037a10 */
/* 0x000fca00017fe4ff */
/*0110*/ @P0 BRA 0x2b0 ; /* 0x0000019000000947 */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R0, R7, 0x100, RZ ; /* 0x0000010007007810 */
/* 0x000fe20007ffe0ff */
/*0130*/ BSSY B0, 0x220 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0140*/ ISETP.GT.U32.AND P0, PT, R6.reuse, R7, PT ; /* 0x000000070600720c */
/* 0x040fe40003f04070 */
/*0150*/ SHF.R.S32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */
/* 0x000fe40000011406 */
/*0160*/ ISETP.GT.U32.AND P1, PT, R6, R0, PT ; /* 0x000000000600720c */
/* 0x000fe40003f24070 */
/*0170*/ ISETP.GT.AND.EX P0, PT, R7.reuse, RZ, PT, P0 ; /* 0x000000ff0700720c */
/* 0x040fe40003f04300 */
/*0180*/ ISETP.GT.AND.EX P1, PT, R7, RZ, PT, P1 ; /* 0x000000ff0700720c */
/* 0x000fd60003f24310 */
/*0190*/ @!P0 BRA 0x210 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*01a0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea2000c1e1900 */
/*01b0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; /* 0x00000000ff087424 */
/* 0x000fe400078e00ff */
/*01c0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x40000000 ; /* 0x40000000ff097424 */
/* 0x000fe200078e00ff */
/*01d0*/ F2F.F64.F32 R6, R0 ; /* 0x0000000000067310 */
/* 0x004e2a0000201800 */
/*01e0*/ DFMA R6, R6, R8, 1 ; /* 0x3ff000000606742b */
/* 0x001e140000000008 */
/*01f0*/ F2F.F32.F64 R7, R6 ; /* 0x0000000600077310 */
/* 0x001e240000301000 */
/*0200*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0011e4000c101904 */
/*0210*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0220*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0230*/ LDG.E R4, [R4.64+0x400] ; /* 0x0004000404047981 */
/* 0x000ea2000c1e1900 */
/*0240*/ IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; /* 0x00000000ff087424 */
/* 0x000fe400078e00ff */
/*0250*/ IMAD.MOV.U32 R9, RZ, RZ, 0x40000000 ; /* 0x40000000ff097424 */
/* 0x000fe200078e00ff */
/*0260*/ F2F.F64.F32 R6, R4 ; /* 0x0000000400067310 */
/* 0x005e2a0000201800 */
/*0270*/ DFMA R6, R6, R8, 1 ; /* 0x3ff000000606742b */
/* 0x001e140000000008 */
/*0280*/ F2F.F32.F64 R7, R6 ; /* 0x0000000600077310 */
/* 0x001e240000301000 */
/*0290*/ STG.E [R2.64+0x400], R7 ; /* 0x0004000702007986 */
/* 0x001fe2000c101904 */
/*02a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02b0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea2000c1e1900 */
/*02c0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a7424 */
/* 0x000fe400078e00ff */
/*02d0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x40000000 ; /* 0x40000000ff0b7424 */
/* 0x000fe200078e00ff */
/*02e0*/ F2F.F64.F32 R6, R0 ; /* 0x0000000000067310 */
/* 0x004e2a0000201800 */
/*02f0*/ DFMA R6, R6, R10, 1 ; /* 0x3ff000000606742b */
/* 0x001e14000000000a */
/*0300*/ F2F.F32.F64 R7, R6 ; /* 0x0000000600077310 */
/* 0x001e240000301000 */
/*0310*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe8000c101904 */
/*0320*/ LDG.E R12, [R4.64+0x400] ; /* 0x00040004040c7981 */
/* 0x000ea4000c1e1900 */
/*0330*/ F2F.F64.F32 R8, R12 ; /* 0x0000000c00087310 */
/* 0x004e240000201800 */
/*0340*/ DFMA R8, R8, R10, 1 ; /* 0x3ff000000808742b */
/* 0x001e14000000000a */
/*0350*/ F2F.F32.F64 R9, R8 ; /* 0x0000000800097310 */
/* 0x001e240000301000 */
/*0360*/ STG.E [R2.64+0x400], R9 ; /* 0x0004000902007986 */
/* 0x001fe2000c101904 */
/*0370*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0380*/ BRA 0x380; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIfEEfEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x040fe40007f3e1ff */
/*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */
/* 0x002fe40007f5e0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */
/* 0x000fe40003f04070 */
/*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */
/* 0x000fe20000ffe5ff */
/*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fe400078210ff */
/*00b0*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fc40003f04100 */
/*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */
/* 0x000fd600008f1403 */
/*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */
/* 0x000fe40000011404 */
/*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */
/* 0x000fca00078e00ff */
/*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e2000c101904 */
/*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fc80003f04070 */
/*0150*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x001fca00078e00ff */
/*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fca00078e00ff */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_:
s_load_b128 s[4:7], s[0:1], 0x10
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_mov_b32_e32 v2, s6
flat_store_b32 v[0:1], v2
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,comdat
.Lfunc_end0:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_, .Lfunc_end0-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_NS3_14no_stencil_tagE15function_objectNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_NS3_14no_stencil_tagE15function_objectNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_NS3_14no_stencil_tagE15function_objectNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_NS3_14no_stencil_tagE15function_objectNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_NS3_14no_stencil_tagE15function_objectNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_NS3_14no_stencil_tagE15function_objectNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_:
s_load_b128 s[4:7], s[0:1], 0x18
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_add_co_u32 v0, s0, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s3, 0, s0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
flat_load_b32 v2, v[2:3]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cvt_f64_f32_e32 v[2:3], v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[2:3], 2.0, 1.0
v_cvt_f32_f64_e32 v2, v[2:3]
flat_store_b32 v[0:1], v2
.LBB1_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_NS3_14no_stencil_tagE15function_objectNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_NS3_14no_stencil_tagE15function_objectNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_NS3_14no_stencil_tagE15function_objectNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,comdat
.Lfunc_end1:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_NS3_14no_stencil_tagE15function_objectNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_, .Lfunc_end1-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_NS3_14no_stencil_tagE15function_objectNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 24
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_NS3_14no_stencil_tagE15function_objectNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_NS3_14no_stencil_tagE15function_objectNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // CudaGameOfLife.Program
extern "C" __global__ void RunGeneration( bool* cells1, int cells1Len0, int cells1Len1, bool* cells2, int cells2Len0, int cells2Len1);
// CudaGameOfLife.Program
__device__ bool CheckCell( bool* cells1, int cells1Len0, int cells1Len1, int x, int y);
// CudaGameOfLife.Program
__device__ bool IsAlive( bool* cells1, int cells1Len0, int cells1Len1, int i, int x, int y);
// CudaGameOfLife.Program
__device__ int GetSurroundingCount( bool* cells1, int cells1Len0, int cells1Len1, int x, int y);
// CudaGameOfLife.Program
__device__ bool GetTL(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetTC(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetTR(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetL(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetR(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetBL(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetBC(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetBR(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
extern "C" __global__ void RunGeneration( bool* cells1, int cells1Len0, int cells1Len1, bool* cells2, int cells2Len0, int cells2Len1)
{
int x = blockIdx.x;
int y = blockIdx.y;
cells2[(x) * cells2Len1 + ( y)] = CheckCell(cells1, cells1Len0, cells1Len1, x, y);
}
// CudaGameOfLife.Program
__device__ bool CheckCell( bool* cells1, int cells1Len0, int cells1Len1, int x, int y)
{
int surroundingCount = GetSurroundingCount(cells1, cells1Len0, cells1Len1, x, y);
return IsAlive(cells1, cells1Len0, cells1Len1, surroundingCount, x, y);
}
// CudaGameOfLife.Program
__device__ bool IsAlive( bool* cells1, int cells1Len0, int cells1Len1, int i, int x, int y)
{
return i == 3 || (cells1[(x) * cells1Len1 + ( y)] && i == 2);
}
// CudaGameOfLife.Program
__device__ int GetSurroundingCount( bool* cells1, int cells1Len0, int cells1Len1, int x, int y)
{
int num = 0;
if (GetTL(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetTC(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetTR(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetL(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetR(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetBL(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetBC(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetBR(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
return num;
}
// CudaGameOfLife.Program
__device__ bool GetTL(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (x == 0)
{
x = 999;
}
else
{
x--;
}
if (y == 0)
{
y = 999;
}
else
{
y--;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetTC(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (y == 0)
{
y = 999;
}
else
{
y--;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetTR(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (x == 999)
{
x = 0;
}
else
{
x++;
}
if (y == 0)
{
y = 999;
}
else
{
y--;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetL(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (x == 0)
{
x = 999;
}
else
{
x--;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetR(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (x == 999)
{
x = 0;
}
else
{
x++;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetBL(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (x == 0)
{
x = 999;
}
else
{
x--;
}
if (y == 999)
{
y = 0;
}
else
{
y++;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetBC(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (y == 999)
{
y = 0;
}
else
{
y++;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetBR(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (x == 999)
{
x = 0;
}
else
{
x++;
}
if (y == 999)
{
y = 0;
}
else
{
y++;
}
return cells[(x) * cellsLen1 + ( y)];
} | code for sm_80
Function : RunGeneration
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e620000002500 */
/*0040*/ ISETP.NE.AND P1, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720c */
/* 0x041fe40003f25270 */
/*0050*/ IADD3 R4, R3, -0x1, RZ ; /* 0xffffffff03047810 */
/* 0x000fe40007ffe0ff */
/*0060*/ ISETP.NE.AND P0, PT, R0.reuse, RZ, PT ; /* 0x000000ff0000720c */
/* 0x042fe40003f05270 */
/*0070*/ IADD3 R2, R0, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x000fe40007ffe0ff */
/*0080*/ SEL R5, R4, 0x3e7, P1 ; /* 0x000003e704057807 */
/* 0x000fe40000800000 */
/*0090*/ SEL R16, R2, 0x3e7, P0 ; /* 0x000003e702107807 */
/* 0x000fc40000000000 */
/*00a0*/ ISETP.NE.AND P0, PT, R0.reuse, 0x3e7, PT ; /* 0x000003e70000780c */
/* 0x040fe20003f05270 */
/*00b0*/ IMAD R6, R0.reuse, c[0x0][0x16c], R5.reuse ; /* 0x00005b0000067a24 */
/* 0x140fe200078e0205 */
/*00c0*/ IADD3 R2, R0, 0x1, RZ ; /* 0x0000000100027810 */
/* 0x000fe20007ffe0ff */
/*00d0*/ IMAD R4, R16, c[0x0][0x16c], R5 ; /* 0x00005b0010047a24 */
/* 0x000fc600078e0205 */
/*00e0*/ SEL R2, R2, RZ, P0 ; /* 0x000000ff02027207 */
/* 0x000fe40000000000 */
/*00f0*/ IADD3 R10, P0, R6, c[0x0][0x160], RZ ; /* 0x00005800060a7a10 */
/* 0x000fe40007f1e0ff */
/*0100*/ IADD3 R8, P1, R4, c[0x0][0x160], RZ ; /* 0x0000580004087a10 */
/* 0x000fe20007f3e0ff */
/*0110*/ IMAD R5, R2, c[0x0][0x16c], R5 ; /* 0x00005b0002057a24 */
/* 0x000fe200078e0205 */
/*0120*/ LEA.HI.X.SX32 R11, R6, c[0x0][0x164], 0x1, P0 ; /* 0x00005900060b7a11 */
/* 0x000fe200000f0eff */
/*0130*/ IMAD R14, R16, c[0x0][0x16c], R3 ; /* 0x00005b00100e7a24 */
/* 0x000fe200078e0203 */
/*0140*/ LEA.HI.X.SX32 R9, R4, c[0x0][0x164], 0x1, P1 ; /* 0x0000590004097a11 */
/* 0x000fc600008f0eff */
/*0150*/ LDG.E.U8 R7, [R10.64] ; /* 0x000000040a077981 */
/* 0x0000a2000c1e1100 */
/*0160*/ IADD3 R12, P1, R5, c[0x0][0x160], RZ ; /* 0x00005800050c7a10 */
/* 0x000fe40007f3e0ff */
/*0170*/ ISETP.NE.AND P0, PT, R3.reuse, 0x3e7, PT ; /* 0x000003e70300780c */
/* 0x040fe20003f05270 */
/*0180*/ LDG.E.U8 R6, [R8.64] ; /* 0x0000000408067981 */
/* 0x0002e2000c1e1100 */
/*0190*/ IADD3 R17, R3, 0x1, RZ ; /* 0x0000000103117810 */
/* 0x000fe40007ffe0ff */
/*01a0*/ IADD3 R4, P2, R14, c[0x0][0x160], RZ ; /* 0x000058000e047a10 */
/* 0x000fe20007f5e0ff */
/*01b0*/ IMAD R15, R2, c[0x0][0x16c], R3 ; /* 0x00005b00020f7a24 */
/* 0x000fe200078e0203 */
/*01c0*/ LEA.HI.X.SX32 R13, R5, c[0x0][0x164], 0x1, P1 ; /* 0x00005900050d7a11 */
/* 0x000fe400008f0eff */
/*01d0*/ LEA.HI.X.SX32 R5, R14, c[0x0][0x164], 0x1, P2 ; /* 0x000059000e057a11 */
/* 0x000fc400010f0eff */
/*01e0*/ SEL R19, R17, RZ, P0 ; /* 0x000000ff11137207 */
/* 0x000fe20000000000 */
/*01f0*/ LDG.E.U8 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f22000c1e1100 */
/*0200*/ IADD3 R14, P0, R15, c[0x0][0x160], RZ ; /* 0x000058000f0e7a10 */
/* 0x000fc60007f1e0ff */
/*0210*/ LDG.E.U8 R17, [R4.64] ; /* 0x0000000404117981 */
/* 0x000b22000c1e1100 */
/*0220*/ IMAD R16, R16, c[0x0][0x16c], R19.reuse ; /* 0x00005b0010107a24 */
/* 0x100fe200078e0213 */
/*0230*/ LEA.HI.X.SX32 R15, R15, c[0x0][0x164], 0x1, P0 ; /* 0x000059000f0f7a11 */
/* 0x000fe200000f0eff */
/*0240*/ IMAD R9, R0, c[0x0][0x16c], R19 ; /* 0x00005b0000097a24 */
/* 0x002fc600078e0213 */
/*0250*/ IADD3 R10, P0, R16.reuse, c[0x0][0x160], RZ ; /* 0x00005800100a7a10 */
/* 0x041fe20007f1e0ff */
/*0260*/ LDG.E.U8 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f26000c1e1100 */
/*0270*/ LEA.HI.X.SX32 R11, R16, c[0x0][0x164], 0x1, P0 ; /* 0x00005900100b7a11 */
/* 0x000fe200000f0eff */
/*0280*/ IMAD R2, R2, c[0x0][0x16c], R19 ; /* 0x00005b0002027a24 */
/* 0x000fe200078e0213 */
/*0290*/ IADD3 R8, P0, R9, c[0x0][0x160], RZ ; /* 0x0000580009087a10 */
/* 0x000fc60007f1e0ff */
/*02a0*/ LDG.E.U8 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f22000c1e1100 */
/*02b0*/ LEA.HI.X.SX32 R9, R9, c[0x0][0x164], 0x1, P0 ; /* 0x0000590009097a11 */
/* 0x000fe400000f0eff */
/*02c0*/ IADD3 R4, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x020fc60007f1e0ff */
/*02d0*/ LDG.E.U8 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f62000c1e1100 */
/*02e0*/ LEA.HI.X.SX32 R5, R2, c[0x0][0x164], 0x1, P0 ; /* 0x0000590002057a11 */
/* 0x000fca00000f0eff */
/*02f0*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000162000c1e1100 */
/*0300*/ ISETP.NE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x004fe40003f45270 */
/*0310*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x008fe20003f25270 */
/*0320*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fc600078e00ff */
/*0330*/ SEL R2, RZ, 0x1, !P1 ; /* 0x00000001ff027807 */
/* 0x000fce0004800000 */
/*0340*/ @P2 SEL R2, R6, 0x2, !P1 ; /* 0x0000000206022807 */
/* 0x000fe40004800000 */
/*0350*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x010fe40003f05270 */
/*0360*/ ISETP.NE.AND P1, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fe40003f25270 */
/*0370*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fca0004000000 */
/*0380*/ IMAD.IADD R2, R2, 0x1, R7 ; /* 0x0000000102027824 */
/* 0x000fe200078e0207 */
/*0390*/ ISETP.NE.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fc80003f05270 */
/*03a0*/ IADD3 R5, R2, 0x1, RZ ; /* 0x0000000102057810 */
/* 0x001fe20007ffe0ff */
/*03b0*/ @!P1 IMAD.MOV R5, RZ, RZ, R2 ; /* 0x000000ffff059224 */
/* 0x000fe200078e0202 */
/*03c0*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc80003f25270 */
/*03d0*/ IADD3 R2, R5, 0x1, RZ ; /* 0x0000000105027810 */
/* 0x000fc60007ffe0ff */
/*03e0*/ @!P0 IMAD.MOV R2, RZ, RZ, R5 ; /* 0x000000ffff028224 */
/* 0x000fe200078e0205 */
/*03f0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x020fc80003f05270 */
/*0400*/ IADD3 R5, R2, 0x1, RZ ; /* 0x0000000102057810 */
/* 0x000fe20007ffe0ff */
/*0410*/ @!P1 IMAD.MOV R5, RZ, RZ, R2 ; /* 0x000000ffff059224 */
/* 0x000fe200078e0202 */
/*0420*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc80003f25270 */
/*0430*/ IADD3 R2, R5, 0x1, RZ ; /* 0x0000000105027810 */
/* 0x000fc60007ffe0ff */
/*0440*/ @!P0 IMAD.MOV R2, RZ, RZ, R5 ; /* 0x000000ffff028224 */
/* 0x000fca00078e0205 */
/*0450*/ IADD3 R6, R2, 0x1, RZ ; /* 0x0000000102067810 */
/* 0x000fe20007ffe0ff */
/*0460*/ @!P1 IMAD.MOV R6, RZ, RZ, R2 ; /* 0x000000ffff069224 */
/* 0x000fca00078e0202 */
/*0470*/ ISETP.NE.AND P1, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fda0003f25270 */
/*0480*/ @P1 IMAD R2, R0, c[0x0][0x16c], R3 ; /* 0x00005b0000021a24 */
/* 0x000fca00078e0203 */
/*0490*/ @P1 IADD3 R4, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002041a10 */
/* 0x000fc80007f1e0ff */
/*04a0*/ @P1 LEA.HI.X.SX32 R5, R2, c[0x0][0x164], 0x1, P0 ; /* 0x0000590002051a11 */
/* 0x000fca00000f0eff */
/*04b0*/ @P1 LDG.E.U8 R4, [R4.64] ; /* 0x0000000404041981 */
/* 0x000ea2000c1e1100 */
/*04c0*/ IMAD R0, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000007a24 */
/* 0x000fe400078e0203 */
/*04d0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fc600078e00ff */
/*04e0*/ IADD3 R2, P2, R0, c[0x0][0x170], RZ ; /* 0x00005c0000027a10 */
/* 0x000fc80007f5e0ff */
/*04f0*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x174], 0x1, P2 ; /* 0x00005d0000037a11 */
/* 0x000fe400010f0eff */
/*0500*/ @P1 ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400120c */
/* 0x004fc80003f05270 */
/*0510*/ @P1 ISETP.EQ.AND P0, PT, R6, 0x2, P0 ; /* 0x000000020600180c */
/* 0x000fc80000702270 */
/*0520*/ @P1 SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff071807 */
/* 0x000fca0004000000 */
/*0530*/ STG.E.U8 [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101104 */
/*0540*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0550*/ BRA 0x550; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // CudaGameOfLife.Program
extern "C" __global__ void RunGeneration( bool* cells1, int cells1Len0, int cells1Len1, bool* cells2, int cells2Len0, int cells2Len1);
// CudaGameOfLife.Program
__device__ bool CheckCell( bool* cells1, int cells1Len0, int cells1Len1, int x, int y);
// CudaGameOfLife.Program
__device__ bool IsAlive( bool* cells1, int cells1Len0, int cells1Len1, int i, int x, int y);
// CudaGameOfLife.Program
__device__ int GetSurroundingCount( bool* cells1, int cells1Len0, int cells1Len1, int x, int y);
// CudaGameOfLife.Program
__device__ bool GetTL(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetTC(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetTR(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetL(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetR(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetBL(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetBC(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetBR(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
extern "C" __global__ void RunGeneration( bool* cells1, int cells1Len0, int cells1Len1, bool* cells2, int cells2Len0, int cells2Len1)
{
int x = blockIdx.x;
int y = blockIdx.y;
cells2[(x) * cells2Len1 + ( y)] = CheckCell(cells1, cells1Len0, cells1Len1, x, y);
}
// CudaGameOfLife.Program
__device__ bool CheckCell( bool* cells1, int cells1Len0, int cells1Len1, int x, int y)
{
int surroundingCount = GetSurroundingCount(cells1, cells1Len0, cells1Len1, x, y);
return IsAlive(cells1, cells1Len0, cells1Len1, surroundingCount, x, y);
}
// CudaGameOfLife.Program
__device__ bool IsAlive( bool* cells1, int cells1Len0, int cells1Len1, int i, int x, int y)
{
return i == 3 || (cells1[(x) * cells1Len1 + ( y)] && i == 2);
}
// CudaGameOfLife.Program
__device__ int GetSurroundingCount( bool* cells1, int cells1Len0, int cells1Len1, int x, int y)
{
int num = 0;
if (GetTL(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetTC(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetTR(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetL(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetR(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetBL(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetBC(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetBR(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
return num;
}
// CudaGameOfLife.Program
__device__ bool GetTL(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (x == 0)
{
x = 999;
}
else
{
x--;
}
if (y == 0)
{
y = 999;
}
else
{
y--;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetTC(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (y == 0)
{
y = 999;
}
else
{
y--;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetTR(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (x == 999)
{
x = 0;
}
else
{
x++;
}
if (y == 0)
{
y = 999;
}
else
{
y--;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetL(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (x == 0)
{
x = 999;
}
else
{
x--;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetR(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (x == 999)
{
x = 0;
}
else
{
x++;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetBL(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (x == 0)
{
x = 999;
}
else
{
x--;
}
if (y == 999)
{
y = 0;
}
else
{
y++;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetBC(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (y == 999)
{
y = 0;
}
else
{
y++;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetBR(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (x == 999)
{
x = 0;
}
else
{
x++;
}
if (y == 999)
{
y = 0;
}
else
{
y++;
}
return cells[(x) * cellsLen1 + ( y)];
} | .file "tmpxft_000896ab_00000000-6_CUDAFYSOURCETEMP.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2040:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2040:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9CheckCellPbiiii
.type _Z9CheckCellPbiiii, @function
_Z9CheckCellPbiiii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z9CheckCellPbiiii, .-_Z9CheckCellPbiiii
.globl _Z7IsAlivePbiiiii
.type _Z7IsAlivePbiiiii, @function
_Z7IsAlivePbiiiii:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z7IsAlivePbiiiii, .-_Z7IsAlivePbiiiii
.globl _Z19GetSurroundingCountPbiiii
.type _Z19GetSurroundingCountPbiiii, @function
_Z19GetSurroundingCountPbiiii:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z19GetSurroundingCountPbiiii, .-_Z19GetSurroundingCountPbiiii
.globl _Z5GetTLiiPbii
.type _Z5GetTLiiPbii, @function
_Z5GetTLiiPbii:
.LFB2030:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2030:
.size _Z5GetTLiiPbii, .-_Z5GetTLiiPbii
.globl _Z5GetTCiiPbii
.type _Z5GetTCiiPbii, @function
_Z5GetTCiiPbii:
.LFB2031:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2031:
.size _Z5GetTCiiPbii, .-_Z5GetTCiiPbii
.globl _Z5GetTRiiPbii
.type _Z5GetTRiiPbii, @function
_Z5GetTRiiPbii:
.LFB2032:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2032:
.size _Z5GetTRiiPbii, .-_Z5GetTRiiPbii
.globl _Z4GetLiiPbii
.type _Z4GetLiiPbii, @function
_Z4GetLiiPbii:
.LFB2033:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2033:
.size _Z4GetLiiPbii, .-_Z4GetLiiPbii
.globl _Z4GetRiiPbii
.type _Z4GetRiiPbii, @function
_Z4GetRiiPbii:
.LFB2034:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2034:
.size _Z4GetRiiPbii, .-_Z4GetRiiPbii
.globl _Z5GetBLiiPbii
.type _Z5GetBLiiPbii, @function
_Z5GetBLiiPbii:
.LFB2035:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2035:
.size _Z5GetBLiiPbii, .-_Z5GetBLiiPbii
.globl _Z5GetBCiiPbii
.type _Z5GetBCiiPbii, @function
_Z5GetBCiiPbii:
.LFB2036:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2036:
.size _Z5GetBCiiPbii, .-_Z5GetBCiiPbii
.globl _Z5GetBRiiPbii
.type _Z5GetBRiiPbii, @function
_Z5GetBRiiPbii:
.LFB2037:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2037:
.size _Z5GetBRiiPbii, .-_Z5GetBRiiPbii
.globl _Z39__device_stub__Z13RunGenerationPbiiS_iiPbiiS_ii
.type _Z39__device_stub__Z13RunGenerationPbiiS_iiPbiiS_ii, @function
_Z39__device_stub__Z13RunGenerationPbiiS_iiPbiiS_ii:
.LFB2062:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq RunGeneration(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size _Z39__device_stub__Z13RunGenerationPbiiS_iiPbiiS_ii, .-_Z39__device_stub__Z13RunGenerationPbiiS_iiPbiiS_ii
.globl RunGeneration
.type RunGeneration, @function
RunGeneration:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z13RunGenerationPbiiS_iiPbiiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size RunGeneration, .-RunGeneration
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "RunGeneration"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq RunGeneration(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // CudaGameOfLife.Program
extern "C" __global__ void RunGeneration( bool* cells1, int cells1Len0, int cells1Len1, bool* cells2, int cells2Len0, int cells2Len1);
// CudaGameOfLife.Program
__device__ bool CheckCell( bool* cells1, int cells1Len0, int cells1Len1, int x, int y);
// CudaGameOfLife.Program
__device__ bool IsAlive( bool* cells1, int cells1Len0, int cells1Len1, int i, int x, int y);
// CudaGameOfLife.Program
__device__ int GetSurroundingCount( bool* cells1, int cells1Len0, int cells1Len1, int x, int y);
// CudaGameOfLife.Program
__device__ bool GetTL(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetTC(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetTR(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetL(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetR(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetBL(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetBC(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetBR(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
extern "C" __global__ void RunGeneration( bool* cells1, int cells1Len0, int cells1Len1, bool* cells2, int cells2Len0, int cells2Len1)
{
int x = blockIdx.x;
int y = blockIdx.y;
cells2[(x) * cells2Len1 + ( y)] = CheckCell(cells1, cells1Len0, cells1Len1, x, y);
}
// CudaGameOfLife.Program
__device__ bool CheckCell( bool* cells1, int cells1Len0, int cells1Len1, int x, int y)
{
int surroundingCount = GetSurroundingCount(cells1, cells1Len0, cells1Len1, x, y);
return IsAlive(cells1, cells1Len0, cells1Len1, surroundingCount, x, y);
}
// CudaGameOfLife.Program
__device__ bool IsAlive( bool* cells1, int cells1Len0, int cells1Len1, int i, int x, int y)
{
return i == 3 || (cells1[(x) * cells1Len1 + ( y)] && i == 2);
}
// CudaGameOfLife.Program
__device__ int GetSurroundingCount( bool* cells1, int cells1Len0, int cells1Len1, int x, int y)
{
int num = 0;
if (GetTL(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetTC(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetTR(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetL(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetR(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetBL(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetBC(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetBR(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
return num;
}
// CudaGameOfLife.Program
__device__ bool GetTL(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (x == 0)
{
x = 999;
}
else
{
x--;
}
if (y == 0)
{
y = 999;
}
else
{
y--;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetTC(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (y == 0)
{
y = 999;
}
else
{
y--;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetTR(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (x == 999)
{
x = 0;
}
else
{
x++;
}
if (y == 0)
{
y = 999;
}
else
{
y--;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetL(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (x == 0)
{
x = 999;
}
else
{
x--;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetR(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (x == 999)
{
x = 0;
}
else
{
x++;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetBL(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (x == 0)
{
x = 999;
}
else
{
x--;
}
if (y == 999)
{
y = 0;
}
else
{
y++;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetBC(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (y == 999)
{
y = 0;
}
else
{
y++;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetBR(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (x == 999)
{
x = 0;
}
else
{
x++;
}
if (y == 999)
{
y = 0;
}
else
{
y++;
}
return cells[(x) * cellsLen1 + ( y)];
} | #include <hip/hip_runtime.h>
// CudaGameOfLife.Program
extern "C" __global__ void RunGeneration( bool* cells1, int cells1Len0, int cells1Len1, bool* cells2, int cells2Len0, int cells2Len1);
// CudaGameOfLife.Program
__device__ bool CheckCell( bool* cells1, int cells1Len0, int cells1Len1, int x, int y);
// CudaGameOfLife.Program
__device__ bool IsAlive( bool* cells1, int cells1Len0, int cells1Len1, int i, int x, int y);
// CudaGameOfLife.Program
__device__ int GetSurroundingCount( bool* cells1, int cells1Len0, int cells1Len1, int x, int y);
// CudaGameOfLife.Program
__device__ bool GetTL(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetTC(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetTR(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetL(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetR(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetBL(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetBC(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetBR(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
extern "C" __global__ void RunGeneration( bool* cells1, int cells1Len0, int cells1Len1, bool* cells2, int cells2Len0, int cells2Len1)
{
int x = blockIdx.x;
int y = blockIdx.y;
cells2[(x) * cells2Len1 + ( y)] = CheckCell(cells1, cells1Len0, cells1Len1, x, y);
}
// CudaGameOfLife.Program
__device__ bool CheckCell( bool* cells1, int cells1Len0, int cells1Len1, int x, int y)
{
int surroundingCount = GetSurroundingCount(cells1, cells1Len0, cells1Len1, x, y);
return IsAlive(cells1, cells1Len0, cells1Len1, surroundingCount, x, y);
}
// CudaGameOfLife.Program
__device__ bool IsAlive( bool* cells1, int cells1Len0, int cells1Len1, int i, int x, int y)
{
return i == 3 || (cells1[(x) * cells1Len1 + ( y)] && i == 2);
}
// CudaGameOfLife.Program
__device__ int GetSurroundingCount( bool* cells1, int cells1Len0, int cells1Len1, int x, int y)
{
int num = 0;
if (GetTL(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetTC(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetTR(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetL(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetR(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetBL(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetBC(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetBR(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
return num;
}
// CudaGameOfLife.Program
__device__ bool GetTL(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (x == 0)
{
x = 999;
}
else
{
x--;
}
if (y == 0)
{
y = 999;
}
else
{
y--;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetTC(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (y == 0)
{
y = 999;
}
else
{
y--;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetTR(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (x == 999)
{
x = 0;
}
else
{
x++;
}
if (y == 0)
{
y = 999;
}
else
{
y--;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetL(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (x == 0)
{
x = 999;
}
else
{
x--;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetR(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (x == 999)
{
x = 0;
}
else
{
x++;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetBL(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (x == 0)
{
x = 999;
}
else
{
x--;
}
if (y == 999)
{
y = 0;
}
else
{
y++;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetBC(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (y == 999)
{
y = 0;
}
else
{
y++;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetBR(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (x == 999)
{
x = 0;
}
else
{
x++;
}
if (y == 999)
{
y = 0;
}
else
{
y++;
}
return cells[(x) * cellsLen1 + ( y)];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// CudaGameOfLife.Program
extern "C" __global__ void RunGeneration( bool* cells1, int cells1Len0, int cells1Len1, bool* cells2, int cells2Len0, int cells2Len1);
// CudaGameOfLife.Program
__device__ bool CheckCell( bool* cells1, int cells1Len0, int cells1Len1, int x, int y);
// CudaGameOfLife.Program
__device__ bool IsAlive( bool* cells1, int cells1Len0, int cells1Len1, int i, int x, int y);
// CudaGameOfLife.Program
__device__ int GetSurroundingCount( bool* cells1, int cells1Len0, int cells1Len1, int x, int y);
// CudaGameOfLife.Program
__device__ bool GetTL(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetTC(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetTR(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetL(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetR(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetBL(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetBC(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetBR(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
extern "C" __global__ void RunGeneration( bool* cells1, int cells1Len0, int cells1Len1, bool* cells2, int cells2Len0, int cells2Len1)
{
int x = blockIdx.x;
int y = blockIdx.y;
cells2[(x) * cells2Len1 + ( y)] = CheckCell(cells1, cells1Len0, cells1Len1, x, y);
}
// CudaGameOfLife.Program
__device__ bool CheckCell( bool* cells1, int cells1Len0, int cells1Len1, int x, int y)
{
int surroundingCount = GetSurroundingCount(cells1, cells1Len0, cells1Len1, x, y);
return IsAlive(cells1, cells1Len0, cells1Len1, surroundingCount, x, y);
}
// CudaGameOfLife.Program
__device__ bool IsAlive( bool* cells1, int cells1Len0, int cells1Len1, int i, int x, int y)
{
return i == 3 || (cells1[(x) * cells1Len1 + ( y)] && i == 2);
}
// CudaGameOfLife.Program
__device__ int GetSurroundingCount( bool* cells1, int cells1Len0, int cells1Len1, int x, int y)
{
int num = 0;
if (GetTL(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetTC(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetTR(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetL(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetR(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetBL(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetBC(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetBR(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
return num;
}
// CudaGameOfLife.Program
__device__ bool GetTL(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (x == 0)
{
x = 999;
}
else
{
x--;
}
if (y == 0)
{
y = 999;
}
else
{
y--;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetTC(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (y == 0)
{
y = 999;
}
else
{
y--;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetTR(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (x == 999)
{
x = 0;
}
else
{
x++;
}
if (y == 0)
{
y = 999;
}
else
{
y--;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetL(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (x == 0)
{
x = 999;
}
else
{
x--;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetR(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (x == 999)
{
x = 0;
}
else
{
x++;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetBL(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (x == 0)
{
x = 999;
}
else
{
x--;
}
if (y == 999)
{
y = 0;
}
else
{
y++;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetBC(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (y == 999)
{
y = 0;
}
else
{
y++;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetBR(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (x == 999)
{
x = 0;
}
else
{
x++;
}
if (y == 999)
{
y = 0;
}
else
{
y++;
}
return cells[(x) * cellsLen1 + ( y)];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected RunGeneration
.globl RunGeneration
.p2align 8
.type RunGeneration,@function
RunGeneration:
s_clause 0x1
s_load_b32 s5, s[0:1], 0xc
s_load_b64 s[2:3], s[0:1], 0x0
s_add_i32 s4, s14, -1
s_cmp_lg_u32 s14, 0
v_mov_b32_e32 v0, 0
s_cselect_b32 s4, s4, 0x3e7
s_add_i32 s6, s15, -1
s_cmp_lg_u32 s15, 0
s_cselect_b32 s10, s6, 0x3e7
s_waitcnt lgkmcnt(0)
s_mul_i32 s16, s4, s5
s_mul_i32 s4, s14, s5
s_add_i32 s6, s16, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_ashr_i32 s7, s6, 31
s_add_u32 s6, s2, s6
s_addc_u32 s7, s3, s7
s_add_i32 s8, s4, s10
s_ashr_i32 s9, s8, 31
s_add_u32 s8, s2, s8
s_addc_u32 s9, s3, s9
s_clause 0x1
global_load_u8 v1, v0, s[6:7]
global_load_u8 v2, v0, s[8:9]
s_add_i32 s11, s14, 1
s_cmpk_lg_i32 s14, 0x3e7
s_cselect_b32 s11, s11, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s5, s11, s5
s_add_i32 s10, s5, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_ashr_i32 s11, s10, 31
s_add_u32 s10, s2, s10
s_addc_u32 s11, s3, s11
s_add_i32 s12, s16, s15
s_ashr_i32 s13, s12, 31
s_add_u32 s12, s2, s12
s_addc_u32 s13, s3, s13
s_add_i32 s6, s5, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s7, s6, 31
s_add_u32 s6, s2, s6
s_addc_u32 s7, s3, s7
s_add_i32 s8, s15, 1
s_cmpk_lg_i32 s15, 0x3e7
s_cselect_b32 s8, s8, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s16, s16, s8
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
s_clause 0x2
global_load_u8 v3, v0, s[10:11]
global_load_u8 v5, v0, s[6:7]
global_load_u8 v4, v0, s[12:13]
s_ashr_i32 s7, s16, 31
s_add_u32 s6, s2, s16
s_addc_u32 s7, s3, s7
s_add_i32 s9, s4, s8
global_load_u8 v6, v0, s[6:7]
s_ashr_i32 s7, s9, 31
s_add_u32 s6, s2, s9
s_addc_u32 s7, s3, s7
s_add_i32 s5, s5, s8
global_load_u8 v7, v0, s[6:7]
s_ashr_i32 s7, s5, 31
s_add_u32 s6, s2, s5
s_addc_u32 s7, s3, s7
s_mov_b32 s5, -1
global_load_u8 v8, v0, s[6:7]
s_waitcnt vmcnt(5)
v_add_nc_u32_e32 v1, v1, v3
s_waitcnt vmcnt(3)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v4
v_add_nc_u32_e32 v1, v1, v5
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v6
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v1, v1, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, 0xff, v1
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v1, v8
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, 3, v1
s_cbranch_vccnz .LBB0_2
s_add_i32 s4, s4, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s5, s4, 31
s_add_u32 s2, s2, s4
s_addc_u32 s3, s3, s5
global_load_u8 v2, v0, s[2:3]
v_cmp_eq_u32_e64 s2, 2, v1
s_waitcnt vmcnt(0)
v_cmp_ne_u16_e32 vcc_lo, 0, v2
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s5, s2, vcc_lo
.LBB0_2:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x10
v_cndmask_b32_e64 v1, 0, 1, s5
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s14, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s15
s_ashr_i32 s3, s2, 31
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b8 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel RunGeneration
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size RunGeneration, .Lfunc_end0-RunGeneration
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: RunGeneration
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: RunGeneration.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// CudaGameOfLife.Program
extern "C" __global__ void RunGeneration( bool* cells1, int cells1Len0, int cells1Len1, bool* cells2, int cells2Len0, int cells2Len1);
// CudaGameOfLife.Program
__device__ bool CheckCell( bool* cells1, int cells1Len0, int cells1Len1, int x, int y);
// CudaGameOfLife.Program
__device__ bool IsAlive( bool* cells1, int cells1Len0, int cells1Len1, int i, int x, int y);
// CudaGameOfLife.Program
__device__ int GetSurroundingCount( bool* cells1, int cells1Len0, int cells1Len1, int x, int y);
// CudaGameOfLife.Program
__device__ bool GetTL(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetTC(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetTR(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetL(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetR(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetBL(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetBC(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
__device__ bool GetBR(int x, int y, bool* cells, int cellsLen0, int cellsLen1);
// CudaGameOfLife.Program
extern "C" __global__ void RunGeneration( bool* cells1, int cells1Len0, int cells1Len1, bool* cells2, int cells2Len0, int cells2Len1)
{
int x = blockIdx.x;
int y = blockIdx.y;
cells2[(x) * cells2Len1 + ( y)] = CheckCell(cells1, cells1Len0, cells1Len1, x, y);
}
// CudaGameOfLife.Program
__device__ bool CheckCell( bool* cells1, int cells1Len0, int cells1Len1, int x, int y)
{
int surroundingCount = GetSurroundingCount(cells1, cells1Len0, cells1Len1, x, y);
return IsAlive(cells1, cells1Len0, cells1Len1, surroundingCount, x, y);
}
// CudaGameOfLife.Program
__device__ bool IsAlive( bool* cells1, int cells1Len0, int cells1Len1, int i, int x, int y)
{
return i == 3 || (cells1[(x) * cells1Len1 + ( y)] && i == 2);
}
// CudaGameOfLife.Program
__device__ int GetSurroundingCount( bool* cells1, int cells1Len0, int cells1Len1, int x, int y)
{
int num = 0;
if (GetTL(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetTC(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetTR(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetL(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetR(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetBL(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetBC(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
if (GetBR(x, y, cells1, cells1Len0, cells1Len1))
{
num++;
}
return num;
}
// CudaGameOfLife.Program
__device__ bool GetTL(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (x == 0)
{
x = 999;
}
else
{
x--;
}
if (y == 0)
{
y = 999;
}
else
{
y--;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetTC(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (y == 0)
{
y = 999;
}
else
{
y--;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetTR(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (x == 999)
{
x = 0;
}
else
{
x++;
}
if (y == 0)
{
y = 999;
}
else
{
y--;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetL(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (x == 0)
{
x = 999;
}
else
{
x--;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetR(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (x == 999)
{
x = 0;
}
else
{
x++;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetBL(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (x == 0)
{
x = 999;
}
else
{
x--;
}
if (y == 999)
{
y = 0;
}
else
{
y++;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetBC(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (y == 999)
{
y = 0;
}
else
{
y++;
}
return cells[(x) * cellsLen1 + ( y)];
}
// CudaGameOfLife.Program
__device__ bool GetBR(int x, int y, bool* cells, int cellsLen0, int cellsLen1)
{
if (x == 999)
{
x = 0;
}
else
{
x++;
}
if (y == 999)
{
y = 0;
}
else
{
y++;
}
return cells[(x) * cellsLen1 + ( y)];
} | .text
.file "CUDAFYSOURCETEMP.hip"
.globl __device_stub__RunGeneration # -- Begin function __device_stub__RunGeneration
.p2align 4, 0x90
.type __device_stub__RunGeneration,@function
__device_stub__RunGeneration: # @__device_stub__RunGeneration
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $RunGeneration, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size __device_stub__RunGeneration, .Lfunc_end0-__device_stub__RunGeneration
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $RunGeneration, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type RunGeneration,@object # @RunGeneration
.section .rodata,"a",@progbits
.globl RunGeneration
.p2align 3, 0x0
RunGeneration:
.quad __device_stub__RunGeneration
.size RunGeneration, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "RunGeneration"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__RunGeneration
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym RunGeneration
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : RunGeneration
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e620000002500 */
/*0040*/ ISETP.NE.AND P1, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720c */
/* 0x041fe40003f25270 */
/*0050*/ IADD3 R4, R3, -0x1, RZ ; /* 0xffffffff03047810 */
/* 0x000fe40007ffe0ff */
/*0060*/ ISETP.NE.AND P0, PT, R0.reuse, RZ, PT ; /* 0x000000ff0000720c */
/* 0x042fe40003f05270 */
/*0070*/ IADD3 R2, R0, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x000fe40007ffe0ff */
/*0080*/ SEL R5, R4, 0x3e7, P1 ; /* 0x000003e704057807 */
/* 0x000fe40000800000 */
/*0090*/ SEL R16, R2, 0x3e7, P0 ; /* 0x000003e702107807 */
/* 0x000fc40000000000 */
/*00a0*/ ISETP.NE.AND P0, PT, R0.reuse, 0x3e7, PT ; /* 0x000003e70000780c */
/* 0x040fe20003f05270 */
/*00b0*/ IMAD R6, R0.reuse, c[0x0][0x16c], R5.reuse ; /* 0x00005b0000067a24 */
/* 0x140fe200078e0205 */
/*00c0*/ IADD3 R2, R0, 0x1, RZ ; /* 0x0000000100027810 */
/* 0x000fe20007ffe0ff */
/*00d0*/ IMAD R4, R16, c[0x0][0x16c], R5 ; /* 0x00005b0010047a24 */
/* 0x000fc600078e0205 */
/*00e0*/ SEL R2, R2, RZ, P0 ; /* 0x000000ff02027207 */
/* 0x000fe40000000000 */
/*00f0*/ IADD3 R10, P0, R6, c[0x0][0x160], RZ ; /* 0x00005800060a7a10 */
/* 0x000fe40007f1e0ff */
/*0100*/ IADD3 R8, P1, R4, c[0x0][0x160], RZ ; /* 0x0000580004087a10 */
/* 0x000fe20007f3e0ff */
/*0110*/ IMAD R5, R2, c[0x0][0x16c], R5 ; /* 0x00005b0002057a24 */
/* 0x000fe200078e0205 */
/*0120*/ LEA.HI.X.SX32 R11, R6, c[0x0][0x164], 0x1, P0 ; /* 0x00005900060b7a11 */
/* 0x000fe200000f0eff */
/*0130*/ IMAD R14, R16, c[0x0][0x16c], R3 ; /* 0x00005b00100e7a24 */
/* 0x000fe200078e0203 */
/*0140*/ LEA.HI.X.SX32 R9, R4, c[0x0][0x164], 0x1, P1 ; /* 0x0000590004097a11 */
/* 0x000fc600008f0eff */
/*0150*/ LDG.E.U8 R7, [R10.64] ; /* 0x000000040a077981 */
/* 0x0000a2000c1e1100 */
/*0160*/ IADD3 R12, P1, R5, c[0x0][0x160], RZ ; /* 0x00005800050c7a10 */
/* 0x000fe40007f3e0ff */
/*0170*/ ISETP.NE.AND P0, PT, R3.reuse, 0x3e7, PT ; /* 0x000003e70300780c */
/* 0x040fe20003f05270 */
/*0180*/ LDG.E.U8 R6, [R8.64] ; /* 0x0000000408067981 */
/* 0x0002e2000c1e1100 */
/*0190*/ IADD3 R17, R3, 0x1, RZ ; /* 0x0000000103117810 */
/* 0x000fe40007ffe0ff */
/*01a0*/ IADD3 R4, P2, R14, c[0x0][0x160], RZ ; /* 0x000058000e047a10 */
/* 0x000fe20007f5e0ff */
/*01b0*/ IMAD R15, R2, c[0x0][0x16c], R3 ; /* 0x00005b00020f7a24 */
/* 0x000fe200078e0203 */
/*01c0*/ LEA.HI.X.SX32 R13, R5, c[0x0][0x164], 0x1, P1 ; /* 0x00005900050d7a11 */
/* 0x000fe400008f0eff */
/*01d0*/ LEA.HI.X.SX32 R5, R14, c[0x0][0x164], 0x1, P2 ; /* 0x000059000e057a11 */
/* 0x000fc400010f0eff */
/*01e0*/ SEL R19, R17, RZ, P0 ; /* 0x000000ff11137207 */
/* 0x000fe20000000000 */
/*01f0*/ LDG.E.U8 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f22000c1e1100 */
/*0200*/ IADD3 R14, P0, R15, c[0x0][0x160], RZ ; /* 0x000058000f0e7a10 */
/* 0x000fc60007f1e0ff */
/*0210*/ LDG.E.U8 R17, [R4.64] ; /* 0x0000000404117981 */
/* 0x000b22000c1e1100 */
/*0220*/ IMAD R16, R16, c[0x0][0x16c], R19.reuse ; /* 0x00005b0010107a24 */
/* 0x100fe200078e0213 */
/*0230*/ LEA.HI.X.SX32 R15, R15, c[0x0][0x164], 0x1, P0 ; /* 0x000059000f0f7a11 */
/* 0x000fe200000f0eff */
/*0240*/ IMAD R9, R0, c[0x0][0x16c], R19 ; /* 0x00005b0000097a24 */
/* 0x002fc600078e0213 */
/*0250*/ IADD3 R10, P0, R16.reuse, c[0x0][0x160], RZ ; /* 0x00005800100a7a10 */
/* 0x041fe20007f1e0ff */
/*0260*/ LDG.E.U8 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f26000c1e1100 */
/*0270*/ LEA.HI.X.SX32 R11, R16, c[0x0][0x164], 0x1, P0 ; /* 0x00005900100b7a11 */
/* 0x000fe200000f0eff */
/*0280*/ IMAD R2, R2, c[0x0][0x16c], R19 ; /* 0x00005b0002027a24 */
/* 0x000fe200078e0213 */
/*0290*/ IADD3 R8, P0, R9, c[0x0][0x160], RZ ; /* 0x0000580009087a10 */
/* 0x000fc60007f1e0ff */
/*02a0*/ LDG.E.U8 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f22000c1e1100 */
/*02b0*/ LEA.HI.X.SX32 R9, R9, c[0x0][0x164], 0x1, P0 ; /* 0x0000590009097a11 */
/* 0x000fe400000f0eff */
/*02c0*/ IADD3 R4, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x020fc60007f1e0ff */
/*02d0*/ LDG.E.U8 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f62000c1e1100 */
/*02e0*/ LEA.HI.X.SX32 R5, R2, c[0x0][0x164], 0x1, P0 ; /* 0x0000590002057a11 */
/* 0x000fca00000f0eff */
/*02f0*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000162000c1e1100 */
/*0300*/ ISETP.NE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x004fe40003f45270 */
/*0310*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x008fe20003f25270 */
/*0320*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fc600078e00ff */
/*0330*/ SEL R2, RZ, 0x1, !P1 ; /* 0x00000001ff027807 */
/* 0x000fce0004800000 */
/*0340*/ @P2 SEL R2, R6, 0x2, !P1 ; /* 0x0000000206022807 */
/* 0x000fe40004800000 */
/*0350*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x010fe40003f05270 */
/*0360*/ ISETP.NE.AND P1, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fe40003f25270 */
/*0370*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fca0004000000 */
/*0380*/ IMAD.IADD R2, R2, 0x1, R7 ; /* 0x0000000102027824 */
/* 0x000fe200078e0207 */
/*0390*/ ISETP.NE.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fc80003f05270 */
/*03a0*/ IADD3 R5, R2, 0x1, RZ ; /* 0x0000000102057810 */
/* 0x001fe20007ffe0ff */
/*03b0*/ @!P1 IMAD.MOV R5, RZ, RZ, R2 ; /* 0x000000ffff059224 */
/* 0x000fe200078e0202 */
/*03c0*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc80003f25270 */
/*03d0*/ IADD3 R2, R5, 0x1, RZ ; /* 0x0000000105027810 */
/* 0x000fc60007ffe0ff */
/*03e0*/ @!P0 IMAD.MOV R2, RZ, RZ, R5 ; /* 0x000000ffff028224 */
/* 0x000fe200078e0205 */
/*03f0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x020fc80003f05270 */
/*0400*/ IADD3 R5, R2, 0x1, RZ ; /* 0x0000000102057810 */
/* 0x000fe20007ffe0ff */
/*0410*/ @!P1 IMAD.MOV R5, RZ, RZ, R2 ; /* 0x000000ffff059224 */
/* 0x000fe200078e0202 */
/*0420*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc80003f25270 */
/*0430*/ IADD3 R2, R5, 0x1, RZ ; /* 0x0000000105027810 */
/* 0x000fc60007ffe0ff */
/*0440*/ @!P0 IMAD.MOV R2, RZ, RZ, R5 ; /* 0x000000ffff028224 */
/* 0x000fca00078e0205 */
/*0450*/ IADD3 R6, R2, 0x1, RZ ; /* 0x0000000102067810 */
/* 0x000fe20007ffe0ff */
/*0460*/ @!P1 IMAD.MOV R6, RZ, RZ, R2 ; /* 0x000000ffff069224 */
/* 0x000fca00078e0202 */
/*0470*/ ISETP.NE.AND P1, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fda0003f25270 */
/*0480*/ @P1 IMAD R2, R0, c[0x0][0x16c], R3 ; /* 0x00005b0000021a24 */
/* 0x000fca00078e0203 */
/*0490*/ @P1 IADD3 R4, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002041a10 */
/* 0x000fc80007f1e0ff */
/*04a0*/ @P1 LEA.HI.X.SX32 R5, R2, c[0x0][0x164], 0x1, P0 ; /* 0x0000590002051a11 */
/* 0x000fca00000f0eff */
/*04b0*/ @P1 LDG.E.U8 R4, [R4.64] ; /* 0x0000000404041981 */
/* 0x000ea2000c1e1100 */
/*04c0*/ IMAD R0, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000007a24 */
/* 0x000fe400078e0203 */
/*04d0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fc600078e00ff */
/*04e0*/ IADD3 R2, P2, R0, c[0x0][0x170], RZ ; /* 0x00005c0000027a10 */
/* 0x000fc80007f5e0ff */
/*04f0*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x174], 0x1, P2 ; /* 0x00005d0000037a11 */
/* 0x000fe400010f0eff */
/*0500*/ @P1 ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400120c */
/* 0x004fc80003f05270 */
/*0510*/ @P1 ISETP.EQ.AND P0, PT, R6, 0x2, P0 ; /* 0x000000020600180c */
/* 0x000fc80000702270 */
/*0520*/ @P1 SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff071807 */
/* 0x000fca0004000000 */
/*0530*/ STG.E.U8 [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101104 */
/*0540*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0550*/ BRA 0x550; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected RunGeneration
.globl RunGeneration
.p2align 8
.type RunGeneration,@function
RunGeneration:
s_clause 0x1
s_load_b32 s5, s[0:1], 0xc
s_load_b64 s[2:3], s[0:1], 0x0
s_add_i32 s4, s14, -1
s_cmp_lg_u32 s14, 0
v_mov_b32_e32 v0, 0
s_cselect_b32 s4, s4, 0x3e7
s_add_i32 s6, s15, -1
s_cmp_lg_u32 s15, 0
s_cselect_b32 s10, s6, 0x3e7
s_waitcnt lgkmcnt(0)
s_mul_i32 s16, s4, s5
s_mul_i32 s4, s14, s5
s_add_i32 s6, s16, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_ashr_i32 s7, s6, 31
s_add_u32 s6, s2, s6
s_addc_u32 s7, s3, s7
s_add_i32 s8, s4, s10
s_ashr_i32 s9, s8, 31
s_add_u32 s8, s2, s8
s_addc_u32 s9, s3, s9
s_clause 0x1
global_load_u8 v1, v0, s[6:7]
global_load_u8 v2, v0, s[8:9]
s_add_i32 s11, s14, 1
s_cmpk_lg_i32 s14, 0x3e7
s_cselect_b32 s11, s11, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s5, s11, s5
s_add_i32 s10, s5, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_ashr_i32 s11, s10, 31
s_add_u32 s10, s2, s10
s_addc_u32 s11, s3, s11
s_add_i32 s12, s16, s15
s_ashr_i32 s13, s12, 31
s_add_u32 s12, s2, s12
s_addc_u32 s13, s3, s13
s_add_i32 s6, s5, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s7, s6, 31
s_add_u32 s6, s2, s6
s_addc_u32 s7, s3, s7
s_add_i32 s8, s15, 1
s_cmpk_lg_i32 s15, 0x3e7
s_cselect_b32 s8, s8, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s16, s16, s8
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
s_clause 0x2
global_load_u8 v3, v0, s[10:11]
global_load_u8 v5, v0, s[6:7]
global_load_u8 v4, v0, s[12:13]
s_ashr_i32 s7, s16, 31
s_add_u32 s6, s2, s16
s_addc_u32 s7, s3, s7
s_add_i32 s9, s4, s8
global_load_u8 v6, v0, s[6:7]
s_ashr_i32 s7, s9, 31
s_add_u32 s6, s2, s9
s_addc_u32 s7, s3, s7
s_add_i32 s5, s5, s8
global_load_u8 v7, v0, s[6:7]
s_ashr_i32 s7, s5, 31
s_add_u32 s6, s2, s5
s_addc_u32 s7, s3, s7
s_mov_b32 s5, -1
global_load_u8 v8, v0, s[6:7]
s_waitcnt vmcnt(5)
v_add_nc_u32_e32 v1, v1, v3
s_waitcnt vmcnt(3)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v4
v_add_nc_u32_e32 v1, v1, v5
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v6
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v1, v1, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, 0xff, v1
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v1, v8
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, 3, v1
s_cbranch_vccnz .LBB0_2
s_add_i32 s4, s4, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s5, s4, 31
s_add_u32 s2, s2, s4
s_addc_u32 s3, s3, s5
global_load_u8 v2, v0, s[2:3]
v_cmp_eq_u32_e64 s2, 2, v1
s_waitcnt vmcnt(0)
v_cmp_ne_u16_e32 vcc_lo, 0, v2
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s5, s2, vcc_lo
.LBB0_2:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x10
v_cndmask_b32_e64 v1, 0, 1, s5
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s14, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s15
s_ashr_i32 s3, s2, 31
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b8 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel RunGeneration
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size RunGeneration, .Lfunc_end0-RunGeneration
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: RunGeneration
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: RunGeneration.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000896ab_00000000-6_CUDAFYSOURCETEMP.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2040:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2040:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9CheckCellPbiiii
.type _Z9CheckCellPbiiii, @function
_Z9CheckCellPbiiii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z9CheckCellPbiiii, .-_Z9CheckCellPbiiii
.globl _Z7IsAlivePbiiiii
.type _Z7IsAlivePbiiiii, @function
_Z7IsAlivePbiiiii:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z7IsAlivePbiiiii, .-_Z7IsAlivePbiiiii
.globl _Z19GetSurroundingCountPbiiii
.type _Z19GetSurroundingCountPbiiii, @function
_Z19GetSurroundingCountPbiiii:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z19GetSurroundingCountPbiiii, .-_Z19GetSurroundingCountPbiiii
.globl _Z5GetTLiiPbii
.type _Z5GetTLiiPbii, @function
_Z5GetTLiiPbii:
.LFB2030:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2030:
.size _Z5GetTLiiPbii, .-_Z5GetTLiiPbii
.globl _Z5GetTCiiPbii
.type _Z5GetTCiiPbii, @function
_Z5GetTCiiPbii:
.LFB2031:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2031:
.size _Z5GetTCiiPbii, .-_Z5GetTCiiPbii
.globl _Z5GetTRiiPbii
.type _Z5GetTRiiPbii, @function
_Z5GetTRiiPbii:
.LFB2032:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2032:
.size _Z5GetTRiiPbii, .-_Z5GetTRiiPbii
.globl _Z4GetLiiPbii
.type _Z4GetLiiPbii, @function
_Z4GetLiiPbii:
.LFB2033:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2033:
.size _Z4GetLiiPbii, .-_Z4GetLiiPbii
.globl _Z4GetRiiPbii
.type _Z4GetRiiPbii, @function
_Z4GetRiiPbii:
.LFB2034:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2034:
.size _Z4GetRiiPbii, .-_Z4GetRiiPbii
.globl _Z5GetBLiiPbii
.type _Z5GetBLiiPbii, @function
_Z5GetBLiiPbii:
.LFB2035:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2035:
.size _Z5GetBLiiPbii, .-_Z5GetBLiiPbii
.globl _Z5GetBCiiPbii
.type _Z5GetBCiiPbii, @function
_Z5GetBCiiPbii:
.LFB2036:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2036:
.size _Z5GetBCiiPbii, .-_Z5GetBCiiPbii
.globl _Z5GetBRiiPbii
.type _Z5GetBRiiPbii, @function
_Z5GetBRiiPbii:
.LFB2037:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2037:
.size _Z5GetBRiiPbii, .-_Z5GetBRiiPbii
.globl _Z39__device_stub__Z13RunGenerationPbiiS_iiPbiiS_ii
.type _Z39__device_stub__Z13RunGenerationPbiiS_iiPbiiS_ii, @function
_Z39__device_stub__Z13RunGenerationPbiiS_iiPbiiS_ii:
.LFB2062:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq RunGeneration(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size _Z39__device_stub__Z13RunGenerationPbiiS_iiPbiiS_ii, .-_Z39__device_stub__Z13RunGenerationPbiiS_iiPbiiS_ii
.globl RunGeneration
.type RunGeneration, @function
RunGeneration:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z13RunGenerationPbiiS_iiPbiiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size RunGeneration, .-RunGeneration
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "RunGeneration"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq RunGeneration(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "CUDAFYSOURCETEMP.hip"
.globl __device_stub__RunGeneration # -- Begin function __device_stub__RunGeneration
.p2align 4, 0x90
.type __device_stub__RunGeneration,@function
__device_stub__RunGeneration: # @__device_stub__RunGeneration
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $RunGeneration, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size __device_stub__RunGeneration, .Lfunc_end0-__device_stub__RunGeneration
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $RunGeneration, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type RunGeneration,@object # @RunGeneration
.section .rodata,"a",@progbits
.globl RunGeneration
.p2align 3, 0x0
RunGeneration:
.quad __device_stub__RunGeneration
.size RunGeneration, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "RunGeneration"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__RunGeneration
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym RunGeneration
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include <complex.h>
#include <cufft.h>
// Kernel used for assigning values to matrix.
__global__ void assign(int N, cufftDoubleComplex* a, cufftDoubleComplex* a_copy){
if (blockIdx.x < N && blockIdx.y < N){
a_copy[blockIdx.x+blockIdx.y*gridDim.x].x = a[blockIdx.x+blockIdx.y*gridDim.x].x;
a_copy[blockIdx.x+blockIdx.y*gridDim.x].y = a[blockIdx.x+blockIdx.y*gridDim.x].y;
}
}
// FFT shift kernel, works in GPU
__global__ void fftshift(int N, cufftDoubleComplex* a, cufftDoubleComplex* a_shift){
if (blockIdx.x < N/2 && blockIdx.y < N/2){
a_shift[blockIdx.x+blockIdx.y*gridDim.x].x = a[(blockIdx.x+N/2)+(blockIdx.y+N/2)*gridDim.x].x;
a_shift[blockIdx.x+blockIdx.y*gridDim.x].y = a[(blockIdx.x+N/2)+(blockIdx.y+N/2)*gridDim.x].y;
}
else if (blockIdx.x < N/2 && blockIdx.y >= N/2)
a_shift[blockIdx.x+blockIdx.y*gridDim.x] = a[(blockIdx.x+N/2)+(blockIdx.y-N/2)*gridDim.x];
else if (blockIdx.x >= N/2 && blockIdx.y < N/2)
a_shift[blockIdx.x+blockIdx.y*gridDim.x] = a[(blockIdx.x-N/2)+(blockIdx.y+N/2)*gridDim.x];
else if (blockIdx.x >= N/2 && blockIdx.y >= N/2)
a_shift[blockIdx.x+blockIdx.y*gridDim.x] = a[(blockIdx.x-N/2)+(blockIdx.y-N/2)*gridDim.x];
}
// Kernel used to compute 2nd derivative
__global__ void del2A(int N, cufftDoubleComplex* del2A_input, cufftDoubleComplex* del2A_output){
if (blockIdx.x < N && blockIdx.y < N){
del2A_output[blockIdx.x+blockIdx.y*gridDim.x].x =
(-((double)(blockIdx.x) + (double)(-N/2))*((double)(blockIdx.x) + (double)(-N/2))
-((double)(blockIdx.y) + (double)(-N/2))*((double)(blockIdx.y) + (double)(-N/2)))
*del2A_input[blockIdx.x+blockIdx.y*gridDim.x].x/N/N;
del2A_output[blockIdx.x+blockIdx.y*gridDim.x].y =
(-((double)(blockIdx.x) + (double)(-N/2))*((double)(blockIdx.x) + (double)(-N/2))
-((double)(blockIdx.y) + (double)(-N/2))*((double)(blockIdx.y) + (double)(-N/2)))
*del2A_input[blockIdx.x+blockIdx.y*gridDim.x].y/(N*N);
}
}
// Kernel used to update A, A1, A2 matrices using pointers to each matrix, with div used to decrement in time.
__global__ void update(int N, double dt, double c1, double c3, int div, double L, cufftDoubleComplex* A, cufftDoubleComplex* d2A, cufftDoubleComplex* A_new){
if (blockIdx.x < N && blockIdx.y < N){
A_new[blockIdx.x+blockIdx.y*gridDim.x].x = A[blockIdx.x+blockIdx.y*gridDim.x].x + dt/div*(A[blockIdx.x+blockIdx.y*gridDim.x].x
+ (d2A[blockIdx.x+blockIdx.y*gridDim.x].x - c1*d2A[blockIdx.x+blockIdx.y*gridDim.x].y)*(2*M_PI/L)*(2*M_PI/L)
- (A[blockIdx.x+blockIdx.y*gridDim.x].x + c3*A[blockIdx.x+blockIdx.y*gridDim.x].y)
*(A[blockIdx.x+blockIdx.y*gridDim.x].x*A[blockIdx.x+blockIdx.y*gridDim.x].x + A[blockIdx.x+blockIdx.y*gridDim.x].y*A[blockIdx.x+blockIdx.y*gridDim.x].y));
A_new[blockIdx.x+blockIdx.y*gridDim.x].y = A[blockIdx.x+blockIdx.y*gridDim.x].y + dt/div*(A[blockIdx.x+blockIdx.y*gridDim.x].y
+ (d2A[blockIdx.x+blockIdx.y*gridDim.x].y + c1*d2A[blockIdx.x+blockIdx.y*gridDim.x].x)*(2*M_PI/L)*(2*M_PI/L)
- (A[blockIdx.x+blockIdx.y*gridDim.x].y - c3*A[blockIdx.x+blockIdx.y*gridDim.x].x)
*(A[blockIdx.x+blockIdx.y*gridDim.x].x*A[blockIdx.x+blockIdx.y*gridDim.x].x + A[blockIdx.x+blockIdx.y*gridDim.x].y*A[blockIdx.x+blockIdx.y*gridDim.x].y));
}
}
int main(int argc, char* argv[]){
// Start runtime clock
clock_t start_time = clock();
// Set up args to be taken as inputs
ptrdiff_t N = atoi(argv[1]);
double c1 = atof(argv[2]);
double c3 = atof(argv[3]);
int M = atoi(argv[4]);
// Insure same seed is used for all processors
long int seed = (long int)time(NULL);
if (argc >= 6){
seed = atol(argv[5]);
}
srand48(seed);
// Define parameter values
double L = 128*M_PI;
int T = 10000;
double dt = (double)T/M;
int interval = N/10;
// Allocate memory within CPU
cufftDoubleComplex *sol = (cufftDoubleComplex*)malloc(N*N*sizeof(cufftDoubleComplex));
// Allocate memory within GPU
cufftDoubleComplex* A;
cudaMalloc((void**)&A, sizeof(cufftDoubleComplex)*N*N);
cufftDoubleComplex* A_temp;
cudaMalloc((void**)&A_temp, sizeof(cufftDoubleComplex)*N*N);
cufftDoubleComplex* del2A_output;
cudaMalloc((void**)&del2A_output, sizeof(cufftDoubleComplex)*N*N);
cufftDoubleComplex* del2A_temp;
cudaMalloc((void**)&del2A_temp, sizeof(cufftDoubleComplex)*N*N);
cufftDoubleComplex* del2A_shift;
cudaMalloc((void**)&del2A_shift, sizeof(cufftDoubleComplex)*N*N);
// Create and open target file
FILE *fileid = fopen("ComplexGL.out", "w");
// ICs
for (int i = 0; i < N; ++i){
for (int j = 0; j < N; ++j){
sol[i*N + j].y = (6*drand48() - 3)/2;
sol[i*N + j].y = (6*drand48() - 3)/2;
}
}
// Create copy on GPU
cudaMemcpy(A, sol, N*N*sizeof(cufftDoubleComplex), cudaMemcpyHostToDevice);
dim3 meshDim(N,N);
cufftHandle plan;
cufftPlan2d(&plan, N, N, CUFFT_Z2Z);
// start loop
for (int n = 0; n < M; ++n){
// Begin 1st
// Take in 2nd derivative, assign values
assign<<<meshDim,1>>>(N, A, del2A_output);
// 2nd derivative
cufftExecZ2Z(plan, del2A_output, del2A_temp, CUFFT_FORWARD);
fftshift<<<meshDim,1>>>(N, del2A_temp, del2A_shift);
del2A<<<meshDim,1>>>(N, del2A_shift, del2A_output);
fftshift<<<meshDim,1>>>(N, del2A_output, del2A_shift);
cufftExecZ2Z(plan, del2A_shift, del2A_output, CUFFT_INVERSE);
// A1 update step, dt/4 step
update<<<meshDim,1>>>(N, dt, c1, c3, 4, L, A, del2A_output, A_temp);
// End 1st
// Begin 2nd
assign<<<meshDim,1>>>(N, A_temp, del2A_output);
// 2nd derivative
cufftExecZ2Z(plan, del2A_output, del2A_temp, CUFFT_FORWARD);
fftshift<<<meshDim,1>>>(N, del2A_temp, del2A_shift);
del2A<<<meshDim,1>>>(N, del2A_shift, del2A_output);
fftshift<<<meshDim,1>>>(N, del2A_output, del2A_shift);
cufftExecZ2Z(plan, del2A_shift, del2A_output, CUFFT_INVERSE);
// Update A2, dt/3 step
update<<<meshDim,1>>>(N, dt, c1, c3, 3, L, A_temp, del2A_output, A);
// End 2nd
// Begin 3rd
assign<<<meshDim,1>>>(N, A, del2A_output);
cufftExecZ2Z(plan, del2A_output, del2A_temp, CUFFT_FORWARD);
fftshift<<<meshDim,1>>>(N, del2A_temp, del2A_shift);
del2A<<<meshDim,1>>>(N, del2A_shift, del2A_output);
fftshift<<<meshDim,1>>>(N, del2A_output, del2A_shift);
cufftExecZ2Z(plan, del2A_shift, del2A_output, CUFFT_INVERSE);
// Update A1, dt/2 step
update<<<meshDim,1>>>(N, dt, c1, c3, 2, L, A, del2A_output, A_temp);
// End 3rd
// Begin 4th
assign<<<meshDim,1>>>(N, A_temp, del2A_output);
cufftExecZ2Z(plan, del2A_output, del2A_temp, CUFFT_FORWARD);
fftshift<<<meshDim,1>>>(N, del2A_temp, del2A_shift);
del2A<<<meshDim,1>>>(N, del2A_shift, del2A_output);
fftshift<<<meshDim,1>>>(N, del2A_output, del2A_shift);
cufftExecZ2Z(plan, del2A_shift, del2A_output, CUFFT_INVERSE);
// update A, dt/1 step
update<<<meshDim,1>>>(N, dt, c1, c3, 1, L, A_temp, del2A_output, A);
// Save final solution and store to CPU
if ((n+1)%interval == 0){
cudaThreadSynchronize();
cudaMemcpy(sol, A, N*N*sizeof(cufftDoubleComplex), cudaMemcpyDeviceToHost);
for (int i = 0; i < N; ++i){
for (int j = 0; j < N; ++j){
fwrite(&(sol[i*N+j].x), sizeof(double), 1, fileid);
}
}
}
}
// End loop
// Copy back to CPU
cudaThreadSynchronize();
cudaMemcpy(sol, A, N*N*sizeof(cufftDoubleComplex), cudaMemcpyDeviceToHost);
// Free up all memory used
free(sol);
cudaFree(A);
cudaFree(A_temp);
cudaFree(del2A_output);
cudaFree(del2A_temp);
cudaFree(del2A_shift);
cufftDestroy(plan);
// Stop clock, output run time
clock_t end_time = clock();
printf("Runtime:%g s.\n", (float)(end_time - start_time)/CLOCKS_PER_SEC);
return 0;
} | .file "tmpxft_0018ba91_00000000-6_ComplexGL.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3996:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3996:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z6assigniP7double2S0_iP7double2S0_
.type _Z36__device_stub__Z6assigniP7double2S0_iP7double2S0_, @function
_Z36__device_stub__Z6assigniP7double2S0_iP7double2S0_:
.LFB4018:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6assigniP7double2S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4018:
.size _Z36__device_stub__Z6assigniP7double2S0_iP7double2S0_, .-_Z36__device_stub__Z6assigniP7double2S0_iP7double2S0_
.globl _Z6assigniP7double2S0_
.type _Z6assigniP7double2S0_, @function
_Z6assigniP7double2S0_:
.LFB4019:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z6assigniP7double2S0_iP7double2S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4019:
.size _Z6assigniP7double2S0_, .-_Z6assigniP7double2S0_
.globl _Z38__device_stub__Z8fftshiftiP7double2S0_iP7double2S0_
.type _Z38__device_stub__Z8fftshiftiP7double2S0_iP7double2S0_, @function
_Z38__device_stub__Z8fftshiftiP7double2S0_iP7double2S0_:
.LFB4020:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8fftshiftiP7double2S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4020:
.size _Z38__device_stub__Z8fftshiftiP7double2S0_iP7double2S0_, .-_Z38__device_stub__Z8fftshiftiP7double2S0_iP7double2S0_
.globl _Z8fftshiftiP7double2S0_
.type _Z8fftshiftiP7double2S0_, @function
_Z8fftshiftiP7double2S0_:
.LFB4021:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z8fftshiftiP7double2S0_iP7double2S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4021:
.size _Z8fftshiftiP7double2S0_, .-_Z8fftshiftiP7double2S0_
.globl _Z35__device_stub__Z5del2AiP7double2S0_iP7double2S0_
.type _Z35__device_stub__Z5del2AiP7double2S0_iP7double2S0_, @function
_Z35__device_stub__Z5del2AiP7double2S0_iP7double2S0_:
.LFB4022:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5del2AiP7double2S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4022:
.size _Z35__device_stub__Z5del2AiP7double2S0_iP7double2S0_, .-_Z35__device_stub__Z5del2AiP7double2S0_iP7double2S0_
.globl _Z5del2AiP7double2S0_
.type _Z5del2AiP7double2S0_, @function
_Z5del2AiP7double2S0_:
.LFB4023:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z5del2AiP7double2S0_iP7double2S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4023:
.size _Z5del2AiP7double2S0_, .-_Z5del2AiP7double2S0_
.globl _Z44__device_stub__Z6updateidddidP7double2S0_S0_idddidP7double2S0_S0_
.type _Z44__device_stub__Z6updateidddidP7double2S0_S0_idddidP7double2S0_S0_, @function
_Z44__device_stub__Z6updateidddidP7double2S0_S0_idddidP7double2S0_S0_:
.LFB4024:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 60(%rsp)
movsd %xmm0, 48(%rsp)
movsd %xmm1, 40(%rsp)
movsd %xmm2, 32(%rsp)
movl %esi, 56(%rsp)
movsd %xmm3, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movq %rsp, %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z6updateidddidP7double2S0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4024:
.size _Z44__device_stub__Z6updateidddidP7double2S0_S0_idddidP7double2S0_S0_, .-_Z44__device_stub__Z6updateidddidP7double2S0_S0_idddidP7double2S0_S0_
.globl _Z6updateidddidP7double2S0_S0_
.type _Z6updateidddidP7double2S0_S0_, @function
_Z6updateidddidP7double2S0_S0_:
.LFB4025:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z6updateidddidP7double2S0_S0_idddidP7double2S0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4025:
.size _Z6updateidddidP7double2S0_S0_, .-_Z6updateidddidP7double2S0_S0_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "w"
.LC2:
.string "ComplexGL.out"
.LC8:
.string "Runtime:%g s.\n"
.text
.globl main
.type main, @function
main:
.LFB3993:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $184, %rsp
.cfi_def_cfa_offset 240
movl %edi, %r15d
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
call clock@PLT
movq %rax, 88(%rsp)
movq 8(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 64(%rsp)
movl %eax, %r13d
movslq %eax, %r12
movq 16(%rbp), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 24(%rbp), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 32(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 40(%rsp)
movl %eax, %ebx
movl $0, %edi
call time@PLT
movq %rax, %rdi
cmpl $5, %r15d
jg .L75
.L36:
call srand48@PLT
pxor %xmm0, %xmm0
cvtsi2sdl 40(%rsp), %xmm0
movsd .LC0(%rip), %xmm1
divsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp)
movabsq $7378697629483820647, %rdx
movq %r12, %rax
imulq %rdx
sarq $2, %rdx
movq %r12, %rax
sarq $63, %rax
movl %edx, %ecx
subl %eax, %ecx
movl %ecx, 52(%rsp)
imulq %r12, %r12
salq $4, %r12
movq %r12, %rdi
movq %r12, 56(%rsp)
call malloc@PLT
movq %rax, %r14
movq %rax, (%rsp)
movq 64(%rsp), %r15
movslq %r15d, %rbp
imulq %rbp, %rbp
salq $4, %rbp
leaq 104(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 112(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 120(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 128(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 136(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq .LC1(%rip), %rsi
leaq .LC2(%rip), %rdi
call fopen@PLT
movq %rax, %r12
testl %r15d, %r15d
jle .L37
movslq %r15d, %rcx
movq %rcx, %rax
salq $4, %rax
movq %rax, 32(%rsp)
leal -1(%r15), %ebp
addq $1, %rbp
salq $4, %rbp
addq %r14, %rbp
movl $0, %r15d
movl $0, %r14d
movq %r12, 72(%rsp)
movl %r14d, %r12d
movl %ebx, 80(%rsp)
movq %rcx, %r14
.L38:
movq %r15, %rbx
salq $4, %rbx
movq (%rsp), %rax
addq %rax, %rbx
.L39:
call drand48@PLT
mulsd .LC3(%rip), %xmm0
subsd .LC4(%rip), %xmm0
mulsd .LC5(%rip), %xmm0
movsd %xmm0, 8(%rbx)
call drand48@PLT
mulsd .LC3(%rip), %xmm0
subsd .LC4(%rip), %xmm0
mulsd .LC5(%rip), %xmm0
movsd %xmm0, 8(%rbx)
addq $16, %rbx
cmpq %rbp, %rbx
jne .L39
addl $1, %r12d
addq %r14, %r15
movq 32(%rsp), %rax
addq %rax, %rbp
cmpl %r13d, %r12d
jne .L38
movq 72(%rsp), %r12
movl 80(%rsp), %ebx
.L37:
movl $1, %ecx
movq 56(%rsp), %rdx
movq (%rsp), %r14
movq %r14, %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
movq 64(%rsp), %r15
movl %r15d, 144(%rsp)
movl %r15d, 148(%rsp)
movl $1, 152(%rsp)
leaq 100(%rsp), %rdi
movl $105, %ecx
movl %r13d, %edx
movl %r13d, %esi
call cufftPlan2d@PLT
cmpl $0, 40(%rsp)
jle .L40
movslq %r15d, %rcx
movq %rcx, %rsi
salq $4, %rsi
movq %rsi, 32(%rsp)
leal -1(%r15), %eax
addq $1, %rax
salq $4, %rax
addq %r14, %rax
movq %rax, 80(%rsp)
movl $0, %r14d
movq %rcx, 40(%rsp)
jmp .L64
.L75:
movq 40(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rdi
jmp .L36
.L77:
movq 120(%rsp), %rdx
movq 104(%rsp), %rsi
movl %r13d, %edi
call _Z36__device_stub__Z6assigniP7double2S0_iP7double2S0_
jmp .L41
.L78:
movq 136(%rsp), %rdx
movq 128(%rsp), %rsi
movl %r13d, %edi
call _Z38__device_stub__Z8fftshiftiP7double2S0_iP7double2S0_
jmp .L42
.L79:
movq 120(%rsp), %rdx
movq 136(%rsp), %rsi
movl %r13d, %edi
call _Z35__device_stub__Z5del2AiP7double2S0_iP7double2S0_
jmp .L43
.L80:
movq 136(%rsp), %rdx
movq 120(%rsp), %rsi
movl %r13d, %edi
call _Z38__device_stub__Z8fftshiftiP7double2S0_iP7double2S0_
jmp .L44
.L81:
movq 112(%rsp), %r8
movq 120(%rsp), %rcx
movq 104(%rsp), %rdx
movsd .LC6(%rip), %xmm3
movl $4, %esi
movsd 16(%rsp), %xmm2
movsd 24(%rsp), %xmm1
movsd 8(%rsp), %xmm0
movl %r13d, %edi
call _Z44__device_stub__Z6updateidddidP7double2S0_S0_idddidP7double2S0_S0_
jmp .L45
.L82:
movq 120(%rsp), %rdx
movq 112(%rsp), %rsi
movl %r13d, %edi
call _Z36__device_stub__Z6assigniP7double2S0_iP7double2S0_
jmp .L46
.L83:
movq 136(%rsp), %rdx
movq 128(%rsp), %rsi
movl %r13d, %edi
call _Z38__device_stub__Z8fftshiftiP7double2S0_iP7double2S0_
jmp .L47
.L84:
movq 120(%rsp), %rdx
movq 136(%rsp), %rsi
movl %r13d, %edi
call _Z35__device_stub__Z5del2AiP7double2S0_iP7double2S0_
jmp .L48
.L85:
movq 136(%rsp), %rdx
movq 120(%rsp), %rsi
movl %r13d, %edi
call _Z38__device_stub__Z8fftshiftiP7double2S0_iP7double2S0_
jmp .L49
.L86:
movq 104(%rsp), %r8
movq 120(%rsp), %rcx
movq 112(%rsp), %rdx
movsd .LC6(%rip), %xmm3
movl $3, %esi
movsd 16(%rsp), %xmm2
movsd 24(%rsp), %xmm1
movsd 8(%rsp), %xmm0
movl %r13d, %edi
call _Z44__device_stub__Z6updateidddidP7double2S0_S0_idddidP7double2S0_S0_
jmp .L50
.L87:
movq 120(%rsp), %rdx
movq 104(%rsp), %rsi
movl %r13d, %edi
call _Z36__device_stub__Z6assigniP7double2S0_iP7double2S0_
jmp .L51
.L88:
movq 136(%rsp), %rdx
movq 128(%rsp), %rsi
movl %r13d, %edi
call _Z38__device_stub__Z8fftshiftiP7double2S0_iP7double2S0_
jmp .L52
.L89:
movq 120(%rsp), %rdx
movq 136(%rsp), %rsi
movl %r13d, %edi
call _Z35__device_stub__Z5del2AiP7double2S0_iP7double2S0_
jmp .L53
.L90:
movq 136(%rsp), %rdx
movq 120(%rsp), %rsi
movl %r13d, %edi
call _Z38__device_stub__Z8fftshiftiP7double2S0_iP7double2S0_
jmp .L54
.L91:
movq 112(%rsp), %r8
movq 120(%rsp), %rcx
movq 104(%rsp), %rdx
movsd .LC6(%rip), %xmm3
movl $2, %esi
movsd 16(%rsp), %xmm2
movsd 24(%rsp), %xmm1
movsd 8(%rsp), %xmm0
movl %r13d, %edi
call _Z44__device_stub__Z6updateidddidP7double2S0_S0_idddidP7double2S0_S0_
jmp .L55
.L92:
movq 120(%rsp), %rdx
movq 112(%rsp), %rsi
movl %r13d, %edi
call _Z36__device_stub__Z6assigniP7double2S0_iP7double2S0_
jmp .L56
.L93:
movq 136(%rsp), %rdx
movq 128(%rsp), %rsi
movl %r13d, %edi
call _Z38__device_stub__Z8fftshiftiP7double2S0_iP7double2S0_
jmp .L57
.L94:
movq 120(%rsp), %rdx
movq 136(%rsp), %rsi
movl %r13d, %edi
call _Z35__device_stub__Z5del2AiP7double2S0_iP7double2S0_
jmp .L58
.L95:
movq 136(%rsp), %rdx
movq 120(%rsp), %rsi
movl %r13d, %edi
call _Z38__device_stub__Z8fftshiftiP7double2S0_iP7double2S0_
jmp .L59
.L60:
addl $1, %r14d
movl %r14d, %eax
cltd
idivl 52(%rsp)
movl %edx, %r15d
testl %edx, %edx
je .L76
.L61:
cmpl %ebx, %r14d
je .L40
.L64:
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 156(%rsp), %rdx
movl $1, %ecx
movq 144(%rsp), %rdi
movl 152(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L77
.L41:
movl $-1, %ecx
movq 128(%rsp), %rdx
movq 120(%rsp), %rsi
movl 100(%rsp), %edi
call cufftExecZ2Z@PLT
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 156(%rsp), %rdx
movl $1, %ecx
movq 144(%rsp), %rdi
movl 152(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L78
.L42:
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 156(%rsp), %rdx
movl $1, %ecx
movq 144(%rsp), %rdi
movl 152(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L79
.L43:
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 156(%rsp), %rdx
movl $1, %ecx
movq 144(%rsp), %rdi
movl 152(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L80
.L44:
movl $1, %ecx
movq 120(%rsp), %rdx
movq 136(%rsp), %rsi
movl 100(%rsp), %edi
call cufftExecZ2Z@PLT
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 156(%rsp), %rdx
movl $1, %ecx
movq 144(%rsp), %rdi
movl 152(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L81
.L45:
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 156(%rsp), %rdx
movl $1, %ecx
movq 144(%rsp), %rdi
movl 152(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L82
.L46:
movl $-1, %ecx
movq 128(%rsp), %rdx
movq 120(%rsp), %rsi
movl 100(%rsp), %edi
call cufftExecZ2Z@PLT
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 156(%rsp), %rdx
movl $1, %ecx
movq 144(%rsp), %rdi
movl 152(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L83
.L47:
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 156(%rsp), %rdx
movl $1, %ecx
movq 144(%rsp), %rdi
movl 152(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L84
.L48:
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 156(%rsp), %rdx
movl $1, %ecx
movq 144(%rsp), %rdi
movl 152(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L85
.L49:
movl $1, %ecx
movq 120(%rsp), %rdx
movq 136(%rsp), %rsi
movl 100(%rsp), %edi
call cufftExecZ2Z@PLT
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 156(%rsp), %rdx
movl $1, %ecx
movq 144(%rsp), %rdi
movl 152(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L86
.L50:
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 156(%rsp), %rdx
movl $1, %ecx
movq 144(%rsp), %rdi
movl 152(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L87
.L51:
movl $-1, %ecx
movq 128(%rsp), %rdx
movq 120(%rsp), %rsi
movl 100(%rsp), %edi
call cufftExecZ2Z@PLT
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 156(%rsp), %rdx
movl $1, %ecx
movq 144(%rsp), %rdi
movl 152(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L88
.L52:
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 156(%rsp), %rdx
movl $1, %ecx
movq 144(%rsp), %rdi
movl 152(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L89
.L53:
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 156(%rsp), %rdx
movl $1, %ecx
movq 144(%rsp), %rdi
movl 152(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L90
.L54:
movl $1, %ecx
movq 120(%rsp), %rdx
movq 136(%rsp), %rsi
movl 100(%rsp), %edi
call cufftExecZ2Z@PLT
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 156(%rsp), %rdx
movl $1, %ecx
movq 144(%rsp), %rdi
movl 152(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L91
.L55:
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 156(%rsp), %rdx
movl $1, %ecx
movq 144(%rsp), %rdi
movl 152(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L92
.L56:
movl $-1, %ecx
movq 128(%rsp), %rdx
movq 120(%rsp), %rsi
movl 100(%rsp), %edi
call cufftExecZ2Z@PLT
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 156(%rsp), %rdx
movl $1, %ecx
movq 144(%rsp), %rdi
movl 152(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L93
.L57:
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 156(%rsp), %rdx
movl $1, %ecx
movq 144(%rsp), %rdi
movl 152(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L94
.L58:
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 156(%rsp), %rdx
movl $1, %ecx
movq 144(%rsp), %rdi
movl 152(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L95
.L59:
movl $1, %ecx
movq 120(%rsp), %rdx
movq 136(%rsp), %rsi
movl 100(%rsp), %edi
call cufftExecZ2Z@PLT
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 156(%rsp), %rdx
movl $1, %ecx
movq 144(%rsp), %rdi
movl 152(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L60
movq 104(%rsp), %r8
movq 120(%rsp), %rcx
movq 112(%rsp), %rdx
movsd .LC6(%rip), %xmm3
movl $1, %esi
movsd 16(%rsp), %xmm2
movsd 24(%rsp), %xmm1
movsd 8(%rsp), %xmm0
movl %r13d, %edi
call _Z44__device_stub__Z6updateidddidP7double2S0_S0_idddidP7double2S0_S0_
jmp .L60
.L76:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movq 56(%rsp), %rdx
movq 104(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movq 80(%rsp), %rbp
movl $0, %eax
testl %r13d, %r13d
jle .L61
movl %r14d, 64(%rsp)
movl %r15d, %r14d
movq %rax, %r15
movl %ebx, 72(%rsp)
.L62:
movq %r15, %rbx
salq $4, %rbx
movq (%rsp), %rax
addq %rax, %rbx
.L63:
movq %r12, %rcx
movl $1, %edx
movl $8, %esi
movq %rbx, %rdi
call fwrite@PLT
addq $16, %rbx
cmpq %rbp, %rbx
jne .L63
addl $1, %r14d
movq 40(%rsp), %rax
addq %rax, %r15
movq 32(%rsp), %rax
addq %rax, %rbp
cmpl %r13d, %r14d
jne .L62
movl 64(%rsp), %r14d
movl 72(%rsp), %ebx
jmp .L61
.L40:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movq 56(%rsp), %rdx
movq 104(%rsp), %rsi
movq (%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rdi
call free@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 112(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rdi
call cudaFree@PLT
movq 128(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rdi
call cudaFree@PLT
movl 100(%rsp), %edi
call cufftDestroy@PLT
call clock@PLT
movq 88(%rsp), %rcx
subq %rcx, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC7(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L96
movl $0, %eax
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L96:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3993:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC9:
.string "_Z6updateidddidP7double2S0_S0_"
.section .rodata.str1.1
.LC10:
.string "_Z5del2AiP7double2S0_"
.LC11:
.string "_Z8fftshiftiP7double2S0_"
.LC12:
.string "_Z6assigniP7double2S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4027:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z6updateidddidP7double2S0_S0_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z5del2AiP7double2S0_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z8fftshiftiP7double2S0_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z6assigniP7double2S0_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4027:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1086556160
.align 8
.LC3:
.long 0
.long 1075314688
.align 8
.LC4:
.long 0
.long 1074266112
.align 8
.LC5:
.long 0
.long 1071644672
.align 8
.LC6:
.long 1413754136
.long 1081680379
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC7:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include <complex.h>
#include <cufft.h>
// Kernel used for assigning values to matrix.
__global__ void assign(int N, cufftDoubleComplex* a, cufftDoubleComplex* a_copy){
if (blockIdx.x < N && blockIdx.y < N){
a_copy[blockIdx.x+blockIdx.y*gridDim.x].x = a[blockIdx.x+blockIdx.y*gridDim.x].x;
a_copy[blockIdx.x+blockIdx.y*gridDim.x].y = a[blockIdx.x+blockIdx.y*gridDim.x].y;
}
}
// FFT shift kernel, works in GPU
__global__ void fftshift(int N, cufftDoubleComplex* a, cufftDoubleComplex* a_shift){
if (blockIdx.x < N/2 && blockIdx.y < N/2){
a_shift[blockIdx.x+blockIdx.y*gridDim.x].x = a[(blockIdx.x+N/2)+(blockIdx.y+N/2)*gridDim.x].x;
a_shift[blockIdx.x+blockIdx.y*gridDim.x].y = a[(blockIdx.x+N/2)+(blockIdx.y+N/2)*gridDim.x].y;
}
else if (blockIdx.x < N/2 && blockIdx.y >= N/2)
a_shift[blockIdx.x+blockIdx.y*gridDim.x] = a[(blockIdx.x+N/2)+(blockIdx.y-N/2)*gridDim.x];
else if (blockIdx.x >= N/2 && blockIdx.y < N/2)
a_shift[blockIdx.x+blockIdx.y*gridDim.x] = a[(blockIdx.x-N/2)+(blockIdx.y+N/2)*gridDim.x];
else if (blockIdx.x >= N/2 && blockIdx.y >= N/2)
a_shift[blockIdx.x+blockIdx.y*gridDim.x] = a[(blockIdx.x-N/2)+(blockIdx.y-N/2)*gridDim.x];
}
// Kernel used to compute 2nd derivative
__global__ void del2A(int N, cufftDoubleComplex* del2A_input, cufftDoubleComplex* del2A_output){
if (blockIdx.x < N && blockIdx.y < N){
del2A_output[blockIdx.x+blockIdx.y*gridDim.x].x =
(-((double)(blockIdx.x) + (double)(-N/2))*((double)(blockIdx.x) + (double)(-N/2))
-((double)(blockIdx.y) + (double)(-N/2))*((double)(blockIdx.y) + (double)(-N/2)))
*del2A_input[blockIdx.x+blockIdx.y*gridDim.x].x/N/N;
del2A_output[blockIdx.x+blockIdx.y*gridDim.x].y =
(-((double)(blockIdx.x) + (double)(-N/2))*((double)(blockIdx.x) + (double)(-N/2))
-((double)(blockIdx.y) + (double)(-N/2))*((double)(blockIdx.y) + (double)(-N/2)))
*del2A_input[blockIdx.x+blockIdx.y*gridDim.x].y/(N*N);
}
}
// Kernel used to update A, A1, A2 matrices using pointers to each matrix, with div used to decrement in time.
__global__ void update(int N, double dt, double c1, double c3, int div, double L, cufftDoubleComplex* A, cufftDoubleComplex* d2A, cufftDoubleComplex* A_new){
if (blockIdx.x < N && blockIdx.y < N){
A_new[blockIdx.x+blockIdx.y*gridDim.x].x = A[blockIdx.x+blockIdx.y*gridDim.x].x + dt/div*(A[blockIdx.x+blockIdx.y*gridDim.x].x
+ (d2A[blockIdx.x+blockIdx.y*gridDim.x].x - c1*d2A[blockIdx.x+blockIdx.y*gridDim.x].y)*(2*M_PI/L)*(2*M_PI/L)
- (A[blockIdx.x+blockIdx.y*gridDim.x].x + c3*A[blockIdx.x+blockIdx.y*gridDim.x].y)
*(A[blockIdx.x+blockIdx.y*gridDim.x].x*A[blockIdx.x+blockIdx.y*gridDim.x].x + A[blockIdx.x+blockIdx.y*gridDim.x].y*A[blockIdx.x+blockIdx.y*gridDim.x].y));
A_new[blockIdx.x+blockIdx.y*gridDim.x].y = A[blockIdx.x+blockIdx.y*gridDim.x].y + dt/div*(A[blockIdx.x+blockIdx.y*gridDim.x].y
+ (d2A[blockIdx.x+blockIdx.y*gridDim.x].y + c1*d2A[blockIdx.x+blockIdx.y*gridDim.x].x)*(2*M_PI/L)*(2*M_PI/L)
- (A[blockIdx.x+blockIdx.y*gridDim.x].y - c3*A[blockIdx.x+blockIdx.y*gridDim.x].x)
*(A[blockIdx.x+blockIdx.y*gridDim.x].x*A[blockIdx.x+blockIdx.y*gridDim.x].x + A[blockIdx.x+blockIdx.y*gridDim.x].y*A[blockIdx.x+blockIdx.y*gridDim.x].y));
}
}
int main(int argc, char* argv[]){
// Start runtime clock
clock_t start_time = clock();
// Set up args to be taken as inputs
ptrdiff_t N = atoi(argv[1]);
double c1 = atof(argv[2]);
double c3 = atof(argv[3]);
int M = atoi(argv[4]);
// Insure same seed is used for all processors
long int seed = (long int)time(NULL);
if (argc >= 6){
seed = atol(argv[5]);
}
srand48(seed);
// Define parameter values
double L = 128*M_PI;
int T = 10000;
double dt = (double)T/M;
int interval = N/10;
// Allocate memory within CPU
cufftDoubleComplex *sol = (cufftDoubleComplex*)malloc(N*N*sizeof(cufftDoubleComplex));
// Allocate memory within GPU
cufftDoubleComplex* A;
cudaMalloc((void**)&A, sizeof(cufftDoubleComplex)*N*N);
cufftDoubleComplex* A_temp;
cudaMalloc((void**)&A_temp, sizeof(cufftDoubleComplex)*N*N);
cufftDoubleComplex* del2A_output;
cudaMalloc((void**)&del2A_output, sizeof(cufftDoubleComplex)*N*N);
cufftDoubleComplex* del2A_temp;
cudaMalloc((void**)&del2A_temp, sizeof(cufftDoubleComplex)*N*N);
cufftDoubleComplex* del2A_shift;
cudaMalloc((void**)&del2A_shift, sizeof(cufftDoubleComplex)*N*N);
// Create and open target file
FILE *fileid = fopen("ComplexGL.out", "w");
// ICs
for (int i = 0; i < N; ++i){
for (int j = 0; j < N; ++j){
sol[i*N + j].y = (6*drand48() - 3)/2;
sol[i*N + j].y = (6*drand48() - 3)/2;
}
}
// Create copy on GPU
cudaMemcpy(A, sol, N*N*sizeof(cufftDoubleComplex), cudaMemcpyHostToDevice);
dim3 meshDim(N,N);
cufftHandle plan;
cufftPlan2d(&plan, N, N, CUFFT_Z2Z);
// start loop
for (int n = 0; n < M; ++n){
// Begin 1st
// Take in 2nd derivative, assign values
assign<<<meshDim,1>>>(N, A, del2A_output);
// 2nd derivative
cufftExecZ2Z(plan, del2A_output, del2A_temp, CUFFT_FORWARD);
fftshift<<<meshDim,1>>>(N, del2A_temp, del2A_shift);
del2A<<<meshDim,1>>>(N, del2A_shift, del2A_output);
fftshift<<<meshDim,1>>>(N, del2A_output, del2A_shift);
cufftExecZ2Z(plan, del2A_shift, del2A_output, CUFFT_INVERSE);
// A1 update step, dt/4 step
update<<<meshDim,1>>>(N, dt, c1, c3, 4, L, A, del2A_output, A_temp);
// End 1st
// Begin 2nd
assign<<<meshDim,1>>>(N, A_temp, del2A_output);
// 2nd derivative
cufftExecZ2Z(plan, del2A_output, del2A_temp, CUFFT_FORWARD);
fftshift<<<meshDim,1>>>(N, del2A_temp, del2A_shift);
del2A<<<meshDim,1>>>(N, del2A_shift, del2A_output);
fftshift<<<meshDim,1>>>(N, del2A_output, del2A_shift);
cufftExecZ2Z(plan, del2A_shift, del2A_output, CUFFT_INVERSE);
// Update A2, dt/3 step
update<<<meshDim,1>>>(N, dt, c1, c3, 3, L, A_temp, del2A_output, A);
// End 2nd
// Begin 3rd
assign<<<meshDim,1>>>(N, A, del2A_output);
cufftExecZ2Z(plan, del2A_output, del2A_temp, CUFFT_FORWARD);
fftshift<<<meshDim,1>>>(N, del2A_temp, del2A_shift);
del2A<<<meshDim,1>>>(N, del2A_shift, del2A_output);
fftshift<<<meshDim,1>>>(N, del2A_output, del2A_shift);
cufftExecZ2Z(plan, del2A_shift, del2A_output, CUFFT_INVERSE);
// Update A1, dt/2 step
update<<<meshDim,1>>>(N, dt, c1, c3, 2, L, A, del2A_output, A_temp);
// End 3rd
// Begin 4th
assign<<<meshDim,1>>>(N, A_temp, del2A_output);
cufftExecZ2Z(plan, del2A_output, del2A_temp, CUFFT_FORWARD);
fftshift<<<meshDim,1>>>(N, del2A_temp, del2A_shift);
del2A<<<meshDim,1>>>(N, del2A_shift, del2A_output);
fftshift<<<meshDim,1>>>(N, del2A_output, del2A_shift);
cufftExecZ2Z(plan, del2A_shift, del2A_output, CUFFT_INVERSE);
// update A, dt/1 step
update<<<meshDim,1>>>(N, dt, c1, c3, 1, L, A_temp, del2A_output, A);
// Save final solution and store to CPU
if ((n+1)%interval == 0){
cudaThreadSynchronize();
cudaMemcpy(sol, A, N*N*sizeof(cufftDoubleComplex), cudaMemcpyDeviceToHost);
for (int i = 0; i < N; ++i){
for (int j = 0; j < N; ++j){
fwrite(&(sol[i*N+j].x), sizeof(double), 1, fileid);
}
}
}
}
// End loop
// Copy back to CPU
cudaThreadSynchronize();
cudaMemcpy(sol, A, N*N*sizeof(cufftDoubleComplex), cudaMemcpyDeviceToHost);
// Free up all memory used
free(sol);
cudaFree(A);
cudaFree(A_temp);
cudaFree(del2A_output);
cudaFree(del2A_temp);
cudaFree(del2A_shift);
cufftDestroy(plan);
// Stop clock, output run time
clock_t end_time = clock();
printf("Runtime:%g s.\n", (float)(end_time - start_time)/CLOCKS_PER_SEC);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include <complex.h>
#include <hipfft/hipfft.h>
// Kernel used for assigning values to matrix.
__global__ void assign(int N, hipfftDoubleComplex* a, hipfftDoubleComplex* a_copy){
if (blockIdx.x < N && blockIdx.y < N){
a_copy[blockIdx.x+blockIdx.y*gridDim.x].x = a[blockIdx.x+blockIdx.y*gridDim.x].x;
a_copy[blockIdx.x+blockIdx.y*gridDim.x].y = a[blockIdx.x+blockIdx.y*gridDim.x].y;
}
}
// FFT shift kernel, works in GPU
__global__ void fftshift(int N, hipfftDoubleComplex* a, hipfftDoubleComplex* a_shift){
if (blockIdx.x < N/2 && blockIdx.y < N/2){
a_shift[blockIdx.x+blockIdx.y*gridDim.x].x = a[(blockIdx.x+N/2)+(blockIdx.y+N/2)*gridDim.x].x;
a_shift[blockIdx.x+blockIdx.y*gridDim.x].y = a[(blockIdx.x+N/2)+(blockIdx.y+N/2)*gridDim.x].y;
}
else if (blockIdx.x < N/2 && blockIdx.y >= N/2)
a_shift[blockIdx.x+blockIdx.y*gridDim.x] = a[(blockIdx.x+N/2)+(blockIdx.y-N/2)*gridDim.x];
else if (blockIdx.x >= N/2 && blockIdx.y < N/2)
a_shift[blockIdx.x+blockIdx.y*gridDim.x] = a[(blockIdx.x-N/2)+(blockIdx.y+N/2)*gridDim.x];
else if (blockIdx.x >= N/2 && blockIdx.y >= N/2)
a_shift[blockIdx.x+blockIdx.y*gridDim.x] = a[(blockIdx.x-N/2)+(blockIdx.y-N/2)*gridDim.x];
}
// Kernel used to compute 2nd derivative
__global__ void del2A(int N, hipfftDoubleComplex* del2A_input, hipfftDoubleComplex* del2A_output){
if (blockIdx.x < N && blockIdx.y < N){
del2A_output[blockIdx.x+blockIdx.y*gridDim.x].x =
(-((double)(blockIdx.x) + (double)(-N/2))*((double)(blockIdx.x) + (double)(-N/2))
-((double)(blockIdx.y) + (double)(-N/2))*((double)(blockIdx.y) + (double)(-N/2)))
*del2A_input[blockIdx.x+blockIdx.y*gridDim.x].x/N/N;
del2A_output[blockIdx.x+blockIdx.y*gridDim.x].y =
(-((double)(blockIdx.x) + (double)(-N/2))*((double)(blockIdx.x) + (double)(-N/2))
-((double)(blockIdx.y) + (double)(-N/2))*((double)(blockIdx.y) + (double)(-N/2)))
*del2A_input[blockIdx.x+blockIdx.y*gridDim.x].y/(N*N);
}
}
// Kernel used to update A, A1, A2 matrices using pointers to each matrix, with div used to decrement in time.
__global__ void update(int N, double dt, double c1, double c3, int div, double L, hipfftDoubleComplex* A, hipfftDoubleComplex* d2A, hipfftDoubleComplex* A_new){
if (blockIdx.x < N && blockIdx.y < N){
A_new[blockIdx.x+blockIdx.y*gridDim.x].x = A[blockIdx.x+blockIdx.y*gridDim.x].x + dt/div*(A[blockIdx.x+blockIdx.y*gridDim.x].x
+ (d2A[blockIdx.x+blockIdx.y*gridDim.x].x - c1*d2A[blockIdx.x+blockIdx.y*gridDim.x].y)*(2*M_PI/L)*(2*M_PI/L)
- (A[blockIdx.x+blockIdx.y*gridDim.x].x + c3*A[blockIdx.x+blockIdx.y*gridDim.x].y)
*(A[blockIdx.x+blockIdx.y*gridDim.x].x*A[blockIdx.x+blockIdx.y*gridDim.x].x + A[blockIdx.x+blockIdx.y*gridDim.x].y*A[blockIdx.x+blockIdx.y*gridDim.x].y));
A_new[blockIdx.x+blockIdx.y*gridDim.x].y = A[blockIdx.x+blockIdx.y*gridDim.x].y + dt/div*(A[blockIdx.x+blockIdx.y*gridDim.x].y
+ (d2A[blockIdx.x+blockIdx.y*gridDim.x].y + c1*d2A[blockIdx.x+blockIdx.y*gridDim.x].x)*(2*M_PI/L)*(2*M_PI/L)
- (A[blockIdx.x+blockIdx.y*gridDim.x].y - c3*A[blockIdx.x+blockIdx.y*gridDim.x].x)
*(A[blockIdx.x+blockIdx.y*gridDim.x].x*A[blockIdx.x+blockIdx.y*gridDim.x].x + A[blockIdx.x+blockIdx.y*gridDim.x].y*A[blockIdx.x+blockIdx.y*gridDim.x].y));
}
}
int main(int argc, char* argv[]){
// Start runtime clock
clock_t start_time = clock();
// Set up args to be taken as inputs
ptrdiff_t N = atoi(argv[1]);
double c1 = atof(argv[2]);
double c3 = atof(argv[3]);
int M = atoi(argv[4]);
// Insure same seed is used for all processors
long int seed = (long int)time(NULL);
if (argc >= 6){
seed = atol(argv[5]);
}
srand48(seed);
// Define parameter values
double L = 128*M_PI;
int T = 10000;
double dt = (double)T/M;
int interval = N/10;
// Allocate memory within CPU
hipfftDoubleComplex *sol = (hipfftDoubleComplex*)malloc(N*N*sizeof(hipfftDoubleComplex));
// Allocate memory within GPU
hipfftDoubleComplex* A;
hipMalloc((void**)&A, sizeof(hipfftDoubleComplex)*N*N);
hipfftDoubleComplex* A_temp;
hipMalloc((void**)&A_temp, sizeof(hipfftDoubleComplex)*N*N);
hipfftDoubleComplex* del2A_output;
hipMalloc((void**)&del2A_output, sizeof(hipfftDoubleComplex)*N*N);
hipfftDoubleComplex* del2A_temp;
hipMalloc((void**)&del2A_temp, sizeof(hipfftDoubleComplex)*N*N);
hipfftDoubleComplex* del2A_shift;
hipMalloc((void**)&del2A_shift, sizeof(hipfftDoubleComplex)*N*N);
// Create and open target file
FILE *fileid = fopen("ComplexGL.out", "w");
// ICs
for (int i = 0; i < N; ++i){
for (int j = 0; j < N; ++j){
sol[i*N + j].y = (6*drand48() - 3)/2;
sol[i*N + j].y = (6*drand48() - 3)/2;
}
}
// Create copy on GPU
hipMemcpy(A, sol, N*N*sizeof(hipfftDoubleComplex), hipMemcpyHostToDevice);
dim3 meshDim(N,N);
hipfftHandle plan;
hipfftPlan2d(&plan, N, N, HIPFFT_Z2Z);
// start loop
for (int n = 0; n < M; ++n){
// Begin 1st
// Take in 2nd derivative, assign values
assign<<<meshDim,1>>>(N, A, del2A_output);
// 2nd derivative
hipfftExecZ2Z(plan, del2A_output, del2A_temp, HIPFFT_FORWARD);
fftshift<<<meshDim,1>>>(N, del2A_temp, del2A_shift);
del2A<<<meshDim,1>>>(N, del2A_shift, del2A_output);
fftshift<<<meshDim,1>>>(N, del2A_output, del2A_shift);
hipfftExecZ2Z(plan, del2A_shift, del2A_output, HIPFFT_BACKWARD);
// A1 update step, dt/4 step
update<<<meshDim,1>>>(N, dt, c1, c3, 4, L, A, del2A_output, A_temp);
// End 1st
// Begin 2nd
assign<<<meshDim,1>>>(N, A_temp, del2A_output);
// 2nd derivative
hipfftExecZ2Z(plan, del2A_output, del2A_temp, HIPFFT_FORWARD);
fftshift<<<meshDim,1>>>(N, del2A_temp, del2A_shift);
del2A<<<meshDim,1>>>(N, del2A_shift, del2A_output);
fftshift<<<meshDim,1>>>(N, del2A_output, del2A_shift);
hipfftExecZ2Z(plan, del2A_shift, del2A_output, HIPFFT_BACKWARD);
// Update A2, dt/3 step
update<<<meshDim,1>>>(N, dt, c1, c3, 3, L, A_temp, del2A_output, A);
// End 2nd
// Begin 3rd
assign<<<meshDim,1>>>(N, A, del2A_output);
hipfftExecZ2Z(plan, del2A_output, del2A_temp, HIPFFT_FORWARD);
fftshift<<<meshDim,1>>>(N, del2A_temp, del2A_shift);
del2A<<<meshDim,1>>>(N, del2A_shift, del2A_output);
fftshift<<<meshDim,1>>>(N, del2A_output, del2A_shift);
hipfftExecZ2Z(plan, del2A_shift, del2A_output, HIPFFT_BACKWARD);
// Update A1, dt/2 step
update<<<meshDim,1>>>(N, dt, c1, c3, 2, L, A, del2A_output, A_temp);
// End 3rd
// Begin 4th
assign<<<meshDim,1>>>(N, A_temp, del2A_output);
hipfftExecZ2Z(plan, del2A_output, del2A_temp, HIPFFT_FORWARD);
fftshift<<<meshDim,1>>>(N, del2A_temp, del2A_shift);
del2A<<<meshDim,1>>>(N, del2A_shift, del2A_output);
fftshift<<<meshDim,1>>>(N, del2A_output, del2A_shift);
hipfftExecZ2Z(plan, del2A_shift, del2A_output, HIPFFT_BACKWARD);
// update A, dt/1 step
update<<<meshDim,1>>>(N, dt, c1, c3, 1, L, A_temp, del2A_output, A);
// Save final solution and store to CPU
if ((n+1)%interval == 0){
hipDeviceSynchronize();
hipMemcpy(sol, A, N*N*sizeof(hipfftDoubleComplex), hipMemcpyDeviceToHost);
for (int i = 0; i < N; ++i){
for (int j = 0; j < N; ++j){
fwrite(&(sol[i*N+j].x), sizeof(double), 1, fileid);
}
}
}
}
// End loop
// Copy back to CPU
hipDeviceSynchronize();
hipMemcpy(sol, A, N*N*sizeof(hipfftDoubleComplex), hipMemcpyDeviceToHost);
// Free up all memory used
free(sol);
hipFree(A);
hipFree(A_temp);
hipFree(del2A_output);
hipFree(del2A_temp);
hipFree(del2A_shift);
hipfftDestroy(plan);
// Stop clock, output run time
clock_t end_time = clock();
printf("Runtime:%g s.\n", (float)(end_time - start_time)/CLOCKS_PER_SEC);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include <complex.h>
#include <hipfft/hipfft.h>
// Kernel used for assigning values to matrix.
__global__ void assign(int N, hipfftDoubleComplex* a, hipfftDoubleComplex* a_copy){
if (blockIdx.x < N && blockIdx.y < N){
a_copy[blockIdx.x+blockIdx.y*gridDim.x].x = a[blockIdx.x+blockIdx.y*gridDim.x].x;
a_copy[blockIdx.x+blockIdx.y*gridDim.x].y = a[blockIdx.x+blockIdx.y*gridDim.x].y;
}
}
// FFT shift kernel, works in GPU
__global__ void fftshift(int N, hipfftDoubleComplex* a, hipfftDoubleComplex* a_shift){
if (blockIdx.x < N/2 && blockIdx.y < N/2){
a_shift[blockIdx.x+blockIdx.y*gridDim.x].x = a[(blockIdx.x+N/2)+(blockIdx.y+N/2)*gridDim.x].x;
a_shift[blockIdx.x+blockIdx.y*gridDim.x].y = a[(blockIdx.x+N/2)+(blockIdx.y+N/2)*gridDim.x].y;
}
else if (blockIdx.x < N/2 && blockIdx.y >= N/2)
a_shift[blockIdx.x+blockIdx.y*gridDim.x] = a[(blockIdx.x+N/2)+(blockIdx.y-N/2)*gridDim.x];
else if (blockIdx.x >= N/2 && blockIdx.y < N/2)
a_shift[blockIdx.x+blockIdx.y*gridDim.x] = a[(blockIdx.x-N/2)+(blockIdx.y+N/2)*gridDim.x];
else if (blockIdx.x >= N/2 && blockIdx.y >= N/2)
a_shift[blockIdx.x+blockIdx.y*gridDim.x] = a[(blockIdx.x-N/2)+(blockIdx.y-N/2)*gridDim.x];
}
// Kernel used to compute 2nd derivative
__global__ void del2A(int N, hipfftDoubleComplex* del2A_input, hipfftDoubleComplex* del2A_output){
if (blockIdx.x < N && blockIdx.y < N){
del2A_output[blockIdx.x+blockIdx.y*gridDim.x].x =
(-((double)(blockIdx.x) + (double)(-N/2))*((double)(blockIdx.x) + (double)(-N/2))
-((double)(blockIdx.y) + (double)(-N/2))*((double)(blockIdx.y) + (double)(-N/2)))
*del2A_input[blockIdx.x+blockIdx.y*gridDim.x].x/N/N;
del2A_output[blockIdx.x+blockIdx.y*gridDim.x].y =
(-((double)(blockIdx.x) + (double)(-N/2))*((double)(blockIdx.x) + (double)(-N/2))
-((double)(blockIdx.y) + (double)(-N/2))*((double)(blockIdx.y) + (double)(-N/2)))
*del2A_input[blockIdx.x+blockIdx.y*gridDim.x].y/(N*N);
}
}
// Kernel used to update A, A1, A2 matrices using pointers to each matrix, with div used to decrement in time.
__global__ void update(int N, double dt, double c1, double c3, int div, double L, hipfftDoubleComplex* A, hipfftDoubleComplex* d2A, hipfftDoubleComplex* A_new){
if (blockIdx.x < N && blockIdx.y < N){
A_new[blockIdx.x+blockIdx.y*gridDim.x].x = A[blockIdx.x+blockIdx.y*gridDim.x].x + dt/div*(A[blockIdx.x+blockIdx.y*gridDim.x].x
+ (d2A[blockIdx.x+blockIdx.y*gridDim.x].x - c1*d2A[blockIdx.x+blockIdx.y*gridDim.x].y)*(2*M_PI/L)*(2*M_PI/L)
- (A[blockIdx.x+blockIdx.y*gridDim.x].x + c3*A[blockIdx.x+blockIdx.y*gridDim.x].y)
*(A[blockIdx.x+blockIdx.y*gridDim.x].x*A[blockIdx.x+blockIdx.y*gridDim.x].x + A[blockIdx.x+blockIdx.y*gridDim.x].y*A[blockIdx.x+blockIdx.y*gridDim.x].y));
A_new[blockIdx.x+blockIdx.y*gridDim.x].y = A[blockIdx.x+blockIdx.y*gridDim.x].y + dt/div*(A[blockIdx.x+blockIdx.y*gridDim.x].y
+ (d2A[blockIdx.x+blockIdx.y*gridDim.x].y + c1*d2A[blockIdx.x+blockIdx.y*gridDim.x].x)*(2*M_PI/L)*(2*M_PI/L)
- (A[blockIdx.x+blockIdx.y*gridDim.x].y - c3*A[blockIdx.x+blockIdx.y*gridDim.x].x)
*(A[blockIdx.x+blockIdx.y*gridDim.x].x*A[blockIdx.x+blockIdx.y*gridDim.x].x + A[blockIdx.x+blockIdx.y*gridDim.x].y*A[blockIdx.x+blockIdx.y*gridDim.x].y));
}
}
int main(int argc, char* argv[]){
// Start runtime clock
clock_t start_time = clock();
// Set up args to be taken as inputs
ptrdiff_t N = atoi(argv[1]);
double c1 = atof(argv[2]);
double c3 = atof(argv[3]);
int M = atoi(argv[4]);
// Insure same seed is used for all processors
long int seed = (long int)time(NULL);
if (argc >= 6){
seed = atol(argv[5]);
}
srand48(seed);
// Define parameter values
double L = 128*M_PI;
int T = 10000;
double dt = (double)T/M;
int interval = N/10;
// Allocate memory within CPU
hipfftDoubleComplex *sol = (hipfftDoubleComplex*)malloc(N*N*sizeof(hipfftDoubleComplex));
// Allocate memory within GPU
hipfftDoubleComplex* A;
hipMalloc((void**)&A, sizeof(hipfftDoubleComplex)*N*N);
hipfftDoubleComplex* A_temp;
hipMalloc((void**)&A_temp, sizeof(hipfftDoubleComplex)*N*N);
hipfftDoubleComplex* del2A_output;
hipMalloc((void**)&del2A_output, sizeof(hipfftDoubleComplex)*N*N);
hipfftDoubleComplex* del2A_temp;
hipMalloc((void**)&del2A_temp, sizeof(hipfftDoubleComplex)*N*N);
hipfftDoubleComplex* del2A_shift;
hipMalloc((void**)&del2A_shift, sizeof(hipfftDoubleComplex)*N*N);
// Create and open target file
FILE *fileid = fopen("ComplexGL.out", "w");
// ICs
for (int i = 0; i < N; ++i){
for (int j = 0; j < N; ++j){
sol[i*N + j].y = (6*drand48() - 3)/2;
sol[i*N + j].y = (6*drand48() - 3)/2;
}
}
// Create copy on GPU
hipMemcpy(A, sol, N*N*sizeof(hipfftDoubleComplex), hipMemcpyHostToDevice);
dim3 meshDim(N,N);
hipfftHandle plan;
hipfftPlan2d(&plan, N, N, HIPFFT_Z2Z);
// start loop
for (int n = 0; n < M; ++n){
// Begin 1st
// Take in 2nd derivative, assign values
assign<<<meshDim,1>>>(N, A, del2A_output);
// 2nd derivative
hipfftExecZ2Z(plan, del2A_output, del2A_temp, HIPFFT_FORWARD);
fftshift<<<meshDim,1>>>(N, del2A_temp, del2A_shift);
del2A<<<meshDim,1>>>(N, del2A_shift, del2A_output);
fftshift<<<meshDim,1>>>(N, del2A_output, del2A_shift);
hipfftExecZ2Z(plan, del2A_shift, del2A_output, HIPFFT_BACKWARD);
// A1 update step, dt/4 step
update<<<meshDim,1>>>(N, dt, c1, c3, 4, L, A, del2A_output, A_temp);
// End 1st
// Begin 2nd
assign<<<meshDim,1>>>(N, A_temp, del2A_output);
// 2nd derivative
hipfftExecZ2Z(plan, del2A_output, del2A_temp, HIPFFT_FORWARD);
fftshift<<<meshDim,1>>>(N, del2A_temp, del2A_shift);
del2A<<<meshDim,1>>>(N, del2A_shift, del2A_output);
fftshift<<<meshDim,1>>>(N, del2A_output, del2A_shift);
hipfftExecZ2Z(plan, del2A_shift, del2A_output, HIPFFT_BACKWARD);
// Update A2, dt/3 step
update<<<meshDim,1>>>(N, dt, c1, c3, 3, L, A_temp, del2A_output, A);
// End 2nd
// Begin 3rd
assign<<<meshDim,1>>>(N, A, del2A_output);
hipfftExecZ2Z(plan, del2A_output, del2A_temp, HIPFFT_FORWARD);
fftshift<<<meshDim,1>>>(N, del2A_temp, del2A_shift);
del2A<<<meshDim,1>>>(N, del2A_shift, del2A_output);
fftshift<<<meshDim,1>>>(N, del2A_output, del2A_shift);
hipfftExecZ2Z(plan, del2A_shift, del2A_output, HIPFFT_BACKWARD);
// Update A1, dt/2 step
update<<<meshDim,1>>>(N, dt, c1, c3, 2, L, A, del2A_output, A_temp);
// End 3rd
// Begin 4th
assign<<<meshDim,1>>>(N, A_temp, del2A_output);
hipfftExecZ2Z(plan, del2A_output, del2A_temp, HIPFFT_FORWARD);
fftshift<<<meshDim,1>>>(N, del2A_temp, del2A_shift);
del2A<<<meshDim,1>>>(N, del2A_shift, del2A_output);
fftshift<<<meshDim,1>>>(N, del2A_output, del2A_shift);
hipfftExecZ2Z(plan, del2A_shift, del2A_output, HIPFFT_BACKWARD);
// update A, dt/1 step
update<<<meshDim,1>>>(N, dt, c1, c3, 1, L, A_temp, del2A_output, A);
// Save final solution and store to CPU
if ((n+1)%interval == 0){
hipDeviceSynchronize();
hipMemcpy(sol, A, N*N*sizeof(hipfftDoubleComplex), hipMemcpyDeviceToHost);
for (int i = 0; i < N; ++i){
for (int j = 0; j < N; ++j){
fwrite(&(sol[i*N+j].x), sizeof(double), 1, fileid);
}
}
}
}
// End loop
// Copy back to CPU
hipDeviceSynchronize();
hipMemcpy(sol, A, N*N*sizeof(hipfftDoubleComplex), hipMemcpyDeviceToHost);
// Free up all memory used
free(sol);
hipFree(A);
hipFree(A_temp);
hipFree(del2A_output);
hipFree(del2A_temp);
hipFree(del2A_shift);
hipfftDestroy(plan);
// Stop clock, output run time
clock_t end_time = clock();
printf("Runtime:%g s.\n", (float)(end_time - start_time)/CLOCKS_PER_SEC);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6assigniP15HIP_vector_typeIdLj2EES1_
.globl _Z6assigniP15HIP_vector_typeIdLj2EES1_
.p2align 8
.type _Z6assigniP15HIP_vector_typeIdLj2EES1_,@function
_Z6assigniP15HIP_vector_typeIdLj2EES1_:
s_load_b32 s2, s[0:1], 0x0
s_max_u32 s3, s14, s15
s_waitcnt lgkmcnt(0)
s_cmp_ge_u32 s3, s2
s_cbranch_scc1 .LBB0_2
s_clause 0x1
s_load_b32 s4, s[0:1], 0x18
s_load_b128 s[0:3], s[0:1], 0x8
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s4, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s4, s4, s14
s_lshl_b64 s[4:5], s[4:5], 4
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s0, s4
s_addc_u32 s1, s1, s5
s_add_u32 s2, s2, s4
s_load_b64 s[6:7], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_addc_u32 s3, s3, s5
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
global_store_b64 v2, v[0:1], s[2:3]
global_load_b64 v[0:1], v2, s[0:1] offset:8
s_waitcnt vmcnt(0)
global_store_b64 v2, v[0:1], s[2:3] offset:8
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6assigniP15HIP_vector_typeIdLj2EES1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6assigniP15HIP_vector_typeIdLj2EES1_, .Lfunc_end0-_Z6assigniP15HIP_vector_typeIdLj2EES1_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8fftshiftiP15HIP_vector_typeIdLj2EES1_
.globl _Z8fftshiftiP15HIP_vector_typeIdLj2EES1_
.p2align 8
.type _Z8fftshiftiP15HIP_vector_typeIdLj2EES1_,@function
_Z8fftshiftiP15HIP_vector_typeIdLj2EES1_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s3
s_ashr_i32 s8, s2, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_cmp_lt_u32 s14, s8
s_cselect_b32 s2, -1, 0
s_cmp_ge_u32 s14, s8
s_cselect_b32 s9, -1, 0
s_and_b32 vcc_lo, exec_lo, s9
s_cbranch_vccnz .LBB1_7
s_cmp_ge_u32 s15, s8
s_cbranch_scc0 .LBB1_9
s_and_b32 vcc_lo, exec_lo, s2
s_mov_b32 s3, -1
s_cbranch_vccz .LBB1_8
s_cmp_ge_u32 s15, s8
s_cbranch_scc0 .LBB1_5
s_load_b32 s12, s[0:1], 0x18
s_sub_i32 s2, s15, s8
s_add_i32 s10, s8, s14
s_mov_b32 s3, 0
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s12, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s10, s2
s_lshl_b64 s[10:11], s[2:3], 4
s_mul_i32 s2, s12, s15
s_add_u32 s10, s4, s10
s_addc_u32 s11, s5, s11
s_add_i32 s2, s2, s14
global_load_b128 v[0:3], v4, s[10:11]
s_lshl_b64 s[10:11], s[2:3], 4
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s10, s6, s10
s_addc_u32 s11, s7, s11
s_waitcnt vmcnt(0)
global_store_b128 v4, v[0:3], s[10:11]
.LBB1_5:
s_and_not1_b32 vcc_lo, exec_lo, s3
s_mov_b32 s3, 0
s_cbranch_vccnz .LBB1_8
s_mov_b32 s3, s9
s_branch .LBB1_8
.LBB1_7:
s_mov_b32 s3, -1
.LBB1_8:
s_mov_b32 s2, 0
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB1_10
s_branch .LBB1_17
.LBB1_9:
s_mov_b32 s2, -1
s_branch .LBB1_17
.LBB1_10:
s_cmp_ge_u32 s15, s8
s_mov_b32 s3, -1
s_cbranch_scc0 .LBB1_15
s_and_not1_b32 vcc_lo, exec_lo, s9
s_cbranch_vccnz .LBB1_14
s_cmp_lt_u32 s15, s8
s_cbranch_scc1 .LBB1_14
s_load_b32 s3, s[0:1], 0x18
s_sub_i32 s9, s15, s8
s_sub_i32 s10, s14, s8
s_mov_b32 s11, 0
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s9, s3, s9
s_mul_i32 s3, s3, s15
s_add_i32 s10, s10, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[12:13], s[10:11], 4
s_add_u32 s12, s4, s12
s_addc_u32 s13, s5, s13
s_add_i32 s10, s3, s14
global_load_b128 v[0:3], v4, s[12:13]
s_lshl_b64 s[10:11], s[10:11], 4
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s10, s6, s10
s_addc_u32 s11, s7, s11
s_waitcnt vmcnt(0)
global_store_b128 v4, v[0:3], s[10:11]
.LBB1_14:
s_mov_b32 s3, 0
.LBB1_15:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB1_17
s_load_b32 s3, s[0:1], 0x18
s_add_i32 s9, s8, s15
s_sub_i32 s10, s14, s8
s_mov_b32 s11, 0
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s9, s3, s9
s_mul_i32 s3, s3, s15
s_add_i32 s10, s10, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[12:13], s[10:11], 4
s_add_u32 s12, s4, s12
s_addc_u32 s13, s5, s13
s_add_i32 s10, s3, s14
global_load_b128 v[0:3], v4, s[12:13]
s_lshl_b64 s[10:11], s[10:11], 4
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s10, s6, s10
s_addc_u32 s11, s7, s11
s_waitcnt vmcnt(0)
global_store_b128 v4, v[0:3], s[10:11]
.LBB1_17:
s_and_not1_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB1_19
s_load_b32 s9, s[0:1], 0x18
s_add_i32 s0, s8, s15
s_add_i32 s2, s8, s14
s_mov_b32 s1, 0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s0, s9, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s2, s0
s_lshl_b64 s[2:3], s[0:1], 4
s_mul_i32 s0, s9, s15
s_add_u32 s2, s4, s2
s_addc_u32 s3, s5, s3
s_add_i32 s0, s0, s14
global_load_b64 v[0:1], v2, s[2:3]
s_lshl_b64 s[0:1], s[0:1], 4
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s6, s0
s_addc_u32 s1, s7, s1
s_waitcnt vmcnt(0)
global_store_b64 v2, v[0:1], s[0:1]
global_load_b64 v[0:1], v2, s[2:3] offset:8
s_waitcnt vmcnt(0)
global_store_b64 v2, v[0:1], s[0:1] offset:8
.LBB1_19:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8fftshiftiP15HIP_vector_typeIdLj2EES1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z8fftshiftiP15HIP_vector_typeIdLj2EES1_, .Lfunc_end1-_Z8fftshiftiP15HIP_vector_typeIdLj2EES1_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z5del2AiP15HIP_vector_typeIdLj2EES1_
.globl _Z5del2AiP15HIP_vector_typeIdLj2EES1_
.p2align 8
.type _Z5del2AiP15HIP_vector_typeIdLj2EES1_,@function
_Z5del2AiP15HIP_vector_typeIdLj2EES1_:
s_load_b32 s2, s[0:1], 0x0
s_max_u32 s3, s14, s15
s_waitcnt lgkmcnt(0)
s_cmp_ge_u32 s3, s2
s_cbranch_scc1 .LBB2_2
s_lshr_b32 s3, s2, 31
v_cvt_f64_u32_e32 v[0:1], s15
s_add_i32 s3, s2, s3
v_cvt_f64_u32_e32 v[4:5], s14
s_ashr_i32 s3, s3, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_sub_i32 s3, 0, s3
v_cvt_f64_i32_e32 v[2:3], s3
s_clause 0x1
s_load_b32 s3, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x8
s_mov_b32 s1, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s0, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s0, s14
s_lshl_b64 s[0:1], s[0:1], 4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
s_add_u32 s4, s4, s0
s_addc_u32 s5, s5, s1
s_add_u32 s0, s6, s0
s_load_b64 s[8:9], s[4:5], 0x0
s_addc_u32 s1, s7, s1
v_add_f64 v[0:1], v[0:1], v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[2:3], v[4:5], v[2:3]
v_mul_f64 v[0:1], v[0:1], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_fma_f64 v[0:1], v[2:3], -v[2:3], -v[0:1]
v_cvt_f64_i32_e32 v[2:3], s2
s_mul_i32 s2, s2, s2
s_waitcnt lgkmcnt(0)
v_mul_f64 v[4:5], v[0:1], s[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[6:7], null, v[2:3], v[2:3], v[4:5]
v_div_scale_f64 v[12:13], vcc_lo, v[4:5], v[2:3], v[4:5]
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_mul_f64 v[10:11], v[12:13], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], -v[6:7], v[10:11], v[12:13]
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[4:5], v[6:7], v[2:3], v[4:5]
v_div_scale_f64 v[6:7], null, v[2:3], v[2:3], v[4:5]
v_div_scale_f64 v[12:13], vcc_lo, v[4:5], v[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[10:11], v[12:13], v[8:9]
v_fma_f64 v[6:7], -v[6:7], v[10:11], v[12:13]
v_mov_b32_e32 v12, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[10:11]
v_div_fixup_f64 v[2:3], v[6:7], v[2:3], v[4:5]
v_cvt_f64_i32_e32 v[4:5], s2
global_store_b64 v12, v[2:3], s[0:1]
global_load_b64 v[2:3], v12, s[4:5] offset:8
s_waitcnt vmcnt(0)
v_mul_f64 v[0:1], v[0:1], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[2:3], null, v[4:5], v[4:5], v[0:1]
v_rcp_f64_e32 v[6:7], v[2:3]
s_waitcnt_depctr 0xfff
v_fma_f64 v[8:9], -v[2:3], v[6:7], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_fma_f64 v[8:9], -v[2:3], v[6:7], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_div_scale_f64 v[8:9], vcc_lo, v[0:1], v[4:5], v[0:1]
v_mul_f64 v[10:11], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], -v[2:3], v[10:11], v[8:9]
v_div_fmas_f64 v[2:3], v[2:3], v[6:7], v[10:11]
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f64 v[0:1], v[2:3], v[4:5], v[0:1]
global_store_b64 v12, v[0:1], s[0:1] offset:8
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5del2AiP15HIP_vector_typeIdLj2EES1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z5del2AiP15HIP_vector_typeIdLj2EES1_, .Lfunc_end2-_Z5del2AiP15HIP_vector_typeIdLj2EES1_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6updateidddidP15HIP_vector_typeIdLj2EES1_S1_
.globl _Z6updateidddidP15HIP_vector_typeIdLj2EES1_S1_
.p2align 8
.type _Z6updateidddidP15HIP_vector_typeIdLj2EES1_S1_,@function
_Z6updateidddidP15HIP_vector_typeIdLj2EES1_S1_:
s_load_b32 s2, s[0:1], 0x0
s_max_u32 s3, s14, s15
s_waitcnt lgkmcnt(0)
s_cmp_ge_u32 s3, s2
s_cbranch_scc1 .LBB3_2
s_clause 0x3
s_load_b32 s2, s[0:1], 0x20
s_load_b128 s[16:19], s[0:1], 0x8
s_load_b256 s[4:11], s[0:1], 0x28
s_load_b64 s[12:13], s[0:1], 0x18
s_mov_b32 s21, 0x401921fb
s_mov_b32 s20, 0x54442d18
s_load_b32 s0, s[0:1], 0x48
s_mov_b32 s1, 0
s_waitcnt lgkmcnt(0)
v_div_scale_f64 v[4:5], null, s[4:5], s[4:5], s[20:21]
v_cvt_f64_i32_e32 v[0:1], s2
s_mul_i32 s0, s0, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s0, s14
s_lshl_b64 s[14:15], s[0:1], 4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
s_add_u32 s6, s6, s14
s_addc_u32 s7, s7, s15
s_add_u32 s8, s8, s14
s_addc_u32 s9, s9, s15
v_rcp_f64_e32 v[8:9], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[2:3], null, v[0:1], v[0:1], s[16:17]
v_div_scale_f64 v[14:15], vcc_lo, s[16:17], v[0:1], s[16:17]
v_rcp_f64_e32 v[6:7], v[2:3]
s_waitcnt_depctr 0xfff
v_fma_f64 v[12:13], -v[4:5], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
v_fma_f64 v[10:11], -v[2:3], v[6:7], 1.0
v_fma_f64 v[12:13], -v[4:5], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7]
v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[2:3], v[6:7], 1.0
v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7]
v_div_scale_f64 v[10:11], s2, s[20:21], s[4:5], s[20:21]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[12:13], v[14:15], v[6:7]
v_mul_f64 v[16:17], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[2:3], -v[2:3], v[12:13], v[14:15]
v_fma_f64 v[4:5], -v[4:5], v[16:17], v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[2:3], v[2:3], v[6:7], v[12:13]
s_mov_b32 vcc_lo, s2
s_load_b128 s[0:3], s[8:9], 0x0
v_div_fmas_f64 v[4:5], v[4:5], v[8:9], v[16:17]
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v7, s1 :: v_dual_mov_b32 v6, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_fma_f64 v[6:7], -s[2:3], s[18:19], v[6:7]
s_load_b128 s[0:3], s[6:7], 0x0
v_div_fixup_f64 v[12:13], v[2:3], v[0:1], s[16:17]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[8:9], v[4:5], s[4:5], s[20:21]
s_waitcnt lgkmcnt(0)
v_mul_f64 v[4:5], s[2:3], s[2:3]
v_dual_mov_b32 v11, s1 :: v_dual_mov_b32 v10, s0
v_fma_f64 v[10:11], s[2:3], s[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f64 v[6:7], v[8:9], v[6:7]
v_fma_f64 v[4:5], s[0:1], s[0:1], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[8:9], v[6:7], s[0:1]
v_fma_f64 v[0:1], -v[10:11], v[4:5], v[6:7]
v_mov_b32_e32 v10, 0
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[0:1], v[12:13], v[0:1], s[0:1]
s_add_u32 s0, s10, s14
s_addc_u32 s1, s11, s15
global_store_b64 v10, v[0:1], s[0:1]
s_clause 0x1
global_load_b128 v[0:3], v10, s[8:9]
global_load_b128 v[4:7], v10, s[6:7]
s_waitcnt vmcnt(1)
v_fma_f64 v[0:1], v[0:1], s[18:19], v[2:3]
s_waitcnt vmcnt(0)
v_mul_f64 v[2:3], v[4:5], v[4:5]
v_fma_f64 v[4:5], -v[4:5], s[12:13], v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[0:1], v[8:9], v[0:1]
v_fma_f64 v[2:3], v[6:7], v[6:7], v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[0:1], v[8:9], v[0:1], v[6:7]
v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[0:1], v[12:13], v[0:1], v[6:7]
global_store_b64 v10, v[0:1], s[0:1] offset:8
.LBB3_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6updateidddidP15HIP_vector_typeIdLj2EES1_S1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 328
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 22
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z6updateidddidP15HIP_vector_typeIdLj2EES1_S1_, .Lfunc_end3-_Z6updateidddidP15HIP_vector_typeIdLj2EES1_S1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6assigniP15HIP_vector_typeIdLj2EES1_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z6assigniP15HIP_vector_typeIdLj2EES1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8fftshiftiP15HIP_vector_typeIdLj2EES1_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8fftshiftiP15HIP_vector_typeIdLj2EES1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5del2AiP15HIP_vector_typeIdLj2EES1_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5del2AiP15HIP_vector_typeIdLj2EES1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .offset: 72
.size: 4
.value_kind: hidden_block_count_x
- .offset: 76
.size: 4
.value_kind: hidden_block_count_y
- .offset: 80
.size: 4
.value_kind: hidden_block_count_z
- .offset: 84
.size: 2
.value_kind: hidden_group_size_x
- .offset: 86
.size: 2
.value_kind: hidden_group_size_y
- .offset: 88
.size: 2
.value_kind: hidden_group_size_z
- .offset: 90
.size: 2
.value_kind: hidden_remainder_x
- .offset: 92
.size: 2
.value_kind: hidden_remainder_y
- .offset: 94
.size: 2
.value_kind: hidden_remainder_z
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 136
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 328
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6updateidddidP15HIP_vector_typeIdLj2EES1_S1_
.private_segment_fixed_size: 0
.sgpr_count: 24
.sgpr_spill_count: 0
.symbol: _Z6updateidddidP15HIP_vector_typeIdLj2EES1_S1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //
// CasAES128_CUDA.c
// CasAES128_CUDA
// Created by Carter McCardwell on 11/11/14.
//
#include <stdint.h>
#include <stdio.h>
#include <time.h>
#include <string.h>
#include <cuda_runtime.h>
struct timing_pair{
long time;
long times[4];
char cipher[16];
char hits[10][4][4];
//long memory_usage;
//int ctx_delta;
//unsigned long tp_delta;
//unsigned short cp_delta;
};
const int Nb_h = 4;
const int Nr_h = 10;
const int Nk_h = 4;
const uint8_t s_h[256]=
{
0x63, 0x7C, 0x77, 0x7B, 0xF2, 0x6B, 0x6F, 0xC5, 0x30, 0x01, 0x67, 0x2B, 0xFE, 0xD7, 0xAB, 0x76,
0xCA, 0x82, 0xC9, 0x7D, 0xFA, 0x59, 0x47, 0xF0, 0xAD, 0xD4, 0xA2, 0xAF, 0x9C, 0xA4, 0x72, 0xC0,
0xB7, 0xFD, 0x93, 0x26, 0x36, 0x3F, 0xF7, 0xCC, 0x34, 0xA5, 0xE5, 0xF1, 0x71, 0xD8, 0x31, 0x15,
0x04, 0xC7, 0x23, 0xC3, 0x18, 0x96, 0x05, 0x9A, 0x07, 0x12, 0x80, 0xE2, 0xEB, 0x27, 0xB2, 0x75,
0x09, 0x83, 0x2C, 0x1A, 0x1B, 0x6E, 0x5A, 0xA0, 0x52, 0x3B, 0xD6, 0xB3, 0x29, 0xE3, 0x2F, 0x84,
0x53, 0xD1, 0x00, 0xED, 0x20, 0xFC, 0xB1, 0x5B, 0x6A, 0xCB, 0xBE, 0x39, 0x4A, 0x4C, 0x58, 0xCF,
0xD0, 0xEF, 0xAA, 0xFB, 0x43, 0x4D, 0x33, 0x85, 0x45, 0xF9, 0x02, 0x7F, 0x50, 0x3C, 0x9F, 0xA8,
0x51, 0xA3, 0x40, 0x8F, 0x92, 0x9D, 0x38, 0xF5, 0xBC, 0xB6, 0xDA, 0x21, 0x10, 0xFF, 0xF3, 0xD2,
0xCD, 0x0C, 0x13, 0xEC, 0x5F, 0x97, 0x44, 0x17, 0xC4, 0xA7, 0x7E, 0x3D, 0x64, 0x5D, 0x19, 0x73,
0x60, 0x81, 0x4F, 0xDC, 0x22, 0x2A, 0x90, 0x88, 0x46, 0xEE, 0xB8, 0x14, 0xDE, 0x5E, 0x0B, 0xDB,
0xE0, 0x32, 0x3A, 0x0A, 0x49, 0x06, 0x24, 0x5C, 0xC2, 0xD3, 0xAC, 0x62, 0x91, 0x95, 0xE4, 0x79,
0xE7, 0xC8, 0x37, 0x6D, 0x8D, 0xD5, 0x4E, 0xA9, 0x6C, 0x56, 0xF4, 0xEA, 0x65, 0x7A, 0xAE, 0x08,
0xBA, 0x78, 0x25, 0x2E, 0x1C, 0xA6, 0xB4, 0xC6, 0xE8, 0xDD, 0x74, 0x1F, 0x4B, 0xBD, 0x8B, 0x8A,
0x70, 0x3E, 0xB5, 0x66, 0x48, 0x03, 0xF6, 0x0E, 0x61, 0x35, 0x57, 0xB9, 0x86, 0xC1, 0x1D, 0x9E,
0xE1, 0xF8, 0x98, 0x11, 0x69, 0xD9, 0x8E, 0x94, 0x9B, 0x1E, 0x87, 0xE9, 0xCE, 0x55, 0x28, 0xDF,
0x8C, 0xA1, 0x89, 0x0D, 0xBF, 0xE6, 0x42, 0x68, 0x41, 0x99, 0x2D, 0x0F, 0xB0, 0x54, 0xBB, 0x16
};
uint8_t Rcon_h[256] = {
0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a,
0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef, 0xc5, 0x91, 0x39,
0x72, 0xe4, 0xd3, 0xbd, 0x61, 0xc2, 0x9f, 0x25, 0x4a, 0x94, 0x33, 0x66, 0xcc, 0x83, 0x1d, 0x3a,
0x74, 0xe8, 0xcb, 0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8,
0xab, 0x4d, 0x9a, 0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef,
0xc5, 0x91, 0x39, 0x72, 0xe4, 0xd3, 0xbd, 0x61, 0xc2, 0x9f, 0x25, 0x4a, 0x94, 0x33, 0x66, 0xcc,
0x83, 0x1d, 0x3a, 0x74, 0xe8, 0xcb, 0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b,
0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a, 0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3,
0x7d, 0xfa, 0xef, 0xc5, 0x91, 0x39, 0x72, 0xe4, 0xd3, 0xbd, 0x61, 0xc2, 0x9f, 0x25, 0x4a, 0x94,
0x33, 0x66, 0xcc, 0x83, 0x1d, 0x3a, 0x74, 0xe8, 0xcb, 0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20,
0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a, 0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35,
0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef, 0xc5, 0x91, 0x39, 0x72, 0xe4, 0xd3, 0xbd, 0x61, 0xc2, 0x9f,
0x25, 0x4a, 0x94, 0x33, 0x66, 0xcc, 0x83, 0x1d, 0x3a, 0x74, 0xe8, 0xcb, 0x8d, 0x01, 0x02, 0x04,
0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a, 0x2f, 0x5e, 0xbc, 0x63,
0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef, 0xc5, 0x91, 0x39, 0x72, 0xe4, 0xd3, 0xbd,
0x61, 0xc2, 0x9f, 0x25, 0x4a, 0x94, 0x33, 0x66, 0xcc, 0x83, 0x1d, 0x3a, 0x74, 0xe8, 0xcb, 0x8d
};
__constant__ uint8_t s[256];
__constant__ int Nb;
__constant__ int Nr;
__constant__ int Nk;
__constant__ uint32_t ek[44];
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void cudaDevAssist(cudaError_t code, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"cudaDevAssistant: %s %d\n", cudaGetErrorString(code), line);
if (abort) exit(code);
}
}
uint32_t sw(uint32_t word)
{
union {
uint32_t word;
uint8_t bytes[4];
} subWord __attribute__ ((aligned));
subWord.word = word;
subWord.bytes[3] = s_h[subWord.bytes[3]];
subWord.bytes[2] = s_h[subWord.bytes[2]];
subWord.bytes[1] = s_h[subWord.bytes[1]];
subWord.bytes[0] = s_h[subWord.bytes[0]];
return subWord.word;
}
__device__ void sb(uint8_t* in)
{
for (int i = 0; i < 16; i++) { in[i] = s[in[i]]; }
}
__device__ void mc(uint8_t* arr)
{
for (int i = 0; i < 4; i++)
{
uint8_t a[4];
uint8_t b[4];
uint8_t c;
uint8_t h;
for(c=0;c<4;c++) {
a[c] = arr[(4*c+i)];
h = (uint8_t)((signed char)arr[(4*c+i)] >> 7);
b[c] = arr[(4*c+i)] << 1;
b[c] ^= 0x1B & h;
}
arr[(i)] = b[0] ^ a[3] ^ a[2] ^ b[1] ^ a[1];
arr[(4+i)] = b[1] ^ a[0] ^ a[3] ^ b[2] ^ a[2];
arr[(8+i)] = b[2] ^ a[1] ^ a[0] ^ b[3] ^ a[3];
arr[(12+i)] = b[3] ^ a[2] ^ a[1] ^ b[0] ^ a[0];
}
}
__device__ void sr(uint8_t* arr)
{
uint8_t out[16];
//On per-row basis (+1 shift ea row)
//Row 1
out[0] = arr[0];
out[1] = arr[1];
out[2] = arr[2];
out[3] = arr[3];
//Row 2
out[4] = arr[5];
out[5] = arr[6];
out[6] = arr[7];
out[7] = arr[4];
//Row 3
out[8] = arr[10];
out[9] = arr[11];
out[10] = arr[8];
out[11] = arr[9];
//Row 4
out[12] = arr[15];
out[13] = arr[12];
out[14] = arr[13];
out[15] = arr[14];
for (int i = 0; i < 16; i++)
{
arr[i] = out[i];
}
}
uint32_t rw(uint32_t word)
{
union {
uint8_t bytes[4];
uint32_t word;
} subWord __attribute__ ((aligned));
subWord.word = word;
uint8_t B0 = subWord.bytes[3], B1 = subWord.bytes[2], B2 = subWord.bytes[1], B3 = subWord.bytes[0];
subWord.bytes[3] = B1; //0
subWord.bytes[2] = B2; //1
subWord.bytes[1] = B3; //2
subWord.bytes[0] = B0; //3
return subWord.word;
}
void K_Exp(uint8_t* pk, uint32_t* out)
{
int i = 0;
union {
uint8_t bytes[4];
uint32_t word;
} temp __attribute__ ((aligned));
union {
uint8_t bytes[4];
uint32_t word;
} univar[44] __attribute__ ((aligned));
for (i = 0; i < Nk_h; i++)
{
univar[i].bytes[3] = pk[i*4];
univar[i].bytes[2] = pk[i*4+1];
univar[i].bytes[1] = pk[i*4+2];
univar[i].bytes[0] = pk[i*4+3];
}
for (i = Nk_h; i < Nb_h*(Nr_h+1); i++)
{
temp.word = univar[i-1].word;
if (i % Nk_h == 0)
{
temp.word = (sw(rw(temp.word)));
temp.bytes[3] = temp.bytes[3] ^ (Rcon_h[i/Nk_h]);
}
else if (Nk_h > 6 && i % Nk_h == 4)
{
temp.word = sw(temp.word);
}
if (i-4 % Nk_h == 0)
{
temp.word = sw(temp.word);
}
univar[i].word = univar[i-Nk_h].word ^ temp.word;
}
for (i = 0; i < 44; i++)
{
out[i] = univar[i].word;
}
}
__device__ void ark(uint8_t* state, int strD)
{
union {
uint32_t word;
uint8_t bytes[4];
} zero __attribute__ ((aligned));
union {
uint32_t word;
uint8_t bytes[4];
} one __attribute__ ((aligned));
union {
uint32_t word;
uint8_t bytes[4];
} two __attribute__ ((aligned));
union {
uint32_t word;
uint8_t bytes[4];
} three __attribute__ ((aligned));
zero.word = ek[strD];
one.word = ek[strD+1];
two.word = ek[strD+2];
three.word = ek[strD+3];
state[0] = state[0] ^ zero.bytes[3];
state[4] = state[4] ^ zero.bytes[2];
state[8] = state[8] ^ zero.bytes[1];
state[12] = state[12] ^ zero.bytes[0];
state[1] = state[1] ^ one.bytes[3];
state[5] = state[5] ^ one.bytes[2];
state[9] = state[9] ^ one.bytes[1];
state[13] = state[13] ^ one.bytes[0];
state[2] = state[2] ^ two.bytes[3];
state[6] = state[6] ^ two.bytes[2];
state[10] = state[10] ^ two.bytes[1];
state[14] = state[14] ^ two.bytes[0];
state[3] = state[3] ^ three.bytes[3];
state[7] = state[7] ^ three.bytes[2];
state[11] = state[11] ^ three.bytes[1];
state[15] = state[15] ^ three.bytes[0];
}
__global__ void cudaRunner(uint8_t *in)
{
uint8_t state[16];
int localid = blockDim.x * blockIdx.x + threadIdx.x; //Data is shifted by 16 * ID of worker
for (int i = 0; i < 16; i++) { state[i] = in[(localid*16)+i]; }
ark(state, 0);
for (int i = 1; i < Nr; i++)
{
sb(state);
sr(state);
mc(state);
ark(state, i*Nb);
}
sb(state);
sr(state);
ark(state, Nr*Nb);
for (int i = 0; i < 16; i++) { in[(localid*16)+i] = state[i]; }
}
long AES_CUDA(char* in_cypher, char* cypher, char* in_key)
{
clock_t c_start, c_stop;
c_start = clock();
uint8_t key[16];
uint32_t ek_h[44];
uint8_t states[16] = { 0x00 };
for (int i = 0; i < 16; i++)
{
states[i] = in_cypher[i];
key[i] = in_key[i];
}
K_Exp(key, ek_h);
//send constants to GPU
cudaSetDevice(0);
cudaDevAssist(cudaMemcpyToSymbol(Nk, &Nk_h, sizeof(int), 0, cudaMemcpyHostToDevice), 535, true);
cudaDevAssist(cudaMemcpyToSymbol(Nr, &Nr_h, sizeof(int), 0, cudaMemcpyHostToDevice), 543, true);
cudaDevAssist(cudaMemcpyToSymbol(Nb, &Nb_h, sizeof(int), 0, cudaMemcpyHostToDevice), 903, true);
cudaDevAssist(cudaMemcpyToSymbol(s, &s_h, 256*sizeof(uint8_t), 0, cudaMemcpyHostToDevice), 920, true);
cudaDevAssist(cudaMemcpyToSymbol(ek, &ek_h, 44*sizeof(uint32_t), 0, cudaMemcpyHostToDevice), 823, true);
cudaThreadSynchronize();
uint8_t *devState = NULL;
cudaDevAssist(cudaMalloc((void**)&devState, 16*sizeof(uint8_t)), 425, true);
//arrange data correctly
uint8_t temp[16];
memcpy(&temp[0], &states[0], sizeof(uint8_t));
memcpy(&temp[4], &states[1], sizeof(uint8_t));
memcpy(&temp[8], &states[2], sizeof(uint8_t));
memcpy(&temp[12], &states[3], sizeof(uint8_t));
memcpy(&temp[1], &states[4], sizeof(uint8_t));
memcpy(&temp[5], &states[5], sizeof(uint8_t));
memcpy(&temp[9], &states[6], sizeof(uint8_t));
memcpy(&temp[13], &states[7], sizeof(uint8_t));
memcpy(&temp[2], &states[8], sizeof(uint8_t));
memcpy(&temp[6], &states[9], sizeof(uint8_t));
memcpy(&temp[10], &states[10], sizeof(uint8_t));
memcpy(&temp[14], &states[11], sizeof(uint8_t));
memcpy(&temp[3], &states[12], sizeof(uint8_t));
memcpy(&temp[7], &states[13], sizeof(uint8_t));
memcpy(&temp[11], &states[14], sizeof(uint8_t));
memcpy(&temp[15], &states[15], sizeof(uint8_t));
for (int c = 0; c < 16; c++) { memcpy(&states[c], &temp[c], sizeof(uint8_t)); }
cudaDevAssist(cudaMemcpy(devState, states, 16*sizeof(uint8_t), cudaMemcpyHostToDevice), 426, true);
cudaDevAssist(cudaDeviceSynchronize(), 268, true);
cudaRunner<<<1,1>>>(devState);
cudaDevAssist(cudaDeviceSynchronize(), 270, true);
cudaDevAssist(cudaMemcpy(states, devState, 16*sizeof(uint8_t), cudaMemcpyDeviceToHost), 431, true);
memcpy(&cypher[0], &states[0], sizeof(uint8_t));
memcpy(&cypher[4], &states[1], sizeof(uint8_t));
memcpy(&cypher[8], &states[2], sizeof(uint8_t));
memcpy(&cypher[12], &states[3], sizeof(uint8_t));
memcpy(&cypher[1], &states[4], sizeof(uint8_t));
memcpy(&cypher[5], &states[5], sizeof(uint8_t));
memcpy(&cypher[9], &states[6], sizeof(uint8_t));
memcpy(&cypher[13], &states[7], sizeof(uint8_t));
memcpy(&cypher[2], &states[8], sizeof(uint8_t));
memcpy(&cypher[6], &states[9], sizeof(uint8_t));
memcpy(&cypher[10], &states[10], sizeof(uint8_t));
memcpy(&cypher[14], &states[11], sizeof(uint8_t));
memcpy(&cypher[3], &states[12], sizeof(uint8_t));
memcpy(&cypher[7], &states[13], sizeof(uint8_t));
memcpy(&cypher[11], &states[14], sizeof(uint8_t));
memcpy(&cypher[15], &states[15], sizeof(uint8_t));
c_stop = clock();
float diff = (((float)c_stop - (float)c_start) / CLOCKS_PER_SEC ) * 1000;
cudaFree(devState);
cudaDeviceReset();
return diff;
} | .file "tmpxft_0016337e_00000000-6_CasAES128_CUDA_NOUNAR_asFUNCT.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2068:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z2swj
.type _Z2swj, @function
_Z2swj:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edi, %edx
leaq _ZL3s_h(%rip), %rcx
movl %edi, %eax
shrl $24, %eax
cltq
movzbl (%rcx,%rax), %eax
movl %edi, %esi
shrl $16, %esi
movzbl %sil, %esi
movzbl (%rcx,%rsi), %esi
sall $16, %esi
sall $24, %eax
orl %esi, %eax
movzbl %dh, %esi
movzbl (%rcx,%rsi), %ebx
movb %bl, %ah
movzbl %dil, %edx
movb (%rcx,%rdx), %al
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z2swj, .-_Z2swj
.globl _Z2sbPh
.type _Z2sbPh, @function
_Z2sbPh:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z2sbPh, .-_Z2sbPh
.globl _Z2mcPh
.type _Z2mcPh, @function
_Z2mcPh:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z2mcPh, .-_Z2mcPh
.globl _Z2srPh
.type _Z2srPh, @function
_Z2srPh:
.LFB2061:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z2srPh, .-_Z2srPh
.globl _Z2rwj
.type _Z2rwj, @function
_Z2rwj:
.LFB2062:
.cfi_startproc
endbr64
movl %edi, %edx
movl %edi, %eax
shrl $16, %eax
movzbl %dh, %ecx
sall $16, %ecx
sall $24, %eax
orl %ecx, %eax
movb %dl, %ah
shrl $24, %edx
movb %dl, %al
ret
.cfi_endproc
.LFE2062:
.size _Z2rwj, .-_Z2rwj
.globl _Z5K_ExpPhPj
.type _Z5K_ExpPhPj, @function
_Z5K_ExpPhPj:
.LFB2063:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $192, %rsp
.cfi_def_cfa_offset 240
movq %rsi, %r13
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
movq %rsp, %rbp
leaq 16(%rsp), %rcx
movq %rbp, %rax
.L13:
movzbl (%rdi), %edx
movb %dl, 3(%rax)
movzbl 1(%rdi), %edx
movb %dl, 2(%rax)
movzbl 2(%rdi), %edx
movb %dl, 1(%rax)
movzbl 3(%rdi), %edx
movb %dl, (%rax)
addq $4, %rdi
addq $4, %rax
cmpq %rcx, %rax
jne .L13
movl $4, %ebx
leaq Rcon_h(%rip), %r14
jmp .L18
.L15:
xorl (%r12), %eax
movl %eax, 16(%r12)
addl $1, %ebx
addq $4, %rbp
cmpl $44, %ebx
je .L24
.L18:
movq %rbp, %r12
movl 12(%rbp), %edi
movl %edi, %eax
testb $3, %bl
jne .L15
call _Z2rwj
movl %eax, %edi
call _Z2swj
leal 3(%rbx), %edx
testl %ebx, %ebx
cmovns %ebx, %edx
sarl $2, %edx
movslq %edx, %rdx
movl %eax, %edi
shrl $24, %edi
xorb (%r14,%rdx), %dil
sall $24, %edi
andl $16777215, %eax
orl %eax, %edi
movl %edi, %eax
testl %ebx, %ebx
jne .L15
call _Z2swj
xorl 0(%rbp), %eax
movl %eax, 16(%rbp)
addl $1, %ebx
addq $4, %rbp
jmp .L18
.L24:
movl $0, %eax
.L17:
movl (%rsp,%rax), %edx
movl %edx, 0(%r13,%rax)
addq $4, %rax
cmpq $176, %rax
jne .L17
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $192, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size _Z5K_ExpPhPj, .-_Z5K_ExpPhPj
.globl _Z3arkPhi
.type _Z3arkPhi, @function
_Z3arkPhi:
.LFB2064:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2064:
.size _Z3arkPhi, .-_Z3arkPhi
.globl _Z30__device_stub__Z10cudaRunnerPhPh
.type _Z30__device_stub__Z10cudaRunnerPhPh, @function
_Z30__device_stub__Z10cudaRunnerPhPh:
.LFB2090:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L32
.L28:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10cudaRunnerPh(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L28
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z30__device_stub__Z10cudaRunnerPhPh, .-_Z30__device_stub__Z10cudaRunnerPhPh
.globl _Z10cudaRunnerPh
.type _Z10cudaRunnerPh, @function
_Z10cudaRunnerPh:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10cudaRunnerPhPh
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z10cudaRunnerPh, .-_Z10cudaRunnerPh
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "cudaDevAssistant: %s %d\n"
.text
.globl _Z8AES_CUDAPcS_S_
.type _Z8AES_CUDAPcS_S_, @function
_Z8AES_CUDAPcS_S_:
.LFB2065:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $296, %rsp
.cfi_def_cfa_offset 336
movq %rdi, %rbp
movq %rsi, %r12
movq %rdx, %rbx
movq %fs:40, %rax
movq %rax, 280(%rsp)
xorl %eax, %eax
call clock@PLT
movq %rax, %r13
movq $0, 240(%rsp)
movq $0, 248(%rsp)
movl $0, %eax
.L37:
movzbl 0(%rbp,%rax), %edx
movb %dl, 240(%rsp,%rax)
movzbl (%rbx,%rax), %edx
movb %dl, 224(%rsp,%rax)
addq $1, %rax
cmpq $16, %rax
jne .L37
leaq 48(%rsp), %rsi
leaq 224(%rsp), %rdi
call _Z5K_ExpPhPj
movl $0, %edi
call cudaSetDevice@PLT
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL4Nk_h(%rip), %rsi
leaq _ZL2Nk(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L54
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL4Nr_h(%rip), %rsi
leaq _ZL2Nr(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L55
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL4Nb_h(%rip), %rsi
leaq _ZL2Nb(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L56
movl $1, %r8d
movl $0, %ecx
movl $256, %edx
leaq _ZL3s_h(%rip), %rsi
leaq _ZL1s(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L57
leaq 48(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $176, %edx
leaq _ZL2ek(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L58
call cudaThreadSynchronize@PLT
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L59
movzbl 240(%rsp), %eax
movb %al, 256(%rsp)
movzbl 241(%rsp), %eax
movb %al, 260(%rsp)
movzbl 242(%rsp), %eax
movb %al, 264(%rsp)
movzbl 243(%rsp), %eax
movb %al, 268(%rsp)
movzbl 244(%rsp), %eax
movb %al, 257(%rsp)
movzbl 245(%rsp), %eax
movb %al, 261(%rsp)
movzbl 246(%rsp), %eax
movb %al, 265(%rsp)
movzbl 247(%rsp), %eax
movb %al, 269(%rsp)
movzbl 248(%rsp), %eax
movb %al, 258(%rsp)
movzbl 249(%rsp), %eax
movb %al, 262(%rsp)
movzbl 250(%rsp), %eax
movb %al, 266(%rsp)
movzbl 251(%rsp), %eax
movb %al, 270(%rsp)
movzbl 252(%rsp), %eax
movb %al, 259(%rsp)
movzbl 253(%rsp), %eax
movb %al, 263(%rsp)
movzbl 254(%rsp), %eax
movb %al, 267(%rsp)
movzbl 255(%rsp), %eax
movb %al, 271(%rsp)
movl $0, %ebx
leaq 256(%rsp), %rbp
.L44:
movl $16, %ecx
cmpq %rcx, %rbx
cmovnb %rbx, %rcx
subq %rbx, %rcx
leaq 0(%rbp,%rbx), %rsi
leaq 240(%rsp,%rbx), %rdi
movl $1, %edx
call __memcpy_chk@PLT
addq $1, %rbx
cmpq $16, %rbx
jne .L44
leaq 240(%rsp), %rsi
movl $1, %ecx
movl $16, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L60
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L61
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L62
.L47:
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L63
leaq 240(%rsp), %rdi
movl $2, %ecx
movl $16, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L64
movzbl 240(%rsp), %eax
movb %al, (%r12)
movzbl 241(%rsp), %eax
movb %al, 4(%r12)
movzbl 242(%rsp), %eax
movb %al, 8(%r12)
movzbl 243(%rsp), %eax
movb %al, 12(%r12)
movzbl 244(%rsp), %eax
movb %al, 1(%r12)
movzbl 245(%rsp), %eax
movb %al, 5(%r12)
movzbl 246(%rsp), %eax
movb %al, 9(%r12)
movzbl 247(%rsp), %eax
movb %al, 13(%r12)
movzbl 248(%rsp), %eax
movb %al, 2(%r12)
movzbl 249(%rsp), %eax
movb %al, 6(%r12)
movzbl 250(%rsp), %eax
movb %al, 10(%r12)
movzbl 251(%rsp), %eax
movb %al, 14(%r12)
movzbl 252(%rsp), %eax
movb %al, 3(%r12)
movzbl 253(%rsp), %eax
movb %al, 7(%r12)
movzbl 254(%rsp), %eax
movb %al, 11(%r12)
movzbl 255(%rsp), %eax
movb %al, 15(%r12)
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssq %r13, %xmm1
subss %xmm1, %xmm0
divss .LC1(%rip), %xmm0
mulss .LC2(%rip), %xmm0
movss %xmm0, 12(%rsp)
movq 16(%rsp), %rdi
call cudaFree@PLT
call cudaDeviceReset@PLT
cvttss2siq 12(%rsp), %rax
movq 280(%rsp), %rdx
subq %fs:40, %rdx
jne .L65
addq $296, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $535, %r8d
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L55:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $543, %r8d
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L56:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $903, %r8d
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L57:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $920, %r8d
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L58:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $823, %r8d
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L59:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $425, %r8d
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L60:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $426, %r8d
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L61:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $268, %r8d
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L62:
movq 16(%rsp), %rdi
call _Z30__device_stub__Z10cudaRunnerPhPh
jmp .L47
.L63:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $270, %r8d
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L64:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $431, %r8d
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L65:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2065:
.size _Z8AES_CUDAPcS_S_, .-_Z8AES_CUDAPcS_S_
.section .rodata.str1.1
.LC3:
.string "_Z10cudaRunnerPh"
.LC4:
.string "s"
.LC5:
.string "Nb"
.LC6:
.string "Nr"
.LC7:
.string "Nk"
.LC8:
.string "ek"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2093:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10cudaRunnerPh(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $256, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1s(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2Nb(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2Nr(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2Nk(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $176, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2ek(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL2ek
.comm _ZL2ek,176,32
.local _ZL2Nk
.comm _ZL2Nk,4,4
.local _ZL2Nr
.comm _ZL2Nr,4,4
.local _ZL2Nb
.comm _ZL2Nb,4,4
.local _ZL1s
.comm _ZL1s,256,32
.globl Rcon_h
.data
.align 32
.type Rcon_h, @object
.size Rcon_h, 256
Rcon_h:
.ascii "\215\001\002\004\b\020 @\200\0336l\330\253M\232/^\274c\306\227"
.ascii "5j\324\263}\372\357\305\2219r\344\323\275a\302\237%J\2243f\314"
.ascii "\203\035:t\350\313\215\001\002\004\b\020 @\200\0336l\330\253"
.ascii "M\232/^\274c\306\2275j\324\263}\372\357\305\2219r\344\323\275"
.ascii "a\302\237%J\2243f\314\203\035:t\350\313\215\001\002\004\b\020"
.ascii " @\200\0336l\330\253M\232/^\274c\306\2275j\324\263}\372\357\305"
.ascii "\2219r\344\323\275a\302\237%J\2243f\314\203\035:t\350\313\215"
.ascii "\001\002\004\b\020 @\200\0336l\330\253M\232/^\274c\306\2275j"
.ascii "\324\263}\372\357\305\2219r\344\323\275a\302\237%J\2243f\314"
.ascii "\203\035:t\350\313\215\001\002\004\b\020 @\200\0336l\330\253"
.ascii "M\232/^\274c\306\2275j\324\263}\372\357\305\2219r\344\323\275"
.ascii "a\302\237%J\2243f\314\203\035:t\350\313\215"
.section .rodata
.align 32
.type _ZL3s_h, @object
.size _ZL3s_h, 256
_ZL3s_h:
.string "c|w{\362ko\3050\001g+\376\327\253v\312\202\311}\372YG\360\255\324\242\257\234\244r\300\267\375\223&6?\367\3144\245\345\361q\3301\025\004\307#\303\030\226\005\232\007\022\200\342\353'\262u\t\203,\032\033nZ\240R;\326\263)\343/\204S\321"
.ascii "\355 \374\261[j\313\2769JLX\317\320\357\252\373CM3\205E\371\002"
.ascii "\177P<\237\250Q\243@\217\222\2358\365\274\266\332!\020\377\363"
.ascii "\322\315\f\023\354_\227D\027\304\247~=d]\031s`\201O\334\"*\220"
.ascii "\210F\356\270\024\336^\013\333\3402:\nI\006$\\\302\323\254b\221"
.ascii "\225\344y\347\3107m\215\325N\251lV\364\352ez\256\b\272x%.\034"
.ascii "\246\264\306\350\335t\037K\275\213\212p>\265fH\003\366\016a5"
.ascii "W\271\206\301\035\236\341\370\230\021i\331\216\224\233\036\207"
.ascii "\351\316U(\337\214\241\211\r\277\346BhA\231-\017\260T\273\026"
.align 4
.type _ZL4Nk_h, @object
.size _ZL4Nk_h, 4
_ZL4Nk_h:
.long 4
.align 4
.type _ZL4Nr_h, @object
.size _ZL4Nr_h, 4
_ZL4Nr_h:
.long 10
.align 4
.type _ZL4Nb_h, @object
.size _ZL4Nb_h, 4
_ZL4Nb_h:
.long 4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1232348160
.align 4
.LC2:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //
// CasAES128_CUDA.c
// CasAES128_CUDA
// Created by Carter McCardwell on 11/11/14.
//
#include <stdint.h>
#include <stdio.h>
#include <time.h>
#include <string.h>
#include <cuda_runtime.h>
struct timing_pair{
long time;
long times[4];
char cipher[16];
char hits[10][4][4];
//long memory_usage;
//int ctx_delta;
//unsigned long tp_delta;
//unsigned short cp_delta;
};
const int Nb_h = 4;
const int Nr_h = 10;
const int Nk_h = 4;
const uint8_t s_h[256]=
{
0x63, 0x7C, 0x77, 0x7B, 0xF2, 0x6B, 0x6F, 0xC5, 0x30, 0x01, 0x67, 0x2B, 0xFE, 0xD7, 0xAB, 0x76,
0xCA, 0x82, 0xC9, 0x7D, 0xFA, 0x59, 0x47, 0xF0, 0xAD, 0xD4, 0xA2, 0xAF, 0x9C, 0xA4, 0x72, 0xC0,
0xB7, 0xFD, 0x93, 0x26, 0x36, 0x3F, 0xF7, 0xCC, 0x34, 0xA5, 0xE5, 0xF1, 0x71, 0xD8, 0x31, 0x15,
0x04, 0xC7, 0x23, 0xC3, 0x18, 0x96, 0x05, 0x9A, 0x07, 0x12, 0x80, 0xE2, 0xEB, 0x27, 0xB2, 0x75,
0x09, 0x83, 0x2C, 0x1A, 0x1B, 0x6E, 0x5A, 0xA0, 0x52, 0x3B, 0xD6, 0xB3, 0x29, 0xE3, 0x2F, 0x84,
0x53, 0xD1, 0x00, 0xED, 0x20, 0xFC, 0xB1, 0x5B, 0x6A, 0xCB, 0xBE, 0x39, 0x4A, 0x4C, 0x58, 0xCF,
0xD0, 0xEF, 0xAA, 0xFB, 0x43, 0x4D, 0x33, 0x85, 0x45, 0xF9, 0x02, 0x7F, 0x50, 0x3C, 0x9F, 0xA8,
0x51, 0xA3, 0x40, 0x8F, 0x92, 0x9D, 0x38, 0xF5, 0xBC, 0xB6, 0xDA, 0x21, 0x10, 0xFF, 0xF3, 0xD2,
0xCD, 0x0C, 0x13, 0xEC, 0x5F, 0x97, 0x44, 0x17, 0xC4, 0xA7, 0x7E, 0x3D, 0x64, 0x5D, 0x19, 0x73,
0x60, 0x81, 0x4F, 0xDC, 0x22, 0x2A, 0x90, 0x88, 0x46, 0xEE, 0xB8, 0x14, 0xDE, 0x5E, 0x0B, 0xDB,
0xE0, 0x32, 0x3A, 0x0A, 0x49, 0x06, 0x24, 0x5C, 0xC2, 0xD3, 0xAC, 0x62, 0x91, 0x95, 0xE4, 0x79,
0xE7, 0xC8, 0x37, 0x6D, 0x8D, 0xD5, 0x4E, 0xA9, 0x6C, 0x56, 0xF4, 0xEA, 0x65, 0x7A, 0xAE, 0x08,
0xBA, 0x78, 0x25, 0x2E, 0x1C, 0xA6, 0xB4, 0xC6, 0xE8, 0xDD, 0x74, 0x1F, 0x4B, 0xBD, 0x8B, 0x8A,
0x70, 0x3E, 0xB5, 0x66, 0x48, 0x03, 0xF6, 0x0E, 0x61, 0x35, 0x57, 0xB9, 0x86, 0xC1, 0x1D, 0x9E,
0xE1, 0xF8, 0x98, 0x11, 0x69, 0xD9, 0x8E, 0x94, 0x9B, 0x1E, 0x87, 0xE9, 0xCE, 0x55, 0x28, 0xDF,
0x8C, 0xA1, 0x89, 0x0D, 0xBF, 0xE6, 0x42, 0x68, 0x41, 0x99, 0x2D, 0x0F, 0xB0, 0x54, 0xBB, 0x16
};
uint8_t Rcon_h[256] = {
0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a,
0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef, 0xc5, 0x91, 0x39,
0x72, 0xe4, 0xd3, 0xbd, 0x61, 0xc2, 0x9f, 0x25, 0x4a, 0x94, 0x33, 0x66, 0xcc, 0x83, 0x1d, 0x3a,
0x74, 0xe8, 0xcb, 0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8,
0xab, 0x4d, 0x9a, 0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef,
0xc5, 0x91, 0x39, 0x72, 0xe4, 0xd3, 0xbd, 0x61, 0xc2, 0x9f, 0x25, 0x4a, 0x94, 0x33, 0x66, 0xcc,
0x83, 0x1d, 0x3a, 0x74, 0xe8, 0xcb, 0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b,
0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a, 0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3,
0x7d, 0xfa, 0xef, 0xc5, 0x91, 0x39, 0x72, 0xe4, 0xd3, 0xbd, 0x61, 0xc2, 0x9f, 0x25, 0x4a, 0x94,
0x33, 0x66, 0xcc, 0x83, 0x1d, 0x3a, 0x74, 0xe8, 0xcb, 0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20,
0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a, 0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35,
0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef, 0xc5, 0x91, 0x39, 0x72, 0xe4, 0xd3, 0xbd, 0x61, 0xc2, 0x9f,
0x25, 0x4a, 0x94, 0x33, 0x66, 0xcc, 0x83, 0x1d, 0x3a, 0x74, 0xe8, 0xcb, 0x8d, 0x01, 0x02, 0x04,
0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a, 0x2f, 0x5e, 0xbc, 0x63,
0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef, 0xc5, 0x91, 0x39, 0x72, 0xe4, 0xd3, 0xbd,
0x61, 0xc2, 0x9f, 0x25, 0x4a, 0x94, 0x33, 0x66, 0xcc, 0x83, 0x1d, 0x3a, 0x74, 0xe8, 0xcb, 0x8d
};
__constant__ uint8_t s[256];
__constant__ int Nb;
__constant__ int Nr;
__constant__ int Nk;
__constant__ uint32_t ek[44];
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void cudaDevAssist(cudaError_t code, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"cudaDevAssistant: %s %d\n", cudaGetErrorString(code), line);
if (abort) exit(code);
}
}
uint32_t sw(uint32_t word)
{
union {
uint32_t word;
uint8_t bytes[4];
} subWord __attribute__ ((aligned));
subWord.word = word;
subWord.bytes[3] = s_h[subWord.bytes[3]];
subWord.bytes[2] = s_h[subWord.bytes[2]];
subWord.bytes[1] = s_h[subWord.bytes[1]];
subWord.bytes[0] = s_h[subWord.bytes[0]];
return subWord.word;
}
__device__ void sb(uint8_t* in)
{
for (int i = 0; i < 16; i++) { in[i] = s[in[i]]; }
}
__device__ void mc(uint8_t* arr)
{
for (int i = 0; i < 4; i++)
{
uint8_t a[4];
uint8_t b[4];
uint8_t c;
uint8_t h;
for(c=0;c<4;c++) {
a[c] = arr[(4*c+i)];
h = (uint8_t)((signed char)arr[(4*c+i)] >> 7);
b[c] = arr[(4*c+i)] << 1;
b[c] ^= 0x1B & h;
}
arr[(i)] = b[0] ^ a[3] ^ a[2] ^ b[1] ^ a[1];
arr[(4+i)] = b[1] ^ a[0] ^ a[3] ^ b[2] ^ a[2];
arr[(8+i)] = b[2] ^ a[1] ^ a[0] ^ b[3] ^ a[3];
arr[(12+i)] = b[3] ^ a[2] ^ a[1] ^ b[0] ^ a[0];
}
}
__device__ void sr(uint8_t* arr)
{
uint8_t out[16];
//On per-row basis (+1 shift ea row)
//Row 1
out[0] = arr[0];
out[1] = arr[1];
out[2] = arr[2];
out[3] = arr[3];
//Row 2
out[4] = arr[5];
out[5] = arr[6];
out[6] = arr[7];
out[7] = arr[4];
//Row 3
out[8] = arr[10];
out[9] = arr[11];
out[10] = arr[8];
out[11] = arr[9];
//Row 4
out[12] = arr[15];
out[13] = arr[12];
out[14] = arr[13];
out[15] = arr[14];
for (int i = 0; i < 16; i++)
{
arr[i] = out[i];
}
}
uint32_t rw(uint32_t word)
{
union {
uint8_t bytes[4];
uint32_t word;
} subWord __attribute__ ((aligned));
subWord.word = word;
uint8_t B0 = subWord.bytes[3], B1 = subWord.bytes[2], B2 = subWord.bytes[1], B3 = subWord.bytes[0];
subWord.bytes[3] = B1; //0
subWord.bytes[2] = B2; //1
subWord.bytes[1] = B3; //2
subWord.bytes[0] = B0; //3
return subWord.word;
}
void K_Exp(uint8_t* pk, uint32_t* out)
{
int i = 0;
union {
uint8_t bytes[4];
uint32_t word;
} temp __attribute__ ((aligned));
union {
uint8_t bytes[4];
uint32_t word;
} univar[44] __attribute__ ((aligned));
for (i = 0; i < Nk_h; i++)
{
univar[i].bytes[3] = pk[i*4];
univar[i].bytes[2] = pk[i*4+1];
univar[i].bytes[1] = pk[i*4+2];
univar[i].bytes[0] = pk[i*4+3];
}
for (i = Nk_h; i < Nb_h*(Nr_h+1); i++)
{
temp.word = univar[i-1].word;
if (i % Nk_h == 0)
{
temp.word = (sw(rw(temp.word)));
temp.bytes[3] = temp.bytes[3] ^ (Rcon_h[i/Nk_h]);
}
else if (Nk_h > 6 && i % Nk_h == 4)
{
temp.word = sw(temp.word);
}
if (i-4 % Nk_h == 0)
{
temp.word = sw(temp.word);
}
univar[i].word = univar[i-Nk_h].word ^ temp.word;
}
for (i = 0; i < 44; i++)
{
out[i] = univar[i].word;
}
}
__device__ void ark(uint8_t* state, int strD)
{
union {
uint32_t word;
uint8_t bytes[4];
} zero __attribute__ ((aligned));
union {
uint32_t word;
uint8_t bytes[4];
} one __attribute__ ((aligned));
union {
uint32_t word;
uint8_t bytes[4];
} two __attribute__ ((aligned));
union {
uint32_t word;
uint8_t bytes[4];
} three __attribute__ ((aligned));
zero.word = ek[strD];
one.word = ek[strD+1];
two.word = ek[strD+2];
three.word = ek[strD+3];
state[0] = state[0] ^ zero.bytes[3];
state[4] = state[4] ^ zero.bytes[2];
state[8] = state[8] ^ zero.bytes[1];
state[12] = state[12] ^ zero.bytes[0];
state[1] = state[1] ^ one.bytes[3];
state[5] = state[5] ^ one.bytes[2];
state[9] = state[9] ^ one.bytes[1];
state[13] = state[13] ^ one.bytes[0];
state[2] = state[2] ^ two.bytes[3];
state[6] = state[6] ^ two.bytes[2];
state[10] = state[10] ^ two.bytes[1];
state[14] = state[14] ^ two.bytes[0];
state[3] = state[3] ^ three.bytes[3];
state[7] = state[7] ^ three.bytes[2];
state[11] = state[11] ^ three.bytes[1];
state[15] = state[15] ^ three.bytes[0];
}
__global__ void cudaRunner(uint8_t *in)
{
uint8_t state[16];
int localid = blockDim.x * blockIdx.x + threadIdx.x; //Data is shifted by 16 * ID of worker
for (int i = 0; i < 16; i++) { state[i] = in[(localid*16)+i]; }
ark(state, 0);
for (int i = 1; i < Nr; i++)
{
sb(state);
sr(state);
mc(state);
ark(state, i*Nb);
}
sb(state);
sr(state);
ark(state, Nr*Nb);
for (int i = 0; i < 16; i++) { in[(localid*16)+i] = state[i]; }
}
long AES_CUDA(char* in_cypher, char* cypher, char* in_key)
{
clock_t c_start, c_stop;
c_start = clock();
uint8_t key[16];
uint32_t ek_h[44];
uint8_t states[16] = { 0x00 };
for (int i = 0; i < 16; i++)
{
states[i] = in_cypher[i];
key[i] = in_key[i];
}
K_Exp(key, ek_h);
//send constants to GPU
cudaSetDevice(0);
cudaDevAssist(cudaMemcpyToSymbol(Nk, &Nk_h, sizeof(int), 0, cudaMemcpyHostToDevice), 535, true);
cudaDevAssist(cudaMemcpyToSymbol(Nr, &Nr_h, sizeof(int), 0, cudaMemcpyHostToDevice), 543, true);
cudaDevAssist(cudaMemcpyToSymbol(Nb, &Nb_h, sizeof(int), 0, cudaMemcpyHostToDevice), 903, true);
cudaDevAssist(cudaMemcpyToSymbol(s, &s_h, 256*sizeof(uint8_t), 0, cudaMemcpyHostToDevice), 920, true);
cudaDevAssist(cudaMemcpyToSymbol(ek, &ek_h, 44*sizeof(uint32_t), 0, cudaMemcpyHostToDevice), 823, true);
cudaThreadSynchronize();
uint8_t *devState = NULL;
cudaDevAssist(cudaMalloc((void**)&devState, 16*sizeof(uint8_t)), 425, true);
//arrange data correctly
uint8_t temp[16];
memcpy(&temp[0], &states[0], sizeof(uint8_t));
memcpy(&temp[4], &states[1], sizeof(uint8_t));
memcpy(&temp[8], &states[2], sizeof(uint8_t));
memcpy(&temp[12], &states[3], sizeof(uint8_t));
memcpy(&temp[1], &states[4], sizeof(uint8_t));
memcpy(&temp[5], &states[5], sizeof(uint8_t));
memcpy(&temp[9], &states[6], sizeof(uint8_t));
memcpy(&temp[13], &states[7], sizeof(uint8_t));
memcpy(&temp[2], &states[8], sizeof(uint8_t));
memcpy(&temp[6], &states[9], sizeof(uint8_t));
memcpy(&temp[10], &states[10], sizeof(uint8_t));
memcpy(&temp[14], &states[11], sizeof(uint8_t));
memcpy(&temp[3], &states[12], sizeof(uint8_t));
memcpy(&temp[7], &states[13], sizeof(uint8_t));
memcpy(&temp[11], &states[14], sizeof(uint8_t));
memcpy(&temp[15], &states[15], sizeof(uint8_t));
for (int c = 0; c < 16; c++) { memcpy(&states[c], &temp[c], sizeof(uint8_t)); }
cudaDevAssist(cudaMemcpy(devState, states, 16*sizeof(uint8_t), cudaMemcpyHostToDevice), 426, true);
cudaDevAssist(cudaDeviceSynchronize(), 268, true);
cudaRunner<<<1,1>>>(devState);
cudaDevAssist(cudaDeviceSynchronize(), 270, true);
cudaDevAssist(cudaMemcpy(states, devState, 16*sizeof(uint8_t), cudaMemcpyDeviceToHost), 431, true);
memcpy(&cypher[0], &states[0], sizeof(uint8_t));
memcpy(&cypher[4], &states[1], sizeof(uint8_t));
memcpy(&cypher[8], &states[2], sizeof(uint8_t));
memcpy(&cypher[12], &states[3], sizeof(uint8_t));
memcpy(&cypher[1], &states[4], sizeof(uint8_t));
memcpy(&cypher[5], &states[5], sizeof(uint8_t));
memcpy(&cypher[9], &states[6], sizeof(uint8_t));
memcpy(&cypher[13], &states[7], sizeof(uint8_t));
memcpy(&cypher[2], &states[8], sizeof(uint8_t));
memcpy(&cypher[6], &states[9], sizeof(uint8_t));
memcpy(&cypher[10], &states[10], sizeof(uint8_t));
memcpy(&cypher[14], &states[11], sizeof(uint8_t));
memcpy(&cypher[3], &states[12], sizeof(uint8_t));
memcpy(&cypher[7], &states[13], sizeof(uint8_t));
memcpy(&cypher[11], &states[14], sizeof(uint8_t));
memcpy(&cypher[15], &states[15], sizeof(uint8_t));
c_stop = clock();
float diff = (((float)c_stop - (float)c_start) / CLOCKS_PER_SEC ) * 1000;
cudaFree(devState);
cudaDeviceReset();
return diff;
} | //
// CasAES128_CUDA.c
// CasAES128_CUDA
// Created by Carter McCardwell on 11/11/14.
//
#include <stdint.h>
#include <stdio.h>
#include <time.h>
#include <string.h>
#include <hip/hip_runtime.h>
struct timing_pair{
long time;
long times[4];
char cipher[16];
char hits[10][4][4];
//long memory_usage;
//int ctx_delta;
//unsigned long tp_delta;
//unsigned short cp_delta;
};
const int Nb_h = 4;
const int Nr_h = 10;
const int Nk_h = 4;
const uint8_t s_h[256]=
{
0x63, 0x7C, 0x77, 0x7B, 0xF2, 0x6B, 0x6F, 0xC5, 0x30, 0x01, 0x67, 0x2B, 0xFE, 0xD7, 0xAB, 0x76,
0xCA, 0x82, 0xC9, 0x7D, 0xFA, 0x59, 0x47, 0xF0, 0xAD, 0xD4, 0xA2, 0xAF, 0x9C, 0xA4, 0x72, 0xC0,
0xB7, 0xFD, 0x93, 0x26, 0x36, 0x3F, 0xF7, 0xCC, 0x34, 0xA5, 0xE5, 0xF1, 0x71, 0xD8, 0x31, 0x15,
0x04, 0xC7, 0x23, 0xC3, 0x18, 0x96, 0x05, 0x9A, 0x07, 0x12, 0x80, 0xE2, 0xEB, 0x27, 0xB2, 0x75,
0x09, 0x83, 0x2C, 0x1A, 0x1B, 0x6E, 0x5A, 0xA0, 0x52, 0x3B, 0xD6, 0xB3, 0x29, 0xE3, 0x2F, 0x84,
0x53, 0xD1, 0x00, 0xED, 0x20, 0xFC, 0xB1, 0x5B, 0x6A, 0xCB, 0xBE, 0x39, 0x4A, 0x4C, 0x58, 0xCF,
0xD0, 0xEF, 0xAA, 0xFB, 0x43, 0x4D, 0x33, 0x85, 0x45, 0xF9, 0x02, 0x7F, 0x50, 0x3C, 0x9F, 0xA8,
0x51, 0xA3, 0x40, 0x8F, 0x92, 0x9D, 0x38, 0xF5, 0xBC, 0xB6, 0xDA, 0x21, 0x10, 0xFF, 0xF3, 0xD2,
0xCD, 0x0C, 0x13, 0xEC, 0x5F, 0x97, 0x44, 0x17, 0xC4, 0xA7, 0x7E, 0x3D, 0x64, 0x5D, 0x19, 0x73,
0x60, 0x81, 0x4F, 0xDC, 0x22, 0x2A, 0x90, 0x88, 0x46, 0xEE, 0xB8, 0x14, 0xDE, 0x5E, 0x0B, 0xDB,
0xE0, 0x32, 0x3A, 0x0A, 0x49, 0x06, 0x24, 0x5C, 0xC2, 0xD3, 0xAC, 0x62, 0x91, 0x95, 0xE4, 0x79,
0xE7, 0xC8, 0x37, 0x6D, 0x8D, 0xD5, 0x4E, 0xA9, 0x6C, 0x56, 0xF4, 0xEA, 0x65, 0x7A, 0xAE, 0x08,
0xBA, 0x78, 0x25, 0x2E, 0x1C, 0xA6, 0xB4, 0xC6, 0xE8, 0xDD, 0x74, 0x1F, 0x4B, 0xBD, 0x8B, 0x8A,
0x70, 0x3E, 0xB5, 0x66, 0x48, 0x03, 0xF6, 0x0E, 0x61, 0x35, 0x57, 0xB9, 0x86, 0xC1, 0x1D, 0x9E,
0xE1, 0xF8, 0x98, 0x11, 0x69, 0xD9, 0x8E, 0x94, 0x9B, 0x1E, 0x87, 0xE9, 0xCE, 0x55, 0x28, 0xDF,
0x8C, 0xA1, 0x89, 0x0D, 0xBF, 0xE6, 0x42, 0x68, 0x41, 0x99, 0x2D, 0x0F, 0xB0, 0x54, 0xBB, 0x16
};
uint8_t Rcon_h[256] = {
0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a,
0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef, 0xc5, 0x91, 0x39,
0x72, 0xe4, 0xd3, 0xbd, 0x61, 0xc2, 0x9f, 0x25, 0x4a, 0x94, 0x33, 0x66, 0xcc, 0x83, 0x1d, 0x3a,
0x74, 0xe8, 0xcb, 0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8,
0xab, 0x4d, 0x9a, 0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef,
0xc5, 0x91, 0x39, 0x72, 0xe4, 0xd3, 0xbd, 0x61, 0xc2, 0x9f, 0x25, 0x4a, 0x94, 0x33, 0x66, 0xcc,
0x83, 0x1d, 0x3a, 0x74, 0xe8, 0xcb, 0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b,
0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a, 0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3,
0x7d, 0xfa, 0xef, 0xc5, 0x91, 0x39, 0x72, 0xe4, 0xd3, 0xbd, 0x61, 0xc2, 0x9f, 0x25, 0x4a, 0x94,
0x33, 0x66, 0xcc, 0x83, 0x1d, 0x3a, 0x74, 0xe8, 0xcb, 0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20,
0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a, 0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35,
0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef, 0xc5, 0x91, 0x39, 0x72, 0xe4, 0xd3, 0xbd, 0x61, 0xc2, 0x9f,
0x25, 0x4a, 0x94, 0x33, 0x66, 0xcc, 0x83, 0x1d, 0x3a, 0x74, 0xe8, 0xcb, 0x8d, 0x01, 0x02, 0x04,
0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a, 0x2f, 0x5e, 0xbc, 0x63,
0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef, 0xc5, 0x91, 0x39, 0x72, 0xe4, 0xd3, 0xbd,
0x61, 0xc2, 0x9f, 0x25, 0x4a, 0x94, 0x33, 0x66, 0xcc, 0x83, 0x1d, 0x3a, 0x74, 0xe8, 0xcb, 0x8d
};
__constant__ uint8_t s[256];
__constant__ int Nb;
__constant__ int Nr;
__constant__ int Nk;
__constant__ uint32_t ek[44];
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void cudaDevAssist(hipError_t code, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"cudaDevAssistant: %s %d\n", hipGetErrorString(code), line);
if (abort) exit(code);
}
}
uint32_t sw(uint32_t word)
{
union {
uint32_t word;
uint8_t bytes[4];
} subWord __attribute__ ((aligned));
subWord.word = word;
subWord.bytes[3] = s_h[subWord.bytes[3]];
subWord.bytes[2] = s_h[subWord.bytes[2]];
subWord.bytes[1] = s_h[subWord.bytes[1]];
subWord.bytes[0] = s_h[subWord.bytes[0]];
return subWord.word;
}
__device__ void sb(uint8_t* in)
{
for (int i = 0; i < 16; i++) { in[i] = s[in[i]]; }
}
__device__ void mc(uint8_t* arr)
{
for (int i = 0; i < 4; i++)
{
uint8_t a[4];
uint8_t b[4];
uint8_t c;
uint8_t h;
for(c=0;c<4;c++) {
a[c] = arr[(4*c+i)];
h = (uint8_t)((signed char)arr[(4*c+i)] >> 7);
b[c] = arr[(4*c+i)] << 1;
b[c] ^= 0x1B & h;
}
arr[(i)] = b[0] ^ a[3] ^ a[2] ^ b[1] ^ a[1];
arr[(4+i)] = b[1] ^ a[0] ^ a[3] ^ b[2] ^ a[2];
arr[(8+i)] = b[2] ^ a[1] ^ a[0] ^ b[3] ^ a[3];
arr[(12+i)] = b[3] ^ a[2] ^ a[1] ^ b[0] ^ a[0];
}
}
__device__ void sr(uint8_t* arr)
{
uint8_t out[16];
//On per-row basis (+1 shift ea row)
//Row 1
out[0] = arr[0];
out[1] = arr[1];
out[2] = arr[2];
out[3] = arr[3];
//Row 2
out[4] = arr[5];
out[5] = arr[6];
out[6] = arr[7];
out[7] = arr[4];
//Row 3
out[8] = arr[10];
out[9] = arr[11];
out[10] = arr[8];
out[11] = arr[9];
//Row 4
out[12] = arr[15];
out[13] = arr[12];
out[14] = arr[13];
out[15] = arr[14];
for (int i = 0; i < 16; i++)
{
arr[i] = out[i];
}
}
uint32_t rw(uint32_t word)
{
union {
uint8_t bytes[4];
uint32_t word;
} subWord __attribute__ ((aligned));
subWord.word = word;
uint8_t B0 = subWord.bytes[3], B1 = subWord.bytes[2], B2 = subWord.bytes[1], B3 = subWord.bytes[0];
subWord.bytes[3] = B1; //0
subWord.bytes[2] = B2; //1
subWord.bytes[1] = B3; //2
subWord.bytes[0] = B0; //3
return subWord.word;
}
void K_Exp(uint8_t* pk, uint32_t* out)
{
int i = 0;
union {
uint8_t bytes[4];
uint32_t word;
} temp __attribute__ ((aligned));
union {
uint8_t bytes[4];
uint32_t word;
} univar[44] __attribute__ ((aligned));
for (i = 0; i < Nk_h; i++)
{
univar[i].bytes[3] = pk[i*4];
univar[i].bytes[2] = pk[i*4+1];
univar[i].bytes[1] = pk[i*4+2];
univar[i].bytes[0] = pk[i*4+3];
}
for (i = Nk_h; i < Nb_h*(Nr_h+1); i++)
{
temp.word = univar[i-1].word;
if (i % Nk_h == 0)
{
temp.word = (sw(rw(temp.word)));
temp.bytes[3] = temp.bytes[3] ^ (Rcon_h[i/Nk_h]);
}
else if (Nk_h > 6 && i % Nk_h == 4)
{
temp.word = sw(temp.word);
}
if (i-4 % Nk_h == 0)
{
temp.word = sw(temp.word);
}
univar[i].word = univar[i-Nk_h].word ^ temp.word;
}
for (i = 0; i < 44; i++)
{
out[i] = univar[i].word;
}
}
__device__ void ark(uint8_t* state, int strD)
{
union {
uint32_t word;
uint8_t bytes[4];
} zero __attribute__ ((aligned));
union {
uint32_t word;
uint8_t bytes[4];
} one __attribute__ ((aligned));
union {
uint32_t word;
uint8_t bytes[4];
} two __attribute__ ((aligned));
union {
uint32_t word;
uint8_t bytes[4];
} three __attribute__ ((aligned));
zero.word = ek[strD];
one.word = ek[strD+1];
two.word = ek[strD+2];
three.word = ek[strD+3];
state[0] = state[0] ^ zero.bytes[3];
state[4] = state[4] ^ zero.bytes[2];
state[8] = state[8] ^ zero.bytes[1];
state[12] = state[12] ^ zero.bytes[0];
state[1] = state[1] ^ one.bytes[3];
state[5] = state[5] ^ one.bytes[2];
state[9] = state[9] ^ one.bytes[1];
state[13] = state[13] ^ one.bytes[0];
state[2] = state[2] ^ two.bytes[3];
state[6] = state[6] ^ two.bytes[2];
state[10] = state[10] ^ two.bytes[1];
state[14] = state[14] ^ two.bytes[0];
state[3] = state[3] ^ three.bytes[3];
state[7] = state[7] ^ three.bytes[2];
state[11] = state[11] ^ three.bytes[1];
state[15] = state[15] ^ three.bytes[0];
}
__global__ void cudaRunner(uint8_t *in)
{
uint8_t state[16];
int localid = blockDim.x * blockIdx.x + threadIdx.x; //Data is shifted by 16 * ID of worker
for (int i = 0; i < 16; i++) { state[i] = in[(localid*16)+i]; }
ark(state, 0);
for (int i = 1; i < Nr; i++)
{
sb(state);
sr(state);
mc(state);
ark(state, i*Nb);
}
sb(state);
sr(state);
ark(state, Nr*Nb);
for (int i = 0; i < 16; i++) { in[(localid*16)+i] = state[i]; }
}
long AES_CUDA(char* in_cypher, char* cypher, char* in_key)
{
clock_t c_start, c_stop;
c_start = clock();
uint8_t key[16];
uint32_t ek_h[44];
uint8_t states[16] = { 0x00 };
for (int i = 0; i < 16; i++)
{
states[i] = in_cypher[i];
key[i] = in_key[i];
}
K_Exp(key, ek_h);
//send constants to GPU
hipSetDevice(0);
cudaDevAssist(hipMemcpyToSymbol(HIP_SYMBOL(Nk), &Nk_h, sizeof(int), 0, hipMemcpyHostToDevice), 535, true);
cudaDevAssist(hipMemcpyToSymbol(HIP_SYMBOL(Nr), &Nr_h, sizeof(int), 0, hipMemcpyHostToDevice), 543, true);
cudaDevAssist(hipMemcpyToSymbol(HIP_SYMBOL(Nb), &Nb_h, sizeof(int), 0, hipMemcpyHostToDevice), 903, true);
cudaDevAssist(hipMemcpyToSymbol(HIP_SYMBOL(s), &s_h, 256*sizeof(uint8_t), 0, hipMemcpyHostToDevice), 920, true);
cudaDevAssist(hipMemcpyToSymbol(HIP_SYMBOL(ek), &ek_h, 44*sizeof(uint32_t), 0, hipMemcpyHostToDevice), 823, true);
hipDeviceSynchronize();
uint8_t *devState = NULL;
cudaDevAssist(hipMalloc((void**)&devState, 16*sizeof(uint8_t)), 425, true);
//arrange data correctly
uint8_t temp[16];
memcpy(&temp[0], &states[0], sizeof(uint8_t));
memcpy(&temp[4], &states[1], sizeof(uint8_t));
memcpy(&temp[8], &states[2], sizeof(uint8_t));
memcpy(&temp[12], &states[3], sizeof(uint8_t));
memcpy(&temp[1], &states[4], sizeof(uint8_t));
memcpy(&temp[5], &states[5], sizeof(uint8_t));
memcpy(&temp[9], &states[6], sizeof(uint8_t));
memcpy(&temp[13], &states[7], sizeof(uint8_t));
memcpy(&temp[2], &states[8], sizeof(uint8_t));
memcpy(&temp[6], &states[9], sizeof(uint8_t));
memcpy(&temp[10], &states[10], sizeof(uint8_t));
memcpy(&temp[14], &states[11], sizeof(uint8_t));
memcpy(&temp[3], &states[12], sizeof(uint8_t));
memcpy(&temp[7], &states[13], sizeof(uint8_t));
memcpy(&temp[11], &states[14], sizeof(uint8_t));
memcpy(&temp[15], &states[15], sizeof(uint8_t));
for (int c = 0; c < 16; c++) { memcpy(&states[c], &temp[c], sizeof(uint8_t)); }
cudaDevAssist(hipMemcpy(devState, states, 16*sizeof(uint8_t), hipMemcpyHostToDevice), 426, true);
cudaDevAssist(hipDeviceSynchronize(), 268, true);
cudaRunner<<<1,1>>>(devState);
cudaDevAssist(hipDeviceSynchronize(), 270, true);
cudaDevAssist(hipMemcpy(states, devState, 16*sizeof(uint8_t), hipMemcpyDeviceToHost), 431, true);
memcpy(&cypher[0], &states[0], sizeof(uint8_t));
memcpy(&cypher[4], &states[1], sizeof(uint8_t));
memcpy(&cypher[8], &states[2], sizeof(uint8_t));
memcpy(&cypher[12], &states[3], sizeof(uint8_t));
memcpy(&cypher[1], &states[4], sizeof(uint8_t));
memcpy(&cypher[5], &states[5], sizeof(uint8_t));
memcpy(&cypher[9], &states[6], sizeof(uint8_t));
memcpy(&cypher[13], &states[7], sizeof(uint8_t));
memcpy(&cypher[2], &states[8], sizeof(uint8_t));
memcpy(&cypher[6], &states[9], sizeof(uint8_t));
memcpy(&cypher[10], &states[10], sizeof(uint8_t));
memcpy(&cypher[14], &states[11], sizeof(uint8_t));
memcpy(&cypher[3], &states[12], sizeof(uint8_t));
memcpy(&cypher[7], &states[13], sizeof(uint8_t));
memcpy(&cypher[11], &states[14], sizeof(uint8_t));
memcpy(&cypher[15], &states[15], sizeof(uint8_t));
c_stop = clock();
float diff = (((float)c_stop - (float)c_start) / CLOCKS_PER_SEC ) * 1000;
hipFree(devState);
hipDeviceReset();
return diff;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //
// CasAES128_CUDA.c
// CasAES128_CUDA
// Created by Carter McCardwell on 11/11/14.
//
#include <stdint.h>
#include <stdio.h>
#include <time.h>
#include <string.h>
#include <hip/hip_runtime.h>
struct timing_pair{
long time;
long times[4];
char cipher[16];
char hits[10][4][4];
//long memory_usage;
//int ctx_delta;
//unsigned long tp_delta;
//unsigned short cp_delta;
};
const int Nb_h = 4;
const int Nr_h = 10;
const int Nk_h = 4;
const uint8_t s_h[256]=
{
0x63, 0x7C, 0x77, 0x7B, 0xF2, 0x6B, 0x6F, 0xC5, 0x30, 0x01, 0x67, 0x2B, 0xFE, 0xD7, 0xAB, 0x76,
0xCA, 0x82, 0xC9, 0x7D, 0xFA, 0x59, 0x47, 0xF0, 0xAD, 0xD4, 0xA2, 0xAF, 0x9C, 0xA4, 0x72, 0xC0,
0xB7, 0xFD, 0x93, 0x26, 0x36, 0x3F, 0xF7, 0xCC, 0x34, 0xA5, 0xE5, 0xF1, 0x71, 0xD8, 0x31, 0x15,
0x04, 0xC7, 0x23, 0xC3, 0x18, 0x96, 0x05, 0x9A, 0x07, 0x12, 0x80, 0xE2, 0xEB, 0x27, 0xB2, 0x75,
0x09, 0x83, 0x2C, 0x1A, 0x1B, 0x6E, 0x5A, 0xA0, 0x52, 0x3B, 0xD6, 0xB3, 0x29, 0xE3, 0x2F, 0x84,
0x53, 0xD1, 0x00, 0xED, 0x20, 0xFC, 0xB1, 0x5B, 0x6A, 0xCB, 0xBE, 0x39, 0x4A, 0x4C, 0x58, 0xCF,
0xD0, 0xEF, 0xAA, 0xFB, 0x43, 0x4D, 0x33, 0x85, 0x45, 0xF9, 0x02, 0x7F, 0x50, 0x3C, 0x9F, 0xA8,
0x51, 0xA3, 0x40, 0x8F, 0x92, 0x9D, 0x38, 0xF5, 0xBC, 0xB6, 0xDA, 0x21, 0x10, 0xFF, 0xF3, 0xD2,
0xCD, 0x0C, 0x13, 0xEC, 0x5F, 0x97, 0x44, 0x17, 0xC4, 0xA7, 0x7E, 0x3D, 0x64, 0x5D, 0x19, 0x73,
0x60, 0x81, 0x4F, 0xDC, 0x22, 0x2A, 0x90, 0x88, 0x46, 0xEE, 0xB8, 0x14, 0xDE, 0x5E, 0x0B, 0xDB,
0xE0, 0x32, 0x3A, 0x0A, 0x49, 0x06, 0x24, 0x5C, 0xC2, 0xD3, 0xAC, 0x62, 0x91, 0x95, 0xE4, 0x79,
0xE7, 0xC8, 0x37, 0x6D, 0x8D, 0xD5, 0x4E, 0xA9, 0x6C, 0x56, 0xF4, 0xEA, 0x65, 0x7A, 0xAE, 0x08,
0xBA, 0x78, 0x25, 0x2E, 0x1C, 0xA6, 0xB4, 0xC6, 0xE8, 0xDD, 0x74, 0x1F, 0x4B, 0xBD, 0x8B, 0x8A,
0x70, 0x3E, 0xB5, 0x66, 0x48, 0x03, 0xF6, 0x0E, 0x61, 0x35, 0x57, 0xB9, 0x86, 0xC1, 0x1D, 0x9E,
0xE1, 0xF8, 0x98, 0x11, 0x69, 0xD9, 0x8E, 0x94, 0x9B, 0x1E, 0x87, 0xE9, 0xCE, 0x55, 0x28, 0xDF,
0x8C, 0xA1, 0x89, 0x0D, 0xBF, 0xE6, 0x42, 0x68, 0x41, 0x99, 0x2D, 0x0F, 0xB0, 0x54, 0xBB, 0x16
};
uint8_t Rcon_h[256] = {
0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a,
0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef, 0xc5, 0x91, 0x39,
0x72, 0xe4, 0xd3, 0xbd, 0x61, 0xc2, 0x9f, 0x25, 0x4a, 0x94, 0x33, 0x66, 0xcc, 0x83, 0x1d, 0x3a,
0x74, 0xe8, 0xcb, 0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8,
0xab, 0x4d, 0x9a, 0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef,
0xc5, 0x91, 0x39, 0x72, 0xe4, 0xd3, 0xbd, 0x61, 0xc2, 0x9f, 0x25, 0x4a, 0x94, 0x33, 0x66, 0xcc,
0x83, 0x1d, 0x3a, 0x74, 0xe8, 0xcb, 0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b,
0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a, 0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3,
0x7d, 0xfa, 0xef, 0xc5, 0x91, 0x39, 0x72, 0xe4, 0xd3, 0xbd, 0x61, 0xc2, 0x9f, 0x25, 0x4a, 0x94,
0x33, 0x66, 0xcc, 0x83, 0x1d, 0x3a, 0x74, 0xe8, 0xcb, 0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20,
0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a, 0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35,
0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef, 0xc5, 0x91, 0x39, 0x72, 0xe4, 0xd3, 0xbd, 0x61, 0xc2, 0x9f,
0x25, 0x4a, 0x94, 0x33, 0x66, 0xcc, 0x83, 0x1d, 0x3a, 0x74, 0xe8, 0xcb, 0x8d, 0x01, 0x02, 0x04,
0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a, 0x2f, 0x5e, 0xbc, 0x63,
0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef, 0xc5, 0x91, 0x39, 0x72, 0xe4, 0xd3, 0xbd,
0x61, 0xc2, 0x9f, 0x25, 0x4a, 0x94, 0x33, 0x66, 0xcc, 0x83, 0x1d, 0x3a, 0x74, 0xe8, 0xcb, 0x8d
};
__constant__ uint8_t s[256];
__constant__ int Nb;
__constant__ int Nr;
__constant__ int Nk;
__constant__ uint32_t ek[44];
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void cudaDevAssist(hipError_t code, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"cudaDevAssistant: %s %d\n", hipGetErrorString(code), line);
if (abort) exit(code);
}
}
uint32_t sw(uint32_t word)
{
union {
uint32_t word;
uint8_t bytes[4];
} subWord __attribute__ ((aligned));
subWord.word = word;
subWord.bytes[3] = s_h[subWord.bytes[3]];
subWord.bytes[2] = s_h[subWord.bytes[2]];
subWord.bytes[1] = s_h[subWord.bytes[1]];
subWord.bytes[0] = s_h[subWord.bytes[0]];
return subWord.word;
}
__device__ void sb(uint8_t* in)
{
for (int i = 0; i < 16; i++) { in[i] = s[in[i]]; }
}
__device__ void mc(uint8_t* arr)
{
for (int i = 0; i < 4; i++)
{
uint8_t a[4];
uint8_t b[4];
uint8_t c;
uint8_t h;
for(c=0;c<4;c++) {
a[c] = arr[(4*c+i)];
h = (uint8_t)((signed char)arr[(4*c+i)] >> 7);
b[c] = arr[(4*c+i)] << 1;
b[c] ^= 0x1B & h;
}
arr[(i)] = b[0] ^ a[3] ^ a[2] ^ b[1] ^ a[1];
arr[(4+i)] = b[1] ^ a[0] ^ a[3] ^ b[2] ^ a[2];
arr[(8+i)] = b[2] ^ a[1] ^ a[0] ^ b[3] ^ a[3];
arr[(12+i)] = b[3] ^ a[2] ^ a[1] ^ b[0] ^ a[0];
}
}
__device__ void sr(uint8_t* arr)
{
uint8_t out[16];
//On per-row basis (+1 shift ea row)
//Row 1
out[0] = arr[0];
out[1] = arr[1];
out[2] = arr[2];
out[3] = arr[3];
//Row 2
out[4] = arr[5];
out[5] = arr[6];
out[6] = arr[7];
out[7] = arr[4];
//Row 3
out[8] = arr[10];
out[9] = arr[11];
out[10] = arr[8];
out[11] = arr[9];
//Row 4
out[12] = arr[15];
out[13] = arr[12];
out[14] = arr[13];
out[15] = arr[14];
for (int i = 0; i < 16; i++)
{
arr[i] = out[i];
}
}
uint32_t rw(uint32_t word)
{
union {
uint8_t bytes[4];
uint32_t word;
} subWord __attribute__ ((aligned));
subWord.word = word;
uint8_t B0 = subWord.bytes[3], B1 = subWord.bytes[2], B2 = subWord.bytes[1], B3 = subWord.bytes[0];
subWord.bytes[3] = B1; //0
subWord.bytes[2] = B2; //1
subWord.bytes[1] = B3; //2
subWord.bytes[0] = B0; //3
return subWord.word;
}
void K_Exp(uint8_t* pk, uint32_t* out)
{
int i = 0;
union {
uint8_t bytes[4];
uint32_t word;
} temp __attribute__ ((aligned));
union {
uint8_t bytes[4];
uint32_t word;
} univar[44] __attribute__ ((aligned));
for (i = 0; i < Nk_h; i++)
{
univar[i].bytes[3] = pk[i*4];
univar[i].bytes[2] = pk[i*4+1];
univar[i].bytes[1] = pk[i*4+2];
univar[i].bytes[0] = pk[i*4+3];
}
for (i = Nk_h; i < Nb_h*(Nr_h+1); i++)
{
temp.word = univar[i-1].word;
if (i % Nk_h == 0)
{
temp.word = (sw(rw(temp.word)));
temp.bytes[3] = temp.bytes[3] ^ (Rcon_h[i/Nk_h]);
}
else if (Nk_h > 6 && i % Nk_h == 4)
{
temp.word = sw(temp.word);
}
if (i-4 % Nk_h == 0)
{
temp.word = sw(temp.word);
}
univar[i].word = univar[i-Nk_h].word ^ temp.word;
}
for (i = 0; i < 44; i++)
{
out[i] = univar[i].word;
}
}
__device__ void ark(uint8_t* state, int strD)
{
union {
uint32_t word;
uint8_t bytes[4];
} zero __attribute__ ((aligned));
union {
uint32_t word;
uint8_t bytes[4];
} one __attribute__ ((aligned));
union {
uint32_t word;
uint8_t bytes[4];
} two __attribute__ ((aligned));
union {
uint32_t word;
uint8_t bytes[4];
} three __attribute__ ((aligned));
zero.word = ek[strD];
one.word = ek[strD+1];
two.word = ek[strD+2];
three.word = ek[strD+3];
state[0] = state[0] ^ zero.bytes[3];
state[4] = state[4] ^ zero.bytes[2];
state[8] = state[8] ^ zero.bytes[1];
state[12] = state[12] ^ zero.bytes[0];
state[1] = state[1] ^ one.bytes[3];
state[5] = state[5] ^ one.bytes[2];
state[9] = state[9] ^ one.bytes[1];
state[13] = state[13] ^ one.bytes[0];
state[2] = state[2] ^ two.bytes[3];
state[6] = state[6] ^ two.bytes[2];
state[10] = state[10] ^ two.bytes[1];
state[14] = state[14] ^ two.bytes[0];
state[3] = state[3] ^ three.bytes[3];
state[7] = state[7] ^ three.bytes[2];
state[11] = state[11] ^ three.bytes[1];
state[15] = state[15] ^ three.bytes[0];
}
__global__ void cudaRunner(uint8_t *in)
{
uint8_t state[16];
int localid = blockDim.x * blockIdx.x + threadIdx.x; //Data is shifted by 16 * ID of worker
for (int i = 0; i < 16; i++) { state[i] = in[(localid*16)+i]; }
ark(state, 0);
for (int i = 1; i < Nr; i++)
{
sb(state);
sr(state);
mc(state);
ark(state, i*Nb);
}
sb(state);
sr(state);
ark(state, Nr*Nb);
for (int i = 0; i < 16; i++) { in[(localid*16)+i] = state[i]; }
}
long AES_CUDA(char* in_cypher, char* cypher, char* in_key)
{
clock_t c_start, c_stop;
c_start = clock();
uint8_t key[16];
uint32_t ek_h[44];
uint8_t states[16] = { 0x00 };
for (int i = 0; i < 16; i++)
{
states[i] = in_cypher[i];
key[i] = in_key[i];
}
K_Exp(key, ek_h);
//send constants to GPU
hipSetDevice(0);
cudaDevAssist(hipMemcpyToSymbol(HIP_SYMBOL(Nk), &Nk_h, sizeof(int), 0, hipMemcpyHostToDevice), 535, true);
cudaDevAssist(hipMemcpyToSymbol(HIP_SYMBOL(Nr), &Nr_h, sizeof(int), 0, hipMemcpyHostToDevice), 543, true);
cudaDevAssist(hipMemcpyToSymbol(HIP_SYMBOL(Nb), &Nb_h, sizeof(int), 0, hipMemcpyHostToDevice), 903, true);
cudaDevAssist(hipMemcpyToSymbol(HIP_SYMBOL(s), &s_h, 256*sizeof(uint8_t), 0, hipMemcpyHostToDevice), 920, true);
cudaDevAssist(hipMemcpyToSymbol(HIP_SYMBOL(ek), &ek_h, 44*sizeof(uint32_t), 0, hipMemcpyHostToDevice), 823, true);
hipDeviceSynchronize();
uint8_t *devState = NULL;
cudaDevAssist(hipMalloc((void**)&devState, 16*sizeof(uint8_t)), 425, true);
//arrange data correctly
uint8_t temp[16];
memcpy(&temp[0], &states[0], sizeof(uint8_t));
memcpy(&temp[4], &states[1], sizeof(uint8_t));
memcpy(&temp[8], &states[2], sizeof(uint8_t));
memcpy(&temp[12], &states[3], sizeof(uint8_t));
memcpy(&temp[1], &states[4], sizeof(uint8_t));
memcpy(&temp[5], &states[5], sizeof(uint8_t));
memcpy(&temp[9], &states[6], sizeof(uint8_t));
memcpy(&temp[13], &states[7], sizeof(uint8_t));
memcpy(&temp[2], &states[8], sizeof(uint8_t));
memcpy(&temp[6], &states[9], sizeof(uint8_t));
memcpy(&temp[10], &states[10], sizeof(uint8_t));
memcpy(&temp[14], &states[11], sizeof(uint8_t));
memcpy(&temp[3], &states[12], sizeof(uint8_t));
memcpy(&temp[7], &states[13], sizeof(uint8_t));
memcpy(&temp[11], &states[14], sizeof(uint8_t));
memcpy(&temp[15], &states[15], sizeof(uint8_t));
for (int c = 0; c < 16; c++) { memcpy(&states[c], &temp[c], sizeof(uint8_t)); }
cudaDevAssist(hipMemcpy(devState, states, 16*sizeof(uint8_t), hipMemcpyHostToDevice), 426, true);
cudaDevAssist(hipDeviceSynchronize(), 268, true);
cudaRunner<<<1,1>>>(devState);
cudaDevAssist(hipDeviceSynchronize(), 270, true);
cudaDevAssist(hipMemcpy(states, devState, 16*sizeof(uint8_t), hipMemcpyDeviceToHost), 431, true);
memcpy(&cypher[0], &states[0], sizeof(uint8_t));
memcpy(&cypher[4], &states[1], sizeof(uint8_t));
memcpy(&cypher[8], &states[2], sizeof(uint8_t));
memcpy(&cypher[12], &states[3], sizeof(uint8_t));
memcpy(&cypher[1], &states[4], sizeof(uint8_t));
memcpy(&cypher[5], &states[5], sizeof(uint8_t));
memcpy(&cypher[9], &states[6], sizeof(uint8_t));
memcpy(&cypher[13], &states[7], sizeof(uint8_t));
memcpy(&cypher[2], &states[8], sizeof(uint8_t));
memcpy(&cypher[6], &states[9], sizeof(uint8_t));
memcpy(&cypher[10], &states[10], sizeof(uint8_t));
memcpy(&cypher[14], &states[11], sizeof(uint8_t));
memcpy(&cypher[3], &states[12], sizeof(uint8_t));
memcpy(&cypher[7], &states[13], sizeof(uint8_t));
memcpy(&cypher[11], &states[14], sizeof(uint8_t));
memcpy(&cypher[15], &states[15], sizeof(uint8_t));
c_stop = clock();
float diff = (((float)c_stop - (float)c_start) / CLOCKS_PER_SEC ) * 1000;
hipFree(devState);
hipDeviceReset();
return diff;
} | .text
.file "CasAES128_CUDA_NOUNAR_asFUNCT.hip"
.globl _Z2swj # -- Begin function _Z2swj
.p2align 4, 0x90
.type _Z2swj,@function
_Z2swj: # @_Z2swj
.cfi_startproc
# %bb.0:
movl %edi, %eax
movl %edi, %ecx
movzbl %ah, %edx
movzbl %al, %esi
shrl $16, %eax
shrl $24, %ecx
movzbl %al, %eax
movzbl _ZL3s_h(%rax), %edi
movzbl _ZL3s_h(%rdx), %eax
movzbl _ZL3s_h(%rsi), %edx
movzbl _ZL3s_h(%rcx), %ecx
shll $24, %ecx
shll $16, %edi
orl %ecx, %edi
shll $8, %eax
orl %edi, %eax
orl %edx, %eax
retq
.Lfunc_end0:
.size _Z2swj, .Lfunc_end0-_Z2swj
.cfi_endproc
# -- End function
.globl _Z2rwj # -- Begin function _Z2rwj
.p2align 4, 0x90
.type _Z2rwj,@function
_Z2rwj: # @_Z2rwj
.cfi_startproc
# %bb.0:
movl %edi, %eax
roll $8, %eax
retq
.Lfunc_end1:
.size _Z2rwj, .Lfunc_end1-_Z2rwj
.cfi_endproc
# -- End function
.globl _Z5K_ExpPhPj # -- Begin function _Z5K_ExpPhPj
.p2align 4, 0x90
.type _Z5K_ExpPhPj,@function
_Z5K_ExpPhPj: # @_Z5K_ExpPhPj
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rsi, %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movzbl (%rdi,%rcx,4), %edx
movb %dl, 3(%rsp,%rcx,4)
movzbl 1(%rdi,%rcx,4), %edx
movb %dl, 2(%rsp,%rcx,4)
movzbl 2(%rdi,%rcx,4), %edx
movb %dl, 1(%rsp,%rcx,4)
movzbl 3(%rdi,%rcx,4), %edx
movb %dl, (%rsp,%rcx,4)
incq %rcx
cmpq $4, %rcx
jne .LBB2_1
# %bb.2: # %.preheader53.preheader
movl $4, %ecx
movl 12(%rsp), %edx
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_5: # in Loop: Header=BB2_3 Depth=1
roll $8, %edx
movl %edx, %esi
movzbl %dh, %edi
movzbl %dl, %r8d
shrl $16, %edx
shrl $24, %esi
movzbl %dl, %edx
movzbl _ZL3s_h(%rdx), %edx
movzbl _ZL3s_h(%rdi), %r9d
movzbl _ZL3s_h(%r8), %edi
shll $16, %edx
orl %edi, %edx
shll $8, %r9d
orl %edx, %r9d
movl %ecx, %edx
shrl $2, %edx
movzbl Rcon_h(%rdx), %edi
xorb _ZL3s_h(%rsi), %dil
movl %r9d, %edx
.LBB2_6: # in Loop: Header=BB2_3 Depth=1
movzbl %dil, %esi
shll $24, %esi
andl $16777215, %edx # imm = 0xFFFFFF
orl %esi, %edx
xorl -16(%rsp,%rcx,4), %edx
movl %edx, (%rsp,%rcx,4)
incq %rcx
cmpq $44, %rcx
je .LBB2_7
.LBB2_3: # %.preheader53
# =>This Inner Loop Header: Depth=1
testb $3, %cl
je .LBB2_5
# %bb.4: # in Loop: Header=BB2_3 Depth=1
movl %edx, %edi
shrl $24, %edi
jmp .LBB2_6
.LBB2_7: # %.preheader.preheader
movq %rsp, %rsi
movl $176, %edx
movq %rax, %rdi
callq memcpy@PLT
addq $184, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z5K_ExpPhPj, .Lfunc_end2-_Z5K_ExpPhPj
.cfi_endproc
# -- End function
.globl _Z25__device_stub__cudaRunnerPh # -- Begin function _Z25__device_stub__cudaRunnerPh
.p2align 4, 0x90
.type _Z25__device_stub__cudaRunnerPh,@function
_Z25__device_stub__cudaRunnerPh: # @_Z25__device_stub__cudaRunnerPh
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10cudaRunnerPh, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end3:
.size _Z25__device_stub__cudaRunnerPh, .Lfunc_end3-_Z25__device_stub__cudaRunnerPh
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z8AES_CUDAPcS_S_
.LCPI4_0:
.long 0x49742400 # float 1.0E+6
.LCPI4_1:
.long 0x447a0000 # float 1000
.text
.globl _Z8AES_CUDAPcS_S_
.p2align 4, 0x90
.type _Z8AES_CUDAPcS_S_,@function
_Z8AES_CUDAPcS_S_: # @_Z8AES_CUDAPcS_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $288, %rsp # imm = 0x120
.cfi_def_cfa_offset 336
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %r15
movq %rsi, %r14
movq %rdi, %r12
callq clock
movq %rax, %rbx
movups (%r12), %xmm0
movaps %xmm0, (%rsp)
movups (%r15), %xmm0
movaps %xmm0, 96(%rsp)
leaq 96(%rsp), %rdi
leaq 112(%rsp), %rsi
callq _Z5K_ExpPhPj
xorl %edi, %edi
callq hipSetDevice
movl $Nk, %edi
movl $_ZL4Nk_h, %esi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
testl %eax, %eax
jne .LBB4_1
# %bb.3: # %_Z13cudaDevAssist10hipError_tib.exit
movl $Nr, %edi
movl $_ZL4Nr_h, %esi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
testl %eax, %eax
jne .LBB4_4
# %bb.5: # %_Z13cudaDevAssist10hipError_tib.exit34
movl $Nb, %edi
movl $_ZL4Nb_h, %esi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
testl %eax, %eax
jne .LBB4_6
# %bb.7: # %_Z13cudaDevAssist10hipError_tib.exit36
movl $s, %edi
movl $_ZL3s_h, %esi
movl $256, %edx # imm = 0x100
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
testl %eax, %eax
jne .LBB4_8
# %bb.9: # %_Z13cudaDevAssist10hipError_tib.exit38
leaq 112(%rsp), %rsi
movl $ek, %edi
movl $176, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
testl %eax, %eax
jne .LBB4_10
# %bb.11: # %_Z13cudaDevAssist10hipError_tib.exit40
callq hipDeviceSynchronize
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movl $16, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB4_12
# %bb.13: # %_Z13cudaDevAssist10hipError_tib.exit42
movzbl 1(%rsp), %eax
movzbl 2(%rsp), %ecx
movzbl 3(%rsp), %edx
movzbl 4(%rsp), %esi
movzbl 6(%rsp), %edi
movzbl 7(%rsp), %r8d
movzbl 8(%rsp), %r9d
movzbl 9(%rsp), %r10d
movzbl 11(%rsp), %r11d
movzbl 12(%rsp), %ebp
movzbl 13(%rsp), %r15d
movzbl 14(%rsp), %r12d
movb %sil, 1(%rsp)
movb %r9b, 2(%rsp)
movb %bpl, 3(%rsp)
movb %al, 4(%rsp)
movb %r10b, 6(%rsp)
movb %r15b, 7(%rsp)
movb %cl, 8(%rsp)
movb %dil, 9(%rsp)
movb %r12b, 11(%rsp)
movb %dl, 12(%rsp)
movb %r8b, 13(%rsp)
movb %r11b, 14(%rsp)
movq 16(%rsp), %rdi
movq %rsp, %rsi
movl $16, %edx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_14
# %bb.15: # %_Z13cudaDevAssist10hipError_tib.exit44
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB4_16
# %bb.17: # %_Z13cudaDevAssist10hipError_tib.exit46
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_19
# %bb.18:
movq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 88(%rsp), %rax
movq %rax, 32(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z10cudaRunnerPh, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_19:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB4_20
# %bb.21: # %_Z13cudaDevAssist10hipError_tib.exit48
movq 16(%rsp), %rsi
movq %rsp, %rdi
movl $16, %edx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_22
# %bb.23: # %_Z13cudaDevAssist10hipError_tib.exit50
movzbl (%rsp), %eax
movb %al, (%r14)
movzbl 1(%rsp), %eax
movb %al, 4(%r14)
movzbl 2(%rsp), %eax
movb %al, 8(%r14)
movzbl 3(%rsp), %eax
movb %al, 12(%r14)
movzbl 4(%rsp), %eax
movb %al, 1(%r14)
movzbl 5(%rsp), %eax
movb %al, 5(%r14)
movzbl 6(%rsp), %eax
movb %al, 9(%r14)
movzbl 7(%rsp), %eax
movb %al, 13(%r14)
movzbl 8(%rsp), %eax
movb %al, 2(%r14)
movzbl 9(%rsp), %eax
movb %al, 6(%r14)
movzbl 10(%rsp), %eax
movb %al, 10(%r14)
movzbl 11(%rsp), %eax
movb %al, 14(%r14)
movzbl 12(%rsp), %eax
movb %al, 3(%r14)
movzbl 13(%rsp), %eax
movb %al, 7(%r14)
movzbl 14(%rsp), %eax
movb %al, 11(%r14)
movzbl 15(%rsp), %eax
movb %al, 15(%r14)
callq clock
cvtsi2ss %rax, %xmm1
cvtsi2ss %rbx, %xmm0
subss %xmm0, %xmm1
divss .LCPI4_0(%rip), %xmm1
mulss .LCPI4_1(%rip), %xmm1
movss %xmm1, 28(%rsp) # 4-byte Spill
movq 16(%rsp), %rdi
callq hipFree
callq hipDeviceReset
cvttss2si 28(%rsp), %rax # 4-byte Folded Reload
addq $288, %rsp # imm = 0x120
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_1:
.cfi_def_cfa_offset 336
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
movl $535, %ecx # imm = 0x217
jmp .LBB4_2
.LBB4_4:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
movl $543, %ecx # imm = 0x21F
jmp .LBB4_2
.LBB4_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
movl $903, %ecx # imm = 0x387
jmp .LBB4_2
.LBB4_8:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
movl $920, %ecx # imm = 0x398
jmp .LBB4_2
.LBB4_10:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
movl $823, %ecx # imm = 0x337
jmp .LBB4_2
.LBB4_12:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
movl $425, %ecx # imm = 0x1A9
jmp .LBB4_2
.LBB4_14:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
movl $426, %ecx # imm = 0x1AA
jmp .LBB4_2
.LBB4_16:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
movl $268, %ecx # imm = 0x10C
jmp .LBB4_2
.LBB4_20:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
movl $270, %ecx # imm = 0x10E
jmp .LBB4_2
.LBB4_22:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
movl $431, %ecx # imm = 0x1AF
.LBB4_2:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end4:
.size _Z8AES_CUDAPcS_S_, .Lfunc_end4-_Z8AES_CUDAPcS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10cudaRunnerPh, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $s, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $256, %r9d # imm = 0x100
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $Nb, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $Nr, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $Nk, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $ek, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movl $176, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type Rcon_h,@object # @Rcon_h
.data
.globl Rcon_h
.p2align 4, 0x0
Rcon_h:
.ascii "\215\001\002\004\b\020 @\200\0336l\330\253M\232/^\274c\306\2275j\324\263}\372\357\305\2219r\344\323\275a\302\237%J\2243f\314\203\035:t\350\313\215\001\002\004\b\020 @\200\0336l\330\253M\232/^\274c\306\2275j\324\263}\372\357\305\2219r\344\323\275a\302\237%J\2243f\314\203\035:t\350\313\215\001\002\004\b\020 @\200\0336l\330\253M\232/^\274c\306\2275j\324\263}\372\357\305\2219r\344\323\275a\302\237%J\2243f\314\203\035:t\350\313\215\001\002\004\b\020 @\200\0336l\330\253M\232/^\274c\306\2275j\324\263}\372\357\305\2219r\344\323\275a\302\237%J\2243f\314\203\035:t\350\313\215\001\002\004\b\020 @\200\0336l\330\253M\232/^\274c\306\2275j\324\263}\372\357\305\2219r\344\323\275a\302\237%J\2243f\314\203\035:t\350\313\215"
.size Rcon_h, 256
.type s,@object # @s
.local s
.comm s,256,16
.type Nb,@object # @Nb
.local Nb
.comm Nb,4,4
.type Nr,@object # @Nr
.local Nr
.comm Nr,4,4
.type Nk,@object # @Nk
.local Nk
.comm Nk,4,4
.type ek,@object # @ek
.local ek
.comm ek,176,16
.type _ZL3s_h,@object # @_ZL3s_h
.section .rodata,"a",@progbits
.p2align 4, 0x0
_ZL3s_h:
.ascii "c|w{\362ko\3050\001g+\376\327\253v\312\202\311}\372YG\360\255\324\242\257\234\244r\300\267\375\223&6?\367\3144\245\345\361q\3301\025\004\307#\303\030\226\005\232\007\022\200\342\353'\262u\t\203,\032\033nZ\240R
.size _ZL3s_h, 256
.type _Z10cudaRunnerPh,@object # @_Z10cudaRunnerPh
.globl _Z10cudaRunnerPh
.p2align 3, 0x0
_Z10cudaRunnerPh:
.quad _Z25__device_stub__cudaRunnerPh
.size _Z10cudaRunnerPh, 8
.type _ZL4Nk_h,@object # @_ZL4Nk_h
.p2align 2, 0x0
_ZL4Nk_h:
.long 4 # 0x4
.size _ZL4Nk_h, 4
.type _ZL4Nr_h,@object # @_ZL4Nr_h
.p2align 2, 0x0
_ZL4Nr_h:
.long 10 # 0xa
.size _ZL4Nr_h, 4
.type _ZL4Nb_h,@object # @_ZL4Nb_h
.p2align 2, 0x0
_ZL4Nb_h:
.long 4 # 0x4
.size _ZL4Nb_h, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "cudaDevAssistant: %s %d\n"
.size .L.str, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10cudaRunnerPh"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "s"
.size .L__unnamed_2, 2
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "Nb"
.size .L__unnamed_3, 3
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "Nr"
.size .L__unnamed_4, 3
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "Nk"
.size .L__unnamed_5, 3
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "ek"
.size .L__unnamed_6, 3
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__cudaRunnerPh
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym s
.addrsig_sym Nb
.addrsig_sym Nr
.addrsig_sym Nk
.addrsig_sym ek
.addrsig_sym _ZL3s_h
.addrsig_sym _Z10cudaRunnerPh
.addrsig_sym _ZL4Nk_h
.addrsig_sym _ZL4Nr_h
.addrsig_sym _ZL4Nb_h
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016337e_00000000-6_CasAES128_CUDA_NOUNAR_asFUNCT.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2068:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z2swj
.type _Z2swj, @function
_Z2swj:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edi, %edx
leaq _ZL3s_h(%rip), %rcx
movl %edi, %eax
shrl $24, %eax
cltq
movzbl (%rcx,%rax), %eax
movl %edi, %esi
shrl $16, %esi
movzbl %sil, %esi
movzbl (%rcx,%rsi), %esi
sall $16, %esi
sall $24, %eax
orl %esi, %eax
movzbl %dh, %esi
movzbl (%rcx,%rsi), %ebx
movb %bl, %ah
movzbl %dil, %edx
movb (%rcx,%rdx), %al
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z2swj, .-_Z2swj
.globl _Z2sbPh
.type _Z2sbPh, @function
_Z2sbPh:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z2sbPh, .-_Z2sbPh
.globl _Z2mcPh
.type _Z2mcPh, @function
_Z2mcPh:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z2mcPh, .-_Z2mcPh
.globl _Z2srPh
.type _Z2srPh, @function
_Z2srPh:
.LFB2061:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z2srPh, .-_Z2srPh
.globl _Z2rwj
.type _Z2rwj, @function
_Z2rwj:
.LFB2062:
.cfi_startproc
endbr64
movl %edi, %edx
movl %edi, %eax
shrl $16, %eax
movzbl %dh, %ecx
sall $16, %ecx
sall $24, %eax
orl %ecx, %eax
movb %dl, %ah
shrl $24, %edx
movb %dl, %al
ret
.cfi_endproc
.LFE2062:
.size _Z2rwj, .-_Z2rwj
.globl _Z5K_ExpPhPj
.type _Z5K_ExpPhPj, @function
_Z5K_ExpPhPj:
.LFB2063:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $192, %rsp
.cfi_def_cfa_offset 240
movq %rsi, %r13
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
movq %rsp, %rbp
leaq 16(%rsp), %rcx
movq %rbp, %rax
.L13:
movzbl (%rdi), %edx
movb %dl, 3(%rax)
movzbl 1(%rdi), %edx
movb %dl, 2(%rax)
movzbl 2(%rdi), %edx
movb %dl, 1(%rax)
movzbl 3(%rdi), %edx
movb %dl, (%rax)
addq $4, %rdi
addq $4, %rax
cmpq %rcx, %rax
jne .L13
movl $4, %ebx
leaq Rcon_h(%rip), %r14
jmp .L18
.L15:
xorl (%r12), %eax
movl %eax, 16(%r12)
addl $1, %ebx
addq $4, %rbp
cmpl $44, %ebx
je .L24
.L18:
movq %rbp, %r12
movl 12(%rbp), %edi
movl %edi, %eax
testb $3, %bl
jne .L15
call _Z2rwj
movl %eax, %edi
call _Z2swj
leal 3(%rbx), %edx
testl %ebx, %ebx
cmovns %ebx, %edx
sarl $2, %edx
movslq %edx, %rdx
movl %eax, %edi
shrl $24, %edi
xorb (%r14,%rdx), %dil
sall $24, %edi
andl $16777215, %eax
orl %eax, %edi
movl %edi, %eax
testl %ebx, %ebx
jne .L15
call _Z2swj
xorl 0(%rbp), %eax
movl %eax, 16(%rbp)
addl $1, %ebx
addq $4, %rbp
jmp .L18
.L24:
movl $0, %eax
.L17:
movl (%rsp,%rax), %edx
movl %edx, 0(%r13,%rax)
addq $4, %rax
cmpq $176, %rax
jne .L17
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $192, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size _Z5K_ExpPhPj, .-_Z5K_ExpPhPj
.globl _Z3arkPhi
.type _Z3arkPhi, @function
_Z3arkPhi:
.LFB2064:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2064:
.size _Z3arkPhi, .-_Z3arkPhi
.globl _Z30__device_stub__Z10cudaRunnerPhPh
.type _Z30__device_stub__Z10cudaRunnerPhPh, @function
_Z30__device_stub__Z10cudaRunnerPhPh:
.LFB2090:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L32
.L28:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10cudaRunnerPh(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L28
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z30__device_stub__Z10cudaRunnerPhPh, .-_Z30__device_stub__Z10cudaRunnerPhPh
.globl _Z10cudaRunnerPh
.type _Z10cudaRunnerPh, @function
_Z10cudaRunnerPh:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10cudaRunnerPhPh
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z10cudaRunnerPh, .-_Z10cudaRunnerPh
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "cudaDevAssistant: %s %d\n"
.text
.globl _Z8AES_CUDAPcS_S_
.type _Z8AES_CUDAPcS_S_, @function
_Z8AES_CUDAPcS_S_:
.LFB2065:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $296, %rsp
.cfi_def_cfa_offset 336
movq %rdi, %rbp
movq %rsi, %r12
movq %rdx, %rbx
movq %fs:40, %rax
movq %rax, 280(%rsp)
xorl %eax, %eax
call clock@PLT
movq %rax, %r13
movq $0, 240(%rsp)
movq $0, 248(%rsp)
movl $0, %eax
.L37:
movzbl 0(%rbp,%rax), %edx
movb %dl, 240(%rsp,%rax)
movzbl (%rbx,%rax), %edx
movb %dl, 224(%rsp,%rax)
addq $1, %rax
cmpq $16, %rax
jne .L37
leaq 48(%rsp), %rsi
leaq 224(%rsp), %rdi
call _Z5K_ExpPhPj
movl $0, %edi
call cudaSetDevice@PLT
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL4Nk_h(%rip), %rsi
leaq _ZL2Nk(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L54
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL4Nr_h(%rip), %rsi
leaq _ZL2Nr(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L55
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL4Nb_h(%rip), %rsi
leaq _ZL2Nb(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L56
movl $1, %r8d
movl $0, %ecx
movl $256, %edx
leaq _ZL3s_h(%rip), %rsi
leaq _ZL1s(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L57
leaq 48(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $176, %edx
leaq _ZL2ek(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L58
call cudaThreadSynchronize@PLT
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L59
movzbl 240(%rsp), %eax
movb %al, 256(%rsp)
movzbl 241(%rsp), %eax
movb %al, 260(%rsp)
movzbl 242(%rsp), %eax
movb %al, 264(%rsp)
movzbl 243(%rsp), %eax
movb %al, 268(%rsp)
movzbl 244(%rsp), %eax
movb %al, 257(%rsp)
movzbl 245(%rsp), %eax
movb %al, 261(%rsp)
movzbl 246(%rsp), %eax
movb %al, 265(%rsp)
movzbl 247(%rsp), %eax
movb %al, 269(%rsp)
movzbl 248(%rsp), %eax
movb %al, 258(%rsp)
movzbl 249(%rsp), %eax
movb %al, 262(%rsp)
movzbl 250(%rsp), %eax
movb %al, 266(%rsp)
movzbl 251(%rsp), %eax
movb %al, 270(%rsp)
movzbl 252(%rsp), %eax
movb %al, 259(%rsp)
movzbl 253(%rsp), %eax
movb %al, 263(%rsp)
movzbl 254(%rsp), %eax
movb %al, 267(%rsp)
movzbl 255(%rsp), %eax
movb %al, 271(%rsp)
movl $0, %ebx
leaq 256(%rsp), %rbp
.L44:
movl $16, %ecx
cmpq %rcx, %rbx
cmovnb %rbx, %rcx
subq %rbx, %rcx
leaq 0(%rbp,%rbx), %rsi
leaq 240(%rsp,%rbx), %rdi
movl $1, %edx
call __memcpy_chk@PLT
addq $1, %rbx
cmpq $16, %rbx
jne .L44
leaq 240(%rsp), %rsi
movl $1, %ecx
movl $16, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L60
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L61
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L62
.L47:
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L63
leaq 240(%rsp), %rdi
movl $2, %ecx
movl $16, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L64
movzbl 240(%rsp), %eax
movb %al, (%r12)
movzbl 241(%rsp), %eax
movb %al, 4(%r12)
movzbl 242(%rsp), %eax
movb %al, 8(%r12)
movzbl 243(%rsp), %eax
movb %al, 12(%r12)
movzbl 244(%rsp), %eax
movb %al, 1(%r12)
movzbl 245(%rsp), %eax
movb %al, 5(%r12)
movzbl 246(%rsp), %eax
movb %al, 9(%r12)
movzbl 247(%rsp), %eax
movb %al, 13(%r12)
movzbl 248(%rsp), %eax
movb %al, 2(%r12)
movzbl 249(%rsp), %eax
movb %al, 6(%r12)
movzbl 250(%rsp), %eax
movb %al, 10(%r12)
movzbl 251(%rsp), %eax
movb %al, 14(%r12)
movzbl 252(%rsp), %eax
movb %al, 3(%r12)
movzbl 253(%rsp), %eax
movb %al, 7(%r12)
movzbl 254(%rsp), %eax
movb %al, 11(%r12)
movzbl 255(%rsp), %eax
movb %al, 15(%r12)
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssq %r13, %xmm1
subss %xmm1, %xmm0
divss .LC1(%rip), %xmm0
mulss .LC2(%rip), %xmm0
movss %xmm0, 12(%rsp)
movq 16(%rsp), %rdi
call cudaFree@PLT
call cudaDeviceReset@PLT
cvttss2siq 12(%rsp), %rax
movq 280(%rsp), %rdx
subq %fs:40, %rdx
jne .L65
addq $296, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $535, %r8d
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L55:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $543, %r8d
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L56:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $903, %r8d
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L57:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $920, %r8d
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L58:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $823, %r8d
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L59:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $425, %r8d
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L60:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $426, %r8d
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L61:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $268, %r8d
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L62:
movq 16(%rsp), %rdi
call _Z30__device_stub__Z10cudaRunnerPhPh
jmp .L47
.L63:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $270, %r8d
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L64:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $431, %r8d
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L65:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2065:
.size _Z8AES_CUDAPcS_S_, .-_Z8AES_CUDAPcS_S_
.section .rodata.str1.1
.LC3:
.string "_Z10cudaRunnerPh"
.LC4:
.string "s"
.LC5:
.string "Nb"
.LC6:
.string "Nr"
.LC7:
.string "Nk"
.LC8:
.string "ek"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2093:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10cudaRunnerPh(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $256, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1s(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2Nb(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2Nr(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2Nk(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $176, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2ek(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL2ek
.comm _ZL2ek,176,32
.local _ZL2Nk
.comm _ZL2Nk,4,4
.local _ZL2Nr
.comm _ZL2Nr,4,4
.local _ZL2Nb
.comm _ZL2Nb,4,4
.local _ZL1s
.comm _ZL1s,256,32
.globl Rcon_h
.data
.align 32
.type Rcon_h, @object
.size Rcon_h, 256
Rcon_h:
.ascii "\215\001\002\004\b\020 @\200\0336l\330\253M\232/^\274c\306\227"
.ascii "5j\324\263}\372\357\305\2219r\344\323\275a\302\237%J\2243f\314"
.ascii "\203\035:t\350\313\215\001\002\004\b\020 @\200\0336l\330\253"
.ascii "M\232/^\274c\306\2275j\324\263}\372\357\305\2219r\344\323\275"
.ascii "a\302\237%J\2243f\314\203\035:t\350\313\215\001\002\004\b\020"
.ascii " @\200\0336l\330\253M\232/^\274c\306\2275j\324\263}\372\357\305"
.ascii "\2219r\344\323\275a\302\237%J\2243f\314\203\035:t\350\313\215"
.ascii "\001\002\004\b\020 @\200\0336l\330\253M\232/^\274c\306\2275j"
.ascii "\324\263}\372\357\305\2219r\344\323\275a\302\237%J\2243f\314"
.ascii "\203\035:t\350\313\215\001\002\004\b\020 @\200\0336l\330\253"
.ascii "M\232/^\274c\306\2275j\324\263}\372\357\305\2219r\344\323\275"
.ascii "a\302\237%J\2243f\314\203\035:t\350\313\215"
.section .rodata
.align 32
.type _ZL3s_h, @object
.size _ZL3s_h, 256
_ZL3s_h:
.string "c|w{\362ko\3050\001g+\376\327\253v\312\202\311}\372YG\360\255\324\242\257\234\244r\300\267\375\223&6?\367\3144\245\345\361q\3301\025\004\307#\303\030\226\005\232\007\022\200\342\353'\262u\t\203,\032\033nZ\240R;\326\263)\343/\204S\321"
.ascii "\355 \374\261[j\313\2769JLX\317\320\357\252\373CM3\205E\371\002"
.ascii "\177P<\237\250Q\243@\217\222\2358\365\274\266\332!\020\377\363"
.ascii "\322\315\f\023\354_\227D\027\304\247~=d]\031s`\201O\334\"*\220"
.ascii "\210F\356\270\024\336^\013\333\3402:\nI\006$\\\302\323\254b\221"
.ascii "\225\344y\347\3107m\215\325N\251lV\364\352ez\256\b\272x%.\034"
.ascii "\246\264\306\350\335t\037K\275\213\212p>\265fH\003\366\016a5"
.ascii "W\271\206\301\035\236\341\370\230\021i\331\216\224\233\036\207"
.ascii "\351\316U(\337\214\241\211\r\277\346BhA\231-\017\260T\273\026"
.align 4
.type _ZL4Nk_h, @object
.size _ZL4Nk_h, 4
_ZL4Nk_h:
.long 4
.align 4
.type _ZL4Nr_h, @object
.size _ZL4Nr_h, 4
_ZL4Nr_h:
.long 10
.align 4
.type _ZL4Nb_h, @object
.size _ZL4Nb_h, 4
_ZL4Nb_h:
.long 4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1232348160
.align 4
.LC2:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "CasAES128_CUDA_NOUNAR_asFUNCT.hip"
.globl _Z2swj # -- Begin function _Z2swj
.p2align 4, 0x90
.type _Z2swj,@function
_Z2swj: # @_Z2swj
.cfi_startproc
# %bb.0:
movl %edi, %eax
movl %edi, %ecx
movzbl %ah, %edx
movzbl %al, %esi
shrl $16, %eax
shrl $24, %ecx
movzbl %al, %eax
movzbl _ZL3s_h(%rax), %edi
movzbl _ZL3s_h(%rdx), %eax
movzbl _ZL3s_h(%rsi), %edx
movzbl _ZL3s_h(%rcx), %ecx
shll $24, %ecx
shll $16, %edi
orl %ecx, %edi
shll $8, %eax
orl %edi, %eax
orl %edx, %eax
retq
.Lfunc_end0:
.size _Z2swj, .Lfunc_end0-_Z2swj
.cfi_endproc
# -- End function
.globl _Z2rwj # -- Begin function _Z2rwj
.p2align 4, 0x90
.type _Z2rwj,@function
_Z2rwj: # @_Z2rwj
.cfi_startproc
# %bb.0:
movl %edi, %eax
roll $8, %eax
retq
.Lfunc_end1:
.size _Z2rwj, .Lfunc_end1-_Z2rwj
.cfi_endproc
# -- End function
.globl _Z5K_ExpPhPj # -- Begin function _Z5K_ExpPhPj
.p2align 4, 0x90
.type _Z5K_ExpPhPj,@function
_Z5K_ExpPhPj: # @_Z5K_ExpPhPj
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rsi, %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movzbl (%rdi,%rcx,4), %edx
movb %dl, 3(%rsp,%rcx,4)
movzbl 1(%rdi,%rcx,4), %edx
movb %dl, 2(%rsp,%rcx,4)
movzbl 2(%rdi,%rcx,4), %edx
movb %dl, 1(%rsp,%rcx,4)
movzbl 3(%rdi,%rcx,4), %edx
movb %dl, (%rsp,%rcx,4)
incq %rcx
cmpq $4, %rcx
jne .LBB2_1
# %bb.2: # %.preheader53.preheader
movl $4, %ecx
movl 12(%rsp), %edx
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_5: # in Loop: Header=BB2_3 Depth=1
roll $8, %edx
movl %edx, %esi
movzbl %dh, %edi
movzbl %dl, %r8d
shrl $16, %edx
shrl $24, %esi
movzbl %dl, %edx
movzbl _ZL3s_h(%rdx), %edx
movzbl _ZL3s_h(%rdi), %r9d
movzbl _ZL3s_h(%r8), %edi
shll $16, %edx
orl %edi, %edx
shll $8, %r9d
orl %edx, %r9d
movl %ecx, %edx
shrl $2, %edx
movzbl Rcon_h(%rdx), %edi
xorb _ZL3s_h(%rsi), %dil
movl %r9d, %edx
.LBB2_6: # in Loop: Header=BB2_3 Depth=1
movzbl %dil, %esi
shll $24, %esi
andl $16777215, %edx # imm = 0xFFFFFF
orl %esi, %edx
xorl -16(%rsp,%rcx,4), %edx
movl %edx, (%rsp,%rcx,4)
incq %rcx
cmpq $44, %rcx
je .LBB2_7
.LBB2_3: # %.preheader53
# =>This Inner Loop Header: Depth=1
testb $3, %cl
je .LBB2_5
# %bb.4: # in Loop: Header=BB2_3 Depth=1
movl %edx, %edi
shrl $24, %edi
jmp .LBB2_6
.LBB2_7: # %.preheader.preheader
movq %rsp, %rsi
movl $176, %edx
movq %rax, %rdi
callq memcpy@PLT
addq $184, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z5K_ExpPhPj, .Lfunc_end2-_Z5K_ExpPhPj
.cfi_endproc
# -- End function
.globl _Z25__device_stub__cudaRunnerPh # -- Begin function _Z25__device_stub__cudaRunnerPh
.p2align 4, 0x90
.type _Z25__device_stub__cudaRunnerPh,@function
_Z25__device_stub__cudaRunnerPh: # @_Z25__device_stub__cudaRunnerPh
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10cudaRunnerPh, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end3:
.size _Z25__device_stub__cudaRunnerPh, .Lfunc_end3-_Z25__device_stub__cudaRunnerPh
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z8AES_CUDAPcS_S_
.LCPI4_0:
.long 0x49742400 # float 1.0E+6
.LCPI4_1:
.long 0x447a0000 # float 1000
.text
.globl _Z8AES_CUDAPcS_S_
.p2align 4, 0x90
.type _Z8AES_CUDAPcS_S_,@function
_Z8AES_CUDAPcS_S_: # @_Z8AES_CUDAPcS_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $288, %rsp # imm = 0x120
.cfi_def_cfa_offset 336
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %r15
movq %rsi, %r14
movq %rdi, %r12
callq clock
movq %rax, %rbx
movups (%r12), %xmm0
movaps %xmm0, (%rsp)
movups (%r15), %xmm0
movaps %xmm0, 96(%rsp)
leaq 96(%rsp), %rdi
leaq 112(%rsp), %rsi
callq _Z5K_ExpPhPj
xorl %edi, %edi
callq hipSetDevice
movl $Nk, %edi
movl $_ZL4Nk_h, %esi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
testl %eax, %eax
jne .LBB4_1
# %bb.3: # %_Z13cudaDevAssist10hipError_tib.exit
movl $Nr, %edi
movl $_ZL4Nr_h, %esi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
testl %eax, %eax
jne .LBB4_4
# %bb.5: # %_Z13cudaDevAssist10hipError_tib.exit34
movl $Nb, %edi
movl $_ZL4Nb_h, %esi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
testl %eax, %eax
jne .LBB4_6
# %bb.7: # %_Z13cudaDevAssist10hipError_tib.exit36
movl $s, %edi
movl $_ZL3s_h, %esi
movl $256, %edx # imm = 0x100
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
testl %eax, %eax
jne .LBB4_8
# %bb.9: # %_Z13cudaDevAssist10hipError_tib.exit38
leaq 112(%rsp), %rsi
movl $ek, %edi
movl $176, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
testl %eax, %eax
jne .LBB4_10
# %bb.11: # %_Z13cudaDevAssist10hipError_tib.exit40
callq hipDeviceSynchronize
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movl $16, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB4_12
# %bb.13: # %_Z13cudaDevAssist10hipError_tib.exit42
movzbl 1(%rsp), %eax
movzbl 2(%rsp), %ecx
movzbl 3(%rsp), %edx
movzbl 4(%rsp), %esi
movzbl 6(%rsp), %edi
movzbl 7(%rsp), %r8d
movzbl 8(%rsp), %r9d
movzbl 9(%rsp), %r10d
movzbl 11(%rsp), %r11d
movzbl 12(%rsp), %ebp
movzbl 13(%rsp), %r15d
movzbl 14(%rsp), %r12d
movb %sil, 1(%rsp)
movb %r9b, 2(%rsp)
movb %bpl, 3(%rsp)
movb %al, 4(%rsp)
movb %r10b, 6(%rsp)
movb %r15b, 7(%rsp)
movb %cl, 8(%rsp)
movb %dil, 9(%rsp)
movb %r12b, 11(%rsp)
movb %dl, 12(%rsp)
movb %r8b, 13(%rsp)
movb %r11b, 14(%rsp)
movq 16(%rsp), %rdi
movq %rsp, %rsi
movl $16, %edx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_14
# %bb.15: # %_Z13cudaDevAssist10hipError_tib.exit44
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB4_16
# %bb.17: # %_Z13cudaDevAssist10hipError_tib.exit46
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_19
# %bb.18:
movq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 88(%rsp), %rax
movq %rax, 32(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z10cudaRunnerPh, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_19:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB4_20
# %bb.21: # %_Z13cudaDevAssist10hipError_tib.exit48
movq 16(%rsp), %rsi
movq %rsp, %rdi
movl $16, %edx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_22
# %bb.23: # %_Z13cudaDevAssist10hipError_tib.exit50
movzbl (%rsp), %eax
movb %al, (%r14)
movzbl 1(%rsp), %eax
movb %al, 4(%r14)
movzbl 2(%rsp), %eax
movb %al, 8(%r14)
movzbl 3(%rsp), %eax
movb %al, 12(%r14)
movzbl 4(%rsp), %eax
movb %al, 1(%r14)
movzbl 5(%rsp), %eax
movb %al, 5(%r14)
movzbl 6(%rsp), %eax
movb %al, 9(%r14)
movzbl 7(%rsp), %eax
movb %al, 13(%r14)
movzbl 8(%rsp), %eax
movb %al, 2(%r14)
movzbl 9(%rsp), %eax
movb %al, 6(%r14)
movzbl 10(%rsp), %eax
movb %al, 10(%r14)
movzbl 11(%rsp), %eax
movb %al, 14(%r14)
movzbl 12(%rsp), %eax
movb %al, 3(%r14)
movzbl 13(%rsp), %eax
movb %al, 7(%r14)
movzbl 14(%rsp), %eax
movb %al, 11(%r14)
movzbl 15(%rsp), %eax
movb %al, 15(%r14)
callq clock
cvtsi2ss %rax, %xmm1
cvtsi2ss %rbx, %xmm0
subss %xmm0, %xmm1
divss .LCPI4_0(%rip), %xmm1
mulss .LCPI4_1(%rip), %xmm1
movss %xmm1, 28(%rsp) # 4-byte Spill
movq 16(%rsp), %rdi
callq hipFree
callq hipDeviceReset
cvttss2si 28(%rsp), %rax # 4-byte Folded Reload
addq $288, %rsp # imm = 0x120
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_1:
.cfi_def_cfa_offset 336
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
movl $535, %ecx # imm = 0x217
jmp .LBB4_2
.LBB4_4:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
movl $543, %ecx # imm = 0x21F
jmp .LBB4_2
.LBB4_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
movl $903, %ecx # imm = 0x387
jmp .LBB4_2
.LBB4_8:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
movl $920, %ecx # imm = 0x398
jmp .LBB4_2
.LBB4_10:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
movl $823, %ecx # imm = 0x337
jmp .LBB4_2
.LBB4_12:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
movl $425, %ecx # imm = 0x1A9
jmp .LBB4_2
.LBB4_14:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
movl $426, %ecx # imm = 0x1AA
jmp .LBB4_2
.LBB4_16:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
movl $268, %ecx # imm = 0x10C
jmp .LBB4_2
.LBB4_20:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
movl $270, %ecx # imm = 0x10E
jmp .LBB4_2
.LBB4_22:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
movl $431, %ecx # imm = 0x1AF
.LBB4_2:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end4:
.size _Z8AES_CUDAPcS_S_, .Lfunc_end4-_Z8AES_CUDAPcS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10cudaRunnerPh, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $s, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $256, %r9d # imm = 0x100
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $Nb, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $Nr, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $Nk, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $ek, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movl $176, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type Rcon_h,@object # @Rcon_h
.data
.globl Rcon_h
.p2align 4, 0x0
Rcon_h:
.ascii "\215\001\002\004\b\020 @\200\0336l\330\253M\232/^\274c\306\2275j\324\263}\372\357\305\2219r\344\323\275a\302\237%J\2243f\314\203\035:t\350\313\215\001\002\004\b\020 @\200\0336l\330\253M\232/^\274c\306\2275j\324\263}\372\357\305\2219r\344\323\275a\302\237%J\2243f\314\203\035:t\350\313\215\001\002\004\b\020 @\200\0336l\330\253M\232/^\274c\306\2275j\324\263}\372\357\305\2219r\344\323\275a\302\237%J\2243f\314\203\035:t\350\313\215\001\002\004\b\020 @\200\0336l\330\253M\232/^\274c\306\2275j\324\263}\372\357\305\2219r\344\323\275a\302\237%J\2243f\314\203\035:t\350\313\215\001\002\004\b\020 @\200\0336l\330\253M\232/^\274c\306\2275j\324\263}\372\357\305\2219r\344\323\275a\302\237%J\2243f\314\203\035:t\350\313\215"
.size Rcon_h, 256
.type s,@object # @s
.local s
.comm s,256,16
.type Nb,@object # @Nb
.local Nb
.comm Nb,4,4
.type Nr,@object # @Nr
.local Nr
.comm Nr,4,4
.type Nk,@object # @Nk
.local Nk
.comm Nk,4,4
.type ek,@object # @ek
.local ek
.comm ek,176,16
.type _ZL3s_h,@object # @_ZL3s_h
.section .rodata,"a",@progbits
.p2align 4, 0x0
_ZL3s_h:
.ascii "c|w{\362ko\3050\001g+\376\327\253v\312\202\311}\372YG\360\255\324\242\257\234\244r\300\267\375\223&6?\367\3144\245\345\361q\3301\025\004\307#\303\030\226\005\232\007\022\200\342\353'\262u\t\203,\032\033nZ\240R
.size _ZL3s_h, 256
.type _Z10cudaRunnerPh,@object # @_Z10cudaRunnerPh
.globl _Z10cudaRunnerPh
.p2align 3, 0x0
_Z10cudaRunnerPh:
.quad _Z25__device_stub__cudaRunnerPh
.size _Z10cudaRunnerPh, 8
.type _ZL4Nk_h,@object # @_ZL4Nk_h
.p2align 2, 0x0
_ZL4Nk_h:
.long 4 # 0x4
.size _ZL4Nk_h, 4
.type _ZL4Nr_h,@object # @_ZL4Nr_h
.p2align 2, 0x0
_ZL4Nr_h:
.long 10 # 0xa
.size _ZL4Nr_h, 4
.type _ZL4Nb_h,@object # @_ZL4Nb_h
.p2align 2, 0x0
_ZL4Nb_h:
.long 4 # 0x4
.size _ZL4Nb_h, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "cudaDevAssistant: %s %d\n"
.size .L.str, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10cudaRunnerPh"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "s"
.size .L__unnamed_2, 2
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "Nb"
.size .L__unnamed_3, 3
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "Nr"
.size .L__unnamed_4, 3
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "Nk"
.size .L__unnamed_5, 3
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "ek"
.size .L__unnamed_6, 3
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__cudaRunnerPh
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym s
.addrsig_sym Nb
.addrsig_sym Nr
.addrsig_sym Nk
.addrsig_sym ek
.addrsig_sym _ZL3s_h
.addrsig_sym _Z10cudaRunnerPh
.addrsig_sym _ZL4Nk_h
.addrsig_sym _ZL4Nr_h
.addrsig_sym _ZL4Nb_h
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <algorithm>
#include <string>
#include <cstdlib>
using namespace std;
#define N 10
__global__ void addKernel(int *a, int *b, int *c)
{
int tid = blockIdx.x;
if ( tid < N )
{
c[tid] = a[tid] + b[tid];
}
}
int main()
{
int *a, *b, *c;
a = new int[N];
b = new int[N];
c = new int[N];
int *dev_a, *dev_b, *dev_c;
if ( cudaErrorMemoryAllocation == cudaMalloc( (void**)&dev_a, N * sizeof(int) ) )
{
fprintf(stderr, "Error allocating memory\n");
return -1;
}
if ( cudaErrorMemoryAllocation == cudaMalloc( (void**)&dev_b, N * sizeof(int) ) )
{
fprintf(stderr, "Error allocating memory\n");
return -1;
}
if ( cudaErrorMemoryAllocation == cudaMalloc( (void**)&dev_c, N * sizeof(int) ) )
{
fprintf(stderr, "Error allocating memory\n");
return -1;
}
for (int i=0; i < N; ++i)
{
a[i]= i;
b[i]= i;
}
int retA = cudaMemcpy( dev_a, a, N*sizeof(int), cudaMemcpyHostToDevice);
if (retA == cudaSuccess) {
printf("Allocated memory ok!\n");
}
else if ( retA == cudaErrorInvalidValue )
{
fprintf(stderr, "Invalid value\n");
return -1;
}
else if ( retA == cudaErrorInvalidDevicePointer )
{
fprintf(stderr, "Invalid pointer\n");
return -1;
}
else
{
fprintf(stderr, "Invalid direction\n");
printf("Error type %x\n",retA );
return -1;
}
if ( cudaMemcpy( dev_b, b, N*sizeof(int), cudaMemcpyHostToDevice ) != cudaSuccess )
{
fprintf(stderr, "Something goes wrong in dev_b\n");
}
addKernel<<<N,1>>>(dev_a, dev_b, dev_c);
cudaMemcpy(c, dev_c, N*sizeof(int), cudaMemcpyDeviceToHost );
for (int i=0;i<N;++i)
{
printf("%d + %d = %d\n",a[i], b[i], c[i]);
}
printf("\n");
cudaFree( dev_a );
cudaFree( dev_b );
cudaFree( dev_c );
return 0;
} | code for sm_80
Function : _Z9addKernelPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0x9, PT ; /* 0x000000090600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <algorithm>
#include <string>
#include <cstdlib>
using namespace std;
#define N 10
__global__ void addKernel(int *a, int *b, int *c)
{
int tid = blockIdx.x;
if ( tid < N )
{
c[tid] = a[tid] + b[tid];
}
}
int main()
{
int *a, *b, *c;
a = new int[N];
b = new int[N];
c = new int[N];
int *dev_a, *dev_b, *dev_c;
if ( cudaErrorMemoryAllocation == cudaMalloc( (void**)&dev_a, N * sizeof(int) ) )
{
fprintf(stderr, "Error allocating memory\n");
return -1;
}
if ( cudaErrorMemoryAllocation == cudaMalloc( (void**)&dev_b, N * sizeof(int) ) )
{
fprintf(stderr, "Error allocating memory\n");
return -1;
}
if ( cudaErrorMemoryAllocation == cudaMalloc( (void**)&dev_c, N * sizeof(int) ) )
{
fprintf(stderr, "Error allocating memory\n");
return -1;
}
for (int i=0; i < N; ++i)
{
a[i]= i;
b[i]= i;
}
int retA = cudaMemcpy( dev_a, a, N*sizeof(int), cudaMemcpyHostToDevice);
if (retA == cudaSuccess) {
printf("Allocated memory ok!\n");
}
else if ( retA == cudaErrorInvalidValue )
{
fprintf(stderr, "Invalid value\n");
return -1;
}
else if ( retA == cudaErrorInvalidDevicePointer )
{
fprintf(stderr, "Invalid pointer\n");
return -1;
}
else
{
fprintf(stderr, "Invalid direction\n");
printf("Error type %x\n",retA );
return -1;
}
if ( cudaMemcpy( dev_b, b, N*sizeof(int), cudaMemcpyHostToDevice ) != cudaSuccess )
{
fprintf(stderr, "Something goes wrong in dev_b\n");
}
addKernel<<<N,1>>>(dev_a, dev_b, dev_c);
cudaMemcpy(c, dev_c, N*sizeof(int), cudaMemcpyDeviceToHost );
for (int i=0;i<N;++i)
{
printf("%d + %d = %d\n",a[i], b[i], c[i]);
}
printf("\n");
cudaFree( dev_a );
cudaFree( dev_b );
cudaFree( dev_c );
return 0;
} | .file "tmpxft_00110bfb_00000000-6_sum_vectors.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3926:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3926:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9addKernelPiS_S_PiS_S_
.type _Z32__device_stub__Z9addKernelPiS_S_PiS_S_, @function
_Z32__device_stub__Z9addKernelPiS_S_PiS_S_:
.LFB3948:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addKernelPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3948:
.size _Z32__device_stub__Z9addKernelPiS_S_PiS_S_, .-_Z32__device_stub__Z9addKernelPiS_S_PiS_S_
.globl _Z9addKernelPiS_S_
.type _Z9addKernelPiS_S_, @function
_Z9addKernelPiS_S_:
.LFB3949:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9addKernelPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3949:
.size _Z9addKernelPiS_S_, .-_Z9addKernelPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Error allocating memory\n"
.LC1:
.string "Allocated memory ok!\n"
.LC2:
.string "Invalid value\n"
.LC3:
.string "Invalid pointer\n"
.LC4:
.string "Invalid direction\n"
.LC5:
.string "Error type %x\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "Something goes wrong in dev_b\n"
.section .rodata.str1.1
.LC7:
.string "%d + %d = %d\n"
.LC8:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3923:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $40, %edi
call _Znam@PLT
movq %rax, %rbp
movl $40, %edi
call _Znam@PLT
movq %rax, %r12
movl $40, %edi
call _Znam@PLT
movq %rax, %r14
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
cmpl $2, %eax
je .L28
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
cmpl $2, %eax
je .L29
leaq 24(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
cmpl $2, %eax
je .L30
movl $0, %eax
.L15:
movl %eax, 0(%rbp,%rax,4)
movl %eax, (%r12,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L15
movl $1, %ecx
movl $40, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r13d
testl %eax, %eax
je .L31
cmpl $1, %eax
je .L32
cmpl $17, %eax
je .L33
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r13d, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %r13d
.L11:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl %r13d, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %r13d
jmp .L11
.L29:
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %r13d
jmp .L11
.L30:
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %r13d
jmp .L11
.L31:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $40, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L35
.L18:
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $10, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L21:
movl $2, %ecx
movl $40, %edx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC7(%rip), %r15
.L22:
movl (%r12,%rbx), %ecx
movl 0(%rbp,%rbx), %edx
movl (%r14,%rbx), %r8d
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $40, %rbx
jne .L22
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
jmp .L11
.L32:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %r13d
jmp .L11
.L33:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %r13d
jmp .L11
.L35:
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L18
.L36:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z9addKernelPiS_S_PiS_S_
jmp .L21
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3923:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z9addKernelPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3951:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addKernelPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3951:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <algorithm>
#include <string>
#include <cstdlib>
using namespace std;
#define N 10
__global__ void addKernel(int *a, int *b, int *c)
{
int tid = blockIdx.x;
if ( tid < N )
{
c[tid] = a[tid] + b[tid];
}
}
int main()
{
int *a, *b, *c;
a = new int[N];
b = new int[N];
c = new int[N];
int *dev_a, *dev_b, *dev_c;
if ( cudaErrorMemoryAllocation == cudaMalloc( (void**)&dev_a, N * sizeof(int) ) )
{
fprintf(stderr, "Error allocating memory\n");
return -1;
}
if ( cudaErrorMemoryAllocation == cudaMalloc( (void**)&dev_b, N * sizeof(int) ) )
{
fprintf(stderr, "Error allocating memory\n");
return -1;
}
if ( cudaErrorMemoryAllocation == cudaMalloc( (void**)&dev_c, N * sizeof(int) ) )
{
fprintf(stderr, "Error allocating memory\n");
return -1;
}
for (int i=0; i < N; ++i)
{
a[i]= i;
b[i]= i;
}
int retA = cudaMemcpy( dev_a, a, N*sizeof(int), cudaMemcpyHostToDevice);
if (retA == cudaSuccess) {
printf("Allocated memory ok!\n");
}
else if ( retA == cudaErrorInvalidValue )
{
fprintf(stderr, "Invalid value\n");
return -1;
}
else if ( retA == cudaErrorInvalidDevicePointer )
{
fprintf(stderr, "Invalid pointer\n");
return -1;
}
else
{
fprintf(stderr, "Invalid direction\n");
printf("Error type %x\n",retA );
return -1;
}
if ( cudaMemcpy( dev_b, b, N*sizeof(int), cudaMemcpyHostToDevice ) != cudaSuccess )
{
fprintf(stderr, "Something goes wrong in dev_b\n");
}
addKernel<<<N,1>>>(dev_a, dev_b, dev_c);
cudaMemcpy(c, dev_c, N*sizeof(int), cudaMemcpyDeviceToHost );
for (int i=0;i<N;++i)
{
printf("%d + %d = %d\n",a[i], b[i], c[i]);
}
printf("\n");
cudaFree( dev_a );
cudaFree( dev_b );
cudaFree( dev_c );
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <algorithm>
#include <string>
#include <cstdlib>
using namespace std;
#define N 10
__global__ void addKernel(int *a, int *b, int *c)
{
int tid = blockIdx.x;
if ( tid < N )
{
c[tid] = a[tid] + b[tid];
}
}
int main()
{
int *a, *b, *c;
a = new int[N];
b = new int[N];
c = new int[N];
int *dev_a, *dev_b, *dev_c;
if ( hipErrorOutOfMemory == hipMalloc( (void**)&dev_a, N * sizeof(int) ) )
{
fprintf(stderr, "Error allocating memory\n");
return -1;
}
if ( hipErrorOutOfMemory == hipMalloc( (void**)&dev_b, N * sizeof(int) ) )
{
fprintf(stderr, "Error allocating memory\n");
return -1;
}
if ( hipErrorOutOfMemory == hipMalloc( (void**)&dev_c, N * sizeof(int) ) )
{
fprintf(stderr, "Error allocating memory\n");
return -1;
}
for (int i=0; i < N; ++i)
{
a[i]= i;
b[i]= i;
}
int retA = hipMemcpy( dev_a, a, N*sizeof(int), hipMemcpyHostToDevice);
if (retA == hipSuccess) {
printf("Allocated memory ok!\n");
}
else if ( retA == hipErrorInvalidValue )
{
fprintf(stderr, "Invalid value\n");
return -1;
}
else if ( retA == hipErrorInvalidDevicePointer )
{
fprintf(stderr, "Invalid pointer\n");
return -1;
}
else
{
fprintf(stderr, "Invalid direction\n");
printf("Error type %x\n",retA );
return -1;
}
if ( hipMemcpy( dev_b, b, N*sizeof(int), hipMemcpyHostToDevice ) != hipSuccess )
{
fprintf(stderr, "Something goes wrong in dev_b\n");
}
addKernel<<<N,1>>>(dev_a, dev_b, dev_c);
hipMemcpy(c, dev_c, N*sizeof(int), hipMemcpyDeviceToHost );
for (int i=0;i<N;++i)
{
printf("%d + %d = %d\n",a[i], b[i], c[i]);
}
printf("\n");
hipFree( dev_a );
hipFree( dev_b );
hipFree( dev_c );
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <algorithm>
#include <string>
#include <cstdlib>
using namespace std;
#define N 10
__global__ void addKernel(int *a, int *b, int *c)
{
int tid = blockIdx.x;
if ( tid < N )
{
c[tid] = a[tid] + b[tid];
}
}
int main()
{
int *a, *b, *c;
a = new int[N];
b = new int[N];
c = new int[N];
int *dev_a, *dev_b, *dev_c;
if ( hipErrorOutOfMemory == hipMalloc( (void**)&dev_a, N * sizeof(int) ) )
{
fprintf(stderr, "Error allocating memory\n");
return -1;
}
if ( hipErrorOutOfMemory == hipMalloc( (void**)&dev_b, N * sizeof(int) ) )
{
fprintf(stderr, "Error allocating memory\n");
return -1;
}
if ( hipErrorOutOfMemory == hipMalloc( (void**)&dev_c, N * sizeof(int) ) )
{
fprintf(stderr, "Error allocating memory\n");
return -1;
}
for (int i=0; i < N; ++i)
{
a[i]= i;
b[i]= i;
}
int retA = hipMemcpy( dev_a, a, N*sizeof(int), hipMemcpyHostToDevice);
if (retA == hipSuccess) {
printf("Allocated memory ok!\n");
}
else if ( retA == hipErrorInvalidValue )
{
fprintf(stderr, "Invalid value\n");
return -1;
}
else if ( retA == hipErrorInvalidDevicePointer )
{
fprintf(stderr, "Invalid pointer\n");
return -1;
}
else
{
fprintf(stderr, "Invalid direction\n");
printf("Error type %x\n",retA );
return -1;
}
if ( hipMemcpy( dev_b, b, N*sizeof(int), hipMemcpyHostToDevice ) != hipSuccess )
{
fprintf(stderr, "Something goes wrong in dev_b\n");
}
addKernel<<<N,1>>>(dev_a, dev_b, dev_c);
hipMemcpy(c, dev_c, N*sizeof(int), hipMemcpyDeviceToHost );
for (int i=0;i<N;++i)
{
printf("%d + %d = %d\n",a[i], b[i], c[i]);
}
printf("\n");
hipFree( dev_a );
hipFree( dev_b );
hipFree( dev_c );
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addKernelPiS_S_
.globl _Z9addKernelPiS_S_
.p2align 8
.type _Z9addKernelPiS_S_,@function
_Z9addKernelPiS_S_:
s_cmp_gt_i32 s15, 9
s_cbranch_scc1 .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addKernelPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addKernelPiS_S_, .Lfunc_end0-_Z9addKernelPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addKernelPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z9addKernelPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <algorithm>
#include <string>
#include <cstdlib>
using namespace std;
#define N 10
__global__ void addKernel(int *a, int *b, int *c)
{
int tid = blockIdx.x;
if ( tid < N )
{
c[tid] = a[tid] + b[tid];
}
}
int main()
{
int *a, *b, *c;
a = new int[N];
b = new int[N];
c = new int[N];
int *dev_a, *dev_b, *dev_c;
if ( hipErrorOutOfMemory == hipMalloc( (void**)&dev_a, N * sizeof(int) ) )
{
fprintf(stderr, "Error allocating memory\n");
return -1;
}
if ( hipErrorOutOfMemory == hipMalloc( (void**)&dev_b, N * sizeof(int) ) )
{
fprintf(stderr, "Error allocating memory\n");
return -1;
}
if ( hipErrorOutOfMemory == hipMalloc( (void**)&dev_c, N * sizeof(int) ) )
{
fprintf(stderr, "Error allocating memory\n");
return -1;
}
for (int i=0; i < N; ++i)
{
a[i]= i;
b[i]= i;
}
int retA = hipMemcpy( dev_a, a, N*sizeof(int), hipMemcpyHostToDevice);
if (retA == hipSuccess) {
printf("Allocated memory ok!\n");
}
else if ( retA == hipErrorInvalidValue )
{
fprintf(stderr, "Invalid value\n");
return -1;
}
else if ( retA == hipErrorInvalidDevicePointer )
{
fprintf(stderr, "Invalid pointer\n");
return -1;
}
else
{
fprintf(stderr, "Invalid direction\n");
printf("Error type %x\n",retA );
return -1;
}
if ( hipMemcpy( dev_b, b, N*sizeof(int), hipMemcpyHostToDevice ) != hipSuccess )
{
fprintf(stderr, "Something goes wrong in dev_b\n");
}
addKernel<<<N,1>>>(dev_a, dev_b, dev_c);
hipMemcpy(c, dev_c, N*sizeof(int), hipMemcpyDeviceToHost );
for (int i=0;i<N;++i)
{
printf("%d + %d = %d\n",a[i], b[i], c[i]);
}
printf("\n");
hipFree( dev_a );
hipFree( dev_b );
hipFree( dev_c );
return 0;
} | .text
.file "sum_vectors.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__addKernelPiS_S_ # -- Begin function _Z24__device_stub__addKernelPiS_S_
.p2align 4, 0x90
.type _Z24__device_stub__addKernelPiS_S_,@function
_Z24__device_stub__addKernelPiS_S_: # @_Z24__device_stub__addKernelPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addKernelPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__addKernelPiS_S_, .Lfunc_end0-_Z24__device_stub__addKernelPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $40, %edi
callq _Znam
movq %rax, %rbx
movl $40, %edi
callq _Znam
movq %rax, %r14
movl $40, %edi
callq _Znam
movq %rax, %r15
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
cmpl $2, %eax
je .LBB1_1
# %bb.3:
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
cmpl $2, %eax
je .LBB1_1
# %bb.4:
movq %rsp, %rdi
movl $40, %esi
callq hipMalloc
cmpl $2, %eax
je .LBB1_1
# %bb.5: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_6: # %.preheader
# =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rax,4)
movl %eax, (%r14,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB1_6
# %bb.7:
movq 16(%rsp), %rdi
movl $40, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_8
# %bb.11:
movl $.Lstr, %edi
callq puts@PLT
movq 8(%rsp), %rdi
movl $40, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_12
.LBB1_13:
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 9(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_15
# %bb.14:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9addKernelPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_15:
movq (%rsp), %rsi
movl $40, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_16: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r12,4), %esi
movl (%r14,%r12,4), %edx
movl (%r15,%r12,4), %ecx
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $10, %r12
jne .LBB1_16
# %bb.17:
movl $10, %edi
callq putchar@PLT
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
jmp .LBB1_20
.LBB1_1:
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $24, %esi
jmp .LBB1_2
.LBB1_8:
cmpl $1, %eax
je .LBB1_21
# %bb.9:
cmpl $17, %eax
jne .LBB1_18
# %bb.10:
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $16, %esi
jmp .LBB1_2
.LBB1_21:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $14, %esi
.LBB1_2:
movl $1, %edx
callq fwrite@PLT
.LBB1_19:
movl $-1, %eax
.LBB1_20:
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_18:
.cfi_def_cfa_offset 160
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
movl $18, %esi
movl $1, %edx
movl %eax, %ebx
callq fwrite@PLT
movl $.L.str.5, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
jmp .LBB1_19
.LBB1_12:
movq stderr(%rip), %rcx
movl $.L.str.6, %edi
movl $30, %esi
movl $1, %edx
callq fwrite@PLT
jmp .LBB1_13
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addKernelPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addKernelPiS_S_,@object # @_Z9addKernelPiS_S_
.section .rodata,"a",@progbits
.globl _Z9addKernelPiS_S_
.p2align 3, 0x0
_Z9addKernelPiS_S_:
.quad _Z24__device_stub__addKernelPiS_S_
.size _Z9addKernelPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error allocating memory\n"
.size .L.str, 25
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Invalid value\n"
.size .L.str.2, 15
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Invalid pointer\n"
.size .L.str.3, 17
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Invalid direction\n"
.size .L.str.4, 19
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Error type %x\n"
.size .L.str.5, 15
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Something goes wrong in dev_b\n"
.size .L.str.6, 31
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%d + %d = %d\n"
.size .L.str.7, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9addKernelPiS_S_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Allocated memory ok!"
.size .Lstr, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addKernelPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addKernelPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9addKernelPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0x9, PT ; /* 0x000000090600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addKernelPiS_S_
.globl _Z9addKernelPiS_S_
.p2align 8
.type _Z9addKernelPiS_S_,@function
_Z9addKernelPiS_S_:
s_cmp_gt_i32 s15, 9
s_cbranch_scc1 .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addKernelPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addKernelPiS_S_, .Lfunc_end0-_Z9addKernelPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addKernelPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z9addKernelPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00110bfb_00000000-6_sum_vectors.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3926:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3926:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9addKernelPiS_S_PiS_S_
.type _Z32__device_stub__Z9addKernelPiS_S_PiS_S_, @function
_Z32__device_stub__Z9addKernelPiS_S_PiS_S_:
.LFB3948:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addKernelPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3948:
.size _Z32__device_stub__Z9addKernelPiS_S_PiS_S_, .-_Z32__device_stub__Z9addKernelPiS_S_PiS_S_
.globl _Z9addKernelPiS_S_
.type _Z9addKernelPiS_S_, @function
_Z9addKernelPiS_S_:
.LFB3949:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9addKernelPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3949:
.size _Z9addKernelPiS_S_, .-_Z9addKernelPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Error allocating memory\n"
.LC1:
.string "Allocated memory ok!\n"
.LC2:
.string "Invalid value\n"
.LC3:
.string "Invalid pointer\n"
.LC4:
.string "Invalid direction\n"
.LC5:
.string "Error type %x\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "Something goes wrong in dev_b\n"
.section .rodata.str1.1
.LC7:
.string "%d + %d = %d\n"
.LC8:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3923:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $40, %edi
call _Znam@PLT
movq %rax, %rbp
movl $40, %edi
call _Znam@PLT
movq %rax, %r12
movl $40, %edi
call _Znam@PLT
movq %rax, %r14
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
cmpl $2, %eax
je .L28
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
cmpl $2, %eax
je .L29
leaq 24(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
cmpl $2, %eax
je .L30
movl $0, %eax
.L15:
movl %eax, 0(%rbp,%rax,4)
movl %eax, (%r12,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L15
movl $1, %ecx
movl $40, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r13d
testl %eax, %eax
je .L31
cmpl $1, %eax
je .L32
cmpl $17, %eax
je .L33
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r13d, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %r13d
.L11:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl %r13d, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %r13d
jmp .L11
.L29:
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %r13d
jmp .L11
.L30:
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %r13d
jmp .L11
.L31:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $40, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L35
.L18:
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $10, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L21:
movl $2, %ecx
movl $40, %edx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC7(%rip), %r15
.L22:
movl (%r12,%rbx), %ecx
movl 0(%rbp,%rbx), %edx
movl (%r14,%rbx), %r8d
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $40, %rbx
jne .L22
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
jmp .L11
.L32:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %r13d
jmp .L11
.L33:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %r13d
jmp .L11
.L35:
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L18
.L36:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z9addKernelPiS_S_PiS_S_
jmp .L21
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3923:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z9addKernelPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3951:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addKernelPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3951:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sum_vectors.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__addKernelPiS_S_ # -- Begin function _Z24__device_stub__addKernelPiS_S_
.p2align 4, 0x90
.type _Z24__device_stub__addKernelPiS_S_,@function
_Z24__device_stub__addKernelPiS_S_: # @_Z24__device_stub__addKernelPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addKernelPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__addKernelPiS_S_, .Lfunc_end0-_Z24__device_stub__addKernelPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $40, %edi
callq _Znam
movq %rax, %rbx
movl $40, %edi
callq _Znam
movq %rax, %r14
movl $40, %edi
callq _Znam
movq %rax, %r15
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
cmpl $2, %eax
je .LBB1_1
# %bb.3:
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
cmpl $2, %eax
je .LBB1_1
# %bb.4:
movq %rsp, %rdi
movl $40, %esi
callq hipMalloc
cmpl $2, %eax
je .LBB1_1
# %bb.5: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_6: # %.preheader
# =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rax,4)
movl %eax, (%r14,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB1_6
# %bb.7:
movq 16(%rsp), %rdi
movl $40, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_8
# %bb.11:
movl $.Lstr, %edi
callq puts@PLT
movq 8(%rsp), %rdi
movl $40, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_12
.LBB1_13:
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 9(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_15
# %bb.14:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9addKernelPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_15:
movq (%rsp), %rsi
movl $40, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_16: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r12,4), %esi
movl (%r14,%r12,4), %edx
movl (%r15,%r12,4), %ecx
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $10, %r12
jne .LBB1_16
# %bb.17:
movl $10, %edi
callq putchar@PLT
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
jmp .LBB1_20
.LBB1_1:
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $24, %esi
jmp .LBB1_2
.LBB1_8:
cmpl $1, %eax
je .LBB1_21
# %bb.9:
cmpl $17, %eax
jne .LBB1_18
# %bb.10:
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $16, %esi
jmp .LBB1_2
.LBB1_21:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $14, %esi
.LBB1_2:
movl $1, %edx
callq fwrite@PLT
.LBB1_19:
movl $-1, %eax
.LBB1_20:
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_18:
.cfi_def_cfa_offset 160
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
movl $18, %esi
movl $1, %edx
movl %eax, %ebx
callq fwrite@PLT
movl $.L.str.5, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
jmp .LBB1_19
.LBB1_12:
movq stderr(%rip), %rcx
movl $.L.str.6, %edi
movl $30, %esi
movl $1, %edx
callq fwrite@PLT
jmp .LBB1_13
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addKernelPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addKernelPiS_S_,@object # @_Z9addKernelPiS_S_
.section .rodata,"a",@progbits
.globl _Z9addKernelPiS_S_
.p2align 3, 0x0
_Z9addKernelPiS_S_:
.quad _Z24__device_stub__addKernelPiS_S_
.size _Z9addKernelPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error allocating memory\n"
.size .L.str, 25
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Invalid value\n"
.size .L.str.2, 15
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Invalid pointer\n"
.size .L.str.3, 17
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Invalid direction\n"
.size .L.str.4, 19
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Error type %x\n"
.size .L.str.5, 15
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Something goes wrong in dev_b\n"
.size .L.str.6, 31
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%d + %d = %d\n"
.size .L.str.7, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9addKernelPiS_S_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Allocated memory ok!"
.size .Lstr, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addKernelPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addKernelPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // compile -> nvcc quiz3.cu -o quiz3
// execute -> quiz3.exe | quiz3.out
// Bruno Maglioni A01700879
#include <stdio.h>
#define N 9 //size of original matrix
#define K N/3 //size of compressed matrrix
#define ThreadsPerBlock N/K
#define NumBlocks N/K
__global__ void compress(float *mat, int n, float *comp, int k){
int x = threadIdx.x + blockIdx.x * blockDim.x; // columns
int y = threadIdx.y + blockIdx.y * blockDim.y; // rows
int offset = x + y * blockDim.x * gridDim.x; // where the thread is on the grid
if(x < K && y < K){
for(int i = 0; i < y; i++){
for(int j = 0; j < x; j++){
comp[j + (i * k)] += mat[offset + (j + (i * n))]/n;
}
}
offset += blockDim.x * gridDim.x;
}
}
void print_mat(float *mat, int n){
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
printf("%.1f\t", mat[i*n+j]);
}
printf("\n");
}
printf("\n");
}
void fill_mat(float *mat, int n){
int c = 0;
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
mat[i*n+j] = c++;
}
}
}
int main(){
float *h_compress, *h_matrix; // CPU variables
float *d_compress, *d_matrix; // GPU variables
// Allocate memory on CPU
h_compress = (float *)malloc(sizeof(float) * K * K);
h_matrix = (float *)malloc(sizeof(float) * N * N);
// Allocate memory on GPU
cudaMalloc((void**)&d_compress, sizeof(float) * K * K);
cudaMalloc((void**)&d_matrix, sizeof(float) * N * N);
// Fill matrix
fill_mat(h_matrix, N);
printf("\n input mat \n");
print_mat(h_matrix, N);
// Copy CPU variables to GPU
cudaMemcpy(d_compress, h_compress, sizeof(float)* K * K, cudaMemcpyHostToDevice);
cudaMemcpy(d_matrix, h_matrix, sizeof(float)* N * N, cudaMemcpyHostToDevice);
// Create grids
dim3 blocks(NumBlocks, NumBlocks);
dim3 threads(ThreadsPerBlock, ThreadsPerBlock);
// Call function in GPU
compress<<<blocks, threads>>>(d_matrix, N, d_compress, K);
// Copy result matrix from GPU to CPU
cudaMemcpy(h_compress, d_compress, sizeof(float) * K * K, cudaMemcpyDeviceToHost);
// Print compressed matrix
printf("\n compress mat \n");
print_mat(h_compress, N);
// Free CPU memory
free(h_compress);
free(h_matrix);
// Free GPU memory
cudaFree(d_compress);
cudaFree(d_matrix);
return 0;
} | code for sm_80
Function : _Z8compressPfiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R12, SR_CTAID.Y ; /* 0x00000000000c7919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002200 */
/*0050*/ IMAD R11, R3, c[0x0][0x0], R0 ; /* 0x00000000030b7a24 */
/* 0x002fc400078e0200 */
/*0060*/ IMAD R12, R12, c[0x0][0x4], R5 ; /* 0x000001000c0c7a24 */
/* 0x001fc600078e0205 */
/*0070*/ ISETP.GT.AND P0, PT, R11, 0x2, PT ; /* 0x000000020b00780c */
/* 0x000fe40003f04270 */
/*0080*/ IADD3 R2, R12, -0x1, RZ ; /* 0xffffffff0c027810 */
/* 0x000fc80007ffe0ff */
/*0090*/ ISETP.GT.U32.OR P0, PT, R2, 0x1, P0 ; /* 0x000000010200780c */
/* 0x000fda0000704470 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ I2F R10, c[0x0][0x168] ; /* 0x00005a00000a7b06 */
/* 0x000e220000201400 */
/*00c0*/ ULDC UR4, c[0x0][0xc] ; /* 0x0000030000047ab9 */
/* 0x000fe20000000800 */
/*00d0*/ IMAD R8, R12, c[0x0][0xc], R3 ; /* 0x000003000c087a24 */
/* 0x000fe200078e0203 */
/*00e0*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe20000000800 */
/*00f0*/ LOP3.LUT R9, R11.reuse, 0x3, RZ, 0xc0, !PT ; /* 0x000000030b097812 */
/* 0x040fe200078ec0ff */
/*0100*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe2000f8e023f */
/*0110*/ IMAD R8, R8, c[0x0][0x0], R0 ; /* 0x0000000008087a24 */
/* 0x000fe200078e0200 */
/*0120*/ IADD3 R6, R11.reuse, -0x1, RZ ; /* 0xffffffff0b067810 */
/* 0x040fe20007ffe0ff */
/*0130*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0140*/ IADD3 R5, R11, -R9, RZ ; /* 0x800000090b057210 */
/* 0x000fe40007ffe0ff */
/*0150*/ IMAD R4, R12, UR4, R11 ; /* 0x000000040c047c24 */
/* 0x000fe2000f8e020b */
/*0160*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc40000000a00 */
/*0170*/ ISETP.GE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fe20003f06270 */
/*0180*/ BSSY B0, 0xae0 ; /* 0x0000095000007945 */
/* 0x000fd80003800000 */
/*0190*/ @!P0 BRA 0xad0 ; /* 0x0000093000008947 */
/* 0x001fea0003800000 */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe20003f06070 */
/*01b0*/ BSSY B1, 0x700 ; /* 0x0000054000017945 */
/* 0x000fe20003800000 */
/*01c0*/ IMAD R3, R7, c[0x0][0x178], RZ ; /* 0x00005e0007037a24 */
/* 0x000fe400078e02ff */
/*01d0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fd200078e00ff */
/*01e0*/ @!P0 BRA 0x6f0 ; /* 0x0000050000008947 */
/* 0x000fea0003800000 */
/*01f0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fe200078e00ff */
/*0200*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fe200000001ff */
/*0210*/ IMAD R14, R7, c[0x0][0x168], R8 ; /* 0x00005a00070e7a24 */
/* 0x000fe200078e0208 */
/*0220*/ MOV R25, R5 ; /* 0x0000000500197202 */
/* 0x000fe20000000f00 */
/*0230*/ IMAD.MOV.U32 R26, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff1a7624 */
/* 0x000fe400078e00ff */
/*0240*/ IMAD.WIDE R14, R14, R15, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fc800078e020f */
/*0250*/ IMAD.MOV.U32 R27, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff1b7624 */
/* 0x000fe400078e00ff */
/*0260*/ LDG.E R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x000ea2000c1e1900 */
/*0270*/ MUFU.RCP R13, R10 ; /* 0x0000000a000d7308 */
/* 0x001e220000001000 */
/*0280*/ BSSY B2, 0x330 ; /* 0x000000a000027945 */
/* 0x000fe20003800000 */
/*0290*/ FFMA R0, -R10, R13, 1 ; /* 0x3f8000000a007423 */
/* 0x001fc8000000010d */
/*02a0*/ FFMA R0, R13, R0, R13 ; /* 0x000000000d007223 */
/* 0x000fe4000000000d */
/*02b0*/ FCHK P0, R22, R10 ; /* 0x0000000a16007302 */
/* 0x004e240000000000 */
/*02c0*/ FFMA R13, R22, R0, RZ ; /* 0x00000000160d7223 */
/* 0x000fc800000000ff */
/*02d0*/ FFMA R16, -R10, R13, R22 ; /* 0x0000000d0a107223 */
/* 0x000fc80000000116 */
/*02e0*/ FFMA R0, R0, R16, R13 ; /* 0x0000001000007223 */
/* 0x000fe2000000000d */
/*02f0*/ @!P0 BRA 0x320 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*0300*/ MOV R18, 0x320 ; /* 0x0000032000127802 */
/* 0x000fe40000000f00 */
/*0310*/ CALL.REL.NOINC 0xb20 ; /* 0x0000080000007944 */
/* 0x000fea0003c00000 */
/*0320*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0330*/ IMAD.WIDE R16, R3, 0x4, R26 ; /* 0x0000000403107825 */
/* 0x000fca00078e021a */
/*0340*/ LDG.E R13, [R16.64] ; /* 0x00000004100d7981 */
/* 0x000ea2000c1e1900 */
/*0350*/ MUFU.RCP R19, R10 ; /* 0x0000000a00137308 */
/* 0x000e220000001000 */
/*0360*/ FADD R13, R13, R0 ; /* 0x000000000d0d7221 */
/* 0x004fca0000000000 */
/*0370*/ STG.E [R16.64], R13 ; /* 0x0000000d10007986 */
/* 0x0003e8000c101904 */
/*0380*/ LDG.E R22, [R14.64+0x4] ; /* 0x000004040e167981 */
/* 0x000ea2000c1e1900 */
/*0390*/ FFMA R0, -R10, R19, 1 ; /* 0x3f8000000a007423 */
/* 0x001fe20000000113 */
/*03a0*/ BSSY B2, 0x440 ; /* 0x0000009000027945 */
/* 0x000fe60003800000 */
/*03b0*/ FFMA R21, R19, R0, R19 ; /* 0x0000000013157223 */
/* 0x000fe20000000013 */
/*03c0*/ FCHK P0, R22, R10 ; /* 0x0000000a16007302 */
/* 0x004e260000000000 */
/*03d0*/ FFMA R19, R21, R22, RZ ; /* 0x0000001615137223 */
/* 0x000fc800000000ff */
/*03e0*/ FFMA R0, -R10, R19, R22 ; /* 0x000000130a007223 */
/* 0x000fc80000000116 */
/*03f0*/ FFMA R0, R21, R0, R19 ; /* 0x0000000015007223 */
/* 0x000fe20000000013 */
/*0400*/ @!P0 BRA 0x430 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*0410*/ MOV R18, 0x430 ; /* 0x0000043000127802 */
/* 0x002fe40000000f00 */
/*0420*/ CALL.REL.NOINC 0xb20 ; /* 0x000006f000007944 */
/* 0x000fea0003c00000 */
/*0430*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x002fea0003800000 */
/*0440*/ LDG.E R13, [R16.64+0x4] ; /* 0x00000404100d7981 */
/* 0x000ea2000c1e1900 */
/*0450*/ MUFU.RCP R19, R10 ; /* 0x0000000a00137308 */
/* 0x000e220000001000 */
/*0460*/ FADD R13, R13, R0 ; /* 0x000000000d0d7221 */
/* 0x004fca0000000000 */
/*0470*/ STG.E [R16.64+0x4], R13 ; /* 0x0000040d10007986 */
/* 0x0003e8000c101904 */
/*0480*/ LDG.E R22, [R14.64+0x8] ; /* 0x000008040e167981 */
/* 0x000ea2000c1e1900 */
/*0490*/ FFMA R0, -R10, R19, 1 ; /* 0x3f8000000a007423 */
/* 0x001fe20000000113 */
/*04a0*/ BSSY B2, 0x540 ; /* 0x0000009000027945 */
/* 0x000fe60003800000 */
/*04b0*/ FFMA R21, R19, R0, R19 ; /* 0x0000000013157223 */
/* 0x000fe20000000013 */
/*04c0*/ FCHK P0, R22, R10 ; /* 0x0000000a16007302 */
/* 0x004e260000000000 */
/*04d0*/ FFMA R19, R21, R22, RZ ; /* 0x0000001615137223 */
/* 0x000fc800000000ff */
/*04e0*/ FFMA R0, -R10, R19, R22 ; /* 0x000000130a007223 */
/* 0x000fc80000000116 */
/*04f0*/ FFMA R0, R21, R0, R19 ; /* 0x0000000015007223 */
/* 0x000fe20000000013 */
/*0500*/ @!P0 BRA 0x530 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*0510*/ MOV R18, 0x530 ; /* 0x0000053000127802 */
/* 0x002fe40000000f00 */
/*0520*/ CALL.REL.NOINC 0xb20 ; /* 0x000005f000007944 */
/* 0x000fea0003c00000 */
/*0530*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x002fea0003800000 */
/*0540*/ LDG.E R13, [R16.64+0x8] ; /* 0x00000804100d7981 */
/* 0x000ea2000c1e1900 */
/*0550*/ MUFU.RCP R19, R10 ; /* 0x0000000a00137308 */
/* 0x000e220000001000 */
/*0560*/ FADD R13, R13, R0 ; /* 0x000000000d0d7221 */
/* 0x004fca0000000000 */
/*0570*/ STG.E [R16.64+0x8], R13 ; /* 0x0000080d10007986 */
/* 0x0003e8000c101904 */
/*0580*/ LDG.E R22, [R14.64+0xc] ; /* 0x00000c040e167981 */
/* 0x000ea2000c1e1900 */
/*0590*/ FFMA R0, -R10, R19, 1 ; /* 0x3f8000000a007423 */
/* 0x001fe20000000113 */
/*05a0*/ BSSY B2, 0x640 ; /* 0x0000009000027945 */
/* 0x000fe60003800000 */
/*05b0*/ FFMA R21, R19, R0, R19 ; /* 0x0000000013157223 */
/* 0x000fe20000000013 */
/*05c0*/ FCHK P0, R22, R10 ; /* 0x0000000a16007302 */
/* 0x004e260000000000 */
/*05d0*/ FFMA R19, R21, R22, RZ ; /* 0x0000001615137223 */
/* 0x000fc800000000ff */
/*05e0*/ FFMA R0, -R10, R19, R22 ; /* 0x000000130a007223 */
/* 0x000fc80000000116 */
/*05f0*/ FFMA R0, R21, R0, R19 ; /* 0x0000000015007223 */
/* 0x000fe20000000013 */
/*0600*/ @!P0 BRA 0x630 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*0610*/ MOV R18, 0x630 ; /* 0x0000063000127802 */
/* 0x002fe40000000f00 */
/*0620*/ CALL.REL.NOINC 0xb20 ; /* 0x000004f000007944 */
/* 0x000fea0003c00000 */
/*0630*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x002fea0003800000 */
/*0640*/ LDG.E R13, [R16.64+0xc] ; /* 0x00000c04100d7981 */
/* 0x000ea2000c1e1900 */
/*0650*/ IADD3 R25, R25, -0x4, RZ ; /* 0xfffffffc19197810 */
/* 0x000fe40007ffe0ff */
/*0660*/ IADD3 R26, P1, R26, 0x10, RZ ; /* 0x000000101a1a7810 */
/* 0x000fe40007f3e0ff */
/*0670*/ ISETP.NE.AND P0, PT, R25, RZ, PT ; /* 0x000000ff1900720c */
/* 0x000fe40003f05270 */
/*0680*/ IADD3 R14, P2, R14, 0x10, RZ ; /* 0x000000100e0e7810 */
/* 0x000fe20007f5e0ff */
/*0690*/ IMAD.X R27, RZ, RZ, R27, P1 ; /* 0x000000ffff1b7224 */
/* 0x000fe200008e061b */
/*06a0*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fc60007ffe0ff */
/*06b0*/ IMAD.X R15, RZ, RZ, R15, P2 ; /* 0x000000ffff0f7224 */
/* 0x000fe400010e060f */
/*06c0*/ FADD R13, R13, R0 ; /* 0x000000000d0d7221 */
/* 0x004fca0000000000 */
/*06d0*/ STG.E [R16.64+0xc], R13 ; /* 0x00000c0d10007986 */
/* 0x0001e2000c101904 */
/*06e0*/ @P0 BRA 0x260 ; /* 0xfffffb7000000947 */
/* 0x000fea000383ffff */
/*06f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0700*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fda0003f05270 */
/*0710*/ @!P0 BRA 0xad0 ; /* 0x000003b000008947 */
/* 0x000fea0003800000 */
/*0720*/ HFMA2.MMA R14, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0e7435 */
/* 0x000fe200000001ff */
/*0730*/ IMAD R13, R7, c[0x0][0x168], R4 ; /* 0x00005a00070d7a24 */
/* 0x001fc800078e0204 */
/*0740*/ IMAD.IADD R13, R13, 0x1, R2 ; /* 0x000000010d0d7824 */
/* 0x000fca00078e0202 */
/*0750*/ IMAD.WIDE R14, R13, R14, c[0x0][0x160] ; /* 0x000058000d0e7625 */
/* 0x000fca00078e020e */
/*0760*/ LDG.E R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x000ea2000c1e1900 */
/*0770*/ MUFU.RCP R13, R10 ; /* 0x0000000a000d7308 */
/* 0x000e220000001000 */
/*0780*/ BSSY B1, 0x840 ; /* 0x000000b000017945 */
/* 0x000fe20003800000 */
/*0790*/ ISETP.NE.AND P2, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fe20003f45270 */
/*07a0*/ FFMA R0, -R10, R13, 1 ; /* 0x3f8000000a007423 */
/* 0x001fc8000000010d */
/*07b0*/ FFMA R17, R13, R0, R13 ; /* 0x000000000d117223 */
/* 0x000fe2000000000d */
/*07c0*/ FCHK P0, R22, R10 ; /* 0x0000000a16007302 */
/* 0x004e260000000000 */
/*07d0*/ FFMA R13, R17, R22, RZ ; /* 0x00000016110d7223 */
/* 0x000fc800000000ff */
/*07e0*/ FFMA R0, -R10, R13, R22 ; /* 0x0000000d0a007223 */
/* 0x000fc80000000116 */
/*07f0*/ FFMA R0, R17, R0, R13 ; /* 0x0000000011007223 */
/* 0x000fe2000000000d */
/*0800*/ @!P0 BRA 0x830 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*0810*/ MOV R18, 0x830 ; /* 0x0000083000127802 */
/* 0x000fe40000000f00 */
/*0820*/ CALL.REL.NOINC 0xb20 ; /* 0x000002f000007944 */
/* 0x000fea0003c00000 */
/*0830*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0840*/ IMAD.IADD R2, R3, 0x1, R2 ; /* 0x0000000103027824 */
/* 0x000fe200078e0202 */
/*0850*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0860*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0870*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000ea4000c1e1900 */
/*0880*/ FADD R13, R13, R0 ; /* 0x000000000d0d7221 */
/* 0x004fca0000000000 */
/*0890*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e2000c101904 */
/*08a0*/ @!P2 BRA 0xad0 ; /* 0x000002200000a947 */
/* 0x000fea0003800000 */
/*08b0*/ LDG.E R22, [R14.64+0x4] ; /* 0x000004040e167981 */
/* 0x000ea2000c1e1900 */
/*08c0*/ MUFU.RCP R13, R10 ; /* 0x0000000a000d7308 */
/* 0x001e220000001000 */
/*08d0*/ BSSY B1, 0x990 ; /* 0x000000b000017945 */
/* 0x000fe20003800000 */
/*08e0*/ ISETP.NE.AND P2, PT, R9, 0x2, PT ; /* 0x000000020900780c */
/* 0x000fe20003f45270 */
/*08f0*/ FFMA R0, -R10, R13, 1 ; /* 0x3f8000000a007423 */
/* 0x001fc8000000010d */
/*0900*/ FFMA R17, R13, R0, R13 ; /* 0x000000000d117223 */
/* 0x000fe2000000000d */
/*0910*/ FCHK P0, R22, R10 ; /* 0x0000000a16007302 */
/* 0x004e260000000000 */
/*0920*/ FFMA R13, R17, R22, RZ ; /* 0x00000016110d7223 */
/* 0x000fc800000000ff */
/*0930*/ FFMA R0, -R10, R13, R22 ; /* 0x0000000d0a007223 */
/* 0x000fc80000000116 */
/*0940*/ FFMA R0, R17, R0, R13 ; /* 0x0000000011007223 */
/* 0x000fe2000000000d */
/*0950*/ @!P0 BRA 0x980 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*0960*/ MOV R18, 0x980 ; /* 0x0000098000127802 */
/* 0x000fe40000000f00 */
/*0970*/ CALL.REL.NOINC 0xb20 ; /* 0x000001a000007944 */
/* 0x000fea0003c00000 */
/*0980*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0990*/ LDG.E R13, [R2.64+0x4] ; /* 0x00000404020d7981 */
/* 0x000ea4000c1e1900 */
/*09a0*/ FADD R13, R13, R0 ; /* 0x000000000d0d7221 */
/* 0x004fca0000000000 */
/*09b0*/ STG.E [R2.64+0x4], R13 ; /* 0x0000040d02007986 */
/* 0x0001e2000c101904 */
/*09c0*/ @!P2 BRA 0xad0 ; /* 0x000001000000a947 */
/* 0x000fea0003800000 */
/*09d0*/ LDG.E R22, [R14.64+0x8] ; /* 0x000008040e167981 */
/* 0x000ea2000c1e1900 */
/*09e0*/ MUFU.RCP R13, R10 ; /* 0x0000000a000d7308 */
/* 0x001e220000001000 */
/*09f0*/ BSSY B1, 0xaa0 ; /* 0x000000a000017945 */
/* 0x000fe20003800000 */
/*0a00*/ FFMA R0, -R10, R13, 1 ; /* 0x3f8000000a007423 */
/* 0x001fc8000000010d */
/*0a10*/ FFMA R17, R13, R0, R13 ; /* 0x000000000d117223 */
/* 0x000fe4000000000d */
/*0a20*/ FCHK P0, R22, R10 ; /* 0x0000000a16007302 */
/* 0x004e240000000000 */
/*0a30*/ FFMA R13, R17, R22, RZ ; /* 0x00000016110d7223 */
/* 0x000fc800000000ff */
/*0a40*/ FFMA R0, -R10, R13, R22 ; /* 0x0000000d0a007223 */
/* 0x000fc80000000116 */
/*0a50*/ FFMA R0, R17, R0, R13 ; /* 0x0000000011007223 */
/* 0x000fe2000000000d */
/*0a60*/ @!P0 BRA 0xa90 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*0a70*/ MOV R18, 0xa90 ; /* 0x00000a9000127802 */
/* 0x000fe40000000f00 */
/*0a80*/ CALL.REL.NOINC 0xb20 ; /* 0x0000009000007944 */
/* 0x000fea0003c00000 */
/*0a90*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0aa0*/ LDG.E R13, [R2.64+0x8] ; /* 0x00000804020d7981 */
/* 0x000ea4000c1e1900 */
/*0ab0*/ FADD R13, R13, R0 ; /* 0x000000000d0d7221 */
/* 0x004fca0000000000 */
/*0ac0*/ STG.E [R2.64+0x8], R13 ; /* 0x0000080d02007986 */
/* 0x0001e4000c101904 */
/*0ad0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0ae0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fc80007ffe0ff */
/*0af0*/ ISETP.GE.AND P0, PT, R7, R12, PT ; /* 0x0000000c0700720c */
/* 0x000fda0003f06270 */
/*0b00*/ @!P0 BRA 0x170 ; /* 0xfffff66000008947 */
/* 0x000fea000383ffff */
/*0b10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b20*/ SHF.R.U32.HI R0, RZ, 0x17, R10 ; /* 0x00000017ff007819 */
/* 0x000fe2000001160a */
/*0b30*/ BSSY B3, 0x1170 ; /* 0x0000063000037945 */
/* 0x000fe20003800000 */
/*0b40*/ SHF.R.U32.HI R21, RZ, 0x17, R22 ; /* 0x00000017ff157819 */
/* 0x000fe20000011616 */
/*0b50*/ IMAD.MOV.U32 R23, RZ, RZ, R10 ; /* 0x000000ffff177224 */
/* 0x000fe200078e000a */
/*0b60*/ LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff00007812 */
/* 0x000fe400078ec0ff */
/*0b70*/ LOP3.LUT R21, R21, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff15157812 */
/* 0x000fe400078ec0ff */
/*0b80*/ IADD3 R19, R0, -0x1, RZ ; /* 0xffffffff00137810 */
/* 0x000fe40007ffe0ff */
/*0b90*/ IADD3 R20, R21, -0x1, RZ ; /* 0xffffffff15147810 */
/* 0x000fc40007ffe0ff */
/*0ba0*/ ISETP.GT.U32.AND P0, PT, R19, 0xfd, PT ; /* 0x000000fd1300780c */
/* 0x000fc80003f04070 */
/*0bb0*/ ISETP.GT.U32.OR P0, PT, R20, 0xfd, P0 ; /* 0x000000fd1400780c */
/* 0x000fda0000704470 */
/*0bc0*/ @!P0 IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d8224 */
/* 0x000fe200078e00ff */
/*0bd0*/ @!P0 BRA 0xd50 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0be0*/ FSETP.GTU.FTZ.AND P0, PT, |R22|, +INF , PT ; /* 0x7f8000001600780b */
/* 0x000fe40003f1c200 */
/*0bf0*/ FSETP.GTU.FTZ.AND P1, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fc80003f3c200 */
/*0c00*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0c10*/ @P0 BRA 0x1150 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0c20*/ LOP3.LUT P0, RZ, R23, 0x7fffffff, R22, 0xc8, !PT ; /* 0x7fffffff17ff7812 */
/* 0x000fda000780c816 */
/*0c30*/ @!P0 BRA 0x1130 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0c40*/ FSETP.NEU.FTZ.AND P3, PT, |R22|, +INF , PT ; /* 0x7f8000001600780b */
/* 0x000fe40003f7d200 */
/*0c50*/ FSETP.NEU.FTZ.AND P1, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fe40003f3d200 */
/*0c60*/ FSETP.NEU.FTZ.AND P0, PT, |R22|, +INF , PT ; /* 0x7f8000001600780b */
/* 0x000fd60003f1d200 */
/*0c70*/ @!P1 BRA !P3, 0x1130 ; /* 0x000004b000009947 */
/* 0x000fea0005800000 */
/*0c80*/ LOP3.LUT P3, RZ, R22, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff16ff7812 */
/* 0x000fc8000786c0ff */
/*0c90*/ PLOP3.LUT P1, PT, P1, P3, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f26572 */
/*0ca0*/ @P1 BRA 0x1110 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0cb0*/ LOP3.LUT P1, RZ, R23, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff17ff7812 */
/* 0x000fc8000782c0ff */
/*0cc0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0cd0*/ @P0 BRA 0x10e0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0ce0*/ ISETP.GE.AND P0, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fe40003f06270 */
/*0cf0*/ ISETP.GE.AND P1, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fd60003f26270 */
/*0d00*/ @P0 MOV R13, RZ ; /* 0x000000ff000d0202 */
/* 0x000fe20000000f00 */
/*0d10*/ @!P0 IMAD.MOV.U32 R13, RZ, RZ, -0x40 ; /* 0xffffffc0ff0d8424 */
/* 0x000fe400078e00ff */
/*0d20*/ @!P0 FFMA R22, R22, 1.84467440737095516160e+19, RZ ; /* 0x5f80000016168823 */
/* 0x000fe400000000ff */
/*0d30*/ @!P1 FFMA R23, R10, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000a179823 */
/* 0x000fe200000000ff */
/*0d40*/ @!P1 IADD3 R13, R13, 0x40, RZ ; /* 0x000000400d0d9810 */
/* 0x000fe40007ffe0ff */
/*0d50*/ LEA R20, R0, 0xc0800000, 0x17 ; /* 0xc080000000147811 */
/* 0x000fe200078eb8ff */
/*0d60*/ BSSY B4, 0x10d0 ; /* 0x0000036000047945 */
/* 0x000fe20003800000 */
/*0d70*/ IADD3 R21, R21, -0x7f, RZ ; /* 0xffffff8115157810 */
/* 0x000fc60007ffe0ff */
/*0d80*/ IMAD.IADD R28, R23, 0x1, -R20 ; /* 0x00000001171c7824 */
/* 0x000fe400078e0a14 */
/*0d90*/ IMAD R23, R21.reuse, -0x800000, R22 ; /* 0xff80000015177824 */
/* 0x040fe400078e0216 */
/*0da0*/ MUFU.RCP R19, R28 ; /* 0x0000001c00137308 */
/* 0x0000620000001000 */
/*0db0*/ FADD.FTZ R20, -R28, -RZ ; /* 0x800000ff1c147221 */
/* 0x000fe20000010100 */
/*0dc0*/ IADD3 R28, R21, 0x7f, -R0 ; /* 0x0000007f151c7810 */
/* 0x001fc80007ffe800 */
/*0dd0*/ IADD3 R13, R28, R13, RZ ; /* 0x0000000d1c0d7210 */
/* 0x000fe20007ffe0ff */
/*0de0*/ FFMA R24, R19, R20, 1 ; /* 0x3f80000013187423 */
/* 0x002fc80000000014 */
/*0df0*/ FFMA R19, R19, R24, R19 ; /* 0x0000001813137223 */
/* 0x000fc80000000013 */
/*0e00*/ FFMA R22, R23, R19, RZ ; /* 0x0000001317167223 */
/* 0x000fc800000000ff */
/*0e10*/ FFMA R24, R20, R22, R23 ; /* 0x0000001614187223 */
/* 0x000fc80000000017 */
/*0e20*/ FFMA R24, R19, R24, R22 ; /* 0x0000001813187223 */
/* 0x000fc80000000016 */
/*0e30*/ FFMA R20, R20, R24, R23 ; /* 0x0000001814147223 */
/* 0x000fc80000000017 */
/*0e40*/ FFMA R22, R19, R20, R24 ; /* 0x0000001413167223 */
/* 0x000fca0000000018 */
/*0e50*/ SHF.R.U32.HI R0, RZ, 0x17, R22 ; /* 0x00000017ff007819 */
/* 0x000fc80000011616 */
/*0e60*/ LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff00007812 */
/* 0x000fca00078ec0ff */
/*0e70*/ IMAD.IADD R0, R0, 0x1, R13 ; /* 0x0000000100007824 */
/* 0x000fca00078e020d */
/*0e80*/ IADD3 R21, R0, -0x1, RZ ; /* 0xffffffff00157810 */
/* 0x000fc80007ffe0ff */
/*0e90*/ ISETP.GE.U32.AND P0, PT, R21, 0xfe, PT ; /* 0x000000fe1500780c */
/* 0x000fda0003f06070 */
/*0ea0*/ @!P0 BRA 0x10b0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0eb0*/ ISETP.GT.AND P0, PT, R0, 0xfe, PT ; /* 0x000000fe0000780c */
/* 0x000fda0003f04270 */
/*0ec0*/ @P0 BRA 0x1080 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0ed0*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0ee0*/ @P0 BRA 0x10c0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0ef0*/ ISETP.GE.AND P0, PT, R0, -0x18, PT ; /* 0xffffffe80000780c */
/* 0x000fe40003f06270 */
/*0f00*/ LOP3.LUT R22, R22, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000016167812 */
/* 0x000fd600078ec0ff */
/*0f10*/ @!P0 BRA 0x10c0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0f20*/ FFMA.RZ R13, R19.reuse, R20.reuse, R24.reuse ; /* 0x00000014130d7223 */
/* 0x1c0fe2000000c018 */
/*0f30*/ ISETP.NE.AND P3, PT, R0.reuse, RZ, PT ; /* 0x000000ff0000720c */
/* 0x040fe20003f65270 */
/*0f40*/ FFMA.RP R21, R19.reuse, R20.reuse, R24.reuse ; /* 0x0000001413157223 */
/* 0x1c0fe20000008018 */
/*0f50*/ ISETP.NE.AND P1, PT, R0.reuse, RZ, PT ; /* 0x000000ff0000720c */
/* 0x040fe20003f25270 */
/*0f60*/ FFMA.RM R20, R19, R20, R24 ; /* 0x0000001413147223 */
/* 0x000fe20000004018 */
/*0f70*/ LOP3.LUT R13, R13, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0d0d7812 */
/* 0x000fe400078ec0ff */
/*0f80*/ IADD3 R19, R0.reuse, 0x20, RZ ; /* 0x0000002000137810 */
/* 0x040fe40007ffe0ff */
/*0f90*/ LOP3.LUT R24, R13, 0x800000, RZ, 0xfc, !PT ; /* 0x008000000d187812 */
/* 0x000fe400078efcff */
/*0fa0*/ IADD3 R0, -R0, RZ, RZ ; /* 0x000000ff00007210 */
/* 0x000fc40007ffe1ff */
/*0fb0*/ SHF.L.U32 R19, R24, R19, RZ ; /* 0x0000001318137219 */
/* 0x000fe400000006ff */
/*0fc0*/ FSETP.NEU.FTZ.AND P0, PT, R21, R20, PT ; /* 0x000000141500720b */
/* 0x000fe40003f1d000 */
/*0fd0*/ SEL R13, R0, RZ, P3 ; /* 0x000000ff000d7207 */
/* 0x000fe40001800000 */
/*0fe0*/ ISETP.NE.AND P1, PT, R19, RZ, P1 ; /* 0x000000ff1300720c */
/* 0x000fe40000f25270 */
/*0ff0*/ SHF.R.U32.HI R13, RZ, R13, R24 ; /* 0x0000000dff0d7219 */
/* 0x000fe40000011618 */
/*1000*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*1010*/ SHF.R.U32.HI R19, RZ, 0x1, R13 ; /* 0x00000001ff137819 */
/* 0x000fe4000001160d */
/*1020*/ SEL R0, RZ, 0x1, !P0 ; /* 0x00000001ff007807 */
/* 0x000fc80004000000 */
/*1030*/ LOP3.LUT R0, R0, 0x1, R19, 0xf8, !PT ; /* 0x0000000100007812 */
/* 0x000fc800078ef813 */
/*1040*/ LOP3.LUT R0, R0, R13, RZ, 0xc0, !PT ; /* 0x0000000d00007212 */
/* 0x000fca00078ec0ff */
/*1050*/ IMAD.IADD R19, R19, 0x1, R0 ; /* 0x0000000113137824 */
/* 0x000fca00078e0200 */
/*1060*/ LOP3.LUT R22, R19, R22, RZ, 0xfc, !PT ; /* 0x0000001613167212 */
/* 0x000fe200078efcff */
/*1070*/ BRA 0x10c0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*1080*/ LOP3.LUT R22, R22, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000016167812 */
/* 0x000fc800078ec0ff */
/*1090*/ LOP3.LUT R22, R22, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000016167812 */
/* 0x000fe200078efcff */
/*10a0*/ BRA 0x10c0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*10b0*/ LEA R22, R13, R22, 0x17 ; /* 0x000000160d167211 */
/* 0x000fe400078eb8ff */
/*10c0*/ BSYNC B4 ; /* 0x0000000000047941 */
/* 0x000fea0003800000 */
/*10d0*/ BRA 0x1160 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*10e0*/ LOP3.LUT R22, R23, 0x80000000, R22, 0x48, !PT ; /* 0x8000000017167812 */
/* 0x000fc800078e4816 */
/*10f0*/ LOP3.LUT R22, R22, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000016167812 */
/* 0x000fe200078efcff */
/*1100*/ BRA 0x1160 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*1110*/ LOP3.LUT R22, R23, 0x80000000, R22, 0x48, !PT ; /* 0x8000000017167812 */
/* 0x000fe200078e4816 */
/*1120*/ BRA 0x1160 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*1130*/ MUFU.RSQ R22, -QNAN ; /* 0xffc0000000167908 */
/* 0x000e220000001400 */
/*1140*/ BRA 0x1160 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*1150*/ FADD.FTZ R22, R22, R10 ; /* 0x0000000a16167221 */
/* 0x000fe40000010000 */
/*1160*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*1170*/ HFMA2.MMA R19, -RZ, RZ, 0, 0 ; /* 0x00000000ff137435 */
/* 0x000fe200000001ff */
/*1180*/ IMAD.MOV.U32 R0, RZ, RZ, R22 ; /* 0x000000ffff007224 */
/* 0x001fca00078e0016 */
/*1190*/ RET.REL.NODEC R18 0x0 ; /* 0xffffee6012007950 */
/* 0x000fea0003c3ffff */
/*11a0*/ BRA 0x11a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*11b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // compile -> nvcc quiz3.cu -o quiz3
// execute -> quiz3.exe | quiz3.out
// Bruno Maglioni A01700879
#include <stdio.h>
#define N 9 //size of original matrix
#define K N/3 //size of compressed matrrix
#define ThreadsPerBlock N/K
#define NumBlocks N/K
__global__ void compress(float *mat, int n, float *comp, int k){
int x = threadIdx.x + blockIdx.x * blockDim.x; // columns
int y = threadIdx.y + blockIdx.y * blockDim.y; // rows
int offset = x + y * blockDim.x * gridDim.x; // where the thread is on the grid
if(x < K && y < K){
for(int i = 0; i < y; i++){
for(int j = 0; j < x; j++){
comp[j + (i * k)] += mat[offset + (j + (i * n))]/n;
}
}
offset += blockDim.x * gridDim.x;
}
}
void print_mat(float *mat, int n){
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
printf("%.1f\t", mat[i*n+j]);
}
printf("\n");
}
printf("\n");
}
void fill_mat(float *mat, int n){
int c = 0;
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
mat[i*n+j] = c++;
}
}
}
int main(){
float *h_compress, *h_matrix; // CPU variables
float *d_compress, *d_matrix; // GPU variables
// Allocate memory on CPU
h_compress = (float *)malloc(sizeof(float) * K * K);
h_matrix = (float *)malloc(sizeof(float) * N * N);
// Allocate memory on GPU
cudaMalloc((void**)&d_compress, sizeof(float) * K * K);
cudaMalloc((void**)&d_matrix, sizeof(float) * N * N);
// Fill matrix
fill_mat(h_matrix, N);
printf("\n input mat \n");
print_mat(h_matrix, N);
// Copy CPU variables to GPU
cudaMemcpy(d_compress, h_compress, sizeof(float)* K * K, cudaMemcpyHostToDevice);
cudaMemcpy(d_matrix, h_matrix, sizeof(float)* N * N, cudaMemcpyHostToDevice);
// Create grids
dim3 blocks(NumBlocks, NumBlocks);
dim3 threads(ThreadsPerBlock, ThreadsPerBlock);
// Call function in GPU
compress<<<blocks, threads>>>(d_matrix, N, d_compress, K);
// Copy result matrix from GPU to CPU
cudaMemcpy(h_compress, d_compress, sizeof(float) * K * K, cudaMemcpyDeviceToHost);
// Print compressed matrix
printf("\n compress mat \n");
print_mat(h_compress, N);
// Free CPU memory
free(h_compress);
free(h_matrix);
// Free GPU memory
cudaFree(d_compress);
cudaFree(d_matrix);
return 0;
} | .file "tmpxft_000834c8_00000000-6_quiz_3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%.1f\t"
.LC1:
.string "\n"
.text
.globl _Z9print_matPfi
.type _Z9print_matPfi, @function
_Z9print_matPfi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L4
movslq %esi, %r14
leaq 0(,%r14,4), %r15
leaq (%rdi,%r15), %rbp
negq %r14
salq $2, %r14
movl $0, %r13d
leaq .LC0(%rip), %r12
.L5:
leaq 0(%rbp,%r14), %rbx
.L6:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addq %r15, %rbp
cmpl %r13d, 12(%rsp)
jne .L5
.L4:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z9print_matPfi, .-_Z9print_matPfi
.globl _Z8fill_matPfi
.type _Z8fill_matPfi, @function
_Z8fill_matPfi:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L9
movslq %esi, %r11
salq $2, %r11
movl %esi, %r8d
movl $0, %r9d
movl $0, %eax
.L11:
movl %eax, %r10d
movq %rdi, %rdx
.L12:
movl %eax, %ecx
addl $1, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %ecx, %xmm0
movss %xmm0, (%rdx)
addq $4, %rdx
cmpl %r8d, %eax
jne .L12
leal (%rsi,%r10), %eax
addl $1, %r9d
addl %esi, %r8d
addq %r11, %rdi
cmpl %r9d, %esi
jne .L11
.L9:
ret
.cfi_endproc
.LFE2058:
.size _Z8fill_matPfi, .-_Z8fill_matPfi
.globl _Z31__device_stub__Z8compressPfiS_iPfiS_i
.type _Z31__device_stub__Z8compressPfiS_iPfiS_i, @function
_Z31__device_stub__Z8compressPfiS_iPfiS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8compressPfiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z31__device_stub__Z8compressPfiS_iPfiS_i, .-_Z31__device_stub__Z8compressPfiS_iPfiS_i
.globl _Z8compressPfiS_i
.type _Z8compressPfiS_i, @function
_Z8compressPfiS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8compressPfiS_iPfiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z8compressPfiS_i, .-_Z8compressPfiS_i
.section .rodata.str1.1
.LC2:
.string "\n input mat \n"
.LC3:
.string "\n compress mat \n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $36, %edi
call malloc@PLT
movq %rax, %rbp
movl $324, %edi
call malloc@PLT
movq %rax, %rbx
movq %rsp, %rdi
movl $36, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $324, %esi
call cudaMalloc@PLT
movl $9, %esi
movq %rbx, %rdi
call _Z8fill_matPfi
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $9, %esi
movq %rbx, %rdi
call _Z9print_matPfi
movl $1, %ecx
movl $36, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $324, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, 16(%rsp)
movl $0, 20(%rsp)
movl $0, 28(%rsp)
movl $0, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L23:
movl $2, %ecx
movl $36, %edx
movq (%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $9, %esi
movq %rbp, %rdi
call _Z9print_matPfi
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L27
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movl $3, %ecx
movq (%rsp), %rdx
movl $9, %esi
movq 8(%rsp), %rdi
call _Z31__device_stub__Z8compressPfiS_iPfiS_i
jmp .L23
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z8compressPfiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z8compressPfiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // compile -> nvcc quiz3.cu -o quiz3
// execute -> quiz3.exe | quiz3.out
// Bruno Maglioni A01700879
#include <stdio.h>
#define N 9 //size of original matrix
#define K N/3 //size of compressed matrrix
#define ThreadsPerBlock N/K
#define NumBlocks N/K
__global__ void compress(float *mat, int n, float *comp, int k){
int x = threadIdx.x + blockIdx.x * blockDim.x; // columns
int y = threadIdx.y + blockIdx.y * blockDim.y; // rows
int offset = x + y * blockDim.x * gridDim.x; // where the thread is on the grid
if(x < K && y < K){
for(int i = 0; i < y; i++){
for(int j = 0; j < x; j++){
comp[j + (i * k)] += mat[offset + (j + (i * n))]/n;
}
}
offset += blockDim.x * gridDim.x;
}
}
void print_mat(float *mat, int n){
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
printf("%.1f\t", mat[i*n+j]);
}
printf("\n");
}
printf("\n");
}
void fill_mat(float *mat, int n){
int c = 0;
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
mat[i*n+j] = c++;
}
}
}
int main(){
float *h_compress, *h_matrix; // CPU variables
float *d_compress, *d_matrix; // GPU variables
// Allocate memory on CPU
h_compress = (float *)malloc(sizeof(float) * K * K);
h_matrix = (float *)malloc(sizeof(float) * N * N);
// Allocate memory on GPU
cudaMalloc((void**)&d_compress, sizeof(float) * K * K);
cudaMalloc((void**)&d_matrix, sizeof(float) * N * N);
// Fill matrix
fill_mat(h_matrix, N);
printf("\n input mat \n");
print_mat(h_matrix, N);
// Copy CPU variables to GPU
cudaMemcpy(d_compress, h_compress, sizeof(float)* K * K, cudaMemcpyHostToDevice);
cudaMemcpy(d_matrix, h_matrix, sizeof(float)* N * N, cudaMemcpyHostToDevice);
// Create grids
dim3 blocks(NumBlocks, NumBlocks);
dim3 threads(ThreadsPerBlock, ThreadsPerBlock);
// Call function in GPU
compress<<<blocks, threads>>>(d_matrix, N, d_compress, K);
// Copy result matrix from GPU to CPU
cudaMemcpy(h_compress, d_compress, sizeof(float) * K * K, cudaMemcpyDeviceToHost);
// Print compressed matrix
printf("\n compress mat \n");
print_mat(h_compress, N);
// Free CPU memory
free(h_compress);
free(h_matrix);
// Free GPU memory
cudaFree(d_compress);
cudaFree(d_matrix);
return 0;
} | // compile -> nvcc quiz3.cu -o quiz3
// execute -> quiz3.exe | quiz3.out
// Bruno Maglioni A01700879
#include <hip/hip_runtime.h>
#include <stdio.h>
#define N 9 //size of original matrix
#define K N/3 //size of compressed matrrix
#define ThreadsPerBlock N/K
#define NumBlocks N/K
__global__ void compress(float *mat, int n, float *comp, int k){
int x = threadIdx.x + blockIdx.x * blockDim.x; // columns
int y = threadIdx.y + blockIdx.y * blockDim.y; // rows
int offset = x + y * blockDim.x * gridDim.x; // where the thread is on the grid
if(x < K && y < K){
for(int i = 0; i < y; i++){
for(int j = 0; j < x; j++){
comp[j + (i * k)] += mat[offset + (j + (i * n))]/n;
}
}
offset += blockDim.x * gridDim.x;
}
}
void print_mat(float *mat, int n){
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
printf("%.1f\t", mat[i*n+j]);
}
printf("\n");
}
printf("\n");
}
void fill_mat(float *mat, int n){
int c = 0;
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
mat[i*n+j] = c++;
}
}
}
int main(){
float *h_compress, *h_matrix; // CPU variables
float *d_compress, *d_matrix; // GPU variables
// Allocate memory on CPU
h_compress = (float *)malloc(sizeof(float) * K * K);
h_matrix = (float *)malloc(sizeof(float) * N * N);
// Allocate memory on GPU
hipMalloc((void**)&d_compress, sizeof(float) * K * K);
hipMalloc((void**)&d_matrix, sizeof(float) * N * N);
// Fill matrix
fill_mat(h_matrix, N);
printf("\n input mat \n");
print_mat(h_matrix, N);
// Copy CPU variables to GPU
hipMemcpy(d_compress, h_compress, sizeof(float)* K * K, hipMemcpyHostToDevice);
hipMemcpy(d_matrix, h_matrix, sizeof(float)* N * N, hipMemcpyHostToDevice);
// Create grids
dim3 blocks(NumBlocks, NumBlocks);
dim3 threads(ThreadsPerBlock, ThreadsPerBlock);
// Call function in GPU
compress<<<blocks, threads>>>(d_matrix, N, d_compress, K);
// Copy result matrix from GPU to CPU
hipMemcpy(h_compress, d_compress, sizeof(float) * K * K, hipMemcpyDeviceToHost);
// Print compressed matrix
printf("\n compress mat \n");
print_mat(h_compress, N);
// Free CPU memory
free(h_compress);
free(h_matrix);
// Free GPU memory
hipFree(d_compress);
hipFree(d_matrix);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // compile -> nvcc quiz3.cu -o quiz3
// execute -> quiz3.exe | quiz3.out
// Bruno Maglioni A01700879
#include <hip/hip_runtime.h>
#include <stdio.h>
#define N 9 //size of original matrix
#define K N/3 //size of compressed matrrix
#define ThreadsPerBlock N/K
#define NumBlocks N/K
__global__ void compress(float *mat, int n, float *comp, int k){
int x = threadIdx.x + blockIdx.x * blockDim.x; // columns
int y = threadIdx.y + blockIdx.y * blockDim.y; // rows
int offset = x + y * blockDim.x * gridDim.x; // where the thread is on the grid
if(x < K && y < K){
for(int i = 0; i < y; i++){
for(int j = 0; j < x; j++){
comp[j + (i * k)] += mat[offset + (j + (i * n))]/n;
}
}
offset += blockDim.x * gridDim.x;
}
}
void print_mat(float *mat, int n){
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
printf("%.1f\t", mat[i*n+j]);
}
printf("\n");
}
printf("\n");
}
void fill_mat(float *mat, int n){
int c = 0;
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
mat[i*n+j] = c++;
}
}
}
int main(){
float *h_compress, *h_matrix; // CPU variables
float *d_compress, *d_matrix; // GPU variables
// Allocate memory on CPU
h_compress = (float *)malloc(sizeof(float) * K * K);
h_matrix = (float *)malloc(sizeof(float) * N * N);
// Allocate memory on GPU
hipMalloc((void**)&d_compress, sizeof(float) * K * K);
hipMalloc((void**)&d_matrix, sizeof(float) * N * N);
// Fill matrix
fill_mat(h_matrix, N);
printf("\n input mat \n");
print_mat(h_matrix, N);
// Copy CPU variables to GPU
hipMemcpy(d_compress, h_compress, sizeof(float)* K * K, hipMemcpyHostToDevice);
hipMemcpy(d_matrix, h_matrix, sizeof(float)* N * N, hipMemcpyHostToDevice);
// Create grids
dim3 blocks(NumBlocks, NumBlocks);
dim3 threads(ThreadsPerBlock, ThreadsPerBlock);
// Call function in GPU
compress<<<blocks, threads>>>(d_matrix, N, d_compress, K);
// Copy result matrix from GPU to CPU
hipMemcpy(h_compress, d_compress, sizeof(float) * K * K, hipMemcpyDeviceToHost);
// Print compressed matrix
printf("\n compress mat \n");
print_mat(h_compress, N);
// Free CPU memory
free(h_compress);
free(h_matrix);
// Free GPU memory
hipFree(d_compress);
hipFree(d_matrix);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8compressPfiS_i
.globl _Z8compressPfiS_i
.p2align 8
.type _Z8compressPfiS_i,@function
_Z8compressPfiS_i:
s_load_b32 s2, s[0:1], 0x2c
v_and_b32_e32 v3, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s6, s2, 0xffff
v_mad_u64_u32 v[4:5], null, s15, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s6, v[3:4]
v_add_nc_u32_e32 v1, -1, v4
v_cmp_gt_u32_e64 s2, 2, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, 3, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_6
s_load_b32 s7, s[4:5], 0x0
s_clause 0x3
s_load_b32 s10, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b32 s1, s[0:1], 0x18
v_cmp_lt_i32_e64 s0, 0, v0
s_mov_b32 s11, 0
s_mov_b32 s12, 0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[5:6], null, s7, v4, s[14:15]
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, v5, s6, v[3:4]
v_cvt_f32_i32_e32 v5, s10
v_max_i32_e32 v4, 1, v4
s_mov_b32 s6, 0
s_branch .LBB0_3
.LBB0_2:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s13
s_add_i32 s12, s12, 1
v_add_nc_u32_e32 v1, s10, v1
v_cmp_eq_u32_e32 vcc_lo, s12, v4
s_add_i32 s6, s6, s1
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execz .LBB0_6
.LBB0_3:
s_and_saveexec_b32 s13, s0
s_cbranch_execz .LBB0_2
s_ashr_i32 s7, s6, 31
v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v7, v0
s_lshl_b64 s[8:9], s[6:7], 2
s_mov_b32 s7, 0
s_add_u32 s8, s4, s8
s_addc_u32 s9, s5, s9
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_5:
v_ashrrev_i32_e32 v3, 31, v2
v_add_nc_u32_e32 v7, -1, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[8:9], 2, v[2:3]
v_add_nc_u32_e32 v2, 1, v2
v_add_co_u32 v8, vcc_lo, s2, v8
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
global_load_b32 v3, v[8:9], off
global_load_b32 v8, v6, s[8:9]
s_waitcnt vmcnt(1)
v_div_scale_f32 v9, null, v5, v5, v3
v_div_scale_f32 v12, vcc_lo, v3, v5, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v10, v9
s_waitcnt_depctr 0xfff
v_fma_f32 v11, -v9, v10, 1.0
v_fmac_f32_e32 v10, v11, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v11, v12, v10
v_fma_f32 v13, -v9, v11, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v11, v13, v10
v_fma_f32 v9, -v9, v11, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v9, v9, v10, v11
v_cmp_eq_u32_e32 vcc_lo, 0, v7
v_div_fixup_f32 v3, v9, v5, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_add_f32_e32 v3, v8, v3
global_store_b32 v6, v3, s[8:9]
s_add_u32 s8, s8, 4
s_addc_u32 s9, s9, 0
s_or_b32 s7, vcc_lo, s7
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_5
s_branch .LBB0_2
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8compressPfiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8compressPfiS_i, .Lfunc_end0-_Z8compressPfiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8compressPfiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8compressPfiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // compile -> nvcc quiz3.cu -o quiz3
// execute -> quiz3.exe | quiz3.out
// Bruno Maglioni A01700879
#include <hip/hip_runtime.h>
#include <stdio.h>
#define N 9 //size of original matrix
#define K N/3 //size of compressed matrrix
#define ThreadsPerBlock N/K
#define NumBlocks N/K
__global__ void compress(float *mat, int n, float *comp, int k){
int x = threadIdx.x + blockIdx.x * blockDim.x; // columns
int y = threadIdx.y + blockIdx.y * blockDim.y; // rows
int offset = x + y * blockDim.x * gridDim.x; // where the thread is on the grid
if(x < K && y < K){
for(int i = 0; i < y; i++){
for(int j = 0; j < x; j++){
comp[j + (i * k)] += mat[offset + (j + (i * n))]/n;
}
}
offset += blockDim.x * gridDim.x;
}
}
void print_mat(float *mat, int n){
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
printf("%.1f\t", mat[i*n+j]);
}
printf("\n");
}
printf("\n");
}
void fill_mat(float *mat, int n){
int c = 0;
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
mat[i*n+j] = c++;
}
}
}
int main(){
float *h_compress, *h_matrix; // CPU variables
float *d_compress, *d_matrix; // GPU variables
// Allocate memory on CPU
h_compress = (float *)malloc(sizeof(float) * K * K);
h_matrix = (float *)malloc(sizeof(float) * N * N);
// Allocate memory on GPU
hipMalloc((void**)&d_compress, sizeof(float) * K * K);
hipMalloc((void**)&d_matrix, sizeof(float) * N * N);
// Fill matrix
fill_mat(h_matrix, N);
printf("\n input mat \n");
print_mat(h_matrix, N);
// Copy CPU variables to GPU
hipMemcpy(d_compress, h_compress, sizeof(float)* K * K, hipMemcpyHostToDevice);
hipMemcpy(d_matrix, h_matrix, sizeof(float)* N * N, hipMemcpyHostToDevice);
// Create grids
dim3 blocks(NumBlocks, NumBlocks);
dim3 threads(ThreadsPerBlock, ThreadsPerBlock);
// Call function in GPU
compress<<<blocks, threads>>>(d_matrix, N, d_compress, K);
// Copy result matrix from GPU to CPU
hipMemcpy(h_compress, d_compress, sizeof(float) * K * K, hipMemcpyDeviceToHost);
// Print compressed matrix
printf("\n compress mat \n");
print_mat(h_compress, N);
// Free CPU memory
free(h_compress);
free(h_matrix);
// Free GPU memory
hipFree(d_compress);
hipFree(d_matrix);
return 0;
} | .text
.file "quiz_3.hip"
.globl _Z23__device_stub__compressPfiS_i # -- Begin function _Z23__device_stub__compressPfiS_i
.p2align 4, 0x90
.type _Z23__device_stub__compressPfiS_i,@function
_Z23__device_stub__compressPfiS_i: # @_Z23__device_stub__compressPfiS_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8compressPfiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__compressPfiS_i, .Lfunc_end0-_Z23__device_stub__compressPfiS_i
.cfi_endproc
# -- End function
.globl _Z9print_matPfi # -- Begin function _Z9print_matPfi
.p2align 4, 0x90
.type _Z9print_matPfi,@function
_Z9print_matPfi: # @_Z9print_matPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, (%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB1_5
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebx
movl %esi, %r15d
xorl %r12d, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movl %r12d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbp,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %r15
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addl %ebx, %r12d
cmpq %r15, %r13
jne .LBB1_2
.LBB1_5: # %._crit_edge14
movl $10, %edi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end1:
.size _Z9print_matPfi, .Lfunc_end1-_Z9print_matPfi
.cfi_endproc
# -- End function
.globl _Z8fill_matPfi # -- Begin function _Z8fill_matPfi
.p2align 4, 0x90
.type _Z8fill_matPfi,@function
_Z8fill_matPfi: # @_Z8fill_matPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_5
# %bb.1: # %.preheader.lr.ph
movl %esi, %eax
xorl %ecx, %ecx
xorl %edx, %edx
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
movl %ecx, %r9d
leaq (%rdi,%r9,4), %r10
movl %r8d, %r8d
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
leal (%r8,%r9), %r11d
xorps %xmm0, %xmm0
cvtsi2ss %r11d, %xmm0
movss %xmm0, (%r10,%r9,4)
incq %r9
cmpq %r9, %rax
jne .LBB2_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %rdx
addl %esi, %ecx
addl %r9d, %r8d
cmpq %rax, %rdx
jne .LBB2_2
.LBB2_5: # %._crit_edge17
retq
.Lfunc_end2:
.size _Z8fill_matPfi, .Lfunc_end2-_Z8fill_matPfi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $36, %edi
callq malloc
movq %rax, %rbx
movl $324, %edi # imm = 0x144
callq malloc
movq %rax, %r14
leaq 8(%rsp), %rdi
movl $36, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $324, %esi # imm = 0x144
callq hipMalloc
xorl %eax, %eax
movq %r14, %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
movl %edx, %edx
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rdx,%rsi), %edi
xorps %xmm0, %xmm0
cvtsi2ss %edi, %xmm0
movss %xmm0, (%rcx,%rsi,4)
incq %rsi
cmpq $9, %rsi
jne .LBB3_2
# %bb.3: # %._crit_edge.i
# in Loop: Header=BB3_1 Depth=1
incq %rax
addq $36, %rcx
addl %esi, %edx
cmpq $9, %rax
jne .LBB3_1
# %bb.4: # %_Z8fill_matPfi.exit
movl $.Lstr, %edi
callq puts@PLT
xorl %r15d, %r15d
movq %r14, %r12
.p2align 4, 0x90
.LBB3_5: # %.preheader.i15
# =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_6: # Parent Loop BB3_5 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r13
cmpq $9, %r13
jne .LBB3_6
# %bb.7: # %._crit_edge.i19
# in Loop: Header=BB3_5 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq $36, %r12
cmpq $9, %r15
jne .LBB3_5
# %bb.8: # %_Z9print_matPfi.exit
movl $10, %edi
callq putchar@PLT
movq 8(%rsp), %rdi
movl $36, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $324, %edx # imm = 0x144
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
xorl %edi, %edi
movl $1, %esi
xorl %edx, %edx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_10
# %bb.9:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movl $9, 28(%rsp)
movq %rcx, 80(%rsp)
movl $3, 24(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 28(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8compressPfiS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_10:
movq 8(%rsp), %rsi
movl $36, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r15d, %r15d
movq %rbx, %r12
.p2align 4, 0x90
.LBB3_11: # %.preheader.i20
# =>This Loop Header: Depth=1
# Child Loop BB3_12 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_12: # Parent Loop BB3_11 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r13
cmpq $9, %r13
jne .LBB3_12
# %bb.13: # %._crit_edge.i25
# in Loop: Header=BB3_11 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq $36, %r12
cmpq $9, %r15
jne .LBB3_11
# %bb.14: # %_Z9print_matPfi.exit30
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8compressPfiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8compressPfiS_i,@object # @_Z8compressPfiS_i
.section .rodata,"a",@progbits
.globl _Z8compressPfiS_i
.p2align 3, 0x0
_Z8compressPfiS_i:
.quad _Z23__device_stub__compressPfiS_i
.size _Z8compressPfiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%.1f\t"
.size .L.str, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8compressPfiS_i"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n input mat "
.size .Lstr, 13
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n compress mat "
.size .Lstr.1, 16
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__compressPfiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8compressPfiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8compressPfiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R12, SR_CTAID.Y ; /* 0x00000000000c7919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002200 */
/*0050*/ IMAD R11, R3, c[0x0][0x0], R0 ; /* 0x00000000030b7a24 */
/* 0x002fc400078e0200 */
/*0060*/ IMAD R12, R12, c[0x0][0x4], R5 ; /* 0x000001000c0c7a24 */
/* 0x001fc600078e0205 */
/*0070*/ ISETP.GT.AND P0, PT, R11, 0x2, PT ; /* 0x000000020b00780c */
/* 0x000fe40003f04270 */
/*0080*/ IADD3 R2, R12, -0x1, RZ ; /* 0xffffffff0c027810 */
/* 0x000fc80007ffe0ff */
/*0090*/ ISETP.GT.U32.OR P0, PT, R2, 0x1, P0 ; /* 0x000000010200780c */
/* 0x000fda0000704470 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ I2F R10, c[0x0][0x168] ; /* 0x00005a00000a7b06 */
/* 0x000e220000201400 */
/*00c0*/ ULDC UR4, c[0x0][0xc] ; /* 0x0000030000047ab9 */
/* 0x000fe20000000800 */
/*00d0*/ IMAD R8, R12, c[0x0][0xc], R3 ; /* 0x000003000c087a24 */
/* 0x000fe200078e0203 */
/*00e0*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe20000000800 */
/*00f0*/ LOP3.LUT R9, R11.reuse, 0x3, RZ, 0xc0, !PT ; /* 0x000000030b097812 */
/* 0x040fe200078ec0ff */
/*0100*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe2000f8e023f */
/*0110*/ IMAD R8, R8, c[0x0][0x0], R0 ; /* 0x0000000008087a24 */
/* 0x000fe200078e0200 */
/*0120*/ IADD3 R6, R11.reuse, -0x1, RZ ; /* 0xffffffff0b067810 */
/* 0x040fe20007ffe0ff */
/*0130*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0140*/ IADD3 R5, R11, -R9, RZ ; /* 0x800000090b057210 */
/* 0x000fe40007ffe0ff */
/*0150*/ IMAD R4, R12, UR4, R11 ; /* 0x000000040c047c24 */
/* 0x000fe2000f8e020b */
/*0160*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc40000000a00 */
/*0170*/ ISETP.GE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fe20003f06270 */
/*0180*/ BSSY B0, 0xae0 ; /* 0x0000095000007945 */
/* 0x000fd80003800000 */
/*0190*/ @!P0 BRA 0xad0 ; /* 0x0000093000008947 */
/* 0x001fea0003800000 */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe20003f06070 */
/*01b0*/ BSSY B1, 0x700 ; /* 0x0000054000017945 */
/* 0x000fe20003800000 */
/*01c0*/ IMAD R3, R7, c[0x0][0x178], RZ ; /* 0x00005e0007037a24 */
/* 0x000fe400078e02ff */
/*01d0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fd200078e00ff */
/*01e0*/ @!P0 BRA 0x6f0 ; /* 0x0000050000008947 */
/* 0x000fea0003800000 */
/*01f0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fe200078e00ff */
/*0200*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fe200000001ff */
/*0210*/ IMAD R14, R7, c[0x0][0x168], R8 ; /* 0x00005a00070e7a24 */
/* 0x000fe200078e0208 */
/*0220*/ MOV R25, R5 ; /* 0x0000000500197202 */
/* 0x000fe20000000f00 */
/*0230*/ IMAD.MOV.U32 R26, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff1a7624 */
/* 0x000fe400078e00ff */
/*0240*/ IMAD.WIDE R14, R14, R15, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fc800078e020f */
/*0250*/ IMAD.MOV.U32 R27, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff1b7624 */
/* 0x000fe400078e00ff */
/*0260*/ LDG.E R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x000ea2000c1e1900 */
/*0270*/ MUFU.RCP R13, R10 ; /* 0x0000000a000d7308 */
/* 0x001e220000001000 */
/*0280*/ BSSY B2, 0x330 ; /* 0x000000a000027945 */
/* 0x000fe20003800000 */
/*0290*/ FFMA R0, -R10, R13, 1 ; /* 0x3f8000000a007423 */
/* 0x001fc8000000010d */
/*02a0*/ FFMA R0, R13, R0, R13 ; /* 0x000000000d007223 */
/* 0x000fe4000000000d */
/*02b0*/ FCHK P0, R22, R10 ; /* 0x0000000a16007302 */
/* 0x004e240000000000 */
/*02c0*/ FFMA R13, R22, R0, RZ ; /* 0x00000000160d7223 */
/* 0x000fc800000000ff */
/*02d0*/ FFMA R16, -R10, R13, R22 ; /* 0x0000000d0a107223 */
/* 0x000fc80000000116 */
/*02e0*/ FFMA R0, R0, R16, R13 ; /* 0x0000001000007223 */
/* 0x000fe2000000000d */
/*02f0*/ @!P0 BRA 0x320 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*0300*/ MOV R18, 0x320 ; /* 0x0000032000127802 */
/* 0x000fe40000000f00 */
/*0310*/ CALL.REL.NOINC 0xb20 ; /* 0x0000080000007944 */
/* 0x000fea0003c00000 */
/*0320*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0330*/ IMAD.WIDE R16, R3, 0x4, R26 ; /* 0x0000000403107825 */
/* 0x000fca00078e021a */
/*0340*/ LDG.E R13, [R16.64] ; /* 0x00000004100d7981 */
/* 0x000ea2000c1e1900 */
/*0350*/ MUFU.RCP R19, R10 ; /* 0x0000000a00137308 */
/* 0x000e220000001000 */
/*0360*/ FADD R13, R13, R0 ; /* 0x000000000d0d7221 */
/* 0x004fca0000000000 */
/*0370*/ STG.E [R16.64], R13 ; /* 0x0000000d10007986 */
/* 0x0003e8000c101904 */
/*0380*/ LDG.E R22, [R14.64+0x4] ; /* 0x000004040e167981 */
/* 0x000ea2000c1e1900 */
/*0390*/ FFMA R0, -R10, R19, 1 ; /* 0x3f8000000a007423 */
/* 0x001fe20000000113 */
/*03a0*/ BSSY B2, 0x440 ; /* 0x0000009000027945 */
/* 0x000fe60003800000 */
/*03b0*/ FFMA R21, R19, R0, R19 ; /* 0x0000000013157223 */
/* 0x000fe20000000013 */
/*03c0*/ FCHK P0, R22, R10 ; /* 0x0000000a16007302 */
/* 0x004e260000000000 */
/*03d0*/ FFMA R19, R21, R22, RZ ; /* 0x0000001615137223 */
/* 0x000fc800000000ff */
/*03e0*/ FFMA R0, -R10, R19, R22 ; /* 0x000000130a007223 */
/* 0x000fc80000000116 */
/*03f0*/ FFMA R0, R21, R0, R19 ; /* 0x0000000015007223 */
/* 0x000fe20000000013 */
/*0400*/ @!P0 BRA 0x430 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*0410*/ MOV R18, 0x430 ; /* 0x0000043000127802 */
/* 0x002fe40000000f00 */
/*0420*/ CALL.REL.NOINC 0xb20 ; /* 0x000006f000007944 */
/* 0x000fea0003c00000 */
/*0430*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x002fea0003800000 */
/*0440*/ LDG.E R13, [R16.64+0x4] ; /* 0x00000404100d7981 */
/* 0x000ea2000c1e1900 */
/*0450*/ MUFU.RCP R19, R10 ; /* 0x0000000a00137308 */
/* 0x000e220000001000 */
/*0460*/ FADD R13, R13, R0 ; /* 0x000000000d0d7221 */
/* 0x004fca0000000000 */
/*0470*/ STG.E [R16.64+0x4], R13 ; /* 0x0000040d10007986 */
/* 0x0003e8000c101904 */
/*0480*/ LDG.E R22, [R14.64+0x8] ; /* 0x000008040e167981 */
/* 0x000ea2000c1e1900 */
/*0490*/ FFMA R0, -R10, R19, 1 ; /* 0x3f8000000a007423 */
/* 0x001fe20000000113 */
/*04a0*/ BSSY B2, 0x540 ; /* 0x0000009000027945 */
/* 0x000fe60003800000 */
/*04b0*/ FFMA R21, R19, R0, R19 ; /* 0x0000000013157223 */
/* 0x000fe20000000013 */
/*04c0*/ FCHK P0, R22, R10 ; /* 0x0000000a16007302 */
/* 0x004e260000000000 */
/*04d0*/ FFMA R19, R21, R22, RZ ; /* 0x0000001615137223 */
/* 0x000fc800000000ff */
/*04e0*/ FFMA R0, -R10, R19, R22 ; /* 0x000000130a007223 */
/* 0x000fc80000000116 */
/*04f0*/ FFMA R0, R21, R0, R19 ; /* 0x0000000015007223 */
/* 0x000fe20000000013 */
/*0500*/ @!P0 BRA 0x530 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*0510*/ MOV R18, 0x530 ; /* 0x0000053000127802 */
/* 0x002fe40000000f00 */
/*0520*/ CALL.REL.NOINC 0xb20 ; /* 0x000005f000007944 */
/* 0x000fea0003c00000 */
/*0530*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x002fea0003800000 */
/*0540*/ LDG.E R13, [R16.64+0x8] ; /* 0x00000804100d7981 */
/* 0x000ea2000c1e1900 */
/*0550*/ MUFU.RCP R19, R10 ; /* 0x0000000a00137308 */
/* 0x000e220000001000 */
/*0560*/ FADD R13, R13, R0 ; /* 0x000000000d0d7221 */
/* 0x004fca0000000000 */
/*0570*/ STG.E [R16.64+0x8], R13 ; /* 0x0000080d10007986 */
/* 0x0003e8000c101904 */
/*0580*/ LDG.E R22, [R14.64+0xc] ; /* 0x00000c040e167981 */
/* 0x000ea2000c1e1900 */
/*0590*/ FFMA R0, -R10, R19, 1 ; /* 0x3f8000000a007423 */
/* 0x001fe20000000113 */
/*05a0*/ BSSY B2, 0x640 ; /* 0x0000009000027945 */
/* 0x000fe60003800000 */
/*05b0*/ FFMA R21, R19, R0, R19 ; /* 0x0000000013157223 */
/* 0x000fe20000000013 */
/*05c0*/ FCHK P0, R22, R10 ; /* 0x0000000a16007302 */
/* 0x004e260000000000 */
/*05d0*/ FFMA R19, R21, R22, RZ ; /* 0x0000001615137223 */
/* 0x000fc800000000ff */
/*05e0*/ FFMA R0, -R10, R19, R22 ; /* 0x000000130a007223 */
/* 0x000fc80000000116 */
/*05f0*/ FFMA R0, R21, R0, R19 ; /* 0x0000000015007223 */
/* 0x000fe20000000013 */
/*0600*/ @!P0 BRA 0x630 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*0610*/ MOV R18, 0x630 ; /* 0x0000063000127802 */
/* 0x002fe40000000f00 */
/*0620*/ CALL.REL.NOINC 0xb20 ; /* 0x000004f000007944 */
/* 0x000fea0003c00000 */
/*0630*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x002fea0003800000 */
/*0640*/ LDG.E R13, [R16.64+0xc] ; /* 0x00000c04100d7981 */
/* 0x000ea2000c1e1900 */
/*0650*/ IADD3 R25, R25, -0x4, RZ ; /* 0xfffffffc19197810 */
/* 0x000fe40007ffe0ff */
/*0660*/ IADD3 R26, P1, R26, 0x10, RZ ; /* 0x000000101a1a7810 */
/* 0x000fe40007f3e0ff */
/*0670*/ ISETP.NE.AND P0, PT, R25, RZ, PT ; /* 0x000000ff1900720c */
/* 0x000fe40003f05270 */
/*0680*/ IADD3 R14, P2, R14, 0x10, RZ ; /* 0x000000100e0e7810 */
/* 0x000fe20007f5e0ff */
/*0690*/ IMAD.X R27, RZ, RZ, R27, P1 ; /* 0x000000ffff1b7224 */
/* 0x000fe200008e061b */
/*06a0*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fc60007ffe0ff */
/*06b0*/ IMAD.X R15, RZ, RZ, R15, P2 ; /* 0x000000ffff0f7224 */
/* 0x000fe400010e060f */
/*06c0*/ FADD R13, R13, R0 ; /* 0x000000000d0d7221 */
/* 0x004fca0000000000 */
/*06d0*/ STG.E [R16.64+0xc], R13 ; /* 0x00000c0d10007986 */
/* 0x0001e2000c101904 */
/*06e0*/ @P0 BRA 0x260 ; /* 0xfffffb7000000947 */
/* 0x000fea000383ffff */
/*06f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0700*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fda0003f05270 */
/*0710*/ @!P0 BRA 0xad0 ; /* 0x000003b000008947 */
/* 0x000fea0003800000 */
/*0720*/ HFMA2.MMA R14, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0e7435 */
/* 0x000fe200000001ff */
/*0730*/ IMAD R13, R7, c[0x0][0x168], R4 ; /* 0x00005a00070d7a24 */
/* 0x001fc800078e0204 */
/*0740*/ IMAD.IADD R13, R13, 0x1, R2 ; /* 0x000000010d0d7824 */
/* 0x000fca00078e0202 */
/*0750*/ IMAD.WIDE R14, R13, R14, c[0x0][0x160] ; /* 0x000058000d0e7625 */
/* 0x000fca00078e020e */
/*0760*/ LDG.E R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x000ea2000c1e1900 */
/*0770*/ MUFU.RCP R13, R10 ; /* 0x0000000a000d7308 */
/* 0x000e220000001000 */
/*0780*/ BSSY B1, 0x840 ; /* 0x000000b000017945 */
/* 0x000fe20003800000 */
/*0790*/ ISETP.NE.AND P2, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fe20003f45270 */
/*07a0*/ FFMA R0, -R10, R13, 1 ; /* 0x3f8000000a007423 */
/* 0x001fc8000000010d */
/*07b0*/ FFMA R17, R13, R0, R13 ; /* 0x000000000d117223 */
/* 0x000fe2000000000d */
/*07c0*/ FCHK P0, R22, R10 ; /* 0x0000000a16007302 */
/* 0x004e260000000000 */
/*07d0*/ FFMA R13, R17, R22, RZ ; /* 0x00000016110d7223 */
/* 0x000fc800000000ff */
/*07e0*/ FFMA R0, -R10, R13, R22 ; /* 0x0000000d0a007223 */
/* 0x000fc80000000116 */
/*07f0*/ FFMA R0, R17, R0, R13 ; /* 0x0000000011007223 */
/* 0x000fe2000000000d */
/*0800*/ @!P0 BRA 0x830 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*0810*/ MOV R18, 0x830 ; /* 0x0000083000127802 */
/* 0x000fe40000000f00 */
/*0820*/ CALL.REL.NOINC 0xb20 ; /* 0x000002f000007944 */
/* 0x000fea0003c00000 */
/*0830*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0840*/ IMAD.IADD R2, R3, 0x1, R2 ; /* 0x0000000103027824 */
/* 0x000fe200078e0202 */
/*0850*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0860*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0870*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000ea4000c1e1900 */
/*0880*/ FADD R13, R13, R0 ; /* 0x000000000d0d7221 */
/* 0x004fca0000000000 */
/*0890*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e2000c101904 */
/*08a0*/ @!P2 BRA 0xad0 ; /* 0x000002200000a947 */
/* 0x000fea0003800000 */
/*08b0*/ LDG.E R22, [R14.64+0x4] ; /* 0x000004040e167981 */
/* 0x000ea2000c1e1900 */
/*08c0*/ MUFU.RCP R13, R10 ; /* 0x0000000a000d7308 */
/* 0x001e220000001000 */
/*08d0*/ BSSY B1, 0x990 ; /* 0x000000b000017945 */
/* 0x000fe20003800000 */
/*08e0*/ ISETP.NE.AND P2, PT, R9, 0x2, PT ; /* 0x000000020900780c */
/* 0x000fe20003f45270 */
/*08f0*/ FFMA R0, -R10, R13, 1 ; /* 0x3f8000000a007423 */
/* 0x001fc8000000010d */
/*0900*/ FFMA R17, R13, R0, R13 ; /* 0x000000000d117223 */
/* 0x000fe2000000000d */
/*0910*/ FCHK P0, R22, R10 ; /* 0x0000000a16007302 */
/* 0x004e260000000000 */
/*0920*/ FFMA R13, R17, R22, RZ ; /* 0x00000016110d7223 */
/* 0x000fc800000000ff */
/*0930*/ FFMA R0, -R10, R13, R22 ; /* 0x0000000d0a007223 */
/* 0x000fc80000000116 */
/*0940*/ FFMA R0, R17, R0, R13 ; /* 0x0000000011007223 */
/* 0x000fe2000000000d */
/*0950*/ @!P0 BRA 0x980 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*0960*/ MOV R18, 0x980 ; /* 0x0000098000127802 */
/* 0x000fe40000000f00 */
/*0970*/ CALL.REL.NOINC 0xb20 ; /* 0x000001a000007944 */
/* 0x000fea0003c00000 */
/*0980*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0990*/ LDG.E R13, [R2.64+0x4] ; /* 0x00000404020d7981 */
/* 0x000ea4000c1e1900 */
/*09a0*/ FADD R13, R13, R0 ; /* 0x000000000d0d7221 */
/* 0x004fca0000000000 */
/*09b0*/ STG.E [R2.64+0x4], R13 ; /* 0x0000040d02007986 */
/* 0x0001e2000c101904 */
/*09c0*/ @!P2 BRA 0xad0 ; /* 0x000001000000a947 */
/* 0x000fea0003800000 */
/*09d0*/ LDG.E R22, [R14.64+0x8] ; /* 0x000008040e167981 */
/* 0x000ea2000c1e1900 */
/*09e0*/ MUFU.RCP R13, R10 ; /* 0x0000000a000d7308 */
/* 0x001e220000001000 */
/*09f0*/ BSSY B1, 0xaa0 ; /* 0x000000a000017945 */
/* 0x000fe20003800000 */
/*0a00*/ FFMA R0, -R10, R13, 1 ; /* 0x3f8000000a007423 */
/* 0x001fc8000000010d */
/*0a10*/ FFMA R17, R13, R0, R13 ; /* 0x000000000d117223 */
/* 0x000fe4000000000d */
/*0a20*/ FCHK P0, R22, R10 ; /* 0x0000000a16007302 */
/* 0x004e240000000000 */
/*0a30*/ FFMA R13, R17, R22, RZ ; /* 0x00000016110d7223 */
/* 0x000fc800000000ff */
/*0a40*/ FFMA R0, -R10, R13, R22 ; /* 0x0000000d0a007223 */
/* 0x000fc80000000116 */
/*0a50*/ FFMA R0, R17, R0, R13 ; /* 0x0000000011007223 */
/* 0x000fe2000000000d */
/*0a60*/ @!P0 BRA 0xa90 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*0a70*/ MOV R18, 0xa90 ; /* 0x00000a9000127802 */
/* 0x000fe40000000f00 */
/*0a80*/ CALL.REL.NOINC 0xb20 ; /* 0x0000009000007944 */
/* 0x000fea0003c00000 */
/*0a90*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0aa0*/ LDG.E R13, [R2.64+0x8] ; /* 0x00000804020d7981 */
/* 0x000ea4000c1e1900 */
/*0ab0*/ FADD R13, R13, R0 ; /* 0x000000000d0d7221 */
/* 0x004fca0000000000 */
/*0ac0*/ STG.E [R2.64+0x8], R13 ; /* 0x0000080d02007986 */
/* 0x0001e4000c101904 */
/*0ad0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0ae0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fc80007ffe0ff */
/*0af0*/ ISETP.GE.AND P0, PT, R7, R12, PT ; /* 0x0000000c0700720c */
/* 0x000fda0003f06270 */
/*0b00*/ @!P0 BRA 0x170 ; /* 0xfffff66000008947 */
/* 0x000fea000383ffff */
/*0b10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b20*/ SHF.R.U32.HI R0, RZ, 0x17, R10 ; /* 0x00000017ff007819 */
/* 0x000fe2000001160a */
/*0b30*/ BSSY B3, 0x1170 ; /* 0x0000063000037945 */
/* 0x000fe20003800000 */
/*0b40*/ SHF.R.U32.HI R21, RZ, 0x17, R22 ; /* 0x00000017ff157819 */
/* 0x000fe20000011616 */
/*0b50*/ IMAD.MOV.U32 R23, RZ, RZ, R10 ; /* 0x000000ffff177224 */
/* 0x000fe200078e000a */
/*0b60*/ LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff00007812 */
/* 0x000fe400078ec0ff */
/*0b70*/ LOP3.LUT R21, R21, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff15157812 */
/* 0x000fe400078ec0ff */
/*0b80*/ IADD3 R19, R0, -0x1, RZ ; /* 0xffffffff00137810 */
/* 0x000fe40007ffe0ff */
/*0b90*/ IADD3 R20, R21, -0x1, RZ ; /* 0xffffffff15147810 */
/* 0x000fc40007ffe0ff */
/*0ba0*/ ISETP.GT.U32.AND P0, PT, R19, 0xfd, PT ; /* 0x000000fd1300780c */
/* 0x000fc80003f04070 */
/*0bb0*/ ISETP.GT.U32.OR P0, PT, R20, 0xfd, P0 ; /* 0x000000fd1400780c */
/* 0x000fda0000704470 */
/*0bc0*/ @!P0 IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d8224 */
/* 0x000fe200078e00ff */
/*0bd0*/ @!P0 BRA 0xd50 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0be0*/ FSETP.GTU.FTZ.AND P0, PT, |R22|, +INF , PT ; /* 0x7f8000001600780b */
/* 0x000fe40003f1c200 */
/*0bf0*/ FSETP.GTU.FTZ.AND P1, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fc80003f3c200 */
/*0c00*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0c10*/ @P0 BRA 0x1150 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0c20*/ LOP3.LUT P0, RZ, R23, 0x7fffffff, R22, 0xc8, !PT ; /* 0x7fffffff17ff7812 */
/* 0x000fda000780c816 */
/*0c30*/ @!P0 BRA 0x1130 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0c40*/ FSETP.NEU.FTZ.AND P3, PT, |R22|, +INF , PT ; /* 0x7f8000001600780b */
/* 0x000fe40003f7d200 */
/*0c50*/ FSETP.NEU.FTZ.AND P1, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fe40003f3d200 */
/*0c60*/ FSETP.NEU.FTZ.AND P0, PT, |R22|, +INF , PT ; /* 0x7f8000001600780b */
/* 0x000fd60003f1d200 */
/*0c70*/ @!P1 BRA !P3, 0x1130 ; /* 0x000004b000009947 */
/* 0x000fea0005800000 */
/*0c80*/ LOP3.LUT P3, RZ, R22, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff16ff7812 */
/* 0x000fc8000786c0ff */
/*0c90*/ PLOP3.LUT P1, PT, P1, P3, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f26572 */
/*0ca0*/ @P1 BRA 0x1110 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0cb0*/ LOP3.LUT P1, RZ, R23, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff17ff7812 */
/* 0x000fc8000782c0ff */
/*0cc0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0cd0*/ @P0 BRA 0x10e0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0ce0*/ ISETP.GE.AND P0, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fe40003f06270 */
/*0cf0*/ ISETP.GE.AND P1, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fd60003f26270 */
/*0d00*/ @P0 MOV R13, RZ ; /* 0x000000ff000d0202 */
/* 0x000fe20000000f00 */
/*0d10*/ @!P0 IMAD.MOV.U32 R13, RZ, RZ, -0x40 ; /* 0xffffffc0ff0d8424 */
/* 0x000fe400078e00ff */
/*0d20*/ @!P0 FFMA R22, R22, 1.84467440737095516160e+19, RZ ; /* 0x5f80000016168823 */
/* 0x000fe400000000ff */
/*0d30*/ @!P1 FFMA R23, R10, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000a179823 */
/* 0x000fe200000000ff */
/*0d40*/ @!P1 IADD3 R13, R13, 0x40, RZ ; /* 0x000000400d0d9810 */
/* 0x000fe40007ffe0ff */
/*0d50*/ LEA R20, R0, 0xc0800000, 0x17 ; /* 0xc080000000147811 */
/* 0x000fe200078eb8ff */
/*0d60*/ BSSY B4, 0x10d0 ; /* 0x0000036000047945 */
/* 0x000fe20003800000 */
/*0d70*/ IADD3 R21, R21, -0x7f, RZ ; /* 0xffffff8115157810 */
/* 0x000fc60007ffe0ff */
/*0d80*/ IMAD.IADD R28, R23, 0x1, -R20 ; /* 0x00000001171c7824 */
/* 0x000fe400078e0a14 */
/*0d90*/ IMAD R23, R21.reuse, -0x800000, R22 ; /* 0xff80000015177824 */
/* 0x040fe400078e0216 */
/*0da0*/ MUFU.RCP R19, R28 ; /* 0x0000001c00137308 */
/* 0x0000620000001000 */
/*0db0*/ FADD.FTZ R20, -R28, -RZ ; /* 0x800000ff1c147221 */
/* 0x000fe20000010100 */
/*0dc0*/ IADD3 R28, R21, 0x7f, -R0 ; /* 0x0000007f151c7810 */
/* 0x001fc80007ffe800 */
/*0dd0*/ IADD3 R13, R28, R13, RZ ; /* 0x0000000d1c0d7210 */
/* 0x000fe20007ffe0ff */
/*0de0*/ FFMA R24, R19, R20, 1 ; /* 0x3f80000013187423 */
/* 0x002fc80000000014 */
/*0df0*/ FFMA R19, R19, R24, R19 ; /* 0x0000001813137223 */
/* 0x000fc80000000013 */
/*0e00*/ FFMA R22, R23, R19, RZ ; /* 0x0000001317167223 */
/* 0x000fc800000000ff */
/*0e10*/ FFMA R24, R20, R22, R23 ; /* 0x0000001614187223 */
/* 0x000fc80000000017 */
/*0e20*/ FFMA R24, R19, R24, R22 ; /* 0x0000001813187223 */
/* 0x000fc80000000016 */
/*0e30*/ FFMA R20, R20, R24, R23 ; /* 0x0000001814147223 */
/* 0x000fc80000000017 */
/*0e40*/ FFMA R22, R19, R20, R24 ; /* 0x0000001413167223 */
/* 0x000fca0000000018 */
/*0e50*/ SHF.R.U32.HI R0, RZ, 0x17, R22 ; /* 0x00000017ff007819 */
/* 0x000fc80000011616 */
/*0e60*/ LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff00007812 */
/* 0x000fca00078ec0ff */
/*0e70*/ IMAD.IADD R0, R0, 0x1, R13 ; /* 0x0000000100007824 */
/* 0x000fca00078e020d */
/*0e80*/ IADD3 R21, R0, -0x1, RZ ; /* 0xffffffff00157810 */
/* 0x000fc80007ffe0ff */
/*0e90*/ ISETP.GE.U32.AND P0, PT, R21, 0xfe, PT ; /* 0x000000fe1500780c */
/* 0x000fda0003f06070 */
/*0ea0*/ @!P0 BRA 0x10b0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0eb0*/ ISETP.GT.AND P0, PT, R0, 0xfe, PT ; /* 0x000000fe0000780c */
/* 0x000fda0003f04270 */
/*0ec0*/ @P0 BRA 0x1080 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0ed0*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0ee0*/ @P0 BRA 0x10c0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0ef0*/ ISETP.GE.AND P0, PT, R0, -0x18, PT ; /* 0xffffffe80000780c */
/* 0x000fe40003f06270 */
/*0f00*/ LOP3.LUT R22, R22, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000016167812 */
/* 0x000fd600078ec0ff */
/*0f10*/ @!P0 BRA 0x10c0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0f20*/ FFMA.RZ R13, R19.reuse, R20.reuse, R24.reuse ; /* 0x00000014130d7223 */
/* 0x1c0fe2000000c018 */
/*0f30*/ ISETP.NE.AND P3, PT, R0.reuse, RZ, PT ; /* 0x000000ff0000720c */
/* 0x040fe20003f65270 */
/*0f40*/ FFMA.RP R21, R19.reuse, R20.reuse, R24.reuse ; /* 0x0000001413157223 */
/* 0x1c0fe20000008018 */
/*0f50*/ ISETP.NE.AND P1, PT, R0.reuse, RZ, PT ; /* 0x000000ff0000720c */
/* 0x040fe20003f25270 */
/*0f60*/ FFMA.RM R20, R19, R20, R24 ; /* 0x0000001413147223 */
/* 0x000fe20000004018 */
/*0f70*/ LOP3.LUT R13, R13, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0d0d7812 */
/* 0x000fe400078ec0ff */
/*0f80*/ IADD3 R19, R0.reuse, 0x20, RZ ; /* 0x0000002000137810 */
/* 0x040fe40007ffe0ff */
/*0f90*/ LOP3.LUT R24, R13, 0x800000, RZ, 0xfc, !PT ; /* 0x008000000d187812 */
/* 0x000fe400078efcff */
/*0fa0*/ IADD3 R0, -R0, RZ, RZ ; /* 0x000000ff00007210 */
/* 0x000fc40007ffe1ff */
/*0fb0*/ SHF.L.U32 R19, R24, R19, RZ ; /* 0x0000001318137219 */
/* 0x000fe400000006ff */
/*0fc0*/ FSETP.NEU.FTZ.AND P0, PT, R21, R20, PT ; /* 0x000000141500720b */
/* 0x000fe40003f1d000 */
/*0fd0*/ SEL R13, R0, RZ, P3 ; /* 0x000000ff000d7207 */
/* 0x000fe40001800000 */
/*0fe0*/ ISETP.NE.AND P1, PT, R19, RZ, P1 ; /* 0x000000ff1300720c */
/* 0x000fe40000f25270 */
/*0ff0*/ SHF.R.U32.HI R13, RZ, R13, R24 ; /* 0x0000000dff0d7219 */
/* 0x000fe40000011618 */
/*1000*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*1010*/ SHF.R.U32.HI R19, RZ, 0x1, R13 ; /* 0x00000001ff137819 */
/* 0x000fe4000001160d */
/*1020*/ SEL R0, RZ, 0x1, !P0 ; /* 0x00000001ff007807 */
/* 0x000fc80004000000 */
/*1030*/ LOP3.LUT R0, R0, 0x1, R19, 0xf8, !PT ; /* 0x0000000100007812 */
/* 0x000fc800078ef813 */
/*1040*/ LOP3.LUT R0, R0, R13, RZ, 0xc0, !PT ; /* 0x0000000d00007212 */
/* 0x000fca00078ec0ff */
/*1050*/ IMAD.IADD R19, R19, 0x1, R0 ; /* 0x0000000113137824 */
/* 0x000fca00078e0200 */
/*1060*/ LOP3.LUT R22, R19, R22, RZ, 0xfc, !PT ; /* 0x0000001613167212 */
/* 0x000fe200078efcff */
/*1070*/ BRA 0x10c0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*1080*/ LOP3.LUT R22, R22, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000016167812 */
/* 0x000fc800078ec0ff */
/*1090*/ LOP3.LUT R22, R22, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000016167812 */
/* 0x000fe200078efcff */
/*10a0*/ BRA 0x10c0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*10b0*/ LEA R22, R13, R22, 0x17 ; /* 0x000000160d167211 */
/* 0x000fe400078eb8ff */
/*10c0*/ BSYNC B4 ; /* 0x0000000000047941 */
/* 0x000fea0003800000 */
/*10d0*/ BRA 0x1160 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*10e0*/ LOP3.LUT R22, R23, 0x80000000, R22, 0x48, !PT ; /* 0x8000000017167812 */
/* 0x000fc800078e4816 */
/*10f0*/ LOP3.LUT R22, R22, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000016167812 */
/* 0x000fe200078efcff */
/*1100*/ BRA 0x1160 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*1110*/ LOP3.LUT R22, R23, 0x80000000, R22, 0x48, !PT ; /* 0x8000000017167812 */
/* 0x000fe200078e4816 */
/*1120*/ BRA 0x1160 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*1130*/ MUFU.RSQ R22, -QNAN ; /* 0xffc0000000167908 */
/* 0x000e220000001400 */
/*1140*/ BRA 0x1160 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*1150*/ FADD.FTZ R22, R22, R10 ; /* 0x0000000a16167221 */
/* 0x000fe40000010000 */
/*1160*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*1170*/ HFMA2.MMA R19, -RZ, RZ, 0, 0 ; /* 0x00000000ff137435 */
/* 0x000fe200000001ff */
/*1180*/ IMAD.MOV.U32 R0, RZ, RZ, R22 ; /* 0x000000ffff007224 */
/* 0x001fca00078e0016 */
/*1190*/ RET.REL.NODEC R18 0x0 ; /* 0xffffee6012007950 */
/* 0x000fea0003c3ffff */
/*11a0*/ BRA 0x11a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*11b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8compressPfiS_i
.globl _Z8compressPfiS_i
.p2align 8
.type _Z8compressPfiS_i,@function
_Z8compressPfiS_i:
s_load_b32 s2, s[0:1], 0x2c
v_and_b32_e32 v3, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s6, s2, 0xffff
v_mad_u64_u32 v[4:5], null, s15, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s6, v[3:4]
v_add_nc_u32_e32 v1, -1, v4
v_cmp_gt_u32_e64 s2, 2, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, 3, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_6
s_load_b32 s7, s[4:5], 0x0
s_clause 0x3
s_load_b32 s10, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b32 s1, s[0:1], 0x18
v_cmp_lt_i32_e64 s0, 0, v0
s_mov_b32 s11, 0
s_mov_b32 s12, 0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[5:6], null, s7, v4, s[14:15]
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, v5, s6, v[3:4]
v_cvt_f32_i32_e32 v5, s10
v_max_i32_e32 v4, 1, v4
s_mov_b32 s6, 0
s_branch .LBB0_3
.LBB0_2:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s13
s_add_i32 s12, s12, 1
v_add_nc_u32_e32 v1, s10, v1
v_cmp_eq_u32_e32 vcc_lo, s12, v4
s_add_i32 s6, s6, s1
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execz .LBB0_6
.LBB0_3:
s_and_saveexec_b32 s13, s0
s_cbranch_execz .LBB0_2
s_ashr_i32 s7, s6, 31
v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v7, v0
s_lshl_b64 s[8:9], s[6:7], 2
s_mov_b32 s7, 0
s_add_u32 s8, s4, s8
s_addc_u32 s9, s5, s9
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_5:
v_ashrrev_i32_e32 v3, 31, v2
v_add_nc_u32_e32 v7, -1, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[8:9], 2, v[2:3]
v_add_nc_u32_e32 v2, 1, v2
v_add_co_u32 v8, vcc_lo, s2, v8
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
global_load_b32 v3, v[8:9], off
global_load_b32 v8, v6, s[8:9]
s_waitcnt vmcnt(1)
v_div_scale_f32 v9, null, v5, v5, v3
v_div_scale_f32 v12, vcc_lo, v3, v5, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v10, v9
s_waitcnt_depctr 0xfff
v_fma_f32 v11, -v9, v10, 1.0
v_fmac_f32_e32 v10, v11, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v11, v12, v10
v_fma_f32 v13, -v9, v11, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v11, v13, v10
v_fma_f32 v9, -v9, v11, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v9, v9, v10, v11
v_cmp_eq_u32_e32 vcc_lo, 0, v7
v_div_fixup_f32 v3, v9, v5, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_add_f32_e32 v3, v8, v3
global_store_b32 v6, v3, s[8:9]
s_add_u32 s8, s8, 4
s_addc_u32 s9, s9, 0
s_or_b32 s7, vcc_lo, s7
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_5
s_branch .LBB0_2
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8compressPfiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8compressPfiS_i, .Lfunc_end0-_Z8compressPfiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8compressPfiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8compressPfiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000834c8_00000000-6_quiz_3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%.1f\t"
.LC1:
.string "\n"
.text
.globl _Z9print_matPfi
.type _Z9print_matPfi, @function
_Z9print_matPfi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L4
movslq %esi, %r14
leaq 0(,%r14,4), %r15
leaq (%rdi,%r15), %rbp
negq %r14
salq $2, %r14
movl $0, %r13d
leaq .LC0(%rip), %r12
.L5:
leaq 0(%rbp,%r14), %rbx
.L6:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addq %r15, %rbp
cmpl %r13d, 12(%rsp)
jne .L5
.L4:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z9print_matPfi, .-_Z9print_matPfi
.globl _Z8fill_matPfi
.type _Z8fill_matPfi, @function
_Z8fill_matPfi:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L9
movslq %esi, %r11
salq $2, %r11
movl %esi, %r8d
movl $0, %r9d
movl $0, %eax
.L11:
movl %eax, %r10d
movq %rdi, %rdx
.L12:
movl %eax, %ecx
addl $1, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %ecx, %xmm0
movss %xmm0, (%rdx)
addq $4, %rdx
cmpl %r8d, %eax
jne .L12
leal (%rsi,%r10), %eax
addl $1, %r9d
addl %esi, %r8d
addq %r11, %rdi
cmpl %r9d, %esi
jne .L11
.L9:
ret
.cfi_endproc
.LFE2058:
.size _Z8fill_matPfi, .-_Z8fill_matPfi
.globl _Z31__device_stub__Z8compressPfiS_iPfiS_i
.type _Z31__device_stub__Z8compressPfiS_iPfiS_i, @function
_Z31__device_stub__Z8compressPfiS_iPfiS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8compressPfiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z31__device_stub__Z8compressPfiS_iPfiS_i, .-_Z31__device_stub__Z8compressPfiS_iPfiS_i
.globl _Z8compressPfiS_i
.type _Z8compressPfiS_i, @function
_Z8compressPfiS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8compressPfiS_iPfiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z8compressPfiS_i, .-_Z8compressPfiS_i
.section .rodata.str1.1
.LC2:
.string "\n input mat \n"
.LC3:
.string "\n compress mat \n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $36, %edi
call malloc@PLT
movq %rax, %rbp
movl $324, %edi
call malloc@PLT
movq %rax, %rbx
movq %rsp, %rdi
movl $36, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $324, %esi
call cudaMalloc@PLT
movl $9, %esi
movq %rbx, %rdi
call _Z8fill_matPfi
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $9, %esi
movq %rbx, %rdi
call _Z9print_matPfi
movl $1, %ecx
movl $36, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $324, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, 16(%rsp)
movl $0, 20(%rsp)
movl $0, 28(%rsp)
movl $0, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L23:
movl $2, %ecx
movl $36, %edx
movq (%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $9, %esi
movq %rbp, %rdi
call _Z9print_matPfi
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L27
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movl $3, %ecx
movq (%rsp), %rdx
movl $9, %esi
movq 8(%rsp), %rdi
call _Z31__device_stub__Z8compressPfiS_iPfiS_i
jmp .L23
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z8compressPfiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z8compressPfiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "quiz_3.hip"
.globl _Z23__device_stub__compressPfiS_i # -- Begin function _Z23__device_stub__compressPfiS_i
.p2align 4, 0x90
.type _Z23__device_stub__compressPfiS_i,@function
_Z23__device_stub__compressPfiS_i: # @_Z23__device_stub__compressPfiS_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8compressPfiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__compressPfiS_i, .Lfunc_end0-_Z23__device_stub__compressPfiS_i
.cfi_endproc
# -- End function
.globl _Z9print_matPfi # -- Begin function _Z9print_matPfi
.p2align 4, 0x90
.type _Z9print_matPfi,@function
_Z9print_matPfi: # @_Z9print_matPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, (%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB1_5
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebx
movl %esi, %r15d
xorl %r12d, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movl %r12d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbp,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %r15
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addl %ebx, %r12d
cmpq %r15, %r13
jne .LBB1_2
.LBB1_5: # %._crit_edge14
movl $10, %edi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end1:
.size _Z9print_matPfi, .Lfunc_end1-_Z9print_matPfi
.cfi_endproc
# -- End function
.globl _Z8fill_matPfi # -- Begin function _Z8fill_matPfi
.p2align 4, 0x90
.type _Z8fill_matPfi,@function
_Z8fill_matPfi: # @_Z8fill_matPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_5
# %bb.1: # %.preheader.lr.ph
movl %esi, %eax
xorl %ecx, %ecx
xorl %edx, %edx
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
movl %ecx, %r9d
leaq (%rdi,%r9,4), %r10
movl %r8d, %r8d
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
leal (%r8,%r9), %r11d
xorps %xmm0, %xmm0
cvtsi2ss %r11d, %xmm0
movss %xmm0, (%r10,%r9,4)
incq %r9
cmpq %r9, %rax
jne .LBB2_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %rdx
addl %esi, %ecx
addl %r9d, %r8d
cmpq %rax, %rdx
jne .LBB2_2
.LBB2_5: # %._crit_edge17
retq
.Lfunc_end2:
.size _Z8fill_matPfi, .Lfunc_end2-_Z8fill_matPfi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $36, %edi
callq malloc
movq %rax, %rbx
movl $324, %edi # imm = 0x144
callq malloc
movq %rax, %r14
leaq 8(%rsp), %rdi
movl $36, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $324, %esi # imm = 0x144
callq hipMalloc
xorl %eax, %eax
movq %r14, %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
movl %edx, %edx
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rdx,%rsi), %edi
xorps %xmm0, %xmm0
cvtsi2ss %edi, %xmm0
movss %xmm0, (%rcx,%rsi,4)
incq %rsi
cmpq $9, %rsi
jne .LBB3_2
# %bb.3: # %._crit_edge.i
# in Loop: Header=BB3_1 Depth=1
incq %rax
addq $36, %rcx
addl %esi, %edx
cmpq $9, %rax
jne .LBB3_1
# %bb.4: # %_Z8fill_matPfi.exit
movl $.Lstr, %edi
callq puts@PLT
xorl %r15d, %r15d
movq %r14, %r12
.p2align 4, 0x90
.LBB3_5: # %.preheader.i15
# =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_6: # Parent Loop BB3_5 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r13
cmpq $9, %r13
jne .LBB3_6
# %bb.7: # %._crit_edge.i19
# in Loop: Header=BB3_5 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq $36, %r12
cmpq $9, %r15
jne .LBB3_5
# %bb.8: # %_Z9print_matPfi.exit
movl $10, %edi
callq putchar@PLT
movq 8(%rsp), %rdi
movl $36, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $324, %edx # imm = 0x144
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
xorl %edi, %edi
movl $1, %esi
xorl %edx, %edx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_10
# %bb.9:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movl $9, 28(%rsp)
movq %rcx, 80(%rsp)
movl $3, 24(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 28(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8compressPfiS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_10:
movq 8(%rsp), %rsi
movl $36, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r15d, %r15d
movq %rbx, %r12
.p2align 4, 0x90
.LBB3_11: # %.preheader.i20
# =>This Loop Header: Depth=1
# Child Loop BB3_12 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_12: # Parent Loop BB3_11 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r13
cmpq $9, %r13
jne .LBB3_12
# %bb.13: # %._crit_edge.i25
# in Loop: Header=BB3_11 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq $36, %r12
cmpq $9, %r15
jne .LBB3_11
# %bb.14: # %_Z9print_matPfi.exit30
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8compressPfiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8compressPfiS_i,@object # @_Z8compressPfiS_i
.section .rodata,"a",@progbits
.globl _Z8compressPfiS_i
.p2align 3, 0x0
_Z8compressPfiS_i:
.quad _Z23__device_stub__compressPfiS_i
.size _Z8compressPfiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%.1f\t"
.size .L.str, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8compressPfiS_i"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n input mat "
.size .Lstr, 13
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n compress mat "
.size .Lstr.1, 16
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__compressPfiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8compressPfiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <time.h>
typedef struct vertex vertex;
struct vertex {
unsigned int vertex_id;
float pagerank;
float pagerank_next;
unsigned int n_successors;
vertex ** successors;
};
float abs_float(float in) {
if (in >= 0)
return in;
else
return -in;
}
int main(int argc, char ** args) {
if (argc != 2) {
fprintf(stderr,"Wrong number of args. Provide input graph file.\n");
exit(-1);
}
// Start CPU timer
clock_t cycles_to_build, cycles_to_calc;
// build up the graph
int i,j;
unsigned int n_vertices = 0;
unsigned int vertex_from = 0, vertex_to = 0;
vertex * vertices;
FILE * fp;
if ((fp = fopen(args[1], "r")) == NULL) {
fprintf(stderr,"ERROR: Could not open input file.\n");
exit(-1);
}
// parse input file to count the number of vertices
// expected format: vertex_from vertex_to
while (fscanf(fp, "%u %u", &vertex_from, &vertex_to) != EOF) {
if (vertex_from > n_vertices) {
n_vertices = vertex_from;
}
else if (vertex_to > n_vertices) {
n_vertices = vertex_to;
}
}
n_vertices++;
clock_t start = clock();
// allocate memory for vertices
vertices = (vertex *)malloc(n_vertices*sizeof(vertex));
if (!vertices) {
fprintf(stderr,"Malloc failed for vertices.\n");
exit(-1);
}
memset((void *)vertices, 0, (size_t)(n_vertices*sizeof(vertex)));
// parse input file to count the number of successors of each vertex
fseek(fp, 0L, SEEK_SET);
while (fscanf(fp, "%u %u", &vertex_from, &vertex_to) != EOF) {
vertices[vertex_from].n_successors++;
}
// allocate memory for successor pointers
for (i=0; i<n_vertices; i++) {
vertices[i].vertex_id = i;
if (vertices[i].n_successors > 0) {
vertices[i].successors = (vertex **)malloc(vertices[i].n_successors*sizeof(vertex *));
if (!vertices[i].successors) {
fprintf(stderr,"Malloc failed for successors of vertex %d.\n",i);
exit(-1);
}
memset((void *)vertices[i].successors, 0, (size_t)(vertices[i].n_successors*sizeof(vertex *)));
}
else {
vertices[i].successors = NULL;
}
}
// parse input file to set up the successor pointers
fseek(fp, 0L, SEEK_SET);
while (fscanf(fp, "%d %d", &vertex_from, &vertex_to) != EOF) {
for (i=0; i<vertices[vertex_from].n_successors; i++) {
if (vertices[vertex_from].successors[i] == NULL) {
vertices[vertex_from].successors[i] = &vertices[vertex_to];
break;
}
else if (i==vertices[vertex_from].n_successors-1) {
printf("Setting up the successor pointers of virtex %u failed",vertex_from);
return -1;
}
}
}
fclose(fp);
cycles_to_build = clock() - start;
start = clock();
/* int j; // PRINT THE DATASTRUCTURE
for(i = 0; i < n_vertices; i++) {
printf("Page: %d, Suc: ", (vertices+i)->vertex_id);
for(j = 0; j < (vertices+i)->n_successors; j++) {
printf("%d, ",(vertices+i)->successors[j]->vertex_id);
}
printf("\n");
} */
/*************************************************************************/
// compute the pagerank
unsigned int n_iterations = 24;
float alpha = 0.85;
float eps = 0.000001;
// run on the host
unsigned int i_iteration;
float value, diff;
float pr_dangling_factor = alpha / (float)n_vertices; // pagerank to redistribute from dangling nodes
float pr_dangling;
float pr_random_factor = (1-alpha) / (float)n_vertices; // random portion of the pagerank
float pr_random;
float pr_sum, pr_sum_inv, pr_sum_dangling;
float temp;
// initialization
for (i=0;i<n_vertices;i++) {
vertices[i].pagerank = 1 / (float)n_vertices;
vertices[i].pagerank_next = 0;
}
pr_sum = 0;
pr_sum_dangling = 0;
for (i=0; i<n_vertices; i++) {
pr_sum += vertices[i].pagerank;
if (!vertices[i].n_successors) {
pr_sum_dangling += vertices[i].pagerank;
}
}
i_iteration = 0;
diff = eps+1;
while ( (diff > eps) && (i_iteration < n_iterations) ) { // can do 23 iterations for 1 million nodes
for (i=0;i<n_vertices;i++) {
if (vertices[i].n_successors) {
value = (alpha * vertices[i].pagerank)/vertices[i].n_successors; //value = vote split equally
} else {
value = 0;
}
for (j=0;j<vertices[i].n_successors;j++) { // pagerank_next = sum of votes linking to it
vertices[i].successors[j]->pagerank_next += value;
}
}
// for normalization
pr_sum_inv = 1/pr_sum;
// alpha
pr_dangling = pr_dangling_factor * pr_sum_dangling;
pr_random = pr_random_factor;
pr_sum = 0;
pr_sum_dangling = 0;
diff = 0;
for (i=0;i<n_vertices;i++) {
// update pagerank
temp = vertices[i].pagerank;
/************************************************************************************/
//vertices[i].pagerank = vertices[i].pagerank_next*pr_sum_inv + pr_dangling + pr_random;
vertices[i].pagerank = vertices[i].pagerank_next + pr_dangling + pr_random;
/************************************************************************************/
vertices[i].pagerank_next = 0;
// for normalization in next cycle
pr_sum += vertices[i].pagerank;
if (!vertices[i].n_successors)
pr_sum_dangling += vertices[i].pagerank;
// convergence
diff += abs_float(temp - vertices[i].pagerank);
// printf("prev: %.12f, pr: %.12f\n",temp, vertices[i].pagerank);
}
// printf("Iteration %u:\t diff = %.12f\n", i_iteration, diff);
i_iteration++;
}
/*************************************************************************/
// End CPU Timer
cycles_to_calc = clock() - start;
// Print time
int build_msec = cycles_to_build * 1000 / CLOCKS_PER_SEC;
int calc_msec = cycles_to_calc * 1000 / CLOCKS_PER_SEC;
// print pageranks
FILE *f_result;
f_result=fopen("result_CPU","w");
for (i=0;i<n_vertices;i++) {
fprintf(f_result,"Vertex %u:\tpagerank = %.18f\n", i, vertices[i].pagerank);
}
fclose(f_result);
printf("Time to build: %d seconds, %d milliseconds\n", build_msec/1000, build_msec%1000);
printf("Time to calc: %d seconds, %d milliseconds\n", calc_msec/1000, calc_msec%1000);
printf("iter: %d\n",i_iteration);
printf("Done\n");
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <time.h>
typedef struct vertex vertex;
struct vertex {
unsigned int vertex_id;
float pagerank;
float pagerank_next;
unsigned int n_successors;
vertex ** successors;
};
float abs_float(float in) {
if (in >= 0)
return in;
else
return -in;
}
int main(int argc, char ** args) {
if (argc != 2) {
fprintf(stderr,"Wrong number of args. Provide input graph file.\n");
exit(-1);
}
// Start CPU timer
clock_t cycles_to_build, cycles_to_calc;
// build up the graph
int i,j;
unsigned int n_vertices = 0;
unsigned int vertex_from = 0, vertex_to = 0;
vertex * vertices;
FILE * fp;
if ((fp = fopen(args[1], "r")) == NULL) {
fprintf(stderr,"ERROR: Could not open input file.\n");
exit(-1);
}
// parse input file to count the number of vertices
// expected format: vertex_from vertex_to
while (fscanf(fp, "%u %u", &vertex_from, &vertex_to) != EOF) {
if (vertex_from > n_vertices) {
n_vertices = vertex_from;
}
else if (vertex_to > n_vertices) {
n_vertices = vertex_to;
}
}
n_vertices++;
clock_t start = clock();
// allocate memory for vertices
vertices = (vertex *)malloc(n_vertices*sizeof(vertex));
if (!vertices) {
fprintf(stderr,"Malloc failed for vertices.\n");
exit(-1);
}
memset((void *)vertices, 0, (size_t)(n_vertices*sizeof(vertex)));
// parse input file to count the number of successors of each vertex
fseek(fp, 0L, SEEK_SET);
while (fscanf(fp, "%u %u", &vertex_from, &vertex_to) != EOF) {
vertices[vertex_from].n_successors++;
}
// allocate memory for successor pointers
for (i=0; i<n_vertices; i++) {
vertices[i].vertex_id = i;
if (vertices[i].n_successors > 0) {
vertices[i].successors = (vertex **)malloc(vertices[i].n_successors*sizeof(vertex *));
if (!vertices[i].successors) {
fprintf(stderr,"Malloc failed for successors of vertex %d.\n",i);
exit(-1);
}
memset((void *)vertices[i].successors, 0, (size_t)(vertices[i].n_successors*sizeof(vertex *)));
}
else {
vertices[i].successors = NULL;
}
}
// parse input file to set up the successor pointers
fseek(fp, 0L, SEEK_SET);
while (fscanf(fp, "%d %d", &vertex_from, &vertex_to) != EOF) {
for (i=0; i<vertices[vertex_from].n_successors; i++) {
if (vertices[vertex_from].successors[i] == NULL) {
vertices[vertex_from].successors[i] = &vertices[vertex_to];
break;
}
else if (i==vertices[vertex_from].n_successors-1) {
printf("Setting up the successor pointers of virtex %u failed",vertex_from);
return -1;
}
}
}
fclose(fp);
cycles_to_build = clock() - start;
start = clock();
/* int j; // PRINT THE DATASTRUCTURE
for(i = 0; i < n_vertices; i++) {
printf("Page: %d, Suc: ", (vertices+i)->vertex_id);
for(j = 0; j < (vertices+i)->n_successors; j++) {
printf("%d, ",(vertices+i)->successors[j]->vertex_id);
}
printf("\n");
} */
/*************************************************************************/
// compute the pagerank
unsigned int n_iterations = 24;
float alpha = 0.85;
float eps = 0.000001;
// run on the host
unsigned int i_iteration;
float value, diff;
float pr_dangling_factor = alpha / (float)n_vertices; // pagerank to redistribute from dangling nodes
float pr_dangling;
float pr_random_factor = (1-alpha) / (float)n_vertices; // random portion of the pagerank
float pr_random;
float pr_sum, pr_sum_inv, pr_sum_dangling;
float temp;
// initialization
for (i=0;i<n_vertices;i++) {
vertices[i].pagerank = 1 / (float)n_vertices;
vertices[i].pagerank_next = 0;
}
pr_sum = 0;
pr_sum_dangling = 0;
for (i=0; i<n_vertices; i++) {
pr_sum += vertices[i].pagerank;
if (!vertices[i].n_successors) {
pr_sum_dangling += vertices[i].pagerank;
}
}
i_iteration = 0;
diff = eps+1;
while ( (diff > eps) && (i_iteration < n_iterations) ) { // can do 23 iterations for 1 million nodes
for (i=0;i<n_vertices;i++) {
if (vertices[i].n_successors) {
value = (alpha * vertices[i].pagerank)/vertices[i].n_successors; //value = vote split equally
} else {
value = 0;
}
for (j=0;j<vertices[i].n_successors;j++) { // pagerank_next = sum of votes linking to it
vertices[i].successors[j]->pagerank_next += value;
}
}
// for normalization
pr_sum_inv = 1/pr_sum;
// alpha
pr_dangling = pr_dangling_factor * pr_sum_dangling;
pr_random = pr_random_factor;
pr_sum = 0;
pr_sum_dangling = 0;
diff = 0;
for (i=0;i<n_vertices;i++) {
// update pagerank
temp = vertices[i].pagerank;
/************************************************************************************/
//vertices[i].pagerank = vertices[i].pagerank_next*pr_sum_inv + pr_dangling + pr_random;
vertices[i].pagerank = vertices[i].pagerank_next + pr_dangling + pr_random;
/************************************************************************************/
vertices[i].pagerank_next = 0;
// for normalization in next cycle
pr_sum += vertices[i].pagerank;
if (!vertices[i].n_successors)
pr_sum_dangling += vertices[i].pagerank;
// convergence
diff += abs_float(temp - vertices[i].pagerank);
// printf("prev: %.12f, pr: %.12f\n",temp, vertices[i].pagerank);
}
// printf("Iteration %u:\t diff = %.12f\n", i_iteration, diff);
i_iteration++;
}
/*************************************************************************/
// End CPU Timer
cycles_to_calc = clock() - start;
// Print time
int build_msec = cycles_to_build * 1000 / CLOCKS_PER_SEC;
int calc_msec = cycles_to_calc * 1000 / CLOCKS_PER_SEC;
// print pageranks
FILE *f_result;
f_result=fopen("result_CPU","w");
for (i=0;i<n_vertices;i++) {
fprintf(f_result,"Vertex %u:\tpagerank = %.18f\n", i, vertices[i].pagerank);
}
fclose(f_result);
printf("Time to build: %d seconds, %d milliseconds\n", build_msec/1000, build_msec%1000);
printf("Time to calc: %d seconds, %d milliseconds\n", calc_msec/1000, calc_msec%1000);
printf("iter: %d\n",i_iteration);
printf("Done\n");
return 0;
} | .file "tmpxft_0017f6e6_00000000-6_pagerank_CPU_benchmark.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9abs_floatf
.type _Z9abs_floatf, @function
_Z9abs_floatf:
.LFB2057:
.cfi_startproc
endbr64
pxor %xmm1, %xmm1
comiss %xmm1, %xmm0
jb .L5
.L4:
ret
.L5:
xorps .LC1(%rip), %xmm0
ret
.cfi_endproc
.LFE2057:
.size _Z9abs_floatf, .-_Z9abs_floatf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Wrong number of args. Provide input graph file.\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "r"
.section .rodata.str1.8
.align 8
.LC4:
.string "ERROR: Could not open input file.\n"
.section .rodata.str1.1
.LC5:
.string "%u %u"
.LC6:
.string "Malloc failed for vertices.\n"
.section .rodata.str1.8
.align 8
.LC7:
.string "Malloc failed for successors of vertex %d.\n"
.align 8
.LC8:
.string "Setting up the successor pointers of virtex %u failed"
.section .rodata.str1.1
.LC9:
.string "%d %d"
.LC14:
.string "Vertex %u:\tpagerank = %.18f\n"
.section .rodata.str1.8
.align 8
.LC15:
.string "Time to build: %d seconds, %d milliseconds\n"
.align 8
.LC16:
.string "Time to calc: %d seconds, %d milliseconds\n"
.section .rodata.str1.1
.LC17:
.string "iter: %d\n"
.LC18:
.string "Done\n"
.LC19:
.string "w"
.LC20:
.string "result_CPU"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jne .L61
movl $0, 32(%rsp)
movl $0, 36(%rsp)
movq 8(%rsi), %rdi
leaq .LC3(%rip), %rsi
call fopen@PLT
movq %rax, %r13
testq %rax, %rax
je .L62
movl $0, %r14d
leaq .LC5(%rip), %rbx
jmp .L8
.L61:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L62:
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L9:
movl %eax, %r14d
.L8:
leaq 36(%rsp), %rcx
leaq 32(%rsp), %rdx
movq %rbx, %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $-1, %eax
je .L63
movl 32(%rsp), %eax
cmpl %eax, %r14d
jb .L9
movl 36(%rsp), %eax
cmpl %eax, %r14d
cmovnb %r14d, %eax
jmp .L9
.L63:
leal 1(%r14), %r15d
call clock@PLT
movq %rax, 24(%rsp)
movl %r15d, %eax
leaq (%rax,%rax,2), %rbx
salq $3, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
testq %rax, %rax
je .L64
movq %rbx, %rcx
movq %rbx, %rdx
movl $0, %esi
movq %rax, %rdi
call __memset_chk@PLT
movl $0, %edx
movl $0, %esi
movq %r13, %rdi
call fseek@PLT
leaq .LC5(%rip), %rbx
jmp .L12
.L64:
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L13:
movl 32(%rsp), %eax
leaq (%rax,%rax,2), %rax
addl $1, 12(%r12,%rax,8)
.L12:
leaq 36(%rsp), %rcx
leaq 32(%rsp), %rdx
movq %rbx, %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl %eax, 16(%rsp)
cmpl $-1, %eax
jne .L13
testl %r15d, %r15d
je .L14
movq %r12, %rbx
movl $0, %ebp
jmp .L18
.L66:
movl %eax, %eax
salq $3, %rax
movq %rax, 8(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %rdi
movq %rax, 16(%rbx)
testq %rax, %rax
je .L65
movq 8(%rsp), %rcx
movq %rcx, %rdx
movl $0, %esi
call __memset_chk@PLT
.L17:
addl $1, %ebp
addq $24, %rbx
cmpl %r15d, %ebp
je .L14
.L18:
movl %ebp, (%rbx)
movl 12(%rbx), %eax
testl %eax, %eax
jne .L66
movq $0, 16(%rbx)
jmp .L17
.L65:
movl %ebp, %ecx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L14:
movl $0, %edx
movl $0, %esi
movq %r13, %rdi
call fseek@PLT
leaq .LC9(%rip), %rbx
.L58:
leaq 36(%rsp), %rcx
leaq 32(%rsp), %rdx
movq %rbx, %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $-1, %eax
je .L25
movl 32(%rsp), %esi
movl %esi, %eax
leaq (%rax,%rax,2), %rax
leaq (%r12,%rax,8), %rax
movl 12(%rax), %edx
testl %edx, %edx
je .L58
movq 16(%rax), %rax
movl %edx, %ecx
leaq (%rax,%rcx,8), %rcx
leal -1(%rdx), %edx
leaq (%rax,%rdx,8), %rdx
.L23:
cmpq $0, (%rax)
je .L67
cmpq %rdx, %rax
je .L68
addq $8, %rax
cmpq %rcx, %rax
jne .L23
jmp .L58
.L67:
movl 36(%rsp), %edx
leaq (%rdx,%rdx,2), %rdx
leaq (%r12,%rdx,8), %rdx
movq %rdx, (%rax)
jmp .L58
.L68:
movl %esi, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L6:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L69
movl 16(%rsp), %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movq %r13, %rdi
call fclose@PLT
call clock@PLT
movq 24(%rsp), %rbx
subq %rbx, %rax
movq %rax, %rbx
call clock@PLT
movq %rax, %r13
movl %r15d, %eax
pxor %xmm1, %xmm1
cvtsi2ssq %rax, %xmm1
movss .LC10(%rip), %xmm9
divss %xmm1, %xmm9
movss .LC11(%rip), %xmm5
divss %xmm1, %xmm5
testl %r15d, %r15d
je .L49
movss .LC12(%rip), %xmm0
divss %xmm1, %xmm0
leaq 4(%r12), %rdx
movl %r14d, %eax
imulq $24, %rax, %rax
leaq 28(%r12,%rax), %rcx
movq %rdx, %rax
.L30:
movss %xmm0, (%rax)
movl $0x00000000, 4(%rax)
addq $24, %rax
cmpq %rcx, %rax
jne .L30
pxor %xmm3, %xmm3
jmp .L32
.L31:
addq $24, %rdx
cmpq %rcx, %rdx
je .L29
.L32:
cmpl $0, 8(%rdx)
jne .L31
addss (%rdx), %xmm3
jmp .L31
.L49:
pxor %xmm3, %xmm3
.L29:
movl %r14d, %eax
imulq $24, %rax, %rax
leaq 28(%r12,%rax), %r8
movl $0, %ebp
movss .LC10(%rip), %xmm7
pxor %xmm6, %xmm6
movss .LC1(%rip), %xmm8
jmp .L33
.L71:
movaps %xmm7, %xmm1
mulss (%rdi), %xmm1
movl %eax, %eax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss %xmm0, %xmm1
movl $0, %eax
.L37:
movq 12(%rcx), %rdx
movq (%rdx,%rax,8), %rdx
movaps %xmm1, %xmm0
addss 8(%rdx), %xmm0
movss %xmm0, 8(%rdx)
addq $1, %rax
cmpl 8(%rcx), %eax
jb .L37
.L34:
addq $24, %rdi
cmpq %rdi, %r8
je .L70
.L38:
movq %rdi, %rcx
movl 8(%rdi), %eax
testl %eax, %eax
je .L34
jmp .L71
.L70:
mulss %xmm9, %xmm3
movaps %xmm3, %xmm4
pxor %xmm3, %xmm3
movaps %xmm3, %xmm2
jmp .L41
.L39:
subss %xmm1, %xmm0
comiss %xmm6, %xmm0
jb .L72
.L40:
addss %xmm0, %xmm2
addq $24, %rsi
cmpq %rsi, %r8
je .L73
.L41:
movss (%rsi), %xmm0
movaps %xmm4, %xmm1
addss 4(%rsi), %xmm1
addss %xmm5, %xmm1
movss %xmm1, (%rsi)
movl $0x00000000, 4(%rsi)
cmpl $0, 8(%rsi)
jne .L39
addss %xmm1, %xmm3
jmp .L39
.L72:
xorps %xmm8, %xmm0
jmp .L40
.L73:
addl $1, %ebp
comiss .LC13(%rip), %xmm2
jbe .L42
cmpl $23, %ebp
ja .L42
.L33:
testl %r15d, %r15d
je .L74
leaq 4(%r12), %rsi
movq %rsi, %rdi
jmp .L38
.L74:
addl $1, %ebp
call clock@PLT
movq %rax, %rsi
movl $1000, %ecx
movq %rbx, %rax
cqto
idivq %rcx
movq %rax, 16(%rsp)
movq %rsi, %rax
subq %r13, %rax
cqto
idivq %rcx
movq %rax, 8(%rsp)
leaq .LC19(%rip), %rsi
leaq .LC20(%rip), %rdi
call fopen@PLT
movq %rax, %r13
.L46:
movq %r13, %rdi
call fclose@PLT
movl $1000, %ebx
movl 16(%rsp), %eax
cltd
idivl %ebx
movl %edx, %ecx
movl %eax, %edx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 8(%rsp), %eax
cltd
idivl %ebx
movl %edx, %ecx
movl %eax, %edx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %edx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, 16(%rsp)
jmp .L6
.L42:
call clock@PLT
movq %rax, %rsi
movl $1000, %ecx
movq %rbx, %rax
cqto
idivq %rcx
movq %rax, 16(%rsp)
movq %rsi, %rax
subq %r13, %rax
cqto
idivq %rcx
movq %rax, 8(%rsp)
leaq .LC19(%rip), %rsi
leaq .LC20(%rip), %rdi
call fopen@PLT
movq %rax, %r13
addq $4, %r12
movl $0, %ebx
leaq .LC14(%rip), %r14
.L45:
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
movl %ebx, %ecx
movq %r14, %rdx
movl $2, %esi
movq %r13, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addl $1, %ebx
addq $24, %r12
cmpl %r15d, %ebx
jne .L45
jmp .L46
.L69:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC1:
.long -2147483648
.long 0
.long 0
.long 0
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC10:
.long 1062836634
.align 4
.LC11:
.long 1041865112
.align 4
.LC12:
.long 1065353216
.align 4
.LC13:
.long 897988541
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <time.h>
typedef struct vertex vertex;
struct vertex {
unsigned int vertex_id;
float pagerank;
float pagerank_next;
unsigned int n_successors;
vertex ** successors;
};
float abs_float(float in) {
if (in >= 0)
return in;
else
return -in;
}
int main(int argc, char ** args) {
if (argc != 2) {
fprintf(stderr,"Wrong number of args. Provide input graph file.\n");
exit(-1);
}
// Start CPU timer
clock_t cycles_to_build, cycles_to_calc;
// build up the graph
int i,j;
unsigned int n_vertices = 0;
unsigned int vertex_from = 0, vertex_to = 0;
vertex * vertices;
FILE * fp;
if ((fp = fopen(args[1], "r")) == NULL) {
fprintf(stderr,"ERROR: Could not open input file.\n");
exit(-1);
}
// parse input file to count the number of vertices
// expected format: vertex_from vertex_to
while (fscanf(fp, "%u %u", &vertex_from, &vertex_to) != EOF) {
if (vertex_from > n_vertices) {
n_vertices = vertex_from;
}
else if (vertex_to > n_vertices) {
n_vertices = vertex_to;
}
}
n_vertices++;
clock_t start = clock();
// allocate memory for vertices
vertices = (vertex *)malloc(n_vertices*sizeof(vertex));
if (!vertices) {
fprintf(stderr,"Malloc failed for vertices.\n");
exit(-1);
}
memset((void *)vertices, 0, (size_t)(n_vertices*sizeof(vertex)));
// parse input file to count the number of successors of each vertex
fseek(fp, 0L, SEEK_SET);
while (fscanf(fp, "%u %u", &vertex_from, &vertex_to) != EOF) {
vertices[vertex_from].n_successors++;
}
// allocate memory for successor pointers
for (i=0; i<n_vertices; i++) {
vertices[i].vertex_id = i;
if (vertices[i].n_successors > 0) {
vertices[i].successors = (vertex **)malloc(vertices[i].n_successors*sizeof(vertex *));
if (!vertices[i].successors) {
fprintf(stderr,"Malloc failed for successors of vertex %d.\n",i);
exit(-1);
}
memset((void *)vertices[i].successors, 0, (size_t)(vertices[i].n_successors*sizeof(vertex *)));
}
else {
vertices[i].successors = NULL;
}
}
// parse input file to set up the successor pointers
fseek(fp, 0L, SEEK_SET);
while (fscanf(fp, "%d %d", &vertex_from, &vertex_to) != EOF) {
for (i=0; i<vertices[vertex_from].n_successors; i++) {
if (vertices[vertex_from].successors[i] == NULL) {
vertices[vertex_from].successors[i] = &vertices[vertex_to];
break;
}
else if (i==vertices[vertex_from].n_successors-1) {
printf("Setting up the successor pointers of virtex %u failed",vertex_from);
return -1;
}
}
}
fclose(fp);
cycles_to_build = clock() - start;
start = clock();
/* int j; // PRINT THE DATASTRUCTURE
for(i = 0; i < n_vertices; i++) {
printf("Page: %d, Suc: ", (vertices+i)->vertex_id);
for(j = 0; j < (vertices+i)->n_successors; j++) {
printf("%d, ",(vertices+i)->successors[j]->vertex_id);
}
printf("\n");
} */
/*************************************************************************/
// compute the pagerank
unsigned int n_iterations = 24;
float alpha = 0.85;
float eps = 0.000001;
// run on the host
unsigned int i_iteration;
float value, diff;
float pr_dangling_factor = alpha / (float)n_vertices; // pagerank to redistribute from dangling nodes
float pr_dangling;
float pr_random_factor = (1-alpha) / (float)n_vertices; // random portion of the pagerank
float pr_random;
float pr_sum, pr_sum_inv, pr_sum_dangling;
float temp;
// initialization
for (i=0;i<n_vertices;i++) {
vertices[i].pagerank = 1 / (float)n_vertices;
vertices[i].pagerank_next = 0;
}
pr_sum = 0;
pr_sum_dangling = 0;
for (i=0; i<n_vertices; i++) {
pr_sum += vertices[i].pagerank;
if (!vertices[i].n_successors) {
pr_sum_dangling += vertices[i].pagerank;
}
}
i_iteration = 0;
diff = eps+1;
while ( (diff > eps) && (i_iteration < n_iterations) ) { // can do 23 iterations for 1 million nodes
for (i=0;i<n_vertices;i++) {
if (vertices[i].n_successors) {
value = (alpha * vertices[i].pagerank)/vertices[i].n_successors; //value = vote split equally
} else {
value = 0;
}
for (j=0;j<vertices[i].n_successors;j++) { // pagerank_next = sum of votes linking to it
vertices[i].successors[j]->pagerank_next += value;
}
}
// for normalization
pr_sum_inv = 1/pr_sum;
// alpha
pr_dangling = pr_dangling_factor * pr_sum_dangling;
pr_random = pr_random_factor;
pr_sum = 0;
pr_sum_dangling = 0;
diff = 0;
for (i=0;i<n_vertices;i++) {
// update pagerank
temp = vertices[i].pagerank;
/************************************************************************************/
//vertices[i].pagerank = vertices[i].pagerank_next*pr_sum_inv + pr_dangling + pr_random;
vertices[i].pagerank = vertices[i].pagerank_next + pr_dangling + pr_random;
/************************************************************************************/
vertices[i].pagerank_next = 0;
// for normalization in next cycle
pr_sum += vertices[i].pagerank;
if (!vertices[i].n_successors)
pr_sum_dangling += vertices[i].pagerank;
// convergence
diff += abs_float(temp - vertices[i].pagerank);
// printf("prev: %.12f, pr: %.12f\n",temp, vertices[i].pagerank);
}
// printf("Iteration %u:\t diff = %.12f\n", i_iteration, diff);
i_iteration++;
}
/*************************************************************************/
// End CPU Timer
cycles_to_calc = clock() - start;
// Print time
int build_msec = cycles_to_build * 1000 / CLOCKS_PER_SEC;
int calc_msec = cycles_to_calc * 1000 / CLOCKS_PER_SEC;
// print pageranks
FILE *f_result;
f_result=fopen("result_CPU","w");
for (i=0;i<n_vertices;i++) {
fprintf(f_result,"Vertex %u:\tpagerank = %.18f\n", i, vertices[i].pagerank);
}
fclose(f_result);
printf("Time to build: %d seconds, %d milliseconds\n", build_msec/1000, build_msec%1000);
printf("Time to calc: %d seconds, %d milliseconds\n", calc_msec/1000, calc_msec%1000);
printf("iter: %d\n",i_iteration);
printf("Done\n");
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
typedef struct vertex vertex;
struct vertex {
unsigned int vertex_id;
float pagerank;
float pagerank_next;
unsigned int n_successors;
vertex ** successors;
};
float abs_float(float in) {
if (in >= 0)
return in;
else
return -in;
}
int main(int argc, char ** args) {
if (argc != 2) {
fprintf(stderr,"Wrong number of args. Provide input graph file.\n");
exit(-1);
}
// Start CPU timer
clock_t cycles_to_build, cycles_to_calc;
// build up the graph
int i,j;
unsigned int n_vertices = 0;
unsigned int vertex_from = 0, vertex_to = 0;
vertex * vertices;
FILE * fp;
if ((fp = fopen(args[1], "r")) == NULL) {
fprintf(stderr,"ERROR: Could not open input file.\n");
exit(-1);
}
// parse input file to count the number of vertices
// expected format: vertex_from vertex_to
while (fscanf(fp, "%u %u", &vertex_from, &vertex_to) != EOF) {
if (vertex_from > n_vertices) {
n_vertices = vertex_from;
}
else if (vertex_to > n_vertices) {
n_vertices = vertex_to;
}
}
n_vertices++;
clock_t start = clock();
// allocate memory for vertices
vertices = (vertex *)malloc(n_vertices*sizeof(vertex));
if (!vertices) {
fprintf(stderr,"Malloc failed for vertices.\n");
exit(-1);
}
memset((void *)vertices, 0, (size_t)(n_vertices*sizeof(vertex)));
// parse input file to count the number of successors of each vertex
fseek(fp, 0L, SEEK_SET);
while (fscanf(fp, "%u %u", &vertex_from, &vertex_to) != EOF) {
vertices[vertex_from].n_successors++;
}
// allocate memory for successor pointers
for (i=0; i<n_vertices; i++) {
vertices[i].vertex_id = i;
if (vertices[i].n_successors > 0) {
vertices[i].successors = (vertex **)malloc(vertices[i].n_successors*sizeof(vertex *));
if (!vertices[i].successors) {
fprintf(stderr,"Malloc failed for successors of vertex %d.\n",i);
exit(-1);
}
memset((void *)vertices[i].successors, 0, (size_t)(vertices[i].n_successors*sizeof(vertex *)));
}
else {
vertices[i].successors = NULL;
}
}
// parse input file to set up the successor pointers
fseek(fp, 0L, SEEK_SET);
while (fscanf(fp, "%d %d", &vertex_from, &vertex_to) != EOF) {
for (i=0; i<vertices[vertex_from].n_successors; i++) {
if (vertices[vertex_from].successors[i] == NULL) {
vertices[vertex_from].successors[i] = &vertices[vertex_to];
break;
}
else if (i==vertices[vertex_from].n_successors-1) {
printf("Setting up the successor pointers of virtex %u failed",vertex_from);
return -1;
}
}
}
fclose(fp);
cycles_to_build = clock() - start;
start = clock();
/* int j; // PRINT THE DATASTRUCTURE
for(i = 0; i < n_vertices; i++) {
printf("Page: %d, Suc: ", (vertices+i)->vertex_id);
for(j = 0; j < (vertices+i)->n_successors; j++) {
printf("%d, ",(vertices+i)->successors[j]->vertex_id);
}
printf("\n");
} */
/*************************************************************************/
// compute the pagerank
unsigned int n_iterations = 24;
float alpha = 0.85;
float eps = 0.000001;
// run on the host
unsigned int i_iteration;
float value, diff;
float pr_dangling_factor = alpha / (float)n_vertices; // pagerank to redistribute from dangling nodes
float pr_dangling;
float pr_random_factor = (1-alpha) / (float)n_vertices; // random portion of the pagerank
float pr_random;
float pr_sum, pr_sum_inv, pr_sum_dangling;
float temp;
// initialization
for (i=0;i<n_vertices;i++) {
vertices[i].pagerank = 1 / (float)n_vertices;
vertices[i].pagerank_next = 0;
}
pr_sum = 0;
pr_sum_dangling = 0;
for (i=0; i<n_vertices; i++) {
pr_sum += vertices[i].pagerank;
if (!vertices[i].n_successors) {
pr_sum_dangling += vertices[i].pagerank;
}
}
i_iteration = 0;
diff = eps+1;
while ( (diff > eps) && (i_iteration < n_iterations) ) { // can do 23 iterations for 1 million nodes
for (i=0;i<n_vertices;i++) {
if (vertices[i].n_successors) {
value = (alpha * vertices[i].pagerank)/vertices[i].n_successors; //value = vote split equally
} else {
value = 0;
}
for (j=0;j<vertices[i].n_successors;j++) { // pagerank_next = sum of votes linking to it
vertices[i].successors[j]->pagerank_next += value;
}
}
// for normalization
pr_sum_inv = 1/pr_sum;
// alpha
pr_dangling = pr_dangling_factor * pr_sum_dangling;
pr_random = pr_random_factor;
pr_sum = 0;
pr_sum_dangling = 0;
diff = 0;
for (i=0;i<n_vertices;i++) {
// update pagerank
temp = vertices[i].pagerank;
/************************************************************************************/
//vertices[i].pagerank = vertices[i].pagerank_next*pr_sum_inv + pr_dangling + pr_random;
vertices[i].pagerank = vertices[i].pagerank_next + pr_dangling + pr_random;
/************************************************************************************/
vertices[i].pagerank_next = 0;
// for normalization in next cycle
pr_sum += vertices[i].pagerank;
if (!vertices[i].n_successors)
pr_sum_dangling += vertices[i].pagerank;
// convergence
diff += abs_float(temp - vertices[i].pagerank);
// printf("prev: %.12f, pr: %.12f\n",temp, vertices[i].pagerank);
}
// printf("Iteration %u:\t diff = %.12f\n", i_iteration, diff);
i_iteration++;
}
/*************************************************************************/
// End CPU Timer
cycles_to_calc = clock() - start;
// Print time
int build_msec = cycles_to_build * 1000 / CLOCKS_PER_SEC;
int calc_msec = cycles_to_calc * 1000 / CLOCKS_PER_SEC;
// print pageranks
FILE *f_result;
f_result=fopen("result_CPU","w");
for (i=0;i<n_vertices;i++) {
fprintf(f_result,"Vertex %u:\tpagerank = %.18f\n", i, vertices[i].pagerank);
}
fclose(f_result);
printf("Time to build: %d seconds, %d milliseconds\n", build_msec/1000, build_msec%1000);
printf("Time to calc: %d seconds, %d milliseconds\n", calc_msec/1000, calc_msec%1000);
printf("iter: %d\n",i_iteration);
printf("Done\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
typedef struct vertex vertex;
struct vertex {
unsigned int vertex_id;
float pagerank;
float pagerank_next;
unsigned int n_successors;
vertex ** successors;
};
float abs_float(float in) {
if (in >= 0)
return in;
else
return -in;
}
int main(int argc, char ** args) {
if (argc != 2) {
fprintf(stderr,"Wrong number of args. Provide input graph file.\n");
exit(-1);
}
// Start CPU timer
clock_t cycles_to_build, cycles_to_calc;
// build up the graph
int i,j;
unsigned int n_vertices = 0;
unsigned int vertex_from = 0, vertex_to = 0;
vertex * vertices;
FILE * fp;
if ((fp = fopen(args[1], "r")) == NULL) {
fprintf(stderr,"ERROR: Could not open input file.\n");
exit(-1);
}
// parse input file to count the number of vertices
// expected format: vertex_from vertex_to
while (fscanf(fp, "%u %u", &vertex_from, &vertex_to) != EOF) {
if (vertex_from > n_vertices) {
n_vertices = vertex_from;
}
else if (vertex_to > n_vertices) {
n_vertices = vertex_to;
}
}
n_vertices++;
clock_t start = clock();
// allocate memory for vertices
vertices = (vertex *)malloc(n_vertices*sizeof(vertex));
if (!vertices) {
fprintf(stderr,"Malloc failed for vertices.\n");
exit(-1);
}
memset((void *)vertices, 0, (size_t)(n_vertices*sizeof(vertex)));
// parse input file to count the number of successors of each vertex
fseek(fp, 0L, SEEK_SET);
while (fscanf(fp, "%u %u", &vertex_from, &vertex_to) != EOF) {
vertices[vertex_from].n_successors++;
}
// allocate memory for successor pointers
for (i=0; i<n_vertices; i++) {
vertices[i].vertex_id = i;
if (vertices[i].n_successors > 0) {
vertices[i].successors = (vertex **)malloc(vertices[i].n_successors*sizeof(vertex *));
if (!vertices[i].successors) {
fprintf(stderr,"Malloc failed for successors of vertex %d.\n",i);
exit(-1);
}
memset((void *)vertices[i].successors, 0, (size_t)(vertices[i].n_successors*sizeof(vertex *)));
}
else {
vertices[i].successors = NULL;
}
}
// parse input file to set up the successor pointers
fseek(fp, 0L, SEEK_SET);
while (fscanf(fp, "%d %d", &vertex_from, &vertex_to) != EOF) {
for (i=0; i<vertices[vertex_from].n_successors; i++) {
if (vertices[vertex_from].successors[i] == NULL) {
vertices[vertex_from].successors[i] = &vertices[vertex_to];
break;
}
else if (i==vertices[vertex_from].n_successors-1) {
printf("Setting up the successor pointers of virtex %u failed",vertex_from);
return -1;
}
}
}
fclose(fp);
cycles_to_build = clock() - start;
start = clock();
/* int j; // PRINT THE DATASTRUCTURE
for(i = 0; i < n_vertices; i++) {
printf("Page: %d, Suc: ", (vertices+i)->vertex_id);
for(j = 0; j < (vertices+i)->n_successors; j++) {
printf("%d, ",(vertices+i)->successors[j]->vertex_id);
}
printf("\n");
} */
/*************************************************************************/
// compute the pagerank
unsigned int n_iterations = 24;
float alpha = 0.85;
float eps = 0.000001;
// run on the host
unsigned int i_iteration;
float value, diff;
float pr_dangling_factor = alpha / (float)n_vertices; // pagerank to redistribute from dangling nodes
float pr_dangling;
float pr_random_factor = (1-alpha) / (float)n_vertices; // random portion of the pagerank
float pr_random;
float pr_sum, pr_sum_inv, pr_sum_dangling;
float temp;
// initialization
for (i=0;i<n_vertices;i++) {
vertices[i].pagerank = 1 / (float)n_vertices;
vertices[i].pagerank_next = 0;
}
pr_sum = 0;
pr_sum_dangling = 0;
for (i=0; i<n_vertices; i++) {
pr_sum += vertices[i].pagerank;
if (!vertices[i].n_successors) {
pr_sum_dangling += vertices[i].pagerank;
}
}
i_iteration = 0;
diff = eps+1;
while ( (diff > eps) && (i_iteration < n_iterations) ) { // can do 23 iterations for 1 million nodes
for (i=0;i<n_vertices;i++) {
if (vertices[i].n_successors) {
value = (alpha * vertices[i].pagerank)/vertices[i].n_successors; //value = vote split equally
} else {
value = 0;
}
for (j=0;j<vertices[i].n_successors;j++) { // pagerank_next = sum of votes linking to it
vertices[i].successors[j]->pagerank_next += value;
}
}
// for normalization
pr_sum_inv = 1/pr_sum;
// alpha
pr_dangling = pr_dangling_factor * pr_sum_dangling;
pr_random = pr_random_factor;
pr_sum = 0;
pr_sum_dangling = 0;
diff = 0;
for (i=0;i<n_vertices;i++) {
// update pagerank
temp = vertices[i].pagerank;
/************************************************************************************/
//vertices[i].pagerank = vertices[i].pagerank_next*pr_sum_inv + pr_dangling + pr_random;
vertices[i].pagerank = vertices[i].pagerank_next + pr_dangling + pr_random;
/************************************************************************************/
vertices[i].pagerank_next = 0;
// for normalization in next cycle
pr_sum += vertices[i].pagerank;
if (!vertices[i].n_successors)
pr_sum_dangling += vertices[i].pagerank;
// convergence
diff += abs_float(temp - vertices[i].pagerank);
// printf("prev: %.12f, pr: %.12f\n",temp, vertices[i].pagerank);
}
// printf("Iteration %u:\t diff = %.12f\n", i_iteration, diff);
i_iteration++;
}
/*************************************************************************/
// End CPU Timer
cycles_to_calc = clock() - start;
// Print time
int build_msec = cycles_to_build * 1000 / CLOCKS_PER_SEC;
int calc_msec = cycles_to_calc * 1000 / CLOCKS_PER_SEC;
// print pageranks
FILE *f_result;
f_result=fopen("result_CPU","w");
for (i=0;i<n_vertices;i++) {
fprintf(f_result,"Vertex %u:\tpagerank = %.18f\n", i, vertices[i].pagerank);
}
fclose(f_result);
printf("Time to build: %d seconds, %d milliseconds\n", build_msec/1000, build_msec%1000);
printf("Time to calc: %d seconds, %d milliseconds\n", calc_msec/1000, calc_msec%1000);
printf("iter: %d\n",i_iteration);
printf("Done\n");
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
typedef struct vertex vertex;
struct vertex {
unsigned int vertex_id;
float pagerank;
float pagerank_next;
unsigned int n_successors;
vertex ** successors;
};
float abs_float(float in) {
if (in >= 0)
return in;
else
return -in;
}
int main(int argc, char ** args) {
if (argc != 2) {
fprintf(stderr,"Wrong number of args. Provide input graph file.\n");
exit(-1);
}
// Start CPU timer
clock_t cycles_to_build, cycles_to_calc;
// build up the graph
int i,j;
unsigned int n_vertices = 0;
unsigned int vertex_from = 0, vertex_to = 0;
vertex * vertices;
FILE * fp;
if ((fp = fopen(args[1], "r")) == NULL) {
fprintf(stderr,"ERROR: Could not open input file.\n");
exit(-1);
}
// parse input file to count the number of vertices
// expected format: vertex_from vertex_to
while (fscanf(fp, "%u %u", &vertex_from, &vertex_to) != EOF) {
if (vertex_from > n_vertices) {
n_vertices = vertex_from;
}
else if (vertex_to > n_vertices) {
n_vertices = vertex_to;
}
}
n_vertices++;
clock_t start = clock();
// allocate memory for vertices
vertices = (vertex *)malloc(n_vertices*sizeof(vertex));
if (!vertices) {
fprintf(stderr,"Malloc failed for vertices.\n");
exit(-1);
}
memset((void *)vertices, 0, (size_t)(n_vertices*sizeof(vertex)));
// parse input file to count the number of successors of each vertex
fseek(fp, 0L, SEEK_SET);
while (fscanf(fp, "%u %u", &vertex_from, &vertex_to) != EOF) {
vertices[vertex_from].n_successors++;
}
// allocate memory for successor pointers
for (i=0; i<n_vertices; i++) {
vertices[i].vertex_id = i;
if (vertices[i].n_successors > 0) {
vertices[i].successors = (vertex **)malloc(vertices[i].n_successors*sizeof(vertex *));
if (!vertices[i].successors) {
fprintf(stderr,"Malloc failed for successors of vertex %d.\n",i);
exit(-1);
}
memset((void *)vertices[i].successors, 0, (size_t)(vertices[i].n_successors*sizeof(vertex *)));
}
else {
vertices[i].successors = NULL;
}
}
// parse input file to set up the successor pointers
fseek(fp, 0L, SEEK_SET);
while (fscanf(fp, "%d %d", &vertex_from, &vertex_to) != EOF) {
for (i=0; i<vertices[vertex_from].n_successors; i++) {
if (vertices[vertex_from].successors[i] == NULL) {
vertices[vertex_from].successors[i] = &vertices[vertex_to];
break;
}
else if (i==vertices[vertex_from].n_successors-1) {
printf("Setting up the successor pointers of virtex %u failed",vertex_from);
return -1;
}
}
}
fclose(fp);
cycles_to_build = clock() - start;
start = clock();
/* int j; // PRINT THE DATASTRUCTURE
for(i = 0; i < n_vertices; i++) {
printf("Page: %d, Suc: ", (vertices+i)->vertex_id);
for(j = 0; j < (vertices+i)->n_successors; j++) {
printf("%d, ",(vertices+i)->successors[j]->vertex_id);
}
printf("\n");
} */
/*************************************************************************/
// compute the pagerank
unsigned int n_iterations = 24;
float alpha = 0.85;
float eps = 0.000001;
// run on the host
unsigned int i_iteration;
float value, diff;
float pr_dangling_factor = alpha / (float)n_vertices; // pagerank to redistribute from dangling nodes
float pr_dangling;
float pr_random_factor = (1-alpha) / (float)n_vertices; // random portion of the pagerank
float pr_random;
float pr_sum, pr_sum_inv, pr_sum_dangling;
float temp;
// initialization
for (i=0;i<n_vertices;i++) {
vertices[i].pagerank = 1 / (float)n_vertices;
vertices[i].pagerank_next = 0;
}
pr_sum = 0;
pr_sum_dangling = 0;
for (i=0; i<n_vertices; i++) {
pr_sum += vertices[i].pagerank;
if (!vertices[i].n_successors) {
pr_sum_dangling += vertices[i].pagerank;
}
}
i_iteration = 0;
diff = eps+1;
while ( (diff > eps) && (i_iteration < n_iterations) ) { // can do 23 iterations for 1 million nodes
for (i=0;i<n_vertices;i++) {
if (vertices[i].n_successors) {
value = (alpha * vertices[i].pagerank)/vertices[i].n_successors; //value = vote split equally
} else {
value = 0;
}
for (j=0;j<vertices[i].n_successors;j++) { // pagerank_next = sum of votes linking to it
vertices[i].successors[j]->pagerank_next += value;
}
}
// for normalization
pr_sum_inv = 1/pr_sum;
// alpha
pr_dangling = pr_dangling_factor * pr_sum_dangling;
pr_random = pr_random_factor;
pr_sum = 0;
pr_sum_dangling = 0;
diff = 0;
for (i=0;i<n_vertices;i++) {
// update pagerank
temp = vertices[i].pagerank;
/************************************************************************************/
//vertices[i].pagerank = vertices[i].pagerank_next*pr_sum_inv + pr_dangling + pr_random;
vertices[i].pagerank = vertices[i].pagerank_next + pr_dangling + pr_random;
/************************************************************************************/
vertices[i].pagerank_next = 0;
// for normalization in next cycle
pr_sum += vertices[i].pagerank;
if (!vertices[i].n_successors)
pr_sum_dangling += vertices[i].pagerank;
// convergence
diff += abs_float(temp - vertices[i].pagerank);
// printf("prev: %.12f, pr: %.12f\n",temp, vertices[i].pagerank);
}
// printf("Iteration %u:\t diff = %.12f\n", i_iteration, diff);
i_iteration++;
}
/*************************************************************************/
// End CPU Timer
cycles_to_calc = clock() - start;
// Print time
int build_msec = cycles_to_build * 1000 / CLOCKS_PER_SEC;
int calc_msec = cycles_to_calc * 1000 / CLOCKS_PER_SEC;
// print pageranks
FILE *f_result;
f_result=fopen("result_CPU","w");
for (i=0;i<n_vertices;i++) {
fprintf(f_result,"Vertex %u:\tpagerank = %.18f\n", i, vertices[i].pagerank);
}
fclose(f_result);
printf("Time to build: %d seconds, %d milliseconds\n", build_msec/1000, build_msec%1000);
printf("Time to calc: %d seconds, %d milliseconds\n", calc_msec/1000, calc_msec%1000);
printf("iter: %d\n",i_iteration);
printf("Done\n");
return 0;
} | .text
.file "pagerank_CPU_benchmark.hip"
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z9abs_floatf
.LCPI0_0:
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.text
.globl _Z9abs_floatf
.p2align 4, 0x90
.type _Z9abs_floatf,@function
_Z9abs_floatf: # @_Z9abs_floatf
.cfi_startproc
# %bb.0:
movaps .LCPI0_0(%rip), %xmm2 # xmm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
xorps %xmm0, %xmm2
movaps %xmm2, %xmm1
cmpnless %xmm0, %xmm1
andps %xmm1, %xmm2
andnps %xmm0, %xmm1
orps %xmm2, %xmm1
movaps %xmm1, %xmm0
retq
.Lfunc_end0:
.size _Z9abs_floatf, .Lfunc_end0-_Z9abs_floatf
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3f59999a # float 0.850000023
.LCPI1_1:
.long 0x3e199998 # float 0.149999976
.LCPI1_2:
.long 0x3f800000 # float 1
.LCPI1_3:
.long 0x80000000 # float -0
.LCPI1_5:
.long 0x358637bd # float 9.99999997E-7
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_4:
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB1_1
# %bb.3:
movl $0, (%rsp)
movl $0, 4(%rsp)
movq 8(%rsi), %rdi
movl $.L.str.1, %esi
callq fopen
testq %rax, %rax
je .LBB1_6
# %bb.4: # %.preheader177
movq %rax, %rbp
movq %rsp, %rdx
leaq 4(%rsp), %rcx
movl $.L.str.3, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
je .LBB1_5
# %bb.7: # %.lr.ph.preheader
movq %rsp, %rbx
leaq 4(%rsp), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_8: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rsp), %eax
movl 4(%rsp), %ecx
cmpl %r15d, %ecx
cmovbel %r15d, %ecx
cmpl %r15d, %eax
movl %ecx, %r15d
cmoval %eax, %r15d
movl $.L.str.3, %esi
movq %rbp, %rdi
movq %rbx, %rdx
movq %r14, %rcx
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
jne .LBB1_8
# %bb.9: # %._crit_edge.loopexit
incl %r15d
jmp .LBB1_10
.LBB1_5:
movl $1, %r15d
.LBB1_10: # %._crit_edge
callq clock
movq %rax, 8(%rsp) # 8-byte Spill
movl %r15d, %r14d
leaq (,%r14,8), %rax
leaq (%rax,%rax,2), %r12
movq %r12, %rdi
callq malloc
testq %rax, %rax
je .LBB1_11
# %bb.12:
movq %rax, %rbx
movq %rax, %rdi
xorl %esi, %esi
movq %r12, %rdx
callq memset@PLT
movq %rbp, %rdi
xorl %esi, %esi
xorl %edx, %edx
callq fseek
movq %rsp, %rdx
leaq 4(%rsp), %rcx
movl $.L.str.3, %esi
movq %rbp, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
je .LBB1_15
# %bb.13:
movq %rsp, %r12
leaq 4(%rsp), %r13
.p2align 4, 0x90
.LBB1_14: # %.lr.ph187
# =>This Inner Loop Header: Depth=1
movl (%rsp), %eax
leaq (%rax,%rax,2), %rax
incl 12(%rbx,%rax,8)
movl $.L.str.3, %esi
movq %rbp, %rdi
movq %r12, %rdx
movq %r13, %rcx
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
jne .LBB1_14
.LBB1_15: # %.preheader176
movq %rbp, 16(%rsp) # 8-byte Spill
testl %r15d, %r15d
je .LBB1_22
# %bb.16: # %.lr.ph189.preheader
leaq 16(%rbx), %rbp
xorl %r12d, %r12d
jmp .LBB1_17
.p2align 4, 0x90
.LBB1_20: # in Loop: Header=BB1_17 Depth=1
movq $0, (%rbp)
.LBB1_21: # in Loop: Header=BB1_17 Depth=1
incq %r12
addq $24, %rbp
cmpq %r12, %r14
je .LBB1_22
.LBB1_17: # %.lr.ph189
# =>This Inner Loop Header: Depth=1
movl %r12d, -16(%rbp)
movl -4(%rbp), %r13d
testq %r13, %r13
je .LBB1_20
# %bb.18: # in Loop: Header=BB1_17 Depth=1
shlq $3, %r13
movq %r13, %rdi
callq malloc
movq %rax, (%rbp)
testq %rax, %rax
je .LBB1_64
# %bb.19: # in Loop: Header=BB1_17 Depth=1
movq %rax, %rdi
xorl %esi, %esi
movq %r13, %rdx
callq memset@PLT
jmp .LBB1_21
.LBB1_22: # %._crit_edge190
movq 16(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdi
xorl %esi, %esi
xorl %edx, %edx
callq fseek
movq %rsp, %rdx
leaq 4(%rsp), %rcx
movl $.L.str.6, %esi
movq %rbp, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
je .LBB1_30
# %bb.23: # %.preheader175.preheader
movq %rsp, %r12
leaq 4(%rsp), %r13
jmp .LBB1_24
.p2align 4, 0x90
.LBB1_26: # in Loop: Header=BB1_24 Depth=1
xorl %edx, %edx
.LBB1_28: # %._crit_edge280
# in Loop: Header=BB1_24 Depth=1
movl 4(%rsp), %ecx
leaq (%rcx,%rcx,2), %rcx
leaq (%rbx,%rcx,8), %rcx
movq %rcx, (%rax,%rdx,8)
.LBB1_29: # %.loopexit
# in Loop: Header=BB1_24 Depth=1
movl $.L.str.6, %esi
movq %rbp, %rdi
movq %r12, %rdx
movq %r13, %rcx
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
je .LBB1_30
.LBB1_24: # %.preheader175
# =>This Loop Header: Depth=1
# Child Loop BB1_33 Depth 2
movl (%rsp), %esi
leaq (%rsi,%rsi,2), %rax
movl 12(%rbx,%rax,8), %ecx
testl %ecx, %ecx
je .LBB1_29
# %bb.25: # %.lr.ph193
# in Loop: Header=BB1_24 Depth=1
movq 16(%rbx,%rax,8), %rax
cmpq $0, (%rax)
je .LBB1_26
# %bb.32: # %.lr.ph279.preheader
# in Loop: Header=BB1_24 Depth=1
decl %ecx
xorl %edi, %edi
.p2align 4, 0x90
.LBB1_33: # %.lr.ph279
# Parent Loop BB1_24 Depth=1
# => This Inner Loop Header: Depth=2
cmpq %rdi, %rcx
je .LBB1_34
# %bb.27: # in Loop: Header=BB1_33 Depth=2
leaq 1(%rdi), %rdx
cmpq $0, 8(%rax,%rdi,8)
movq %rdx, %rdi
jne .LBB1_33
jmp .LBB1_28
.LBB1_34:
movl $.L.str.7, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
movl $-1, %ebx
jmp .LBB1_63
.LBB1_30: # %._crit_edge195
movq %rbp, %rdi
callq fclose
callq clock
movq %rax, %r13
callq clock
cvtsi2ss %r14, %xmm4
movq %rax, %r12
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
testl %r15d, %r15d
je .LBB1_31
# %bb.35: # %.lr.ph198
movss .LCPI1_2(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
divss %xmm4, %xmm2
leaq (,%r14,8), %rax
leaq (%rax,%rax,2), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_36: # =>This Inner Loop Header: Depth=1
movss %xmm2, 4(%rbx,%rcx)
movl $0, 8(%rbx,%rcx)
addq $24, %rcx
cmpq %rcx, %rax
jne .LBB1_36
# %bb.37: # %.lr.ph201.preheader
leaq (,%r14,8), %rax
leaq (%rax,%rax,2), %rax
xorps %xmm2, %xmm2
xorl %ecx, %ecx
jmp .LBB1_38
.p2align 4, 0x90
.LBB1_40: # in Loop: Header=BB1_38 Depth=1
addq $24, %rcx
cmpq %rcx, %rax
je .LBB1_41
.LBB1_38: # %.lr.ph201
# =>This Inner Loop Header: Depth=1
cmpl $0, 12(%rbx,%rcx)
jne .LBB1_40
# %bb.39: # in Loop: Header=BB1_38 Depth=1
addss 4(%rbx,%rcx), %xmm2
jmp .LBB1_40
.LBB1_31:
xorps %xmm2, %xmm2
.LBB1_41: # %.preheader173
subq 8(%rsp), %r13 # 8-byte Folded Reload
movaps %xmm0, %xmm3
divss %xmm4, %xmm3
divss %xmm4, %xmm1
leaq (,%r14,8), %rax
leaq (%rax,%rax,2), %rax
xorl %ecx, %ecx
movss .LCPI1_5(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
movss .LCPI1_3(%rip), %xmm5 # xmm5 = mem[0],zero,zero,zero
movaps .LCPI1_4(%rip), %xmm6 # xmm6 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
.p2align 4, 0x90
.LBB1_42: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_44 Depth 2
# Child Loop BB1_49 Depth 3
# Child Loop BB1_54 Depth 2
testl %r15d, %r15d
je .LBB1_51
# %bb.43: # %.lr.ph208.preheader
# in Loop: Header=BB1_42 Depth=1
xorl %edx, %edx
jmp .LBB1_44
.p2align 4, 0x90
.LBB1_50: # %._crit_edge206
# in Loop: Header=BB1_44 Depth=2
incq %rdx
cmpq %r14, %rdx
je .LBB1_51
.LBB1_44: # %.lr.ph208
# Parent Loop BB1_42 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_49 Depth 3
leaq (%rdx,%rdx,2), %rdi
movl 12(%rbx,%rdi,8), %esi
testq %rsi, %rsi
je .LBB1_45
# %bb.46: # in Loop: Header=BB1_44 Depth=2
movss 4(%rbx,%rdi,8), %xmm7 # xmm7 = mem[0],zero,zero,zero
mulss %xmm0, %xmm7
xorps %xmm8, %xmm8
cvtsi2ss %rsi, %xmm8
divss %xmm8, %xmm7
testq %rsi, %rsi
jne .LBB1_48
jmp .LBB1_50
.p2align 4, 0x90
.LBB1_45: # in Loop: Header=BB1_44 Depth=2
xorps %xmm7, %xmm7
testq %rsi, %rsi
je .LBB1_50
.LBB1_48: # %.lr.ph205
# in Loop: Header=BB1_44 Depth=2
movq 16(%rbx,%rdi,8), %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB1_49: # Parent Loop BB1_42 Depth=1
# Parent Loop BB1_44 Depth=2
# => This Inner Loop Header: Depth=3
movq (%rdi,%r8,8), %r9
movss 8(%r9), %xmm8 # xmm8 = mem[0],zero,zero,zero
addss %xmm7, %xmm8
movss %xmm8, 8(%r9)
incq %r8
cmpq %r8, %rsi
jne .LBB1_49
jmp .LBB1_50
.p2align 4, 0x90
.LBB1_51: # %._crit_edge209
# in Loop: Header=BB1_42 Depth=1
testl %r15d, %r15d
je .LBB1_52
# %bb.53: # %.lr.ph214.preheader
# in Loop: Header=BB1_42 Depth=1
movaps %xmm2, %xmm8
mulss %xmm3, %xmm8
xorps %xmm2, %xmm2
xorl %edx, %edx
xorps %xmm7, %xmm7
jmp .LBB1_54
.p2align 4, 0x90
.LBB1_56: # %.lr.ph214
# in Loop: Header=BB1_54 Depth=2
addss %xmm11, %xmm2
subss %xmm10, %xmm9
movaps %xmm9, %xmm10
xorps %xmm6, %xmm10
movaps %xmm10, %xmm11
cmpnless %xmm9, %xmm11
andps %xmm11, %xmm10
andnps %xmm9, %xmm11
orps %xmm10, %xmm11
addss %xmm11, %xmm7
addq $24, %rdx
cmpq %rdx, %rax
je .LBB1_57
.LBB1_54: # %.lr.ph214
# Parent Loop BB1_42 Depth=1
# => This Inner Loop Header: Depth=2
movss 4(%rbx,%rdx), %xmm9 # xmm9 = mem[0],zero,zero,zero
movss 8(%rbx,%rdx), %xmm10 # xmm10 = mem[0],zero,zero,zero
addss %xmm8, %xmm10
addss %xmm1, %xmm10
movss %xmm10, 4(%rbx,%rdx)
movl $0, 8(%rbx,%rdx)
cmpl $0, 12(%rbx,%rdx)
movaps %xmm10, %xmm11
je .LBB1_56
# %bb.55: # %.lr.ph214
# in Loop: Header=BB1_54 Depth=2
movaps %xmm5, %xmm11
jmp .LBB1_56
.p2align 4, 0x90
.LBB1_52: # in Loop: Header=BB1_42 Depth=1
xorps %xmm7, %xmm7
xorps %xmm2, %xmm2
.LBB1_57: # %._crit_edge215
# in Loop: Header=BB1_42 Depth=1
leal 1(%rcx), %ebp
ucomiss %xmm4, %xmm7
jbe .LBB1_59
# %bb.58: # %._crit_edge215
# in Loop: Header=BB1_42 Depth=1
cmpl $23, %ecx
movl %ebp, %ecx
jb .LBB1_42
.LBB1_59:
callq clock
movq %rax, %rcx
subq %r12, %rcx
movabsq $2361183241434822607, %rsi # imm = 0x20C49BA5E353F7CF
movq %r13, %rax
imulq %rsi
movq %rdx, %rax
shrq $63, %rax
shrq $7, %rdx
addl %eax, %edx
movq %rdx, 8(%rsp) # 8-byte Spill
movq %rcx, %rax
imulq %rsi
movq %rdx, %rax
shrq $63, %rax
shrq $7, %rdx
addl %eax, %edx
movq %rdx, 16(%rsp) # 8-byte Spill
movl $.L.str.8, %edi
movl $.L.str.9, %esi
callq fopen
movq %rax, %r12
testl %r15d, %r15d
je .LBB1_62
# %bb.60: # %.lr.ph222.preheader
addq $4, %rbx
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_61: # %.lr.ph222
# =>This Inner Loop Header: Depth=1
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.10, %esi
movq %r12, %rdi
movl %r13d, %edx
movb $1, %al
callq fprintf
incq %r13
addq $24, %rbx
cmpq %r13, %r14
jne .LBB1_61
.LBB1_62: # %._crit_edge223
movq %r12, %rdi
callq fclose
movslq 8(%rsp), %rdx # 4-byte Folded Reload
imulq $274877907, %rdx, %rsi # imm = 0x10624DD3
movq %rsi, %rax
shrq $63, %rax
sarq $38, %rsi
addl %eax, %esi
imull $1000, %esi, %eax # imm = 0x3E8
subl %eax, %edx
xorl %ebx, %ebx
movl $.L.str.11, %edi
# kill: def $esi killed $esi killed $rsi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
movslq 16(%rsp), %rdx # 4-byte Folded Reload
imulq $274877907, %rdx, %rsi # imm = 0x10624DD3
movq %rsi, %rax
shrq $63, %rax
sarq $38, %rsi
addl %eax, %esi
imull $1000, %esi, %eax # imm = 0x3E8
subl %eax, %edx
movl $.L.str.12, %edi
# kill: def $esi killed $esi killed $rsi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
movl $.L.str.13, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
callq puts@PLT
.LBB1_63:
movl %ebx, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_64:
.cfi_def_cfa_offset 80
movq stderr(%rip), %rdi
movl $.L.str.5, %esi
movl %r12d, %edx
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.LBB1_1:
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $48, %esi
jmp .LBB1_2
.LBB1_6:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $34, %esi
jmp .LBB1_2
.LBB1_11:
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
movl $28, %esi
.LBB1_2:
movl $1, %edx
callq fwrite@PLT
movl $-1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Wrong number of args. Provide input graph file.\n"
.size .L.str, 49
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "ERROR: Could not open input file.\n"
.size .L.str.2, 35
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%u %u"
.size .L.str.3, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Malloc failed for vertices.\n"
.size .L.str.4, 29
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Malloc failed for successors of vertex %d.\n"
.size .L.str.5, 44
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d %d"
.size .L.str.6, 6
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Setting up the successor pointers of virtex %u failed"
.size .L.str.7, 54
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "result_CPU"
.size .L.str.8, 11
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "w"
.size .L.str.9, 2
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Vertex %u:\tpagerank = %.18f\n"
.size .L.str.10, 29
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Time to build: %d seconds, %d milliseconds\n"
.size .L.str.11, 44
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Time to calc: %d seconds, %d milliseconds\n"
.size .L.str.12, 43
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "iter: %d\n"
.size .L.str.13, 10
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Done"
.size .Lstr, 5
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017f6e6_00000000-6_pagerank_CPU_benchmark.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9abs_floatf
.type _Z9abs_floatf, @function
_Z9abs_floatf:
.LFB2057:
.cfi_startproc
endbr64
pxor %xmm1, %xmm1
comiss %xmm1, %xmm0
jb .L5
.L4:
ret
.L5:
xorps .LC1(%rip), %xmm0
ret
.cfi_endproc
.LFE2057:
.size _Z9abs_floatf, .-_Z9abs_floatf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Wrong number of args. Provide input graph file.\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "r"
.section .rodata.str1.8
.align 8
.LC4:
.string "ERROR: Could not open input file.\n"
.section .rodata.str1.1
.LC5:
.string "%u %u"
.LC6:
.string "Malloc failed for vertices.\n"
.section .rodata.str1.8
.align 8
.LC7:
.string "Malloc failed for successors of vertex %d.\n"
.align 8
.LC8:
.string "Setting up the successor pointers of virtex %u failed"
.section .rodata.str1.1
.LC9:
.string "%d %d"
.LC14:
.string "Vertex %u:\tpagerank = %.18f\n"
.section .rodata.str1.8
.align 8
.LC15:
.string "Time to build: %d seconds, %d milliseconds\n"
.align 8
.LC16:
.string "Time to calc: %d seconds, %d milliseconds\n"
.section .rodata.str1.1
.LC17:
.string "iter: %d\n"
.LC18:
.string "Done\n"
.LC19:
.string "w"
.LC20:
.string "result_CPU"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jne .L61
movl $0, 32(%rsp)
movl $0, 36(%rsp)
movq 8(%rsi), %rdi
leaq .LC3(%rip), %rsi
call fopen@PLT
movq %rax, %r13
testq %rax, %rax
je .L62
movl $0, %r14d
leaq .LC5(%rip), %rbx
jmp .L8
.L61:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L62:
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L9:
movl %eax, %r14d
.L8:
leaq 36(%rsp), %rcx
leaq 32(%rsp), %rdx
movq %rbx, %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $-1, %eax
je .L63
movl 32(%rsp), %eax
cmpl %eax, %r14d
jb .L9
movl 36(%rsp), %eax
cmpl %eax, %r14d
cmovnb %r14d, %eax
jmp .L9
.L63:
leal 1(%r14), %r15d
call clock@PLT
movq %rax, 24(%rsp)
movl %r15d, %eax
leaq (%rax,%rax,2), %rbx
salq $3, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
testq %rax, %rax
je .L64
movq %rbx, %rcx
movq %rbx, %rdx
movl $0, %esi
movq %rax, %rdi
call __memset_chk@PLT
movl $0, %edx
movl $0, %esi
movq %r13, %rdi
call fseek@PLT
leaq .LC5(%rip), %rbx
jmp .L12
.L64:
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L13:
movl 32(%rsp), %eax
leaq (%rax,%rax,2), %rax
addl $1, 12(%r12,%rax,8)
.L12:
leaq 36(%rsp), %rcx
leaq 32(%rsp), %rdx
movq %rbx, %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl %eax, 16(%rsp)
cmpl $-1, %eax
jne .L13
testl %r15d, %r15d
je .L14
movq %r12, %rbx
movl $0, %ebp
jmp .L18
.L66:
movl %eax, %eax
salq $3, %rax
movq %rax, 8(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %rdi
movq %rax, 16(%rbx)
testq %rax, %rax
je .L65
movq 8(%rsp), %rcx
movq %rcx, %rdx
movl $0, %esi
call __memset_chk@PLT
.L17:
addl $1, %ebp
addq $24, %rbx
cmpl %r15d, %ebp
je .L14
.L18:
movl %ebp, (%rbx)
movl 12(%rbx), %eax
testl %eax, %eax
jne .L66
movq $0, 16(%rbx)
jmp .L17
.L65:
movl %ebp, %ecx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L14:
movl $0, %edx
movl $0, %esi
movq %r13, %rdi
call fseek@PLT
leaq .LC9(%rip), %rbx
.L58:
leaq 36(%rsp), %rcx
leaq 32(%rsp), %rdx
movq %rbx, %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $-1, %eax
je .L25
movl 32(%rsp), %esi
movl %esi, %eax
leaq (%rax,%rax,2), %rax
leaq (%r12,%rax,8), %rax
movl 12(%rax), %edx
testl %edx, %edx
je .L58
movq 16(%rax), %rax
movl %edx, %ecx
leaq (%rax,%rcx,8), %rcx
leal -1(%rdx), %edx
leaq (%rax,%rdx,8), %rdx
.L23:
cmpq $0, (%rax)
je .L67
cmpq %rdx, %rax
je .L68
addq $8, %rax
cmpq %rcx, %rax
jne .L23
jmp .L58
.L67:
movl 36(%rsp), %edx
leaq (%rdx,%rdx,2), %rdx
leaq (%r12,%rdx,8), %rdx
movq %rdx, (%rax)
jmp .L58
.L68:
movl %esi, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L6:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L69
movl 16(%rsp), %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movq %r13, %rdi
call fclose@PLT
call clock@PLT
movq 24(%rsp), %rbx
subq %rbx, %rax
movq %rax, %rbx
call clock@PLT
movq %rax, %r13
movl %r15d, %eax
pxor %xmm1, %xmm1
cvtsi2ssq %rax, %xmm1
movss .LC10(%rip), %xmm9
divss %xmm1, %xmm9
movss .LC11(%rip), %xmm5
divss %xmm1, %xmm5
testl %r15d, %r15d
je .L49
movss .LC12(%rip), %xmm0
divss %xmm1, %xmm0
leaq 4(%r12), %rdx
movl %r14d, %eax
imulq $24, %rax, %rax
leaq 28(%r12,%rax), %rcx
movq %rdx, %rax
.L30:
movss %xmm0, (%rax)
movl $0x00000000, 4(%rax)
addq $24, %rax
cmpq %rcx, %rax
jne .L30
pxor %xmm3, %xmm3
jmp .L32
.L31:
addq $24, %rdx
cmpq %rcx, %rdx
je .L29
.L32:
cmpl $0, 8(%rdx)
jne .L31
addss (%rdx), %xmm3
jmp .L31
.L49:
pxor %xmm3, %xmm3
.L29:
movl %r14d, %eax
imulq $24, %rax, %rax
leaq 28(%r12,%rax), %r8
movl $0, %ebp
movss .LC10(%rip), %xmm7
pxor %xmm6, %xmm6
movss .LC1(%rip), %xmm8
jmp .L33
.L71:
movaps %xmm7, %xmm1
mulss (%rdi), %xmm1
movl %eax, %eax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss %xmm0, %xmm1
movl $0, %eax
.L37:
movq 12(%rcx), %rdx
movq (%rdx,%rax,8), %rdx
movaps %xmm1, %xmm0
addss 8(%rdx), %xmm0
movss %xmm0, 8(%rdx)
addq $1, %rax
cmpl 8(%rcx), %eax
jb .L37
.L34:
addq $24, %rdi
cmpq %rdi, %r8
je .L70
.L38:
movq %rdi, %rcx
movl 8(%rdi), %eax
testl %eax, %eax
je .L34
jmp .L71
.L70:
mulss %xmm9, %xmm3
movaps %xmm3, %xmm4
pxor %xmm3, %xmm3
movaps %xmm3, %xmm2
jmp .L41
.L39:
subss %xmm1, %xmm0
comiss %xmm6, %xmm0
jb .L72
.L40:
addss %xmm0, %xmm2
addq $24, %rsi
cmpq %rsi, %r8
je .L73
.L41:
movss (%rsi), %xmm0
movaps %xmm4, %xmm1
addss 4(%rsi), %xmm1
addss %xmm5, %xmm1
movss %xmm1, (%rsi)
movl $0x00000000, 4(%rsi)
cmpl $0, 8(%rsi)
jne .L39
addss %xmm1, %xmm3
jmp .L39
.L72:
xorps %xmm8, %xmm0
jmp .L40
.L73:
addl $1, %ebp
comiss .LC13(%rip), %xmm2
jbe .L42
cmpl $23, %ebp
ja .L42
.L33:
testl %r15d, %r15d
je .L74
leaq 4(%r12), %rsi
movq %rsi, %rdi
jmp .L38
.L74:
addl $1, %ebp
call clock@PLT
movq %rax, %rsi
movl $1000, %ecx
movq %rbx, %rax
cqto
idivq %rcx
movq %rax, 16(%rsp)
movq %rsi, %rax
subq %r13, %rax
cqto
idivq %rcx
movq %rax, 8(%rsp)
leaq .LC19(%rip), %rsi
leaq .LC20(%rip), %rdi
call fopen@PLT
movq %rax, %r13
.L46:
movq %r13, %rdi
call fclose@PLT
movl $1000, %ebx
movl 16(%rsp), %eax
cltd
idivl %ebx
movl %edx, %ecx
movl %eax, %edx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 8(%rsp), %eax
cltd
idivl %ebx
movl %edx, %ecx
movl %eax, %edx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %edx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, 16(%rsp)
jmp .L6
.L42:
call clock@PLT
movq %rax, %rsi
movl $1000, %ecx
movq %rbx, %rax
cqto
idivq %rcx
movq %rax, 16(%rsp)
movq %rsi, %rax
subq %r13, %rax
cqto
idivq %rcx
movq %rax, 8(%rsp)
leaq .LC19(%rip), %rsi
leaq .LC20(%rip), %rdi
call fopen@PLT
movq %rax, %r13
addq $4, %r12
movl $0, %ebx
leaq .LC14(%rip), %r14
.L45:
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
movl %ebx, %ecx
movq %r14, %rdx
movl $2, %esi
movq %r13, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addl $1, %ebx
addq $24, %r12
cmpl %r15d, %ebx
jne .L45
jmp .L46
.L69:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC1:
.long -2147483648
.long 0
.long 0
.long 0
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC10:
.long 1062836634
.align 4
.LC11:
.long 1041865112
.align 4
.LC12:
.long 1065353216
.align 4
.LC13:
.long 897988541
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "pagerank_CPU_benchmark.hip"
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z9abs_floatf
.LCPI0_0:
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.text
.globl _Z9abs_floatf
.p2align 4, 0x90
.type _Z9abs_floatf,@function
_Z9abs_floatf: # @_Z9abs_floatf
.cfi_startproc
# %bb.0:
movaps .LCPI0_0(%rip), %xmm2 # xmm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
xorps %xmm0, %xmm2
movaps %xmm2, %xmm1
cmpnless %xmm0, %xmm1
andps %xmm1, %xmm2
andnps %xmm0, %xmm1
orps %xmm2, %xmm1
movaps %xmm1, %xmm0
retq
.Lfunc_end0:
.size _Z9abs_floatf, .Lfunc_end0-_Z9abs_floatf
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3f59999a # float 0.850000023
.LCPI1_1:
.long 0x3e199998 # float 0.149999976
.LCPI1_2:
.long 0x3f800000 # float 1
.LCPI1_3:
.long 0x80000000 # float -0
.LCPI1_5:
.long 0x358637bd # float 9.99999997E-7
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_4:
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB1_1
# %bb.3:
movl $0, (%rsp)
movl $0, 4(%rsp)
movq 8(%rsi), %rdi
movl $.L.str.1, %esi
callq fopen
testq %rax, %rax
je .LBB1_6
# %bb.4: # %.preheader177
movq %rax, %rbp
movq %rsp, %rdx
leaq 4(%rsp), %rcx
movl $.L.str.3, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
je .LBB1_5
# %bb.7: # %.lr.ph.preheader
movq %rsp, %rbx
leaq 4(%rsp), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_8: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rsp), %eax
movl 4(%rsp), %ecx
cmpl %r15d, %ecx
cmovbel %r15d, %ecx
cmpl %r15d, %eax
movl %ecx, %r15d
cmoval %eax, %r15d
movl $.L.str.3, %esi
movq %rbp, %rdi
movq %rbx, %rdx
movq %r14, %rcx
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
jne .LBB1_8
# %bb.9: # %._crit_edge.loopexit
incl %r15d
jmp .LBB1_10
.LBB1_5:
movl $1, %r15d
.LBB1_10: # %._crit_edge
callq clock
movq %rax, 8(%rsp) # 8-byte Spill
movl %r15d, %r14d
leaq (,%r14,8), %rax
leaq (%rax,%rax,2), %r12
movq %r12, %rdi
callq malloc
testq %rax, %rax
je .LBB1_11
# %bb.12:
movq %rax, %rbx
movq %rax, %rdi
xorl %esi, %esi
movq %r12, %rdx
callq memset@PLT
movq %rbp, %rdi
xorl %esi, %esi
xorl %edx, %edx
callq fseek
movq %rsp, %rdx
leaq 4(%rsp), %rcx
movl $.L.str.3, %esi
movq %rbp, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
je .LBB1_15
# %bb.13:
movq %rsp, %r12
leaq 4(%rsp), %r13
.p2align 4, 0x90
.LBB1_14: # %.lr.ph187
# =>This Inner Loop Header: Depth=1
movl (%rsp), %eax
leaq (%rax,%rax,2), %rax
incl 12(%rbx,%rax,8)
movl $.L.str.3, %esi
movq %rbp, %rdi
movq %r12, %rdx
movq %r13, %rcx
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
jne .LBB1_14
.LBB1_15: # %.preheader176
movq %rbp, 16(%rsp) # 8-byte Spill
testl %r15d, %r15d
je .LBB1_22
# %bb.16: # %.lr.ph189.preheader
leaq 16(%rbx), %rbp
xorl %r12d, %r12d
jmp .LBB1_17
.p2align 4, 0x90
.LBB1_20: # in Loop: Header=BB1_17 Depth=1
movq $0, (%rbp)
.LBB1_21: # in Loop: Header=BB1_17 Depth=1
incq %r12
addq $24, %rbp
cmpq %r12, %r14
je .LBB1_22
.LBB1_17: # %.lr.ph189
# =>This Inner Loop Header: Depth=1
movl %r12d, -16(%rbp)
movl -4(%rbp), %r13d
testq %r13, %r13
je .LBB1_20
# %bb.18: # in Loop: Header=BB1_17 Depth=1
shlq $3, %r13
movq %r13, %rdi
callq malloc
movq %rax, (%rbp)
testq %rax, %rax
je .LBB1_64
# %bb.19: # in Loop: Header=BB1_17 Depth=1
movq %rax, %rdi
xorl %esi, %esi
movq %r13, %rdx
callq memset@PLT
jmp .LBB1_21
.LBB1_22: # %._crit_edge190
movq 16(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdi
xorl %esi, %esi
xorl %edx, %edx
callq fseek
movq %rsp, %rdx
leaq 4(%rsp), %rcx
movl $.L.str.6, %esi
movq %rbp, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
je .LBB1_30
# %bb.23: # %.preheader175.preheader
movq %rsp, %r12
leaq 4(%rsp), %r13
jmp .LBB1_24
.p2align 4, 0x90
.LBB1_26: # in Loop: Header=BB1_24 Depth=1
xorl %edx, %edx
.LBB1_28: # %._crit_edge280
# in Loop: Header=BB1_24 Depth=1
movl 4(%rsp), %ecx
leaq (%rcx,%rcx,2), %rcx
leaq (%rbx,%rcx,8), %rcx
movq %rcx, (%rax,%rdx,8)
.LBB1_29: # %.loopexit
# in Loop: Header=BB1_24 Depth=1
movl $.L.str.6, %esi
movq %rbp, %rdi
movq %r12, %rdx
movq %r13, %rcx
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
je .LBB1_30
.LBB1_24: # %.preheader175
# =>This Loop Header: Depth=1
# Child Loop BB1_33 Depth 2
movl (%rsp), %esi
leaq (%rsi,%rsi,2), %rax
movl 12(%rbx,%rax,8), %ecx
testl %ecx, %ecx
je .LBB1_29
# %bb.25: # %.lr.ph193
# in Loop: Header=BB1_24 Depth=1
movq 16(%rbx,%rax,8), %rax
cmpq $0, (%rax)
je .LBB1_26
# %bb.32: # %.lr.ph279.preheader
# in Loop: Header=BB1_24 Depth=1
decl %ecx
xorl %edi, %edi
.p2align 4, 0x90
.LBB1_33: # %.lr.ph279
# Parent Loop BB1_24 Depth=1
# => This Inner Loop Header: Depth=2
cmpq %rdi, %rcx
je .LBB1_34
# %bb.27: # in Loop: Header=BB1_33 Depth=2
leaq 1(%rdi), %rdx
cmpq $0, 8(%rax,%rdi,8)
movq %rdx, %rdi
jne .LBB1_33
jmp .LBB1_28
.LBB1_34:
movl $.L.str.7, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
movl $-1, %ebx
jmp .LBB1_63
.LBB1_30: # %._crit_edge195
movq %rbp, %rdi
callq fclose
callq clock
movq %rax, %r13
callq clock
cvtsi2ss %r14, %xmm4
movq %rax, %r12
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
testl %r15d, %r15d
je .LBB1_31
# %bb.35: # %.lr.ph198
movss .LCPI1_2(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
divss %xmm4, %xmm2
leaq (,%r14,8), %rax
leaq (%rax,%rax,2), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_36: # =>This Inner Loop Header: Depth=1
movss %xmm2, 4(%rbx,%rcx)
movl $0, 8(%rbx,%rcx)
addq $24, %rcx
cmpq %rcx, %rax
jne .LBB1_36
# %bb.37: # %.lr.ph201.preheader
leaq (,%r14,8), %rax
leaq (%rax,%rax,2), %rax
xorps %xmm2, %xmm2
xorl %ecx, %ecx
jmp .LBB1_38
.p2align 4, 0x90
.LBB1_40: # in Loop: Header=BB1_38 Depth=1
addq $24, %rcx
cmpq %rcx, %rax
je .LBB1_41
.LBB1_38: # %.lr.ph201
# =>This Inner Loop Header: Depth=1
cmpl $0, 12(%rbx,%rcx)
jne .LBB1_40
# %bb.39: # in Loop: Header=BB1_38 Depth=1
addss 4(%rbx,%rcx), %xmm2
jmp .LBB1_40
.LBB1_31:
xorps %xmm2, %xmm2
.LBB1_41: # %.preheader173
subq 8(%rsp), %r13 # 8-byte Folded Reload
movaps %xmm0, %xmm3
divss %xmm4, %xmm3
divss %xmm4, %xmm1
leaq (,%r14,8), %rax
leaq (%rax,%rax,2), %rax
xorl %ecx, %ecx
movss .LCPI1_5(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
movss .LCPI1_3(%rip), %xmm5 # xmm5 = mem[0],zero,zero,zero
movaps .LCPI1_4(%rip), %xmm6 # xmm6 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
.p2align 4, 0x90
.LBB1_42: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_44 Depth 2
# Child Loop BB1_49 Depth 3
# Child Loop BB1_54 Depth 2
testl %r15d, %r15d
je .LBB1_51
# %bb.43: # %.lr.ph208.preheader
# in Loop: Header=BB1_42 Depth=1
xorl %edx, %edx
jmp .LBB1_44
.p2align 4, 0x90
.LBB1_50: # %._crit_edge206
# in Loop: Header=BB1_44 Depth=2
incq %rdx
cmpq %r14, %rdx
je .LBB1_51
.LBB1_44: # %.lr.ph208
# Parent Loop BB1_42 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_49 Depth 3
leaq (%rdx,%rdx,2), %rdi
movl 12(%rbx,%rdi,8), %esi
testq %rsi, %rsi
je .LBB1_45
# %bb.46: # in Loop: Header=BB1_44 Depth=2
movss 4(%rbx,%rdi,8), %xmm7 # xmm7 = mem[0],zero,zero,zero
mulss %xmm0, %xmm7
xorps %xmm8, %xmm8
cvtsi2ss %rsi, %xmm8
divss %xmm8, %xmm7
testq %rsi, %rsi
jne .LBB1_48
jmp .LBB1_50
.p2align 4, 0x90
.LBB1_45: # in Loop: Header=BB1_44 Depth=2
xorps %xmm7, %xmm7
testq %rsi, %rsi
je .LBB1_50
.LBB1_48: # %.lr.ph205
# in Loop: Header=BB1_44 Depth=2
movq 16(%rbx,%rdi,8), %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB1_49: # Parent Loop BB1_42 Depth=1
# Parent Loop BB1_44 Depth=2
# => This Inner Loop Header: Depth=3
movq (%rdi,%r8,8), %r9
movss 8(%r9), %xmm8 # xmm8 = mem[0],zero,zero,zero
addss %xmm7, %xmm8
movss %xmm8, 8(%r9)
incq %r8
cmpq %r8, %rsi
jne .LBB1_49
jmp .LBB1_50
.p2align 4, 0x90
.LBB1_51: # %._crit_edge209
# in Loop: Header=BB1_42 Depth=1
testl %r15d, %r15d
je .LBB1_52
# %bb.53: # %.lr.ph214.preheader
# in Loop: Header=BB1_42 Depth=1
movaps %xmm2, %xmm8
mulss %xmm3, %xmm8
xorps %xmm2, %xmm2
xorl %edx, %edx
xorps %xmm7, %xmm7
jmp .LBB1_54
.p2align 4, 0x90
.LBB1_56: # %.lr.ph214
# in Loop: Header=BB1_54 Depth=2
addss %xmm11, %xmm2
subss %xmm10, %xmm9
movaps %xmm9, %xmm10
xorps %xmm6, %xmm10
movaps %xmm10, %xmm11
cmpnless %xmm9, %xmm11
andps %xmm11, %xmm10
andnps %xmm9, %xmm11
orps %xmm10, %xmm11
addss %xmm11, %xmm7
addq $24, %rdx
cmpq %rdx, %rax
je .LBB1_57
.LBB1_54: # %.lr.ph214
# Parent Loop BB1_42 Depth=1
# => This Inner Loop Header: Depth=2
movss 4(%rbx,%rdx), %xmm9 # xmm9 = mem[0],zero,zero,zero
movss 8(%rbx,%rdx), %xmm10 # xmm10 = mem[0],zero,zero,zero
addss %xmm8, %xmm10
addss %xmm1, %xmm10
movss %xmm10, 4(%rbx,%rdx)
movl $0, 8(%rbx,%rdx)
cmpl $0, 12(%rbx,%rdx)
movaps %xmm10, %xmm11
je .LBB1_56
# %bb.55: # %.lr.ph214
# in Loop: Header=BB1_54 Depth=2
movaps %xmm5, %xmm11
jmp .LBB1_56
.p2align 4, 0x90
.LBB1_52: # in Loop: Header=BB1_42 Depth=1
xorps %xmm7, %xmm7
xorps %xmm2, %xmm2
.LBB1_57: # %._crit_edge215
# in Loop: Header=BB1_42 Depth=1
leal 1(%rcx), %ebp
ucomiss %xmm4, %xmm7
jbe .LBB1_59
# %bb.58: # %._crit_edge215
# in Loop: Header=BB1_42 Depth=1
cmpl $23, %ecx
movl %ebp, %ecx
jb .LBB1_42
.LBB1_59:
callq clock
movq %rax, %rcx
subq %r12, %rcx
movabsq $2361183241434822607, %rsi # imm = 0x20C49BA5E353F7CF
movq %r13, %rax
imulq %rsi
movq %rdx, %rax
shrq $63, %rax
shrq $7, %rdx
addl %eax, %edx
movq %rdx, 8(%rsp) # 8-byte Spill
movq %rcx, %rax
imulq %rsi
movq %rdx, %rax
shrq $63, %rax
shrq $7, %rdx
addl %eax, %edx
movq %rdx, 16(%rsp) # 8-byte Spill
movl $.L.str.8, %edi
movl $.L.str.9, %esi
callq fopen
movq %rax, %r12
testl %r15d, %r15d
je .LBB1_62
# %bb.60: # %.lr.ph222.preheader
addq $4, %rbx
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_61: # %.lr.ph222
# =>This Inner Loop Header: Depth=1
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.10, %esi
movq %r12, %rdi
movl %r13d, %edx
movb $1, %al
callq fprintf
incq %r13
addq $24, %rbx
cmpq %r13, %r14
jne .LBB1_61
.LBB1_62: # %._crit_edge223
movq %r12, %rdi
callq fclose
movslq 8(%rsp), %rdx # 4-byte Folded Reload
imulq $274877907, %rdx, %rsi # imm = 0x10624DD3
movq %rsi, %rax
shrq $63, %rax
sarq $38, %rsi
addl %eax, %esi
imull $1000, %esi, %eax # imm = 0x3E8
subl %eax, %edx
xorl %ebx, %ebx
movl $.L.str.11, %edi
# kill: def $esi killed $esi killed $rsi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
movslq 16(%rsp), %rdx # 4-byte Folded Reload
imulq $274877907, %rdx, %rsi # imm = 0x10624DD3
movq %rsi, %rax
shrq $63, %rax
sarq $38, %rsi
addl %eax, %esi
imull $1000, %esi, %eax # imm = 0x3E8
subl %eax, %edx
movl $.L.str.12, %edi
# kill: def $esi killed $esi killed $rsi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
movl $.L.str.13, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
callq puts@PLT
.LBB1_63:
movl %ebx, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_64:
.cfi_def_cfa_offset 80
movq stderr(%rip), %rdi
movl $.L.str.5, %esi
movl %r12d, %edx
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.LBB1_1:
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $48, %esi
jmp .LBB1_2
.LBB1_6:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $34, %esi
jmp .LBB1_2
.LBB1_11:
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
movl $28, %esi
.LBB1_2:
movl $1, %edx
callq fwrite@PLT
movl $-1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Wrong number of args. Provide input graph file.\n"
.size .L.str, 49
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "ERROR: Could not open input file.\n"
.size .L.str.2, 35
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%u %u"
.size .L.str.3, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Malloc failed for vertices.\n"
.size .L.str.4, 29
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Malloc failed for successors of vertex %d.\n"
.size .L.str.5, 44
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d %d"
.size .L.str.6, 6
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Setting up the successor pointers of virtex %u failed"
.size .L.str.7, 54
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "result_CPU"
.size .L.str.8, 11
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "w"
.size .L.str.9, 2
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Vertex %u:\tpagerank = %.18f\n"
.size .L.str.10, 29
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Time to build: %d seconds, %d milliseconds\n"
.size .L.str.11, 44
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Time to calc: %d seconds, %d milliseconds\n"
.size .L.str.12, 43
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "iter: %d\n"
.size .L.str.13, 10
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Done"
.size .Lstr, 5
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <math.h>
__global__ void multi(float *a, float *b, float *c, int width) {
int col = threadIdx.x + blockIdx.x * blockDim.x;
int row = threadIdx.y + blockIdx.y * blockDim.y;
float result = 0;
if (col < width && row < width) {
for (int k = 0; k < width; k++) {
result += a[row * width + k] * b[k * width + col];
}
c[row * width + col] = result;
}
}
int main(int arg0, char **arg1) {
cudaThreadSynchronize();
int width = atoi(arg1[1]);
int THREADS_PER_BLOCK = 256;
if(arg0 == 3) THREADS_PER_BLOCK = atoi(arg1[2]);
int sqrtThreads = sqrt(THREADS_PER_BLOCK);
int nBlocks = width/sqrtThreads;
if (width % sqrtThreads != 0) {
nBlocks++;
}
dim3 grid(nBlocks, nBlocks, 1);
dim3 block(sqrtThreads, sqrtThreads, 1);
float *a_h;
float *b_h;
float *c_h;
float *d_h;
float *a_d;
float *b_d;
float *c_d;
int size;
cudaEvent_t start;
cudaEvent_t stop;
float elapsed1;
size = width * width * sizeof(float);
a_h = (float*) malloc(size);
b_h = (float*) malloc(size);
c_h = (float*) malloc(size);
d_h = (float*) malloc(size);
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
a_h[i * width + j] = i;
b_h[i * width + j] = i;
}
}
cudaMalloc((void**)&a_d, size);
cudaMalloc((void**)&b_d, size);
cudaMalloc((void**)&c_d, size);
cudaMemcpy(a_d, a_h, size, cudaMemcpyHostToDevice);
cudaMemcpy(b_d, b_h, size, cudaMemcpyHostToDevice);
cudaMemcpy(c_d, c_h, size, cudaMemcpyHostToDevice);
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
multi<<<grid, block>>>(a_d, b_d, c_d, width);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed1, start, stop);
printf("%f\n", elapsed1/1000);
cudaMemcpy(c_h, c_d, size, cudaMemcpyDeviceToHost);
free(a_h);
free(b_h);
free(c_h);
free(d_h);
cudaFree(a_d);
cudaFree(b_d);
cudaFree(c_d);
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
} | code for sm_80
Function : _Z5multiPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xc00 ; /* 0x00000b0000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xb00 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*01b0*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x000fcc00078e0219 */
/*01d0*/ @!P0 BRA 0x970 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6b0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0270*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0280*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0290*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*02a0*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*02b0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*02c0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*02d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02e0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*02f0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*0300*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*0320*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*0330*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0340*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*0350*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0360*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0370*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0380*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0390*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*03a0*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*03b0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03d0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*03e0*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*03f0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*0400*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0410*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*0420*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*0430*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0440*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*0450*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*0460*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0490*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*04a0*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*04b0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*04c0*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*04d0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*04e0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04f0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*0500*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*0510*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*0520*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*0530*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0540*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0550*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0560*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0570*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0580*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0590*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*05b0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*05c0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05e0*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*05f0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*0600*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*0610*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*0660*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0670*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0680*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0690*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*06a0*/ @P1 BRA 0x220 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x950 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06d0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*06e0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06f0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0710*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*0720*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0730*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fe200078e0208 */
/*0740*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0750*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0760*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0770*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0780*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0790*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*07a0*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*07b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07c0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07d0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*07e0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07f0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*0800*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0810*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0830*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0840*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0850*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0860*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0870*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0880*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0890*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*08a0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08b0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08c0*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*08d0*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*08e0*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*08f0*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*0900*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*0910*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*0920*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*0930*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*0940*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*0950*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0960*/ @!P0 BRA 0xb00 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0970*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0980*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0990*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*09a0*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fc800078e0208 */
/*09c0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*09d0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09f0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*0a00*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0a10*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a30*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a40*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a50*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0ab0*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0ac0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0ad0*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0ae0*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0af0*/ @P0 BRA 0x970 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc00 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b20*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b30*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x000fe20007ffe0ff */
/*0b40*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fd000078e0200 */
/*0b50*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b60*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b70*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b80*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b90*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0ba0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0bb0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bc0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bd0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0be0*/ FFMA R28, R11, R4, R28 ; /* 0x000000040b1c7223 */
/* 0x004fcc000000001c */
/*0bf0*/ @P0 BRA 0xb70 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0c00*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c10*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0c20*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c30*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c50*/ BRA 0xc50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <math.h>
__global__ void multi(float *a, float *b, float *c, int width) {
int col = threadIdx.x + blockIdx.x * blockDim.x;
int row = threadIdx.y + blockIdx.y * blockDim.y;
float result = 0;
if (col < width && row < width) {
for (int k = 0; k < width; k++) {
result += a[row * width + k] * b[k * width + col];
}
c[row * width + col] = result;
}
}
int main(int arg0, char **arg1) {
cudaThreadSynchronize();
int width = atoi(arg1[1]);
int THREADS_PER_BLOCK = 256;
if(arg0 == 3) THREADS_PER_BLOCK = atoi(arg1[2]);
int sqrtThreads = sqrt(THREADS_PER_BLOCK);
int nBlocks = width/sqrtThreads;
if (width % sqrtThreads != 0) {
nBlocks++;
}
dim3 grid(nBlocks, nBlocks, 1);
dim3 block(sqrtThreads, sqrtThreads, 1);
float *a_h;
float *b_h;
float *c_h;
float *d_h;
float *a_d;
float *b_d;
float *c_d;
int size;
cudaEvent_t start;
cudaEvent_t stop;
float elapsed1;
size = width * width * sizeof(float);
a_h = (float*) malloc(size);
b_h = (float*) malloc(size);
c_h = (float*) malloc(size);
d_h = (float*) malloc(size);
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
a_h[i * width + j] = i;
b_h[i * width + j] = i;
}
}
cudaMalloc((void**)&a_d, size);
cudaMalloc((void**)&b_d, size);
cudaMalloc((void**)&c_d, size);
cudaMemcpy(a_d, a_h, size, cudaMemcpyHostToDevice);
cudaMemcpy(b_d, b_h, size, cudaMemcpyHostToDevice);
cudaMemcpy(c_d, c_h, size, cudaMemcpyHostToDevice);
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
multi<<<grid, block>>>(a_d, b_d, c_d, width);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed1, start, stop);
printf("%f\n", elapsed1/1000);
cudaMemcpy(c_h, c_d, size, cudaMemcpyDeviceToHost);
free(a_h);
free(b_h);
free(c_h);
free(d_h);
cudaFree(a_d);
cudaFree(b_d);
cudaFree(c_d);
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
} | .file "tmpxft_0009be0a_00000000-6_MatrixGPUGlobal.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z5multiPfS_S_iPfS_S_i
.type _Z29__device_stub__Z5multiPfS_S_iPfS_S_i, @function
_Z29__device_stub__Z5multiPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5multiPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z5multiPfS_S_iPfS_S_i, .-_Z29__device_stub__Z5multiPfS_S_iPfS_S_i
.globl _Z5multiPfS_S_i
.type _Z5multiPfS_S_i, @function
_Z5multiPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z5multiPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5multiPfS_S_i, .-_Z5multiPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "%f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movl %edi, %ebp
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
call cudaThreadSynchronize@PLT
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movl %eax, %r13d
movsd .LC0(%rip), %xmm0
cmpl $3, %ebp
je .L26
.L12:
sqrtsd %xmm0, %xmm0
.L15:
cvttsd2sil %xmm0, %ecx
movl %r13d, %eax
cltd
idivl %ecx
cmpl $1, %edx
sbbl $-1, %eax
movl %eax, 48(%rsp)
movl %eax, 52(%rsp)
movl $1, 56(%rsp)
movl %ecx, 60(%rsp)
movl %ecx, 64(%rsp)
movl $1, 68(%rsp)
movl %r15d, %r12d
imull %r15d, %r12d
sall $2, %r12d
movslq %r12d, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r12, %rdi
call malloc@PLT
movq %rax, %r14
testl %r15d, %r15d
jle .L17
movslq %r15d, %rdi
salq $2, %rdi
leal -1(%r15), %esi
leaq 4(,%rsi,4), %rdx
movl $0, %ecx
notq %rsi
salq $2, %rsi
.L18:
leaq (%rsi,%rdx), %rax
pxor %xmm0, %xmm0
cvtsi2ssl %ecx, %xmm0
.L19:
movss %xmm0, 0(%rbp,%rax)
movss %xmm0, (%rbx,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L19
addl $1, %ecx
addq %rdi, %rdx
cmpl %r13d, %ecx
jne .L18
.L17:
leaq 8(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L20:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 4(%rsp), %xmm0
divss .LC2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %r12, %rdx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
pxor %xmm1, %xmm1
ucomisd %xmm0, %xmm1
jbe .L12
call sqrt@PLT
jmp .L15
.L27:
movl %r13d, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z5multiPfS_S_iPfS_S_i
jmp .L20
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z5multiPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z5multiPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1081081856
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <math.h>
__global__ void multi(float *a, float *b, float *c, int width) {
int col = threadIdx.x + blockIdx.x * blockDim.x;
int row = threadIdx.y + blockIdx.y * blockDim.y;
float result = 0;
if (col < width && row < width) {
for (int k = 0; k < width; k++) {
result += a[row * width + k] * b[k * width + col];
}
c[row * width + col] = result;
}
}
int main(int arg0, char **arg1) {
cudaThreadSynchronize();
int width = atoi(arg1[1]);
int THREADS_PER_BLOCK = 256;
if(arg0 == 3) THREADS_PER_BLOCK = atoi(arg1[2]);
int sqrtThreads = sqrt(THREADS_PER_BLOCK);
int nBlocks = width/sqrtThreads;
if (width % sqrtThreads != 0) {
nBlocks++;
}
dim3 grid(nBlocks, nBlocks, 1);
dim3 block(sqrtThreads, sqrtThreads, 1);
float *a_h;
float *b_h;
float *c_h;
float *d_h;
float *a_d;
float *b_d;
float *c_d;
int size;
cudaEvent_t start;
cudaEvent_t stop;
float elapsed1;
size = width * width * sizeof(float);
a_h = (float*) malloc(size);
b_h = (float*) malloc(size);
c_h = (float*) malloc(size);
d_h = (float*) malloc(size);
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
a_h[i * width + j] = i;
b_h[i * width + j] = i;
}
}
cudaMalloc((void**)&a_d, size);
cudaMalloc((void**)&b_d, size);
cudaMalloc((void**)&c_d, size);
cudaMemcpy(a_d, a_h, size, cudaMemcpyHostToDevice);
cudaMemcpy(b_d, b_h, size, cudaMemcpyHostToDevice);
cudaMemcpy(c_d, c_h, size, cudaMemcpyHostToDevice);
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
multi<<<grid, block>>>(a_d, b_d, c_d, width);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed1, start, stop);
printf("%f\n", elapsed1/1000);
cudaMemcpy(c_h, c_d, size, cudaMemcpyDeviceToHost);
free(a_h);
free(b_h);
free(c_h);
free(d_h);
cudaFree(a_d);
cudaFree(b_d);
cudaFree(c_d);
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
__global__ void multi(float *a, float *b, float *c, int width) {
int col = threadIdx.x + blockIdx.x * blockDim.x;
int row = threadIdx.y + blockIdx.y * blockDim.y;
float result = 0;
if (col < width && row < width) {
for (int k = 0; k < width; k++) {
result += a[row * width + k] * b[k * width + col];
}
c[row * width + col] = result;
}
}
int main(int arg0, char **arg1) {
hipDeviceSynchronize();
int width = atoi(arg1[1]);
int THREADS_PER_BLOCK = 256;
if(arg0 == 3) THREADS_PER_BLOCK = atoi(arg1[2]);
int sqrtThreads = sqrt(THREADS_PER_BLOCK);
int nBlocks = width/sqrtThreads;
if (width % sqrtThreads != 0) {
nBlocks++;
}
dim3 grid(nBlocks, nBlocks, 1);
dim3 block(sqrtThreads, sqrtThreads, 1);
float *a_h;
float *b_h;
float *c_h;
float *d_h;
float *a_d;
float *b_d;
float *c_d;
int size;
hipEvent_t start;
hipEvent_t stop;
float elapsed1;
size = width * width * sizeof(float);
a_h = (float*) malloc(size);
b_h = (float*) malloc(size);
c_h = (float*) malloc(size);
d_h = (float*) malloc(size);
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
a_h[i * width + j] = i;
b_h[i * width + j] = i;
}
}
hipMalloc((void**)&a_d, size);
hipMalloc((void**)&b_d, size);
hipMalloc((void**)&c_d, size);
hipMemcpy(a_d, a_h, size, hipMemcpyHostToDevice);
hipMemcpy(b_d, b_h, size, hipMemcpyHostToDevice);
hipMemcpy(c_d, c_h, size, hipMemcpyHostToDevice);
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
multi<<<grid, block>>>(a_d, b_d, c_d, width);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed1, start, stop);
printf("%f\n", elapsed1/1000);
hipMemcpy(c_h, c_d, size, hipMemcpyDeviceToHost);
free(a_h);
free(b_h);
free(c_h);
free(d_h);
hipFree(a_d);
hipFree(b_d);
hipFree(c_d);
hipEventDestroy(start);
hipEventDestroy(stop);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
__global__ void multi(float *a, float *b, float *c, int width) {
int col = threadIdx.x + blockIdx.x * blockDim.x;
int row = threadIdx.y + blockIdx.y * blockDim.y;
float result = 0;
if (col < width && row < width) {
for (int k = 0; k < width; k++) {
result += a[row * width + k] * b[k * width + col];
}
c[row * width + col] = result;
}
}
int main(int arg0, char **arg1) {
hipDeviceSynchronize();
int width = atoi(arg1[1]);
int THREADS_PER_BLOCK = 256;
if(arg0 == 3) THREADS_PER_BLOCK = atoi(arg1[2]);
int sqrtThreads = sqrt(THREADS_PER_BLOCK);
int nBlocks = width/sqrtThreads;
if (width % sqrtThreads != 0) {
nBlocks++;
}
dim3 grid(nBlocks, nBlocks, 1);
dim3 block(sqrtThreads, sqrtThreads, 1);
float *a_h;
float *b_h;
float *c_h;
float *d_h;
float *a_d;
float *b_d;
float *c_d;
int size;
hipEvent_t start;
hipEvent_t stop;
float elapsed1;
size = width * width * sizeof(float);
a_h = (float*) malloc(size);
b_h = (float*) malloc(size);
c_h = (float*) malloc(size);
d_h = (float*) malloc(size);
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
a_h[i * width + j] = i;
b_h[i * width + j] = i;
}
}
hipMalloc((void**)&a_d, size);
hipMalloc((void**)&b_d, size);
hipMalloc((void**)&c_d, size);
hipMemcpy(a_d, a_h, size, hipMemcpyHostToDevice);
hipMemcpy(b_d, b_h, size, hipMemcpyHostToDevice);
hipMemcpy(c_d, c_h, size, hipMemcpyHostToDevice);
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
multi<<<grid, block>>>(a_d, b_d, c_d, width);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed1, start, stop);
printf("%f\n", elapsed1/1000);
hipMemcpy(c_h, c_d, size, hipMemcpyDeviceToHost);
free(a_h);
free(b_h);
free(c_h);
free(d_h);
hipFree(a_d);
hipFree(b_d);
hipFree(c_d);
hipEventDestroy(start);
hipEventDestroy(stop);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5multiPfS_S_i
.globl _Z5multiPfS_S_i
.p2align 8
.type _Z5multiPfS_S_i,@function
_Z5multiPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5multiPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5multiPfS_S_i, .Lfunc_end0-_Z5multiPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5multiPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5multiPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
__global__ void multi(float *a, float *b, float *c, int width) {
int col = threadIdx.x + blockIdx.x * blockDim.x;
int row = threadIdx.y + blockIdx.y * blockDim.y;
float result = 0;
if (col < width && row < width) {
for (int k = 0; k < width; k++) {
result += a[row * width + k] * b[k * width + col];
}
c[row * width + col] = result;
}
}
int main(int arg0, char **arg1) {
hipDeviceSynchronize();
int width = atoi(arg1[1]);
int THREADS_PER_BLOCK = 256;
if(arg0 == 3) THREADS_PER_BLOCK = atoi(arg1[2]);
int sqrtThreads = sqrt(THREADS_PER_BLOCK);
int nBlocks = width/sqrtThreads;
if (width % sqrtThreads != 0) {
nBlocks++;
}
dim3 grid(nBlocks, nBlocks, 1);
dim3 block(sqrtThreads, sqrtThreads, 1);
float *a_h;
float *b_h;
float *c_h;
float *d_h;
float *a_d;
float *b_d;
float *c_d;
int size;
hipEvent_t start;
hipEvent_t stop;
float elapsed1;
size = width * width * sizeof(float);
a_h = (float*) malloc(size);
b_h = (float*) malloc(size);
c_h = (float*) malloc(size);
d_h = (float*) malloc(size);
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
a_h[i * width + j] = i;
b_h[i * width + j] = i;
}
}
hipMalloc((void**)&a_d, size);
hipMalloc((void**)&b_d, size);
hipMalloc((void**)&c_d, size);
hipMemcpy(a_d, a_h, size, hipMemcpyHostToDevice);
hipMemcpy(b_d, b_h, size, hipMemcpyHostToDevice);
hipMemcpy(c_d, c_h, size, hipMemcpyHostToDevice);
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
multi<<<grid, block>>>(a_d, b_d, c_d, width);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed1, start, stop);
printf("%f\n", elapsed1/1000);
hipMemcpy(c_h, c_d, size, hipMemcpyDeviceToHost);
free(a_h);
free(b_h);
free(c_h);
free(d_h);
hipFree(a_d);
hipFree(b_d);
hipFree(c_d);
hipEventDestroy(start);
hipEventDestroy(stop);
return 0;
} | .text
.file "MatrixGPUGlobal.hip"
.globl _Z20__device_stub__multiPfS_S_i # -- Begin function _Z20__device_stub__multiPfS_S_i
.p2align 4, 0x90
.type _Z20__device_stub__multiPfS_S_i,@function
_Z20__device_stub__multiPfS_S_i: # @_Z20__device_stub__multiPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5multiPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__multiPfS_S_i, .Lfunc_end0-_Z20__device_stub__multiPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x4070000000000000 # double 256
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI1_1:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
callq hipDeviceSynchronize
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
cmpl $3, %ebp
jne .LBB1_1
# %bb.2:
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
cvtsi2sd %eax, %xmm0
jmp .LBB1_3
.LBB1_1:
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
.LBB1_3:
movabsq $4294967297, %rbx # imm = 0x100000001
xorpd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jb .LBB1_5
# %bb.4:
sqrtsd %xmm0, %xmm0
jmp .LBB1_6
.LBB1_5: # %call.sqrt
callq sqrt
.LBB1_6: # %.split
cvttsd2si %xmm0, %ebp
movl %r13d, %eax
cltd
idivl %ebp
movl %eax, %r12d
cmpl $1, %edx
sbbl $-1, %r12d
imulq %rbx, %r12
imulq %rbx, %rbp
movl %r13d, %eax
imull %r13d, %eax
shll $2, %eax
movslq %eax, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r14
movq %rbx, %rdi
callq malloc
movq %rax, %r15
movq %rbx, %rdi
callq malloc
movq %rax, 48(%rsp) # 8-byte Spill
testl %r13d, %r13d
jle .LBB1_11
# %bb.7: # %.preheader.lr.ph
movl %r13d, %eax
xorl %ecx, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_8: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_9 Depth 2
movl %ecx, %edi
leaq (%r15,%rdi,4), %rsi
leaq (%r14,%rdi,4), %rdi
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB1_9: # Parent Loop BB1_8 Depth=1
# => This Inner Loop Header: Depth=2
movss %xmm0, (%rdi,%r8,4)
movss %xmm0, (%rsi,%r8,4)
incq %r8
cmpq %r8, %rax
jne .LBB1_9
# %bb.10: # %._crit_edge
# in Loop: Header=BB1_8 Depth=1
incq %rdx
addl %r13d, %ecx
cmpq %rax, %rdx
jne .LBB1_8
.LBB1_11: # %._crit_edge66
leaq 32(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %r15, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq 48(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r12, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_13
# %bb.12:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl %r13d, 44(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 44(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z5multiPfS_S_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_13:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq (%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI1_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rsi
movq 48(%rsp), %r12 # 8-byte Reload
movq %r12, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipEventDestroy
movq (%rsp), %rdi
callq hipEventDestroy
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5multiPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5multiPfS_S_i,@object # @_Z5multiPfS_S_i
.section .rodata,"a",@progbits
.globl _Z5multiPfS_S_i
.p2align 3, 0x0
_Z5multiPfS_S_i:
.quad _Z20__device_stub__multiPfS_S_i
.size _Z5multiPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f\n"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5multiPfS_S_i"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__multiPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5multiPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5multiPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xc00 ; /* 0x00000b0000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xb00 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*01b0*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x000fcc00078e0219 */
/*01d0*/ @!P0 BRA 0x970 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6b0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0270*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0280*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0290*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*02a0*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*02b0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*02c0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*02d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02e0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*02f0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*0300*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*0320*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*0330*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0340*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*0350*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0360*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0370*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0380*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0390*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*03a0*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*03b0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03d0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*03e0*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*03f0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*0400*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0410*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*0420*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*0430*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0440*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*0450*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*0460*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0490*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*04a0*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*04b0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*04c0*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*04d0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*04e0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04f0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*0500*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*0510*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*0520*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*0530*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0540*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0550*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0560*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0570*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0580*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0590*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*05b0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*05c0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05e0*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*05f0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*0600*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*0610*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*0660*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0670*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0680*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0690*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*06a0*/ @P1 BRA 0x220 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x950 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06d0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*06e0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06f0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0710*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*0720*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0730*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fe200078e0208 */
/*0740*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0750*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0760*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0770*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0780*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0790*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*07a0*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*07b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07c0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07d0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*07e0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07f0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*0800*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0810*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0830*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0840*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0850*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0860*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0870*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0880*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0890*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*08a0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08b0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08c0*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*08d0*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*08e0*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*08f0*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*0900*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*0910*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*0920*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*0930*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*0940*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*0950*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0960*/ @!P0 BRA 0xb00 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0970*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0980*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0990*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*09a0*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fc800078e0208 */
/*09c0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*09d0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09f0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*0a00*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0a10*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a30*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a40*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a50*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0ab0*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0ac0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0ad0*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0ae0*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0af0*/ @P0 BRA 0x970 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc00 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b20*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b30*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x000fe20007ffe0ff */
/*0b40*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fd000078e0200 */
/*0b50*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b60*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b70*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b80*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b90*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0ba0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0bb0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bc0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bd0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0be0*/ FFMA R28, R11, R4, R28 ; /* 0x000000040b1c7223 */
/* 0x004fcc000000001c */
/*0bf0*/ @P0 BRA 0xb70 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0c00*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c10*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0c20*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c30*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c50*/ BRA 0xc50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5multiPfS_S_i
.globl _Z5multiPfS_S_i
.p2align 8
.type _Z5multiPfS_S_i,@function
_Z5multiPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5multiPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5multiPfS_S_i, .Lfunc_end0-_Z5multiPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5multiPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5multiPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009be0a_00000000-6_MatrixGPUGlobal.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z5multiPfS_S_iPfS_S_i
.type _Z29__device_stub__Z5multiPfS_S_iPfS_S_i, @function
_Z29__device_stub__Z5multiPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5multiPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z5multiPfS_S_iPfS_S_i, .-_Z29__device_stub__Z5multiPfS_S_iPfS_S_i
.globl _Z5multiPfS_S_i
.type _Z5multiPfS_S_i, @function
_Z5multiPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z5multiPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5multiPfS_S_i, .-_Z5multiPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "%f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movl %edi, %ebp
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
call cudaThreadSynchronize@PLT
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movl %eax, %r13d
movsd .LC0(%rip), %xmm0
cmpl $3, %ebp
je .L26
.L12:
sqrtsd %xmm0, %xmm0
.L15:
cvttsd2sil %xmm0, %ecx
movl %r13d, %eax
cltd
idivl %ecx
cmpl $1, %edx
sbbl $-1, %eax
movl %eax, 48(%rsp)
movl %eax, 52(%rsp)
movl $1, 56(%rsp)
movl %ecx, 60(%rsp)
movl %ecx, 64(%rsp)
movl $1, 68(%rsp)
movl %r15d, %r12d
imull %r15d, %r12d
sall $2, %r12d
movslq %r12d, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r12, %rdi
call malloc@PLT
movq %rax, %r14
testl %r15d, %r15d
jle .L17
movslq %r15d, %rdi
salq $2, %rdi
leal -1(%r15), %esi
leaq 4(,%rsi,4), %rdx
movl $0, %ecx
notq %rsi
salq $2, %rsi
.L18:
leaq (%rsi,%rdx), %rax
pxor %xmm0, %xmm0
cvtsi2ssl %ecx, %xmm0
.L19:
movss %xmm0, 0(%rbp,%rax)
movss %xmm0, (%rbx,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L19
addl $1, %ecx
addq %rdi, %rdx
cmpl %r13d, %ecx
jne .L18
.L17:
leaq 8(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L20:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 4(%rsp), %xmm0
divss .LC2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %r12, %rdx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
pxor %xmm1, %xmm1
ucomisd %xmm0, %xmm1
jbe .L12
call sqrt@PLT
jmp .L15
.L27:
movl %r13d, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z5multiPfS_S_iPfS_S_i
jmp .L20
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z5multiPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z5multiPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1081081856
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "MatrixGPUGlobal.hip"
.globl _Z20__device_stub__multiPfS_S_i # -- Begin function _Z20__device_stub__multiPfS_S_i
.p2align 4, 0x90
.type _Z20__device_stub__multiPfS_S_i,@function
_Z20__device_stub__multiPfS_S_i: # @_Z20__device_stub__multiPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5multiPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__multiPfS_S_i, .Lfunc_end0-_Z20__device_stub__multiPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x4070000000000000 # double 256
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI1_1:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
callq hipDeviceSynchronize
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
cmpl $3, %ebp
jne .LBB1_1
# %bb.2:
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
cvtsi2sd %eax, %xmm0
jmp .LBB1_3
.LBB1_1:
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
.LBB1_3:
movabsq $4294967297, %rbx # imm = 0x100000001
xorpd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jb .LBB1_5
# %bb.4:
sqrtsd %xmm0, %xmm0
jmp .LBB1_6
.LBB1_5: # %call.sqrt
callq sqrt
.LBB1_6: # %.split
cvttsd2si %xmm0, %ebp
movl %r13d, %eax
cltd
idivl %ebp
movl %eax, %r12d
cmpl $1, %edx
sbbl $-1, %r12d
imulq %rbx, %r12
imulq %rbx, %rbp
movl %r13d, %eax
imull %r13d, %eax
shll $2, %eax
movslq %eax, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r14
movq %rbx, %rdi
callq malloc
movq %rax, %r15
movq %rbx, %rdi
callq malloc
movq %rax, 48(%rsp) # 8-byte Spill
testl %r13d, %r13d
jle .LBB1_11
# %bb.7: # %.preheader.lr.ph
movl %r13d, %eax
xorl %ecx, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_8: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_9 Depth 2
movl %ecx, %edi
leaq (%r15,%rdi,4), %rsi
leaq (%r14,%rdi,4), %rdi
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB1_9: # Parent Loop BB1_8 Depth=1
# => This Inner Loop Header: Depth=2
movss %xmm0, (%rdi,%r8,4)
movss %xmm0, (%rsi,%r8,4)
incq %r8
cmpq %r8, %rax
jne .LBB1_9
# %bb.10: # %._crit_edge
# in Loop: Header=BB1_8 Depth=1
incq %rdx
addl %r13d, %ecx
cmpq %rax, %rdx
jne .LBB1_8
.LBB1_11: # %._crit_edge66
leaq 32(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %r15, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq 48(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r12, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_13
# %bb.12:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl %r13d, 44(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 44(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z5multiPfS_S_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_13:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq (%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI1_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rsi
movq 48(%rsp), %r12 # 8-byte Reload
movq %r12, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipEventDestroy
movq (%rsp), %rdi
callq hipEventDestroy
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5multiPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5multiPfS_S_i,@object # @_Z5multiPfS_S_i
.section .rodata,"a",@progbits
.globl _Z5multiPfS_S_i
.p2align 3, 0x0
_Z5multiPfS_S_i:
.quad _Z20__device_stub__multiPfS_S_i
.size _Z5multiPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f\n"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5multiPfS_S_i"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__multiPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5multiPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void cosineSimilarityCuda(float3* pDotProducts, size_t pSize, float* results) {
int instance = blockIdx.x * blockDim.x + threadIdx.x;
while (instance < pSize) {
results[instance] = pDotProducts[instance].y / (sqrtf(pDotProducts[instance].x)* sqrtf(pDotProducts[instance].z));
instance += gridDim.x;
}
} | code for sm_80
Function : _Z20cosineSimilarityCudaP6float3mPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R0, RZ, 0x1f, R4 ; /* 0x0000001fff007819 */
/* 0x000fc80000011404 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R0, c[0x0][0x16c], PT, P0 ; /* 0x00005b0000007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, R4 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0004 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, 0xc ; /* 0x0000000cff027424 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD R7, R0, 0xc, RZ ; /* 0x0000000c00077824 */
/* 0x000fe400078e02ff */
/*00c0*/ IMAD.WIDE.U32 R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fc800078e0002 */
/*00d0*/ IMAD.IADD R3, R3, 0x1, R7 ; /* 0x0000000103037824 */
/* 0x000fca00078e0207 */
/*00e0*/ LDG.E R12, [R2.64] ; /* 0x00000004020c7981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ BSSY B0, 0x1d0 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0100*/ IADD3 R6, R12, -0xd000000, RZ ; /* 0xf30000000c067810 */
/* 0x004fe20007ffe0ff */
/*0110*/ MUFU.RSQ R7, R12 ; /* 0x0000000c00077308 */
/* 0x0000660000001400 */
/*0120*/ ISETP.GT.U32.AND P0, PT, R6, 0x727fffff, PT ; /* 0x727fffff0600780c */
/* 0x000fda0003f04070 */
/*0130*/ @!P0 BRA 0x180 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0140*/ MOV R13, 0x160 ; /* 0x00000160000d7802 */
/* 0x003fe40000000f00 */
/*0150*/ CALL.REL.NOINC 0x440 ; /* 0x000002e000007944 */
/* 0x000fea0003c00000 */
/*0160*/ IMAD.MOV.U32 R8, RZ, RZ, R9 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0009 */
/*0170*/ BRA 0x1c0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0180*/ FMUL.FTZ R8, R12, R7 ; /* 0x000000070c087220 */
/* 0x003fe40000410000 */
/*0190*/ FMUL.FTZ R6, R7, 0.5 ; /* 0x3f00000007067820 */
/* 0x000fe40000410000 */
/*01a0*/ FFMA R7, -R8, R8, R12 ; /* 0x0000000808077223 */
/* 0x000fc8000000010c */
/*01b0*/ FFMA R8, R7, R6, R8 ; /* 0x0000000607087223 */
/* 0x000fe40000000008 */
/*01c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01d0*/ LDG.E R12, [R2.64+0x8] ; /* 0x00000804020c7981 */
/* 0x000ea2000c1e1900 */
/*01e0*/ BSSY B0, 0x2c0 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*01f0*/ IADD3 R6, R12, -0xd000000, RZ ; /* 0xf30000000c067810 */
/* 0x004fe20007ffe0ff */
/*0200*/ MUFU.RSQ R9, R12 ; /* 0x0000000c00097308 */
/* 0x0000660000001400 */
/*0210*/ ISETP.GT.U32.AND P0, PT, R6, 0x727fffff, PT ; /* 0x727fffff0600780c */
/* 0x000fda0003f04070 */
/*0220*/ @!P0 BRA 0x270 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0230*/ MOV R13, 0x250 ; /* 0x00000250000d7802 */
/* 0x003fe40000000f00 */
/*0240*/ CALL.REL.NOINC 0x440 ; /* 0x000001f000007944 */
/* 0x000fea0003c00000 */
/*0250*/ IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0009 */
/*0260*/ BRA 0x2b0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0270*/ FMUL.FTZ R7, R12, R9 ; /* 0x000000090c077220 */
/* 0x003fe40000410000 */
/*0280*/ FMUL.FTZ R9, R9, 0.5 ; /* 0x3f00000009097820 */
/* 0x000fe40000410000 */
/*0290*/ FFMA R6, -R7, R7, R12 ; /* 0x0000000707067223 */
/* 0x000fc8000000010c */
/*02a0*/ FFMA R7, R6, R9, R7 ; /* 0x0000000906077223 */
/* 0x000fe40000000007 */
/*02b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02c0*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040402097981 */
/* 0x000ea2000c1e1900 */
/*02d0*/ FMUL R10, R7, R8 ; /* 0x00000008070a7220 */
/* 0x000fe20000400000 */
/*02e0*/ BSSY B0, 0x3a0 ; /* 0x000000b000007945 */
/* 0x000fe60003800000 */
/*02f0*/ MUFU.RCP R6, R10 ; /* 0x0000000a00067308 */
/* 0x000e240000001000 */
/*0300*/ FFMA R7, -R10, R6, 1 ; /* 0x3f8000000a077423 */
/* 0x001fc80000000106 */
/*0310*/ FFMA R7, R6, R7, R6 ; /* 0x0000000706077223 */
/* 0x000fe40000000006 */
/*0320*/ FCHK P0, R9, R10 ; /* 0x0000000a09007302 */
/* 0x004e240000000000 */
/*0330*/ FFMA R6, R9, R7, RZ ; /* 0x0000000709067223 */
/* 0x000fc800000000ff */
/*0340*/ FFMA R8, -R10, R6, R9 ; /* 0x000000060a087223 */
/* 0x000fc80000000109 */
/*0350*/ FFMA R7, R7, R8, R6 ; /* 0x0000000807077223 */
/* 0x000fe20000000006 */
/*0360*/ @!P0 BRA 0x390 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*0370*/ MOV R2, 0x390 ; /* 0x0000039000027802 */
/* 0x000fe40000000f00 */
/*0380*/ CALL.REL.NOINC 0x5b0 ; /* 0x0000022000007944 */
/* 0x000fea0003c00000 */
/*0390*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03a0*/ LEA R2, P0, R5, c[0x0][0x170], 0x2 ; /* 0x00005c0005027a11 */
/* 0x000fc800078010ff */
/*03b0*/ LEA.HI.X R3, R5, c[0x0][0x174], R0, 0x2, P0 ; /* 0x00005d0005037a11 */
/* 0x000fe400000f1400 */
/*03c0*/ IADD3 R5, R4, c[0x0][0xc], RZ ; /* 0x0000030004057a10 */
/* 0x000fc60007ffe0ff */
/*03d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e2000c101904 */
/*03e0*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fe20003f06070 */
/*03f0*/ IMAD.MOV.U32 R4, RZ, RZ, R5.reuse ; /* 0x000000ffff047224 */
/* 0x100fe200078e0005 */
/*0400*/ SHF.R.S32.HI R0, RZ, 0x1f, R5 ; /* 0x0000001fff007819 */
/* 0x000fc80000011405 */
/*0410*/ ISETP.GE.U32.AND.EX P0, PT, R0, c[0x0][0x16c], PT, P0 ; /* 0x00005b0000007a0c */
/* 0x000fda0003f06100 */
/*0420*/ @!P0 BRA 0xa0 ; /* 0xfffffc7000008947 */
/* 0x001fea000383ffff */
/*0430*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0440*/ LOP3.LUT P0, RZ, R12, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0cff7812 */
/* 0x000fda000780c0ff */
/*0450*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, R12 ; /* 0x000000ffff068224 */
/* 0x000fe200078e000c */
/*0460*/ @!P0 BRA 0x570 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0470*/ FSETP.GEU.FTZ.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720b */
/* 0x000fda0003f1e000 */
/*0480*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, 0x7fffffff ; /* 0x7fffffffff068424 */
/* 0x000fe200078e00ff */
/*0490*/ @!P0 BRA 0x570 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*04a0*/ FSETP.GTU.FTZ.AND P0, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */
/* 0x000fda0003f1c200 */
/*04b0*/ @P0 FADD.FTZ R6, R12, 1 ; /* 0x3f8000000c060421 */
/* 0x000fe20000010000 */
/*04c0*/ @P0 BRA 0x570 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*04d0*/ FSETP.NEU.FTZ.AND P0, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */
/* 0x000fda0003f1d200 */
/*04e0*/ @P0 FFMA R7, R12, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000c070823 */
/* 0x000fc800000000ff */
/*04f0*/ @P0 MUFU.RSQ R6, R7 ; /* 0x0000000700060308 */
/* 0x000e240000001400 */
/*0500*/ @P0 FMUL.FTZ R10, R7, R6 ; /* 0x00000006070a0220 */
/* 0x001fe40000410000 */
/*0510*/ @P0 FMUL.FTZ R11, R6, 0.5 ; /* 0x3f000000060b0820 */
/* 0x000fe40000410000 */
/*0520*/ @P0 FADD.FTZ R9, -R10.reuse, -RZ ; /* 0x800000ff0a090221 */
/* 0x040fe40000010100 */
/*0530*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, R12 ; /* 0x000000ffff068224 */
/* 0x000fe400078e000c */
/*0540*/ @P0 FFMA R9, R10, R9, R7 ; /* 0x000000090a090223 */
/* 0x000fc80000000007 */
/*0550*/ @P0 FFMA R9, R9, R11, R10 ; /* 0x0000000b09090223 */
/* 0x000fc8000000000a */
/*0560*/ @P0 FMUL.FTZ R6, R9, 2.3283064365386962891e-10 ; /* 0x2f80000009060820 */
/* 0x000fc80000410000 */
/*0570*/ IMAD.MOV.U32 R9, RZ, RZ, R6 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0006 */
/*0580*/ IMAD.MOV.U32 R6, RZ, RZ, R13 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000d */
/*0590*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc800078e00ff */
/*05a0*/ RET.REL.NODEC R6 0x0 ; /* 0xfffffa5006007950 */
/* 0x000fea0003c3ffff */
/*05b0*/ SHF.R.U32.HI R6, RZ, 0x17, R10 ; /* 0x00000017ff067819 */
/* 0x000fe2000001160a */
/*05c0*/ BSSY B1, 0xc20 ; /* 0x0000065000017945 */
/* 0x000fe20003800000 */
/*05d0*/ SHF.R.U32.HI R3, RZ, 0x17, R9.reuse ; /* 0x00000017ff037819 */
/* 0x100fe20000011609 */
/*05e0*/ IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0009 */
/*05f0*/ LOP3.LUT R13, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff060d7812 */
/* 0x000fe400078ec0ff */
/*0600*/ LOP3.LUT R11, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff030b7812 */
/* 0x000fe400078ec0ff */
/*0610*/ IADD3 R14, R13, -0x1, RZ ; /* 0xffffffff0d0e7810 */
/* 0x000fe40007ffe0ff */
/*0620*/ IADD3 R12, R11, -0x1, RZ ; /* 0xffffffff0b0c7810 */
/* 0x000fc40007ffe0ff */
/*0630*/ ISETP.GT.U32.AND P0, PT, R14, 0xfd, PT ; /* 0x000000fd0e00780c */
/* 0x000fc80003f04070 */
/*0640*/ ISETP.GT.U32.OR P0, PT, R12, 0xfd, P0 ; /* 0x000000fd0c00780c */
/* 0x000fda0000704470 */
/*0650*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff068224 */
/* 0x000fe200078e00ff */
/*0660*/ @!P0 BRA 0x800 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0670*/ FSETP.GTU.FTZ.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fe20003f1c200 */
/*0680*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0009 */
/*0690*/ FSETP.GTU.FTZ.AND P1, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fe20003f3c200 */
/*06a0*/ IMAD.MOV.U32 R8, RZ, RZ, R10 ; /* 0x000000ffff087224 */
/* 0x000fc600078e000a */
/*06b0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*06c0*/ @P0 BRA 0xc00 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*06d0*/ LOP3.LUT P0, RZ, R10, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff0aff7812 */
/* 0x000fda000780c807 */
/*06e0*/ @!P0 BRA 0xbe0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*06f0*/ FSETP.NEU.FTZ.AND P2, PT, |R3|.reuse, +INF , PT ; /* 0x7f8000000300780b */
/* 0x040fe40003f5d200 */
/*0700*/ FSETP.NEU.FTZ.AND P1, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fe40003f3d200 */
/*0710*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fd60003f1d200 */
/*0720*/ @!P1 BRA !P2, 0xbe0 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0730*/ LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000784c0ff */
/*0740*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0750*/ @P1 BRA 0xbc0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0760*/ LOP3.LUT P1, RZ, R10, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0aff7812 */
/* 0x000fc8000782c0ff */
/*0770*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0780*/ @P0 BRA 0xb90 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0790*/ ISETP.GE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f06270 */
/*07a0*/ ISETP.GE.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fd60003f26270 */
/*07b0*/ @P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff060224 */
/* 0x000fe400078e00ff */
/*07c0*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, -0x40 ; /* 0xffffffc0ff068424 */
/* 0x000fe400078e00ff */
/*07d0*/ @!P0 FFMA R7, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003078823 */
/* 0x000fe400000000ff */
/*07e0*/ @!P1 FFMA R10, R8, 1.84467440737095516160e+19, RZ ; /* 0x5f800000080a9823 */
/* 0x000fe200000000ff */
/*07f0*/ @!P1 IADD3 R6, R6, 0x40, RZ ; /* 0x0000004006069810 */
/* 0x000fe40007ffe0ff */
/*0800*/ LEA R3, R13, 0xc0800000, 0x17 ; /* 0xc08000000d037811 */
/* 0x000fe200078eb8ff */
/*0810*/ BSSY B2, 0xb80 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0820*/ IADD3 R8, R11, -0x7f, RZ ; /* 0xffffff810b087810 */
/* 0x000fc60007ffe0ff */
/*0830*/ IMAD.IADD R10, R10, 0x1, -R3 ; /* 0x000000010a0a7824 */
/* 0x000fe200078e0a03 */
/*0840*/ IADD3 R9, R8.reuse, 0x7f, -R13 ; /* 0x0000007f08097810 */
/* 0x040fe20007ffe80d */
/*0850*/ IMAD R7, R8, -0x800000, R7 ; /* 0xff80000008077824 */
/* 0x000fe400078e0207 */
/*0860*/ MUFU.RCP R3, R10 ; /* 0x0000000a00037308 */
/* 0x000e220000001000 */
/*0870*/ FADD.FTZ R12, -R10, -RZ ; /* 0x800000ff0a0c7221 */
/* 0x000fe40000010100 */
/*0880*/ IMAD.IADD R6, R9, 0x1, R6 ; /* 0x0000000109067824 */
/* 0x000fe400078e0206 */
/*0890*/ FFMA R14, R3, R12, 1 ; /* 0x3f800000030e7423 */
/* 0x001fc8000000000c */
/*08a0*/ FFMA R16, R3, R14, R3 ; /* 0x0000000e03107223 */
/* 0x000fc80000000003 */
/*08b0*/ FFMA R3, R7, R16, RZ ; /* 0x0000001007037223 */
/* 0x000fc800000000ff */
/*08c0*/ FFMA R14, R12, R3, R7 ; /* 0x000000030c0e7223 */
/* 0x000fc80000000007 */
/*08d0*/ FFMA R11, R16, R14, R3 ; /* 0x0000000e100b7223 */
/* 0x000fc80000000003 */
/*08e0*/ FFMA R12, R12, R11, R7 ; /* 0x0000000b0c0c7223 */
/* 0x000fc80000000007 */
/*08f0*/ FFMA R3, R16, R12, R11 ; /* 0x0000000c10037223 */
/* 0x000fca000000000b */
/*0900*/ SHF.R.U32.HI R7, RZ, 0x17, R3 ; /* 0x00000017ff077819 */
/* 0x000fc80000011603 */
/*0910*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fca00078ec0ff */
/*0920*/ IMAD.IADD R10, R7, 0x1, R6 ; /* 0x00000001070a7824 */
/* 0x000fca00078e0206 */
/*0930*/ IADD3 R7, R10, -0x1, RZ ; /* 0xffffffff0a077810 */
/* 0x000fc80007ffe0ff */
/*0940*/ ISETP.GE.U32.AND P0, PT, R7, 0xfe, PT ; /* 0x000000fe0700780c */
/* 0x000fda0003f06070 */
/*0950*/ @!P0 BRA 0xb60 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0960*/ ISETP.GT.AND P0, PT, R10, 0xfe, PT ; /* 0x000000fe0a00780c */
/* 0x000fda0003f04270 */
/*0970*/ @P0 BRA 0xb30 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0980*/ ISETP.GE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fda0003f06270 */
/*0990*/ @P0 BRA 0xb70 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*09a0*/ ISETP.GE.AND P0, PT, R10, -0x18, PT ; /* 0xffffffe80a00780c */
/* 0x000fe40003f06270 */
/*09b0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*09c0*/ @!P0 BRA 0xb70 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*09d0*/ FFMA.RZ R6, R16, R12.reuse, R11.reuse ; /* 0x0000000c10067223 */
/* 0x180fe2000000c00b */
/*09e0*/ IADD3 R9, R10, 0x20, RZ ; /* 0x000000200a097810 */
/* 0x000fe20007ffe0ff */
/*09f0*/ FFMA.RM R7, R16, R12.reuse, R11.reuse ; /* 0x0000000c10077223 */
/* 0x180fe2000000400b */
/*0a00*/ ISETP.NE.AND P2, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f45270 */
/*0a10*/ LOP3.LUT R8, R6, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff06087812 */
/* 0x000fe200078ec0ff */
/*0a20*/ FFMA.RP R6, R16, R12, R11 ; /* 0x0000000c10067223 */
/* 0x000fe2000000800b */
/*0a30*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f25270 */
/*0a40*/ IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0a0a */
/*0a50*/ LOP3.LUT R8, R8, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000008087812 */
/* 0x000fe400078efcff */
/*0a60*/ FSETP.NEU.FTZ.AND P0, PT, R6, R7, PT ; /* 0x000000070600720b */
/* 0x000fc40003f1d000 */
/*0a70*/ SHF.L.U32 R9, R8, R9, RZ ; /* 0x0000000908097219 */
/* 0x000fe400000006ff */
/*0a80*/ SEL R7, R10, RZ, P2 ; /* 0x000000ff0a077207 */
/* 0x000fe40001000000 */
/*0a90*/ ISETP.NE.AND P1, PT, R9, RZ, P1 ; /* 0x000000ff0900720c */
/* 0x000fe40000f25270 */
/*0aa0*/ SHF.R.U32.HI R7, RZ, R7, R8 ; /* 0x00000007ff077219 */
/* 0x000fe40000011608 */
/*0ab0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0ac0*/ SHF.R.U32.HI R9, RZ, 0x1, R7 ; /* 0x00000001ff097819 */
/* 0x000fc40000011607 */
/*0ad0*/ SEL R6, RZ, 0x1, !P0 ; /* 0x00000001ff067807 */
/* 0x000fc80004000000 */
/*0ae0*/ LOP3.LUT R6, R6, 0x1, R9, 0xf8, !PT ; /* 0x0000000106067812 */
/* 0x000fc800078ef809 */
/*0af0*/ LOP3.LUT R6, R6, R7, RZ, 0xc0, !PT ; /* 0x0000000706067212 */
/* 0x000fca00078ec0ff */
/*0b00*/ IMAD.IADD R6, R9, 0x1, R6 ; /* 0x0000000109067824 */
/* 0x000fca00078e0206 */
/*0b10*/ LOP3.LUT R3, R6, R3, RZ, 0xfc, !PT ; /* 0x0000000306037212 */
/* 0x000fe200078efcff */
/*0b20*/ BRA 0xb70 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0b30*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0b40*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0b50*/ BRA 0xb70 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0b60*/ IMAD R3, R6, 0x800000, R3 ; /* 0x0080000006037824 */
/* 0x000fe400078e0203 */
/*0b70*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0b80*/ BRA 0xc10 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0b90*/ LOP3.LUT R3, R10, 0x80000000, R7, 0x48, !PT ; /* 0x800000000a037812 */
/* 0x000fc800078e4807 */
/*0ba0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0bb0*/ BRA 0xc10 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0bc0*/ LOP3.LUT R3, R10, 0x80000000, R7, 0x48, !PT ; /* 0x800000000a037812 */
/* 0x000fe200078e4807 */
/*0bd0*/ BRA 0xc10 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0be0*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*0bf0*/ BRA 0xc10 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0c00*/ FADD.FTZ R3, R3, R8 ; /* 0x0000000803037221 */
/* 0x000fe40000010000 */
/*0c10*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0c20*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x001fe400078e0003 */
/*0c30*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0c40*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff3b002007950 */
/* 0x000fea0003c3ffff */
/*0c50*/ BRA 0xc50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void cosineSimilarityCuda(float3* pDotProducts, size_t pSize, float* results) {
int instance = blockIdx.x * blockDim.x + threadIdx.x;
while (instance < pSize) {
results[instance] = pDotProducts[instance].y / (sqrtf(pDotProducts[instance].x)* sqrtf(pDotProducts[instance].z));
instance += gridDim.x;
}
} | .file "tmpxft_00199f7d_00000000-6_cosineSimilarityCuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z20cosineSimilarityCudaP6float3mPfP6float3mPf
.type _Z49__device_stub__Z20cosineSimilarityCudaP6float3mPfP6float3mPf, @function
_Z49__device_stub__Z20cosineSimilarityCudaP6float3mPfP6float3mPf:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20cosineSimilarityCudaP6float3mPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z20cosineSimilarityCudaP6float3mPfP6float3mPf, .-_Z49__device_stub__Z20cosineSimilarityCudaP6float3mPfP6float3mPf
.globl _Z20cosineSimilarityCudaP6float3mPf
.type _Z20cosineSimilarityCudaP6float3mPf, @function
_Z20cosineSimilarityCudaP6float3mPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z20cosineSimilarityCudaP6float3mPfP6float3mPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20cosineSimilarityCudaP6float3mPf, .-_Z20cosineSimilarityCudaP6float3mPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20cosineSimilarityCudaP6float3mPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20cosineSimilarityCudaP6float3mPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void cosineSimilarityCuda(float3* pDotProducts, size_t pSize, float* results) {
int instance = blockIdx.x * blockDim.x + threadIdx.x;
while (instance < pSize) {
results[instance] = pDotProducts[instance].y / (sqrtf(pDotProducts[instance].x)* sqrtf(pDotProducts[instance].z));
instance += gridDim.x;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cosineSimilarityCuda(float3* pDotProducts, size_t pSize, float* results) {
int instance = blockIdx.x * blockDim.x + threadIdx.x;
while (instance < pSize) {
results[instance] = pDotProducts[instance].y / (sqrtf(pDotProducts[instance].x)* sqrtf(pDotProducts[instance].z));
instance += gridDim.x;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cosineSimilarityCuda(float3* pDotProducts, size_t pSize, float* results) {
int instance = blockIdx.x * blockDim.x + threadIdx.x;
while (instance < pSize) {
results[instance] = pDotProducts[instance].y / (sqrtf(pDotProducts[instance].x)* sqrtf(pDotProducts[instance].z));
instance += gridDim.x;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf
.globl _Z20cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf
.p2align 8
.type _Z20cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf,@function
_Z20cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x8
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s6
s_mov_b32 s6, exec_lo
v_add_nc_u32_e32 v1, s15, v0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[4:5], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b32 s3, s[2:3], 0x0
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
v_add3_u32 v3, s15, s3, v0
.LBB0_2:
v_mad_u64_u32 v[4:5], null, v1, 12, s[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v0, v5
v_mad_u64_u32 v[5:6], null, v2, 12, v[0:1]
global_load_b96 v[4:6], v[4:5], off
s_waitcnt vmcnt(0)
v_dual_mul_f32 v7, 0x4f800000, v6 :: v_dual_mul_f32 v0, 0x4f800000, v4
v_cmp_gt_f32_e64 s0, 0xf800000, v4
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v0, v4, v0, s0
v_cndmask_b32_e32 v4, v6, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sqrt_f32_e32 v6, v0
v_sqrt_f32_e32 v7, v4
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v8, -1, v6
v_add_nc_u32_e32 v10, 1, v6
v_add_nc_u32_e32 v9, -1, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v12, -v8, v6, v0
v_fma_f32 v14, -v10, v6, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v13, -v9, v7, v4
v_cmp_ge_f32_e64 s1, 0, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_f32_e64 s2, 0, v14
v_cndmask_b32_e64 v6, v6, v8, s1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ge_f32_e64 s1, 0, v13
v_cndmask_b32_e64 v6, v6, v10, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v8, 0x37800000, v6 :: v_dual_add_nc_u32 v11, 1, v7
v_fma_f32 v15, -v11, v7, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v7, v7, v9, s1
v_cndmask_b32_e64 v6, v6, v8, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_lt_f32_e64 s1, 0, v15
v_cmp_class_f32_e64 s0, v0, 0x260
v_cndmask_b32_e64 v7, v7, v11, s1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v0, v6, v0, s0
v_mul_f32_e32 v9, 0x37800000, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v7, v7, v9, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v4, 0x260
v_cndmask_b32_e32 v4, v7, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v8, v0, v4
v_ashrrev_i32_e32 v4, 31, v3
v_div_scale_f32 v6, null, v8, v8, v5
v_div_scale_f32 v9, vcc_lo, v5, v8, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_u64_e64 s0, s[4:5], v[3:4]
v_rcp_f32_e32 v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_or_b32 s10, s0, s10
s_waitcnt_depctr 0xfff
v_fma_f32 v0, -v6, v7, 1.0
v_fmac_f32_e32 v7, v0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v10, v9, v7
v_fma_f32 v0, -v6, v10, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v10, v0, v7
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_fma_f32 v2, -v6, v10, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fmas_f32 v9, v2, v7, v10
v_add_co_u32 v6, vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v1, vcc_lo
v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
v_div_fixup_f32 v0, v9, v8, v5
v_add_nc_u32_e32 v3, s3, v3
global_store_b32 v[6:7], v0, off
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf, .Lfunc_end0-_Z20cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cosineSimilarityCuda(float3* pDotProducts, size_t pSize, float* results) {
int instance = blockIdx.x * blockDim.x + threadIdx.x;
while (instance < pSize) {
results[instance] = pDotProducts[instance].y / (sqrtf(pDotProducts[instance].x)* sqrtf(pDotProducts[instance].z));
instance += gridDim.x;
}
} | .text
.file "cosineSimilarityCuda.hip"
.globl _Z35__device_stub__cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf # -- Begin function _Z35__device_stub__cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf
.p2align 4, 0x90
.type _Z35__device_stub__cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf,@function
_Z35__device_stub__cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf: # @_Z35__device_stub__cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z35__device_stub__cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf, .Lfunc_end0-_Z35__device_stub__cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf,@object # @_Z20cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf
.section .rodata,"a",@progbits
.globl _Z20cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf
.p2align 3, 0x0
_Z20cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf:
.quad _Z35__device_stub__cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf
.size _Z20cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf"
.size .L__unnamed_1, 53
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20cosineSimilarityCudaP6float3mPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R0, RZ, 0x1f, R4 ; /* 0x0000001fff007819 */
/* 0x000fc80000011404 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R0, c[0x0][0x16c], PT, P0 ; /* 0x00005b0000007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, R4 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0004 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, 0xc ; /* 0x0000000cff027424 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD R7, R0, 0xc, RZ ; /* 0x0000000c00077824 */
/* 0x000fe400078e02ff */
/*00c0*/ IMAD.WIDE.U32 R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fc800078e0002 */
/*00d0*/ IMAD.IADD R3, R3, 0x1, R7 ; /* 0x0000000103037824 */
/* 0x000fca00078e0207 */
/*00e0*/ LDG.E R12, [R2.64] ; /* 0x00000004020c7981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ BSSY B0, 0x1d0 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0100*/ IADD3 R6, R12, -0xd000000, RZ ; /* 0xf30000000c067810 */
/* 0x004fe20007ffe0ff */
/*0110*/ MUFU.RSQ R7, R12 ; /* 0x0000000c00077308 */
/* 0x0000660000001400 */
/*0120*/ ISETP.GT.U32.AND P0, PT, R6, 0x727fffff, PT ; /* 0x727fffff0600780c */
/* 0x000fda0003f04070 */
/*0130*/ @!P0 BRA 0x180 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0140*/ MOV R13, 0x160 ; /* 0x00000160000d7802 */
/* 0x003fe40000000f00 */
/*0150*/ CALL.REL.NOINC 0x440 ; /* 0x000002e000007944 */
/* 0x000fea0003c00000 */
/*0160*/ IMAD.MOV.U32 R8, RZ, RZ, R9 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0009 */
/*0170*/ BRA 0x1c0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0180*/ FMUL.FTZ R8, R12, R7 ; /* 0x000000070c087220 */
/* 0x003fe40000410000 */
/*0190*/ FMUL.FTZ R6, R7, 0.5 ; /* 0x3f00000007067820 */
/* 0x000fe40000410000 */
/*01a0*/ FFMA R7, -R8, R8, R12 ; /* 0x0000000808077223 */
/* 0x000fc8000000010c */
/*01b0*/ FFMA R8, R7, R6, R8 ; /* 0x0000000607087223 */
/* 0x000fe40000000008 */
/*01c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01d0*/ LDG.E R12, [R2.64+0x8] ; /* 0x00000804020c7981 */
/* 0x000ea2000c1e1900 */
/*01e0*/ BSSY B0, 0x2c0 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*01f0*/ IADD3 R6, R12, -0xd000000, RZ ; /* 0xf30000000c067810 */
/* 0x004fe20007ffe0ff */
/*0200*/ MUFU.RSQ R9, R12 ; /* 0x0000000c00097308 */
/* 0x0000660000001400 */
/*0210*/ ISETP.GT.U32.AND P0, PT, R6, 0x727fffff, PT ; /* 0x727fffff0600780c */
/* 0x000fda0003f04070 */
/*0220*/ @!P0 BRA 0x270 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0230*/ MOV R13, 0x250 ; /* 0x00000250000d7802 */
/* 0x003fe40000000f00 */
/*0240*/ CALL.REL.NOINC 0x440 ; /* 0x000001f000007944 */
/* 0x000fea0003c00000 */
/*0250*/ IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0009 */
/*0260*/ BRA 0x2b0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0270*/ FMUL.FTZ R7, R12, R9 ; /* 0x000000090c077220 */
/* 0x003fe40000410000 */
/*0280*/ FMUL.FTZ R9, R9, 0.5 ; /* 0x3f00000009097820 */
/* 0x000fe40000410000 */
/*0290*/ FFMA R6, -R7, R7, R12 ; /* 0x0000000707067223 */
/* 0x000fc8000000010c */
/*02a0*/ FFMA R7, R6, R9, R7 ; /* 0x0000000906077223 */
/* 0x000fe40000000007 */
/*02b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02c0*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040402097981 */
/* 0x000ea2000c1e1900 */
/*02d0*/ FMUL R10, R7, R8 ; /* 0x00000008070a7220 */
/* 0x000fe20000400000 */
/*02e0*/ BSSY B0, 0x3a0 ; /* 0x000000b000007945 */
/* 0x000fe60003800000 */
/*02f0*/ MUFU.RCP R6, R10 ; /* 0x0000000a00067308 */
/* 0x000e240000001000 */
/*0300*/ FFMA R7, -R10, R6, 1 ; /* 0x3f8000000a077423 */
/* 0x001fc80000000106 */
/*0310*/ FFMA R7, R6, R7, R6 ; /* 0x0000000706077223 */
/* 0x000fe40000000006 */
/*0320*/ FCHK P0, R9, R10 ; /* 0x0000000a09007302 */
/* 0x004e240000000000 */
/*0330*/ FFMA R6, R9, R7, RZ ; /* 0x0000000709067223 */
/* 0x000fc800000000ff */
/*0340*/ FFMA R8, -R10, R6, R9 ; /* 0x000000060a087223 */
/* 0x000fc80000000109 */
/*0350*/ FFMA R7, R7, R8, R6 ; /* 0x0000000807077223 */
/* 0x000fe20000000006 */
/*0360*/ @!P0 BRA 0x390 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*0370*/ MOV R2, 0x390 ; /* 0x0000039000027802 */
/* 0x000fe40000000f00 */
/*0380*/ CALL.REL.NOINC 0x5b0 ; /* 0x0000022000007944 */
/* 0x000fea0003c00000 */
/*0390*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03a0*/ LEA R2, P0, R5, c[0x0][0x170], 0x2 ; /* 0x00005c0005027a11 */
/* 0x000fc800078010ff */
/*03b0*/ LEA.HI.X R3, R5, c[0x0][0x174], R0, 0x2, P0 ; /* 0x00005d0005037a11 */
/* 0x000fe400000f1400 */
/*03c0*/ IADD3 R5, R4, c[0x0][0xc], RZ ; /* 0x0000030004057a10 */
/* 0x000fc60007ffe0ff */
/*03d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e2000c101904 */
/*03e0*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fe20003f06070 */
/*03f0*/ IMAD.MOV.U32 R4, RZ, RZ, R5.reuse ; /* 0x000000ffff047224 */
/* 0x100fe200078e0005 */
/*0400*/ SHF.R.S32.HI R0, RZ, 0x1f, R5 ; /* 0x0000001fff007819 */
/* 0x000fc80000011405 */
/*0410*/ ISETP.GE.U32.AND.EX P0, PT, R0, c[0x0][0x16c], PT, P0 ; /* 0x00005b0000007a0c */
/* 0x000fda0003f06100 */
/*0420*/ @!P0 BRA 0xa0 ; /* 0xfffffc7000008947 */
/* 0x001fea000383ffff */
/*0430*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0440*/ LOP3.LUT P0, RZ, R12, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0cff7812 */
/* 0x000fda000780c0ff */
/*0450*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, R12 ; /* 0x000000ffff068224 */
/* 0x000fe200078e000c */
/*0460*/ @!P0 BRA 0x570 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0470*/ FSETP.GEU.FTZ.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720b */
/* 0x000fda0003f1e000 */
/*0480*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, 0x7fffffff ; /* 0x7fffffffff068424 */
/* 0x000fe200078e00ff */
/*0490*/ @!P0 BRA 0x570 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*04a0*/ FSETP.GTU.FTZ.AND P0, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */
/* 0x000fda0003f1c200 */
/*04b0*/ @P0 FADD.FTZ R6, R12, 1 ; /* 0x3f8000000c060421 */
/* 0x000fe20000010000 */
/*04c0*/ @P0 BRA 0x570 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*04d0*/ FSETP.NEU.FTZ.AND P0, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */
/* 0x000fda0003f1d200 */
/*04e0*/ @P0 FFMA R7, R12, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000c070823 */
/* 0x000fc800000000ff */
/*04f0*/ @P0 MUFU.RSQ R6, R7 ; /* 0x0000000700060308 */
/* 0x000e240000001400 */
/*0500*/ @P0 FMUL.FTZ R10, R7, R6 ; /* 0x00000006070a0220 */
/* 0x001fe40000410000 */
/*0510*/ @P0 FMUL.FTZ R11, R6, 0.5 ; /* 0x3f000000060b0820 */
/* 0x000fe40000410000 */
/*0520*/ @P0 FADD.FTZ R9, -R10.reuse, -RZ ; /* 0x800000ff0a090221 */
/* 0x040fe40000010100 */
/*0530*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, R12 ; /* 0x000000ffff068224 */
/* 0x000fe400078e000c */
/*0540*/ @P0 FFMA R9, R10, R9, R7 ; /* 0x000000090a090223 */
/* 0x000fc80000000007 */
/*0550*/ @P0 FFMA R9, R9, R11, R10 ; /* 0x0000000b09090223 */
/* 0x000fc8000000000a */
/*0560*/ @P0 FMUL.FTZ R6, R9, 2.3283064365386962891e-10 ; /* 0x2f80000009060820 */
/* 0x000fc80000410000 */
/*0570*/ IMAD.MOV.U32 R9, RZ, RZ, R6 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0006 */
/*0580*/ IMAD.MOV.U32 R6, RZ, RZ, R13 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000d */
/*0590*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc800078e00ff */
/*05a0*/ RET.REL.NODEC R6 0x0 ; /* 0xfffffa5006007950 */
/* 0x000fea0003c3ffff */
/*05b0*/ SHF.R.U32.HI R6, RZ, 0x17, R10 ; /* 0x00000017ff067819 */
/* 0x000fe2000001160a */
/*05c0*/ BSSY B1, 0xc20 ; /* 0x0000065000017945 */
/* 0x000fe20003800000 */
/*05d0*/ SHF.R.U32.HI R3, RZ, 0x17, R9.reuse ; /* 0x00000017ff037819 */
/* 0x100fe20000011609 */
/*05e0*/ IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0009 */
/*05f0*/ LOP3.LUT R13, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff060d7812 */
/* 0x000fe400078ec0ff */
/*0600*/ LOP3.LUT R11, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff030b7812 */
/* 0x000fe400078ec0ff */
/*0610*/ IADD3 R14, R13, -0x1, RZ ; /* 0xffffffff0d0e7810 */
/* 0x000fe40007ffe0ff */
/*0620*/ IADD3 R12, R11, -0x1, RZ ; /* 0xffffffff0b0c7810 */
/* 0x000fc40007ffe0ff */
/*0630*/ ISETP.GT.U32.AND P0, PT, R14, 0xfd, PT ; /* 0x000000fd0e00780c */
/* 0x000fc80003f04070 */
/*0640*/ ISETP.GT.U32.OR P0, PT, R12, 0xfd, P0 ; /* 0x000000fd0c00780c */
/* 0x000fda0000704470 */
/*0650*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff068224 */
/* 0x000fe200078e00ff */
/*0660*/ @!P0 BRA 0x800 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0670*/ FSETP.GTU.FTZ.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fe20003f1c200 */
/*0680*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0009 */
/*0690*/ FSETP.GTU.FTZ.AND P1, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fe20003f3c200 */
/*06a0*/ IMAD.MOV.U32 R8, RZ, RZ, R10 ; /* 0x000000ffff087224 */
/* 0x000fc600078e000a */
/*06b0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*06c0*/ @P0 BRA 0xc00 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*06d0*/ LOP3.LUT P0, RZ, R10, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff0aff7812 */
/* 0x000fda000780c807 */
/*06e0*/ @!P0 BRA 0xbe0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*06f0*/ FSETP.NEU.FTZ.AND P2, PT, |R3|.reuse, +INF , PT ; /* 0x7f8000000300780b */
/* 0x040fe40003f5d200 */
/*0700*/ FSETP.NEU.FTZ.AND P1, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fe40003f3d200 */
/*0710*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fd60003f1d200 */
/*0720*/ @!P1 BRA !P2, 0xbe0 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0730*/ LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000784c0ff */
/*0740*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0750*/ @P1 BRA 0xbc0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0760*/ LOP3.LUT P1, RZ, R10, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0aff7812 */
/* 0x000fc8000782c0ff */
/*0770*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0780*/ @P0 BRA 0xb90 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0790*/ ISETP.GE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f06270 */
/*07a0*/ ISETP.GE.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fd60003f26270 */
/*07b0*/ @P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff060224 */
/* 0x000fe400078e00ff */
/*07c0*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, -0x40 ; /* 0xffffffc0ff068424 */
/* 0x000fe400078e00ff */
/*07d0*/ @!P0 FFMA R7, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003078823 */
/* 0x000fe400000000ff */
/*07e0*/ @!P1 FFMA R10, R8, 1.84467440737095516160e+19, RZ ; /* 0x5f800000080a9823 */
/* 0x000fe200000000ff */
/*07f0*/ @!P1 IADD3 R6, R6, 0x40, RZ ; /* 0x0000004006069810 */
/* 0x000fe40007ffe0ff */
/*0800*/ LEA R3, R13, 0xc0800000, 0x17 ; /* 0xc08000000d037811 */
/* 0x000fe200078eb8ff */
/*0810*/ BSSY B2, 0xb80 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0820*/ IADD3 R8, R11, -0x7f, RZ ; /* 0xffffff810b087810 */
/* 0x000fc60007ffe0ff */
/*0830*/ IMAD.IADD R10, R10, 0x1, -R3 ; /* 0x000000010a0a7824 */
/* 0x000fe200078e0a03 */
/*0840*/ IADD3 R9, R8.reuse, 0x7f, -R13 ; /* 0x0000007f08097810 */
/* 0x040fe20007ffe80d */
/*0850*/ IMAD R7, R8, -0x800000, R7 ; /* 0xff80000008077824 */
/* 0x000fe400078e0207 */
/*0860*/ MUFU.RCP R3, R10 ; /* 0x0000000a00037308 */
/* 0x000e220000001000 */
/*0870*/ FADD.FTZ R12, -R10, -RZ ; /* 0x800000ff0a0c7221 */
/* 0x000fe40000010100 */
/*0880*/ IMAD.IADD R6, R9, 0x1, R6 ; /* 0x0000000109067824 */
/* 0x000fe400078e0206 */
/*0890*/ FFMA R14, R3, R12, 1 ; /* 0x3f800000030e7423 */
/* 0x001fc8000000000c */
/*08a0*/ FFMA R16, R3, R14, R3 ; /* 0x0000000e03107223 */
/* 0x000fc80000000003 */
/*08b0*/ FFMA R3, R7, R16, RZ ; /* 0x0000001007037223 */
/* 0x000fc800000000ff */
/*08c0*/ FFMA R14, R12, R3, R7 ; /* 0x000000030c0e7223 */
/* 0x000fc80000000007 */
/*08d0*/ FFMA R11, R16, R14, R3 ; /* 0x0000000e100b7223 */
/* 0x000fc80000000003 */
/*08e0*/ FFMA R12, R12, R11, R7 ; /* 0x0000000b0c0c7223 */
/* 0x000fc80000000007 */
/*08f0*/ FFMA R3, R16, R12, R11 ; /* 0x0000000c10037223 */
/* 0x000fca000000000b */
/*0900*/ SHF.R.U32.HI R7, RZ, 0x17, R3 ; /* 0x00000017ff077819 */
/* 0x000fc80000011603 */
/*0910*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fca00078ec0ff */
/*0920*/ IMAD.IADD R10, R7, 0x1, R6 ; /* 0x00000001070a7824 */
/* 0x000fca00078e0206 */
/*0930*/ IADD3 R7, R10, -0x1, RZ ; /* 0xffffffff0a077810 */
/* 0x000fc80007ffe0ff */
/*0940*/ ISETP.GE.U32.AND P0, PT, R7, 0xfe, PT ; /* 0x000000fe0700780c */
/* 0x000fda0003f06070 */
/*0950*/ @!P0 BRA 0xb60 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0960*/ ISETP.GT.AND P0, PT, R10, 0xfe, PT ; /* 0x000000fe0a00780c */
/* 0x000fda0003f04270 */
/*0970*/ @P0 BRA 0xb30 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0980*/ ISETP.GE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fda0003f06270 */
/*0990*/ @P0 BRA 0xb70 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*09a0*/ ISETP.GE.AND P0, PT, R10, -0x18, PT ; /* 0xffffffe80a00780c */
/* 0x000fe40003f06270 */
/*09b0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*09c0*/ @!P0 BRA 0xb70 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*09d0*/ FFMA.RZ R6, R16, R12.reuse, R11.reuse ; /* 0x0000000c10067223 */
/* 0x180fe2000000c00b */
/*09e0*/ IADD3 R9, R10, 0x20, RZ ; /* 0x000000200a097810 */
/* 0x000fe20007ffe0ff */
/*09f0*/ FFMA.RM R7, R16, R12.reuse, R11.reuse ; /* 0x0000000c10077223 */
/* 0x180fe2000000400b */
/*0a00*/ ISETP.NE.AND P2, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f45270 */
/*0a10*/ LOP3.LUT R8, R6, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff06087812 */
/* 0x000fe200078ec0ff */
/*0a20*/ FFMA.RP R6, R16, R12, R11 ; /* 0x0000000c10067223 */
/* 0x000fe2000000800b */
/*0a30*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f25270 */
/*0a40*/ IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0a0a */
/*0a50*/ LOP3.LUT R8, R8, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000008087812 */
/* 0x000fe400078efcff */
/*0a60*/ FSETP.NEU.FTZ.AND P0, PT, R6, R7, PT ; /* 0x000000070600720b */
/* 0x000fc40003f1d000 */
/*0a70*/ SHF.L.U32 R9, R8, R9, RZ ; /* 0x0000000908097219 */
/* 0x000fe400000006ff */
/*0a80*/ SEL R7, R10, RZ, P2 ; /* 0x000000ff0a077207 */
/* 0x000fe40001000000 */
/*0a90*/ ISETP.NE.AND P1, PT, R9, RZ, P1 ; /* 0x000000ff0900720c */
/* 0x000fe40000f25270 */
/*0aa0*/ SHF.R.U32.HI R7, RZ, R7, R8 ; /* 0x00000007ff077219 */
/* 0x000fe40000011608 */
/*0ab0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0ac0*/ SHF.R.U32.HI R9, RZ, 0x1, R7 ; /* 0x00000001ff097819 */
/* 0x000fc40000011607 */
/*0ad0*/ SEL R6, RZ, 0x1, !P0 ; /* 0x00000001ff067807 */
/* 0x000fc80004000000 */
/*0ae0*/ LOP3.LUT R6, R6, 0x1, R9, 0xf8, !PT ; /* 0x0000000106067812 */
/* 0x000fc800078ef809 */
/*0af0*/ LOP3.LUT R6, R6, R7, RZ, 0xc0, !PT ; /* 0x0000000706067212 */
/* 0x000fca00078ec0ff */
/*0b00*/ IMAD.IADD R6, R9, 0x1, R6 ; /* 0x0000000109067824 */
/* 0x000fca00078e0206 */
/*0b10*/ LOP3.LUT R3, R6, R3, RZ, 0xfc, !PT ; /* 0x0000000306037212 */
/* 0x000fe200078efcff */
/*0b20*/ BRA 0xb70 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0b30*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0b40*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0b50*/ BRA 0xb70 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0b60*/ IMAD R3, R6, 0x800000, R3 ; /* 0x0080000006037824 */
/* 0x000fe400078e0203 */
/*0b70*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0b80*/ BRA 0xc10 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0b90*/ LOP3.LUT R3, R10, 0x80000000, R7, 0x48, !PT ; /* 0x800000000a037812 */
/* 0x000fc800078e4807 */
/*0ba0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0bb0*/ BRA 0xc10 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0bc0*/ LOP3.LUT R3, R10, 0x80000000, R7, 0x48, !PT ; /* 0x800000000a037812 */
/* 0x000fe200078e4807 */
/*0bd0*/ BRA 0xc10 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0be0*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*0bf0*/ BRA 0xc10 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0c00*/ FADD.FTZ R3, R3, R8 ; /* 0x0000000803037221 */
/* 0x000fe40000010000 */
/*0c10*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0c20*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x001fe400078e0003 */
/*0c30*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0c40*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff3b002007950 */
/* 0x000fea0003c3ffff */
/*0c50*/ BRA 0xc50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf
.globl _Z20cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf
.p2align 8
.type _Z20cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf,@function
_Z20cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x8
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s6
s_mov_b32 s6, exec_lo
v_add_nc_u32_e32 v1, s15, v0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[4:5], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b32 s3, s[2:3], 0x0
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
v_add3_u32 v3, s15, s3, v0
.LBB0_2:
v_mad_u64_u32 v[4:5], null, v1, 12, s[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v0, v5
v_mad_u64_u32 v[5:6], null, v2, 12, v[0:1]
global_load_b96 v[4:6], v[4:5], off
s_waitcnt vmcnt(0)
v_dual_mul_f32 v7, 0x4f800000, v6 :: v_dual_mul_f32 v0, 0x4f800000, v4
v_cmp_gt_f32_e64 s0, 0xf800000, v4
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v0, v4, v0, s0
v_cndmask_b32_e32 v4, v6, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sqrt_f32_e32 v6, v0
v_sqrt_f32_e32 v7, v4
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v8, -1, v6
v_add_nc_u32_e32 v10, 1, v6
v_add_nc_u32_e32 v9, -1, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v12, -v8, v6, v0
v_fma_f32 v14, -v10, v6, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v13, -v9, v7, v4
v_cmp_ge_f32_e64 s1, 0, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_f32_e64 s2, 0, v14
v_cndmask_b32_e64 v6, v6, v8, s1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ge_f32_e64 s1, 0, v13
v_cndmask_b32_e64 v6, v6, v10, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v8, 0x37800000, v6 :: v_dual_add_nc_u32 v11, 1, v7
v_fma_f32 v15, -v11, v7, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v7, v7, v9, s1
v_cndmask_b32_e64 v6, v6, v8, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_lt_f32_e64 s1, 0, v15
v_cmp_class_f32_e64 s0, v0, 0x260
v_cndmask_b32_e64 v7, v7, v11, s1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v0, v6, v0, s0
v_mul_f32_e32 v9, 0x37800000, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v7, v7, v9, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v4, 0x260
v_cndmask_b32_e32 v4, v7, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v8, v0, v4
v_ashrrev_i32_e32 v4, 31, v3
v_div_scale_f32 v6, null, v8, v8, v5
v_div_scale_f32 v9, vcc_lo, v5, v8, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_u64_e64 s0, s[4:5], v[3:4]
v_rcp_f32_e32 v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_or_b32 s10, s0, s10
s_waitcnt_depctr 0xfff
v_fma_f32 v0, -v6, v7, 1.0
v_fmac_f32_e32 v7, v0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v10, v9, v7
v_fma_f32 v0, -v6, v10, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v10, v0, v7
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_fma_f32 v2, -v6, v10, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fmas_f32 v9, v2, v7, v10
v_add_co_u32 v6, vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v1, vcc_lo
v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
v_div_fixup_f32 v0, v9, v8, v5
v_add_nc_u32_e32 v3, s3, v3
global_store_b32 v[6:7], v0, off
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf, .Lfunc_end0-_Z20cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20cosineSimilarityCudaP15HIP_vector_typeIfLj3EEmPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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