system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019d4e9_00000000-6_helloworld.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z8mykernelvv
.type _Z26__device_stub__Z8mykernelvv, @function
_Z26__device_stub__Z8mykernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8mykernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z8mykernelvv, .-_Z26__device_stub__Z8mykernelvv
.globl _Z8mykernelv
.type _Z8mykernelv, @function
_Z8mykernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8mykernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8mykernelv, .-_Z8mykernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CPU Hello World!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z26__device_stub__Z8mykernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z8mykernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8mykernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "helloworld.hip"
.globl _Z23__device_stub__mykernelv # -- Begin function _Z23__device_stub__mykernelv
.p2align 4, 0x90
.type _Z23__device_stub__mykernelv,@function
_Z23__device_stub__mykernelv: # @_Z23__device_stub__mykernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8mykernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z23__device_stub__mykernelv, .Lfunc_end0-_Z23__device_stub__mykernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8mykernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8mykernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8mykernelv,@object # @_Z8mykernelv
.section .rodata,"a",@progbits
.globl _Z8mykernelv
.p2align 3, 0x0
_Z8mykernelv:
.quad _Z23__device_stub__mykernelv
.size _Z8mykernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8mykernelv"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "CPU Hello World!"
.size .Lstr, 17
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__mykernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8mykernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__device__ void MakeCountSegment(float *segment, int *bins, const int seglength, int *segCounter, const int countlength, const float low, const float high, const float slope)
{
int bin;
float temp;
for (int jj=0; jj<seglength; jj++){
temp = abs(segment[jj]);
if ( ( temp > low ) & ( temp < high ) ) {
bin = (int)ceil(slope*abs(high-temp));
}
else if (temp >= high) {
bin = 0;
}
else bin = countlength - 1;
bins[jj]=bin;
segCounter[bin] = segCounter[bin] + 1;
}
return;
}
__global__ void make_and_count_seg(float *vec, int *bin, int *segcounter, const int length, const int countlength, const int HighLength, const int HighSegmentLength, const int threadsHigh, const int LowSegmentLength, const float low, const float high, const float slope)
{
int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
int startIndex, SegmentLength, startCountIndex;
startCountIndex = xIndex*countlength;
if ( (xIndex*HighSegmentLength > HighLength) & ( (HighLength + (xIndex-threadsHigh+1)*LowSegmentLength) < length ) ){
startIndex = HighLength + (xIndex-threadsHigh)*LowSegmentLength;
SegmentLength = LowSegmentLength;
}
else {
startIndex = xIndex*HighSegmentLength;
SegmentLength = HighSegmentLength;
}
MakeCountSegment(vec+startIndex, bin+startIndex, SegmentLength, segcounter+startCountIndex, countlength, low, high, slope);
} | code for sm_80
Function : _Z18make_and_count_segPfPiS0_iiiiiifff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff057624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fe400078e0203 */
/*0050*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff037624 */
/* 0x000fe400078e00ff */
/*0060*/ IMAD R7, R4.reuse, c[0x0][0x184], RZ ; /* 0x0000610004077a24 */
/* 0x040fe200078e02ff */
/*0070*/ IADD3 R2, R4, -c[0x0][0x188], RZ ; /* 0x8000620004027a10 */
/* 0x000fc80007ffe0ff */
/*0080*/ IADD3 R0, R2, 0x1, RZ ; /* 0x0000000102007810 */
/* 0x000fca0007ffe0ff */
/*0090*/ IMAD R0, R0, c[0x0][0x18c], R5 ; /* 0x0000630000007a24 */
/* 0x000fca00078e0205 */
/*00a0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06270 */
/*00b0*/ ISETP.GT.AND P0, PT, R7, c[0x0][0x180], !P0 ; /* 0x0000600007007a0c */
/* 0x000fc80004704270 */
/*00c0*/ SEL R3, R3, c[0x0][0x184], P0 ; /* 0x0000610003037a07 */
/* 0x000fc80000000000 */
/*00d0*/ ISETP.GE.AND P1, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fda0003f26270 */
/*00e0*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R6, R3.reuse, -0x1, RZ ; /* 0xffffffff03067810 */
/* 0x040fe20007ffe0ff */
/*0100*/ @P0 IMAD R7, R2, c[0x0][0x18c], R5 ; /* 0x0000630002070a24 */
/* 0x000fe200078e0205 */
/*0110*/ LOP3.LUT R0, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303007812 */
/* 0x000fe200078ec0ff */
/*0120*/ IMAD R4, R4, c[0x0][0x17c], RZ ; /* 0x00005f0004047a24 */
/* 0x000fe200078e02ff */
/*0130*/ ISETP.GE.U32.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe20003f06070 */
/*0140*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fe200078e00ff */
/*0150*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0160*/ BSSY B0, 0x700 ; /* 0x0000059000007945 */
/* 0x000fe20003800000 */
/*0170*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f25270 */
/*0180*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*0190*/ SHF.R.S32.HI R10, RZ, 0x1f, R7 ; /* 0x0000001fff0a7819 */
/* 0x000fc40000011407 */
/*01a0*/ IADD3 R5, -R5, c[0x0][0x17c], RZ ; /* 0x00005f0005057a10 */
/* 0x000fe40007ffe1ff */
/*01b0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */
/* 0x000fc60000011404 */
/*01c0*/ @!P0 BRA 0x6f0 ; /* 0x0000052000008947 */
/* 0x000fea0003800000 */
/*01d0*/ IMAD.SHL.U32 R17, R7.reuse, 0x4, RZ ; /* 0x0000000407117824 */
/* 0x040fe200078e00ff */
/*01e0*/ SHF.L.U64.HI R18, R7, 0x2, R10 ; /* 0x0000000207127819 */
/* 0x000fe2000001020a */
/*01f0*/ IMAD.IADD R12, R3, 0x1, -R0 ; /* 0x00000001030c7824 */
/* 0x000fe400078e0a00 */
/*0200*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*0210*/ IADD3 R2, P0, R17.reuse, c[0x0][0x160], RZ ; /* 0x0000580011027a10 */
/* 0x040fe40007f1e0ff */
/*0220*/ IADD3 R17, P2, R17, c[0x0][0x168], RZ ; /* 0x00005a0011117a10 */
/* 0x000fe40007f5e0ff */
/*0230*/ IADD3.X R3, R18.reuse, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590012037a10 */
/* 0x040fe400007fe4ff */
/*0240*/ IADD3.X R18, R18, c[0x0][0x16c], RZ, P2, !PT ; /* 0x00005b0012127a10 */
/* 0x000fc600017fe4ff */
/*0250*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x002ea4000c1e1900 */
/*0260*/ FSETP.GEU.AND P0, PT, |R9|, c[0x0][0x194], PT ; /* 0x0000650009007a0b */
/* 0x004fc80003f0e200 */
/*0270*/ FSETP.GT.AND P0, PT, |R9|, c[0x0][0x190], !P0 ; /* 0x0000640009007a0b */
/* 0x000fda0004704200 */
/*0280*/ @!P0 FSETP.GE.AND P2, PT, |R9|.reuse, c[0x0][0x194], PT ; /* 0x0000650009008a0b */
/* 0x040fe20003f46200 */
/*0290*/ @P0 FADD R8, -|R9|, c[0x0][0x194] ; /* 0x0000650009080621 */
/* 0x000fc60000000300 */
/*02a0*/ @!P0 SEL R13, R5, RZ, !P2 ; /* 0x000000ff050d8207 */
/* 0x000fe20005000000 */
/*02b0*/ @P0 FMUL R8, |R8|, c[0x0][0x198] ; /* 0x0000660008080a20 */
/* 0x000fca0000400200 */
/*02c0*/ @P0 F2I.CEIL.NTZ R13, R8 ; /* 0x00000008000d0305 */
/* 0x000064000020b100 */
/*02d0*/ IMAD.MOV.U32 R8, RZ, RZ, R17 ; /* 0x000000ffff087224 */
/* 0x001fe200078e0011 */
/*02e0*/ IADD3 R9, P0, R4, R13, RZ ; /* 0x0000000d04097210 */
/* 0x002fc80007f1e0ff */
/*02f0*/ LEA.HI.X.SX32 R16, R13, R6, 0x1, P0 ; /* 0x000000060d107211 */
/* 0x000fe400000f0eff */
/*0300*/ LEA R14, P0, R9, c[0x0][0x170], 0x2 ; /* 0x00005c00090e7a11 */
/* 0x000fc800078010ff */
/*0310*/ LEA.HI.X R15, R9, c[0x0][0x174], R16, 0x2, P0 ; /* 0x00005d00090f7a11 */
/* 0x000fe200000f1410 */
/*0320*/ IMAD.MOV.U32 R9, RZ, RZ, R18 ; /* 0x000000ffff097224 */
/* 0x000fca00078e0012 */
/*0330*/ STG.E [R8.64], R13 ; /* 0x0000000d08007986 */
/* 0x0001e8000c101904 */
/*0340*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ea4000c1e1900 */
/*0350*/ IADD3 R17, R16, 0x1, RZ ; /* 0x0000000110117810 */
/* 0x004fca0007ffe0ff */
/*0360*/ STG.E [R14.64], R17 ; /* 0x000000110e007986 */
/* 0x0003e8000c101904 */
/*0370*/ LDG.E R18, [R2.64+0x4] ; /* 0x0000040402127981 */
/* 0x000ea4000c1e1900 */
/*0380*/ FSETP.GEU.AND P0, PT, |R18|, c[0x0][0x194], PT ; /* 0x0000650012007a0b */
/* 0x004fc80003f0e200 */
/*0390*/ FSETP.GT.AND P0, PT, |R18|, c[0x0][0x190], !P0 ; /* 0x0000640012007a0b */
/* 0x000fda0004704200 */
/*03a0*/ @!P0 FSETP.GE.AND P2, PT, |R18|.reuse, c[0x0][0x194], PT ; /* 0x0000650012008a0b */
/* 0x040fe20003f46200 */
/*03b0*/ @P0 FADD R16, -|R18|, c[0x0][0x194] ; /* 0x0000650012100621 */
/* 0x000fc60000000300 */
/*03c0*/ @!P0 SEL R19, R5, RZ, !P2 ; /* 0x000000ff05138207 */
/* 0x000fe20005000000 */
/*03d0*/ @P0 FMUL R16, |R16|, c[0x0][0x198] ; /* 0x0000660010100a20 */
/* 0x000fca0000400200 */
/*03e0*/ @P0 F2I.CEIL.NTZ R19, R16 ; /* 0x0000001000130305 */
/* 0x000e24000020b100 */
/*03f0*/ IADD3 R13, P0, R4, R19, RZ ; /* 0x00000013040d7210 */
/* 0x001fe20007f1e0ff */
/*0400*/ STG.E [R8.64+0x4], R19 ; /* 0x0000041308007986 */
/* 0x0001e6000c101904 */
/*0410*/ LEA.HI.X.SX32 R18, R19, R6, 0x1, P0 ; /* 0x0000000613127211 */
/* 0x000fe400000f0eff */
/*0420*/ LEA R14, P0, R13, c[0x0][0x170], 0x2 ; /* 0x00005c000d0e7a11 */
/* 0x002fc800078010ff */
/*0430*/ LEA.HI.X R15, R13, c[0x0][0x174], R18, 0x2, P0 ; /* 0x00005d000d0f7a11 */
/* 0x000fca00000f1412 */
/*0440*/ LDG.E R13, [R14.64] ; /* 0x000000040e0d7981 */
/* 0x000ea4000c1e1900 */
/*0450*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x004fca0007ffe0ff */
/*0460*/ STG.E [R14.64], R13 ; /* 0x0000000d0e007986 */
/* 0x0003e8000c101904 */
/*0470*/ LDG.E R17, [R2.64+0x8] ; /* 0x0000080402117981 */
/* 0x000ea4000c1e1900 */
/*0480*/ FSETP.GEU.AND P0, PT, |R17|, c[0x0][0x194], PT ; /* 0x0000650011007a0b */
/* 0x004fc80003f0e200 */
/*0490*/ FSETP.GT.AND P0, PT, |R17|, c[0x0][0x190], !P0 ; /* 0x0000640011007a0b */
/* 0x000fda0004704200 */
/*04a0*/ @!P0 FSETP.GE.AND P2, PT, |R17|.reuse, c[0x0][0x194], PT ; /* 0x0000650011008a0b */
/* 0x040fe20003f46200 */
/*04b0*/ @P0 FADD R16, -|R17|, c[0x0][0x194] ; /* 0x0000650011100621 */
/* 0x000fc60000000300 */
/*04c0*/ @!P0 SEL R17, R5, RZ, !P2 ; /* 0x000000ff05118207 */
/* 0x000fe20005000000 */
/*04d0*/ @P0 FMUL R16, |R16|, c[0x0][0x198] ; /* 0x0000660010100a20 */
/* 0x000fca0000400200 */
/*04e0*/ @P0 F2I.CEIL.NTZ R17, R16 ; /* 0x0000001000110305 */
/* 0x000ea4000020b100 */
/*04f0*/ IADD3 R18, P0, R4, R17, RZ ; /* 0x0000001104127210 */
/* 0x004fe20007f1e0ff */
/*0500*/ STG.E [R8.64+0x8], R17 ; /* 0x0000081108007986 */
/* 0x0005e6000c101904 */
/*0510*/ LEA.HI.X.SX32 R19, R17, R6, 0x1, P0 ; /* 0x0000000611137211 */
/* 0x001fe400000f0eff */
/*0520*/ LEA R14, P0, R18, c[0x0][0x170], 0x2 ; /* 0x00005c00120e7a11 */
/* 0x002fc800078010ff */
/*0530*/ LEA.HI.X R15, R18, c[0x0][0x174], R19, 0x2, P0 ; /* 0x00005d00120f7a11 */
/* 0x000fca00000f1413 */
/*0540*/ LDG.E R13, [R14.64] ; /* 0x000000040e0d7981 */
/* 0x000ee4000c1e1900 */
/*0550*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x008fca0007ffe0ff */
/*0560*/ STG.E [R14.64], R13 ; /* 0x0000000d0e007986 */
/* 0x0001e8000c101904 */
/*0570*/ LDG.E R18, [R2.64+0xc] ; /* 0x00000c0402127981 */
/* 0x000ee4000c1e1900 */
/*0580*/ FSETP.GEU.AND P0, PT, |R18|, c[0x0][0x194], PT ; /* 0x0000650012007a0b */
/* 0x008fc80003f0e200 */
/*0590*/ FSETP.GT.AND P0, PT, |R18|, c[0x0][0x190], !P0 ; /* 0x0000640012007a0b */
/* 0x000fda0004704200 */
/*05a0*/ @!P0 FSETP.GE.AND P2, PT, |R18|.reuse, c[0x0][0x194], PT ; /* 0x0000650012008a0b */
/* 0x040fe20003f46200 */
/*05b0*/ @P0 FADD R16, -|R18|, c[0x0][0x194] ; /* 0x0000650012100621 */
/* 0x000fc60000000300 */
/*05c0*/ @!P0 SEL R19, R5, RZ, !P2 ; /* 0x000000ff05138207 */
/* 0x000fe20005000000 */
/*05d0*/ @P0 FMUL R16, |R16|, c[0x0][0x198] ; /* 0x0000660010100a20 */
/* 0x000fca0000400200 */
/*05e0*/ @P0 F2I.CEIL.NTZ R19, R16 ; /* 0x0000001000130305 */
/* 0x000ea4000020b100 */
/*05f0*/ IADD3 R17, P0, R4, R19, RZ ; /* 0x0000001304117210 */
/* 0x004fe20007f1e0ff */
/*0600*/ STG.E [R8.64+0xc], R19 ; /* 0x00000c1308007986 */
/* 0x0003e6000c101904 */
/*0610*/ LEA.HI.X.SX32 R18, R19, R6, 0x1, P0 ; /* 0x0000000613127211 */
/* 0x000fe400000f0eff */
/*0620*/ LEA R14, P0, R17, c[0x0][0x170], 0x2 ; /* 0x00005c00110e7a11 */
/* 0x001fc800078010ff */
/*0630*/ LEA.HI.X R15, R17, c[0x0][0x174], R18, 0x2, P0 ; /* 0x00005d00110f7a11 */
/* 0x000fca00000f1412 */
/*0640*/ LDG.E R13, [R14.64] ; /* 0x000000040e0d7981 */
/* 0x000ea2000c1e1900 */
/*0650*/ IADD3 R12, R12, -0x4, RZ ; /* 0xfffffffc0c0c7810 */
/* 0x000fe40007ffe0ff */
/*0660*/ IADD3 R17, P3, R8, 0x10, RZ ; /* 0x0000001008117810 */
/* 0x000fe40007f7e0ff */
/*0670*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f05270 */
/*0680*/ IADD3 R2, P2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe20007f5e0ff */
/*0690*/ IMAD.X R18, RZ, RZ, R9, P3 ; /* 0x000000ffff127224 */
/* 0x000fe200018e0609 */
/*06a0*/ IADD3 R11, R11, 0x4, RZ ; /* 0x000000040b0b7810 */
/* 0x000fc60007ffe0ff */
/*06b0*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*06c0*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x004fca0007ffe0ff */
/*06d0*/ STG.E [R14.64], R13 ; /* 0x0000000d0e007986 */
/* 0x0003e2000c101904 */
/*06e0*/ @P0 BRA 0x250 ; /* 0xfffffb6000000947 */
/* 0x000fea000383ffff */
/*06f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0700*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0710*/ IADD3 R7, P0, R7, R11, RZ ; /* 0x0000000b07077210 */
/* 0x000fc80007f1e0ff */
/*0720*/ LEA.HI.X.SX32 R10, R11, R10, 0x1, P0 ; /* 0x0000000a0b0a7211 */
/* 0x000fe200000f0eff */
/*0730*/ IMAD.SHL.U32 R12, R7, 0x4, RZ ; /* 0x00000004070c7824 */
/* 0x000fc600078e00ff */
/*0740*/ SHF.L.U64.HI R15, R7, 0x2, R10 ; /* 0x00000002070f7819 */
/* 0x002fe4000001020a */
/*0750*/ IADD3 R14, P0, R12.reuse, c[0x0][0x168], RZ ; /* 0x00005a000c0e7a10 */
/* 0x040fe40007f1e0ff */
/*0760*/ IADD3 R12, P1, R12, c[0x0][0x160], RZ ; /* 0x000058000c0c7a10 */
/* 0x000fe40007f3e0ff */
/*0770*/ IADD3.X R17, R15.reuse, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b000f117a10 */
/* 0x040fe400007fe4ff */
/*0780*/ IADD3.X R15, R15, c[0x0][0x164], RZ, P1, !PT ; /* 0x000059000f0f7a10 */
/* 0x000fc60000ffe4ff */
/*0790*/ IMAD.MOV.U32 R8, RZ, RZ, R12 ; /* 0x000000ffff087224 */
/* 0x001fe400078e000c */
/*07a0*/ IMAD.MOV.U32 R9, RZ, RZ, R15 ; /* 0x000000ffff097224 */
/* 0x000fca00078e000f */
/*07b0*/ LDG.E R3, [R8.64] ; /* 0x0000000408037981 */
/* 0x0000a4000c1e1900 */
/*07c0*/ IMAD.MOV.U32 R8, RZ, RZ, R14 ; /* 0x000000ffff087224 */
/* 0x001fe400078e000e */
/*07d0*/ IMAD.MOV.U32 R9, RZ, RZ, R17 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0011 */
/*07e0*/ FSETP.GEU.AND P0, PT, |R3|, c[0x0][0x194], PT ; /* 0x0000650003007a0b */
/* 0x004fc80003f0e200 */
/*07f0*/ FSETP.GT.AND P0, PT, |R3|, c[0x0][0x190], !P0 ; /* 0x0000640003007a0b */
/* 0x000fda0004704200 */
/*0800*/ @!P0 FSETP.GE.AND P1, PT, |R3|.reuse, c[0x0][0x194], PT ; /* 0x0000650003008a0b */
/* 0x040fe20003f26200 */
/*0810*/ @P0 FADD R2, -|R3|, c[0x0][0x194] ; /* 0x0000650003020621 */
/* 0x000fc60000000300 */
/*0820*/ @!P0 SEL R11, R5, RZ, !P1 ; /* 0x000000ff050b8207 */
/* 0x000fe20004800000 */
/*0830*/ @P0 FMUL R7, |R2|, c[0x0][0x198] ; /* 0x0000660002070a20 */
/* 0x000fca0000400200 */
/*0840*/ @P0 F2I.CEIL.NTZ R11, R7 ; /* 0x00000007000b0305 */
/* 0x000e24000020b100 */
/*0850*/ IADD3 R3, P0, R4, R11, RZ ; /* 0x0000000b04037210 */
/* 0x001fe20007f1e0ff */
/*0860*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x0001e6000c101904 */
/*0870*/ LEA.HI.X.SX32 R10, R11, R6, 0x1, P0 ; /* 0x000000060b0a7211 */
/* 0x000fe400000f0eff */
/*0880*/ LEA R2, P0, R3, c[0x0][0x170], 0x2 ; /* 0x00005c0003027a11 */
/* 0x000fc800078010ff */
/*0890*/ LEA.HI.X R3, R3, c[0x0][0x174], R10, 0x2, P0 ; /* 0x00005d0003037a11 */
/* 0x000fca00000f140a */
/*08a0*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ea2000c1e1900 */
/*08b0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe40007ffe0ff */
/*08c0*/ IADD3 R14, P1, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fe40007f3e0ff */
/*08d0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*08e0*/ IADD3 R12, P2, R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fe20007f5e0ff */
/*08f0*/ IMAD.X R17, RZ, RZ, R17, P1 ; /* 0x000000ffff117224 */
/* 0x000fc800008e0611 */
/*0900*/ IMAD.X R15, RZ, RZ, R15, P2 ; /* 0x000000ffff0f7224 */
/* 0x000fe200010e060f */
/*0910*/ IADD3 R13, R10, 0x1, RZ ; /* 0x000000010a0d7810 */
/* 0x004fca0007ffe0ff */
/*0920*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e2000c101904 */
/*0930*/ @P0 BRA 0x790 ; /* 0xfffffe5000000947 */
/* 0x000fea000383ffff */
/*0940*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0950*/ BRA 0x950; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ void MakeCountSegment(float *segment, int *bins, const int seglength, int *segCounter, const int countlength, const float low, const float high, const float slope)
{
int bin;
float temp;
for (int jj=0; jj<seglength; jj++){
temp = abs(segment[jj]);
if ( ( temp > low ) & ( temp < high ) ) {
bin = (int)ceil(slope*abs(high-temp));
}
else if (temp >= high) {
bin = 0;
}
else bin = countlength - 1;
bins[jj]=bin;
segCounter[bin] = segCounter[bin] + 1;
}
return;
}
__global__ void make_and_count_seg(float *vec, int *bin, int *segcounter, const int length, const int countlength, const int HighLength, const int HighSegmentLength, const int threadsHigh, const int LowSegmentLength, const float low, const float high, const float slope)
{
int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
int startIndex, SegmentLength, startCountIndex;
startCountIndex = xIndex*countlength;
if ( (xIndex*HighSegmentLength > HighLength) & ( (HighLength + (xIndex-threadsHigh+1)*LowSegmentLength) < length ) ){
startIndex = HighLength + (xIndex-threadsHigh)*LowSegmentLength;
SegmentLength = LowSegmentLength;
}
else {
startIndex = xIndex*HighSegmentLength;
SegmentLength = HighSegmentLength;
}
MakeCountSegment(vec+startIndex, bin+startIndex, SegmentLength, segcounter+startCountIndex, countlength, low, high, slope);
} | .file "tmpxft_0008c74b_00000000-6_make_and_count_seg.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z16MakeCountSegmentPfPiiS0_ifff
.type _Z16MakeCountSegmentPfPiiS0_ifff, @function
_Z16MakeCountSegmentPfPiiS0_ifff:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z16MakeCountSegmentPfPiiS0_ifff, .-_Z16MakeCountSegmentPfPiiS0_ifff
.globl _Z52__device_stub__Z18make_and_count_segPfPiS0_iiiiiifffPfPiS0_iiiiiifff
.type _Z52__device_stub__Z18make_and_count_segPfPiS0_iiiiiifffPfPiS0_iiiiiifff, @function
_Z52__device_stub__Z18make_and_count_segPfPiS0_iiiiiifffPfPiS0_iiiiiifff:
.LFB2052:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm1, 4(%rsp)
movss %xmm2, (%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
leaq 4(%rsp), %rax
movq %rax, 192(%rsp)
movq %rsp, %rax
movq %rax, 200(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 248
pushq 56(%rsp)
.cfi_def_cfa_offset 256
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18make_and_count_segPfPiS0_iiiiiifff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z52__device_stub__Z18make_and_count_segPfPiS0_iiiiiifffPfPiS0_iiiiiifff, .-_Z52__device_stub__Z18make_and_count_segPfPiS0_iiiiiifffPfPiS0_iiiiiifff
.globl _Z18make_and_count_segPfPiS0_iiiiiifff
.type _Z18make_and_count_segPfPiS0_iiiiiifff, @function
_Z18make_and_count_segPfPiS0_iiiiiifff:
.LFB2053:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z52__device_stub__Z18make_and_count_segPfPiS0_iiiiiifffPfPiS0_iiiiiifff
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z18make_and_count_segPfPiS0_iiiiiifff, .-_Z18make_and_count_segPfPiS0_iiiiiifff
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18make_and_count_segPfPiS0_iiiiiifff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18make_and_count_segPfPiS0_iiiiiifff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ void MakeCountSegment(float *segment, int *bins, const int seglength, int *segCounter, const int countlength, const float low, const float high, const float slope)
{
int bin;
float temp;
for (int jj=0; jj<seglength; jj++){
temp = abs(segment[jj]);
if ( ( temp > low ) & ( temp < high ) ) {
bin = (int)ceil(slope*abs(high-temp));
}
else if (temp >= high) {
bin = 0;
}
else bin = countlength - 1;
bins[jj]=bin;
segCounter[bin] = segCounter[bin] + 1;
}
return;
}
__global__ void make_and_count_seg(float *vec, int *bin, int *segcounter, const int length, const int countlength, const int HighLength, const int HighSegmentLength, const int threadsHigh, const int LowSegmentLength, const float low, const float high, const float slope)
{
int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
int startIndex, SegmentLength, startCountIndex;
startCountIndex = xIndex*countlength;
if ( (xIndex*HighSegmentLength > HighLength) & ( (HighLength + (xIndex-threadsHigh+1)*LowSegmentLength) < length ) ){
startIndex = HighLength + (xIndex-threadsHigh)*LowSegmentLength;
SegmentLength = LowSegmentLength;
}
else {
startIndex = xIndex*HighSegmentLength;
SegmentLength = HighSegmentLength;
}
MakeCountSegment(vec+startIndex, bin+startIndex, SegmentLength, segcounter+startCountIndex, countlength, low, high, slope);
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ void MakeCountSegment(float *segment, int *bins, const int seglength, int *segCounter, const int countlength, const float low, const float high, const float slope)
{
int bin;
float temp;
for (int jj=0; jj<seglength; jj++){
temp = abs(segment[jj]);
if ( ( temp > low ) & ( temp < high ) ) {
bin = (int)ceil(slope*abs(high-temp));
}
else if (temp >= high) {
bin = 0;
}
else bin = countlength - 1;
bins[jj]=bin;
segCounter[bin] = segCounter[bin] + 1;
}
return;
}
__global__ void make_and_count_seg(float *vec, int *bin, int *segcounter, const int length, const int countlength, const int HighLength, const int HighSegmentLength, const int threadsHigh, const int LowSegmentLength, const float low, const float high, const float slope)
{
int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
int startIndex, SegmentLength, startCountIndex;
startCountIndex = xIndex*countlength;
if ( (xIndex*HighSegmentLength > HighLength) & ( (HighLength + (xIndex-threadsHigh+1)*LowSegmentLength) < length ) ){
startIndex = HighLength + (xIndex-threadsHigh)*LowSegmentLength;
SegmentLength = LowSegmentLength;
}
else {
startIndex = xIndex*HighSegmentLength;
SegmentLength = HighSegmentLength;
}
MakeCountSegment(vec+startIndex, bin+startIndex, SegmentLength, segcounter+startCountIndex, countlength, low, high, slope);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ void MakeCountSegment(float *segment, int *bins, const int seglength, int *segCounter, const int countlength, const float low, const float high, const float slope)
{
int bin;
float temp;
for (int jj=0; jj<seglength; jj++){
temp = abs(segment[jj]);
if ( ( temp > low ) & ( temp < high ) ) {
bin = (int)ceil(slope*abs(high-temp));
}
else if (temp >= high) {
bin = 0;
}
else bin = countlength - 1;
bins[jj]=bin;
segCounter[bin] = segCounter[bin] + 1;
}
return;
}
__global__ void make_and_count_seg(float *vec, int *bin, int *segcounter, const int length, const int countlength, const int HighLength, const int HighSegmentLength, const int threadsHigh, const int LowSegmentLength, const float low, const float high, const float slope)
{
int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
int startIndex, SegmentLength, startCountIndex;
startCountIndex = xIndex*countlength;
if ( (xIndex*HighSegmentLength > HighLength) & ( (HighLength + (xIndex-threadsHigh+1)*LowSegmentLength) < length ) ){
startIndex = HighLength + (xIndex-threadsHigh)*LowSegmentLength;
SegmentLength = LowSegmentLength;
}
else {
startIndex = xIndex*HighSegmentLength;
SegmentLength = HighSegmentLength;
}
MakeCountSegment(vec+startIndex, bin+startIndex, SegmentLength, segcounter+startCountIndex, countlength, low, high, slope);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18make_and_count_segPfPiS0_iiiiiifff
.globl _Z18make_and_count_segPfPiS0_iiiiiifff
.p2align 8
.type _Z18make_and_count_segPfPiS0_iiiiiifff,@function
_Z18make_and_count_segPfPiS0_iiiiiifff:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x4c
s_load_b128 s[4:7], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
v_mov_b32_e32 v6, s5
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_load_b32 s2, s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v0, s6, v1
v_mul_lo_u32 v2, v1, s5
v_mul_lo_u32 v3, s7, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_i32_e32 vcc_lo, s4, v2
v_add3_u32 v3, s4, s7, v3
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s2, v3
s_and_b32 s3, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s3
v_mad_u64_u32 v[2:3], null, v0, s7, s[4:5]
v_mov_b32_e32 v6, s7
s_or_b32 exec_lo, exec_lo, s2
s_mov_b32 s4, 0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e32 0, v6
s_cbranch_execz .LBB0_11
s_clause 0x4
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[6:7], s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x30
s_load_b32 s1, s[0:1], 0x38
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v4, v1, s5
v_add_co_u32 v0, vcc_lo, s8, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s5, s5, -1
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v5, vcc_lo
s_branch .LBB0_5
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
global_store_b32 v[2:3], v4, off
v_add_nc_u32_e32 v6, -1, v6
v_add_co_u32 v2, s0, v2, 4
v_lshlrev_b64 v[9:10], 2, v[4:5]
v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v9, vcc_lo, v7, v9
v_add_co_ci_u32_e32 v10, vcc_lo, v8, v10, vcc_lo
v_add_co_u32 v0, vcc_lo, v0, 4
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
global_load_b32 v4, v[9:10], off
v_cmp_eq_u32_e32 vcc_lo, 0, v6
s_or_b32 s4, vcc_lo, s4
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, 1, v4
global_store_b32 v[9:10], v4, off
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB0_11
.LBB0_5:
global_load_b32 v5, v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_ngt_f32_e64 s0, |v5|, s2
v_cmp_nlt_f32_e64 s6, |v5|, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, s0, s6
s_and_saveexec_b32 s6, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s6
s_cbranch_execz .LBB0_9
v_mov_b32_e32 v4, 0
s_mov_b32 s6, exec_lo
v_cmpx_nge_f32_e64 |v5|, s3
v_mov_b32_e32 v4, s5
s_or_b32 exec_lo, exec_lo, s6
.LBB0_9:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_4
v_sub_f32_e64 v4, s3, |v5|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e64 v4, |v4|, s1
v_ceil_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v4, v4
s_branch .LBB0_4
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18make_and_count_segPfPiS0_iiiiiifff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18make_and_count_segPfPiS0_iiiiiifff, .Lfunc_end0-_Z18make_and_count_segPfPiS0_iiiiiifff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18make_and_count_segPfPiS0_iiiiiifff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18make_and_count_segPfPiS0_iiiiiifff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ void MakeCountSegment(float *segment, int *bins, const int seglength, int *segCounter, const int countlength, const float low, const float high, const float slope)
{
int bin;
float temp;
for (int jj=0; jj<seglength; jj++){
temp = abs(segment[jj]);
if ( ( temp > low ) & ( temp < high ) ) {
bin = (int)ceil(slope*abs(high-temp));
}
else if (temp >= high) {
bin = 0;
}
else bin = countlength - 1;
bins[jj]=bin;
segCounter[bin] = segCounter[bin] + 1;
}
return;
}
__global__ void make_and_count_seg(float *vec, int *bin, int *segcounter, const int length, const int countlength, const int HighLength, const int HighSegmentLength, const int threadsHigh, const int LowSegmentLength, const float low, const float high, const float slope)
{
int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
int startIndex, SegmentLength, startCountIndex;
startCountIndex = xIndex*countlength;
if ( (xIndex*HighSegmentLength > HighLength) & ( (HighLength + (xIndex-threadsHigh+1)*LowSegmentLength) < length ) ){
startIndex = HighLength + (xIndex-threadsHigh)*LowSegmentLength;
SegmentLength = LowSegmentLength;
}
else {
startIndex = xIndex*HighSegmentLength;
SegmentLength = HighSegmentLength;
}
MakeCountSegment(vec+startIndex, bin+startIndex, SegmentLength, segcounter+startCountIndex, countlength, low, high, slope);
} | .text
.file "make_and_count_seg.hip"
.globl _Z33__device_stub__make_and_count_segPfPiS0_iiiiiifff # -- Begin function _Z33__device_stub__make_and_count_segPfPiS0_iiiiiifff
.p2align 4, 0x90
.type _Z33__device_stub__make_and_count_segPfPiS0_iiiiiifff,@function
_Z33__device_stub__make_and_count_segPfPiS0_iiiiiifff: # @_Z33__device_stub__make_and_count_segPfPiS0_iiiiiifff
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm1, 4(%rsp)
movss %xmm2, (%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 4(%rsp), %rax
movq %rax, 176(%rsp)
movq %rsp, %rax
movq %rax, 184(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18make_and_count_segPfPiS0_iiiiiifff, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size _Z33__device_stub__make_and_count_segPfPiS0_iiiiiifff, .Lfunc_end0-_Z33__device_stub__make_and_count_segPfPiS0_iiiiiifff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18make_and_count_segPfPiS0_iiiiiifff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18make_and_count_segPfPiS0_iiiiiifff,@object # @_Z18make_and_count_segPfPiS0_iiiiiifff
.section .rodata,"a",@progbits
.globl _Z18make_and_count_segPfPiS0_iiiiiifff
.p2align 3, 0x0
_Z18make_and_count_segPfPiS0_iiiiiifff:
.quad _Z33__device_stub__make_and_count_segPfPiS0_iiiiiifff
.size _Z18make_and_count_segPfPiS0_iiiiiifff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18make_and_count_segPfPiS0_iiiiiifff"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__make_and_count_segPfPiS0_iiiiiifff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18make_and_count_segPfPiS0_iiiiiifff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18make_and_count_segPfPiS0_iiiiiifff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff057624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fe400078e0203 */
/*0050*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff037624 */
/* 0x000fe400078e00ff */
/*0060*/ IMAD R7, R4.reuse, c[0x0][0x184], RZ ; /* 0x0000610004077a24 */
/* 0x040fe200078e02ff */
/*0070*/ IADD3 R2, R4, -c[0x0][0x188], RZ ; /* 0x8000620004027a10 */
/* 0x000fc80007ffe0ff */
/*0080*/ IADD3 R0, R2, 0x1, RZ ; /* 0x0000000102007810 */
/* 0x000fca0007ffe0ff */
/*0090*/ IMAD R0, R0, c[0x0][0x18c], R5 ; /* 0x0000630000007a24 */
/* 0x000fca00078e0205 */
/*00a0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06270 */
/*00b0*/ ISETP.GT.AND P0, PT, R7, c[0x0][0x180], !P0 ; /* 0x0000600007007a0c */
/* 0x000fc80004704270 */
/*00c0*/ SEL R3, R3, c[0x0][0x184], P0 ; /* 0x0000610003037a07 */
/* 0x000fc80000000000 */
/*00d0*/ ISETP.GE.AND P1, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fda0003f26270 */
/*00e0*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R6, R3.reuse, -0x1, RZ ; /* 0xffffffff03067810 */
/* 0x040fe20007ffe0ff */
/*0100*/ @P0 IMAD R7, R2, c[0x0][0x18c], R5 ; /* 0x0000630002070a24 */
/* 0x000fe200078e0205 */
/*0110*/ LOP3.LUT R0, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303007812 */
/* 0x000fe200078ec0ff */
/*0120*/ IMAD R4, R4, c[0x0][0x17c], RZ ; /* 0x00005f0004047a24 */
/* 0x000fe200078e02ff */
/*0130*/ ISETP.GE.U32.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe20003f06070 */
/*0140*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fe200078e00ff */
/*0150*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0160*/ BSSY B0, 0x700 ; /* 0x0000059000007945 */
/* 0x000fe20003800000 */
/*0170*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f25270 */
/*0180*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*0190*/ SHF.R.S32.HI R10, RZ, 0x1f, R7 ; /* 0x0000001fff0a7819 */
/* 0x000fc40000011407 */
/*01a0*/ IADD3 R5, -R5, c[0x0][0x17c], RZ ; /* 0x00005f0005057a10 */
/* 0x000fe40007ffe1ff */
/*01b0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */
/* 0x000fc60000011404 */
/*01c0*/ @!P0 BRA 0x6f0 ; /* 0x0000052000008947 */
/* 0x000fea0003800000 */
/*01d0*/ IMAD.SHL.U32 R17, R7.reuse, 0x4, RZ ; /* 0x0000000407117824 */
/* 0x040fe200078e00ff */
/*01e0*/ SHF.L.U64.HI R18, R7, 0x2, R10 ; /* 0x0000000207127819 */
/* 0x000fe2000001020a */
/*01f0*/ IMAD.IADD R12, R3, 0x1, -R0 ; /* 0x00000001030c7824 */
/* 0x000fe400078e0a00 */
/*0200*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*0210*/ IADD3 R2, P0, R17.reuse, c[0x0][0x160], RZ ; /* 0x0000580011027a10 */
/* 0x040fe40007f1e0ff */
/*0220*/ IADD3 R17, P2, R17, c[0x0][0x168], RZ ; /* 0x00005a0011117a10 */
/* 0x000fe40007f5e0ff */
/*0230*/ IADD3.X R3, R18.reuse, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590012037a10 */
/* 0x040fe400007fe4ff */
/*0240*/ IADD3.X R18, R18, c[0x0][0x16c], RZ, P2, !PT ; /* 0x00005b0012127a10 */
/* 0x000fc600017fe4ff */
/*0250*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x002ea4000c1e1900 */
/*0260*/ FSETP.GEU.AND P0, PT, |R9|, c[0x0][0x194], PT ; /* 0x0000650009007a0b */
/* 0x004fc80003f0e200 */
/*0270*/ FSETP.GT.AND P0, PT, |R9|, c[0x0][0x190], !P0 ; /* 0x0000640009007a0b */
/* 0x000fda0004704200 */
/*0280*/ @!P0 FSETP.GE.AND P2, PT, |R9|.reuse, c[0x0][0x194], PT ; /* 0x0000650009008a0b */
/* 0x040fe20003f46200 */
/*0290*/ @P0 FADD R8, -|R9|, c[0x0][0x194] ; /* 0x0000650009080621 */
/* 0x000fc60000000300 */
/*02a0*/ @!P0 SEL R13, R5, RZ, !P2 ; /* 0x000000ff050d8207 */
/* 0x000fe20005000000 */
/*02b0*/ @P0 FMUL R8, |R8|, c[0x0][0x198] ; /* 0x0000660008080a20 */
/* 0x000fca0000400200 */
/*02c0*/ @P0 F2I.CEIL.NTZ R13, R8 ; /* 0x00000008000d0305 */
/* 0x000064000020b100 */
/*02d0*/ IMAD.MOV.U32 R8, RZ, RZ, R17 ; /* 0x000000ffff087224 */
/* 0x001fe200078e0011 */
/*02e0*/ IADD3 R9, P0, R4, R13, RZ ; /* 0x0000000d04097210 */
/* 0x002fc80007f1e0ff */
/*02f0*/ LEA.HI.X.SX32 R16, R13, R6, 0x1, P0 ; /* 0x000000060d107211 */
/* 0x000fe400000f0eff */
/*0300*/ LEA R14, P0, R9, c[0x0][0x170], 0x2 ; /* 0x00005c00090e7a11 */
/* 0x000fc800078010ff */
/*0310*/ LEA.HI.X R15, R9, c[0x0][0x174], R16, 0x2, P0 ; /* 0x00005d00090f7a11 */
/* 0x000fe200000f1410 */
/*0320*/ IMAD.MOV.U32 R9, RZ, RZ, R18 ; /* 0x000000ffff097224 */
/* 0x000fca00078e0012 */
/*0330*/ STG.E [R8.64], R13 ; /* 0x0000000d08007986 */
/* 0x0001e8000c101904 */
/*0340*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ea4000c1e1900 */
/*0350*/ IADD3 R17, R16, 0x1, RZ ; /* 0x0000000110117810 */
/* 0x004fca0007ffe0ff */
/*0360*/ STG.E [R14.64], R17 ; /* 0x000000110e007986 */
/* 0x0003e8000c101904 */
/*0370*/ LDG.E R18, [R2.64+0x4] ; /* 0x0000040402127981 */
/* 0x000ea4000c1e1900 */
/*0380*/ FSETP.GEU.AND P0, PT, |R18|, c[0x0][0x194], PT ; /* 0x0000650012007a0b */
/* 0x004fc80003f0e200 */
/*0390*/ FSETP.GT.AND P0, PT, |R18|, c[0x0][0x190], !P0 ; /* 0x0000640012007a0b */
/* 0x000fda0004704200 */
/*03a0*/ @!P0 FSETP.GE.AND P2, PT, |R18|.reuse, c[0x0][0x194], PT ; /* 0x0000650012008a0b */
/* 0x040fe20003f46200 */
/*03b0*/ @P0 FADD R16, -|R18|, c[0x0][0x194] ; /* 0x0000650012100621 */
/* 0x000fc60000000300 */
/*03c0*/ @!P0 SEL R19, R5, RZ, !P2 ; /* 0x000000ff05138207 */
/* 0x000fe20005000000 */
/*03d0*/ @P0 FMUL R16, |R16|, c[0x0][0x198] ; /* 0x0000660010100a20 */
/* 0x000fca0000400200 */
/*03e0*/ @P0 F2I.CEIL.NTZ R19, R16 ; /* 0x0000001000130305 */
/* 0x000e24000020b100 */
/*03f0*/ IADD3 R13, P0, R4, R19, RZ ; /* 0x00000013040d7210 */
/* 0x001fe20007f1e0ff */
/*0400*/ STG.E [R8.64+0x4], R19 ; /* 0x0000041308007986 */
/* 0x0001e6000c101904 */
/*0410*/ LEA.HI.X.SX32 R18, R19, R6, 0x1, P0 ; /* 0x0000000613127211 */
/* 0x000fe400000f0eff */
/*0420*/ LEA R14, P0, R13, c[0x0][0x170], 0x2 ; /* 0x00005c000d0e7a11 */
/* 0x002fc800078010ff */
/*0430*/ LEA.HI.X R15, R13, c[0x0][0x174], R18, 0x2, P0 ; /* 0x00005d000d0f7a11 */
/* 0x000fca00000f1412 */
/*0440*/ LDG.E R13, [R14.64] ; /* 0x000000040e0d7981 */
/* 0x000ea4000c1e1900 */
/*0450*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x004fca0007ffe0ff */
/*0460*/ STG.E [R14.64], R13 ; /* 0x0000000d0e007986 */
/* 0x0003e8000c101904 */
/*0470*/ LDG.E R17, [R2.64+0x8] ; /* 0x0000080402117981 */
/* 0x000ea4000c1e1900 */
/*0480*/ FSETP.GEU.AND P0, PT, |R17|, c[0x0][0x194], PT ; /* 0x0000650011007a0b */
/* 0x004fc80003f0e200 */
/*0490*/ FSETP.GT.AND P0, PT, |R17|, c[0x0][0x190], !P0 ; /* 0x0000640011007a0b */
/* 0x000fda0004704200 */
/*04a0*/ @!P0 FSETP.GE.AND P2, PT, |R17|.reuse, c[0x0][0x194], PT ; /* 0x0000650011008a0b */
/* 0x040fe20003f46200 */
/*04b0*/ @P0 FADD R16, -|R17|, c[0x0][0x194] ; /* 0x0000650011100621 */
/* 0x000fc60000000300 */
/*04c0*/ @!P0 SEL R17, R5, RZ, !P2 ; /* 0x000000ff05118207 */
/* 0x000fe20005000000 */
/*04d0*/ @P0 FMUL R16, |R16|, c[0x0][0x198] ; /* 0x0000660010100a20 */
/* 0x000fca0000400200 */
/*04e0*/ @P0 F2I.CEIL.NTZ R17, R16 ; /* 0x0000001000110305 */
/* 0x000ea4000020b100 */
/*04f0*/ IADD3 R18, P0, R4, R17, RZ ; /* 0x0000001104127210 */
/* 0x004fe20007f1e0ff */
/*0500*/ STG.E [R8.64+0x8], R17 ; /* 0x0000081108007986 */
/* 0x0005e6000c101904 */
/*0510*/ LEA.HI.X.SX32 R19, R17, R6, 0x1, P0 ; /* 0x0000000611137211 */
/* 0x001fe400000f0eff */
/*0520*/ LEA R14, P0, R18, c[0x0][0x170], 0x2 ; /* 0x00005c00120e7a11 */
/* 0x002fc800078010ff */
/*0530*/ LEA.HI.X R15, R18, c[0x0][0x174], R19, 0x2, P0 ; /* 0x00005d00120f7a11 */
/* 0x000fca00000f1413 */
/*0540*/ LDG.E R13, [R14.64] ; /* 0x000000040e0d7981 */
/* 0x000ee4000c1e1900 */
/*0550*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x008fca0007ffe0ff */
/*0560*/ STG.E [R14.64], R13 ; /* 0x0000000d0e007986 */
/* 0x0001e8000c101904 */
/*0570*/ LDG.E R18, [R2.64+0xc] ; /* 0x00000c0402127981 */
/* 0x000ee4000c1e1900 */
/*0580*/ FSETP.GEU.AND P0, PT, |R18|, c[0x0][0x194], PT ; /* 0x0000650012007a0b */
/* 0x008fc80003f0e200 */
/*0590*/ FSETP.GT.AND P0, PT, |R18|, c[0x0][0x190], !P0 ; /* 0x0000640012007a0b */
/* 0x000fda0004704200 */
/*05a0*/ @!P0 FSETP.GE.AND P2, PT, |R18|.reuse, c[0x0][0x194], PT ; /* 0x0000650012008a0b */
/* 0x040fe20003f46200 */
/*05b0*/ @P0 FADD R16, -|R18|, c[0x0][0x194] ; /* 0x0000650012100621 */
/* 0x000fc60000000300 */
/*05c0*/ @!P0 SEL R19, R5, RZ, !P2 ; /* 0x000000ff05138207 */
/* 0x000fe20005000000 */
/*05d0*/ @P0 FMUL R16, |R16|, c[0x0][0x198] ; /* 0x0000660010100a20 */
/* 0x000fca0000400200 */
/*05e0*/ @P0 F2I.CEIL.NTZ R19, R16 ; /* 0x0000001000130305 */
/* 0x000ea4000020b100 */
/*05f0*/ IADD3 R17, P0, R4, R19, RZ ; /* 0x0000001304117210 */
/* 0x004fe20007f1e0ff */
/*0600*/ STG.E [R8.64+0xc], R19 ; /* 0x00000c1308007986 */
/* 0x0003e6000c101904 */
/*0610*/ LEA.HI.X.SX32 R18, R19, R6, 0x1, P0 ; /* 0x0000000613127211 */
/* 0x000fe400000f0eff */
/*0620*/ LEA R14, P0, R17, c[0x0][0x170], 0x2 ; /* 0x00005c00110e7a11 */
/* 0x001fc800078010ff */
/*0630*/ LEA.HI.X R15, R17, c[0x0][0x174], R18, 0x2, P0 ; /* 0x00005d00110f7a11 */
/* 0x000fca00000f1412 */
/*0640*/ LDG.E R13, [R14.64] ; /* 0x000000040e0d7981 */
/* 0x000ea2000c1e1900 */
/*0650*/ IADD3 R12, R12, -0x4, RZ ; /* 0xfffffffc0c0c7810 */
/* 0x000fe40007ffe0ff */
/*0660*/ IADD3 R17, P3, R8, 0x10, RZ ; /* 0x0000001008117810 */
/* 0x000fe40007f7e0ff */
/*0670*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f05270 */
/*0680*/ IADD3 R2, P2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe20007f5e0ff */
/*0690*/ IMAD.X R18, RZ, RZ, R9, P3 ; /* 0x000000ffff127224 */
/* 0x000fe200018e0609 */
/*06a0*/ IADD3 R11, R11, 0x4, RZ ; /* 0x000000040b0b7810 */
/* 0x000fc60007ffe0ff */
/*06b0*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*06c0*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x004fca0007ffe0ff */
/*06d0*/ STG.E [R14.64], R13 ; /* 0x0000000d0e007986 */
/* 0x0003e2000c101904 */
/*06e0*/ @P0 BRA 0x250 ; /* 0xfffffb6000000947 */
/* 0x000fea000383ffff */
/*06f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0700*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0710*/ IADD3 R7, P0, R7, R11, RZ ; /* 0x0000000b07077210 */
/* 0x000fc80007f1e0ff */
/*0720*/ LEA.HI.X.SX32 R10, R11, R10, 0x1, P0 ; /* 0x0000000a0b0a7211 */
/* 0x000fe200000f0eff */
/*0730*/ IMAD.SHL.U32 R12, R7, 0x4, RZ ; /* 0x00000004070c7824 */
/* 0x000fc600078e00ff */
/*0740*/ SHF.L.U64.HI R15, R7, 0x2, R10 ; /* 0x00000002070f7819 */
/* 0x002fe4000001020a */
/*0750*/ IADD3 R14, P0, R12.reuse, c[0x0][0x168], RZ ; /* 0x00005a000c0e7a10 */
/* 0x040fe40007f1e0ff */
/*0760*/ IADD3 R12, P1, R12, c[0x0][0x160], RZ ; /* 0x000058000c0c7a10 */
/* 0x000fe40007f3e0ff */
/*0770*/ IADD3.X R17, R15.reuse, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b000f117a10 */
/* 0x040fe400007fe4ff */
/*0780*/ IADD3.X R15, R15, c[0x0][0x164], RZ, P1, !PT ; /* 0x000059000f0f7a10 */
/* 0x000fc60000ffe4ff */
/*0790*/ IMAD.MOV.U32 R8, RZ, RZ, R12 ; /* 0x000000ffff087224 */
/* 0x001fe400078e000c */
/*07a0*/ IMAD.MOV.U32 R9, RZ, RZ, R15 ; /* 0x000000ffff097224 */
/* 0x000fca00078e000f */
/*07b0*/ LDG.E R3, [R8.64] ; /* 0x0000000408037981 */
/* 0x0000a4000c1e1900 */
/*07c0*/ IMAD.MOV.U32 R8, RZ, RZ, R14 ; /* 0x000000ffff087224 */
/* 0x001fe400078e000e */
/*07d0*/ IMAD.MOV.U32 R9, RZ, RZ, R17 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0011 */
/*07e0*/ FSETP.GEU.AND P0, PT, |R3|, c[0x0][0x194], PT ; /* 0x0000650003007a0b */
/* 0x004fc80003f0e200 */
/*07f0*/ FSETP.GT.AND P0, PT, |R3|, c[0x0][0x190], !P0 ; /* 0x0000640003007a0b */
/* 0x000fda0004704200 */
/*0800*/ @!P0 FSETP.GE.AND P1, PT, |R3|.reuse, c[0x0][0x194], PT ; /* 0x0000650003008a0b */
/* 0x040fe20003f26200 */
/*0810*/ @P0 FADD R2, -|R3|, c[0x0][0x194] ; /* 0x0000650003020621 */
/* 0x000fc60000000300 */
/*0820*/ @!P0 SEL R11, R5, RZ, !P1 ; /* 0x000000ff050b8207 */
/* 0x000fe20004800000 */
/*0830*/ @P0 FMUL R7, |R2|, c[0x0][0x198] ; /* 0x0000660002070a20 */
/* 0x000fca0000400200 */
/*0840*/ @P0 F2I.CEIL.NTZ R11, R7 ; /* 0x00000007000b0305 */
/* 0x000e24000020b100 */
/*0850*/ IADD3 R3, P0, R4, R11, RZ ; /* 0x0000000b04037210 */
/* 0x001fe20007f1e0ff */
/*0860*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x0001e6000c101904 */
/*0870*/ LEA.HI.X.SX32 R10, R11, R6, 0x1, P0 ; /* 0x000000060b0a7211 */
/* 0x000fe400000f0eff */
/*0880*/ LEA R2, P0, R3, c[0x0][0x170], 0x2 ; /* 0x00005c0003027a11 */
/* 0x000fc800078010ff */
/*0890*/ LEA.HI.X R3, R3, c[0x0][0x174], R10, 0x2, P0 ; /* 0x00005d0003037a11 */
/* 0x000fca00000f140a */
/*08a0*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ea2000c1e1900 */
/*08b0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe40007ffe0ff */
/*08c0*/ IADD3 R14, P1, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fe40007f3e0ff */
/*08d0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*08e0*/ IADD3 R12, P2, R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fe20007f5e0ff */
/*08f0*/ IMAD.X R17, RZ, RZ, R17, P1 ; /* 0x000000ffff117224 */
/* 0x000fc800008e0611 */
/*0900*/ IMAD.X R15, RZ, RZ, R15, P2 ; /* 0x000000ffff0f7224 */
/* 0x000fe200010e060f */
/*0910*/ IADD3 R13, R10, 0x1, RZ ; /* 0x000000010a0d7810 */
/* 0x004fca0007ffe0ff */
/*0920*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e2000c101904 */
/*0930*/ @P0 BRA 0x790 ; /* 0xfffffe5000000947 */
/* 0x000fea000383ffff */
/*0940*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0950*/ BRA 0x950; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18make_and_count_segPfPiS0_iiiiiifff
.globl _Z18make_and_count_segPfPiS0_iiiiiifff
.p2align 8
.type _Z18make_and_count_segPfPiS0_iiiiiifff,@function
_Z18make_and_count_segPfPiS0_iiiiiifff:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x4c
s_load_b128 s[4:7], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
v_mov_b32_e32 v6, s5
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_load_b32 s2, s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v0, s6, v1
v_mul_lo_u32 v2, v1, s5
v_mul_lo_u32 v3, s7, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_i32_e32 vcc_lo, s4, v2
v_add3_u32 v3, s4, s7, v3
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s2, v3
s_and_b32 s3, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s3
v_mad_u64_u32 v[2:3], null, v0, s7, s[4:5]
v_mov_b32_e32 v6, s7
s_or_b32 exec_lo, exec_lo, s2
s_mov_b32 s4, 0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e32 0, v6
s_cbranch_execz .LBB0_11
s_clause 0x4
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[6:7], s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x30
s_load_b32 s1, s[0:1], 0x38
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v4, v1, s5
v_add_co_u32 v0, vcc_lo, s8, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s5, s5, -1
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v5, vcc_lo
s_branch .LBB0_5
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
global_store_b32 v[2:3], v4, off
v_add_nc_u32_e32 v6, -1, v6
v_add_co_u32 v2, s0, v2, 4
v_lshlrev_b64 v[9:10], 2, v[4:5]
v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v9, vcc_lo, v7, v9
v_add_co_ci_u32_e32 v10, vcc_lo, v8, v10, vcc_lo
v_add_co_u32 v0, vcc_lo, v0, 4
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
global_load_b32 v4, v[9:10], off
v_cmp_eq_u32_e32 vcc_lo, 0, v6
s_or_b32 s4, vcc_lo, s4
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, 1, v4
global_store_b32 v[9:10], v4, off
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB0_11
.LBB0_5:
global_load_b32 v5, v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_ngt_f32_e64 s0, |v5|, s2
v_cmp_nlt_f32_e64 s6, |v5|, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, s0, s6
s_and_saveexec_b32 s6, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s6
s_cbranch_execz .LBB0_9
v_mov_b32_e32 v4, 0
s_mov_b32 s6, exec_lo
v_cmpx_nge_f32_e64 |v5|, s3
v_mov_b32_e32 v4, s5
s_or_b32 exec_lo, exec_lo, s6
.LBB0_9:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_4
v_sub_f32_e64 v4, s3, |v5|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e64 v4, |v4|, s1
v_ceil_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v4, v4
s_branch .LBB0_4
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18make_and_count_segPfPiS0_iiiiiifff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18make_and_count_segPfPiS0_iiiiiifff, .Lfunc_end0-_Z18make_and_count_segPfPiS0_iiiiiifff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18make_and_count_segPfPiS0_iiiiiifff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18make_and_count_segPfPiS0_iiiiiifff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008c74b_00000000-6_make_and_count_seg.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z16MakeCountSegmentPfPiiS0_ifff
.type _Z16MakeCountSegmentPfPiiS0_ifff, @function
_Z16MakeCountSegmentPfPiiS0_ifff:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z16MakeCountSegmentPfPiiS0_ifff, .-_Z16MakeCountSegmentPfPiiS0_ifff
.globl _Z52__device_stub__Z18make_and_count_segPfPiS0_iiiiiifffPfPiS0_iiiiiifff
.type _Z52__device_stub__Z18make_and_count_segPfPiS0_iiiiiifffPfPiS0_iiiiiifff, @function
_Z52__device_stub__Z18make_and_count_segPfPiS0_iiiiiifffPfPiS0_iiiiiifff:
.LFB2052:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm1, 4(%rsp)
movss %xmm2, (%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
leaq 4(%rsp), %rax
movq %rax, 192(%rsp)
movq %rsp, %rax
movq %rax, 200(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 248
pushq 56(%rsp)
.cfi_def_cfa_offset 256
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18make_and_count_segPfPiS0_iiiiiifff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z52__device_stub__Z18make_and_count_segPfPiS0_iiiiiifffPfPiS0_iiiiiifff, .-_Z52__device_stub__Z18make_and_count_segPfPiS0_iiiiiifffPfPiS0_iiiiiifff
.globl _Z18make_and_count_segPfPiS0_iiiiiifff
.type _Z18make_and_count_segPfPiS0_iiiiiifff, @function
_Z18make_and_count_segPfPiS0_iiiiiifff:
.LFB2053:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z52__device_stub__Z18make_and_count_segPfPiS0_iiiiiifffPfPiS0_iiiiiifff
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z18make_and_count_segPfPiS0_iiiiiifff, .-_Z18make_and_count_segPfPiS0_iiiiiifff
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18make_and_count_segPfPiS0_iiiiiifff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18make_and_count_segPfPiS0_iiiiiifff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "make_and_count_seg.hip"
.globl _Z33__device_stub__make_and_count_segPfPiS0_iiiiiifff # -- Begin function _Z33__device_stub__make_and_count_segPfPiS0_iiiiiifff
.p2align 4, 0x90
.type _Z33__device_stub__make_and_count_segPfPiS0_iiiiiifff,@function
_Z33__device_stub__make_and_count_segPfPiS0_iiiiiifff: # @_Z33__device_stub__make_and_count_segPfPiS0_iiiiiifff
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm1, 4(%rsp)
movss %xmm2, (%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 4(%rsp), %rax
movq %rax, 176(%rsp)
movq %rsp, %rax
movq %rax, 184(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18make_and_count_segPfPiS0_iiiiiifff, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size _Z33__device_stub__make_and_count_segPfPiS0_iiiiiifff, .Lfunc_end0-_Z33__device_stub__make_and_count_segPfPiS0_iiiiiifff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18make_and_count_segPfPiS0_iiiiiifff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18make_and_count_segPfPiS0_iiiiiifff,@object # @_Z18make_and_count_segPfPiS0_iiiiiifff
.section .rodata,"a",@progbits
.globl _Z18make_and_count_segPfPiS0_iiiiiifff
.p2align 3, 0x0
_Z18make_and_count_segPfPiS0_iiiiiifff:
.quad _Z33__device_stub__make_and_count_segPfPiS0_iiiiiifff
.size _Z18make_and_count_segPfPiS0_iiiiiifff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18make_and_count_segPfPiS0_iiiiiifff"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__make_and_count_segPfPiS0_iiiiiifff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18make_and_count_segPfPiS0_iiiiiifff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <assert.h>
#include <cuda.h>
#define u32 unsigned int
#define BLOCK_SIZE 64
#define CREATE_RAND_ARR(arr, size, min, max) \
do { \
time_t t; \
srand((unsigned)time(&t)); \
for (u32 i = 0; i < size; i++) \
arr[i] = rand() % max + min; \
} while (0) \
template <typename T>
T cpuFindMax(T* arr, const u32 arr_size);
template <typename T>
T gpuFindMax(T* arr, const u32 arr_size);
__device__
float atomicFloatMax(float* address, const float val)
{
if (*address > val) {
return *address;
}
int* const addressInt = (int*)address;
int old = *addressInt, assumed;
do {
assumed = old;
if (__int_as_float(assumed) > val) {
break;
}
old = atomicCAS(addressInt, assumed, __float_as_int(val));
} while (old != assumed);
return old;
}
__global__
void find_max_int_kernel(const int* __restrict__ arr, const u32 arr_size, int* maxval)
{
__shared__ int shared_maxval;
u32 id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (id_x == 0) {
shared_maxval = arr[0];
}
__syncthreads();
int register_maxval = shared_maxval;
if (blockIdx.x == 0) {
for (u32 i = threadIdx.x; i < arr_size; i += blockDim.x) {
register_maxval = (register_maxval > arr[i])? register_maxval : arr[i];
}
}
atomicMax(&shared_maxval, register_maxval);
__syncthreads();
if (id_x == 0) {
*maxval = shared_maxval;
}
}
__global__
void find_max_float_kernel(const float* __restrict__ arr, const u32 arr_size, float* maxval)
{
__shared__ float shared_maxval;
u32 id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (id_x == 0) {
shared_maxval = arr[0];
}
__syncthreads();
float register_maxval = shared_maxval;
if (blockIdx.x == 0) {
for (u32 i = threadIdx.x; i < arr_size; i += blockDim.x) {
register_maxval = (register_maxval > arr[i])? register_maxval : arr[i];
}
}
atomicFloatMax(&shared_maxval, register_maxval);
__syncthreads();
if (id_x == 0) {
*maxval = shared_maxval;
}
}
// __device__
// void warp_find_max_kernel(const int* __restrict__ arr, const u32 size, int* max)
// {
// }
// __host__
// int gpuWarpFindMax(int* h_arr, const u32 size)
// {
// assert(size == 32);
// int* d_arr;
// cudaMalloc((void**)&d_arr, size * sizeof(int));
// cudaMemcpy(d_arr, h_arr, size * sizeof(int), cudaMemcpyHostToDevice);
// int* d_max;
// cudaMalloc((void**)&d_max, 1 * sizeof(int));
// warp_find_max_kernel(d_arr, d_max);
// if (cudaSuccess != cudaGetLastError()) {
// printf("warp_find_max_kernel fault!\n");
// }
// int* h_max = (int*)malloc(1 * sizeof(int));
// cudaMemcpy(h_max, d_max, 1 * sizeof(int), cudaMemcpyDeviceToHost);
// int max = *h_max;
// cudaFree(d_arr);
// cudaFree(d_max);
// free(h_max);
// return max;
// }
template <>
int gpuFindMax<int>(int* h_arr, const u32 arr_size)
{
assert(arr_size > 0);
int* d_arr;
cudaMalloc((void**)&d_arr, arr_size * sizeof(int));
cudaMemcpy(d_arr, h_arr, arr_size * sizeof(int), cudaMemcpyHostToDevice);
int* d_maxval;
cudaMalloc((void**)&d_maxval, 1 * sizeof(int));
dim3 blocks = BLOCK_SIZE;
dim3 grid = (arr_size + BLOCK_SIZE - 1) / BLOCK_SIZE;
find_max_int_kernel <<< grid , blocks >>> (d_arr, arr_size, d_maxval);
if (cudaSuccess != cudaGetLastError()) {
printf("find_max_int_kernel fault!\n");
}
int* h_maxval = (int*)malloc(1 * sizeof(int));
cudaMemcpy(h_maxval, d_maxval, 1 * sizeof(int), cudaMemcpyDeviceToHost);
int result = *h_maxval;
cudaFree(d_arr);
cudaFree(d_maxval);
free(h_maxval);
return result;
}
template <>
float gpuFindMax<float>(float* h_arr, const u32 arr_size)
{
assert(arr_size > 0);
float* d_arr;
cudaMalloc((void**)&d_arr, arr_size * sizeof(float));
cudaMemcpy(d_arr, h_arr, arr_size * sizeof(float), cudaMemcpyHostToDevice);
float* d_maxval;
cudaMalloc((void**)&d_maxval, 1 * sizeof(float));
dim3 blocks = BLOCK_SIZE;
dim3 grid = (arr_size + BLOCK_SIZE - 1) / BLOCK_SIZE;
find_max_float_kernel <<< grid , blocks >>> (d_arr, arr_size, d_maxval);
if (cudaSuccess != cudaGetLastError()) {
printf("find_max_float_kernel fault!\n");
}
float* h_maxval = (float*)malloc(1 * sizeof(float));
cudaMemcpy(h_maxval, d_maxval, 1 * sizeof(float), cudaMemcpyDeviceToHost);
float result = *h_maxval;
cudaFree(d_arr);
cudaFree(d_maxval);
free(h_maxval);
return result;
}
template <>
int cpuFindMax<int>(int* arr, const u32 arr_size)
{
assert(arr_size > 0);
int maxval = arr[0];
for (u32 i = 0; i < arr_size; i++) {
maxval = (arr[i] > maxval)? arr[i] : maxval;
}
return maxval;
}
template <>
float cpuFindMax<float>(float* arr, const u32 arr_size)
{
assert(arr_size > 0);
float maxval = arr[0];
for (u32 i = 0; i < arr_size; i++) {
maxval = (arr[i] > maxval)? arr[i] : maxval;
}
return maxval;
}
int main()
{
const u32 arr_size = 1000;
int* int_arr = (int*)malloc(arr_size * sizeof(int));
CREATE_RAND_ARR(int_arr, arr_size, 0, 1000);
float* float_arr = (float*)malloc(arr_size * sizeof(float));
CREATE_RAND_ARR(float_arr, arr_size, 0, 1000);
for (u32 i = 0; i < arr_size; i++) {
float_arr[i] /= 10.0;
}
int cpu_int_maxval = cpuFindMax<int>(int_arr, arr_size);
printf("CPU find max int element: %d\n", cpu_int_maxval);
int gpu_int_maxval = gpuFindMax<int>(int_arr, arr_size);
printf("GPU find max int element: %d\n", gpu_int_maxval);
float cpu_float_maxval = cpuFindMax<float>(float_arr, arr_size);
printf("CPU find max float element: %f\n", cpu_float_maxval);
float gpu_float_maxval = gpuFindMax<float>(float_arr, arr_size);
printf("GPU find max float element: %f\n", gpu_float_maxval);
const u32 warp_size = 32;
int* warp_arr = (int*)malloc(warp_size * sizeof(int));
CREATE_RAND_ARR(warp_arr, warp_size, 0, 1000);
// int gpu_warp_int_maxval = gpuWarpFindMax(warp_arr, warp_size);
// printf("GPU warp find max int element: %d\n", gpu_warp_int_maxval);
free(int_arr);
free(float_arr);
free(warp_arr);
return 0;
} | code for sm_80
Function : _Z21find_max_float_kernelPKfjPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2UR UR6, SR_CTAID.X ; /* 0x00000000000679c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0030*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0040*/ BSSY B0, 0xf0 ; /* 0x000000a000007945 */
/* 0x000fe20003800000 */
/*0050*/ UIMAD UR4, UR6, UR4, URZ ; /* 0x00000004060472a4 */
/* 0x001fe2000f8e023f */
/*0060*/ IMAD.MOV R2, RZ, RZ, -R0 ; /* 0x000000ffff027224 */
/* 0x002fca00078e0a00 */
/*0070*/ ISETP.NE.AND P1, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x000fe2000bf25270 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd80000000a00 */
/*0090*/ @P1 BRA 0xe0 ; /* 0x0000004000001947 */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fca00078e00ff */
/*00c0*/ LDG.E.CONSTANT R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e9900 */
/*00d0*/ STS [RZ], R2 ; /* 0x00000002ff007388 */
/* 0x0041e40000000800 */
/*00e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0100*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fc80003f06070 */
/*0110*/ ISETP.NE.OR P0, PT, RZ, UR6, P0 ; /* 0x00000006ff007c0c */
/* 0x000fe20008705670 */
/*0120*/ BSSY B0, 0x200 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0130*/ LDS R4, [RZ] ; /* 0x00000000ff047984 */
/* 0x000e640000000800 */
/*0140*/ IMAD.MOV.U32 R5, RZ, RZ, R4 ; /* 0x000000ffff057224 */
/* 0x002fd200078e0004 */
/*0150*/ @P0 BRA 0x1f0 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*0160*/ MOV R5, R4 ; /* 0x0000000400057202 */
/* 0x000fe40000000f00 */
/*0170*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0180*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fcc00078e0003 */
/*0190*/ LDG.E.CONSTANT R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e9900 */
/*01a0*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fc80007ffe0ff */
/*01b0*/ ISETP.GE.U32.AND P2, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe40003f46070 */
/*01c0*/ FSETP.GT.AND P0, PT, R5, R2, PT ; /* 0x000000020500720b */
/* 0x004fc80003f04000 */
/*01d0*/ FSEL R5, R5, R2, P0 ; /* 0x0000000205057208 */
/* 0x000fce0000000000 */
/*01e0*/ @!P2 BRA 0x170 ; /* 0xffffff800000a947 */
/* 0x000fea000383ffff */
/*01f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0200*/ FSETP.GT.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fda0003f04000 */
/*0210*/ @P0 BRA 0x290 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0220*/ FSETP.GEU.AND P0, PT, R5, R4, PT ; /* 0x000000040500720b */
/* 0x000fe20003f0e000 */
/*0230*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fd80003800000 */
/*0240*/ @!P0 BRA 0x290 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0250*/ ATOMS.CAS R3, [RZ], R4, R5 ; /* 0x00000004ff03738d */
/* 0x000e640000000005 */
/*0260*/ ISETP.NE.AND P0, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x002fe20003f05270 */
/*0270*/ IMAD.MOV.U32 R4, RZ, RZ, R3 ; /* 0x000000ffff047224 */
/* 0x000fd800078e0003 */
/*0280*/ @P0 BRA 0x220 ; /* 0xffffff9000000947 */
/* 0x000fea000383ffff */
/*0290*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*02a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02b0*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*02c0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e620000000800 */
/*02d0*/ MOV R2, c[0x0][0x170] ; /* 0x00005c0000027a02 */
/* 0x001fe20000000f00 */
/*02e0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fca00078e00ff */
/*02f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101904 */
/*0300*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0310*/ BRA 0x310; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z19find_max_int_kernelPKijPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2UR UR5, SR_CTAID.X ; /* 0x00000000000579c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0030*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0040*/ BSSY B0, 0x120 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0050*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0060*/ S2R R5, SR_LANEID ; /* 0x0000000000057919 */
/* 0x000ea20000000000 */
/*0070*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x001fe2000f8e023f */
/*0080*/ IMAD.MOV R2, RZ, RZ, -R0 ; /* 0x000000ffff027224 */
/* 0x002fe200078e0a00 */
/*0090*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fc80003f06070 */
/*00a0*/ ISETP.NE.AND P1, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x000fe4000bf25270 */
/*00b0*/ ISETP.NE.OR P0, PT, RZ, UR5, P0 ; /* 0x00000005ff007c0c */
/* 0x000fd60008705670 */
/*00c0*/ @P1 BRA 0x110 ; /* 0x0000004000001947 */
/* 0x000fea0003800000 */
/*00d0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x004fe400078e00ff */
/*00e0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fca00078e00ff */
/*00f0*/ LDG.E.CONSTANT R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea8000c1e9900 */
/*0100*/ STS [RZ], R2 ; /* 0x00000002ff007388 */
/* 0x0041e40000000800 */
/*0110*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x004fea0003800000 */
/*0120*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0130*/ BSSY B0, 0x1e0 ; /* 0x000000a000007945 */
/* 0x000fe20003800000 */
/*0140*/ LDS R4, [RZ] ; /* 0x00000000ff047984 */
/* 0x000e620000000800 */
/*0150*/ @P0 BRA 0x1d0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0160*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0170*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fcc00078e0003 */
/*0180*/ LDG.E.CONSTANT R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e9900 */
/*0190*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fc80007ffe0ff */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe40003f06070 */
/*01b0*/ IMNMX R4, R3, R4, !PT ; /* 0x0000000403047217 */
/* 0x006fd60007800200 */
/*01c0*/ @!P0 BRA 0x160 ; /* 0xffffff9000008947 */
/* 0x000fea000383ffff */
/*01d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01e0*/ REDUX.MAX.S32 UR5, R4 ; /* 0x00000000040573c4 */
/* 0x002e620000014200 */
/*01f0*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*0200*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fcc00080e0000 */
/*0210*/ ISETP.EQ.U32.AND P0, PT, R5, UR4, PT ; /* 0x0000000405007c0c */
/* 0x000fe2000bf02070 */
/*0220*/ IMAD.U32 R0, RZ, RZ, UR5 ; /* 0x00000005ff007e24 */
/* 0x002fd8000f8e00ff */
/*0230*/ @P0 ATOMS.MAX.S32 RZ, [RZ], R0 ; /* 0x00000000ffff038c */
/* 0x0003e80001000200 */
/*0240*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0250*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0260*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x002e620000000800 */
/*0270*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x001fe200078e00ff */
/*0280*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fca0000000f00 */
/*0290*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101906 */
/*02a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02b0*/ BRA 0x2b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <assert.h>
#include <cuda.h>
#define u32 unsigned int
#define BLOCK_SIZE 64
#define CREATE_RAND_ARR(arr, size, min, max) \
do { \
time_t t; \
srand((unsigned)time(&t)); \
for (u32 i = 0; i < size; i++) \
arr[i] = rand() % max + min; \
} while (0) \
template <typename T>
T cpuFindMax(T* arr, const u32 arr_size);
template <typename T>
T gpuFindMax(T* arr, const u32 arr_size);
__device__
float atomicFloatMax(float* address, const float val)
{
if (*address > val) {
return *address;
}
int* const addressInt = (int*)address;
int old = *addressInt, assumed;
do {
assumed = old;
if (__int_as_float(assumed) > val) {
break;
}
old = atomicCAS(addressInt, assumed, __float_as_int(val));
} while (old != assumed);
return old;
}
__global__
void find_max_int_kernel(const int* __restrict__ arr, const u32 arr_size, int* maxval)
{
__shared__ int shared_maxval;
u32 id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (id_x == 0) {
shared_maxval = arr[0];
}
__syncthreads();
int register_maxval = shared_maxval;
if (blockIdx.x == 0) {
for (u32 i = threadIdx.x; i < arr_size; i += blockDim.x) {
register_maxval = (register_maxval > arr[i])? register_maxval : arr[i];
}
}
atomicMax(&shared_maxval, register_maxval);
__syncthreads();
if (id_x == 0) {
*maxval = shared_maxval;
}
}
__global__
void find_max_float_kernel(const float* __restrict__ arr, const u32 arr_size, float* maxval)
{
__shared__ float shared_maxval;
u32 id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (id_x == 0) {
shared_maxval = arr[0];
}
__syncthreads();
float register_maxval = shared_maxval;
if (blockIdx.x == 0) {
for (u32 i = threadIdx.x; i < arr_size; i += blockDim.x) {
register_maxval = (register_maxval > arr[i])? register_maxval : arr[i];
}
}
atomicFloatMax(&shared_maxval, register_maxval);
__syncthreads();
if (id_x == 0) {
*maxval = shared_maxval;
}
}
// __device__
// void warp_find_max_kernel(const int* __restrict__ arr, const u32 size, int* max)
// {
// }
// __host__
// int gpuWarpFindMax(int* h_arr, const u32 size)
// {
// assert(size == 32);
// int* d_arr;
// cudaMalloc((void**)&d_arr, size * sizeof(int));
// cudaMemcpy(d_arr, h_arr, size * sizeof(int), cudaMemcpyHostToDevice);
// int* d_max;
// cudaMalloc((void**)&d_max, 1 * sizeof(int));
// warp_find_max_kernel(d_arr, d_max);
// if (cudaSuccess != cudaGetLastError()) {
// printf("warp_find_max_kernel fault!\n");
// }
// int* h_max = (int*)malloc(1 * sizeof(int));
// cudaMemcpy(h_max, d_max, 1 * sizeof(int), cudaMemcpyDeviceToHost);
// int max = *h_max;
// cudaFree(d_arr);
// cudaFree(d_max);
// free(h_max);
// return max;
// }
template <>
int gpuFindMax<int>(int* h_arr, const u32 arr_size)
{
assert(arr_size > 0);
int* d_arr;
cudaMalloc((void**)&d_arr, arr_size * sizeof(int));
cudaMemcpy(d_arr, h_arr, arr_size * sizeof(int), cudaMemcpyHostToDevice);
int* d_maxval;
cudaMalloc((void**)&d_maxval, 1 * sizeof(int));
dim3 blocks = BLOCK_SIZE;
dim3 grid = (arr_size + BLOCK_SIZE - 1) / BLOCK_SIZE;
find_max_int_kernel <<< grid , blocks >>> (d_arr, arr_size, d_maxval);
if (cudaSuccess != cudaGetLastError()) {
printf("find_max_int_kernel fault!\n");
}
int* h_maxval = (int*)malloc(1 * sizeof(int));
cudaMemcpy(h_maxval, d_maxval, 1 * sizeof(int), cudaMemcpyDeviceToHost);
int result = *h_maxval;
cudaFree(d_arr);
cudaFree(d_maxval);
free(h_maxval);
return result;
}
template <>
float gpuFindMax<float>(float* h_arr, const u32 arr_size)
{
assert(arr_size > 0);
float* d_arr;
cudaMalloc((void**)&d_arr, arr_size * sizeof(float));
cudaMemcpy(d_arr, h_arr, arr_size * sizeof(float), cudaMemcpyHostToDevice);
float* d_maxval;
cudaMalloc((void**)&d_maxval, 1 * sizeof(float));
dim3 blocks = BLOCK_SIZE;
dim3 grid = (arr_size + BLOCK_SIZE - 1) / BLOCK_SIZE;
find_max_float_kernel <<< grid , blocks >>> (d_arr, arr_size, d_maxval);
if (cudaSuccess != cudaGetLastError()) {
printf("find_max_float_kernel fault!\n");
}
float* h_maxval = (float*)malloc(1 * sizeof(float));
cudaMemcpy(h_maxval, d_maxval, 1 * sizeof(float), cudaMemcpyDeviceToHost);
float result = *h_maxval;
cudaFree(d_arr);
cudaFree(d_maxval);
free(h_maxval);
return result;
}
template <>
int cpuFindMax<int>(int* arr, const u32 arr_size)
{
assert(arr_size > 0);
int maxval = arr[0];
for (u32 i = 0; i < arr_size; i++) {
maxval = (arr[i] > maxval)? arr[i] : maxval;
}
return maxval;
}
template <>
float cpuFindMax<float>(float* arr, const u32 arr_size)
{
assert(arr_size > 0);
float maxval = arr[0];
for (u32 i = 0; i < arr_size; i++) {
maxval = (arr[i] > maxval)? arr[i] : maxval;
}
return maxval;
}
int main()
{
const u32 arr_size = 1000;
int* int_arr = (int*)malloc(arr_size * sizeof(int));
CREATE_RAND_ARR(int_arr, arr_size, 0, 1000);
float* float_arr = (float*)malloc(arr_size * sizeof(float));
CREATE_RAND_ARR(float_arr, arr_size, 0, 1000);
for (u32 i = 0; i < arr_size; i++) {
float_arr[i] /= 10.0;
}
int cpu_int_maxval = cpuFindMax<int>(int_arr, arr_size);
printf("CPU find max int element: %d\n", cpu_int_maxval);
int gpu_int_maxval = gpuFindMax<int>(int_arr, arr_size);
printf("GPU find max int element: %d\n", gpu_int_maxval);
float cpu_float_maxval = cpuFindMax<float>(float_arr, arr_size);
printf("CPU find max float element: %f\n", cpu_float_maxval);
float gpu_float_maxval = gpuFindMax<float>(float_arr, arr_size);
printf("GPU find max float element: %f\n", gpu_float_maxval);
const u32 warp_size = 32;
int* warp_arr = (int*)malloc(warp_size * sizeof(int));
CREATE_RAND_ARR(warp_arr, warp_size, 0, 1000);
// int gpu_warp_int_maxval = gpuWarpFindMax(warp_arr, warp_size);
// printf("GPU warp find max int element: %d\n", gpu_warp_int_maxval);
free(int_arr);
free(float_arr);
free(warp_arr);
return 0;
} | .file "tmpxft_00037da1_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14atomicFloatMaxPff
.type _Z14atomicFloatMaxPff, @function
_Z14atomicFloatMaxPff:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z14atomicFloatMaxPff, .-_Z14atomicFloatMaxPff
.globl _Z10cpuFindMaxIiET_PS0_j
.type _Z10cpuFindMaxIiET_PS0_j, @function
_Z10cpuFindMaxIiET_PS0_j:
.LFB2060:
.cfi_startproc
endbr64
movl (%rdi), %edx
testl %esi, %esi
je .L5
movq %rdi, %rax
movl %esi, %esi
leaq (%rdi,%rsi,4), %rsi
.L7:
movl (%rax), %ecx
cmpl %ecx, %edx
cmovl %ecx, %edx
addq $4, %rax
cmpq %rsi, %rax
jne .L7
.L5:
movl %edx, %eax
ret
.cfi_endproc
.LFE2060:
.size _Z10cpuFindMaxIiET_PS0_j, .-_Z10cpuFindMaxIiET_PS0_j
.globl _Z10cpuFindMaxIfET_PS0_j
.type _Z10cpuFindMaxIfET_PS0_j, @function
_Z10cpuFindMaxIfET_PS0_j:
.LFB2061:
.cfi_startproc
endbr64
movss (%rdi), %xmm0
testl %esi, %esi
je .L9
movq %rdi, %rax
movl %esi, %esi
leaq (%rdi,%rsi,4), %rdx
.L12:
movss (%rax), %xmm1
maxss %xmm0, %xmm1
movaps %xmm1, %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L12
.L9:
ret
.cfi_endproc
.LFE2061:
.size _Z10cpuFindMaxIfET_PS0_j, .-_Z10cpuFindMaxIfET_PS0_j
.globl _Z43__device_stub__Z19find_max_int_kernelPKijPiPKijPi
.type _Z43__device_stub__Z19find_max_int_kernelPKijPiPKijPi, @function
_Z43__device_stub__Z19find_max_int_kernelPKijPiPKijPi:
.LFB2087:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %esi, 12(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19find_max_int_kernelPKijPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z43__device_stub__Z19find_max_int_kernelPKijPiPKijPi, .-_Z43__device_stub__Z19find_max_int_kernelPKijPiPKijPi
.globl _Z19find_max_int_kernelPKijPi
.type _Z19find_max_int_kernelPKijPi, @function
_Z19find_max_int_kernelPKijPi:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z19find_max_int_kernelPKijPiPKijPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z19find_max_int_kernelPKijPi, .-_Z19find_max_int_kernelPKijPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "find_max_int_kernel fault!\n"
.text
.globl _Z10gpuFindMaxIiET_PS0_j
.type _Z10gpuFindMaxIiET_PS0_j, @function
_Z10gpuFindMaxIiET_PS0_j:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r12
movl %esi, %ebx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl %esi, %ebp
salq $2, %rbp
movq %rsp, %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $64, 16(%rsp)
movl $1, 20(%rsp)
leal 63(%rbx), %eax
shrl $6, %eax
movl %eax, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L29
.L25:
movl $4, %edi
call malloc@PLT
movq %rax, %rbx
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movl (%rbx), %ebp
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl %ebp, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movq 8(%rsp), %rdx
movl %ebx, %esi
movq (%rsp), %rdi
call _Z43__device_stub__Z19find_max_int_kernelPKijPiPKijPi
jmp .L24
.L29:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z10gpuFindMaxIiET_PS0_j, .-_Z10gpuFindMaxIiET_PS0_j
.globl _Z45__device_stub__Z21find_max_float_kernelPKfjPfPKfjPf
.type _Z45__device_stub__Z21find_max_float_kernelPKfjPfPKfjPf, @function
_Z45__device_stub__Z21find_max_float_kernelPKfjPfPKfjPf:
.LFB2089:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %esi, 12(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L35
.L31:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21find_max_float_kernelPKfjPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L31
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z45__device_stub__Z21find_max_float_kernelPKfjPfPKfjPf, .-_Z45__device_stub__Z21find_max_float_kernelPKfjPfPKfjPf
.globl _Z21find_max_float_kernelPKfjPf
.type _Z21find_max_float_kernelPKfjPf, @function
_Z21find_max_float_kernelPKfjPf:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z21find_max_float_kernelPKfjPfPKfjPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z21find_max_float_kernelPKfjPf, .-_Z21find_max_float_kernelPKfjPf
.section .rodata.str1.1
.LC1:
.string "find_max_float_kernel fault!\n"
.text
.globl _Z10gpuFindMaxIfET_PS0_j
.type _Z10gpuFindMaxIfET_PS0_j, @function
_Z10gpuFindMaxIfET_PS0_j:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r12
movl %esi, %ebx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl %esi, %ebp
salq $2, %rbp
movq %rsp, %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $64, 16(%rsp)
movl $1, 20(%rsp)
leal 63(%rbx), %eax
shrl $6, %eax
movl %eax, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L44
.L40:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L45
.L41:
movl $4, %edi
call malloc@PLT
movq %rax, %rbx
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movl (%rbx), %ebp
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L46
movd %ebp, %xmm0
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
movq 8(%rsp), %rdx
movl %ebx, %esi
movq (%rsp), %rdi
call _Z45__device_stub__Z21find_max_float_kernelPKfjPfPKfjPf
jmp .L40
.L45:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L41
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z10gpuFindMaxIfET_PS0_j, .-_Z10gpuFindMaxIfET_PS0_j
.section .rodata.str1.1
.LC3:
.string "CPU find max int element: %d\n"
.LC4:
.string "GPU find max int element: %d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "CPU find max float element: %f\n"
.align 8
.LC6:
.string "GPU find max float element: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2062:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $16, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl $4000, %edi
call malloc@PLT
movq %rax, %r14
movq %rsp, %rdi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %r14, %rbx
leaq 4000(%r14), %rbp
.L48:
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L48
movl $4000, %edi
call malloc@PLT
movq %rax, %r13
movq %rsp, %rdi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %r13, %rbx
leaq 4000(%r13), %r12
movq %r13, %rbp
.L49:
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp)
addq $4, %rbp
cmpq %r12, %rbp
jne .L49
movss .LC2(%rip), %xmm1
.L50:
movss (%rbx), %xmm0
divss %xmm1, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L50
movl $1000, %esi
movq %r14, %rdi
call _Z10cpuFindMaxIiET_PS0_j
movl %eax, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1000, %esi
movq %r14, %rdi
call _Z10gpuFindMaxIiET_PS0_j
movl %eax, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1000, %esi
movq %r13, %rdi
call _Z10cpuFindMaxIfET_PS0_j
cvtss2sd %xmm0, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $1000, %esi
movq %r13, %rdi
call _Z10gpuFindMaxIfET_PS0_j
cvtss2sd %xmm0, %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $128, %edi
call malloc@PLT
movq %rax, %r12
movq %rsp, %rdi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %r12, %rbx
leaq 128(%r12), %rbp
.L51:
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L51
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L58
movl $0, %eax
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC7:
.string "_Z21find_max_float_kernelPKfjPf"
.section .rodata.str1.1
.LC8:
.string "_Z19find_max_int_kernelPKijPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z21find_max_float_kernelPKfjPf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z19find_max_int_kernelPKijPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1092616192
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <assert.h>
#include <cuda.h>
#define u32 unsigned int
#define BLOCK_SIZE 64
#define CREATE_RAND_ARR(arr, size, min, max) \
do { \
time_t t; \
srand((unsigned)time(&t)); \
for (u32 i = 0; i < size; i++) \
arr[i] = rand() % max + min; \
} while (0) \
template <typename T>
T cpuFindMax(T* arr, const u32 arr_size);
template <typename T>
T gpuFindMax(T* arr, const u32 arr_size);
__device__
float atomicFloatMax(float* address, const float val)
{
if (*address > val) {
return *address;
}
int* const addressInt = (int*)address;
int old = *addressInt, assumed;
do {
assumed = old;
if (__int_as_float(assumed) > val) {
break;
}
old = atomicCAS(addressInt, assumed, __float_as_int(val));
} while (old != assumed);
return old;
}
__global__
void find_max_int_kernel(const int* __restrict__ arr, const u32 arr_size, int* maxval)
{
__shared__ int shared_maxval;
u32 id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (id_x == 0) {
shared_maxval = arr[0];
}
__syncthreads();
int register_maxval = shared_maxval;
if (blockIdx.x == 0) {
for (u32 i = threadIdx.x; i < arr_size; i += blockDim.x) {
register_maxval = (register_maxval > arr[i])? register_maxval : arr[i];
}
}
atomicMax(&shared_maxval, register_maxval);
__syncthreads();
if (id_x == 0) {
*maxval = shared_maxval;
}
}
__global__
void find_max_float_kernel(const float* __restrict__ arr, const u32 arr_size, float* maxval)
{
__shared__ float shared_maxval;
u32 id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (id_x == 0) {
shared_maxval = arr[0];
}
__syncthreads();
float register_maxval = shared_maxval;
if (blockIdx.x == 0) {
for (u32 i = threadIdx.x; i < arr_size; i += blockDim.x) {
register_maxval = (register_maxval > arr[i])? register_maxval : arr[i];
}
}
atomicFloatMax(&shared_maxval, register_maxval);
__syncthreads();
if (id_x == 0) {
*maxval = shared_maxval;
}
}
// __device__
// void warp_find_max_kernel(const int* __restrict__ arr, const u32 size, int* max)
// {
// }
// __host__
// int gpuWarpFindMax(int* h_arr, const u32 size)
// {
// assert(size == 32);
// int* d_arr;
// cudaMalloc((void**)&d_arr, size * sizeof(int));
// cudaMemcpy(d_arr, h_arr, size * sizeof(int), cudaMemcpyHostToDevice);
// int* d_max;
// cudaMalloc((void**)&d_max, 1 * sizeof(int));
// warp_find_max_kernel(d_arr, d_max);
// if (cudaSuccess != cudaGetLastError()) {
// printf("warp_find_max_kernel fault!\n");
// }
// int* h_max = (int*)malloc(1 * sizeof(int));
// cudaMemcpy(h_max, d_max, 1 * sizeof(int), cudaMemcpyDeviceToHost);
// int max = *h_max;
// cudaFree(d_arr);
// cudaFree(d_max);
// free(h_max);
// return max;
// }
template <>
int gpuFindMax<int>(int* h_arr, const u32 arr_size)
{
assert(arr_size > 0);
int* d_arr;
cudaMalloc((void**)&d_arr, arr_size * sizeof(int));
cudaMemcpy(d_arr, h_arr, arr_size * sizeof(int), cudaMemcpyHostToDevice);
int* d_maxval;
cudaMalloc((void**)&d_maxval, 1 * sizeof(int));
dim3 blocks = BLOCK_SIZE;
dim3 grid = (arr_size + BLOCK_SIZE - 1) / BLOCK_SIZE;
find_max_int_kernel <<< grid , blocks >>> (d_arr, arr_size, d_maxval);
if (cudaSuccess != cudaGetLastError()) {
printf("find_max_int_kernel fault!\n");
}
int* h_maxval = (int*)malloc(1 * sizeof(int));
cudaMemcpy(h_maxval, d_maxval, 1 * sizeof(int), cudaMemcpyDeviceToHost);
int result = *h_maxval;
cudaFree(d_arr);
cudaFree(d_maxval);
free(h_maxval);
return result;
}
template <>
float gpuFindMax<float>(float* h_arr, const u32 arr_size)
{
assert(arr_size > 0);
float* d_arr;
cudaMalloc((void**)&d_arr, arr_size * sizeof(float));
cudaMemcpy(d_arr, h_arr, arr_size * sizeof(float), cudaMemcpyHostToDevice);
float* d_maxval;
cudaMalloc((void**)&d_maxval, 1 * sizeof(float));
dim3 blocks = BLOCK_SIZE;
dim3 grid = (arr_size + BLOCK_SIZE - 1) / BLOCK_SIZE;
find_max_float_kernel <<< grid , blocks >>> (d_arr, arr_size, d_maxval);
if (cudaSuccess != cudaGetLastError()) {
printf("find_max_float_kernel fault!\n");
}
float* h_maxval = (float*)malloc(1 * sizeof(float));
cudaMemcpy(h_maxval, d_maxval, 1 * sizeof(float), cudaMemcpyDeviceToHost);
float result = *h_maxval;
cudaFree(d_arr);
cudaFree(d_maxval);
free(h_maxval);
return result;
}
template <>
int cpuFindMax<int>(int* arr, const u32 arr_size)
{
assert(arr_size > 0);
int maxval = arr[0];
for (u32 i = 0; i < arr_size; i++) {
maxval = (arr[i] > maxval)? arr[i] : maxval;
}
return maxval;
}
template <>
float cpuFindMax<float>(float* arr, const u32 arr_size)
{
assert(arr_size > 0);
float maxval = arr[0];
for (u32 i = 0; i < arr_size; i++) {
maxval = (arr[i] > maxval)? arr[i] : maxval;
}
return maxval;
}
int main()
{
const u32 arr_size = 1000;
int* int_arr = (int*)malloc(arr_size * sizeof(int));
CREATE_RAND_ARR(int_arr, arr_size, 0, 1000);
float* float_arr = (float*)malloc(arr_size * sizeof(float));
CREATE_RAND_ARR(float_arr, arr_size, 0, 1000);
for (u32 i = 0; i < arr_size; i++) {
float_arr[i] /= 10.0;
}
int cpu_int_maxval = cpuFindMax<int>(int_arr, arr_size);
printf("CPU find max int element: %d\n", cpu_int_maxval);
int gpu_int_maxval = gpuFindMax<int>(int_arr, arr_size);
printf("GPU find max int element: %d\n", gpu_int_maxval);
float cpu_float_maxval = cpuFindMax<float>(float_arr, arr_size);
printf("CPU find max float element: %f\n", cpu_float_maxval);
float gpu_float_maxval = gpuFindMax<float>(float_arr, arr_size);
printf("GPU find max float element: %f\n", gpu_float_maxval);
const u32 warp_size = 32;
int* warp_arr = (int*)malloc(warp_size * sizeof(int));
CREATE_RAND_ARR(warp_arr, warp_size, 0, 1000);
// int gpu_warp_int_maxval = gpuWarpFindMax(warp_arr, warp_size);
// printf("GPU warp find max int element: %d\n", gpu_warp_int_maxval);
free(int_arr);
free(float_arr);
free(warp_arr);
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <assert.h>
#include <hip/hip_runtime.h>
#define u32 unsigned int
#define BLOCK_SIZE 64
#define CREATE_RAND_ARR(arr, size, min, max) \
do { \
time_t t; \
srand((unsigned)time(&t)); \
for (u32 i = 0; i < size; i++) \
arr[i] = rand() % max + min; \
} while (0) \
template <typename T>
T cpuFindMax(T* arr, const u32 arr_size);
template <typename T>
T gpuFindMax(T* arr, const u32 arr_size);
__device__
float atomicFloatMax(float* address, const float val)
{
if (*address > val) {
return *address;
}
int* const addressInt = (int*)address;
int old = *addressInt, assumed;
do {
assumed = old;
if (__int_as_float(assumed) > val) {
break;
}
old = atomicCAS(addressInt, assumed, __float_as_int(val));
} while (old != assumed);
return old;
}
__global__
void find_max_int_kernel(const int* __restrict__ arr, const u32 arr_size, int* maxval)
{
__shared__ int shared_maxval;
u32 id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (id_x == 0) {
shared_maxval = arr[0];
}
__syncthreads();
int register_maxval = shared_maxval;
if (blockIdx.x == 0) {
for (u32 i = threadIdx.x; i < arr_size; i += blockDim.x) {
register_maxval = (register_maxval > arr[i])? register_maxval : arr[i];
}
}
atomicMax(&shared_maxval, register_maxval);
__syncthreads();
if (id_x == 0) {
*maxval = shared_maxval;
}
}
__global__
void find_max_float_kernel(const float* __restrict__ arr, const u32 arr_size, float* maxval)
{
__shared__ float shared_maxval;
u32 id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (id_x == 0) {
shared_maxval = arr[0];
}
__syncthreads();
float register_maxval = shared_maxval;
if (blockIdx.x == 0) {
for (u32 i = threadIdx.x; i < arr_size; i += blockDim.x) {
register_maxval = (register_maxval > arr[i])? register_maxval : arr[i];
}
}
atomicFloatMax(&shared_maxval, register_maxval);
__syncthreads();
if (id_x == 0) {
*maxval = shared_maxval;
}
}
// __device__
// void warp_find_max_kernel(const int* __restrict__ arr, const u32 size, int* max)
// {
// }
// __host__
// int gpuWarpFindMax(int* h_arr, const u32 size)
// {
// assert(size == 32);
// int* d_arr;
// cudaMalloc((void**)&d_arr, size * sizeof(int));
// cudaMemcpy(d_arr, h_arr, size * sizeof(int), cudaMemcpyHostToDevice);
// int* d_max;
// cudaMalloc((void**)&d_max, 1 * sizeof(int));
// warp_find_max_kernel(d_arr, d_max);
// if (cudaSuccess != cudaGetLastError()) {
// printf("warp_find_max_kernel fault!\n");
// }
// int* h_max = (int*)malloc(1 * sizeof(int));
// cudaMemcpy(h_max, d_max, 1 * sizeof(int), cudaMemcpyDeviceToHost);
// int max = *h_max;
// cudaFree(d_arr);
// cudaFree(d_max);
// free(h_max);
// return max;
// }
template <>
int gpuFindMax<int>(int* h_arr, const u32 arr_size)
{
assert(arr_size > 0);
int* d_arr;
hipMalloc((void**)&d_arr, arr_size * sizeof(int));
hipMemcpy(d_arr, h_arr, arr_size * sizeof(int), hipMemcpyHostToDevice);
int* d_maxval;
hipMalloc((void**)&d_maxval, 1 * sizeof(int));
dim3 blocks = BLOCK_SIZE;
dim3 grid = (arr_size + BLOCK_SIZE - 1) / BLOCK_SIZE;
find_max_int_kernel <<< grid , blocks >>> (d_arr, arr_size, d_maxval);
if (hipSuccess != hipGetLastError()) {
printf("find_max_int_kernel fault!\n");
}
int* h_maxval = (int*)malloc(1 * sizeof(int));
hipMemcpy(h_maxval, d_maxval, 1 * sizeof(int), hipMemcpyDeviceToHost);
int result = *h_maxval;
hipFree(d_arr);
hipFree(d_maxval);
free(h_maxval);
return result;
}
template <>
float gpuFindMax<float>(float* h_arr, const u32 arr_size)
{
assert(arr_size > 0);
float* d_arr;
hipMalloc((void**)&d_arr, arr_size * sizeof(float));
hipMemcpy(d_arr, h_arr, arr_size * sizeof(float), hipMemcpyHostToDevice);
float* d_maxval;
hipMalloc((void**)&d_maxval, 1 * sizeof(float));
dim3 blocks = BLOCK_SIZE;
dim3 grid = (arr_size + BLOCK_SIZE - 1) / BLOCK_SIZE;
find_max_float_kernel <<< grid , blocks >>> (d_arr, arr_size, d_maxval);
if (hipSuccess != hipGetLastError()) {
printf("find_max_float_kernel fault!\n");
}
float* h_maxval = (float*)malloc(1 * sizeof(float));
hipMemcpy(h_maxval, d_maxval, 1 * sizeof(float), hipMemcpyDeviceToHost);
float result = *h_maxval;
hipFree(d_arr);
hipFree(d_maxval);
free(h_maxval);
return result;
}
template <>
int cpuFindMax<int>(int* arr, const u32 arr_size)
{
assert(arr_size > 0);
int maxval = arr[0];
for (u32 i = 0; i < arr_size; i++) {
maxval = (arr[i] > maxval)? arr[i] : maxval;
}
return maxval;
}
template <>
float cpuFindMax<float>(float* arr, const u32 arr_size)
{
assert(arr_size > 0);
float maxval = arr[0];
for (u32 i = 0; i < arr_size; i++) {
maxval = (arr[i] > maxval)? arr[i] : maxval;
}
return maxval;
}
int main()
{
const u32 arr_size = 1000;
int* int_arr = (int*)malloc(arr_size * sizeof(int));
CREATE_RAND_ARR(int_arr, arr_size, 0, 1000);
float* float_arr = (float*)malloc(arr_size * sizeof(float));
CREATE_RAND_ARR(float_arr, arr_size, 0, 1000);
for (u32 i = 0; i < arr_size; i++) {
float_arr[i] /= 10.0;
}
int cpu_int_maxval = cpuFindMax<int>(int_arr, arr_size);
printf("CPU find max int element: %d\n", cpu_int_maxval);
int gpu_int_maxval = gpuFindMax<int>(int_arr, arr_size);
printf("GPU find max int element: %d\n", gpu_int_maxval);
float cpu_float_maxval = cpuFindMax<float>(float_arr, arr_size);
printf("CPU find max float element: %f\n", cpu_float_maxval);
float gpu_float_maxval = gpuFindMax<float>(float_arr, arr_size);
printf("GPU find max float element: %f\n", gpu_float_maxval);
const u32 warp_size = 32;
int* warp_arr = (int*)malloc(warp_size * sizeof(int));
CREATE_RAND_ARR(warp_arr, warp_size, 0, 1000);
// int gpu_warp_int_maxval = gpuWarpFindMax(warp_arr, warp_size);
// printf("GPU warp find max int element: %d\n", gpu_warp_int_maxval);
free(int_arr);
free(float_arr);
free(warp_arr);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <assert.h>
#include <hip/hip_runtime.h>
#define u32 unsigned int
#define BLOCK_SIZE 64
#define CREATE_RAND_ARR(arr, size, min, max) \
do { \
time_t t; \
srand((unsigned)time(&t)); \
for (u32 i = 0; i < size; i++) \
arr[i] = rand() % max + min; \
} while (0) \
template <typename T>
T cpuFindMax(T* arr, const u32 arr_size);
template <typename T>
T gpuFindMax(T* arr, const u32 arr_size);
__device__
float atomicFloatMax(float* address, const float val)
{
if (*address > val) {
return *address;
}
int* const addressInt = (int*)address;
int old = *addressInt, assumed;
do {
assumed = old;
if (__int_as_float(assumed) > val) {
break;
}
old = atomicCAS(addressInt, assumed, __float_as_int(val));
} while (old != assumed);
return old;
}
__global__
void find_max_int_kernel(const int* __restrict__ arr, const u32 arr_size, int* maxval)
{
__shared__ int shared_maxval;
u32 id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (id_x == 0) {
shared_maxval = arr[0];
}
__syncthreads();
int register_maxval = shared_maxval;
if (blockIdx.x == 0) {
for (u32 i = threadIdx.x; i < arr_size; i += blockDim.x) {
register_maxval = (register_maxval > arr[i])? register_maxval : arr[i];
}
}
atomicMax(&shared_maxval, register_maxval);
__syncthreads();
if (id_x == 0) {
*maxval = shared_maxval;
}
}
__global__
void find_max_float_kernel(const float* __restrict__ arr, const u32 arr_size, float* maxval)
{
__shared__ float shared_maxval;
u32 id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (id_x == 0) {
shared_maxval = arr[0];
}
__syncthreads();
float register_maxval = shared_maxval;
if (blockIdx.x == 0) {
for (u32 i = threadIdx.x; i < arr_size; i += blockDim.x) {
register_maxval = (register_maxval > arr[i])? register_maxval : arr[i];
}
}
atomicFloatMax(&shared_maxval, register_maxval);
__syncthreads();
if (id_x == 0) {
*maxval = shared_maxval;
}
}
// __device__
// void warp_find_max_kernel(const int* __restrict__ arr, const u32 size, int* max)
// {
// }
// __host__
// int gpuWarpFindMax(int* h_arr, const u32 size)
// {
// assert(size == 32);
// int* d_arr;
// cudaMalloc((void**)&d_arr, size * sizeof(int));
// cudaMemcpy(d_arr, h_arr, size * sizeof(int), cudaMemcpyHostToDevice);
// int* d_max;
// cudaMalloc((void**)&d_max, 1 * sizeof(int));
// warp_find_max_kernel(d_arr, d_max);
// if (cudaSuccess != cudaGetLastError()) {
// printf("warp_find_max_kernel fault!\n");
// }
// int* h_max = (int*)malloc(1 * sizeof(int));
// cudaMemcpy(h_max, d_max, 1 * sizeof(int), cudaMemcpyDeviceToHost);
// int max = *h_max;
// cudaFree(d_arr);
// cudaFree(d_max);
// free(h_max);
// return max;
// }
template <>
int gpuFindMax<int>(int* h_arr, const u32 arr_size)
{
assert(arr_size > 0);
int* d_arr;
hipMalloc((void**)&d_arr, arr_size * sizeof(int));
hipMemcpy(d_arr, h_arr, arr_size * sizeof(int), hipMemcpyHostToDevice);
int* d_maxval;
hipMalloc((void**)&d_maxval, 1 * sizeof(int));
dim3 blocks = BLOCK_SIZE;
dim3 grid = (arr_size + BLOCK_SIZE - 1) / BLOCK_SIZE;
find_max_int_kernel <<< grid , blocks >>> (d_arr, arr_size, d_maxval);
if (hipSuccess != hipGetLastError()) {
printf("find_max_int_kernel fault!\n");
}
int* h_maxval = (int*)malloc(1 * sizeof(int));
hipMemcpy(h_maxval, d_maxval, 1 * sizeof(int), hipMemcpyDeviceToHost);
int result = *h_maxval;
hipFree(d_arr);
hipFree(d_maxval);
free(h_maxval);
return result;
}
template <>
float gpuFindMax<float>(float* h_arr, const u32 arr_size)
{
assert(arr_size > 0);
float* d_arr;
hipMalloc((void**)&d_arr, arr_size * sizeof(float));
hipMemcpy(d_arr, h_arr, arr_size * sizeof(float), hipMemcpyHostToDevice);
float* d_maxval;
hipMalloc((void**)&d_maxval, 1 * sizeof(float));
dim3 blocks = BLOCK_SIZE;
dim3 grid = (arr_size + BLOCK_SIZE - 1) / BLOCK_SIZE;
find_max_float_kernel <<< grid , blocks >>> (d_arr, arr_size, d_maxval);
if (hipSuccess != hipGetLastError()) {
printf("find_max_float_kernel fault!\n");
}
float* h_maxval = (float*)malloc(1 * sizeof(float));
hipMemcpy(h_maxval, d_maxval, 1 * sizeof(float), hipMemcpyDeviceToHost);
float result = *h_maxval;
hipFree(d_arr);
hipFree(d_maxval);
free(h_maxval);
return result;
}
template <>
int cpuFindMax<int>(int* arr, const u32 arr_size)
{
assert(arr_size > 0);
int maxval = arr[0];
for (u32 i = 0; i < arr_size; i++) {
maxval = (arr[i] > maxval)? arr[i] : maxval;
}
return maxval;
}
template <>
float cpuFindMax<float>(float* arr, const u32 arr_size)
{
assert(arr_size > 0);
float maxval = arr[0];
for (u32 i = 0; i < arr_size; i++) {
maxval = (arr[i] > maxval)? arr[i] : maxval;
}
return maxval;
}
int main()
{
const u32 arr_size = 1000;
int* int_arr = (int*)malloc(arr_size * sizeof(int));
CREATE_RAND_ARR(int_arr, arr_size, 0, 1000);
float* float_arr = (float*)malloc(arr_size * sizeof(float));
CREATE_RAND_ARR(float_arr, arr_size, 0, 1000);
for (u32 i = 0; i < arr_size; i++) {
float_arr[i] /= 10.0;
}
int cpu_int_maxval = cpuFindMax<int>(int_arr, arr_size);
printf("CPU find max int element: %d\n", cpu_int_maxval);
int gpu_int_maxval = gpuFindMax<int>(int_arr, arr_size);
printf("GPU find max int element: %d\n", gpu_int_maxval);
float cpu_float_maxval = cpuFindMax<float>(float_arr, arr_size);
printf("CPU find max float element: %f\n", cpu_float_maxval);
float gpu_float_maxval = gpuFindMax<float>(float_arr, arr_size);
printf("GPU find max float element: %f\n", gpu_float_maxval);
const u32 warp_size = 32;
int* warp_arr = (int*)malloc(warp_size * sizeof(int));
CREATE_RAND_ARR(warp_arr, warp_size, 0, 1000);
// int gpu_warp_int_maxval = gpuWarpFindMax(warp_arr, warp_size);
// printf("GPU warp find max int element: %d\n", gpu_warp_int_maxval);
free(int_arr);
free(float_arr);
free(warp_arr);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19find_max_int_kernelPKijPi
.globl _Z19find_max_int_kernelPKijPi
.p2align 8
.type _Z19find_max_int_kernelPKijPi,@function
_Z19find_max_int_kernelPKijPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x0
v_sub_nc_u32_e32 v1, 0, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s2, s15, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b32 s6, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s6
ds_store_b32 v1, v2
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_load_b32 s6, s[0:1], 0x8
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cmp_eq_u32 s15, 0
ds_load_b32 v2, v1
s_cselect_b32 s7, -1, 0
v_cmp_gt_u32_e64 s2, s6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s7, s2
s_and_saveexec_b32 s7, s2
s_cbranch_execz .LBB0_6
s_mov_b32 s8, 0
.LBB0_4:
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_add_nc_u32_e32 v0, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s2, s4, v3
v_add_co_ci_u32_e64 v4, s2, s5, v4, s2
s_delay_alu instid0(VALU_DEP_3)
v_cmp_le_u32_e64 s2, s6, v0
global_load_b32 v3, v[3:4], off
s_or_b32 s8, s2, s8
s_waitcnt vmcnt(0) lgkmcnt(0)
v_max_i32_e32 v2, v2, v3
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_4
s_or_b32 exec_lo, exec_lo, s8
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s7
s_mov_b32 s2, exec_lo
s_brev_b32 s3, 1
.LBB0_7:
s_ctz_i32_b32 s4, s2
s_waitcnt lgkmcnt(0)
v_readlane_b32 s5, v2, s4
s_lshl_b32 s4, 1, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_not1_b32 s2, s2, s4
s_max_i32 s3, s3, s5
s_cmp_lg_u32 s2, 0
s_cbranch_scc1 .LBB0_7
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s2, 0, v0
s_and_saveexec_b32 s4, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s4
s_cbranch_execz .LBB0_10
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s3
ds_max_i32 v0, v1
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_12
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x10
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19find_max_int_kernelPKijPi
.amdhsa_group_segment_fixed_size 4
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19find_max_int_kernelPKijPi, .Lfunc_end0-_Z19find_max_int_kernelPKijPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z21find_max_float_kernelPKfjPf
.globl _Z21find_max_float_kernelPKfjPf
.p2align 8
.type _Z21find_max_float_kernelPKfjPf,@function
_Z21find_max_float_kernelPKfjPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x0
v_sub_nc_u32_e32 v1, 0, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s2, s15, s6
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_2
s_load_b32 s3, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s3
ds_store_b32 v1, v2
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s2
v_mov_b32_e32 v1, 0
s_load_b32 s7, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v1
s_cmp_eq_u32 s15, 0
s_cselect_b32 s3, -1, 0
v_cmp_gt_u32_e64 s2, s7, v0
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s3, s2
s_and_saveexec_b32 s8, s2
s_cbranch_execz .LBB1_6
v_mov_b32_e32 v2, v3
s_mov_b32 s9, 0
.p2align 6
.LBB1_4:
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_add_nc_u32_e32 v0, s6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s2, s4, v4
v_add_co_ci_u32_e64 v5, s2, s5, v5, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_cmp_le_u32_e64 s2, s7, v0
global_load_b32 v4, v[4:5], off
s_or_b32 s9, s2, s9
s_waitcnt vmcnt(0)
v_cmp_gt_f32_e64 s3, v2, v4
v_cndmask_b32_e64 v2, v4, v2, s3
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB1_4
s_or_b32 exec_lo, exec_lo, s9
.LBB1_6:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s8
s_mov_b32 s3, exec_lo
v_cmpx_ngt_f32_e32 v3, v2
s_cbranch_execz .LBB1_11
v_mov_b32_e32 v0, 0
s_mov_b32 s4, 0
ds_load_b32 v1, v0
s_branch .LBB1_9
.p2align 6
.LBB1_8:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, exec_lo, s5
s_or_b32 s4, s2, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB1_11
.LBB1_9:
s_or_b32 s5, s5, exec_lo
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_nlt_f32_e32 v2, v1
s_cbranch_execz .LBB1_8
ds_cmpstore_rtn_b32 v3, v0, v2, v1
s_and_not1_b32 s5, s5, exec_lo
s_waitcnt lgkmcnt(0)
v_cmp_eq_u32_e64 s2, v3, v1
v_mov_b32_e32 v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, exec_lo
s_or_b32 s5, s5, s2
s_branch .LBB1_8
.LBB1_11:
s_or_b32 exec_lo, exec_lo, s3
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_13
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x10
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB1_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21find_max_float_kernelPKfjPf
.amdhsa_group_segment_fixed_size 4
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z21find_max_float_kernelPKfjPf, .Lfunc_end1-_Z21find_max_float_kernelPKfjPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .actual_access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19find_max_int_kernelPKijPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19find_max_int_kernelPKijPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .actual_access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21find_max_float_kernelPKfjPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21find_max_float_kernelPKfjPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <assert.h>
#include <hip/hip_runtime.h>
#define u32 unsigned int
#define BLOCK_SIZE 64
#define CREATE_RAND_ARR(arr, size, min, max) \
do { \
time_t t; \
srand((unsigned)time(&t)); \
for (u32 i = 0; i < size; i++) \
arr[i] = rand() % max + min; \
} while (0) \
template <typename T>
T cpuFindMax(T* arr, const u32 arr_size);
template <typename T>
T gpuFindMax(T* arr, const u32 arr_size);
__device__
float atomicFloatMax(float* address, const float val)
{
if (*address > val) {
return *address;
}
int* const addressInt = (int*)address;
int old = *addressInt, assumed;
do {
assumed = old;
if (__int_as_float(assumed) > val) {
break;
}
old = atomicCAS(addressInt, assumed, __float_as_int(val));
} while (old != assumed);
return old;
}
__global__
void find_max_int_kernel(const int* __restrict__ arr, const u32 arr_size, int* maxval)
{
__shared__ int shared_maxval;
u32 id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (id_x == 0) {
shared_maxval = arr[0];
}
__syncthreads();
int register_maxval = shared_maxval;
if (blockIdx.x == 0) {
for (u32 i = threadIdx.x; i < arr_size; i += blockDim.x) {
register_maxval = (register_maxval > arr[i])? register_maxval : arr[i];
}
}
atomicMax(&shared_maxval, register_maxval);
__syncthreads();
if (id_x == 0) {
*maxval = shared_maxval;
}
}
__global__
void find_max_float_kernel(const float* __restrict__ arr, const u32 arr_size, float* maxval)
{
__shared__ float shared_maxval;
u32 id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (id_x == 0) {
shared_maxval = arr[0];
}
__syncthreads();
float register_maxval = shared_maxval;
if (blockIdx.x == 0) {
for (u32 i = threadIdx.x; i < arr_size; i += blockDim.x) {
register_maxval = (register_maxval > arr[i])? register_maxval : arr[i];
}
}
atomicFloatMax(&shared_maxval, register_maxval);
__syncthreads();
if (id_x == 0) {
*maxval = shared_maxval;
}
}
// __device__
// void warp_find_max_kernel(const int* __restrict__ arr, const u32 size, int* max)
// {
// }
// __host__
// int gpuWarpFindMax(int* h_arr, const u32 size)
// {
// assert(size == 32);
// int* d_arr;
// cudaMalloc((void**)&d_arr, size * sizeof(int));
// cudaMemcpy(d_arr, h_arr, size * sizeof(int), cudaMemcpyHostToDevice);
// int* d_max;
// cudaMalloc((void**)&d_max, 1 * sizeof(int));
// warp_find_max_kernel(d_arr, d_max);
// if (cudaSuccess != cudaGetLastError()) {
// printf("warp_find_max_kernel fault!\n");
// }
// int* h_max = (int*)malloc(1 * sizeof(int));
// cudaMemcpy(h_max, d_max, 1 * sizeof(int), cudaMemcpyDeviceToHost);
// int max = *h_max;
// cudaFree(d_arr);
// cudaFree(d_max);
// free(h_max);
// return max;
// }
template <>
int gpuFindMax<int>(int* h_arr, const u32 arr_size)
{
assert(arr_size > 0);
int* d_arr;
hipMalloc((void**)&d_arr, arr_size * sizeof(int));
hipMemcpy(d_arr, h_arr, arr_size * sizeof(int), hipMemcpyHostToDevice);
int* d_maxval;
hipMalloc((void**)&d_maxval, 1 * sizeof(int));
dim3 blocks = BLOCK_SIZE;
dim3 grid = (arr_size + BLOCK_SIZE - 1) / BLOCK_SIZE;
find_max_int_kernel <<< grid , blocks >>> (d_arr, arr_size, d_maxval);
if (hipSuccess != hipGetLastError()) {
printf("find_max_int_kernel fault!\n");
}
int* h_maxval = (int*)malloc(1 * sizeof(int));
hipMemcpy(h_maxval, d_maxval, 1 * sizeof(int), hipMemcpyDeviceToHost);
int result = *h_maxval;
hipFree(d_arr);
hipFree(d_maxval);
free(h_maxval);
return result;
}
template <>
float gpuFindMax<float>(float* h_arr, const u32 arr_size)
{
assert(arr_size > 0);
float* d_arr;
hipMalloc((void**)&d_arr, arr_size * sizeof(float));
hipMemcpy(d_arr, h_arr, arr_size * sizeof(float), hipMemcpyHostToDevice);
float* d_maxval;
hipMalloc((void**)&d_maxval, 1 * sizeof(float));
dim3 blocks = BLOCK_SIZE;
dim3 grid = (arr_size + BLOCK_SIZE - 1) / BLOCK_SIZE;
find_max_float_kernel <<< grid , blocks >>> (d_arr, arr_size, d_maxval);
if (hipSuccess != hipGetLastError()) {
printf("find_max_float_kernel fault!\n");
}
float* h_maxval = (float*)malloc(1 * sizeof(float));
hipMemcpy(h_maxval, d_maxval, 1 * sizeof(float), hipMemcpyDeviceToHost);
float result = *h_maxval;
hipFree(d_arr);
hipFree(d_maxval);
free(h_maxval);
return result;
}
template <>
int cpuFindMax<int>(int* arr, const u32 arr_size)
{
assert(arr_size > 0);
int maxval = arr[0];
for (u32 i = 0; i < arr_size; i++) {
maxval = (arr[i] > maxval)? arr[i] : maxval;
}
return maxval;
}
template <>
float cpuFindMax<float>(float* arr, const u32 arr_size)
{
assert(arr_size > 0);
float maxval = arr[0];
for (u32 i = 0; i < arr_size; i++) {
maxval = (arr[i] > maxval)? arr[i] : maxval;
}
return maxval;
}
int main()
{
const u32 arr_size = 1000;
int* int_arr = (int*)malloc(arr_size * sizeof(int));
CREATE_RAND_ARR(int_arr, arr_size, 0, 1000);
float* float_arr = (float*)malloc(arr_size * sizeof(float));
CREATE_RAND_ARR(float_arr, arr_size, 0, 1000);
for (u32 i = 0; i < arr_size; i++) {
float_arr[i] /= 10.0;
}
int cpu_int_maxval = cpuFindMax<int>(int_arr, arr_size);
printf("CPU find max int element: %d\n", cpu_int_maxval);
int gpu_int_maxval = gpuFindMax<int>(int_arr, arr_size);
printf("GPU find max int element: %d\n", gpu_int_maxval);
float cpu_float_maxval = cpuFindMax<float>(float_arr, arr_size);
printf("CPU find max float element: %f\n", cpu_float_maxval);
float gpu_float_maxval = gpuFindMax<float>(float_arr, arr_size);
printf("GPU find max float element: %f\n", gpu_float_maxval);
const u32 warp_size = 32;
int* warp_arr = (int*)malloc(warp_size * sizeof(int));
CREATE_RAND_ARR(warp_arr, warp_size, 0, 1000);
// int gpu_warp_int_maxval = gpuWarpFindMax(warp_arr, warp_size);
// printf("GPU warp find max int element: %d\n", gpu_warp_int_maxval);
free(int_arr);
free(float_arr);
free(warp_arr);
return 0;
} | .text
.file "main.hip"
.globl _Z34__device_stub__find_max_int_kernelPKijPi # -- Begin function _Z34__device_stub__find_max_int_kernelPKijPi
.p2align 4, 0x90
.type _Z34__device_stub__find_max_int_kernelPKijPi,@function
_Z34__device_stub__find_max_int_kernelPKijPi: # @_Z34__device_stub__find_max_int_kernelPKijPi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19find_max_int_kernelPKijPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z34__device_stub__find_max_int_kernelPKijPi, .Lfunc_end0-_Z34__device_stub__find_max_int_kernelPKijPi
.cfi_endproc
# -- End function
.globl _Z36__device_stub__find_max_float_kernelPKfjPf # -- Begin function _Z36__device_stub__find_max_float_kernelPKfjPf
.p2align 4, 0x90
.type _Z36__device_stub__find_max_float_kernelPKfjPf,@function
_Z36__device_stub__find_max_float_kernelPKfjPf: # @_Z36__device_stub__find_max_float_kernelPKfjPf
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21find_max_float_kernelPKfjPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z36__device_stub__find_max_float_kernelPKfjPf, .Lfunc_end1-_Z36__device_stub__find_max_float_kernelPKfjPf
.cfi_endproc
# -- End function
.globl _Z10gpuFindMaxIiET_PS0_j # -- Begin function _Z10gpuFindMaxIiET_PS0_j
.p2align 4, 0x90
.type _Z10gpuFindMaxIiET_PS0_j,@function
_Z10gpuFindMaxIiET_PS0_j: # @_Z10gpuFindMaxIiET_PS0_j
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebx
movq %rdi, %r14
movl %esi, %r15d
shlq $2, %r15
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leal 63(%rbx), %edi
shrl $6, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $64, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movl %ebx, 28(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 28(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19find_max_int_kernelPKijPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipGetLastError
testl %eax, %eax
je .LBB2_4
# %bb.3:
movl $.Lstr, %edi
callq puts@PLT
.LBB2_4:
movl $4, %edi
callq malloc
movq %rax, %rbx
movq 8(%rsp), %rsi
movl $4, %edx
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
movl (%rbx), %ebp
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movl %ebp, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z10gpuFindMaxIiET_PS0_j, .Lfunc_end2-_Z10gpuFindMaxIiET_PS0_j
.cfi_endproc
# -- End function
.globl _Z10gpuFindMaxIfET_PS0_j # -- Begin function _Z10gpuFindMaxIfET_PS0_j
.p2align 4, 0x90
.type _Z10gpuFindMaxIfET_PS0_j,@function
_Z10gpuFindMaxIfET_PS0_j: # @_Z10gpuFindMaxIfET_PS0_j
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %ebx
movq %rdi, %r14
movl %esi, %r15d
shlq $2, %r15
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leal 63(%rbx), %edi
shrl $6, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $64, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movl %ebx, 28(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 28(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z21find_max_float_kernelPKfjPf, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
callq hipGetLastError
testl %eax, %eax
je .LBB3_4
# %bb.3:
movl $.Lstr.1, %edi
callq puts@PLT
.LBB3_4:
movl $4, %edi
callq malloc
movq %rax, %rbx
movq 8(%rsp), %rsi
movl $4, %edx
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, 24(%rsp) # 4-byte Spill
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movss 24(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z10gpuFindMaxIfET_PS0_j, .Lfunc_end3-_Z10gpuFindMaxIfET_PS0_j
.cfi_endproc
# -- End function
.globl _Z10cpuFindMaxIiET_PS0_j # -- Begin function _Z10cpuFindMaxIiET_PS0_j
.p2align 4, 0x90
.type _Z10cpuFindMaxIiET_PS0_j,@function
_Z10cpuFindMaxIiET_PS0_j: # @_Z10cpuFindMaxIiET_PS0_j
.cfi_startproc
# %bb.0:
movl (%rdi), %eax
testl %esi, %esi
je .LBB4_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rdi,%rdx,4), %esi
cmpl %eax, %esi
cmovgl %esi, %eax
incq %rdx
cmpq %rdx, %rcx
jne .LBB4_2
.LBB4_3: # %._crit_edge
retq
.Lfunc_end4:
.size _Z10cpuFindMaxIiET_PS0_j, .Lfunc_end4-_Z10cpuFindMaxIiET_PS0_j
.cfi_endproc
# -- End function
.globl _Z10cpuFindMaxIfET_PS0_j # -- Begin function _Z10cpuFindMaxIfET_PS0_j
.p2align 4, 0x90
.type _Z10cpuFindMaxIfET_PS0_j,@function
_Z10cpuFindMaxIfET_PS0_j: # @_Z10cpuFindMaxIfET_PS0_j
.cfi_startproc
# %bb.0:
movss (%rdi), %xmm1 # xmm1 = mem[0],zero,zero,zero
testl %esi, %esi
je .LBB5_1
# %bb.3: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB5_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rdi,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
maxss %xmm1, %xmm0
incq %rcx
movaps %xmm0, %xmm1
cmpq %rcx, %rax
jne .LBB5_4
# %bb.2: # %._crit_edge
retq
.LBB5_1:
movaps %xmm1, %xmm0
retq
.Lfunc_end5:
.size _Z10cpuFindMaxIfET_PS0_j, .Lfunc_end5-_Z10cpuFindMaxIfET_PS0_j
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI6_0:
.long 0x41200000 # float 10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4000, %edi # imm = 0xFA0
callq malloc
movq %rax, %rbx
movq %rsp, %rdi
callq time
movl %eax, %edi
callq srand
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB6_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $1000, %r14 # imm = 0x3E8
jne .LBB6_1
# %bb.2:
movl $4000, %edi # imm = 0xFA0
callq malloc
movq %rax, %r14
movq %rsp, %rdi
callq time
movl %eax, %edi
callq srand
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB6_3: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%r15,4)
incq %r15
cmpq $1000, %r15 # imm = 0x3E8
jne .LBB6_3
# %bb.4:
xorl %eax, %eax
movss .LCPI6_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB6_5: # =>This Inner Loop Header: Depth=1
movss (%r14,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
movss %xmm1, (%r14,%rax,4)
incq %rax
cmpq $1000, %rax # imm = 0x3E8
jne .LBB6_5
# %bb.6:
movl (%rbx), %esi
xorl %eax, %eax
.p2align 4, 0x90
.LBB6_7: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl (%rbx,%rax,4), %ecx
cmpl %esi, %ecx
cmovgl %ecx, %esi
incq %rax
cmpq $1000, %rax # imm = 0x3E8
jne .LBB6_7
# %bb.8: # %_Z10cpuFindMaxIiET_PS0_j.exit
xorl %r15d, %r15d
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
movl $1000, %esi # imm = 0x3E8
callq _Z10gpuFindMaxIiET_PS0_j
movl $.L.str.3, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
movss (%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB6_9: # %.lr.ph.i29
# =>This Inner Loop Header: Depth=1
movaps %xmm0, %xmm1
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
maxss %xmm1, %xmm0
incq %r15
cmpq $1000, %r15 # imm = 0x3E8
jne .LBB6_9
# %bb.10: # %_Z10cpuFindMaxIfET_PS0_j.exit
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movq %r14, %rdi
movl $1000, %esi # imm = 0x3E8
callq _Z10gpuFindMaxIfET_PS0_j
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
movq %rsp, %rdi
callq time
movl %eax, %edi
callq srand
movl $32, %ebp
.p2align 4, 0x90
.LBB6_11: # =>This Inner Loop Header: Depth=1
callq rand
decl %ebp
jne .LBB6_11
# %bb.12:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19find_max_int_kernelPKijPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21find_max_float_kernelPKfjPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19find_max_int_kernelPKijPi,@object # @_Z19find_max_int_kernelPKijPi
.section .rodata,"a",@progbits
.globl _Z19find_max_int_kernelPKijPi
.p2align 3, 0x0
_Z19find_max_int_kernelPKijPi:
.quad _Z34__device_stub__find_max_int_kernelPKijPi
.size _Z19find_max_int_kernelPKijPi, 8
.type _Z21find_max_float_kernelPKfjPf,@object # @_Z21find_max_float_kernelPKfjPf
.globl _Z21find_max_float_kernelPKfjPf
.p2align 3, 0x0
_Z21find_max_float_kernelPKfjPf:
.quad _Z36__device_stub__find_max_float_kernelPKfjPf
.size _Z21find_max_float_kernelPKfjPf, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "CPU find max int element: %d\n"
.size .L.str.2, 30
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "GPU find max int element: %d\n"
.size .L.str.3, 30
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "CPU find max float element: %f\n"
.size .L.str.4, 32
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "GPU find max float element: %f\n"
.size .L.str.5, 32
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19find_max_int_kernelPKijPi"
.size .L__unnamed_1, 30
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z21find_max_float_kernelPKfjPf"
.size .L__unnamed_2, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "find_max_int_kernel fault!"
.size .Lstr, 27
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "find_max_float_kernel fault!"
.size .Lstr.1, 29
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__find_max_int_kernelPKijPi
.addrsig_sym _Z36__device_stub__find_max_float_kernelPKfjPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19find_max_int_kernelPKijPi
.addrsig_sym _Z21find_max_float_kernelPKfjPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z21find_max_float_kernelPKfjPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2UR UR6, SR_CTAID.X ; /* 0x00000000000679c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0030*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0040*/ BSSY B0, 0xf0 ; /* 0x000000a000007945 */
/* 0x000fe20003800000 */
/*0050*/ UIMAD UR4, UR6, UR4, URZ ; /* 0x00000004060472a4 */
/* 0x001fe2000f8e023f */
/*0060*/ IMAD.MOV R2, RZ, RZ, -R0 ; /* 0x000000ffff027224 */
/* 0x002fca00078e0a00 */
/*0070*/ ISETP.NE.AND P1, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x000fe2000bf25270 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd80000000a00 */
/*0090*/ @P1 BRA 0xe0 ; /* 0x0000004000001947 */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fca00078e00ff */
/*00c0*/ LDG.E.CONSTANT R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e9900 */
/*00d0*/ STS [RZ], R2 ; /* 0x00000002ff007388 */
/* 0x0041e40000000800 */
/*00e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0100*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fc80003f06070 */
/*0110*/ ISETP.NE.OR P0, PT, RZ, UR6, P0 ; /* 0x00000006ff007c0c */
/* 0x000fe20008705670 */
/*0120*/ BSSY B0, 0x200 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0130*/ LDS R4, [RZ] ; /* 0x00000000ff047984 */
/* 0x000e640000000800 */
/*0140*/ IMAD.MOV.U32 R5, RZ, RZ, R4 ; /* 0x000000ffff057224 */
/* 0x002fd200078e0004 */
/*0150*/ @P0 BRA 0x1f0 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*0160*/ MOV R5, R4 ; /* 0x0000000400057202 */
/* 0x000fe40000000f00 */
/*0170*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0180*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fcc00078e0003 */
/*0190*/ LDG.E.CONSTANT R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e9900 */
/*01a0*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fc80007ffe0ff */
/*01b0*/ ISETP.GE.U32.AND P2, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe40003f46070 */
/*01c0*/ FSETP.GT.AND P0, PT, R5, R2, PT ; /* 0x000000020500720b */
/* 0x004fc80003f04000 */
/*01d0*/ FSEL R5, R5, R2, P0 ; /* 0x0000000205057208 */
/* 0x000fce0000000000 */
/*01e0*/ @!P2 BRA 0x170 ; /* 0xffffff800000a947 */
/* 0x000fea000383ffff */
/*01f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0200*/ FSETP.GT.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fda0003f04000 */
/*0210*/ @P0 BRA 0x290 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0220*/ FSETP.GEU.AND P0, PT, R5, R4, PT ; /* 0x000000040500720b */
/* 0x000fe20003f0e000 */
/*0230*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fd80003800000 */
/*0240*/ @!P0 BRA 0x290 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0250*/ ATOMS.CAS R3, [RZ], R4, R5 ; /* 0x00000004ff03738d */
/* 0x000e640000000005 */
/*0260*/ ISETP.NE.AND P0, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x002fe20003f05270 */
/*0270*/ IMAD.MOV.U32 R4, RZ, RZ, R3 ; /* 0x000000ffff047224 */
/* 0x000fd800078e0003 */
/*0280*/ @P0 BRA 0x220 ; /* 0xffffff9000000947 */
/* 0x000fea000383ffff */
/*0290*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*02a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02b0*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*02c0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e620000000800 */
/*02d0*/ MOV R2, c[0x0][0x170] ; /* 0x00005c0000027a02 */
/* 0x001fe20000000f00 */
/*02e0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fca00078e00ff */
/*02f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101904 */
/*0300*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0310*/ BRA 0x310; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z19find_max_int_kernelPKijPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2UR UR5, SR_CTAID.X ; /* 0x00000000000579c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0030*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0040*/ BSSY B0, 0x120 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0050*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0060*/ S2R R5, SR_LANEID ; /* 0x0000000000057919 */
/* 0x000ea20000000000 */
/*0070*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x001fe2000f8e023f */
/*0080*/ IMAD.MOV R2, RZ, RZ, -R0 ; /* 0x000000ffff027224 */
/* 0x002fe200078e0a00 */
/*0090*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fc80003f06070 */
/*00a0*/ ISETP.NE.AND P1, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x000fe4000bf25270 */
/*00b0*/ ISETP.NE.OR P0, PT, RZ, UR5, P0 ; /* 0x00000005ff007c0c */
/* 0x000fd60008705670 */
/*00c0*/ @P1 BRA 0x110 ; /* 0x0000004000001947 */
/* 0x000fea0003800000 */
/*00d0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x004fe400078e00ff */
/*00e0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fca00078e00ff */
/*00f0*/ LDG.E.CONSTANT R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea8000c1e9900 */
/*0100*/ STS [RZ], R2 ; /* 0x00000002ff007388 */
/* 0x0041e40000000800 */
/*0110*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x004fea0003800000 */
/*0120*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0130*/ BSSY B0, 0x1e0 ; /* 0x000000a000007945 */
/* 0x000fe20003800000 */
/*0140*/ LDS R4, [RZ] ; /* 0x00000000ff047984 */
/* 0x000e620000000800 */
/*0150*/ @P0 BRA 0x1d0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0160*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0170*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fcc00078e0003 */
/*0180*/ LDG.E.CONSTANT R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e9900 */
/*0190*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fc80007ffe0ff */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe40003f06070 */
/*01b0*/ IMNMX R4, R3, R4, !PT ; /* 0x0000000403047217 */
/* 0x006fd60007800200 */
/*01c0*/ @!P0 BRA 0x160 ; /* 0xffffff9000008947 */
/* 0x000fea000383ffff */
/*01d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01e0*/ REDUX.MAX.S32 UR5, R4 ; /* 0x00000000040573c4 */
/* 0x002e620000014200 */
/*01f0*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*0200*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fcc00080e0000 */
/*0210*/ ISETP.EQ.U32.AND P0, PT, R5, UR4, PT ; /* 0x0000000405007c0c */
/* 0x000fe2000bf02070 */
/*0220*/ IMAD.U32 R0, RZ, RZ, UR5 ; /* 0x00000005ff007e24 */
/* 0x002fd8000f8e00ff */
/*0230*/ @P0 ATOMS.MAX.S32 RZ, [RZ], R0 ; /* 0x00000000ffff038c */
/* 0x0003e80001000200 */
/*0240*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0250*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0260*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x002e620000000800 */
/*0270*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x001fe200078e00ff */
/*0280*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fca0000000f00 */
/*0290*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101906 */
/*02a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02b0*/ BRA 0x2b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19find_max_int_kernelPKijPi
.globl _Z19find_max_int_kernelPKijPi
.p2align 8
.type _Z19find_max_int_kernelPKijPi,@function
_Z19find_max_int_kernelPKijPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x0
v_sub_nc_u32_e32 v1, 0, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s2, s15, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b32 s6, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s6
ds_store_b32 v1, v2
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_load_b32 s6, s[0:1], 0x8
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cmp_eq_u32 s15, 0
ds_load_b32 v2, v1
s_cselect_b32 s7, -1, 0
v_cmp_gt_u32_e64 s2, s6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s7, s2
s_and_saveexec_b32 s7, s2
s_cbranch_execz .LBB0_6
s_mov_b32 s8, 0
.LBB0_4:
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_add_nc_u32_e32 v0, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s2, s4, v3
v_add_co_ci_u32_e64 v4, s2, s5, v4, s2
s_delay_alu instid0(VALU_DEP_3)
v_cmp_le_u32_e64 s2, s6, v0
global_load_b32 v3, v[3:4], off
s_or_b32 s8, s2, s8
s_waitcnt vmcnt(0) lgkmcnt(0)
v_max_i32_e32 v2, v2, v3
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_4
s_or_b32 exec_lo, exec_lo, s8
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s7
s_mov_b32 s2, exec_lo
s_brev_b32 s3, 1
.LBB0_7:
s_ctz_i32_b32 s4, s2
s_waitcnt lgkmcnt(0)
v_readlane_b32 s5, v2, s4
s_lshl_b32 s4, 1, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_not1_b32 s2, s2, s4
s_max_i32 s3, s3, s5
s_cmp_lg_u32 s2, 0
s_cbranch_scc1 .LBB0_7
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s2, 0, v0
s_and_saveexec_b32 s4, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s4
s_cbranch_execz .LBB0_10
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s3
ds_max_i32 v0, v1
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_12
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x10
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19find_max_int_kernelPKijPi
.amdhsa_group_segment_fixed_size 4
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19find_max_int_kernelPKijPi, .Lfunc_end0-_Z19find_max_int_kernelPKijPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z21find_max_float_kernelPKfjPf
.globl _Z21find_max_float_kernelPKfjPf
.p2align 8
.type _Z21find_max_float_kernelPKfjPf,@function
_Z21find_max_float_kernelPKfjPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x0
v_sub_nc_u32_e32 v1, 0, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s2, s15, s6
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_2
s_load_b32 s3, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s3
ds_store_b32 v1, v2
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s2
v_mov_b32_e32 v1, 0
s_load_b32 s7, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v1
s_cmp_eq_u32 s15, 0
s_cselect_b32 s3, -1, 0
v_cmp_gt_u32_e64 s2, s7, v0
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s3, s2
s_and_saveexec_b32 s8, s2
s_cbranch_execz .LBB1_6
v_mov_b32_e32 v2, v3
s_mov_b32 s9, 0
.p2align 6
.LBB1_4:
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_add_nc_u32_e32 v0, s6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s2, s4, v4
v_add_co_ci_u32_e64 v5, s2, s5, v5, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_cmp_le_u32_e64 s2, s7, v0
global_load_b32 v4, v[4:5], off
s_or_b32 s9, s2, s9
s_waitcnt vmcnt(0)
v_cmp_gt_f32_e64 s3, v2, v4
v_cndmask_b32_e64 v2, v4, v2, s3
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB1_4
s_or_b32 exec_lo, exec_lo, s9
.LBB1_6:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s8
s_mov_b32 s3, exec_lo
v_cmpx_ngt_f32_e32 v3, v2
s_cbranch_execz .LBB1_11
v_mov_b32_e32 v0, 0
s_mov_b32 s4, 0
ds_load_b32 v1, v0
s_branch .LBB1_9
.p2align 6
.LBB1_8:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, exec_lo, s5
s_or_b32 s4, s2, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB1_11
.LBB1_9:
s_or_b32 s5, s5, exec_lo
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_nlt_f32_e32 v2, v1
s_cbranch_execz .LBB1_8
ds_cmpstore_rtn_b32 v3, v0, v2, v1
s_and_not1_b32 s5, s5, exec_lo
s_waitcnt lgkmcnt(0)
v_cmp_eq_u32_e64 s2, v3, v1
v_mov_b32_e32 v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, exec_lo
s_or_b32 s5, s5, s2
s_branch .LBB1_8
.LBB1_11:
s_or_b32 exec_lo, exec_lo, s3
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_13
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x10
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB1_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21find_max_float_kernelPKfjPf
.amdhsa_group_segment_fixed_size 4
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z21find_max_float_kernelPKfjPf, .Lfunc_end1-_Z21find_max_float_kernelPKfjPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .actual_access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19find_max_int_kernelPKijPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19find_max_int_kernelPKijPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .actual_access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21find_max_float_kernelPKfjPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21find_max_float_kernelPKfjPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00037da1_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14atomicFloatMaxPff
.type _Z14atomicFloatMaxPff, @function
_Z14atomicFloatMaxPff:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z14atomicFloatMaxPff, .-_Z14atomicFloatMaxPff
.globl _Z10cpuFindMaxIiET_PS0_j
.type _Z10cpuFindMaxIiET_PS0_j, @function
_Z10cpuFindMaxIiET_PS0_j:
.LFB2060:
.cfi_startproc
endbr64
movl (%rdi), %edx
testl %esi, %esi
je .L5
movq %rdi, %rax
movl %esi, %esi
leaq (%rdi,%rsi,4), %rsi
.L7:
movl (%rax), %ecx
cmpl %ecx, %edx
cmovl %ecx, %edx
addq $4, %rax
cmpq %rsi, %rax
jne .L7
.L5:
movl %edx, %eax
ret
.cfi_endproc
.LFE2060:
.size _Z10cpuFindMaxIiET_PS0_j, .-_Z10cpuFindMaxIiET_PS0_j
.globl _Z10cpuFindMaxIfET_PS0_j
.type _Z10cpuFindMaxIfET_PS0_j, @function
_Z10cpuFindMaxIfET_PS0_j:
.LFB2061:
.cfi_startproc
endbr64
movss (%rdi), %xmm0
testl %esi, %esi
je .L9
movq %rdi, %rax
movl %esi, %esi
leaq (%rdi,%rsi,4), %rdx
.L12:
movss (%rax), %xmm1
maxss %xmm0, %xmm1
movaps %xmm1, %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L12
.L9:
ret
.cfi_endproc
.LFE2061:
.size _Z10cpuFindMaxIfET_PS0_j, .-_Z10cpuFindMaxIfET_PS0_j
.globl _Z43__device_stub__Z19find_max_int_kernelPKijPiPKijPi
.type _Z43__device_stub__Z19find_max_int_kernelPKijPiPKijPi, @function
_Z43__device_stub__Z19find_max_int_kernelPKijPiPKijPi:
.LFB2087:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %esi, 12(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19find_max_int_kernelPKijPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z43__device_stub__Z19find_max_int_kernelPKijPiPKijPi, .-_Z43__device_stub__Z19find_max_int_kernelPKijPiPKijPi
.globl _Z19find_max_int_kernelPKijPi
.type _Z19find_max_int_kernelPKijPi, @function
_Z19find_max_int_kernelPKijPi:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z19find_max_int_kernelPKijPiPKijPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z19find_max_int_kernelPKijPi, .-_Z19find_max_int_kernelPKijPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "find_max_int_kernel fault!\n"
.text
.globl _Z10gpuFindMaxIiET_PS0_j
.type _Z10gpuFindMaxIiET_PS0_j, @function
_Z10gpuFindMaxIiET_PS0_j:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r12
movl %esi, %ebx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl %esi, %ebp
salq $2, %rbp
movq %rsp, %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $64, 16(%rsp)
movl $1, 20(%rsp)
leal 63(%rbx), %eax
shrl $6, %eax
movl %eax, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L29
.L25:
movl $4, %edi
call malloc@PLT
movq %rax, %rbx
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movl (%rbx), %ebp
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl %ebp, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movq 8(%rsp), %rdx
movl %ebx, %esi
movq (%rsp), %rdi
call _Z43__device_stub__Z19find_max_int_kernelPKijPiPKijPi
jmp .L24
.L29:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z10gpuFindMaxIiET_PS0_j, .-_Z10gpuFindMaxIiET_PS0_j
.globl _Z45__device_stub__Z21find_max_float_kernelPKfjPfPKfjPf
.type _Z45__device_stub__Z21find_max_float_kernelPKfjPfPKfjPf, @function
_Z45__device_stub__Z21find_max_float_kernelPKfjPfPKfjPf:
.LFB2089:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %esi, 12(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L35
.L31:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21find_max_float_kernelPKfjPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L31
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z45__device_stub__Z21find_max_float_kernelPKfjPfPKfjPf, .-_Z45__device_stub__Z21find_max_float_kernelPKfjPfPKfjPf
.globl _Z21find_max_float_kernelPKfjPf
.type _Z21find_max_float_kernelPKfjPf, @function
_Z21find_max_float_kernelPKfjPf:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z21find_max_float_kernelPKfjPfPKfjPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z21find_max_float_kernelPKfjPf, .-_Z21find_max_float_kernelPKfjPf
.section .rodata.str1.1
.LC1:
.string "find_max_float_kernel fault!\n"
.text
.globl _Z10gpuFindMaxIfET_PS0_j
.type _Z10gpuFindMaxIfET_PS0_j, @function
_Z10gpuFindMaxIfET_PS0_j:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r12
movl %esi, %ebx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl %esi, %ebp
salq $2, %rbp
movq %rsp, %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $64, 16(%rsp)
movl $1, 20(%rsp)
leal 63(%rbx), %eax
shrl $6, %eax
movl %eax, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L44
.L40:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L45
.L41:
movl $4, %edi
call malloc@PLT
movq %rax, %rbx
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movl (%rbx), %ebp
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L46
movd %ebp, %xmm0
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
movq 8(%rsp), %rdx
movl %ebx, %esi
movq (%rsp), %rdi
call _Z45__device_stub__Z21find_max_float_kernelPKfjPfPKfjPf
jmp .L40
.L45:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L41
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z10gpuFindMaxIfET_PS0_j, .-_Z10gpuFindMaxIfET_PS0_j
.section .rodata.str1.1
.LC3:
.string "CPU find max int element: %d\n"
.LC4:
.string "GPU find max int element: %d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "CPU find max float element: %f\n"
.align 8
.LC6:
.string "GPU find max float element: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2062:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $16, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl $4000, %edi
call malloc@PLT
movq %rax, %r14
movq %rsp, %rdi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %r14, %rbx
leaq 4000(%r14), %rbp
.L48:
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L48
movl $4000, %edi
call malloc@PLT
movq %rax, %r13
movq %rsp, %rdi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %r13, %rbx
leaq 4000(%r13), %r12
movq %r13, %rbp
.L49:
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp)
addq $4, %rbp
cmpq %r12, %rbp
jne .L49
movss .LC2(%rip), %xmm1
.L50:
movss (%rbx), %xmm0
divss %xmm1, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L50
movl $1000, %esi
movq %r14, %rdi
call _Z10cpuFindMaxIiET_PS0_j
movl %eax, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1000, %esi
movq %r14, %rdi
call _Z10gpuFindMaxIiET_PS0_j
movl %eax, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1000, %esi
movq %r13, %rdi
call _Z10cpuFindMaxIfET_PS0_j
cvtss2sd %xmm0, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $1000, %esi
movq %r13, %rdi
call _Z10gpuFindMaxIfET_PS0_j
cvtss2sd %xmm0, %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $128, %edi
call malloc@PLT
movq %rax, %r12
movq %rsp, %rdi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %r12, %rbx
leaq 128(%r12), %rbp
.L51:
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L51
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L58
movl $0, %eax
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC7:
.string "_Z21find_max_float_kernelPKfjPf"
.section .rodata.str1.1
.LC8:
.string "_Z19find_max_int_kernelPKijPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z21find_max_float_kernelPKfjPf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z19find_max_int_kernelPKijPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1092616192
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z34__device_stub__find_max_int_kernelPKijPi # -- Begin function _Z34__device_stub__find_max_int_kernelPKijPi
.p2align 4, 0x90
.type _Z34__device_stub__find_max_int_kernelPKijPi,@function
_Z34__device_stub__find_max_int_kernelPKijPi: # @_Z34__device_stub__find_max_int_kernelPKijPi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19find_max_int_kernelPKijPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z34__device_stub__find_max_int_kernelPKijPi, .Lfunc_end0-_Z34__device_stub__find_max_int_kernelPKijPi
.cfi_endproc
# -- End function
.globl _Z36__device_stub__find_max_float_kernelPKfjPf # -- Begin function _Z36__device_stub__find_max_float_kernelPKfjPf
.p2align 4, 0x90
.type _Z36__device_stub__find_max_float_kernelPKfjPf,@function
_Z36__device_stub__find_max_float_kernelPKfjPf: # @_Z36__device_stub__find_max_float_kernelPKfjPf
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21find_max_float_kernelPKfjPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z36__device_stub__find_max_float_kernelPKfjPf, .Lfunc_end1-_Z36__device_stub__find_max_float_kernelPKfjPf
.cfi_endproc
# -- End function
.globl _Z10gpuFindMaxIiET_PS0_j # -- Begin function _Z10gpuFindMaxIiET_PS0_j
.p2align 4, 0x90
.type _Z10gpuFindMaxIiET_PS0_j,@function
_Z10gpuFindMaxIiET_PS0_j: # @_Z10gpuFindMaxIiET_PS0_j
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebx
movq %rdi, %r14
movl %esi, %r15d
shlq $2, %r15
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leal 63(%rbx), %edi
shrl $6, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $64, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movl %ebx, 28(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 28(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19find_max_int_kernelPKijPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipGetLastError
testl %eax, %eax
je .LBB2_4
# %bb.3:
movl $.Lstr, %edi
callq puts@PLT
.LBB2_4:
movl $4, %edi
callq malloc
movq %rax, %rbx
movq 8(%rsp), %rsi
movl $4, %edx
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
movl (%rbx), %ebp
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movl %ebp, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z10gpuFindMaxIiET_PS0_j, .Lfunc_end2-_Z10gpuFindMaxIiET_PS0_j
.cfi_endproc
# -- End function
.globl _Z10gpuFindMaxIfET_PS0_j # -- Begin function _Z10gpuFindMaxIfET_PS0_j
.p2align 4, 0x90
.type _Z10gpuFindMaxIfET_PS0_j,@function
_Z10gpuFindMaxIfET_PS0_j: # @_Z10gpuFindMaxIfET_PS0_j
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %ebx
movq %rdi, %r14
movl %esi, %r15d
shlq $2, %r15
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leal 63(%rbx), %edi
shrl $6, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $64, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movl %ebx, 28(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 28(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z21find_max_float_kernelPKfjPf, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
callq hipGetLastError
testl %eax, %eax
je .LBB3_4
# %bb.3:
movl $.Lstr.1, %edi
callq puts@PLT
.LBB3_4:
movl $4, %edi
callq malloc
movq %rax, %rbx
movq 8(%rsp), %rsi
movl $4, %edx
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, 24(%rsp) # 4-byte Spill
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movss 24(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z10gpuFindMaxIfET_PS0_j, .Lfunc_end3-_Z10gpuFindMaxIfET_PS0_j
.cfi_endproc
# -- End function
.globl _Z10cpuFindMaxIiET_PS0_j # -- Begin function _Z10cpuFindMaxIiET_PS0_j
.p2align 4, 0x90
.type _Z10cpuFindMaxIiET_PS0_j,@function
_Z10cpuFindMaxIiET_PS0_j: # @_Z10cpuFindMaxIiET_PS0_j
.cfi_startproc
# %bb.0:
movl (%rdi), %eax
testl %esi, %esi
je .LBB4_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rdi,%rdx,4), %esi
cmpl %eax, %esi
cmovgl %esi, %eax
incq %rdx
cmpq %rdx, %rcx
jne .LBB4_2
.LBB4_3: # %._crit_edge
retq
.Lfunc_end4:
.size _Z10cpuFindMaxIiET_PS0_j, .Lfunc_end4-_Z10cpuFindMaxIiET_PS0_j
.cfi_endproc
# -- End function
.globl _Z10cpuFindMaxIfET_PS0_j # -- Begin function _Z10cpuFindMaxIfET_PS0_j
.p2align 4, 0x90
.type _Z10cpuFindMaxIfET_PS0_j,@function
_Z10cpuFindMaxIfET_PS0_j: # @_Z10cpuFindMaxIfET_PS0_j
.cfi_startproc
# %bb.0:
movss (%rdi), %xmm1 # xmm1 = mem[0],zero,zero,zero
testl %esi, %esi
je .LBB5_1
# %bb.3: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB5_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rdi,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
maxss %xmm1, %xmm0
incq %rcx
movaps %xmm0, %xmm1
cmpq %rcx, %rax
jne .LBB5_4
# %bb.2: # %._crit_edge
retq
.LBB5_1:
movaps %xmm1, %xmm0
retq
.Lfunc_end5:
.size _Z10cpuFindMaxIfET_PS0_j, .Lfunc_end5-_Z10cpuFindMaxIfET_PS0_j
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI6_0:
.long 0x41200000 # float 10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4000, %edi # imm = 0xFA0
callq malloc
movq %rax, %rbx
movq %rsp, %rdi
callq time
movl %eax, %edi
callq srand
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB6_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $1000, %r14 # imm = 0x3E8
jne .LBB6_1
# %bb.2:
movl $4000, %edi # imm = 0xFA0
callq malloc
movq %rax, %r14
movq %rsp, %rdi
callq time
movl %eax, %edi
callq srand
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB6_3: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%r15,4)
incq %r15
cmpq $1000, %r15 # imm = 0x3E8
jne .LBB6_3
# %bb.4:
xorl %eax, %eax
movss .LCPI6_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB6_5: # =>This Inner Loop Header: Depth=1
movss (%r14,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
movss %xmm1, (%r14,%rax,4)
incq %rax
cmpq $1000, %rax # imm = 0x3E8
jne .LBB6_5
# %bb.6:
movl (%rbx), %esi
xorl %eax, %eax
.p2align 4, 0x90
.LBB6_7: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl (%rbx,%rax,4), %ecx
cmpl %esi, %ecx
cmovgl %ecx, %esi
incq %rax
cmpq $1000, %rax # imm = 0x3E8
jne .LBB6_7
# %bb.8: # %_Z10cpuFindMaxIiET_PS0_j.exit
xorl %r15d, %r15d
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
movl $1000, %esi # imm = 0x3E8
callq _Z10gpuFindMaxIiET_PS0_j
movl $.L.str.3, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
movss (%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB6_9: # %.lr.ph.i29
# =>This Inner Loop Header: Depth=1
movaps %xmm0, %xmm1
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
maxss %xmm1, %xmm0
incq %r15
cmpq $1000, %r15 # imm = 0x3E8
jne .LBB6_9
# %bb.10: # %_Z10cpuFindMaxIfET_PS0_j.exit
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movq %r14, %rdi
movl $1000, %esi # imm = 0x3E8
callq _Z10gpuFindMaxIfET_PS0_j
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
movq %rsp, %rdi
callq time
movl %eax, %edi
callq srand
movl $32, %ebp
.p2align 4, 0x90
.LBB6_11: # =>This Inner Loop Header: Depth=1
callq rand
decl %ebp
jne .LBB6_11
# %bb.12:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19find_max_int_kernelPKijPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21find_max_float_kernelPKfjPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19find_max_int_kernelPKijPi,@object # @_Z19find_max_int_kernelPKijPi
.section .rodata,"a",@progbits
.globl _Z19find_max_int_kernelPKijPi
.p2align 3, 0x0
_Z19find_max_int_kernelPKijPi:
.quad _Z34__device_stub__find_max_int_kernelPKijPi
.size _Z19find_max_int_kernelPKijPi, 8
.type _Z21find_max_float_kernelPKfjPf,@object # @_Z21find_max_float_kernelPKfjPf
.globl _Z21find_max_float_kernelPKfjPf
.p2align 3, 0x0
_Z21find_max_float_kernelPKfjPf:
.quad _Z36__device_stub__find_max_float_kernelPKfjPf
.size _Z21find_max_float_kernelPKfjPf, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "CPU find max int element: %d\n"
.size .L.str.2, 30
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "GPU find max int element: %d\n"
.size .L.str.3, 30
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "CPU find max float element: %f\n"
.size .L.str.4, 32
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "GPU find max float element: %f\n"
.size .L.str.5, 32
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19find_max_int_kernelPKijPi"
.size .L__unnamed_1, 30
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z21find_max_float_kernelPKfjPf"
.size .L__unnamed_2, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "find_max_int_kernel fault!"
.size .Lstr, 27
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "find_max_float_kernel fault!"
.size .Lstr.1, 29
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__find_max_int_kernelPKijPi
.addrsig_sym _Z36__device_stub__find_max_float_kernelPKfjPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19find_max_int_kernelPKijPi
.addrsig_sym _Z21find_max_float_kernelPKfjPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda.h"
__global__ void kernel_saxpy( int n, float a, float * x, float * y, float * z ) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if ( i < n ) {
z[i] = a * x[i] + y [i];
}
}
void saxpy( int nblocks, int nthreads, int n, float a, float * x, float * y, float * z ) {
kernel_saxpy<<<nblocks, nthreads>>>( n, a, x, y, z );
} | code for sm_80
Function : _Z12kernel_saxpyifPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FFMA R9, R2, c[0x0][0x164], R5 ; /* 0x0000590002097a23 */
/* 0x004fca0000000005 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda.h"
__global__ void kernel_saxpy( int n, float a, float * x, float * y, float * z ) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if ( i < n ) {
z[i] = a * x[i] + y [i];
}
}
void saxpy( int nblocks, int nthreads, int n, float a, float * x, float * y, float * z ) {
kernel_saxpy<<<nblocks, nthreads>>>( n, a, x, y, z );
} | .file "tmpxft_000e71b5_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z12kernel_saxpyifPfS_S_ifPfS_S_
.type _Z38__device_stub__Z12kernel_saxpyifPfS_S_ifPfS_S_, @function
_Z38__device_stub__Z12kernel_saxpyifPfS_S_ifPfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12kernel_saxpyifPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z38__device_stub__Z12kernel_saxpyifPfS_S_ifPfS_S_, .-_Z38__device_stub__Z12kernel_saxpyifPfS_S_ifPfS_S_
.globl _Z12kernel_saxpyifPfS_S_
.type _Z12kernel_saxpyifPfS_S_, @function
_Z12kernel_saxpyifPfS_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z12kernel_saxpyifPfS_S_ifPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z12kernel_saxpyifPfS_S_, .-_Z12kernel_saxpyifPfS_S_
.globl _Z5saxpyiiifPfS_S_
.type _Z5saxpyiiifPfS_S_, @function
_Z5saxpyiiifPfS_S_:
.LFB2027:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movl %edx, %ebx
movss %xmm0, 12(%rsp)
movq %rcx, %rbp
movq %r8, %r12
movq %r9, %r13
movl %esi, 36(%rsp)
movl $1, 40(%rsp)
movl %edi, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movq %r13, %rcx
movq %r12, %rdx
movq %rbp, %rsi
movss 12(%rsp), %xmm0
movl %ebx, %edi
call _Z38__device_stub__Z12kernel_saxpyifPfS_S_ifPfS_S_
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z5saxpyiiifPfS_S_, .-_Z5saxpyiiifPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12kernel_saxpyifPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12kernel_saxpyifPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda.h"
__global__ void kernel_saxpy( int n, float a, float * x, float * y, float * z ) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if ( i < n ) {
z[i] = a * x[i] + y [i];
}
}
void saxpy( int nblocks, int nthreads, int n, float a, float * x, float * y, float * z ) {
kernel_saxpy<<<nblocks, nthreads>>>( n, a, x, y, z );
} | #include "hip/hip_runtime.h"
__global__ void kernel_saxpy( int n, float a, float * x, float * y, float * z ) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if ( i < n ) {
z[i] = a * x[i] + y [i];
}
}
void saxpy( int nblocks, int nthreads, int n, float a, float * x, float * y, float * z ) {
kernel_saxpy<<<nblocks, nthreads>>>( n, a, x, y, z );
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
__global__ void kernel_saxpy( int n, float a, float * x, float * y, float * z ) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if ( i < n ) {
z[i] = a * x[i] + y [i];
}
}
void saxpy( int nblocks, int nthreads, int n, float a, float * x, float * y, float * z ) {
kernel_saxpy<<<nblocks, nthreads>>>( n, a, x, y, z );
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12kernel_saxpyifPfS_S_
.globl _Z12kernel_saxpyifPfS_S_
.p2align 8
.type _Z12kernel_saxpyifPfS_S_,@function
_Z12kernel_saxpyifPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
s_clause 0x1
s_load_b32 s2, s[0:1], 0x4
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, s2, v2
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12kernel_saxpyifPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12kernel_saxpyifPfS_S_, .Lfunc_end0-_Z12kernel_saxpyifPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12kernel_saxpyifPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12kernel_saxpyifPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
__global__ void kernel_saxpy( int n, float a, float * x, float * y, float * z ) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if ( i < n ) {
z[i] = a * x[i] + y [i];
}
}
void saxpy( int nblocks, int nthreads, int n, float a, float * x, float * y, float * z ) {
kernel_saxpy<<<nblocks, nthreads>>>( n, a, x, y, z );
} | .text
.file "kernel.hip"
.globl _Z27__device_stub__kernel_saxpyifPfS_S_ # -- Begin function _Z27__device_stub__kernel_saxpyifPfS_S_
.p2align 4, 0x90
.type _Z27__device_stub__kernel_saxpyifPfS_S_,@function
_Z27__device_stub__kernel_saxpyifPfS_S_: # @_Z27__device_stub__kernel_saxpyifPfS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movss %xmm0, (%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12kernel_saxpyifPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__kernel_saxpyifPfS_S_, .Lfunc_end0-_Z27__device_stub__kernel_saxpyifPfS_S_
.cfi_endproc
# -- End function
.globl _Z5saxpyiiifPfS_S_ # -- Begin function _Z5saxpyiiifPfS_S_
.p2align 4, 0x90
.type _Z5saxpyiiifPfS_S_,@function
_Z5saxpyiiifPfS_S_: # @_Z5saxpyiiifPfS_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $136, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, %r14
movq %rcx, %r15
movss %xmm0, 12(%rsp) # 4-byte Spill
movl %edx, %ebp
movl %edi, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %esi, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movl %ebp, 20(%rsp)
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 16(%rsp)
movq %r15, 88(%rsp)
movq %r14, 80(%rsp)
movq %rbx, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12kernel_saxpyifPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $136, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z5saxpyiiifPfS_S_, .Lfunc_end1-_Z5saxpyiiifPfS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12kernel_saxpyifPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12kernel_saxpyifPfS_S_,@object # @_Z12kernel_saxpyifPfS_S_
.section .rodata,"a",@progbits
.globl _Z12kernel_saxpyifPfS_S_
.p2align 3, 0x0
_Z12kernel_saxpyifPfS_S_:
.quad _Z27__device_stub__kernel_saxpyifPfS_S_
.size _Z12kernel_saxpyifPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12kernel_saxpyifPfS_S_"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__kernel_saxpyifPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12kernel_saxpyifPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12kernel_saxpyifPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FFMA R9, R2, c[0x0][0x164], R5 ; /* 0x0000590002097a23 */
/* 0x004fca0000000005 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12kernel_saxpyifPfS_S_
.globl _Z12kernel_saxpyifPfS_S_
.p2align 8
.type _Z12kernel_saxpyifPfS_S_,@function
_Z12kernel_saxpyifPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
s_clause 0x1
s_load_b32 s2, s[0:1], 0x4
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, s2, v2
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12kernel_saxpyifPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12kernel_saxpyifPfS_S_, .Lfunc_end0-_Z12kernel_saxpyifPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12kernel_saxpyifPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12kernel_saxpyifPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e71b5_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z12kernel_saxpyifPfS_S_ifPfS_S_
.type _Z38__device_stub__Z12kernel_saxpyifPfS_S_ifPfS_S_, @function
_Z38__device_stub__Z12kernel_saxpyifPfS_S_ifPfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12kernel_saxpyifPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z38__device_stub__Z12kernel_saxpyifPfS_S_ifPfS_S_, .-_Z38__device_stub__Z12kernel_saxpyifPfS_S_ifPfS_S_
.globl _Z12kernel_saxpyifPfS_S_
.type _Z12kernel_saxpyifPfS_S_, @function
_Z12kernel_saxpyifPfS_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z12kernel_saxpyifPfS_S_ifPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z12kernel_saxpyifPfS_S_, .-_Z12kernel_saxpyifPfS_S_
.globl _Z5saxpyiiifPfS_S_
.type _Z5saxpyiiifPfS_S_, @function
_Z5saxpyiiifPfS_S_:
.LFB2027:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movl %edx, %ebx
movss %xmm0, 12(%rsp)
movq %rcx, %rbp
movq %r8, %r12
movq %r9, %r13
movl %esi, 36(%rsp)
movl $1, 40(%rsp)
movl %edi, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movq %r13, %rcx
movq %r12, %rdx
movq %rbp, %rsi
movss 12(%rsp), %xmm0
movl %ebx, %edi
call _Z38__device_stub__Z12kernel_saxpyifPfS_S_ifPfS_S_
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z5saxpyiiifPfS_S_, .-_Z5saxpyiiifPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12kernel_saxpyifPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12kernel_saxpyifPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z27__device_stub__kernel_saxpyifPfS_S_ # -- Begin function _Z27__device_stub__kernel_saxpyifPfS_S_
.p2align 4, 0x90
.type _Z27__device_stub__kernel_saxpyifPfS_S_,@function
_Z27__device_stub__kernel_saxpyifPfS_S_: # @_Z27__device_stub__kernel_saxpyifPfS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movss %xmm0, (%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12kernel_saxpyifPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__kernel_saxpyifPfS_S_, .Lfunc_end0-_Z27__device_stub__kernel_saxpyifPfS_S_
.cfi_endproc
# -- End function
.globl _Z5saxpyiiifPfS_S_ # -- Begin function _Z5saxpyiiifPfS_S_
.p2align 4, 0x90
.type _Z5saxpyiiifPfS_S_,@function
_Z5saxpyiiifPfS_S_: # @_Z5saxpyiiifPfS_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $136, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, %r14
movq %rcx, %r15
movss %xmm0, 12(%rsp) # 4-byte Spill
movl %edx, %ebp
movl %edi, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %esi, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movl %ebp, 20(%rsp)
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 16(%rsp)
movq %r15, 88(%rsp)
movq %r14, 80(%rsp)
movq %rbx, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12kernel_saxpyifPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $136, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z5saxpyiiifPfS_S_, .Lfunc_end1-_Z5saxpyiiifPfS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12kernel_saxpyifPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12kernel_saxpyifPfS_S_,@object # @_Z12kernel_saxpyifPfS_S_
.section .rodata,"a",@progbits
.globl _Z12kernel_saxpyifPfS_S_
.p2align 3, 0x0
_Z12kernel_saxpyifPfS_S_:
.quad _Z27__device_stub__kernel_saxpyifPfS_S_
.size _Z12kernel_saxpyifPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12kernel_saxpyifPfS_S_"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__kernel_saxpyifPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12kernel_saxpyifPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void gpuMatMul(float * A, float * B, float *C,
int ROW_A, int COL_A, int COL_B);
void mat_mul_cuda_multi(float *A, float *B, float *C,
int ROW_A, int COL_A, int COL_B) {
/******************** TODO *********************/
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void gpuMatMul(float * A, float * B, float *C,
int ROW_A, int COL_A, int COL_B);
void mat_mul_cuda_multi(float *A, float *B, float *C,
int ROW_A, int COL_A, int COL_B) {
/******************** TODO *********************/
} | .file "tmpxft_0018118e_00000000-6_mat_mul_cuda_multi.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z18mat_mul_cuda_multiPfS_S_iii
.type _Z18mat_mul_cuda_multiPfS_S_iii, @function
_Z18mat_mul_cuda_multiPfS_S_iii:
.LFB2057:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE2057:
.size _Z18mat_mul_cuda_multiPfS_S_iii, .-_Z18mat_mul_cuda_multiPfS_S_iii
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void gpuMatMul(float * A, float * B, float *C,
int ROW_A, int COL_A, int COL_B);
void mat_mul_cuda_multi(float *A, float *B, float *C,
int ROW_A, int COL_A, int COL_B) {
/******************** TODO *********************/
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void gpuMatMul(float * A, float * B, float *C,
int ROW_A, int COL_A, int COL_B);
void mat_mul_cuda_multi(float *A, float *B, float *C,
int ROW_A, int COL_A, int COL_B) {
/******************** TODO *********************/
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void gpuMatMul(float * A, float * B, float *C,
int ROW_A, int COL_A, int COL_B);
void mat_mul_cuda_multi(float *A, float *B, float *C,
int ROW_A, int COL_A, int COL_B) {
/******************** TODO *********************/
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void gpuMatMul(float * A, float * B, float *C,
int ROW_A, int COL_A, int COL_B);
void mat_mul_cuda_multi(float *A, float *B, float *C,
int ROW_A, int COL_A, int COL_B) {
/******************** TODO *********************/
} | .text
.file "mat_mul_cuda_multi.hip"
.globl _Z18mat_mul_cuda_multiPfS_S_iii # -- Begin function _Z18mat_mul_cuda_multiPfS_S_iii
.p2align 4, 0x90
.type _Z18mat_mul_cuda_multiPfS_S_iii,@function
_Z18mat_mul_cuda_multiPfS_S_iii: # @_Z18mat_mul_cuda_multiPfS_S_iii
.cfi_startproc
# %bb.0:
retq
.Lfunc_end0:
.size _Z18mat_mul_cuda_multiPfS_S_iii, .Lfunc_end0-_Z18mat_mul_cuda_multiPfS_S_iii
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018118e_00000000-6_mat_mul_cuda_multi.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z18mat_mul_cuda_multiPfS_S_iii
.type _Z18mat_mul_cuda_multiPfS_S_iii, @function
_Z18mat_mul_cuda_multiPfS_S_iii:
.LFB2057:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE2057:
.size _Z18mat_mul_cuda_multiPfS_S_iii, .-_Z18mat_mul_cuda_multiPfS_S_iii
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mat_mul_cuda_multi.hip"
.globl _Z18mat_mul_cuda_multiPfS_S_iii # -- Begin function _Z18mat_mul_cuda_multiPfS_S_iii
.p2align 4, 0x90
.type _Z18mat_mul_cuda_multiPfS_S_iii,@function
_Z18mat_mul_cuda_multiPfS_S_iii: # @_Z18mat_mul_cuda_multiPfS_S_iii
.cfi_startproc
# %bb.0:
retq
.Lfunc_end0:
.size _Z18mat_mul_cuda_multiPfS_S_iii, .Lfunc_end0-_Z18mat_mul_cuda_multiPfS_S_iii
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
Sample Implementation of
Yamazaki and Tanaka (2005).
Neural Modeling of an Internal Clock.
Neural Computation 17:1032--1058.
using only global memory of CUDA.
Licensed under Creative Commons Attribution License (CC-BY)
http://creativecommons.org/licenses/by/3.0/
*/
#include<stdio.h>
#include<stdlib.h>
#include<math.h>
#define N 1024 // To be 2^k
#define T 1000
#define Pr 0.5
#define I 1.0
#define Kappa 2.0
#define Tau 100.0
#define BLOCK_SIZE 512
float *z, *u, *result;
//int *w;
int *w11, *w12, *w21, *w22;
void initialize()
{
int i, j, k;
//w = (int *)malloc(N*N*sizeof(int));
w11 = (int *)malloc((N/2)*(N/2)*sizeof(int));
w12 = (int *)malloc((N/2)*(N/2)*sizeof(int));
w21 = (int *)malloc((N/2)*(N/2)*sizeof(int));
w22 = (int *)malloc((N/2)*(N/2)*sizeof(int));
z = (float *)malloc(N*sizeof(float));
u = (float *)malloc(N*sizeof(float));
result = (float *)malloc(T*N*sizeof(float));
for(i = 0; i < N; i++){
z[i] = 0;
u[i] = I;
}
srand(23);
/*
for(i = 0; i < N; i++){
k = 0;
for(j = 0; j < N; j++){
if ((float)rand()/(float)RAND_MAX < Pr){
w[k+N*i] = j;
k++;
}
}
w[k+N*i] = -1;
}
*/
for(i = 0; i < N/2; i++){
k = 0;
for(j = 0; j < N/2; j++){
if ((float)rand()/(float)RAND_MAX < Pr){
w11[k+(N/2)*i] = j;
k++;
}
}
w11[k+(N/2)*i] = -1;
w11[(N/2)-1+(N/2)*i] = -1;
}
for(i = 0; i < N/2; i++){
k = 0;
for(j = N/2; j < N; j++){
if ((float)rand()/(float)RAND_MAX < Pr){
w12[k+(N/2)*i] = j-N/2;
k++;
}
}
w12[k+(N/2)*i] = -1;
w12[(N/2)-1+(N/2)*i] = -1;
}
for(i = N/2; i < N; i++){
k = 0;
for(j = 0; j < N/2; j++){
if ((float)rand()/(float)RAND_MAX < Pr){
w21[k+(N/2)*(i-N/2)] = j;
k++;
}
}
w21[k+(N/2)*(i-N/2)] = -1;
w21[(N/2)-1+(N/2)*(i-N/2)] = -1;
}
for(i = N/2; i < N; i++){
k = 0;
for(j = N/2; j < N; j++){
if ((float)rand()/(float)RAND_MAX < Pr){
w22[k+(N/2)*(i-N/2)] = j-N/2;
k++;
}
}
w22[k+(N/2)*(i-N/2)] = -1;
w22[(N/2)-1+(N/2)*(i-N/2)] = -1;
}
}
void finalize()
{
//free(w);
free(w11);
free(w12);
free(w21);
free(w22);
free(z);
free(u);
free(result);
}
__global__ void Kernel(const int *w11, const int *w12, const int *w21, const int *w22, float *z, float *u, float *result, const float decay, const int t)
{
int i, j, k;
float r;
__shared__ float zsh[N/2];
i = threadIdx.x;
if (blockIdx.x == 0){ // i = 0...N/2
// w11
zsh[i] = z[i];
__syncthreads();
r = 0;
for(k = 0; w11[k+(N/2)*i] != -1; k++){
j = w11[k+(N/2)*i];
r += zsh[j];
}
u[i] = decay*u[i] + (1 - decay)*I - Kappa*r/N;
__syncthreads();
// w12
zsh[i] = z[i+N/2];
__syncthreads();
r = 0;
for(k = 0; w12[k+(N/2)*i] != -1; k++){
j = w12[k+(N/2)*i];
r += zsh[j];
}
u[i] += - Kappa*r/N;
__syncthreads();
if (u[i] > 0){
z[i] = u[i];
}else{
z[i] = 0;
}
result[i+N*t] = z[i];
}else{ // i = N/2...N
// w21
zsh[i] = z[i];
__syncthreads();
r = 0;
for(k = 0; w21[k+(N/2)*i] != -1; k++){
j = w21[k+(N/2)*i];
r += zsh[j];
}
u[i+N/2] = decay*u[i+N/2] + (1 - decay)*I - Kappa*r/N;
__syncthreads();
// w22
zsh[i] = z[i+N/2];
__syncthreads();
r = 0;
for(k = 0; w22[k+(N/2)*i] != -1; k++){
j = w22[k+(N/2)*i];
r += zsh[j];
}
u[i+N/2] += - Kappa*r/N;
__syncthreads();
if (u[i+N/2] > 0){
z[i+N/2] = u[i+N/2];
}else{
z[i+N/2] = 0;
}
result[(i+N/2)+N*t] = z[i+N/2];
}
}
void loop()
{
float *zd, *ud, *resultd;
//int *wd;
int *w11d, *w12d, *w21d, *w22d;
float decay;
cudaError_t stat;
int t;
decay = exp(-1.0/Tau);
//cudaMalloc((void**)&wd, N*N*sizeof(int));
cudaMalloc((void**)&w11d, (N/2)*(N/2)*sizeof(int));
cudaMalloc((void**)&w12d, (N/2)*(N/2)*sizeof(int));
cudaMalloc((void**)&w21d, (N/2)*(N/2)*sizeof(int));
cudaMalloc((void**)&w22d, (N/2)*(N/2)*sizeof(int));
cudaMalloc((void**)&zd, N*sizeof(float));
cudaMalloc((void**)&ud, N*sizeof(float));
cudaMalloc((void**)&resultd, N*T*sizeof(float));
//cudaMemcpy(wd, w, N*N*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(w11d, w11, (N/2)*(N/2)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(w12d, w12, (N/2)*(N/2)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(w21d, w21, (N/2)*(N/2)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(w22d, w22, (N/2)*(N/2)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(zd, z, N*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(ud, u, N*sizeof(float), cudaMemcpyHostToDevice);
dim3 dimBlock(BLOCK_SIZE);
dim3 dimGrid(N/BLOCK_SIZE);
for(t = 0; t < T; t++){
//Kernel<<<dimGrid,dimBlock>>>(wd, zd, ud, resultd, decay, t);
Kernel<<<dimGrid,dimBlock>>>(w11d, w12d, w21d, w22d, zd, ud, resultd, decay, t);
}
stat = cudaMemcpy(result, resultd, N*T*sizeof(float), cudaMemcpyDeviceToHost);
if (stat != cudaSuccess){
puts("error");
}
//cudaFree(wd);
cudaFree(w11d);
cudaFree(w12d);
cudaFree(w21d);
cudaFree(w22d);
cudaFree(zd);
cudaFree(ud);
cudaFree(resultd);
}
void output(char *prefix)
{
FILE *f;
int t, i;
char fn[1024];
sprintf(fn, "%s.r", prefix);
f = fopen(fn, "w");
for(t = 0; t < T; t++){
for(i = 0; i < N; i++){
if (result[i+N*t] > 0){
fprintf(f, "%d %d\n", t, i);
}
}
}
fclose(f);
}
int main(int argc, char *argv[])
{
char *prefix;
if (argc < 2){
fprintf(stderr, "%s <prefix>\n", argv[0]);
exit(1);
}
prefix = argv[1];
initialize();
loop();
output(prefix);
finalize();
return 0;
} | code for sm_80
Function : _Z6KernelPKiS0_S0_S0_PfS1_S1_fi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE R2, R0, R11, c[0x0][0x180] ; /* 0x0000600000027625 */
/* 0x001fca00078e020b */
/*0050*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea2000c1e1900 */
/*0060*/ S2UR UR6, SR_CTAID.X ; /* 0x00000000000679c3 */
/* 0x000e220000002500 */
/*0070*/ MOV R5, c[0x0][0x19c] ; /* 0x0000670000057a02 */
/* 0x000fca0000000f00 */
/*0080*/ IMAD R6, R5, 0x400, R0 ; /* 0x0000040005067824 */
/* 0x000fe400078e0200 */
/*0090*/ IMAD.WIDE R4, R0, R11, c[0x0][0x188] ; /* 0x0000620000047625 */
/* 0x000fc800078e020b */
/*00a0*/ IMAD.WIDE R6, R6, R11, c[0x0][0x190] ; /* 0x0000640006067625 */
/* 0x000fe200078e020b */
/*00b0*/ ISETP.NE.AND P0, PT, RZ, UR6, PT ; /* 0x00000006ff007c0c */
/* 0x001fe2000bf05270 */
/*00c0*/ STS [R0.X4], R9 ; /* 0x0000000900007388 */
/* 0x0041d80000004800 */
/*00d0*/ @!P0 BRA 0x560 ; /* 0x0000048000008947 */
/* 0x000fea0003800000 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*00f0*/ IMAD.SHL.U32 R8, R0, 0x200, RZ ; /* 0x0000020000087824 */
/* 0x000fc800078e00ff */
/*0100*/ IMAD.WIDE R10, R8, R11, c[0x0][0x170] ; /* 0x00005c00080a7625 */
/* 0x000fca00078e020b */
/*0110*/ LDG.E R14, [R10.64] ; /* 0x000000040a0e7981 */
/* 0x000ea2000c1e1900 */
/*0120*/ BSSY B0, 0x260 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*0130*/ CS2R R12, SRZ ; /* 0x00000000000c7805 */
/* 0x000fe2000001ff00 */
/*0140*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff097819 */
/* 0x001fe40000011408 */
/*0150*/ ISETP.NE.AND P0, PT, R14, -0x1, PT ; /* 0xffffffff0e00780c */
/* 0x004fda0003f05270 */
/*0160*/ @!P0 BRA 0x250 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0170*/ HFMA2.MMA R15, -RZ, RZ, 0, 0 ; /* 0x00000000ff0f7435 */
/* 0x000fe200000001ff */
/*0180*/ BSSY B1, 0x220 ; /* 0x0000009000017945 */
/* 0x000fe20003800000 */
/*0190*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fd000078e00ff */
/*01a0*/ IMAD.WIDE R12, R15.reuse, 0x4, R10 ; /* 0x000000040f0c7825 */
/* 0x040fe200078e020a */
/*01b0*/ LDS R17, [R14.X4] ; /* 0x000000000e117984 */
/* 0x0000680000004800 */
/*01c0*/ LDG.E R14, [R12.64+0x4] ; /* 0x000004040c0e7981 */
/* 0x001ea2000c1e1900 */
/*01d0*/ IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0f7810 */
/* 0x000fe20007ffe0ff */
/*01e0*/ FADD R16, R17, R16 ; /* 0x0000001011107221 */
/* 0x002fe20000000000 */
/*01f0*/ ISETP.NE.AND P0, PT, R14, -0x1, PT ; /* 0xffffffff0e00780c */
/* 0x004fda0003f05270 */
/*0200*/ @P0 BRA 0x1a0 ; /* 0xffffff9000000947 */
/* 0x000fea000383ffff */
/*0210*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0220*/ F2F.F64.F32 R10, R16 ; /* 0x00000010000a7310 */
/* 0x000e240000201800 */
/*0230*/ DADD R10, R10, R10 ; /* 0x000000000a0a7229 */
/* 0x001e0c000000000a */
/*0240*/ DMUL R12, R10, 0.0009765625 ; /* 0x3f5000000a0c7828 */
/* 0x00104c0000000000 */
/*0250*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0260*/ LDG.E R10, [R4.64+0x800] ; /* 0x00080004040a7981 */
/* 0x001ea2000c1e1900 */
/*0270*/ MOV R14, c[0x0][0x198] ; /* 0x00006600000e7a02 */
/* 0x000fca0000000f00 */
/*0280*/ FADD R14, -R14, 1 ; /* 0x3f8000000e0e7421 */
/* 0x000fcc0000000100 */
/*0290*/ F2F.F64.F32 R14, R14 ; /* 0x0000000e000e7310 */
/* 0x000fe20000201800 */
/*02a0*/ FMUL R16, R10, c[0x0][0x198] ; /* 0x000066000a107a20 */
/* 0x004fce0000400000 */
/*02b0*/ F2F.F64.F32 R10, R16 ; /* 0x00000010000a7310 */
/* 0x000e240000201800 */
/*02c0*/ DADD R10, R10, R14 ; /* 0x000000000a0a7229 */
/* 0x001e0c000000000e */
/*02d0*/ DADD R12, R10, -R12 ; /* 0x000000000a0c7229 */
/* 0x003e14000000080c */
/*02e0*/ F2F.F32.F64 R13, R12 ; /* 0x0000000c000d7310 */
/* 0x001e240000301000 */
/*02f0*/ STG.E [R4.64+0x800], R13 ; /* 0x0008000d04007986 */
/* 0x0011e8000c101904 */
/*0300*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0310*/ LDG.E R15, [R2.64+0x800] ; /* 0x00080004020f7981 */
/* 0x000ea2000c1e1900 */
/*0320*/ LEA R10, P0, R8, c[0x0][0x178], 0x2 ; /* 0x00005e00080a7a11 */
/* 0x000fc800078010ff */
/*0330*/ LEA.HI.X R11, R8, c[0x0][0x17c], R9, 0x2, P0 ; /* 0x00005f00080b7a11 */
/* 0x000fe200000f1409 */
/*0340*/ STS [R0.X4], R15 ; /* 0x0000000f00007388 */
/* 0x0041e80000004800 */
/*0350*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0360*/ LDG.E R14, [R10.64] ; /* 0x000000040a0e7981 */
/* 0x000ea2000c1e1900 */
/*0370*/ BSSY B0, 0x4b0 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*0380*/ IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; /* 0x00000000ff087424 */
/* 0x000fe200078e00ff */
/*0390*/ MOV R9, 0x80000000 ; /* 0x8000000000097802 */
/* 0x000fc40000000f00 */
/*03a0*/ ISETP.NE.AND P0, PT, R14, -0x1, PT ; /* 0xffffffff0e00780c */
/* 0x004fda0003f05270 */
/*03b0*/ @!P0 BRA 0x4a0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*03c0*/ BSSY B1, 0x470 ; /* 0x000000a000017945 */
/* 0x001fe20003800000 */
/*03d0*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e00ff */
/*03e0*/ MOV R0, RZ ; /* 0x000000ff00007202 */
/* 0x000fc60000000f00 */
/*03f0*/ IMAD.WIDE R8, R13.reuse, 0x4, R10 ; /* 0x000000040d087825 */
/* 0x040fe200078e020a */
/*0400*/ LDS R15, [R14.X4] ; /* 0x000000000e0f7984 */
/* 0x0000680000004800 */
/*0410*/ LDG.E R14, [R8.64+0x4] ; /* 0x00000404080e7981 */
/* 0x001ea2000c1e1900 */
/*0420*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x000fe20007ffe0ff */
/*0430*/ FADD R0, R15, R0 ; /* 0x000000000f007221 */
/* 0x002fe20000000000 */
/*0440*/ ISETP.NE.AND P0, PT, R14, -0x1, PT ; /* 0xffffffff0e00780c */
/* 0x004fda0003f05270 */
/*0450*/ @P0 BRA 0x3f0 ; /* 0xffffff9000000947 */
/* 0x000fea000383ffff */
/*0460*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0470*/ F2F.F64.F32 R8, R0 ; /* 0x0000000000087310 */
/* 0x000e240000201800 */
/*0480*/ DMUL R8, R8, -2 ; /* 0xc000000008087828 */
/* 0x001e0c0000000000 */
/*0490*/ DMUL R8, R8, 0.0009765625 ; /* 0x3f50000008087828 */
/* 0x001e0c0000000000 */
/*04a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*04b0*/ LDG.E R10, [R4.64+0x800] ; /* 0x00080004040a7981 */
/* 0x000ea4000c1e1900 */
/*04c0*/ F2F.F64.F32 R10, R10 ; /* 0x0000000a000a7310 */
/* 0x004e240000201800 */
/*04d0*/ DADD R8, R10, R8 ; /* 0x000000000a087229 */
/* 0x001e140000000008 */
/*04e0*/ F2F.F32.F64 R9, R8 ; /* 0x0000000800097310 */
/* 0x001e240000301000 */
/*04f0*/ STG.E [R4.64+0x800], R9 ; /* 0x0008000904007986 */
/* 0x001fe8000c101904 */
/*0500*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0510*/ LDG.E R0, [R4.64+0x800] ; /* 0x0008000404007981 */
/* 0x000ea4000c1e1900 */
/*0520*/ FMNMX R11, RZ, R0, !PT ; /* 0x00000000ff0b7209 */
/* 0x004fca0007800000 */
/*0530*/ STG.E [R2.64+0x800], R11 ; /* 0x0008000b02007986 */
/* 0x000fe8000c101904 */
/*0540*/ STG.E [R6.64+0x800], R11 ; /* 0x0008000b06007986 */
/* 0x000fe2000c101904 */
/*0550*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0560*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0570*/ IMAD.SHL.U32 R8, R0, 0x200, RZ ; /* 0x0000020000087824 */
/* 0x000fc800078e00ff */
/*0580*/ IMAD.WIDE R10, R8, R11, c[0x0][0x160] ; /* 0x00005800080a7625 */
/* 0x000fca00078e020b */
/*0590*/ LDG.E R14, [R10.64] ; /* 0x000000040a0e7981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ BSSY B0, 0x6e0 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*05b0*/ CS2R R12, SRZ ; /* 0x00000000000c7805 */
/* 0x000fe2000001ff00 */
/*05c0*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff097819 */
/* 0x001fe40000011408 */
/*05d0*/ ISETP.NE.AND P0, PT, R14, -0x1, PT ; /* 0xffffffff0e00780c */
/* 0x004fda0003f05270 */
/*05e0*/ @!P0 BRA 0x6d0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*05f0*/ BSSY B1, 0x6a0 ; /* 0x000000a000017945 */
/* 0x000fe20003800000 */
/*0600*/ MOV R15, RZ ; /* 0x000000ff000f7202 */
/* 0x000fe20000000f00 */
/*0610*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fc800078e00ff */
/*0620*/ IMAD.WIDE R12, R15.reuse, 0x4, R10 ; /* 0x000000040f0c7825 */
/* 0x040fe200078e020a */
/*0630*/ LDS R17, [R14.X4] ; /* 0x000000000e117984 */
/* 0x0000680000004800 */
/*0640*/ LDG.E R14, [R12.64+0x4] ; /* 0x000004040c0e7981 */
/* 0x001ea2000c1e1900 */
/*0650*/ IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0f7810 */
/* 0x000fe20007ffe0ff */
/*0660*/ FADD R16, R17, R16 ; /* 0x0000001011107221 */
/* 0x002fe20000000000 */
/*0670*/ ISETP.NE.AND P0, PT, R14, -0x1, PT ; /* 0xffffffff0e00780c */
/* 0x004fda0003f05270 */
/*0680*/ @P0 BRA 0x620 ; /* 0xffffff9000000947 */
/* 0x000fea000383ffff */
/*0690*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*06a0*/ F2F.F64.F32 R10, R16 ; /* 0x00000010000a7310 */
/* 0x000e240000201800 */
/*06b0*/ DADD R10, R10, R10 ; /* 0x000000000a0a7229 */
/* 0x001e0c000000000a */
/*06c0*/ DMUL R12, R10, 0.0009765625 ; /* 0x3f5000000a0c7828 */
/* 0x00104c0000000000 */
/*06d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06e0*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x001ea2000c1e1900 */
/*06f0*/ MOV R11, c[0x0][0x198] ; /* 0x00006600000b7a02 */
/* 0x000fca0000000f00 */
/*0700*/ FADD R14, -R11, 1 ; /* 0x3f8000000b0e7421 */
/* 0x000fcc0000000100 */
/*0710*/ F2F.F64.F32 R14, R14 ; /* 0x0000000e000e7310 */
/* 0x000fe20000201800 */
/*0720*/ FMUL R16, R10, c[0x0][0x198] ; /* 0x000066000a107a20 */
/* 0x004fce0000400000 */
/*0730*/ F2F.F64.F32 R10, R16 ; /* 0x00000010000a7310 */
/* 0x000e240000201800 */
/*0740*/ DADD R10, R14, R10 ; /* 0x000000000e0a7229 */
/* 0x001e0c000000000a */
/*0750*/ DADD R12, R10, -R12 ; /* 0x000000000a0c7229 */
/* 0x003e14000000080c */
/*0760*/ F2F.F32.F64 R13, R12 ; /* 0x0000000c000d7310 */
/* 0x001e240000301000 */
/*0770*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x0011e8000c101904 */
/*0780*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0790*/ LDG.E R15, [R2.64+0x800] ; /* 0x00080004020f7981 */
/* 0x000ea2000c1e1900 */
/*07a0*/ LEA R10, P0, R8, c[0x0][0x168], 0x2 ; /* 0x00005a00080a7a11 */
/* 0x000fc800078010ff */
/*07b0*/ LEA.HI.X R11, R8, c[0x0][0x16c], R9, 0x2, P0 ; /* 0x00005b00080b7a11 */
/* 0x000fe200000f1409 */
/*07c0*/ STS [R0.X4], R15 ; /* 0x0000000f00007388 */
/* 0x0041e80000004800 */
/*07d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*07e0*/ LDG.E R14, [R10.64] ; /* 0x000000040a0e7981 */
/* 0x000ea2000c1e1900 */
/*07f0*/ BSSY B0, 0x930 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*0800*/ IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; /* 0x00000000ff087424 */
/* 0x000fe200078e00ff */
/*0810*/ MOV R9, 0x80000000 ; /* 0x8000000000097802 */
/* 0x000fc40000000f00 */
/*0820*/ ISETP.NE.AND P0, PT, R14, -0x1, PT ; /* 0xffffffff0e00780c */
/* 0x004fda0003f05270 */
/*0830*/ @!P0 BRA 0x920 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0840*/ BSSY B1, 0x8f0 ; /* 0x000000a000017945 */
/* 0x001fe20003800000 */
/*0850*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e00ff */
/*0860*/ MOV R0, RZ ; /* 0x000000ff00007202 */
/* 0x000fc60000000f00 */
/*0870*/ IMAD.WIDE R8, R13.reuse, 0x4, R10 ; /* 0x000000040d087825 */
/* 0x040fe200078e020a */
/*0880*/ LDS R15, [R14.X4] ; /* 0x000000000e0f7984 */
/* 0x0000680000004800 */
/*0890*/ LDG.E R14, [R8.64+0x4] ; /* 0x00000404080e7981 */
/* 0x001ea2000c1e1900 */
/*08a0*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x000fe20007ffe0ff */
/*08b0*/ FADD R0, R15, R0 ; /* 0x000000000f007221 */
/* 0x002fe20000000000 */
/*08c0*/ ISETP.NE.AND P0, PT, R14, -0x1, PT ; /* 0xffffffff0e00780c */
/* 0x004fda0003f05270 */
/*08d0*/ @P0 BRA 0x870 ; /* 0xffffff9000000947 */
/* 0x000fea000383ffff */
/*08e0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*08f0*/ F2F.F64.F32 R8, R0 ; /* 0x0000000000087310 */
/* 0x000e240000201800 */
/*0900*/ DMUL R8, R8, -2 ; /* 0xc000000008087828 */
/* 0x001e0c0000000000 */
/*0910*/ DMUL R8, R8, 0.0009765625 ; /* 0x3f50000008087828 */
/* 0x001e0c0000000000 */
/*0920*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0930*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea4000c1e1900 */
/*0940*/ F2F.F64.F32 R10, R10 ; /* 0x0000000a000a7310 */
/* 0x004e240000201800 */
/*0950*/ DADD R8, R10, R8 ; /* 0x000000000a087229 */
/* 0x001e140000000008 */
/*0960*/ F2F.F32.F64 R9, R8 ; /* 0x0000000800097310 */
/* 0x001e240000301000 */
/*0970*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x001fe8000c101904 */
/*0980*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0990*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*09a0*/ FMNMX R11, RZ, R0, !PT ; /* 0x00000000ff0b7209 */
/* 0x004fca0007800000 */
/*09b0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe8000c101904 */
/*09c0*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x000fe2000c101904 */
/*09d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09e0*/ BRA 0x9e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
Sample Implementation of
Yamazaki and Tanaka (2005).
Neural Modeling of an Internal Clock.
Neural Computation 17:1032--1058.
using only global memory of CUDA.
Licensed under Creative Commons Attribution License (CC-BY)
http://creativecommons.org/licenses/by/3.0/
*/
#include<stdio.h>
#include<stdlib.h>
#include<math.h>
#define N 1024 // To be 2^k
#define T 1000
#define Pr 0.5
#define I 1.0
#define Kappa 2.0
#define Tau 100.0
#define BLOCK_SIZE 512
float *z, *u, *result;
//int *w;
int *w11, *w12, *w21, *w22;
void initialize()
{
int i, j, k;
//w = (int *)malloc(N*N*sizeof(int));
w11 = (int *)malloc((N/2)*(N/2)*sizeof(int));
w12 = (int *)malloc((N/2)*(N/2)*sizeof(int));
w21 = (int *)malloc((N/2)*(N/2)*sizeof(int));
w22 = (int *)malloc((N/2)*(N/2)*sizeof(int));
z = (float *)malloc(N*sizeof(float));
u = (float *)malloc(N*sizeof(float));
result = (float *)malloc(T*N*sizeof(float));
for(i = 0; i < N; i++){
z[i] = 0;
u[i] = I;
}
srand(23);
/*
for(i = 0; i < N; i++){
k = 0;
for(j = 0; j < N; j++){
if ((float)rand()/(float)RAND_MAX < Pr){
w[k+N*i] = j;
k++;
}
}
w[k+N*i] = -1;
}
*/
for(i = 0; i < N/2; i++){
k = 0;
for(j = 0; j < N/2; j++){
if ((float)rand()/(float)RAND_MAX < Pr){
w11[k+(N/2)*i] = j;
k++;
}
}
w11[k+(N/2)*i] = -1;
w11[(N/2)-1+(N/2)*i] = -1;
}
for(i = 0; i < N/2; i++){
k = 0;
for(j = N/2; j < N; j++){
if ((float)rand()/(float)RAND_MAX < Pr){
w12[k+(N/2)*i] = j-N/2;
k++;
}
}
w12[k+(N/2)*i] = -1;
w12[(N/2)-1+(N/2)*i] = -1;
}
for(i = N/2; i < N; i++){
k = 0;
for(j = 0; j < N/2; j++){
if ((float)rand()/(float)RAND_MAX < Pr){
w21[k+(N/2)*(i-N/2)] = j;
k++;
}
}
w21[k+(N/2)*(i-N/2)] = -1;
w21[(N/2)-1+(N/2)*(i-N/2)] = -1;
}
for(i = N/2; i < N; i++){
k = 0;
for(j = N/2; j < N; j++){
if ((float)rand()/(float)RAND_MAX < Pr){
w22[k+(N/2)*(i-N/2)] = j-N/2;
k++;
}
}
w22[k+(N/2)*(i-N/2)] = -1;
w22[(N/2)-1+(N/2)*(i-N/2)] = -1;
}
}
void finalize()
{
//free(w);
free(w11);
free(w12);
free(w21);
free(w22);
free(z);
free(u);
free(result);
}
__global__ void Kernel(const int *w11, const int *w12, const int *w21, const int *w22, float *z, float *u, float *result, const float decay, const int t)
{
int i, j, k;
float r;
__shared__ float zsh[N/2];
i = threadIdx.x;
if (blockIdx.x == 0){ // i = 0...N/2
// w11
zsh[i] = z[i];
__syncthreads();
r = 0;
for(k = 0; w11[k+(N/2)*i] != -1; k++){
j = w11[k+(N/2)*i];
r += zsh[j];
}
u[i] = decay*u[i] + (1 - decay)*I - Kappa*r/N;
__syncthreads();
// w12
zsh[i] = z[i+N/2];
__syncthreads();
r = 0;
for(k = 0; w12[k+(N/2)*i] != -1; k++){
j = w12[k+(N/2)*i];
r += zsh[j];
}
u[i] += - Kappa*r/N;
__syncthreads();
if (u[i] > 0){
z[i] = u[i];
}else{
z[i] = 0;
}
result[i+N*t] = z[i];
}else{ // i = N/2...N
// w21
zsh[i] = z[i];
__syncthreads();
r = 0;
for(k = 0; w21[k+(N/2)*i] != -1; k++){
j = w21[k+(N/2)*i];
r += zsh[j];
}
u[i+N/2] = decay*u[i+N/2] + (1 - decay)*I - Kappa*r/N;
__syncthreads();
// w22
zsh[i] = z[i+N/2];
__syncthreads();
r = 0;
for(k = 0; w22[k+(N/2)*i] != -1; k++){
j = w22[k+(N/2)*i];
r += zsh[j];
}
u[i+N/2] += - Kappa*r/N;
__syncthreads();
if (u[i+N/2] > 0){
z[i+N/2] = u[i+N/2];
}else{
z[i+N/2] = 0;
}
result[(i+N/2)+N*t] = z[i+N/2];
}
}
void loop()
{
float *zd, *ud, *resultd;
//int *wd;
int *w11d, *w12d, *w21d, *w22d;
float decay;
cudaError_t stat;
int t;
decay = exp(-1.0/Tau);
//cudaMalloc((void**)&wd, N*N*sizeof(int));
cudaMalloc((void**)&w11d, (N/2)*(N/2)*sizeof(int));
cudaMalloc((void**)&w12d, (N/2)*(N/2)*sizeof(int));
cudaMalloc((void**)&w21d, (N/2)*(N/2)*sizeof(int));
cudaMalloc((void**)&w22d, (N/2)*(N/2)*sizeof(int));
cudaMalloc((void**)&zd, N*sizeof(float));
cudaMalloc((void**)&ud, N*sizeof(float));
cudaMalloc((void**)&resultd, N*T*sizeof(float));
//cudaMemcpy(wd, w, N*N*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(w11d, w11, (N/2)*(N/2)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(w12d, w12, (N/2)*(N/2)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(w21d, w21, (N/2)*(N/2)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(w22d, w22, (N/2)*(N/2)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(zd, z, N*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(ud, u, N*sizeof(float), cudaMemcpyHostToDevice);
dim3 dimBlock(BLOCK_SIZE);
dim3 dimGrid(N/BLOCK_SIZE);
for(t = 0; t < T; t++){
//Kernel<<<dimGrid,dimBlock>>>(wd, zd, ud, resultd, decay, t);
Kernel<<<dimGrid,dimBlock>>>(w11d, w12d, w21d, w22d, zd, ud, resultd, decay, t);
}
stat = cudaMemcpy(result, resultd, N*T*sizeof(float), cudaMemcpyDeviceToHost);
if (stat != cudaSuccess){
puts("error");
}
//cudaFree(wd);
cudaFree(w11d);
cudaFree(w12d);
cudaFree(w21d);
cudaFree(w22d);
cudaFree(zd);
cudaFree(ud);
cudaFree(resultd);
}
void output(char *prefix)
{
FILE *f;
int t, i;
char fn[1024];
sprintf(fn, "%s.r", prefix);
f = fopen(fn, "w");
for(t = 0; t < T; t++){
for(i = 0; i < N; i++){
if (result[i+N*t] > 0){
fprintf(f, "%d %d\n", t, i);
}
}
}
fclose(f);
}
int main(int argc, char *argv[])
{
char *prefix;
if (argc < 2){
fprintf(stderr, "%s <prefix>\n", argv[0]);
exit(1);
}
prefix = argv[1];
initialize();
loop();
output(prefix);
finalize();
return 0;
} | .file "tmpxft_0007f921_00000000-6_ic_shared.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10initializev
.type _Z10initializev, @function
_Z10initializev:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl $1048576, %edi
call malloc@PLT
movq %rax, w11(%rip)
movl $1048576, %edi
call malloc@PLT
movq %rax, w12(%rip)
movl $1048576, %edi
call malloc@PLT
movq %rax, w21(%rip)
movl $1048576, %edi
call malloc@PLT
movq %rax, w22(%rip)
movl $4096, %edi
call malloc@PLT
movq %rax, z(%rip)
movl $4096, %edi
call malloc@PLT
movq %rax, u(%rip)
movl $4096000, %edi
call malloc@PLT
movq %rax, result(%rip)
movl $0, %eax
movss .LC1(%rip), %xmm0
.L4:
movq z(%rip), %rdx
movl $0x00000000, (%rdx,%rax)
movq u(%rip), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $4096, %rax
jne .L4
movl $23, %edi
call srand@PLT
movl $2044, %r13d
movl $0, %r14d
jmp .L5
.L6:
addl $1, %ebx
cmpl $512, %ebx
je .L35
.L8:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC2(%rip), %xmm0
movss .LC3(%rip), %xmm1
comiss %xmm0, %xmm1
jbe .L6
leal (%r12,%rbp), %eax
cltq
movq w11(%rip), %rdx
movl %ebx, (%rdx,%rax,4)
addl $1, %ebp
jmp .L6
.L35:
leal (%r12,%rbp), %eax
cltq
movq w11(%rip), %rdx
movl $-1, (%rdx,%rax,4)
movq w11(%rip), %rax
movl $-1, (%rax,%r13)
addl $512, %r14d
addq $2048, %r13
cmpq $1050620, %r13
je .L22
.L5:
movl %r14d, %r12d
movl $0, %ebp
movl $0, %ebx
jmp .L8
.L10:
addl $1, %ebx
cmpl $512, %ebx
je .L36
.L12:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC2(%rip), %xmm0
movss .LC3(%rip), %xmm2
comiss %xmm0, %xmm2
jbe .L10
leal (%r12,%rbp), %eax
cltq
movq w12(%rip), %rdx
movl %ebx, (%rdx,%rax,4)
addl $1, %ebp
jmp .L10
.L36:
leal (%r12,%rbp), %eax
cltq
movq w12(%rip), %rdx
movl $-1, (%rdx,%rax,4)
movq w12(%rip), %rax
movl $-1, (%rax,%r13)
addl $512, %r14d
addq $2048, %r13
cmpq $1050620, %r13
je .L37
.L9:
movl %r14d, %r12d
movl $0, %ebx
movl $0, %ebp
jmp .L12
.L22:
movl $2044, %r13d
movl $0, %r14d
jmp .L9
.L14:
addl $1, %ebx
cmpl $512, %ebx
je .L38
.L16:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC2(%rip), %xmm0
movss .LC3(%rip), %xmm3
comiss %xmm0, %xmm3
jbe .L14
leal (%r12,%rbp), %eax
cltq
movq w21(%rip), %rdx
movl %ebx, (%rdx,%rax,4)
addl $1, %ebp
jmp .L14
.L38:
leal (%r12,%rbp), %eax
cltq
movq w21(%rip), %rdx
movl $-1, (%rdx,%rax,4)
movq w21(%rip), %rax
movl $-1, (%rax,%r14)
addl $512, %r13d
addq $2048, %r14
cmpl $262144, %r13d
je .L39
.L13:
movl %r13d, %r12d
movl $0, %ebp
movl $0, %ebx
jmp .L16
.L37:
movl $2044, %r14d
movl $0, %r13d
jmp .L13
.L18:
addl $1, %ebx
cmpl $512, %ebx
je .L40
.L20:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC2(%rip), %xmm0
movss .LC3(%rip), %xmm4
comiss %xmm0, %xmm4
jbe .L18
leal (%r12,%rbp), %eax
cltq
movq w22(%rip), %rdx
movl %ebx, (%rdx,%rax,4)
addl $1, %ebp
jmp .L18
.L40:
leal (%r12,%rbp), %eax
cltq
movq w22(%rip), %rdx
movl $-1, (%rdx,%rax,4)
movq w22(%rip), %rax
movl $-1, (%rax,%r14)
addl $512, %r13d
addq $2048, %r14
cmpl $262144, %r13d
je .L41
.L17:
movl %r13d, %r12d
movl $0, %ebx
movl $0, %ebp
jmp .L20
.L39:
movl $2044, %r14d
movl $0, %r13d
jmp .L17
.L41:
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z10initializev, .-_Z10initializev
.globl _Z8finalizev
.type _Z8finalizev, @function
_Z8finalizev:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq w11(%rip), %rdi
call free@PLT
movq w12(%rip), %rdi
call free@PLT
movq w21(%rip), %rdi
call free@PLT
movq w22(%rip), %rdi
call free@PLT
movq z(%rip), %rdi
call free@PLT
movq u(%rip), %rdi
call free@PLT
movq result(%rip), %rdi
call free@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z8finalizev, .-_Z8finalizev
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "%s.r"
.LC5:
.string "w"
.LC6:
.string "%d %d\n"
.text
.globl _Z6outputPc
.type _Z6outputPc, @function
_Z6outputPc:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1048, %rsp
.cfi_def_cfa_offset 1104
movq %rdi, %r8
movq %fs:40, %rax
movq %rax, 1032(%rsp)
xorl %eax, %eax
movq %rsp, %rbx
leaq .LC4(%rip), %rcx
movl $1024, %edx
movl $2, %esi
movq %rbx, %rdi
call __sprintf_chk@PLT
leaq .LC5(%rip), %rsi
movq %rbx, %rdi
call fopen@PLT
movq %rax, %r13
movl $0, %r15d
leaq .LC6(%rip), %r14
jmp .L45
.L46:
addl $1, %ebx
addq $4, %rbp
cmpl $1024, %ebx
je .L54
.L48:
movq result(%rip), %rax
movss (%rax,%rbp), %xmm1
pxor %xmm0, %xmm0
comiss %xmm0, %xmm1
jbe .L46
movl %ebx, %r8d
movl %r12d, %ecx
movq %r14, %rdx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L46
.L54:
addq $1, %r15
cmpq $1000, %r15
je .L49
.L45:
movl %r15d, %r12d
movq %r15, %rbp
salq $12, %rbp
movl $0, %ebx
jmp .L48
.L49:
movq %r13, %rdi
call fclose@PLT
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L55
addq $1048, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z6outputPc, .-_Z6outputPc
.globl _Z45__device_stub__Z6KernelPKiS0_S0_S0_PfS1_S1_fiPKiS0_S0_S0_PfS1_S1_fi
.type _Z45__device_stub__Z6KernelPKiS0_S0_S0_PfS1_S1_fiPKiS0_S0_S0_PfS1_S1_fi, @function
_Z45__device_stub__Z6KernelPKiS0_S0_S0_PfS1_S1_fiPKiS0_S0_S0_PfS1_S1_fi:
.LFB2086:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movss %xmm0, 4(%rsp)
movq 224(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 4(%rsp), %rax
movq %rax, 184(%rsp)
leaq 232(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L60
.L56:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L61
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z6KernelPKiS0_S0_S0_PfS1_S1_fi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L56
.L61:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z45__device_stub__Z6KernelPKiS0_S0_S0_PfS1_S1_fiPKiS0_S0_S0_PfS1_S1_fi, .-_Z45__device_stub__Z6KernelPKiS0_S0_S0_PfS1_S1_fiPKiS0_S0_S0_PfS1_S1_fi
.globl _Z6KernelPKiS0_S0_S0_PfS1_S1_fi
.type _Z6KernelPKiS0_S0_S0_PfS1_S1_fi, @function
_Z6KernelPKiS0_S0_S0_PfS1_S1_fi:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z45__device_stub__Z6KernelPKiS0_S0_S0_PfS1_S1_fiPKiS0_S0_S0_PfS1_S1_fi
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z6KernelPKiS0_S0_S0_PfS1_S1_fi, .-_Z6KernelPKiS0_S0_S0_PfS1_S1_fi
.section .rodata.str1.1
.LC8:
.string "error"
.text
.globl _Z4loopv
.type _Z4loopv, @function
_Z4loopv:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $96, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4096000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $1048576, %edx
movq w11(%rip), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1048576, %edx
movq w12(%rip), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1048576, %edx
movq w21(%rip), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1048576, %edx
movq w22(%rip), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq z(%rip), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq u(%rip), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $2, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %ebx
jmp .L66
.L65:
addl $1, %ebx
cmpl $1000, %ebx
je .L71
.L66:
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L65
pushq %rbx
.cfi_def_cfa_offset 120
pushq 32(%rsp)
.cfi_def_cfa_offset 128
movss .LC7(%rip), %xmm0
movq 32(%rsp), %r9
movq 24(%rsp), %r8
movq 72(%rsp), %rcx
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z45__device_stub__Z6KernelPKiS0_S0_S0_PfS1_S1_fiPKiS0_S0_S0_PfS1_S1_fi
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L65
.L71:
movl $2, %ecx
movl $4096000, %edx
movq 24(%rsp), %rsi
movq result(%rip), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L72
.L67:
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L73
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L72:
.cfi_restore_state
leaq .LC8(%rip), %rdi
call puts@PLT
jmp .L67
.L73:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z4loopv, .-_Z4loopv
.section .rodata.str1.1
.LC9:
.string "%s <prefix>\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
cmpl $1, %edi
jle .L77
movq 8(%rsi), %rbx
call _Z10initializev
call _Z4loopv
movq %rbx, %rdi
call _Z6outputPc
call _Z8finalizev
movl $0, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L77:
.cfi_restore_state
movq (%rsi), %rcx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC10:
.string "_Z6KernelPKiS0_S0_S0_PfS1_S1_fi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z6KernelPKiS0_S0_S0_PfS1_S1_fi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl w22
.bss
.align 8
.type w22, @object
.size w22, 8
w22:
.zero 8
.globl w21
.align 8
.type w21, @object
.size w21, 8
w21:
.zero 8
.globl w12
.align 8
.type w12, @object
.size w12, 8
w12:
.zero 8
.globl w11
.align 8
.type w11, @object
.size w11, 8
w11:
.zero 8
.globl result
.align 8
.type result, @object
.size result, 8
result:
.zero 8
.globl u
.align 8
.type u, @object
.size u, 8
u:
.zero 8
.globl z
.align 8
.type z, @object
.size z, 8
z:
.zero 8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 805306368
.align 4
.LC3:
.long 1056964608
.align 4
.LC7:
.long 1065186280
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
Sample Implementation of
Yamazaki and Tanaka (2005).
Neural Modeling of an Internal Clock.
Neural Computation 17:1032--1058.
using only global memory of CUDA.
Licensed under Creative Commons Attribution License (CC-BY)
http://creativecommons.org/licenses/by/3.0/
*/
#include<stdio.h>
#include<stdlib.h>
#include<math.h>
#define N 1024 // To be 2^k
#define T 1000
#define Pr 0.5
#define I 1.0
#define Kappa 2.0
#define Tau 100.0
#define BLOCK_SIZE 512
float *z, *u, *result;
//int *w;
int *w11, *w12, *w21, *w22;
void initialize()
{
int i, j, k;
//w = (int *)malloc(N*N*sizeof(int));
w11 = (int *)malloc((N/2)*(N/2)*sizeof(int));
w12 = (int *)malloc((N/2)*(N/2)*sizeof(int));
w21 = (int *)malloc((N/2)*(N/2)*sizeof(int));
w22 = (int *)malloc((N/2)*(N/2)*sizeof(int));
z = (float *)malloc(N*sizeof(float));
u = (float *)malloc(N*sizeof(float));
result = (float *)malloc(T*N*sizeof(float));
for(i = 0; i < N; i++){
z[i] = 0;
u[i] = I;
}
srand(23);
/*
for(i = 0; i < N; i++){
k = 0;
for(j = 0; j < N; j++){
if ((float)rand()/(float)RAND_MAX < Pr){
w[k+N*i] = j;
k++;
}
}
w[k+N*i] = -1;
}
*/
for(i = 0; i < N/2; i++){
k = 0;
for(j = 0; j < N/2; j++){
if ((float)rand()/(float)RAND_MAX < Pr){
w11[k+(N/2)*i] = j;
k++;
}
}
w11[k+(N/2)*i] = -1;
w11[(N/2)-1+(N/2)*i] = -1;
}
for(i = 0; i < N/2; i++){
k = 0;
for(j = N/2; j < N; j++){
if ((float)rand()/(float)RAND_MAX < Pr){
w12[k+(N/2)*i] = j-N/2;
k++;
}
}
w12[k+(N/2)*i] = -1;
w12[(N/2)-1+(N/2)*i] = -1;
}
for(i = N/2; i < N; i++){
k = 0;
for(j = 0; j < N/2; j++){
if ((float)rand()/(float)RAND_MAX < Pr){
w21[k+(N/2)*(i-N/2)] = j;
k++;
}
}
w21[k+(N/2)*(i-N/2)] = -1;
w21[(N/2)-1+(N/2)*(i-N/2)] = -1;
}
for(i = N/2; i < N; i++){
k = 0;
for(j = N/2; j < N; j++){
if ((float)rand()/(float)RAND_MAX < Pr){
w22[k+(N/2)*(i-N/2)] = j-N/2;
k++;
}
}
w22[k+(N/2)*(i-N/2)] = -1;
w22[(N/2)-1+(N/2)*(i-N/2)] = -1;
}
}
void finalize()
{
//free(w);
free(w11);
free(w12);
free(w21);
free(w22);
free(z);
free(u);
free(result);
}
__global__ void Kernel(const int *w11, const int *w12, const int *w21, const int *w22, float *z, float *u, float *result, const float decay, const int t)
{
int i, j, k;
float r;
__shared__ float zsh[N/2];
i = threadIdx.x;
if (blockIdx.x == 0){ // i = 0...N/2
// w11
zsh[i] = z[i];
__syncthreads();
r = 0;
for(k = 0; w11[k+(N/2)*i] != -1; k++){
j = w11[k+(N/2)*i];
r += zsh[j];
}
u[i] = decay*u[i] + (1 - decay)*I - Kappa*r/N;
__syncthreads();
// w12
zsh[i] = z[i+N/2];
__syncthreads();
r = 0;
for(k = 0; w12[k+(N/2)*i] != -1; k++){
j = w12[k+(N/2)*i];
r += zsh[j];
}
u[i] += - Kappa*r/N;
__syncthreads();
if (u[i] > 0){
z[i] = u[i];
}else{
z[i] = 0;
}
result[i+N*t] = z[i];
}else{ // i = N/2...N
// w21
zsh[i] = z[i];
__syncthreads();
r = 0;
for(k = 0; w21[k+(N/2)*i] != -1; k++){
j = w21[k+(N/2)*i];
r += zsh[j];
}
u[i+N/2] = decay*u[i+N/2] + (1 - decay)*I - Kappa*r/N;
__syncthreads();
// w22
zsh[i] = z[i+N/2];
__syncthreads();
r = 0;
for(k = 0; w22[k+(N/2)*i] != -1; k++){
j = w22[k+(N/2)*i];
r += zsh[j];
}
u[i+N/2] += - Kappa*r/N;
__syncthreads();
if (u[i+N/2] > 0){
z[i+N/2] = u[i+N/2];
}else{
z[i+N/2] = 0;
}
result[(i+N/2)+N*t] = z[i+N/2];
}
}
void loop()
{
float *zd, *ud, *resultd;
//int *wd;
int *w11d, *w12d, *w21d, *w22d;
float decay;
cudaError_t stat;
int t;
decay = exp(-1.0/Tau);
//cudaMalloc((void**)&wd, N*N*sizeof(int));
cudaMalloc((void**)&w11d, (N/2)*(N/2)*sizeof(int));
cudaMalloc((void**)&w12d, (N/2)*(N/2)*sizeof(int));
cudaMalloc((void**)&w21d, (N/2)*(N/2)*sizeof(int));
cudaMalloc((void**)&w22d, (N/2)*(N/2)*sizeof(int));
cudaMalloc((void**)&zd, N*sizeof(float));
cudaMalloc((void**)&ud, N*sizeof(float));
cudaMalloc((void**)&resultd, N*T*sizeof(float));
//cudaMemcpy(wd, w, N*N*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(w11d, w11, (N/2)*(N/2)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(w12d, w12, (N/2)*(N/2)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(w21d, w21, (N/2)*(N/2)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(w22d, w22, (N/2)*(N/2)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(zd, z, N*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(ud, u, N*sizeof(float), cudaMemcpyHostToDevice);
dim3 dimBlock(BLOCK_SIZE);
dim3 dimGrid(N/BLOCK_SIZE);
for(t = 0; t < T; t++){
//Kernel<<<dimGrid,dimBlock>>>(wd, zd, ud, resultd, decay, t);
Kernel<<<dimGrid,dimBlock>>>(w11d, w12d, w21d, w22d, zd, ud, resultd, decay, t);
}
stat = cudaMemcpy(result, resultd, N*T*sizeof(float), cudaMemcpyDeviceToHost);
if (stat != cudaSuccess){
puts("error");
}
//cudaFree(wd);
cudaFree(w11d);
cudaFree(w12d);
cudaFree(w21d);
cudaFree(w22d);
cudaFree(zd);
cudaFree(ud);
cudaFree(resultd);
}
void output(char *prefix)
{
FILE *f;
int t, i;
char fn[1024];
sprintf(fn, "%s.r", prefix);
f = fopen(fn, "w");
for(t = 0; t < T; t++){
for(i = 0; i < N; i++){
if (result[i+N*t] > 0){
fprintf(f, "%d %d\n", t, i);
}
}
}
fclose(f);
}
int main(int argc, char *argv[])
{
char *prefix;
if (argc < 2){
fprintf(stderr, "%s <prefix>\n", argv[0]);
exit(1);
}
prefix = argv[1];
initialize();
loop();
output(prefix);
finalize();
return 0;
} | /*
Sample Implementation of
Yamazaki and Tanaka (2005).
Neural Modeling of an Internal Clock.
Neural Computation 17:1032--1058.
using only global memory of CUDA.
Licensed under Creative Commons Attribution License (CC-BY)
http://creativecommons.org/licenses/by/3.0/
*/
#include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<math.h>
#define N 1024 // To be 2^k
#define T 1000
#define Pr 0.5
#define I 1.0
#define Kappa 2.0
#define Tau 100.0
#define BLOCK_SIZE 512
float *z, *u, *result;
//int *w;
int *w11, *w12, *w21, *w22;
void initialize()
{
int i, j, k;
//w = (int *)malloc(N*N*sizeof(int));
w11 = (int *)malloc((N/2)*(N/2)*sizeof(int));
w12 = (int *)malloc((N/2)*(N/2)*sizeof(int));
w21 = (int *)malloc((N/2)*(N/2)*sizeof(int));
w22 = (int *)malloc((N/2)*(N/2)*sizeof(int));
z = (float *)malloc(N*sizeof(float));
u = (float *)malloc(N*sizeof(float));
result = (float *)malloc(T*N*sizeof(float));
for(i = 0; i < N; i++){
z[i] = 0;
u[i] = I;
}
srand(23);
/*
for(i = 0; i < N; i++){
k = 0;
for(j = 0; j < N; j++){
if ((float)rand()/(float)RAND_MAX < Pr){
w[k+N*i] = j;
k++;
}
}
w[k+N*i] = -1;
}
*/
for(i = 0; i < N/2; i++){
k = 0;
for(j = 0; j < N/2; j++){
if ((float)rand()/(float)RAND_MAX < Pr){
w11[k+(N/2)*i] = j;
k++;
}
}
w11[k+(N/2)*i] = -1;
w11[(N/2)-1+(N/2)*i] = -1;
}
for(i = 0; i < N/2; i++){
k = 0;
for(j = N/2; j < N; j++){
if ((float)rand()/(float)RAND_MAX < Pr){
w12[k+(N/2)*i] = j-N/2;
k++;
}
}
w12[k+(N/2)*i] = -1;
w12[(N/2)-1+(N/2)*i] = -1;
}
for(i = N/2; i < N; i++){
k = 0;
for(j = 0; j < N/2; j++){
if ((float)rand()/(float)RAND_MAX < Pr){
w21[k+(N/2)*(i-N/2)] = j;
k++;
}
}
w21[k+(N/2)*(i-N/2)] = -1;
w21[(N/2)-1+(N/2)*(i-N/2)] = -1;
}
for(i = N/2; i < N; i++){
k = 0;
for(j = N/2; j < N; j++){
if ((float)rand()/(float)RAND_MAX < Pr){
w22[k+(N/2)*(i-N/2)] = j-N/2;
k++;
}
}
w22[k+(N/2)*(i-N/2)] = -1;
w22[(N/2)-1+(N/2)*(i-N/2)] = -1;
}
}
void finalize()
{
//free(w);
free(w11);
free(w12);
free(w21);
free(w22);
free(z);
free(u);
free(result);
}
__global__ void Kernel(const int *w11, const int *w12, const int *w21, const int *w22, float *z, float *u, float *result, const float decay, const int t)
{
int i, j, k;
float r;
__shared__ float zsh[N/2];
i = threadIdx.x;
if (blockIdx.x == 0){ // i = 0...N/2
// w11
zsh[i] = z[i];
__syncthreads();
r = 0;
for(k = 0; w11[k+(N/2)*i] != -1; k++){
j = w11[k+(N/2)*i];
r += zsh[j];
}
u[i] = decay*u[i] + (1 - decay)*I - Kappa*r/N;
__syncthreads();
// w12
zsh[i] = z[i+N/2];
__syncthreads();
r = 0;
for(k = 0; w12[k+(N/2)*i] != -1; k++){
j = w12[k+(N/2)*i];
r += zsh[j];
}
u[i] += - Kappa*r/N;
__syncthreads();
if (u[i] > 0){
z[i] = u[i];
}else{
z[i] = 0;
}
result[i+N*t] = z[i];
}else{ // i = N/2...N
// w21
zsh[i] = z[i];
__syncthreads();
r = 0;
for(k = 0; w21[k+(N/2)*i] != -1; k++){
j = w21[k+(N/2)*i];
r += zsh[j];
}
u[i+N/2] = decay*u[i+N/2] + (1 - decay)*I - Kappa*r/N;
__syncthreads();
// w22
zsh[i] = z[i+N/2];
__syncthreads();
r = 0;
for(k = 0; w22[k+(N/2)*i] != -1; k++){
j = w22[k+(N/2)*i];
r += zsh[j];
}
u[i+N/2] += - Kappa*r/N;
__syncthreads();
if (u[i+N/2] > 0){
z[i+N/2] = u[i+N/2];
}else{
z[i+N/2] = 0;
}
result[(i+N/2)+N*t] = z[i+N/2];
}
}
void loop()
{
float *zd, *ud, *resultd;
//int *wd;
int *w11d, *w12d, *w21d, *w22d;
float decay;
hipError_t stat;
int t;
decay = exp(-1.0/Tau);
//cudaMalloc((void**)&wd, N*N*sizeof(int));
hipMalloc((void**)&w11d, (N/2)*(N/2)*sizeof(int));
hipMalloc((void**)&w12d, (N/2)*(N/2)*sizeof(int));
hipMalloc((void**)&w21d, (N/2)*(N/2)*sizeof(int));
hipMalloc((void**)&w22d, (N/2)*(N/2)*sizeof(int));
hipMalloc((void**)&zd, N*sizeof(float));
hipMalloc((void**)&ud, N*sizeof(float));
hipMalloc((void**)&resultd, N*T*sizeof(float));
//cudaMemcpy(wd, w, N*N*sizeof(int), cudaMemcpyHostToDevice);
hipMemcpy(w11d, w11, (N/2)*(N/2)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(w12d, w12, (N/2)*(N/2)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(w21d, w21, (N/2)*(N/2)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(w22d, w22, (N/2)*(N/2)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(zd, z, N*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(ud, u, N*sizeof(float), hipMemcpyHostToDevice);
dim3 dimBlock(BLOCK_SIZE);
dim3 dimGrid(N/BLOCK_SIZE);
for(t = 0; t < T; t++){
//Kernel<<<dimGrid,dimBlock>>>(wd, zd, ud, resultd, decay, t);
Kernel<<<dimGrid,dimBlock>>>(w11d, w12d, w21d, w22d, zd, ud, resultd, decay, t);
}
stat = hipMemcpy(result, resultd, N*T*sizeof(float), hipMemcpyDeviceToHost);
if (stat != hipSuccess){
puts("error");
}
//cudaFree(wd);
hipFree(w11d);
hipFree(w12d);
hipFree(w21d);
hipFree(w22d);
hipFree(zd);
hipFree(ud);
hipFree(resultd);
}
void output(char *prefix)
{
FILE *f;
int t, i;
char fn[1024];
sprintf(fn, "%s.r", prefix);
f = fopen(fn, "w");
for(t = 0; t < T; t++){
for(i = 0; i < N; i++){
if (result[i+N*t] > 0){
fprintf(f, "%d %d\n", t, i);
}
}
}
fclose(f);
}
int main(int argc, char *argv[])
{
char *prefix;
if (argc < 2){
fprintf(stderr, "%s <prefix>\n", argv[0]);
exit(1);
}
prefix = argv[1];
initialize();
loop();
output(prefix);
finalize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
Sample Implementation of
Yamazaki and Tanaka (2005).
Neural Modeling of an Internal Clock.
Neural Computation 17:1032--1058.
using only global memory of CUDA.
Licensed under Creative Commons Attribution License (CC-BY)
http://creativecommons.org/licenses/by/3.0/
*/
#include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<math.h>
#define N 1024 // To be 2^k
#define T 1000
#define Pr 0.5
#define I 1.0
#define Kappa 2.0
#define Tau 100.0
#define BLOCK_SIZE 512
float *z, *u, *result;
//int *w;
int *w11, *w12, *w21, *w22;
void initialize()
{
int i, j, k;
//w = (int *)malloc(N*N*sizeof(int));
w11 = (int *)malloc((N/2)*(N/2)*sizeof(int));
w12 = (int *)malloc((N/2)*(N/2)*sizeof(int));
w21 = (int *)malloc((N/2)*(N/2)*sizeof(int));
w22 = (int *)malloc((N/2)*(N/2)*sizeof(int));
z = (float *)malloc(N*sizeof(float));
u = (float *)malloc(N*sizeof(float));
result = (float *)malloc(T*N*sizeof(float));
for(i = 0; i < N; i++){
z[i] = 0;
u[i] = I;
}
srand(23);
/*
for(i = 0; i < N; i++){
k = 0;
for(j = 0; j < N; j++){
if ((float)rand()/(float)RAND_MAX < Pr){
w[k+N*i] = j;
k++;
}
}
w[k+N*i] = -1;
}
*/
for(i = 0; i < N/2; i++){
k = 0;
for(j = 0; j < N/2; j++){
if ((float)rand()/(float)RAND_MAX < Pr){
w11[k+(N/2)*i] = j;
k++;
}
}
w11[k+(N/2)*i] = -1;
w11[(N/2)-1+(N/2)*i] = -1;
}
for(i = 0; i < N/2; i++){
k = 0;
for(j = N/2; j < N; j++){
if ((float)rand()/(float)RAND_MAX < Pr){
w12[k+(N/2)*i] = j-N/2;
k++;
}
}
w12[k+(N/2)*i] = -1;
w12[(N/2)-1+(N/2)*i] = -1;
}
for(i = N/2; i < N; i++){
k = 0;
for(j = 0; j < N/2; j++){
if ((float)rand()/(float)RAND_MAX < Pr){
w21[k+(N/2)*(i-N/2)] = j;
k++;
}
}
w21[k+(N/2)*(i-N/2)] = -1;
w21[(N/2)-1+(N/2)*(i-N/2)] = -1;
}
for(i = N/2; i < N; i++){
k = 0;
for(j = N/2; j < N; j++){
if ((float)rand()/(float)RAND_MAX < Pr){
w22[k+(N/2)*(i-N/2)] = j-N/2;
k++;
}
}
w22[k+(N/2)*(i-N/2)] = -1;
w22[(N/2)-1+(N/2)*(i-N/2)] = -1;
}
}
void finalize()
{
//free(w);
free(w11);
free(w12);
free(w21);
free(w22);
free(z);
free(u);
free(result);
}
__global__ void Kernel(const int *w11, const int *w12, const int *w21, const int *w22, float *z, float *u, float *result, const float decay, const int t)
{
int i, j, k;
float r;
__shared__ float zsh[N/2];
i = threadIdx.x;
if (blockIdx.x == 0){ // i = 0...N/2
// w11
zsh[i] = z[i];
__syncthreads();
r = 0;
for(k = 0; w11[k+(N/2)*i] != -1; k++){
j = w11[k+(N/2)*i];
r += zsh[j];
}
u[i] = decay*u[i] + (1 - decay)*I - Kappa*r/N;
__syncthreads();
// w12
zsh[i] = z[i+N/2];
__syncthreads();
r = 0;
for(k = 0; w12[k+(N/2)*i] != -1; k++){
j = w12[k+(N/2)*i];
r += zsh[j];
}
u[i] += - Kappa*r/N;
__syncthreads();
if (u[i] > 0){
z[i] = u[i];
}else{
z[i] = 0;
}
result[i+N*t] = z[i];
}else{ // i = N/2...N
// w21
zsh[i] = z[i];
__syncthreads();
r = 0;
for(k = 0; w21[k+(N/2)*i] != -1; k++){
j = w21[k+(N/2)*i];
r += zsh[j];
}
u[i+N/2] = decay*u[i+N/2] + (1 - decay)*I - Kappa*r/N;
__syncthreads();
// w22
zsh[i] = z[i+N/2];
__syncthreads();
r = 0;
for(k = 0; w22[k+(N/2)*i] != -1; k++){
j = w22[k+(N/2)*i];
r += zsh[j];
}
u[i+N/2] += - Kappa*r/N;
__syncthreads();
if (u[i+N/2] > 0){
z[i+N/2] = u[i+N/2];
}else{
z[i+N/2] = 0;
}
result[(i+N/2)+N*t] = z[i+N/2];
}
}
void loop()
{
float *zd, *ud, *resultd;
//int *wd;
int *w11d, *w12d, *w21d, *w22d;
float decay;
hipError_t stat;
int t;
decay = exp(-1.0/Tau);
//cudaMalloc((void**)&wd, N*N*sizeof(int));
hipMalloc((void**)&w11d, (N/2)*(N/2)*sizeof(int));
hipMalloc((void**)&w12d, (N/2)*(N/2)*sizeof(int));
hipMalloc((void**)&w21d, (N/2)*(N/2)*sizeof(int));
hipMalloc((void**)&w22d, (N/2)*(N/2)*sizeof(int));
hipMalloc((void**)&zd, N*sizeof(float));
hipMalloc((void**)&ud, N*sizeof(float));
hipMalloc((void**)&resultd, N*T*sizeof(float));
//cudaMemcpy(wd, w, N*N*sizeof(int), cudaMemcpyHostToDevice);
hipMemcpy(w11d, w11, (N/2)*(N/2)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(w12d, w12, (N/2)*(N/2)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(w21d, w21, (N/2)*(N/2)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(w22d, w22, (N/2)*(N/2)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(zd, z, N*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(ud, u, N*sizeof(float), hipMemcpyHostToDevice);
dim3 dimBlock(BLOCK_SIZE);
dim3 dimGrid(N/BLOCK_SIZE);
for(t = 0; t < T; t++){
//Kernel<<<dimGrid,dimBlock>>>(wd, zd, ud, resultd, decay, t);
Kernel<<<dimGrid,dimBlock>>>(w11d, w12d, w21d, w22d, zd, ud, resultd, decay, t);
}
stat = hipMemcpy(result, resultd, N*T*sizeof(float), hipMemcpyDeviceToHost);
if (stat != hipSuccess){
puts("error");
}
//cudaFree(wd);
hipFree(w11d);
hipFree(w12d);
hipFree(w21d);
hipFree(w22d);
hipFree(zd);
hipFree(ud);
hipFree(resultd);
}
void output(char *prefix)
{
FILE *f;
int t, i;
char fn[1024];
sprintf(fn, "%s.r", prefix);
f = fopen(fn, "w");
for(t = 0; t < T; t++){
for(i = 0; i < N; i++){
if (result[i+N*t] > 0){
fprintf(f, "%d %d\n", t, i);
}
}
}
fclose(f);
}
int main(int argc, char *argv[])
{
char *prefix;
if (argc < 2){
fprintf(stderr, "%s <prefix>\n", argv[0]);
exit(1);
}
prefix = argv[1];
initialize();
loop();
output(prefix);
finalize();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6KernelPKiS0_S0_S0_PfS1_S1_fi
.globl _Z6KernelPKiS0_S0_S0_PfS1_S1_fi
.p2align 8
.type _Z6KernelPKiS0_S0_S0_PfS1_S1_fi,@function
_Z6KernelPKiS0_S0_S0_PfS1_S1_fi:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x20
s_load_b64 s[8:9], s[0:1], 0x38
v_lshlrev_b32_e32 v7, 2, v0
v_lshlrev_b32_e32 v8, 9, v0
s_cmp_lg_u32 s15, 0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v7, s[4:5]
s_waitcnt vmcnt(0)
ds_store_b32 v7, v1
s_waitcnt lgkmcnt(0)
s_cbranch_scc0 .LBB0_10
s_load_b64 s[2:3], s[0:1], 0x10
v_lshlrev_b32_e32 v1, 2, v8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s10, exec_lo
global_load_b32 v3, v1, s[2:3]
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e32 -1, v3
s_cbranch_execz .LBB0_5
v_dual_mov_b32 v4, 0 :: v_dual_lshlrev_b32 v1, 11, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s2, v1, s2
v_add_co_ci_u32_e64 v2, null, 0, s3, s2
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, v1, 4
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
.LBB0_3:
v_lshlrev_b32_e32 v5, 2, v3
global_load_b32 v3, v[1:2], off
v_add_co_u32 v1, vcc_lo, v1, 4
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
ds_load_b32 v5, v5
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v4, v4, v5
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s2, -1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s3, s2, s3
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s3
v_cvt_f64_f32_e32 v[1:2], v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[1:2], v[1:2], v[1:2]
v_ldexp_f64 v[1:2], v[1:2], -10
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s10
v_dual_mov_b32 v10, 0 :: v_dual_add_nc_u32 v9, 0x200, v0
v_sub_f32_e64 v4, 1.0, s8
s_load_b64 s[2:3], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v12, 2, v9
global_load_b32 v3, v12, s[6:7]
s_waitcnt vmcnt(0)
v_mul_f32_e32 v5, s8, v3
v_cvt_f64_f32_e32 v[3:4], v4
v_cvt_f64_f32_e32 v[5:6], v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_f64 v[3:4], v[3:4], v[5:6]
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v6, 0
v_add_f64 v[1:2], v[3:4], -v[1:2]
v_add_co_u32 v3, s10, s6, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v4, null, s7, 0, s10
v_cvt_f32_f64_e32 v1, v[1:2]
v_lshlrev_b32_e32 v2, 2, v8
global_store_b32 v12, v1, s[6:7]
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_load_b32 v1, v12, s[4:5]
s_waitcnt vmcnt(0)
ds_store_b32 v7, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
global_load_b32 v11, v2, s[2:3]
v_add_co_u32 v1, s10, s4, v12
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, null, s5, 0, s10
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e32 -1, v11
s_cbranch_execz .LBB0_9
v_lshlrev_b32_e32 v5, 11, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s2, v5, s2
v_add_co_ci_u32_e64 v6, null, 0, s3, s2
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
.LBB0_7:
v_lshlrev_b32_e32 v12, 2, v11
global_load_b32 v11, v[5:6], off
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
ds_load_b32 v12, v12
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v10, v10, v12
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s2, -1, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s3, s2, s3
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_7
s_or_b32 exec_lo, exec_lo, s3
v_cvt_f64_f32_e32 v[5:6], v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[5:6], v[5:6]
v_ldexp_f64 v[5:6], v[5:6], -10
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s10
global_load_b32 v10, v[3:4], off
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[10:11], v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[10:11], -v[5:6]
v_cvt_f32_f64_e32 v5, v[5:6]
global_store_b32 v[3:4], v5, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_max_f32_e32 v3, v3, v3
s_delay_alu instid0(VALU_DEP_1)
v_max_f32_e32 v5, 0, v3
v_lshl_add_u32 v3, s9, 10, v9
global_store_b32 v[1:2], v5, off
s_branch .LBB0_20
.LBB0_10:
s_cbranch_execz .LBB0_20
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v8
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_load_b32 v5, v1, s[2:3]
v_add_co_u32 v1, s4, s4, v7
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, null, s5, 0, s4
s_mov_b32 s4, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e32 -1, v5
s_cbranch_execz .LBB0_15
v_dual_mov_b32 v6, 0 :: v_dual_lshlrev_b32 v3, 11, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s2, v3, s2
v_add_co_ci_u32_e64 v4, null, 0, s3, s2
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_13:
v_lshlrev_b32_e32 v9, 2, v5
global_load_b32 v5, v[3:4], off
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
ds_load_b32 v9, v9
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v6, v6, v9
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s2, -1, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s3, s2, s3
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_13
s_or_b32 exec_lo, exec_lo, s3
v_cvt_f64_f32_e32 v[3:4], v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[3:4], v[3:4], v[3:4]
v_ldexp_f64 v[3:4], v[3:4], -10
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s4
v_lshlrev_b32_e32 v11, 2, v0
v_sub_f32_e64 v6, 1.0, s8
s_load_b64 s[2:3], s[0:1], 0x8
global_load_b32 v5, v11, s[6:7]
s_waitcnt vmcnt(0)
v_mul_f32_e32 v9, s8, v5
v_cvt_f64_f32_e32 v[5:6], v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[9:10], v9
v_add_f64 v[5:6], v[5:6], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_f64 v[3:4], v[5:6], -v[3:4]
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v6, 0
v_cvt_f32_f64_e32 v3, v[3:4]
v_lshlrev_b32_e32 v4, 2, v8
global_store_b32 v11, v3, s[6:7]
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_load_b32 v3, v[1:2], off offset:2048
s_waitcnt vmcnt(0)
ds_store_b32 v7, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
global_load_b32 v8, v4, s[2:3]
v_add_co_u32 v3, s4, s6, v11
v_mov_b32_e32 v7, 0
v_add_co_ci_u32_e64 v4, null, s7, 0, s4
s_mov_b32 s4, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e32 -1, v8
s_cbranch_execz .LBB0_19
v_lshlrev_b32_e32 v5, 11, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s2, v5, s2
v_add_co_ci_u32_e64 v6, null, 0, s3, s2
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
.LBB0_17:
v_lshlrev_b32_e32 v9, 2, v8
global_load_b32 v8, v[5:6], off
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
ds_load_b32 v9, v9
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v7, v7, v9
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s2, -1, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s3, s2, s3
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_17
s_or_b32 exec_lo, exec_lo, s3
v_cvt_f64_f32_e32 v[5:6], v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[5:6], v[5:6]
v_ldexp_f64 v[5:6], v[5:6], -10
.LBB0_19:
s_or_b32 exec_lo, exec_lo, s4
global_load_b32 v7, v[3:4], off
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[7:8], v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[7:8], -v[5:6]
v_cvt_f32_f64_e32 v5, v[5:6]
global_store_b32 v[3:4], v5, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_max_f32_e32 v3, v3, v3
s_delay_alu instid0(VALU_DEP_1)
v_max_f32_e32 v5, 0, v3
v_lshl_or_b32 v3, s9, 10, v0
global_store_b32 v[1:2], v5, off
.LBB0_20:
s_load_b64 s[0:1], s[0:1], 0x30
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6KernelPKiS0_S0_S0_PfS1_S1_fi
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 64
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6KernelPKiS0_S0_S0_PfS1_S1_fi, .Lfunc_end0-_Z6KernelPKiS0_S0_S0_PfS1_S1_fi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 60
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 64
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6KernelPKiS0_S0_S0_PfS1_S1_fi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6KernelPKiS0_S0_S0_PfS1_S1_fi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
Sample Implementation of
Yamazaki and Tanaka (2005).
Neural Modeling of an Internal Clock.
Neural Computation 17:1032--1058.
using only global memory of CUDA.
Licensed under Creative Commons Attribution License (CC-BY)
http://creativecommons.org/licenses/by/3.0/
*/
#include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<math.h>
#define N 1024 // To be 2^k
#define T 1000
#define Pr 0.5
#define I 1.0
#define Kappa 2.0
#define Tau 100.0
#define BLOCK_SIZE 512
float *z, *u, *result;
//int *w;
int *w11, *w12, *w21, *w22;
void initialize()
{
int i, j, k;
//w = (int *)malloc(N*N*sizeof(int));
w11 = (int *)malloc((N/2)*(N/2)*sizeof(int));
w12 = (int *)malloc((N/2)*(N/2)*sizeof(int));
w21 = (int *)malloc((N/2)*(N/2)*sizeof(int));
w22 = (int *)malloc((N/2)*(N/2)*sizeof(int));
z = (float *)malloc(N*sizeof(float));
u = (float *)malloc(N*sizeof(float));
result = (float *)malloc(T*N*sizeof(float));
for(i = 0; i < N; i++){
z[i] = 0;
u[i] = I;
}
srand(23);
/*
for(i = 0; i < N; i++){
k = 0;
for(j = 0; j < N; j++){
if ((float)rand()/(float)RAND_MAX < Pr){
w[k+N*i] = j;
k++;
}
}
w[k+N*i] = -1;
}
*/
for(i = 0; i < N/2; i++){
k = 0;
for(j = 0; j < N/2; j++){
if ((float)rand()/(float)RAND_MAX < Pr){
w11[k+(N/2)*i] = j;
k++;
}
}
w11[k+(N/2)*i] = -1;
w11[(N/2)-1+(N/2)*i] = -1;
}
for(i = 0; i < N/2; i++){
k = 0;
for(j = N/2; j < N; j++){
if ((float)rand()/(float)RAND_MAX < Pr){
w12[k+(N/2)*i] = j-N/2;
k++;
}
}
w12[k+(N/2)*i] = -1;
w12[(N/2)-1+(N/2)*i] = -1;
}
for(i = N/2; i < N; i++){
k = 0;
for(j = 0; j < N/2; j++){
if ((float)rand()/(float)RAND_MAX < Pr){
w21[k+(N/2)*(i-N/2)] = j;
k++;
}
}
w21[k+(N/2)*(i-N/2)] = -1;
w21[(N/2)-1+(N/2)*(i-N/2)] = -1;
}
for(i = N/2; i < N; i++){
k = 0;
for(j = N/2; j < N; j++){
if ((float)rand()/(float)RAND_MAX < Pr){
w22[k+(N/2)*(i-N/2)] = j-N/2;
k++;
}
}
w22[k+(N/2)*(i-N/2)] = -1;
w22[(N/2)-1+(N/2)*(i-N/2)] = -1;
}
}
void finalize()
{
//free(w);
free(w11);
free(w12);
free(w21);
free(w22);
free(z);
free(u);
free(result);
}
__global__ void Kernel(const int *w11, const int *w12, const int *w21, const int *w22, float *z, float *u, float *result, const float decay, const int t)
{
int i, j, k;
float r;
__shared__ float zsh[N/2];
i = threadIdx.x;
if (blockIdx.x == 0){ // i = 0...N/2
// w11
zsh[i] = z[i];
__syncthreads();
r = 0;
for(k = 0; w11[k+(N/2)*i] != -1; k++){
j = w11[k+(N/2)*i];
r += zsh[j];
}
u[i] = decay*u[i] + (1 - decay)*I - Kappa*r/N;
__syncthreads();
// w12
zsh[i] = z[i+N/2];
__syncthreads();
r = 0;
for(k = 0; w12[k+(N/2)*i] != -1; k++){
j = w12[k+(N/2)*i];
r += zsh[j];
}
u[i] += - Kappa*r/N;
__syncthreads();
if (u[i] > 0){
z[i] = u[i];
}else{
z[i] = 0;
}
result[i+N*t] = z[i];
}else{ // i = N/2...N
// w21
zsh[i] = z[i];
__syncthreads();
r = 0;
for(k = 0; w21[k+(N/2)*i] != -1; k++){
j = w21[k+(N/2)*i];
r += zsh[j];
}
u[i+N/2] = decay*u[i+N/2] + (1 - decay)*I - Kappa*r/N;
__syncthreads();
// w22
zsh[i] = z[i+N/2];
__syncthreads();
r = 0;
for(k = 0; w22[k+(N/2)*i] != -1; k++){
j = w22[k+(N/2)*i];
r += zsh[j];
}
u[i+N/2] += - Kappa*r/N;
__syncthreads();
if (u[i+N/2] > 0){
z[i+N/2] = u[i+N/2];
}else{
z[i+N/2] = 0;
}
result[(i+N/2)+N*t] = z[i+N/2];
}
}
void loop()
{
float *zd, *ud, *resultd;
//int *wd;
int *w11d, *w12d, *w21d, *w22d;
float decay;
hipError_t stat;
int t;
decay = exp(-1.0/Tau);
//cudaMalloc((void**)&wd, N*N*sizeof(int));
hipMalloc((void**)&w11d, (N/2)*(N/2)*sizeof(int));
hipMalloc((void**)&w12d, (N/2)*(N/2)*sizeof(int));
hipMalloc((void**)&w21d, (N/2)*(N/2)*sizeof(int));
hipMalloc((void**)&w22d, (N/2)*(N/2)*sizeof(int));
hipMalloc((void**)&zd, N*sizeof(float));
hipMalloc((void**)&ud, N*sizeof(float));
hipMalloc((void**)&resultd, N*T*sizeof(float));
//cudaMemcpy(wd, w, N*N*sizeof(int), cudaMemcpyHostToDevice);
hipMemcpy(w11d, w11, (N/2)*(N/2)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(w12d, w12, (N/2)*(N/2)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(w21d, w21, (N/2)*(N/2)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(w22d, w22, (N/2)*(N/2)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(zd, z, N*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(ud, u, N*sizeof(float), hipMemcpyHostToDevice);
dim3 dimBlock(BLOCK_SIZE);
dim3 dimGrid(N/BLOCK_SIZE);
for(t = 0; t < T; t++){
//Kernel<<<dimGrid,dimBlock>>>(wd, zd, ud, resultd, decay, t);
Kernel<<<dimGrid,dimBlock>>>(w11d, w12d, w21d, w22d, zd, ud, resultd, decay, t);
}
stat = hipMemcpy(result, resultd, N*T*sizeof(float), hipMemcpyDeviceToHost);
if (stat != hipSuccess){
puts("error");
}
//cudaFree(wd);
hipFree(w11d);
hipFree(w12d);
hipFree(w21d);
hipFree(w22d);
hipFree(zd);
hipFree(ud);
hipFree(resultd);
}
void output(char *prefix)
{
FILE *f;
int t, i;
char fn[1024];
sprintf(fn, "%s.r", prefix);
f = fopen(fn, "w");
for(t = 0; t < T; t++){
for(i = 0; i < N; i++){
if (result[i+N*t] > 0){
fprintf(f, "%d %d\n", t, i);
}
}
}
fclose(f);
}
int main(int argc, char *argv[])
{
char *prefix;
if (argc < 2){
fprintf(stderr, "%s <prefix>\n", argv[0]);
exit(1);
}
prefix = argv[1];
initialize();
loop();
output(prefix);
finalize();
return 0;
} | .text
.file "ic_shared.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z10initializev
.LCPI0_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI0_1:
.long 0x3f000000 # float 0.5
.text
.globl _Z10initializev
.p2align 4, 0x90
.type _Z10initializev,@function
_Z10initializev: # @_Z10initializev
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $1048576, %edi # imm = 0x100000
callq malloc
movq %rax, w11(%rip)
movl $1048576, %edi # imm = 0x100000
callq malloc
movq %rax, w12(%rip)
movl $1048576, %edi # imm = 0x100000
callq malloc
movq %rax, w21(%rip)
movl $1048576, %edi # imm = 0x100000
callq malloc
movq %rax, w22(%rip)
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r14
movq %rax, z(%rip)
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbx
movq %rax, u(%rip)
movl $4096000, %edi # imm = 0x3E8000
callq malloc
movq %rax, result(%rip)
xorl %r15d, %r15d
movl $4096, %edx # imm = 0x1000
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%r15,4) # imm = 0x3F800000
incq %r15
cmpq $1024, %r15 # imm = 0x400
jne .LBB0_1
# %bb.2:
movl $23, %edi
callq srand
xorl %ebx, %ebx
jmp .LBB0_3
.p2align 4, 0x90
.LBB0_7: # in Loop: Header=BB0_3 Depth=1
movq w11(%rip), %rax
movslq %r15d, %rcx
movq %rbx, %rdx
shlq $11, %rdx
leaq (%rax,%rdx), %rsi
movl $-1, (%rsi,%rcx,4)
movl $-1, 2044(%rax,%rdx)
incq %rbx
cmpq $512, %rbx # imm = 0x200
je .LBB0_8
.LBB0_3: # %.preheader62
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
movq %rbx, %r14
shlq $9, %r14
shlq $2, %r14
xorl %r15d, %r15d
xorl %ebp, %ebp
jmp .LBB0_4
.p2align 4, 0x90
.LBB0_6: # in Loop: Header=BB0_4 Depth=2
incl %ebp
cmpl $512, %ebp # imm = 0x200
je .LBB0_7
.LBB0_4: # Parent Loop BB0_3 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI0_0(%rip), %xmm0
movss .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
jbe .LBB0_6
# %bb.5: # in Loop: Header=BB0_4 Depth=2
movslq %r15d, %r15
movq w11(%rip), %rax
addq %r14, %rax
movl %ebp, (%rax,%r15,4)
incl %r15d
jmp .LBB0_6
.LBB0_8: # %.preheader60.preheader
xorl %ebx, %ebx
jmp .LBB0_9
.p2align 4, 0x90
.LBB0_13: # in Loop: Header=BB0_9 Depth=1
movq w12(%rip), %rax
movslq %r15d, %rcx
movq %rbx, %rdx
shlq $11, %rdx
leaq (%rax,%rdx), %rsi
movl $-1, (%rsi,%rcx,4)
movl $-1, 2044(%rax,%rdx)
incq %rbx
cmpq $512, %rbx # imm = 0x200
je .LBB0_14
.LBB0_9: # %.preheader60
# =>This Loop Header: Depth=1
# Child Loop BB0_10 Depth 2
movq %rbx, %r14
shlq $9, %r14
shlq $2, %r14
xorl %ebp, %ebp
xorl %r15d, %r15d
jmp .LBB0_10
.p2align 4, 0x90
.LBB0_12: # in Loop: Header=BB0_10 Depth=2
incl %ebp
cmpl $512, %ebp # imm = 0x200
je .LBB0_13
.LBB0_10: # Parent Loop BB0_9 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI0_0(%rip), %xmm0
movss .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
jbe .LBB0_12
# %bb.11: # in Loop: Header=BB0_10 Depth=2
movslq %r15d, %r15
movq w12(%rip), %rax
addq %r14, %rax
movl %ebp, (%rax,%r15,4)
incl %r15d
jmp .LBB0_12
.LBB0_14: # %.preheader58.preheader
movl $512, %ebx # imm = 0x200
jmp .LBB0_15
.p2align 4, 0x90
.LBB0_19: # in Loop: Header=BB0_15 Depth=1
movq w21(%rip), %rax
movslq %r14d, %rcx
movq %rbx, %rdx
shlq $11, %rdx
leaq (%rax,%rdx), %rsi
movl $-1, -1048576(%rsi,%rcx,4)
movl $-1, -1046532(%rax,%rdx)
incq %rbx
cmpq $1024, %rbx # imm = 0x400
je .LBB0_20
.LBB0_15: # %.preheader58
# =>This Loop Header: Depth=1
# Child Loop BB0_16 Depth 2
movq %rbx, %r15
shlq $9, %r15
xorl %r14d, %r14d
shlq $2, %r15
xorl %ebp, %ebp
jmp .LBB0_16
.p2align 4, 0x90
.LBB0_18: # in Loop: Header=BB0_16 Depth=2
incl %ebp
cmpl $512, %ebp # imm = 0x200
je .LBB0_19
.LBB0_16: # Parent Loop BB0_15 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI0_0(%rip), %xmm0
movss .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
jbe .LBB0_18
# %bb.17: # in Loop: Header=BB0_16 Depth=2
movslq %r14d, %r14
movq w21(%rip), %rax
addq %r15, %rax
movl %ebp, -1048576(%rax,%r14,4)
incl %r14d
jmp .LBB0_18
.LBB0_20: # %.preheader.preheader
movl $512, %ebx # imm = 0x200
jmp .LBB0_21
.p2align 4, 0x90
.LBB0_25: # in Loop: Header=BB0_21 Depth=1
movq w22(%rip), %rax
movslq %r15d, %rcx
movq %rbx, %rdx
shlq $11, %rdx
leaq (%rax,%rdx), %rsi
movl $-1, -1048576(%rsi,%rcx,4)
movl $-1, -1046532(%rax,%rdx)
incq %rbx
cmpq $1024, %rbx # imm = 0x400
je .LBB0_26
.LBB0_21: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_22 Depth 2
movq %rbx, %r14
shlq $9, %r14
xorl %ebp, %ebp
shlq $2, %r14
xorl %r15d, %r15d
jmp .LBB0_22
.p2align 4, 0x90
.LBB0_24: # in Loop: Header=BB0_22 Depth=2
incl %ebp
cmpl $512, %ebp # imm = 0x200
je .LBB0_25
.LBB0_22: # Parent Loop BB0_21 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI0_0(%rip), %xmm0
movss .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
jbe .LBB0_24
# %bb.23: # in Loop: Header=BB0_22 Depth=2
movslq %r15d, %r15
movq w22(%rip), %rax
addq %r14, %rax
movl %ebp, -1048576(%rax,%r15,4)
incl %r15d
jmp .LBB0_24
.LBB0_26:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z10initializev, .Lfunc_end0-_Z10initializev
.cfi_endproc
# -- End function
.globl _Z8finalizev # -- Begin function _Z8finalizev
.p2align 4, 0x90
.type _Z8finalizev,@function
_Z8finalizev: # @_Z8finalizev
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq w11(%rip), %rdi
callq free
movq w12(%rip), %rdi
callq free
movq w21(%rip), %rdi
callq free
movq w22(%rip), %rdi
callq free
movq z(%rip), %rdi
callq free
movq u(%rip), %rdi
callq free
movq result(%rip), %rdi
popq %rax
.cfi_def_cfa_offset 8
jmp free # TAILCALL
.Lfunc_end1:
.size _Z8finalizev, .Lfunc_end1-_Z8finalizev
.cfi_endproc
# -- End function
.globl _Z21__device_stub__KernelPKiS0_S0_S0_PfS1_S1_fi # -- Begin function _Z21__device_stub__KernelPKiS0_S0_S0_PfS1_S1_fi
.p2align 4, 0x90
.type _Z21__device_stub__KernelPKiS0_S0_S0_PfS1_S1_fi,@function
_Z21__device_stub__KernelPKiS0_S0_S0_PfS1_S1_fi: # @_Z21__device_stub__KernelPKiS0_S0_S0_PfS1_S1_fi
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movss %xmm0, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 200(%rsp), %rax
movq %rax, 176(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6KernelPKiS0_S0_S0_PfS1_S1_fi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end2:
.size _Z21__device_stub__KernelPKiS0_S0_S0_PfS1_S1_fi, .Lfunc_end2-_Z21__device_stub__KernelPKiS0_S0_S0_PfS1_S1_fi
.cfi_endproc
# -- End function
.globl _Z4loopv # -- Begin function _Z4loopv
.p2align 4, 0x90
.type _Z4loopv,@function
_Z4loopv: # @_Z4loopv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967298, %rbx # imm = 0x100000002
leaq 32(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
leaq 56(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 48(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 40(%rsp), %rdi
movl $4096000, %esi # imm = 0x3E8000
callq hipMalloc
movq 32(%rsp), %rdi
movq w11(%rip), %rsi
movl $1048576, %edx # imm = 0x100000
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq w12(%rip), %rsi
movl $1048576, %edx # imm = 0x100000
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq w21(%rip), %rsi
movl $1048576, %edx # imm = 0x100000
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq w22(%rip), %rsi
movl $1048576, %edx # imm = 0x100000
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
movq z(%rip), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq u(%rip), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
xorl %r12d, %r12d
leaq 510(%rbx), %r14
leaq 80(%rsp), %r13
leaq 72(%rsp), %rbp
leaq 176(%rsp), %r15
jmp .LBB3_1
.p2align 4, 0x90
.LBB3_3: # in Loop: Header=BB3_1 Depth=1
incl %r12d
cmpl $1000, %r12d # imm = 0x3E8
je .LBB3_4
.LBB3_1: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_3
# %bb.2: # in Loop: Header=BB3_1 Depth=1
movq 32(%rsp), %rax
movq %rax, 168(%rsp)
movq 24(%rsp), %rax
movq %rax, 160(%rsp)
movq 16(%rsp), %rax
movq %rax, 152(%rsp)
movq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq 56(%rsp), %rax
movq %rax, 136(%rsp)
movq 48(%rsp), %rax
movq %rax, 128(%rsp)
movq 40(%rsp), %rax
movq %rax, 120(%rsp)
movl $1065186280, 68(%rsp) # imm = 0x3F7D73E8
movl %r12d, 64(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 144(%rsp), %rax
movq %rax, 200(%rsp)
leaq 136(%rsp), %rax
movq %rax, 208(%rsp)
leaq 128(%rsp), %rax
movq %rax, 216(%rsp)
leaq 120(%rsp), %rax
movq %rax, 224(%rsp)
leaq 68(%rsp), %rax
movq %rax, 232(%rsp)
leaq 64(%rsp), %rax
movq %rax, 240(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
movl $_Z6KernelPKiS0_S0_S0_PfS1_S1_fi, %edi
movq %r15, %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_3
.LBB3_4:
movq result(%rip), %rdi
movq 40(%rsp), %rsi
movl $4096000, %edx # imm = 0x3E8000
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB3_6
# %bb.5:
movl $.L.str, %edi
callq puts
.LBB3_6:
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z4loopv, .Lfunc_end3-_Z4loopv
.cfi_endproc
# -- End function
.globl _Z6outputPc # -- Begin function _Z6outputPc
.p2align 4, 0x90
.type _Z6outputPc,@function
_Z6outputPc: # @_Z6outputPc
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1032, %rsp # imm = 0x408
.cfi_def_cfa_offset 1072
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rdx
movq %rsp, %rbx
movl $.L.str.1, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq sprintf
movl $.L.str.2, %esi
movq %rbx, %rdi
callq fopen
movq %rax, %rbx
xorps %xmm1, %xmm1
xorl %r12d, %r12d
xorl %r14d, %r14d
jmp .LBB4_1
.p2align 4, 0x90
.LBB4_5: # in Loop: Header=BB4_1 Depth=1
incq %r14
addq $4096, %r12 # imm = 0x1000
cmpq $1000, %r14 # imm = 0x3E8
je .LBB4_6
.LBB4_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
xorl %r15d, %r15d
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_4: # in Loop: Header=BB4_2 Depth=2
incq %r15
cmpq $1024, %r15 # imm = 0x400
je .LBB4_5
.LBB4_2: # Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
movq result(%rip), %rax
addq %r12, %rax
movss (%rax,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jbe .LBB4_4
# %bb.3: # in Loop: Header=BB4_2 Depth=2
movl $.L.str.3, %esi
movq %rbx, %rdi
movl %r14d, %edx
movl %r15d, %ecx
xorl %eax, %eax
callq fprintf
xorps %xmm1, %xmm1
jmp .LBB4_4
.LBB4_6:
movq %rbx, %rdi
addq $1032, %rsp # imm = 0x408
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end4:
.size _Z6outputPc, .Lfunc_end4-_Z6outputPc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1032, %rsp # imm = 0x408
.cfi_def_cfa_offset 1072
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
cmpl $1, %edi
jle .LBB5_8
# %bb.1:
movq 8(%rsi), %rbx
callq _Z10initializev
callq _Z4loopv
movq %rsp, %r14
movl $.L.str.1, %esi
movq %r14, %rdi
movq %rbx, %rdx
xorl %eax, %eax
callq sprintf
movl $.L.str.2, %esi
movq %r14, %rdi
callq fopen
movq %rax, %rbx
xorps %xmm1, %xmm1
xorl %r12d, %r12d
xorl %r14d, %r14d
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_6: # in Loop: Header=BB5_2 Depth=1
incq %r14
addq $4096, %r12 # imm = 0x1000
cmpq $1000, %r14 # imm = 0x3E8
je .LBB5_7
.LBB5_2: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB5_3 Depth 2
xorl %r15d, %r15d
jmp .LBB5_3
.p2align 4, 0x90
.LBB5_5: # in Loop: Header=BB5_3 Depth=2
incq %r15
cmpq $1024, %r15 # imm = 0x400
je .LBB5_6
.LBB5_3: # Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
movq result(%rip), %rax
addq %r12, %rax
movss (%rax,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jbe .LBB5_5
# %bb.4: # in Loop: Header=BB5_3 Depth=2
movl $.L.str.3, %esi
movq %rbx, %rdi
movl %r14d, %edx
movl %r15d, %ecx
xorl %eax, %eax
callq fprintf
xorps %xmm1, %xmm1
jmp .LBB5_5
.LBB5_7: # %_Z6outputPc.exit
movq %rbx, %rdi
callq fclose
movq w11(%rip), %rdi
callq free
movq w12(%rip), %rdi
callq free
movq w21(%rip), %rdi
callq free
movq w22(%rip), %rdi
callq free
movq z(%rip), %rdi
callq free
movq u(%rip), %rdi
callq free
movq result(%rip), %rdi
callq free
xorl %eax, %eax
addq $1032, %rsp # imm = 0x408
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB5_8:
.cfi_def_cfa_offset 1072
movq stderr(%rip), %rdi
movq (%rsi), %rdx
movl $.L.str.4, %esi
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6KernelPKiS0_S0_S0_PfS1_S1_fi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type z,@object # @z
.bss
.globl z
.p2align 3, 0x0
z:
.quad 0
.size z, 8
.type u,@object # @u
.globl u
.p2align 3, 0x0
u:
.quad 0
.size u, 8
.type result,@object # @result
.globl result
.p2align 3, 0x0
result:
.quad 0
.size result, 8
.type w11,@object # @w11
.globl w11
.p2align 3, 0x0
w11:
.quad 0
.size w11, 8
.type w12,@object # @w12
.globl w12
.p2align 3, 0x0
w12:
.quad 0
.size w12, 8
.type w21,@object # @w21
.globl w21
.p2align 3, 0x0
w21:
.quad 0
.size w21, 8
.type w22,@object # @w22
.globl w22
.p2align 3, 0x0
w22:
.quad 0
.size w22, 8
.type _Z6KernelPKiS0_S0_S0_PfS1_S1_fi,@object # @_Z6KernelPKiS0_S0_S0_PfS1_S1_fi
.section .rodata,"a",@progbits
.globl _Z6KernelPKiS0_S0_S0_PfS1_S1_fi
.p2align 3, 0x0
_Z6KernelPKiS0_S0_S0_PfS1_S1_fi:
.quad _Z21__device_stub__KernelPKiS0_S0_S0_PfS1_S1_fi
.size _Z6KernelPKiS0_S0_S0_PfS1_S1_fi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "error"
.size .L.str, 6
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%s.r"
.size .L.str.1, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "w"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d %d\n"
.size .L.str.3, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%s <prefix>\n"
.size .L.str.4, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6KernelPKiS0_S0_S0_PfS1_S1_fi"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__KernelPKiS0_S0_S0_PfS1_S1_fi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6KernelPKiS0_S0_S0_PfS1_S1_fi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6KernelPKiS0_S0_S0_PfS1_S1_fi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE R2, R0, R11, c[0x0][0x180] ; /* 0x0000600000027625 */
/* 0x001fca00078e020b */
/*0050*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea2000c1e1900 */
/*0060*/ S2UR UR6, SR_CTAID.X ; /* 0x00000000000679c3 */
/* 0x000e220000002500 */
/*0070*/ MOV R5, c[0x0][0x19c] ; /* 0x0000670000057a02 */
/* 0x000fca0000000f00 */
/*0080*/ IMAD R6, R5, 0x400, R0 ; /* 0x0000040005067824 */
/* 0x000fe400078e0200 */
/*0090*/ IMAD.WIDE R4, R0, R11, c[0x0][0x188] ; /* 0x0000620000047625 */
/* 0x000fc800078e020b */
/*00a0*/ IMAD.WIDE R6, R6, R11, c[0x0][0x190] ; /* 0x0000640006067625 */
/* 0x000fe200078e020b */
/*00b0*/ ISETP.NE.AND P0, PT, RZ, UR6, PT ; /* 0x00000006ff007c0c */
/* 0x001fe2000bf05270 */
/*00c0*/ STS [R0.X4], R9 ; /* 0x0000000900007388 */
/* 0x0041d80000004800 */
/*00d0*/ @!P0 BRA 0x560 ; /* 0x0000048000008947 */
/* 0x000fea0003800000 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*00f0*/ IMAD.SHL.U32 R8, R0, 0x200, RZ ; /* 0x0000020000087824 */
/* 0x000fc800078e00ff */
/*0100*/ IMAD.WIDE R10, R8, R11, c[0x0][0x170] ; /* 0x00005c00080a7625 */
/* 0x000fca00078e020b */
/*0110*/ LDG.E R14, [R10.64] ; /* 0x000000040a0e7981 */
/* 0x000ea2000c1e1900 */
/*0120*/ BSSY B0, 0x260 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*0130*/ CS2R R12, SRZ ; /* 0x00000000000c7805 */
/* 0x000fe2000001ff00 */
/*0140*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff097819 */
/* 0x001fe40000011408 */
/*0150*/ ISETP.NE.AND P0, PT, R14, -0x1, PT ; /* 0xffffffff0e00780c */
/* 0x004fda0003f05270 */
/*0160*/ @!P0 BRA 0x250 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0170*/ HFMA2.MMA R15, -RZ, RZ, 0, 0 ; /* 0x00000000ff0f7435 */
/* 0x000fe200000001ff */
/*0180*/ BSSY B1, 0x220 ; /* 0x0000009000017945 */
/* 0x000fe20003800000 */
/*0190*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fd000078e00ff */
/*01a0*/ IMAD.WIDE R12, R15.reuse, 0x4, R10 ; /* 0x000000040f0c7825 */
/* 0x040fe200078e020a */
/*01b0*/ LDS R17, [R14.X4] ; /* 0x000000000e117984 */
/* 0x0000680000004800 */
/*01c0*/ LDG.E R14, [R12.64+0x4] ; /* 0x000004040c0e7981 */
/* 0x001ea2000c1e1900 */
/*01d0*/ IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0f7810 */
/* 0x000fe20007ffe0ff */
/*01e0*/ FADD R16, R17, R16 ; /* 0x0000001011107221 */
/* 0x002fe20000000000 */
/*01f0*/ ISETP.NE.AND P0, PT, R14, -0x1, PT ; /* 0xffffffff0e00780c */
/* 0x004fda0003f05270 */
/*0200*/ @P0 BRA 0x1a0 ; /* 0xffffff9000000947 */
/* 0x000fea000383ffff */
/*0210*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0220*/ F2F.F64.F32 R10, R16 ; /* 0x00000010000a7310 */
/* 0x000e240000201800 */
/*0230*/ DADD R10, R10, R10 ; /* 0x000000000a0a7229 */
/* 0x001e0c000000000a */
/*0240*/ DMUL R12, R10, 0.0009765625 ; /* 0x3f5000000a0c7828 */
/* 0x00104c0000000000 */
/*0250*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0260*/ LDG.E R10, [R4.64+0x800] ; /* 0x00080004040a7981 */
/* 0x001ea2000c1e1900 */
/*0270*/ MOV R14, c[0x0][0x198] ; /* 0x00006600000e7a02 */
/* 0x000fca0000000f00 */
/*0280*/ FADD R14, -R14, 1 ; /* 0x3f8000000e0e7421 */
/* 0x000fcc0000000100 */
/*0290*/ F2F.F64.F32 R14, R14 ; /* 0x0000000e000e7310 */
/* 0x000fe20000201800 */
/*02a0*/ FMUL R16, R10, c[0x0][0x198] ; /* 0x000066000a107a20 */
/* 0x004fce0000400000 */
/*02b0*/ F2F.F64.F32 R10, R16 ; /* 0x00000010000a7310 */
/* 0x000e240000201800 */
/*02c0*/ DADD R10, R10, R14 ; /* 0x000000000a0a7229 */
/* 0x001e0c000000000e */
/*02d0*/ DADD R12, R10, -R12 ; /* 0x000000000a0c7229 */
/* 0x003e14000000080c */
/*02e0*/ F2F.F32.F64 R13, R12 ; /* 0x0000000c000d7310 */
/* 0x001e240000301000 */
/*02f0*/ STG.E [R4.64+0x800], R13 ; /* 0x0008000d04007986 */
/* 0x0011e8000c101904 */
/*0300*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0310*/ LDG.E R15, [R2.64+0x800] ; /* 0x00080004020f7981 */
/* 0x000ea2000c1e1900 */
/*0320*/ LEA R10, P0, R8, c[0x0][0x178], 0x2 ; /* 0x00005e00080a7a11 */
/* 0x000fc800078010ff */
/*0330*/ LEA.HI.X R11, R8, c[0x0][0x17c], R9, 0x2, P0 ; /* 0x00005f00080b7a11 */
/* 0x000fe200000f1409 */
/*0340*/ STS [R0.X4], R15 ; /* 0x0000000f00007388 */
/* 0x0041e80000004800 */
/*0350*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0360*/ LDG.E R14, [R10.64] ; /* 0x000000040a0e7981 */
/* 0x000ea2000c1e1900 */
/*0370*/ BSSY B0, 0x4b0 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*0380*/ IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; /* 0x00000000ff087424 */
/* 0x000fe200078e00ff */
/*0390*/ MOV R9, 0x80000000 ; /* 0x8000000000097802 */
/* 0x000fc40000000f00 */
/*03a0*/ ISETP.NE.AND P0, PT, R14, -0x1, PT ; /* 0xffffffff0e00780c */
/* 0x004fda0003f05270 */
/*03b0*/ @!P0 BRA 0x4a0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*03c0*/ BSSY B1, 0x470 ; /* 0x000000a000017945 */
/* 0x001fe20003800000 */
/*03d0*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e00ff */
/*03e0*/ MOV R0, RZ ; /* 0x000000ff00007202 */
/* 0x000fc60000000f00 */
/*03f0*/ IMAD.WIDE R8, R13.reuse, 0x4, R10 ; /* 0x000000040d087825 */
/* 0x040fe200078e020a */
/*0400*/ LDS R15, [R14.X4] ; /* 0x000000000e0f7984 */
/* 0x0000680000004800 */
/*0410*/ LDG.E R14, [R8.64+0x4] ; /* 0x00000404080e7981 */
/* 0x001ea2000c1e1900 */
/*0420*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x000fe20007ffe0ff */
/*0430*/ FADD R0, R15, R0 ; /* 0x000000000f007221 */
/* 0x002fe20000000000 */
/*0440*/ ISETP.NE.AND P0, PT, R14, -0x1, PT ; /* 0xffffffff0e00780c */
/* 0x004fda0003f05270 */
/*0450*/ @P0 BRA 0x3f0 ; /* 0xffffff9000000947 */
/* 0x000fea000383ffff */
/*0460*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0470*/ F2F.F64.F32 R8, R0 ; /* 0x0000000000087310 */
/* 0x000e240000201800 */
/*0480*/ DMUL R8, R8, -2 ; /* 0xc000000008087828 */
/* 0x001e0c0000000000 */
/*0490*/ DMUL R8, R8, 0.0009765625 ; /* 0x3f50000008087828 */
/* 0x001e0c0000000000 */
/*04a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*04b0*/ LDG.E R10, [R4.64+0x800] ; /* 0x00080004040a7981 */
/* 0x000ea4000c1e1900 */
/*04c0*/ F2F.F64.F32 R10, R10 ; /* 0x0000000a000a7310 */
/* 0x004e240000201800 */
/*04d0*/ DADD R8, R10, R8 ; /* 0x000000000a087229 */
/* 0x001e140000000008 */
/*04e0*/ F2F.F32.F64 R9, R8 ; /* 0x0000000800097310 */
/* 0x001e240000301000 */
/*04f0*/ STG.E [R4.64+0x800], R9 ; /* 0x0008000904007986 */
/* 0x001fe8000c101904 */
/*0500*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0510*/ LDG.E R0, [R4.64+0x800] ; /* 0x0008000404007981 */
/* 0x000ea4000c1e1900 */
/*0520*/ FMNMX R11, RZ, R0, !PT ; /* 0x00000000ff0b7209 */
/* 0x004fca0007800000 */
/*0530*/ STG.E [R2.64+0x800], R11 ; /* 0x0008000b02007986 */
/* 0x000fe8000c101904 */
/*0540*/ STG.E [R6.64+0x800], R11 ; /* 0x0008000b06007986 */
/* 0x000fe2000c101904 */
/*0550*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0560*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0570*/ IMAD.SHL.U32 R8, R0, 0x200, RZ ; /* 0x0000020000087824 */
/* 0x000fc800078e00ff */
/*0580*/ IMAD.WIDE R10, R8, R11, c[0x0][0x160] ; /* 0x00005800080a7625 */
/* 0x000fca00078e020b */
/*0590*/ LDG.E R14, [R10.64] ; /* 0x000000040a0e7981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ BSSY B0, 0x6e0 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*05b0*/ CS2R R12, SRZ ; /* 0x00000000000c7805 */
/* 0x000fe2000001ff00 */
/*05c0*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff097819 */
/* 0x001fe40000011408 */
/*05d0*/ ISETP.NE.AND P0, PT, R14, -0x1, PT ; /* 0xffffffff0e00780c */
/* 0x004fda0003f05270 */
/*05e0*/ @!P0 BRA 0x6d0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*05f0*/ BSSY B1, 0x6a0 ; /* 0x000000a000017945 */
/* 0x000fe20003800000 */
/*0600*/ MOV R15, RZ ; /* 0x000000ff000f7202 */
/* 0x000fe20000000f00 */
/*0610*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fc800078e00ff */
/*0620*/ IMAD.WIDE R12, R15.reuse, 0x4, R10 ; /* 0x000000040f0c7825 */
/* 0x040fe200078e020a */
/*0630*/ LDS R17, [R14.X4] ; /* 0x000000000e117984 */
/* 0x0000680000004800 */
/*0640*/ LDG.E R14, [R12.64+0x4] ; /* 0x000004040c0e7981 */
/* 0x001ea2000c1e1900 */
/*0650*/ IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0f7810 */
/* 0x000fe20007ffe0ff */
/*0660*/ FADD R16, R17, R16 ; /* 0x0000001011107221 */
/* 0x002fe20000000000 */
/*0670*/ ISETP.NE.AND P0, PT, R14, -0x1, PT ; /* 0xffffffff0e00780c */
/* 0x004fda0003f05270 */
/*0680*/ @P0 BRA 0x620 ; /* 0xffffff9000000947 */
/* 0x000fea000383ffff */
/*0690*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*06a0*/ F2F.F64.F32 R10, R16 ; /* 0x00000010000a7310 */
/* 0x000e240000201800 */
/*06b0*/ DADD R10, R10, R10 ; /* 0x000000000a0a7229 */
/* 0x001e0c000000000a */
/*06c0*/ DMUL R12, R10, 0.0009765625 ; /* 0x3f5000000a0c7828 */
/* 0x00104c0000000000 */
/*06d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06e0*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x001ea2000c1e1900 */
/*06f0*/ MOV R11, c[0x0][0x198] ; /* 0x00006600000b7a02 */
/* 0x000fca0000000f00 */
/*0700*/ FADD R14, -R11, 1 ; /* 0x3f8000000b0e7421 */
/* 0x000fcc0000000100 */
/*0710*/ F2F.F64.F32 R14, R14 ; /* 0x0000000e000e7310 */
/* 0x000fe20000201800 */
/*0720*/ FMUL R16, R10, c[0x0][0x198] ; /* 0x000066000a107a20 */
/* 0x004fce0000400000 */
/*0730*/ F2F.F64.F32 R10, R16 ; /* 0x00000010000a7310 */
/* 0x000e240000201800 */
/*0740*/ DADD R10, R14, R10 ; /* 0x000000000e0a7229 */
/* 0x001e0c000000000a */
/*0750*/ DADD R12, R10, -R12 ; /* 0x000000000a0c7229 */
/* 0x003e14000000080c */
/*0760*/ F2F.F32.F64 R13, R12 ; /* 0x0000000c000d7310 */
/* 0x001e240000301000 */
/*0770*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x0011e8000c101904 */
/*0780*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0790*/ LDG.E R15, [R2.64+0x800] ; /* 0x00080004020f7981 */
/* 0x000ea2000c1e1900 */
/*07a0*/ LEA R10, P0, R8, c[0x0][0x168], 0x2 ; /* 0x00005a00080a7a11 */
/* 0x000fc800078010ff */
/*07b0*/ LEA.HI.X R11, R8, c[0x0][0x16c], R9, 0x2, P0 ; /* 0x00005b00080b7a11 */
/* 0x000fe200000f1409 */
/*07c0*/ STS [R0.X4], R15 ; /* 0x0000000f00007388 */
/* 0x0041e80000004800 */
/*07d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*07e0*/ LDG.E R14, [R10.64] ; /* 0x000000040a0e7981 */
/* 0x000ea2000c1e1900 */
/*07f0*/ BSSY B0, 0x930 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*0800*/ IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; /* 0x00000000ff087424 */
/* 0x000fe200078e00ff */
/*0810*/ MOV R9, 0x80000000 ; /* 0x8000000000097802 */
/* 0x000fc40000000f00 */
/*0820*/ ISETP.NE.AND P0, PT, R14, -0x1, PT ; /* 0xffffffff0e00780c */
/* 0x004fda0003f05270 */
/*0830*/ @!P0 BRA 0x920 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0840*/ BSSY B1, 0x8f0 ; /* 0x000000a000017945 */
/* 0x001fe20003800000 */
/*0850*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e00ff */
/*0860*/ MOV R0, RZ ; /* 0x000000ff00007202 */
/* 0x000fc60000000f00 */
/*0870*/ IMAD.WIDE R8, R13.reuse, 0x4, R10 ; /* 0x000000040d087825 */
/* 0x040fe200078e020a */
/*0880*/ LDS R15, [R14.X4] ; /* 0x000000000e0f7984 */
/* 0x0000680000004800 */
/*0890*/ LDG.E R14, [R8.64+0x4] ; /* 0x00000404080e7981 */
/* 0x001ea2000c1e1900 */
/*08a0*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x000fe20007ffe0ff */
/*08b0*/ FADD R0, R15, R0 ; /* 0x000000000f007221 */
/* 0x002fe20000000000 */
/*08c0*/ ISETP.NE.AND P0, PT, R14, -0x1, PT ; /* 0xffffffff0e00780c */
/* 0x004fda0003f05270 */
/*08d0*/ @P0 BRA 0x870 ; /* 0xffffff9000000947 */
/* 0x000fea000383ffff */
/*08e0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*08f0*/ F2F.F64.F32 R8, R0 ; /* 0x0000000000087310 */
/* 0x000e240000201800 */
/*0900*/ DMUL R8, R8, -2 ; /* 0xc000000008087828 */
/* 0x001e0c0000000000 */
/*0910*/ DMUL R8, R8, 0.0009765625 ; /* 0x3f50000008087828 */
/* 0x001e0c0000000000 */
/*0920*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0930*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea4000c1e1900 */
/*0940*/ F2F.F64.F32 R10, R10 ; /* 0x0000000a000a7310 */
/* 0x004e240000201800 */
/*0950*/ DADD R8, R10, R8 ; /* 0x000000000a087229 */
/* 0x001e140000000008 */
/*0960*/ F2F.F32.F64 R9, R8 ; /* 0x0000000800097310 */
/* 0x001e240000301000 */
/*0970*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x001fe8000c101904 */
/*0980*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0990*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*09a0*/ FMNMX R11, RZ, R0, !PT ; /* 0x00000000ff0b7209 */
/* 0x004fca0007800000 */
/*09b0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe8000c101904 */
/*09c0*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x000fe2000c101904 */
/*09d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09e0*/ BRA 0x9e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6KernelPKiS0_S0_S0_PfS1_S1_fi
.globl _Z6KernelPKiS0_S0_S0_PfS1_S1_fi
.p2align 8
.type _Z6KernelPKiS0_S0_S0_PfS1_S1_fi,@function
_Z6KernelPKiS0_S0_S0_PfS1_S1_fi:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x20
s_load_b64 s[8:9], s[0:1], 0x38
v_lshlrev_b32_e32 v7, 2, v0
v_lshlrev_b32_e32 v8, 9, v0
s_cmp_lg_u32 s15, 0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v7, s[4:5]
s_waitcnt vmcnt(0)
ds_store_b32 v7, v1
s_waitcnt lgkmcnt(0)
s_cbranch_scc0 .LBB0_10
s_load_b64 s[2:3], s[0:1], 0x10
v_lshlrev_b32_e32 v1, 2, v8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s10, exec_lo
global_load_b32 v3, v1, s[2:3]
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e32 -1, v3
s_cbranch_execz .LBB0_5
v_dual_mov_b32 v4, 0 :: v_dual_lshlrev_b32 v1, 11, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s2, v1, s2
v_add_co_ci_u32_e64 v2, null, 0, s3, s2
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, v1, 4
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
.LBB0_3:
v_lshlrev_b32_e32 v5, 2, v3
global_load_b32 v3, v[1:2], off
v_add_co_u32 v1, vcc_lo, v1, 4
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
ds_load_b32 v5, v5
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v4, v4, v5
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s2, -1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s3, s2, s3
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s3
v_cvt_f64_f32_e32 v[1:2], v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[1:2], v[1:2], v[1:2]
v_ldexp_f64 v[1:2], v[1:2], -10
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s10
v_dual_mov_b32 v10, 0 :: v_dual_add_nc_u32 v9, 0x200, v0
v_sub_f32_e64 v4, 1.0, s8
s_load_b64 s[2:3], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v12, 2, v9
global_load_b32 v3, v12, s[6:7]
s_waitcnt vmcnt(0)
v_mul_f32_e32 v5, s8, v3
v_cvt_f64_f32_e32 v[3:4], v4
v_cvt_f64_f32_e32 v[5:6], v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_f64 v[3:4], v[3:4], v[5:6]
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v6, 0
v_add_f64 v[1:2], v[3:4], -v[1:2]
v_add_co_u32 v3, s10, s6, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v4, null, s7, 0, s10
v_cvt_f32_f64_e32 v1, v[1:2]
v_lshlrev_b32_e32 v2, 2, v8
global_store_b32 v12, v1, s[6:7]
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_load_b32 v1, v12, s[4:5]
s_waitcnt vmcnt(0)
ds_store_b32 v7, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
global_load_b32 v11, v2, s[2:3]
v_add_co_u32 v1, s10, s4, v12
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, null, s5, 0, s10
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e32 -1, v11
s_cbranch_execz .LBB0_9
v_lshlrev_b32_e32 v5, 11, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s2, v5, s2
v_add_co_ci_u32_e64 v6, null, 0, s3, s2
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
.LBB0_7:
v_lshlrev_b32_e32 v12, 2, v11
global_load_b32 v11, v[5:6], off
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
ds_load_b32 v12, v12
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v10, v10, v12
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s2, -1, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s3, s2, s3
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_7
s_or_b32 exec_lo, exec_lo, s3
v_cvt_f64_f32_e32 v[5:6], v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[5:6], v[5:6]
v_ldexp_f64 v[5:6], v[5:6], -10
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s10
global_load_b32 v10, v[3:4], off
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[10:11], v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[10:11], -v[5:6]
v_cvt_f32_f64_e32 v5, v[5:6]
global_store_b32 v[3:4], v5, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_max_f32_e32 v3, v3, v3
s_delay_alu instid0(VALU_DEP_1)
v_max_f32_e32 v5, 0, v3
v_lshl_add_u32 v3, s9, 10, v9
global_store_b32 v[1:2], v5, off
s_branch .LBB0_20
.LBB0_10:
s_cbranch_execz .LBB0_20
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v8
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_load_b32 v5, v1, s[2:3]
v_add_co_u32 v1, s4, s4, v7
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, null, s5, 0, s4
s_mov_b32 s4, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e32 -1, v5
s_cbranch_execz .LBB0_15
v_dual_mov_b32 v6, 0 :: v_dual_lshlrev_b32 v3, 11, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s2, v3, s2
v_add_co_ci_u32_e64 v4, null, 0, s3, s2
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_13:
v_lshlrev_b32_e32 v9, 2, v5
global_load_b32 v5, v[3:4], off
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
ds_load_b32 v9, v9
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v6, v6, v9
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s2, -1, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s3, s2, s3
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_13
s_or_b32 exec_lo, exec_lo, s3
v_cvt_f64_f32_e32 v[3:4], v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[3:4], v[3:4], v[3:4]
v_ldexp_f64 v[3:4], v[3:4], -10
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s4
v_lshlrev_b32_e32 v11, 2, v0
v_sub_f32_e64 v6, 1.0, s8
s_load_b64 s[2:3], s[0:1], 0x8
global_load_b32 v5, v11, s[6:7]
s_waitcnt vmcnt(0)
v_mul_f32_e32 v9, s8, v5
v_cvt_f64_f32_e32 v[5:6], v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[9:10], v9
v_add_f64 v[5:6], v[5:6], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_f64 v[3:4], v[5:6], -v[3:4]
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v6, 0
v_cvt_f32_f64_e32 v3, v[3:4]
v_lshlrev_b32_e32 v4, 2, v8
global_store_b32 v11, v3, s[6:7]
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_load_b32 v3, v[1:2], off offset:2048
s_waitcnt vmcnt(0)
ds_store_b32 v7, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
global_load_b32 v8, v4, s[2:3]
v_add_co_u32 v3, s4, s6, v11
v_mov_b32_e32 v7, 0
v_add_co_ci_u32_e64 v4, null, s7, 0, s4
s_mov_b32 s4, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e32 -1, v8
s_cbranch_execz .LBB0_19
v_lshlrev_b32_e32 v5, 11, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s2, v5, s2
v_add_co_ci_u32_e64 v6, null, 0, s3, s2
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
.LBB0_17:
v_lshlrev_b32_e32 v9, 2, v8
global_load_b32 v8, v[5:6], off
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
ds_load_b32 v9, v9
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v7, v7, v9
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s2, -1, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s3, s2, s3
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_17
s_or_b32 exec_lo, exec_lo, s3
v_cvt_f64_f32_e32 v[5:6], v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[5:6], v[5:6]
v_ldexp_f64 v[5:6], v[5:6], -10
.LBB0_19:
s_or_b32 exec_lo, exec_lo, s4
global_load_b32 v7, v[3:4], off
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[7:8], v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[7:8], -v[5:6]
v_cvt_f32_f64_e32 v5, v[5:6]
global_store_b32 v[3:4], v5, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_max_f32_e32 v3, v3, v3
s_delay_alu instid0(VALU_DEP_1)
v_max_f32_e32 v5, 0, v3
v_lshl_or_b32 v3, s9, 10, v0
global_store_b32 v[1:2], v5, off
.LBB0_20:
s_load_b64 s[0:1], s[0:1], 0x30
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6KernelPKiS0_S0_S0_PfS1_S1_fi
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 64
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6KernelPKiS0_S0_S0_PfS1_S1_fi, .Lfunc_end0-_Z6KernelPKiS0_S0_S0_PfS1_S1_fi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 60
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 64
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6KernelPKiS0_S0_S0_PfS1_S1_fi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6KernelPKiS0_S0_S0_PfS1_S1_fi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007f921_00000000-6_ic_shared.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10initializev
.type _Z10initializev, @function
_Z10initializev:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl $1048576, %edi
call malloc@PLT
movq %rax, w11(%rip)
movl $1048576, %edi
call malloc@PLT
movq %rax, w12(%rip)
movl $1048576, %edi
call malloc@PLT
movq %rax, w21(%rip)
movl $1048576, %edi
call malloc@PLT
movq %rax, w22(%rip)
movl $4096, %edi
call malloc@PLT
movq %rax, z(%rip)
movl $4096, %edi
call malloc@PLT
movq %rax, u(%rip)
movl $4096000, %edi
call malloc@PLT
movq %rax, result(%rip)
movl $0, %eax
movss .LC1(%rip), %xmm0
.L4:
movq z(%rip), %rdx
movl $0x00000000, (%rdx,%rax)
movq u(%rip), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $4096, %rax
jne .L4
movl $23, %edi
call srand@PLT
movl $2044, %r13d
movl $0, %r14d
jmp .L5
.L6:
addl $1, %ebx
cmpl $512, %ebx
je .L35
.L8:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC2(%rip), %xmm0
movss .LC3(%rip), %xmm1
comiss %xmm0, %xmm1
jbe .L6
leal (%r12,%rbp), %eax
cltq
movq w11(%rip), %rdx
movl %ebx, (%rdx,%rax,4)
addl $1, %ebp
jmp .L6
.L35:
leal (%r12,%rbp), %eax
cltq
movq w11(%rip), %rdx
movl $-1, (%rdx,%rax,4)
movq w11(%rip), %rax
movl $-1, (%rax,%r13)
addl $512, %r14d
addq $2048, %r13
cmpq $1050620, %r13
je .L22
.L5:
movl %r14d, %r12d
movl $0, %ebp
movl $0, %ebx
jmp .L8
.L10:
addl $1, %ebx
cmpl $512, %ebx
je .L36
.L12:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC2(%rip), %xmm0
movss .LC3(%rip), %xmm2
comiss %xmm0, %xmm2
jbe .L10
leal (%r12,%rbp), %eax
cltq
movq w12(%rip), %rdx
movl %ebx, (%rdx,%rax,4)
addl $1, %ebp
jmp .L10
.L36:
leal (%r12,%rbp), %eax
cltq
movq w12(%rip), %rdx
movl $-1, (%rdx,%rax,4)
movq w12(%rip), %rax
movl $-1, (%rax,%r13)
addl $512, %r14d
addq $2048, %r13
cmpq $1050620, %r13
je .L37
.L9:
movl %r14d, %r12d
movl $0, %ebx
movl $0, %ebp
jmp .L12
.L22:
movl $2044, %r13d
movl $0, %r14d
jmp .L9
.L14:
addl $1, %ebx
cmpl $512, %ebx
je .L38
.L16:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC2(%rip), %xmm0
movss .LC3(%rip), %xmm3
comiss %xmm0, %xmm3
jbe .L14
leal (%r12,%rbp), %eax
cltq
movq w21(%rip), %rdx
movl %ebx, (%rdx,%rax,4)
addl $1, %ebp
jmp .L14
.L38:
leal (%r12,%rbp), %eax
cltq
movq w21(%rip), %rdx
movl $-1, (%rdx,%rax,4)
movq w21(%rip), %rax
movl $-1, (%rax,%r14)
addl $512, %r13d
addq $2048, %r14
cmpl $262144, %r13d
je .L39
.L13:
movl %r13d, %r12d
movl $0, %ebp
movl $0, %ebx
jmp .L16
.L37:
movl $2044, %r14d
movl $0, %r13d
jmp .L13
.L18:
addl $1, %ebx
cmpl $512, %ebx
je .L40
.L20:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC2(%rip), %xmm0
movss .LC3(%rip), %xmm4
comiss %xmm0, %xmm4
jbe .L18
leal (%r12,%rbp), %eax
cltq
movq w22(%rip), %rdx
movl %ebx, (%rdx,%rax,4)
addl $1, %ebp
jmp .L18
.L40:
leal (%r12,%rbp), %eax
cltq
movq w22(%rip), %rdx
movl $-1, (%rdx,%rax,4)
movq w22(%rip), %rax
movl $-1, (%rax,%r14)
addl $512, %r13d
addq $2048, %r14
cmpl $262144, %r13d
je .L41
.L17:
movl %r13d, %r12d
movl $0, %ebx
movl $0, %ebp
jmp .L20
.L39:
movl $2044, %r14d
movl $0, %r13d
jmp .L17
.L41:
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z10initializev, .-_Z10initializev
.globl _Z8finalizev
.type _Z8finalizev, @function
_Z8finalizev:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq w11(%rip), %rdi
call free@PLT
movq w12(%rip), %rdi
call free@PLT
movq w21(%rip), %rdi
call free@PLT
movq w22(%rip), %rdi
call free@PLT
movq z(%rip), %rdi
call free@PLT
movq u(%rip), %rdi
call free@PLT
movq result(%rip), %rdi
call free@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z8finalizev, .-_Z8finalizev
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "%s.r"
.LC5:
.string "w"
.LC6:
.string "%d %d\n"
.text
.globl _Z6outputPc
.type _Z6outputPc, @function
_Z6outputPc:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1048, %rsp
.cfi_def_cfa_offset 1104
movq %rdi, %r8
movq %fs:40, %rax
movq %rax, 1032(%rsp)
xorl %eax, %eax
movq %rsp, %rbx
leaq .LC4(%rip), %rcx
movl $1024, %edx
movl $2, %esi
movq %rbx, %rdi
call __sprintf_chk@PLT
leaq .LC5(%rip), %rsi
movq %rbx, %rdi
call fopen@PLT
movq %rax, %r13
movl $0, %r15d
leaq .LC6(%rip), %r14
jmp .L45
.L46:
addl $1, %ebx
addq $4, %rbp
cmpl $1024, %ebx
je .L54
.L48:
movq result(%rip), %rax
movss (%rax,%rbp), %xmm1
pxor %xmm0, %xmm0
comiss %xmm0, %xmm1
jbe .L46
movl %ebx, %r8d
movl %r12d, %ecx
movq %r14, %rdx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L46
.L54:
addq $1, %r15
cmpq $1000, %r15
je .L49
.L45:
movl %r15d, %r12d
movq %r15, %rbp
salq $12, %rbp
movl $0, %ebx
jmp .L48
.L49:
movq %r13, %rdi
call fclose@PLT
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L55
addq $1048, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z6outputPc, .-_Z6outputPc
.globl _Z45__device_stub__Z6KernelPKiS0_S0_S0_PfS1_S1_fiPKiS0_S0_S0_PfS1_S1_fi
.type _Z45__device_stub__Z6KernelPKiS0_S0_S0_PfS1_S1_fiPKiS0_S0_S0_PfS1_S1_fi, @function
_Z45__device_stub__Z6KernelPKiS0_S0_S0_PfS1_S1_fiPKiS0_S0_S0_PfS1_S1_fi:
.LFB2086:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movss %xmm0, 4(%rsp)
movq 224(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 4(%rsp), %rax
movq %rax, 184(%rsp)
leaq 232(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L60
.L56:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L61
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z6KernelPKiS0_S0_S0_PfS1_S1_fi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L56
.L61:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z45__device_stub__Z6KernelPKiS0_S0_S0_PfS1_S1_fiPKiS0_S0_S0_PfS1_S1_fi, .-_Z45__device_stub__Z6KernelPKiS0_S0_S0_PfS1_S1_fiPKiS0_S0_S0_PfS1_S1_fi
.globl _Z6KernelPKiS0_S0_S0_PfS1_S1_fi
.type _Z6KernelPKiS0_S0_S0_PfS1_S1_fi, @function
_Z6KernelPKiS0_S0_S0_PfS1_S1_fi:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z45__device_stub__Z6KernelPKiS0_S0_S0_PfS1_S1_fiPKiS0_S0_S0_PfS1_S1_fi
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z6KernelPKiS0_S0_S0_PfS1_S1_fi, .-_Z6KernelPKiS0_S0_S0_PfS1_S1_fi
.section .rodata.str1.1
.LC8:
.string "error"
.text
.globl _Z4loopv
.type _Z4loopv, @function
_Z4loopv:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $96, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4096000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $1048576, %edx
movq w11(%rip), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1048576, %edx
movq w12(%rip), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1048576, %edx
movq w21(%rip), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1048576, %edx
movq w22(%rip), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq z(%rip), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq u(%rip), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $2, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %ebx
jmp .L66
.L65:
addl $1, %ebx
cmpl $1000, %ebx
je .L71
.L66:
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L65
pushq %rbx
.cfi_def_cfa_offset 120
pushq 32(%rsp)
.cfi_def_cfa_offset 128
movss .LC7(%rip), %xmm0
movq 32(%rsp), %r9
movq 24(%rsp), %r8
movq 72(%rsp), %rcx
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z45__device_stub__Z6KernelPKiS0_S0_S0_PfS1_S1_fiPKiS0_S0_S0_PfS1_S1_fi
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L65
.L71:
movl $2, %ecx
movl $4096000, %edx
movq 24(%rsp), %rsi
movq result(%rip), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L72
.L67:
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L73
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L72:
.cfi_restore_state
leaq .LC8(%rip), %rdi
call puts@PLT
jmp .L67
.L73:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z4loopv, .-_Z4loopv
.section .rodata.str1.1
.LC9:
.string "%s <prefix>\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
cmpl $1, %edi
jle .L77
movq 8(%rsi), %rbx
call _Z10initializev
call _Z4loopv
movq %rbx, %rdi
call _Z6outputPc
call _Z8finalizev
movl $0, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L77:
.cfi_restore_state
movq (%rsi), %rcx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC10:
.string "_Z6KernelPKiS0_S0_S0_PfS1_S1_fi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z6KernelPKiS0_S0_S0_PfS1_S1_fi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl w22
.bss
.align 8
.type w22, @object
.size w22, 8
w22:
.zero 8
.globl w21
.align 8
.type w21, @object
.size w21, 8
w21:
.zero 8
.globl w12
.align 8
.type w12, @object
.size w12, 8
w12:
.zero 8
.globl w11
.align 8
.type w11, @object
.size w11, 8
w11:
.zero 8
.globl result
.align 8
.type result, @object
.size result, 8
result:
.zero 8
.globl u
.align 8
.type u, @object
.size u, 8
u:
.zero 8
.globl z
.align 8
.type z, @object
.size z, 8
z:
.zero 8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 805306368
.align 4
.LC3:
.long 1056964608
.align 4
.LC7:
.long 1065186280
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ic_shared.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z10initializev
.LCPI0_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI0_1:
.long 0x3f000000 # float 0.5
.text
.globl _Z10initializev
.p2align 4, 0x90
.type _Z10initializev,@function
_Z10initializev: # @_Z10initializev
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $1048576, %edi # imm = 0x100000
callq malloc
movq %rax, w11(%rip)
movl $1048576, %edi # imm = 0x100000
callq malloc
movq %rax, w12(%rip)
movl $1048576, %edi # imm = 0x100000
callq malloc
movq %rax, w21(%rip)
movl $1048576, %edi # imm = 0x100000
callq malloc
movq %rax, w22(%rip)
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r14
movq %rax, z(%rip)
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbx
movq %rax, u(%rip)
movl $4096000, %edi # imm = 0x3E8000
callq malloc
movq %rax, result(%rip)
xorl %r15d, %r15d
movl $4096, %edx # imm = 0x1000
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%r15,4) # imm = 0x3F800000
incq %r15
cmpq $1024, %r15 # imm = 0x400
jne .LBB0_1
# %bb.2:
movl $23, %edi
callq srand
xorl %ebx, %ebx
jmp .LBB0_3
.p2align 4, 0x90
.LBB0_7: # in Loop: Header=BB0_3 Depth=1
movq w11(%rip), %rax
movslq %r15d, %rcx
movq %rbx, %rdx
shlq $11, %rdx
leaq (%rax,%rdx), %rsi
movl $-1, (%rsi,%rcx,4)
movl $-1, 2044(%rax,%rdx)
incq %rbx
cmpq $512, %rbx # imm = 0x200
je .LBB0_8
.LBB0_3: # %.preheader62
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
movq %rbx, %r14
shlq $9, %r14
shlq $2, %r14
xorl %r15d, %r15d
xorl %ebp, %ebp
jmp .LBB0_4
.p2align 4, 0x90
.LBB0_6: # in Loop: Header=BB0_4 Depth=2
incl %ebp
cmpl $512, %ebp # imm = 0x200
je .LBB0_7
.LBB0_4: # Parent Loop BB0_3 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI0_0(%rip), %xmm0
movss .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
jbe .LBB0_6
# %bb.5: # in Loop: Header=BB0_4 Depth=2
movslq %r15d, %r15
movq w11(%rip), %rax
addq %r14, %rax
movl %ebp, (%rax,%r15,4)
incl %r15d
jmp .LBB0_6
.LBB0_8: # %.preheader60.preheader
xorl %ebx, %ebx
jmp .LBB0_9
.p2align 4, 0x90
.LBB0_13: # in Loop: Header=BB0_9 Depth=1
movq w12(%rip), %rax
movslq %r15d, %rcx
movq %rbx, %rdx
shlq $11, %rdx
leaq (%rax,%rdx), %rsi
movl $-1, (%rsi,%rcx,4)
movl $-1, 2044(%rax,%rdx)
incq %rbx
cmpq $512, %rbx # imm = 0x200
je .LBB0_14
.LBB0_9: # %.preheader60
# =>This Loop Header: Depth=1
# Child Loop BB0_10 Depth 2
movq %rbx, %r14
shlq $9, %r14
shlq $2, %r14
xorl %ebp, %ebp
xorl %r15d, %r15d
jmp .LBB0_10
.p2align 4, 0x90
.LBB0_12: # in Loop: Header=BB0_10 Depth=2
incl %ebp
cmpl $512, %ebp # imm = 0x200
je .LBB0_13
.LBB0_10: # Parent Loop BB0_9 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI0_0(%rip), %xmm0
movss .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
jbe .LBB0_12
# %bb.11: # in Loop: Header=BB0_10 Depth=2
movslq %r15d, %r15
movq w12(%rip), %rax
addq %r14, %rax
movl %ebp, (%rax,%r15,4)
incl %r15d
jmp .LBB0_12
.LBB0_14: # %.preheader58.preheader
movl $512, %ebx # imm = 0x200
jmp .LBB0_15
.p2align 4, 0x90
.LBB0_19: # in Loop: Header=BB0_15 Depth=1
movq w21(%rip), %rax
movslq %r14d, %rcx
movq %rbx, %rdx
shlq $11, %rdx
leaq (%rax,%rdx), %rsi
movl $-1, -1048576(%rsi,%rcx,4)
movl $-1, -1046532(%rax,%rdx)
incq %rbx
cmpq $1024, %rbx # imm = 0x400
je .LBB0_20
.LBB0_15: # %.preheader58
# =>This Loop Header: Depth=1
# Child Loop BB0_16 Depth 2
movq %rbx, %r15
shlq $9, %r15
xorl %r14d, %r14d
shlq $2, %r15
xorl %ebp, %ebp
jmp .LBB0_16
.p2align 4, 0x90
.LBB0_18: # in Loop: Header=BB0_16 Depth=2
incl %ebp
cmpl $512, %ebp # imm = 0x200
je .LBB0_19
.LBB0_16: # Parent Loop BB0_15 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI0_0(%rip), %xmm0
movss .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
jbe .LBB0_18
# %bb.17: # in Loop: Header=BB0_16 Depth=2
movslq %r14d, %r14
movq w21(%rip), %rax
addq %r15, %rax
movl %ebp, -1048576(%rax,%r14,4)
incl %r14d
jmp .LBB0_18
.LBB0_20: # %.preheader.preheader
movl $512, %ebx # imm = 0x200
jmp .LBB0_21
.p2align 4, 0x90
.LBB0_25: # in Loop: Header=BB0_21 Depth=1
movq w22(%rip), %rax
movslq %r15d, %rcx
movq %rbx, %rdx
shlq $11, %rdx
leaq (%rax,%rdx), %rsi
movl $-1, -1048576(%rsi,%rcx,4)
movl $-1, -1046532(%rax,%rdx)
incq %rbx
cmpq $1024, %rbx # imm = 0x400
je .LBB0_26
.LBB0_21: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_22 Depth 2
movq %rbx, %r14
shlq $9, %r14
xorl %ebp, %ebp
shlq $2, %r14
xorl %r15d, %r15d
jmp .LBB0_22
.p2align 4, 0x90
.LBB0_24: # in Loop: Header=BB0_22 Depth=2
incl %ebp
cmpl $512, %ebp # imm = 0x200
je .LBB0_25
.LBB0_22: # Parent Loop BB0_21 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI0_0(%rip), %xmm0
movss .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
jbe .LBB0_24
# %bb.23: # in Loop: Header=BB0_22 Depth=2
movslq %r15d, %r15
movq w22(%rip), %rax
addq %r14, %rax
movl %ebp, -1048576(%rax,%r15,4)
incl %r15d
jmp .LBB0_24
.LBB0_26:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z10initializev, .Lfunc_end0-_Z10initializev
.cfi_endproc
# -- End function
.globl _Z8finalizev # -- Begin function _Z8finalizev
.p2align 4, 0x90
.type _Z8finalizev,@function
_Z8finalizev: # @_Z8finalizev
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq w11(%rip), %rdi
callq free
movq w12(%rip), %rdi
callq free
movq w21(%rip), %rdi
callq free
movq w22(%rip), %rdi
callq free
movq z(%rip), %rdi
callq free
movq u(%rip), %rdi
callq free
movq result(%rip), %rdi
popq %rax
.cfi_def_cfa_offset 8
jmp free # TAILCALL
.Lfunc_end1:
.size _Z8finalizev, .Lfunc_end1-_Z8finalizev
.cfi_endproc
# -- End function
.globl _Z21__device_stub__KernelPKiS0_S0_S0_PfS1_S1_fi # -- Begin function _Z21__device_stub__KernelPKiS0_S0_S0_PfS1_S1_fi
.p2align 4, 0x90
.type _Z21__device_stub__KernelPKiS0_S0_S0_PfS1_S1_fi,@function
_Z21__device_stub__KernelPKiS0_S0_S0_PfS1_S1_fi: # @_Z21__device_stub__KernelPKiS0_S0_S0_PfS1_S1_fi
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movss %xmm0, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 200(%rsp), %rax
movq %rax, 176(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6KernelPKiS0_S0_S0_PfS1_S1_fi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end2:
.size _Z21__device_stub__KernelPKiS0_S0_S0_PfS1_S1_fi, .Lfunc_end2-_Z21__device_stub__KernelPKiS0_S0_S0_PfS1_S1_fi
.cfi_endproc
# -- End function
.globl _Z4loopv # -- Begin function _Z4loopv
.p2align 4, 0x90
.type _Z4loopv,@function
_Z4loopv: # @_Z4loopv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967298, %rbx # imm = 0x100000002
leaq 32(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
leaq 56(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 48(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 40(%rsp), %rdi
movl $4096000, %esi # imm = 0x3E8000
callq hipMalloc
movq 32(%rsp), %rdi
movq w11(%rip), %rsi
movl $1048576, %edx # imm = 0x100000
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq w12(%rip), %rsi
movl $1048576, %edx # imm = 0x100000
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq w21(%rip), %rsi
movl $1048576, %edx # imm = 0x100000
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq w22(%rip), %rsi
movl $1048576, %edx # imm = 0x100000
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
movq z(%rip), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq u(%rip), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
xorl %r12d, %r12d
leaq 510(%rbx), %r14
leaq 80(%rsp), %r13
leaq 72(%rsp), %rbp
leaq 176(%rsp), %r15
jmp .LBB3_1
.p2align 4, 0x90
.LBB3_3: # in Loop: Header=BB3_1 Depth=1
incl %r12d
cmpl $1000, %r12d # imm = 0x3E8
je .LBB3_4
.LBB3_1: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_3
# %bb.2: # in Loop: Header=BB3_1 Depth=1
movq 32(%rsp), %rax
movq %rax, 168(%rsp)
movq 24(%rsp), %rax
movq %rax, 160(%rsp)
movq 16(%rsp), %rax
movq %rax, 152(%rsp)
movq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq 56(%rsp), %rax
movq %rax, 136(%rsp)
movq 48(%rsp), %rax
movq %rax, 128(%rsp)
movq 40(%rsp), %rax
movq %rax, 120(%rsp)
movl $1065186280, 68(%rsp) # imm = 0x3F7D73E8
movl %r12d, 64(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 144(%rsp), %rax
movq %rax, 200(%rsp)
leaq 136(%rsp), %rax
movq %rax, 208(%rsp)
leaq 128(%rsp), %rax
movq %rax, 216(%rsp)
leaq 120(%rsp), %rax
movq %rax, 224(%rsp)
leaq 68(%rsp), %rax
movq %rax, 232(%rsp)
leaq 64(%rsp), %rax
movq %rax, 240(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
movl $_Z6KernelPKiS0_S0_S0_PfS1_S1_fi, %edi
movq %r15, %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_3
.LBB3_4:
movq result(%rip), %rdi
movq 40(%rsp), %rsi
movl $4096000, %edx # imm = 0x3E8000
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB3_6
# %bb.5:
movl $.L.str, %edi
callq puts
.LBB3_6:
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z4loopv, .Lfunc_end3-_Z4loopv
.cfi_endproc
# -- End function
.globl _Z6outputPc # -- Begin function _Z6outputPc
.p2align 4, 0x90
.type _Z6outputPc,@function
_Z6outputPc: # @_Z6outputPc
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1032, %rsp # imm = 0x408
.cfi_def_cfa_offset 1072
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rdx
movq %rsp, %rbx
movl $.L.str.1, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq sprintf
movl $.L.str.2, %esi
movq %rbx, %rdi
callq fopen
movq %rax, %rbx
xorps %xmm1, %xmm1
xorl %r12d, %r12d
xorl %r14d, %r14d
jmp .LBB4_1
.p2align 4, 0x90
.LBB4_5: # in Loop: Header=BB4_1 Depth=1
incq %r14
addq $4096, %r12 # imm = 0x1000
cmpq $1000, %r14 # imm = 0x3E8
je .LBB4_6
.LBB4_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
xorl %r15d, %r15d
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_4: # in Loop: Header=BB4_2 Depth=2
incq %r15
cmpq $1024, %r15 # imm = 0x400
je .LBB4_5
.LBB4_2: # Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
movq result(%rip), %rax
addq %r12, %rax
movss (%rax,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jbe .LBB4_4
# %bb.3: # in Loop: Header=BB4_2 Depth=2
movl $.L.str.3, %esi
movq %rbx, %rdi
movl %r14d, %edx
movl %r15d, %ecx
xorl %eax, %eax
callq fprintf
xorps %xmm1, %xmm1
jmp .LBB4_4
.LBB4_6:
movq %rbx, %rdi
addq $1032, %rsp # imm = 0x408
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end4:
.size _Z6outputPc, .Lfunc_end4-_Z6outputPc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1032, %rsp # imm = 0x408
.cfi_def_cfa_offset 1072
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
cmpl $1, %edi
jle .LBB5_8
# %bb.1:
movq 8(%rsi), %rbx
callq _Z10initializev
callq _Z4loopv
movq %rsp, %r14
movl $.L.str.1, %esi
movq %r14, %rdi
movq %rbx, %rdx
xorl %eax, %eax
callq sprintf
movl $.L.str.2, %esi
movq %r14, %rdi
callq fopen
movq %rax, %rbx
xorps %xmm1, %xmm1
xorl %r12d, %r12d
xorl %r14d, %r14d
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_6: # in Loop: Header=BB5_2 Depth=1
incq %r14
addq $4096, %r12 # imm = 0x1000
cmpq $1000, %r14 # imm = 0x3E8
je .LBB5_7
.LBB5_2: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB5_3 Depth 2
xorl %r15d, %r15d
jmp .LBB5_3
.p2align 4, 0x90
.LBB5_5: # in Loop: Header=BB5_3 Depth=2
incq %r15
cmpq $1024, %r15 # imm = 0x400
je .LBB5_6
.LBB5_3: # Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
movq result(%rip), %rax
addq %r12, %rax
movss (%rax,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jbe .LBB5_5
# %bb.4: # in Loop: Header=BB5_3 Depth=2
movl $.L.str.3, %esi
movq %rbx, %rdi
movl %r14d, %edx
movl %r15d, %ecx
xorl %eax, %eax
callq fprintf
xorps %xmm1, %xmm1
jmp .LBB5_5
.LBB5_7: # %_Z6outputPc.exit
movq %rbx, %rdi
callq fclose
movq w11(%rip), %rdi
callq free
movq w12(%rip), %rdi
callq free
movq w21(%rip), %rdi
callq free
movq w22(%rip), %rdi
callq free
movq z(%rip), %rdi
callq free
movq u(%rip), %rdi
callq free
movq result(%rip), %rdi
callq free
xorl %eax, %eax
addq $1032, %rsp # imm = 0x408
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB5_8:
.cfi_def_cfa_offset 1072
movq stderr(%rip), %rdi
movq (%rsi), %rdx
movl $.L.str.4, %esi
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6KernelPKiS0_S0_S0_PfS1_S1_fi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type z,@object # @z
.bss
.globl z
.p2align 3, 0x0
z:
.quad 0
.size z, 8
.type u,@object # @u
.globl u
.p2align 3, 0x0
u:
.quad 0
.size u, 8
.type result,@object # @result
.globl result
.p2align 3, 0x0
result:
.quad 0
.size result, 8
.type w11,@object # @w11
.globl w11
.p2align 3, 0x0
w11:
.quad 0
.size w11, 8
.type w12,@object # @w12
.globl w12
.p2align 3, 0x0
w12:
.quad 0
.size w12, 8
.type w21,@object # @w21
.globl w21
.p2align 3, 0x0
w21:
.quad 0
.size w21, 8
.type w22,@object # @w22
.globl w22
.p2align 3, 0x0
w22:
.quad 0
.size w22, 8
.type _Z6KernelPKiS0_S0_S0_PfS1_S1_fi,@object # @_Z6KernelPKiS0_S0_S0_PfS1_S1_fi
.section .rodata,"a",@progbits
.globl _Z6KernelPKiS0_S0_S0_PfS1_S1_fi
.p2align 3, 0x0
_Z6KernelPKiS0_S0_S0_PfS1_S1_fi:
.quad _Z21__device_stub__KernelPKiS0_S0_S0_PfS1_S1_fi
.size _Z6KernelPKiS0_S0_S0_PfS1_S1_fi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "error"
.size .L.str, 6
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%s.r"
.size .L.str.1, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "w"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d %d\n"
.size .L.str.3, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%s <prefix>\n"
.size .L.str.4, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6KernelPKiS0_S0_S0_PfS1_S1_fi"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__KernelPKiS0_S0_S0_PfS1_S1_fi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6KernelPKiS0_S0_S0_PfS1_S1_fi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void ShortestPath2(float *Arr1,float *Arr2,float *recv,int N,int rows, int k,int rank,int owner){
int col=blockIdx.x * blockDim.x + threadIdx.x;
int row=blockIdx.y * blockDim.y + threadIdx.y;
int index=row*N+col;
int index_ik = row*N+k;
if(Arr1[index]>(Arr1[index_ik]+recv[col])){
Arr2[index]=Arr1[index_ik]+recv[col];
}
__syncthreads();
} | code for sm_80
Function : _Z13ShortestPath2PfS_S_iiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R4, c[0x0][0x178] ; /* 0x00005e0000047a02 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0060*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0070*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0080*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fc800078e0202 */
/*0090*/ IMAD R4, R3, R4, c[0x0][0x180] ; /* 0x0000600003047624 */
/* 0x000fe400078e0204 */
/*00a0*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fe400078e0205 */
/*00b0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0209 */
/*00c0*/ IMAD.WIDE R6, R0, R9.reuse, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x080fe400078e0209 */
/*00d0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*00e0*/ IMAD R0, R3, c[0x0][0x178], R0 ; /* 0x00005e0003007a24 */
/* 0x000fe400078e0200 */
/*00f0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1900 */
/*0100*/ IMAD.WIDE R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0209 */
/*0110*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ee2000c1e1900 */
/*0120*/ SHF.R.S32.HI R9, RZ, 0x1f, R0 ; /* 0x0000001fff097819 */
/* 0x000fe20000011400 */
/*0130*/ FADD R11, R6, R5 ; /* 0x00000005060b7221 */
/* 0x004fca0000000000 */
/*0140*/ FSETP.GT.AND P0, PT, R2, R11, PT ; /* 0x0000000b0200720b */
/* 0x008fda0003f04000 */
/*0150*/ @P0 LEA R8, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000080a11 */
/* 0x000fc800078210ff */
/*0160*/ @P0 LEA.HI.X R9, R0, c[0x0][0x16c], R9, 0x2, P1 ; /* 0x00005b0000090a11 */
/* 0x000fca00008f1409 */
/*0170*/ @P0 STG.E [R8.64], R11 ; /* 0x0000000b08000986 */
/* 0x000fe8000c101904 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void ShortestPath2(float *Arr1,float *Arr2,float *recv,int N,int rows, int k,int rank,int owner){
int col=blockIdx.x * blockDim.x + threadIdx.x;
int row=blockIdx.y * blockDim.y + threadIdx.y;
int index=row*N+col;
int index_ik = row*N+k;
if(Arr1[index]>(Arr1[index_ik]+recv[col])){
Arr2[index]=Arr1[index_ik]+recv[col];
}
__syncthreads();
} | .file "tmpxft_00041546_00000000-6_ShortestPath2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z13ShortestPath2PfS_S_iiiiiPfS_S_iiiii
.type _Z42__device_stub__Z13ShortestPath2PfS_S_iiiiiPfS_S_iiiii, @function
_Z42__device_stub__Z13ShortestPath2PfS_S_iiiiiPfS_S_iiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13ShortestPath2PfS_S_iiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z13ShortestPath2PfS_S_iiiiiPfS_S_iiiii, .-_Z42__device_stub__Z13ShortestPath2PfS_S_iiiiiPfS_S_iiiii
.globl _Z13ShortestPath2PfS_S_iiiii
.type _Z13ShortestPath2PfS_S_iiiii, @function
_Z13ShortestPath2PfS_S_iiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z42__device_stub__Z13ShortestPath2PfS_S_iiiiiPfS_S_iiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13ShortestPath2PfS_S_iiiii, .-_Z13ShortestPath2PfS_S_iiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13ShortestPath2PfS_S_iiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13ShortestPath2PfS_S_iiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void ShortestPath2(float *Arr1,float *Arr2,float *recv,int N,int rows, int k,int rank,int owner){
int col=blockIdx.x * blockDim.x + threadIdx.x;
int row=blockIdx.y * blockDim.y + threadIdx.y;
int index=row*N+col;
int index_ik = row*N+k;
if(Arr1[index]>(Arr1[index_ik]+recv[col])){
Arr2[index]=Arr1[index_ik]+recv[col];
}
__syncthreads();
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ShortestPath2(float *Arr1,float *Arr2,float *recv,int N,int rows, int k,int rank,int owner){
int col=blockIdx.x * blockDim.x + threadIdx.x;
int row=blockIdx.y * blockDim.y + threadIdx.y;
int index=row*N+col;
int index_ik = row*N+k;
if(Arr1[index]>(Arr1[index_ik]+recv[col])){
Arr2[index]=Arr1[index_ik]+recv[col];
}
__syncthreads();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ShortestPath2(float *Arr1,float *Arr2,float *recv,int N,int rows, int k,int rank,int owner){
int col=blockIdx.x * blockDim.x + threadIdx.x;
int row=blockIdx.y * blockDim.y + threadIdx.y;
int index=row*N+col;
int index_ik = row*N+k;
if(Arr1[index]>(Arr1[index_ik]+recv[col])){
Arr2[index]=Arr1[index_ik]+recv[col];
}
__syncthreads();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13ShortestPath2PfS_S_iiiii
.globl _Z13ShortestPath2PfS_S_iiiii
.p2align 8
.type _Z13ShortestPath2PfS_S_iiiii,@function
_Z13ShortestPath2PfS_S_iiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
s_load_b32 s6, s[0:1], 0x20
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
v_mad_u64_u32 v[3:4], null, s14, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mul_lo_u32 v1, v2, s3
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x0
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v5, s6, v1
v_add_nc_u32_e32 v0, v1, v3
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v6, 31, v5
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[5:6]
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v1, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[6:7], off
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(1)
v_add_f32_e32 v2, v4, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_f32_e32 v3, v2
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13ShortestPath2PfS_S_iiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13ShortestPath2PfS_S_iiiii, .Lfunc_end0-_Z13ShortestPath2PfS_S_iiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13ShortestPath2PfS_S_iiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13ShortestPath2PfS_S_iiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ShortestPath2(float *Arr1,float *Arr2,float *recv,int N,int rows, int k,int rank,int owner){
int col=blockIdx.x * blockDim.x + threadIdx.x;
int row=blockIdx.y * blockDim.y + threadIdx.y;
int index=row*N+col;
int index_ik = row*N+k;
if(Arr1[index]>(Arr1[index_ik]+recv[col])){
Arr2[index]=Arr1[index_ik]+recv[col];
}
__syncthreads();
} | .text
.file "ShortestPath2.hip"
.globl _Z28__device_stub__ShortestPath2PfS_S_iiiii # -- Begin function _Z28__device_stub__ShortestPath2PfS_S_iiiii
.p2align 4, 0x90
.type _Z28__device_stub__ShortestPath2PfS_S_iiiii,@function
_Z28__device_stub__ShortestPath2PfS_S_iiiii: # @_Z28__device_stub__ShortestPath2PfS_S_iiiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13ShortestPath2PfS_S_iiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z28__device_stub__ShortestPath2PfS_S_iiiii, .Lfunc_end0-_Z28__device_stub__ShortestPath2PfS_S_iiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13ShortestPath2PfS_S_iiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13ShortestPath2PfS_S_iiiii,@object # @_Z13ShortestPath2PfS_S_iiiii
.section .rodata,"a",@progbits
.globl _Z13ShortestPath2PfS_S_iiiii
.p2align 3, 0x0
_Z13ShortestPath2PfS_S_iiiii:
.quad _Z28__device_stub__ShortestPath2PfS_S_iiiii
.size _Z13ShortestPath2PfS_S_iiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13ShortestPath2PfS_S_iiiii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__ShortestPath2PfS_S_iiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13ShortestPath2PfS_S_iiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13ShortestPath2PfS_S_iiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R4, c[0x0][0x178] ; /* 0x00005e0000047a02 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0060*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0070*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0080*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fc800078e0202 */
/*0090*/ IMAD R4, R3, R4, c[0x0][0x180] ; /* 0x0000600003047624 */
/* 0x000fe400078e0204 */
/*00a0*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fe400078e0205 */
/*00b0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0209 */
/*00c0*/ IMAD.WIDE R6, R0, R9.reuse, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x080fe400078e0209 */
/*00d0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*00e0*/ IMAD R0, R3, c[0x0][0x178], R0 ; /* 0x00005e0003007a24 */
/* 0x000fe400078e0200 */
/*00f0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1900 */
/*0100*/ IMAD.WIDE R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0209 */
/*0110*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ee2000c1e1900 */
/*0120*/ SHF.R.S32.HI R9, RZ, 0x1f, R0 ; /* 0x0000001fff097819 */
/* 0x000fe20000011400 */
/*0130*/ FADD R11, R6, R5 ; /* 0x00000005060b7221 */
/* 0x004fca0000000000 */
/*0140*/ FSETP.GT.AND P0, PT, R2, R11, PT ; /* 0x0000000b0200720b */
/* 0x008fda0003f04000 */
/*0150*/ @P0 LEA R8, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000080a11 */
/* 0x000fc800078210ff */
/*0160*/ @P0 LEA.HI.X R9, R0, c[0x0][0x16c], R9, 0x2, P1 ; /* 0x00005b0000090a11 */
/* 0x000fca00008f1409 */
/*0170*/ @P0 STG.E [R8.64], R11 ; /* 0x0000000b08000986 */
/* 0x000fe8000c101904 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13ShortestPath2PfS_S_iiiii
.globl _Z13ShortestPath2PfS_S_iiiii
.p2align 8
.type _Z13ShortestPath2PfS_S_iiiii,@function
_Z13ShortestPath2PfS_S_iiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
s_load_b32 s6, s[0:1], 0x20
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
v_mad_u64_u32 v[3:4], null, s14, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mul_lo_u32 v1, v2, s3
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x0
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v5, s6, v1
v_add_nc_u32_e32 v0, v1, v3
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v6, 31, v5
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[5:6]
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v1, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[6:7], off
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(1)
v_add_f32_e32 v2, v4, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_f32_e32 v3, v2
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13ShortestPath2PfS_S_iiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13ShortestPath2PfS_S_iiiii, .Lfunc_end0-_Z13ShortestPath2PfS_S_iiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13ShortestPath2PfS_S_iiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13ShortestPath2PfS_S_iiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00041546_00000000-6_ShortestPath2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z13ShortestPath2PfS_S_iiiiiPfS_S_iiiii
.type _Z42__device_stub__Z13ShortestPath2PfS_S_iiiiiPfS_S_iiiii, @function
_Z42__device_stub__Z13ShortestPath2PfS_S_iiiiiPfS_S_iiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13ShortestPath2PfS_S_iiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z13ShortestPath2PfS_S_iiiiiPfS_S_iiiii, .-_Z42__device_stub__Z13ShortestPath2PfS_S_iiiiiPfS_S_iiiii
.globl _Z13ShortestPath2PfS_S_iiiii
.type _Z13ShortestPath2PfS_S_iiiii, @function
_Z13ShortestPath2PfS_S_iiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z42__device_stub__Z13ShortestPath2PfS_S_iiiiiPfS_S_iiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13ShortestPath2PfS_S_iiiii, .-_Z13ShortestPath2PfS_S_iiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13ShortestPath2PfS_S_iiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13ShortestPath2PfS_S_iiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ShortestPath2.hip"
.globl _Z28__device_stub__ShortestPath2PfS_S_iiiii # -- Begin function _Z28__device_stub__ShortestPath2PfS_S_iiiii
.p2align 4, 0x90
.type _Z28__device_stub__ShortestPath2PfS_S_iiiii,@function
_Z28__device_stub__ShortestPath2PfS_S_iiiii: # @_Z28__device_stub__ShortestPath2PfS_S_iiiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13ShortestPath2PfS_S_iiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z28__device_stub__ShortestPath2PfS_S_iiiii, .Lfunc_end0-_Z28__device_stub__ShortestPath2PfS_S_iiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13ShortestPath2PfS_S_iiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13ShortestPath2PfS_S_iiiii,@object # @_Z13ShortestPath2PfS_S_iiiii
.section .rodata,"a",@progbits
.globl _Z13ShortestPath2PfS_S_iiiii
.p2align 3, 0x0
_Z13ShortestPath2PfS_S_iiiii:
.quad _Z28__device_stub__ShortestPath2PfS_S_iiiii
.size _Z13ShortestPath2PfS_S_iiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13ShortestPath2PfS_S_iiiii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__ShortestPath2PfS_S_iiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13ShortestPath2PfS_S_iiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //#define _USE_MATH_DEFINES
//
//#include "cuda_runtime.h"
//#include "device_launch_parameters.h"
//
//#include <math.h>
//#include <stdio.h>
//#include <conio.h>
//#include <iostream>
//#include <fstream>
//#include <ctime>
//#include <string>
//
//void GetInputAndCalcInfluence();
//void GetInputAndCalcDistr();
//void CreateMatrix(double* Matrixij, double* BECoords, double* BE, int BeNumber, int BEInfoSize);
//void CreateNodes(double* Matrixij, int size, double* Coeffs, int BeNumber, double* BE, int BEInfoSize);
//
//// cuda function create influence matrix with pointer 'Matrixij' for boundary condition in points with coords 'BECoords',
//// but boundary elements are in coords 'BE'
//__global__ void MatrixCreation(double* Matrixij, double* BECoords, double* BE)
//{
// int i = blockIdx.x;
// int j0 = threadIdx.x;
// int index = i * blockDim.x + j0;
//
// // coords of calculation point which is be coords with shift to avoid undeterminated state
// double x = BECoords[i];
// double y = BECoords[i + 1];
//
// if (j0 % 2)
// {
// int j = (j0 - 1) / 2 * (19 + 7) + 19;
// Matrixij[index] = (-6 * atanf((-BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) / ((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]))) * ((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6])) *
// (3 * powf(BE[j + 5], 2) + powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) - 3 * powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) +
// (BE[j + 5] - (-BE[j + 3] + x) * cosf(BE[j + 6]) - (-BE[j + 4] + y) * sinf(BE[j + 6])) * (-16 * powf(BE[j + 5], 2) - 6 * powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) +
// 5 * BE[j + 5] * ((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) + 11 * powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) -
// 3 * logf(powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) + powf(-BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) *
// (powf(BE[j + 5], 3) + 3 * powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) * ((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) -
// powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 3) + 3 * powf(BE[j + 5], 2) * (-BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])))) / (36. * powf(BE[j + 5], 2) * M_PI) -
// (-6 * atanf((BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) / ((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]))) * ((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6])) *
// (3 * powf(BE[j + 5], 2) + powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) - 3 * powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) +
// (-BE[j + 5] - (-BE[j + 3] + x) * cosf(BE[j + 6]) - (-BE[j + 4] + y) * sinf(BE[j + 6])) * (-16 * powf(BE[j + 5], 2) - 6 * powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) -
// 5 * BE[j + 5] * ((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) + 11 * powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) -
// 3 * logf(powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) + powf(BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) *
// (-powf(BE[j + 5], 3) + 3 * powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) * ((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) -
// powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 3) + 3 * powf(BE[j + 5], 2) * (BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])))) / (36. * powf(BE[j + 5], 2) * M_PI);
// }
// else
// {
// int j = j0 / 2 * (19 + 7);
// Matrixij[index] = -(12 * atanf((BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) / ((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]))) * ((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9])) *
// (powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - 3 * BE[j + 10] * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) -
// 3 * powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) +
// (BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) * (9 * BE[j + 10] * (-BE[j + 10] + 3 * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]))) +
// 2 * (2 * powf(BE[j + 10], 2) - 6 * powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - 5 * BE[j + 10] * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) +
// 11 * powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2))) +
// logf(powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) + powf(BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) *
// (9 * BE[j + 10] * (powf(BE[j + 10], 2) + powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) +
// 6 * (-powf(BE[j + 10], 3) + 3 * powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) -
// powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 3)))) / (144. * powf(BE[j + 10], 2) * M_PI) +
// (12 * atanf((-BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) / ((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]))) * ((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9])) *
// (powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - 3 * BE[j + 10] * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) -
// 3 * powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) +
// (-BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) * (9 * BE[j + 10] * (BE[j + 10] + 3 * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]))) +
// 2 * (2 * powf(BE[j + 10], 2) - 6 * powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) + 5 * BE[j + 10] * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) +
// 11 * powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2))) +
// logf(powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) + powf(-BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) *
// (9 * BE[j + 10] * (powf(BE[j + 10], 2) + powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) +
// 6 * (powf(BE[j + 10], 3) + 3 * powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) -
// powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 3)))) / (144. * powf(BE[j + 10], 2) * M_PI) -
// (-12 * atanf((-BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) / ((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]))) *
// ((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17])) * (powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) +
// 3 * BE[j + 18] * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) - 3 * powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) +
// (-BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) * (9 * BE[j + 18] * (BE[j + 18] + 3 * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]))) -
// 2 * (2 * powf(BE[j + 18], 2) - 6 * powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) + 5 * BE[j + 18] * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) +
// 11 * powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2))) +
// logf(powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) + powf(-BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) *
// (9 * BE[j + 18] * (powf(BE[j + 18], 2) + powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) - powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) +
// 6 * (-powf(BE[j + 18], 3) - 3 * powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) +
// powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 3)))) / (144. * powf(BE[j + 18], 2) * M_PI) +
// (-12 * atanf((BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) / ((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]))) *
// ((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17])) * (powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) +
// 3 * BE[j + 18] * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) - 3 * powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) +
// (BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) * (9 * BE[j + 18] * (-BE[j + 18] + 3 * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]))) -
// 2 * (2 * powf(BE[j + 18], 2) - 6 * powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) - 5 * BE[j + 18] * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) +
// 11 * powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2))) +
// logf(powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) + powf(BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) *
// (9 * BE[j + 18] * (powf(BE[j + 18], 2) + powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) - powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) +
// 6 * (powf(BE[j + 18], 3) - 3 * powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) +
// powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 3)))) / (144. * powf(BE[j + 18], 2) * M_PI);
// }
//}
//
//// cuda function calculate one term for one be coord and add it to value belong to be coord
//__global__ void CalculateNodes(double* Matrixij, double* Coeff, double* BE)
//{
// int i = blockIdx.x; // index by x axis
// int j0 = blockIdx.y; // index by be element
// int k = threadIdx.x; // index by y axis
//
// int index = (i * blockDim.x + k) * 3;
//
// double x = Matrixij[index];
// double y = Matrixij[index + 1];
//
// if (j0 % 2) {
// int j = (j0 - 1) / 2 * (19 + 7) + 19;
// double increment = Coeff[j0] * ((-6 * atanf((-BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) / ((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]))) * ((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6])) *
// (3 * powf(BE[j + 5], 2) + powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) - 3 * powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) +
// (BE[j + 5] - (-BE[j + 3] + x) * cosf(BE[j + 6]) - (-BE[j + 4] + y) * sinf(BE[j + 6])) * (-16 * powf(BE[j + 5], 2) - 6 * powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) +
// 5 * BE[j + 5] * ((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) + 11 * powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) -
// 3 * logf(powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) + powf(-BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) *
// (powf(BE[j + 5], 3) + 3 * powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) * ((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) -
// powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 3) + 3 * powf(BE[j + 5], 2) * (-BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])))) / (36. * powf(BE[j + 5], 2) * M_PI) -
// (-6 * atanf((BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) / ((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]))) * ((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6])) *
// (3 * powf(BE[j + 5], 2) + powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) - 3 * powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) +
// (-BE[j + 5] - (-BE[j + 3] + x) * cosf(BE[j + 6]) - (-BE[j + 4] + y) * sinf(BE[j + 6])) * (-16 * powf(BE[j + 5], 2) - 6 * powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) -
// 5 * BE[j + 5] * ((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) + 11 * powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) -
// 3 * logf(powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) + powf(BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) *
// (-powf(BE[j + 5], 3) + 3 * powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) * ((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) -
// powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 3) + 3 * powf(BE[j + 5], 2) * (BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])))) / (36. * powf(BE[j + 5], 2) * M_PI));
// atomicAdd(&(Matrixij[index + 2]), increment);
// }
// else {
// int j = j0 / 2 * (19 + 7);
// double increment = Coeff[j0] * (-(12 * atanf((BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) / ((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]))) * ((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9])) *
// (powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - 3 * BE[j + 10] * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) -
// 3 * powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) +
// (BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) * (9 * BE[j + 10] * (-BE[j + 10] + 3 * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]))) +
// 2 * (2 * powf(BE[j + 10], 2) - 6 * powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - 5 * BE[j + 10] * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) +
// 11 * powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2))) +
// logf(powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) + powf(BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) *
// (9 * BE[j + 10] * (powf(BE[j + 10], 2) + powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) +
// 6 * (-powf(BE[j + 10], 3) + 3 * powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) -
// powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 3)))) / (144. * powf(BE[j + 10], 2) * M_PI) +
// (12 * atanf((-BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) / ((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]))) * ((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9])) *
// (powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - 3 * BE[j + 10] * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) -
// 3 * powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) +
// (-BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) * (9 * BE[j + 10] * (BE[j + 10] + 3 * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]))) +
// 2 * (2 * powf(BE[j + 10], 2) - 6 * powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) + 5 * BE[j + 10] * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) +
// 11 * powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2))) +
// logf(powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) + powf(-BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) *
// (9 * BE[j + 10] * (powf(BE[j + 10], 2) + powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) +
// 6 * (powf(BE[j + 10], 3) + 3 * powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) -
// powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 3)))) / (144. * powf(BE[j + 10], 2) * M_PI) -
// (-12 * atanf((-BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) / ((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]))) *
// ((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17])) * (powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) +
// 3 * BE[j + 18] * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) - 3 * powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) +
// (-BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) * (9 * BE[j + 18] * (BE[j + 18] + 3 * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]))) -
// 2 * (2 * powf(BE[j + 18], 2) - 6 * powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) + 5 * BE[j + 18] * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) +
// 11 * powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2))) +
// logf(powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) + powf(-BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) *
// (9 * BE[j + 18] * (powf(BE[j + 18], 2) + powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) - powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) +
// 6 * (-powf(BE[j + 18], 3) - 3 * powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) +
// powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 3)))) / (144. * powf(BE[j + 18], 2) * M_PI) +
// (-12 * atanf((BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) / ((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]))) *
// ((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17])) * (powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) +
// 3 * BE[j + 18] * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) - 3 * powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) +
// (BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) * (9 * BE[j + 18] * (-BE[j + 18] + 3 * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]))) -
// 2 * (2 * powf(BE[j + 18], 2) - 6 * powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) - 5 * BE[j + 18] * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) +
// 11 * powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2))) +
// logf(powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) + powf(BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) *
// (9 * BE[j + 18] * (powf(BE[j + 18], 2) + powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) - powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) +
// 6 * (powf(BE[j + 18], 3) - 3 * powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) +
// powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 3)))) / (144. * powf(BE[j + 18], 2) * M_PI));
// atomicAdd(&(Matrixij[index + 2]), increment);
// }
//}
//
//// function using CUDA function "MatrixCreation" create influence matrix by pointer Matrixij[size*size]
//void CreateMatrix(double* Matrixij, double* BECoords, double* BE, int BeNumber, int BEInfoSize)
//{
// double* dev_a, * dev_b, * dev_c;
//
// cudaSetDevice(0);
//
// cudaMalloc((void**)&dev_a, BeNumber * BeNumber * sizeof(double));
// cudaMalloc((void**)&dev_b, 2 * BeNumber * sizeof(double));
// cudaMalloc((void**)&dev_c, BEInfoSize * sizeof(double));
// cudaMemcpy(dev_a, Matrixij, BeNumber * BeNumber * sizeof(double), cudaMemcpyHostToDevice);
// cudaMemcpy(dev_b, BECoords, BeNumber * 2 * sizeof(double), cudaMemcpyHostToDevice);
// cudaMemcpy(dev_c, BE, BEInfoSize * sizeof(double), cudaMemcpyHostToDevice);
//
// dim3 blockSize = dim3(BeNumber, 1, 1);
// dim3 gridSize = dim3(BeNumber, 1, 1);
//
// MatrixCreation << <gridSize, blockSize >> > (dev_a, dev_b, dev_c);
//
// cudaEvent_t syncEvent;
// cudaEventCreate(&syncEvent);
// cudaEventRecord(syncEvent, 0);
// cudaEventSynchronize(syncEvent);
//
// cudaMemcpy(Matrixij, dev_a, BeNumber * BeNumber * sizeof(double), cudaMemcpyDeviceToHost);
//}
//
//void CreateNodes(double* Matrixij, int size, double* Coeffs, int BeNumber, double* BE, int BEInfoSize)
//{
// double* dev_a, * dev_b, * dev_c;
//
// cudaSetDevice(0);
//
// cudaMalloc((void**)&dev_a, 3 * size * size * sizeof(double));
// cudaMalloc((void**)&dev_b, BeNumber * sizeof(double));
// cudaMalloc((void**)&dev_c, BEInfoSize * sizeof(double));
// cudaMemcpy(dev_a, Matrixij, 3 * size * size * sizeof(double), cudaMemcpyHostToDevice);
// cudaMemcpy(dev_b, Coeffs, BeNumber * sizeof(double), cudaMemcpyHostToDevice);
// cudaMemcpy(dev_c, BE, BEInfoSize * sizeof(double), cudaMemcpyHostToDevice);
//
// dim3 blockSize = dim3(size, 1, 1);
// dim3 gridSize = dim3(size, BeNumber, 1);
//
// CalculateNodes << < gridSize, blockSize >> > (dev_a, dev_b, dev_c);
//
// cudaEvent_t syncEvent;
// cudaEventCreate(&syncEvent);
// cudaEventRecord(syncEvent, 0);
// cudaEventSynchronize(syncEvent);
//
// cudaMemcpy(Matrixij, dev_a, 3 * size * size * sizeof(double), cudaMemcpyDeviceToHost);
//}
//
//void GetInputAndCalcInfluence()
//{
// double* Coords, * BE;
// double* Matrixij;
//
// int bediscr_array[] = { 5,10,15,20,25,30,35 };
// string input_file_name;
// string output_file_name;
//
// for (int i = 0; i < 7; i++)
// {
// int bediscr = bediscr_array[i];
// int CoordsNumber, BEInfoSize;
//
// input_file_name = "D:/Docs/article_03_20/data/shifted_coords" + to_string(bediscr) + ".txt";
// ifstream in;
// in.open(input_file_name);
//
// in >> CoordsNumber;
// Coords = new double[CoordsNumber];
//
// for (int i = 0; i < CoordsNumber; i++)
// in >> Coords[i];
//
// in.close();
//
// input_file_name = "D:/Docs/article_03_20/data/beinfo" + to_string(bediscr) + ".txt";
// in.open(input_file_name);
//
// in >> BEInfoSize;
// BE = new double[BEInfoSize];
//
// for (int i = 0; i < BEInfoSize; i++)
// in >> BE[i];
//
// in.close();
//
// int benumb = CoordsNumber / 2;
//
// Matrixij = new double[benumb * benumb];
//
// unsigned int start_time;
// unsigned int end_time;
// unsigned int search_time = 0;
//
// /////////////// CUDA method //////////////////////////
// CreateMatrix(Matrixij, Coords, BE, benumb, BEInfoSize);
// start_time = clock();
// CreateMatrix(Matrixij, Coords, BE, benumb, BEInfoSize);
// end_time = clock();
// search_time = end_time - start_time;
//
// output_file_name = "D:/Docs/article_03_20/CUDA_output/matr" + to_string(bediscr) + ".txt";
// ofstream out;
// out.open(output_file_name);
//
// for (int i = 0; i < benumb; i++)
// for (int j = 0; j < benumb; j++)
// out << Matrixij[i * benumb + j] << '\n';
// out << search_time;
// out.close();
//
// /////////////// sequential method ////////////////////
// start_time = clock();
// MatrixCreationSeq(Matrixij, Coords, BE, benumb);
// end_time = clock();
// search_time = end_time - start_time;
//
// output_file_name = "D:/Docs/article_03_20/SEQ_output/matr" + to_string(bediscr) + ".txt";
// out.open(output_file_name);
//
// for (int i = 0; i < benumb; i++)
// for (int j = 0; j < benumb; j++)
// out << Matrixij[i * benumb + j] << '\n';
// out << search_time;
// out.close();
//
// ///////////////////////////////////////////////////////
//
// delete(Matrixij);
// delete(BE);
// delete(Coords);
// }
//}
//
//void GetInputAndCalcDistr()
//{
// int bediscr_array[] = { 5,10,15,20,25,30,35 };
// int areadiscr_array[] = { 10, 20, 30, 40, 50 };
// double* BE, * Coefs;
// int CoefsNumb, BEInfoSize;
// string input_file_name;
// string output_file_name;
// int bediscr, areadiscr;
//
// for (int k = 0; k < 7; k++)
// {
// bediscr = bediscr_array[k];
// input_file_name = "D:/Docs/article_03_20/data/coefs" + to_string(bediscr) + ".txt";
// ifstream in;
// in.open(input_file_name);
//
// in >> CoefsNumb;
// Coefs = new double[CoefsNumb];
//
// for (int i = 0; i < CoefsNumb; i++)
// in >> Coefs[i];
//
// in.close();
//
// input_file_name = "D:/Docs/article_03_20/data/beinfo" + to_string(bediscr) + ".txt";
// in.open(input_file_name);
//
// in >> BEInfoSize;
// BE = new double[BEInfoSize];
//
// for (int i = 0; i < BEInfoSize; i++)
// in >> BE[i];
//
// in.close();
//
// for (int s = 0; s < 5; s++)
// {
// areadiscr = areadiscr_array[s];
// float discrx = (WIDTH - 2 * EPS) / (areadiscr - 1);
// float discry = (HEIGHT - 2 * EPS) / (areadiscr - 1);
//
// int matrixsize = areadiscr * areadiscr * 3;
// double* Matrixij = new double[matrixsize];
//
// for (int i = 0; i < areadiscr; i++)
// for (int j = 0; j < areadiscr; j++)
// {
// int idx = (i * areadiscr + j) * 3;
// Matrixij[idx] = -WIDTH / 2 + EPS + discrx * i;
// Matrixij[idx + 1] = -EPS - discry * j;
// Matrixij[idx + 2] = 0;
// }
//
// unsigned int start_time;
// unsigned int end_time;
// unsigned int search_time = 0;
//
// CreateNodes(Matrixij, areadiscr, Coefs, CoefsNumb, BE, BEInfoSize); // startup calculation to activate cuda memory
// start_time = clock();
// CreateNodes(Matrixij, areadiscr, Coefs, CoefsNumb, BE, BEInfoSize);
// end_time = clock();
// search_time = end_time - start_time;
//
// output_file_name = "D:/Docs/article_03_20/CUDA_Output/node" + to_string(bediscr) + "-" + to_string(areadiscr) + ".txt";
// ofstream out;
// out.open(output_file_name);
//
// for (int i = 0; i < matrixsize; i = i + 3)
// out << Matrixij[i] << " " << Matrixij[i + 1] << " " << Matrixij[i + 2] << '\n';
// out << search_time;
//
// out.close();
//
// /////////////// sequential method ////////////////////
// start_time = clock();
// CalculateNodesSeq(Matrixij, areadiscr, Coefs, CoefsNumb, BE);
// end_time = clock();
// search_time = end_time - start_time;
//
// output_file_name = "D:/Docs/article_03_20/SEQ_output/node" + to_string(bediscr) + "-" + to_string(areadiscr) + ".txt";
// out.open(output_file_name);
//
// for (int i = 0; i < matrixsize; i = i + 3)
// out << Matrixij[i] << " " << Matrixij[i + 1] << " " << Matrixij[i + 2] << '\n';
// out << search_time;
// out.close();
//
// ///////////////////////////////////////////////////////
//
// delete(Matrixij);
// }
//
// delete(Coefs);
// delete(BE);
// }
//} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //#define _USE_MATH_DEFINES
//
//#include "cuda_runtime.h"
//#include "device_launch_parameters.h"
//
//#include <math.h>
//#include <stdio.h>
//#include <conio.h>
//#include <iostream>
//#include <fstream>
//#include <ctime>
//#include <string>
//
//void GetInputAndCalcInfluence();
//void GetInputAndCalcDistr();
//void CreateMatrix(double* Matrixij, double* BECoords, double* BE, int BeNumber, int BEInfoSize);
//void CreateNodes(double* Matrixij, int size, double* Coeffs, int BeNumber, double* BE, int BEInfoSize);
//
//// cuda function create influence matrix with pointer 'Matrixij' for boundary condition in points with coords 'BECoords',
//// but boundary elements are in coords 'BE'
//__global__ void MatrixCreation(double* Matrixij, double* BECoords, double* BE)
//{
// int i = blockIdx.x;
// int j0 = threadIdx.x;
// int index = i * blockDim.x + j0;
//
// // coords of calculation point which is be coords with shift to avoid undeterminated state
// double x = BECoords[i];
// double y = BECoords[i + 1];
//
// if (j0 % 2)
// {
// int j = (j0 - 1) / 2 * (19 + 7) + 19;
// Matrixij[index] = (-6 * atanf((-BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) / ((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]))) * ((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6])) *
// (3 * powf(BE[j + 5], 2) + powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) - 3 * powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) +
// (BE[j + 5] - (-BE[j + 3] + x) * cosf(BE[j + 6]) - (-BE[j + 4] + y) * sinf(BE[j + 6])) * (-16 * powf(BE[j + 5], 2) - 6 * powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) +
// 5 * BE[j + 5] * ((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) + 11 * powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) -
// 3 * logf(powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) + powf(-BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) *
// (powf(BE[j + 5], 3) + 3 * powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) * ((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) -
// powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 3) + 3 * powf(BE[j + 5], 2) * (-BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])))) / (36. * powf(BE[j + 5], 2) * M_PI) -
// (-6 * atanf((BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) / ((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]))) * ((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6])) *
// (3 * powf(BE[j + 5], 2) + powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) - 3 * powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) +
// (-BE[j + 5] - (-BE[j + 3] + x) * cosf(BE[j + 6]) - (-BE[j + 4] + y) * sinf(BE[j + 6])) * (-16 * powf(BE[j + 5], 2) - 6 * powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) -
// 5 * BE[j + 5] * ((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) + 11 * powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) -
// 3 * logf(powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) + powf(BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) *
// (-powf(BE[j + 5], 3) + 3 * powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) * ((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) -
// powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 3) + 3 * powf(BE[j + 5], 2) * (BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])))) / (36. * powf(BE[j + 5], 2) * M_PI);
// }
// else
// {
// int j = j0 / 2 * (19 + 7);
// Matrixij[index] = -(12 * atanf((BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) / ((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]))) * ((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9])) *
// (powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - 3 * BE[j + 10] * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) -
// 3 * powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) +
// (BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) * (9 * BE[j + 10] * (-BE[j + 10] + 3 * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]))) +
// 2 * (2 * powf(BE[j + 10], 2) - 6 * powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - 5 * BE[j + 10] * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) +
// 11 * powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2))) +
// logf(powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) + powf(BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) *
// (9 * BE[j + 10] * (powf(BE[j + 10], 2) + powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) +
// 6 * (-powf(BE[j + 10], 3) + 3 * powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) -
// powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 3)))) / (144. * powf(BE[j + 10], 2) * M_PI) +
// (12 * atanf((-BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) / ((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]))) * ((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9])) *
// (powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - 3 * BE[j + 10] * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) -
// 3 * powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) +
// (-BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) * (9 * BE[j + 10] * (BE[j + 10] + 3 * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]))) +
// 2 * (2 * powf(BE[j + 10], 2) - 6 * powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) + 5 * BE[j + 10] * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) +
// 11 * powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2))) +
// logf(powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) + powf(-BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) *
// (9 * BE[j + 10] * (powf(BE[j + 10], 2) + powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) +
// 6 * (powf(BE[j + 10], 3) + 3 * powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) -
// powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 3)))) / (144. * powf(BE[j + 10], 2) * M_PI) -
// (-12 * atanf((-BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) / ((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]))) *
// ((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17])) * (powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) +
// 3 * BE[j + 18] * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) - 3 * powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) +
// (-BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) * (9 * BE[j + 18] * (BE[j + 18] + 3 * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]))) -
// 2 * (2 * powf(BE[j + 18], 2) - 6 * powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) + 5 * BE[j + 18] * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) +
// 11 * powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2))) +
// logf(powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) + powf(-BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) *
// (9 * BE[j + 18] * (powf(BE[j + 18], 2) + powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) - powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) +
// 6 * (-powf(BE[j + 18], 3) - 3 * powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) +
// powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 3)))) / (144. * powf(BE[j + 18], 2) * M_PI) +
// (-12 * atanf((BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) / ((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]))) *
// ((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17])) * (powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) +
// 3 * BE[j + 18] * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) - 3 * powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) +
// (BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) * (9 * BE[j + 18] * (-BE[j + 18] + 3 * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]))) -
// 2 * (2 * powf(BE[j + 18], 2) - 6 * powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) - 5 * BE[j + 18] * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) +
// 11 * powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2))) +
// logf(powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) + powf(BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) *
// (9 * BE[j + 18] * (powf(BE[j + 18], 2) + powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) - powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) +
// 6 * (powf(BE[j + 18], 3) - 3 * powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) +
// powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 3)))) / (144. * powf(BE[j + 18], 2) * M_PI);
// }
//}
//
//// cuda function calculate one term for one be coord and add it to value belong to be coord
//__global__ void CalculateNodes(double* Matrixij, double* Coeff, double* BE)
//{
// int i = blockIdx.x; // index by x axis
// int j0 = blockIdx.y; // index by be element
// int k = threadIdx.x; // index by y axis
//
// int index = (i * blockDim.x + k) * 3;
//
// double x = Matrixij[index];
// double y = Matrixij[index + 1];
//
// if (j0 % 2) {
// int j = (j0 - 1) / 2 * (19 + 7) + 19;
// double increment = Coeff[j0] * ((-6 * atanf((-BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) / ((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]))) * ((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6])) *
// (3 * powf(BE[j + 5], 2) + powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) - 3 * powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) +
// (BE[j + 5] - (-BE[j + 3] + x) * cosf(BE[j + 6]) - (-BE[j + 4] + y) * sinf(BE[j + 6])) * (-16 * powf(BE[j + 5], 2) - 6 * powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) +
// 5 * BE[j + 5] * ((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) + 11 * powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) -
// 3 * logf(powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) + powf(-BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) *
// (powf(BE[j + 5], 3) + 3 * powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) * ((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) -
// powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 3) + 3 * powf(BE[j + 5], 2) * (-BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])))) / (36. * powf(BE[j + 5], 2) * M_PI) -
// (-6 * atanf((BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) / ((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]))) * ((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6])) *
// (3 * powf(BE[j + 5], 2) + powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) - 3 * powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) +
// (-BE[j + 5] - (-BE[j + 3] + x) * cosf(BE[j + 6]) - (-BE[j + 4] + y) * sinf(BE[j + 6])) * (-16 * powf(BE[j + 5], 2) - 6 * powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) -
// 5 * BE[j + 5] * ((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) + 11 * powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) -
// 3 * logf(powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) + powf(BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) *
// (-powf(BE[j + 5], 3) + 3 * powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) * ((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) -
// powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 3) + 3 * powf(BE[j + 5], 2) * (BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])))) / (36. * powf(BE[j + 5], 2) * M_PI));
// atomicAdd(&(Matrixij[index + 2]), increment);
// }
// else {
// int j = j0 / 2 * (19 + 7);
// double increment = Coeff[j0] * (-(12 * atanf((BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) / ((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]))) * ((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9])) *
// (powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - 3 * BE[j + 10] * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) -
// 3 * powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) +
// (BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) * (9 * BE[j + 10] * (-BE[j + 10] + 3 * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]))) +
// 2 * (2 * powf(BE[j + 10], 2) - 6 * powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - 5 * BE[j + 10] * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) +
// 11 * powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2))) +
// logf(powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) + powf(BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) *
// (9 * BE[j + 10] * (powf(BE[j + 10], 2) + powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) +
// 6 * (-powf(BE[j + 10], 3) + 3 * powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) -
// powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 3)))) / (144. * powf(BE[j + 10], 2) * M_PI) +
// (12 * atanf((-BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) / ((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]))) * ((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9])) *
// (powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - 3 * BE[j + 10] * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) -
// 3 * powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) +
// (-BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) * (9 * BE[j + 10] * (BE[j + 10] + 3 * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]))) +
// 2 * (2 * powf(BE[j + 10], 2) - 6 * powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) + 5 * BE[j + 10] * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) +
// 11 * powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2))) +
// logf(powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) + powf(-BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) *
// (9 * BE[j + 10] * (powf(BE[j + 10], 2) + powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) +
// 6 * (powf(BE[j + 10], 3) + 3 * powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) -
// powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 3)))) / (144. * powf(BE[j + 10], 2) * M_PI) -
// (-12 * atanf((-BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) / ((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]))) *
// ((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17])) * (powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) +
// 3 * BE[j + 18] * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) - 3 * powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) +
// (-BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) * (9 * BE[j + 18] * (BE[j + 18] + 3 * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]))) -
// 2 * (2 * powf(BE[j + 18], 2) - 6 * powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) + 5 * BE[j + 18] * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) +
// 11 * powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2))) +
// logf(powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) + powf(-BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) *
// (9 * BE[j + 18] * (powf(BE[j + 18], 2) + powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) - powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) +
// 6 * (-powf(BE[j + 18], 3) - 3 * powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) +
// powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 3)))) / (144. * powf(BE[j + 18], 2) * M_PI) +
// (-12 * atanf((BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) / ((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]))) *
// ((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17])) * (powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) +
// 3 * BE[j + 18] * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) - 3 * powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) +
// (BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) * (9 * BE[j + 18] * (-BE[j + 18] + 3 * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]))) -
// 2 * (2 * powf(BE[j + 18], 2) - 6 * powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) - 5 * BE[j + 18] * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) +
// 11 * powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2))) +
// logf(powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) + powf(BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) *
// (9 * BE[j + 18] * (powf(BE[j + 18], 2) + powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) - powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) +
// 6 * (powf(BE[j + 18], 3) - 3 * powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) +
// powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 3)))) / (144. * powf(BE[j + 18], 2) * M_PI));
// atomicAdd(&(Matrixij[index + 2]), increment);
// }
//}
//
//// function using CUDA function "MatrixCreation" create influence matrix by pointer Matrixij[size*size]
//void CreateMatrix(double* Matrixij, double* BECoords, double* BE, int BeNumber, int BEInfoSize)
//{
// double* dev_a, * dev_b, * dev_c;
//
// cudaSetDevice(0);
//
// cudaMalloc((void**)&dev_a, BeNumber * BeNumber * sizeof(double));
// cudaMalloc((void**)&dev_b, 2 * BeNumber * sizeof(double));
// cudaMalloc((void**)&dev_c, BEInfoSize * sizeof(double));
// cudaMemcpy(dev_a, Matrixij, BeNumber * BeNumber * sizeof(double), cudaMemcpyHostToDevice);
// cudaMemcpy(dev_b, BECoords, BeNumber * 2 * sizeof(double), cudaMemcpyHostToDevice);
// cudaMemcpy(dev_c, BE, BEInfoSize * sizeof(double), cudaMemcpyHostToDevice);
//
// dim3 blockSize = dim3(BeNumber, 1, 1);
// dim3 gridSize = dim3(BeNumber, 1, 1);
//
// MatrixCreation << <gridSize, blockSize >> > (dev_a, dev_b, dev_c);
//
// cudaEvent_t syncEvent;
// cudaEventCreate(&syncEvent);
// cudaEventRecord(syncEvent, 0);
// cudaEventSynchronize(syncEvent);
//
// cudaMemcpy(Matrixij, dev_a, BeNumber * BeNumber * sizeof(double), cudaMemcpyDeviceToHost);
//}
//
//void CreateNodes(double* Matrixij, int size, double* Coeffs, int BeNumber, double* BE, int BEInfoSize)
//{
// double* dev_a, * dev_b, * dev_c;
//
// cudaSetDevice(0);
//
// cudaMalloc((void**)&dev_a, 3 * size * size * sizeof(double));
// cudaMalloc((void**)&dev_b, BeNumber * sizeof(double));
// cudaMalloc((void**)&dev_c, BEInfoSize * sizeof(double));
// cudaMemcpy(dev_a, Matrixij, 3 * size * size * sizeof(double), cudaMemcpyHostToDevice);
// cudaMemcpy(dev_b, Coeffs, BeNumber * sizeof(double), cudaMemcpyHostToDevice);
// cudaMemcpy(dev_c, BE, BEInfoSize * sizeof(double), cudaMemcpyHostToDevice);
//
// dim3 blockSize = dim3(size, 1, 1);
// dim3 gridSize = dim3(size, BeNumber, 1);
//
// CalculateNodes << < gridSize, blockSize >> > (dev_a, dev_b, dev_c);
//
// cudaEvent_t syncEvent;
// cudaEventCreate(&syncEvent);
// cudaEventRecord(syncEvent, 0);
// cudaEventSynchronize(syncEvent);
//
// cudaMemcpy(Matrixij, dev_a, 3 * size * size * sizeof(double), cudaMemcpyDeviceToHost);
//}
//
//void GetInputAndCalcInfluence()
//{
// double* Coords, * BE;
// double* Matrixij;
//
// int bediscr_array[] = { 5,10,15,20,25,30,35 };
// string input_file_name;
// string output_file_name;
//
// for (int i = 0; i < 7; i++)
// {
// int bediscr = bediscr_array[i];
// int CoordsNumber, BEInfoSize;
//
// input_file_name = "D:/Docs/article_03_20/data/shifted_coords" + to_string(bediscr) + ".txt";
// ifstream in;
// in.open(input_file_name);
//
// in >> CoordsNumber;
// Coords = new double[CoordsNumber];
//
// for (int i = 0; i < CoordsNumber; i++)
// in >> Coords[i];
//
// in.close();
//
// input_file_name = "D:/Docs/article_03_20/data/beinfo" + to_string(bediscr) + ".txt";
// in.open(input_file_name);
//
// in >> BEInfoSize;
// BE = new double[BEInfoSize];
//
// for (int i = 0; i < BEInfoSize; i++)
// in >> BE[i];
//
// in.close();
//
// int benumb = CoordsNumber / 2;
//
// Matrixij = new double[benumb * benumb];
//
// unsigned int start_time;
// unsigned int end_time;
// unsigned int search_time = 0;
//
// /////////////// CUDA method //////////////////////////
// CreateMatrix(Matrixij, Coords, BE, benumb, BEInfoSize);
// start_time = clock();
// CreateMatrix(Matrixij, Coords, BE, benumb, BEInfoSize);
// end_time = clock();
// search_time = end_time - start_time;
//
// output_file_name = "D:/Docs/article_03_20/CUDA_output/matr" + to_string(bediscr) + ".txt";
// ofstream out;
// out.open(output_file_name);
//
// for (int i = 0; i < benumb; i++)
// for (int j = 0; j < benumb; j++)
// out << Matrixij[i * benumb + j] << '\n';
// out << search_time;
// out.close();
//
// /////////////// sequential method ////////////////////
// start_time = clock();
// MatrixCreationSeq(Matrixij, Coords, BE, benumb);
// end_time = clock();
// search_time = end_time - start_time;
//
// output_file_name = "D:/Docs/article_03_20/SEQ_output/matr" + to_string(bediscr) + ".txt";
// out.open(output_file_name);
//
// for (int i = 0; i < benumb; i++)
// for (int j = 0; j < benumb; j++)
// out << Matrixij[i * benumb + j] << '\n';
// out << search_time;
// out.close();
//
// ///////////////////////////////////////////////////////
//
// delete(Matrixij);
// delete(BE);
// delete(Coords);
// }
//}
//
//void GetInputAndCalcDistr()
//{
// int bediscr_array[] = { 5,10,15,20,25,30,35 };
// int areadiscr_array[] = { 10, 20, 30, 40, 50 };
// double* BE, * Coefs;
// int CoefsNumb, BEInfoSize;
// string input_file_name;
// string output_file_name;
// int bediscr, areadiscr;
//
// for (int k = 0; k < 7; k++)
// {
// bediscr = bediscr_array[k];
// input_file_name = "D:/Docs/article_03_20/data/coefs" + to_string(bediscr) + ".txt";
// ifstream in;
// in.open(input_file_name);
//
// in >> CoefsNumb;
// Coefs = new double[CoefsNumb];
//
// for (int i = 0; i < CoefsNumb; i++)
// in >> Coefs[i];
//
// in.close();
//
// input_file_name = "D:/Docs/article_03_20/data/beinfo" + to_string(bediscr) + ".txt";
// in.open(input_file_name);
//
// in >> BEInfoSize;
// BE = new double[BEInfoSize];
//
// for (int i = 0; i < BEInfoSize; i++)
// in >> BE[i];
//
// in.close();
//
// for (int s = 0; s < 5; s++)
// {
// areadiscr = areadiscr_array[s];
// float discrx = (WIDTH - 2 * EPS) / (areadiscr - 1);
// float discry = (HEIGHT - 2 * EPS) / (areadiscr - 1);
//
// int matrixsize = areadiscr * areadiscr * 3;
// double* Matrixij = new double[matrixsize];
//
// for (int i = 0; i < areadiscr; i++)
// for (int j = 0; j < areadiscr; j++)
// {
// int idx = (i * areadiscr + j) * 3;
// Matrixij[idx] = -WIDTH / 2 + EPS + discrx * i;
// Matrixij[idx + 1] = -EPS - discry * j;
// Matrixij[idx + 2] = 0;
// }
//
// unsigned int start_time;
// unsigned int end_time;
// unsigned int search_time = 0;
//
// CreateNodes(Matrixij, areadiscr, Coefs, CoefsNumb, BE, BEInfoSize); // startup calculation to activate cuda memory
// start_time = clock();
// CreateNodes(Matrixij, areadiscr, Coefs, CoefsNumb, BE, BEInfoSize);
// end_time = clock();
// search_time = end_time - start_time;
//
// output_file_name = "D:/Docs/article_03_20/CUDA_Output/node" + to_string(bediscr) + "-" + to_string(areadiscr) + ".txt";
// ofstream out;
// out.open(output_file_name);
//
// for (int i = 0; i < matrixsize; i = i + 3)
// out << Matrixij[i] << " " << Matrixij[i + 1] << " " << Matrixij[i + 2] << '\n';
// out << search_time;
//
// out.close();
//
// /////////////// sequential method ////////////////////
// start_time = clock();
// CalculateNodesSeq(Matrixij, areadiscr, Coefs, CoefsNumb, BE);
// end_time = clock();
// search_time = end_time - start_time;
//
// output_file_name = "D:/Docs/article_03_20/SEQ_output/node" + to_string(bediscr) + "-" + to_string(areadiscr) + ".txt";
// out.open(output_file_name);
//
// for (int i = 0; i < matrixsize; i = i + 3)
// out << Matrixij[i] << " " << Matrixij[i + 1] << " " << Matrixij[i + 2] << '\n';
// out << search_time;
// out.close();
//
// ///////////////////////////////////////////////////////
//
// delete(Matrixij);
// }
//
// delete(Coefs);
// delete(BE);
// }
//} | .file "tmpxft_0004c921_00000000-6_NonLinThreeFF.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
//#define _USE_MATH_DEFINES
//
//#include "cuda_runtime.h"
//#include "device_launch_parameters.h"
//
//#include <math.h>
//#include <stdio.h>
//#include <conio.h>
//#include <iostream>
//#include <fstream>
//#include <ctime>
//#include <string>
//
//void GetInputAndCalcInfluence();
//void GetInputAndCalcDistr();
//void CreateMatrix(double* Matrixij, double* BECoords, double* BE, int BeNumber, int BEInfoSize);
//void CreateNodes(double* Matrixij, int size, double* Coeffs, int BeNumber, double* BE, int BEInfoSize);
//
//// cuda function create influence matrix with pointer 'Matrixij' for boundary condition in points with coords 'BECoords',
//// but boundary elements are in coords 'BE'
//__global__ void MatrixCreation(double* Matrixij, double* BECoords, double* BE)
//{
// int i = blockIdx.x;
// int j0 = threadIdx.x;
// int index = i * blockDim.x + j0;
//
// // coords of calculation point which is be coords with shift to avoid undeterminated state
// double x = BECoords[i];
// double y = BECoords[i + 1];
//
// if (j0 % 2)
// {
// int j = (j0 - 1) / 2 * (19 + 7) + 19;
// Matrixij[index] = (-6 * atanf((-BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) / ((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]))) * ((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6])) *
// (3 * powf(BE[j + 5], 2) + powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) - 3 * powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) +
// (BE[j + 5] - (-BE[j + 3] + x) * cosf(BE[j + 6]) - (-BE[j + 4] + y) * sinf(BE[j + 6])) * (-16 * powf(BE[j + 5], 2) - 6 * powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) +
// 5 * BE[j + 5] * ((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) + 11 * powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) -
// 3 * logf(powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) + powf(-BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) *
// (powf(BE[j + 5], 3) + 3 * powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) * ((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) -
// powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 3) + 3 * powf(BE[j + 5], 2) * (-BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])))) / (36. * powf(BE[j + 5], 2) * M_PI) -
// (-6 * atanf((BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) / ((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]))) * ((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6])) *
// (3 * powf(BE[j + 5], 2) + powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) - 3 * powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) +
// (-BE[j + 5] - (-BE[j + 3] + x) * cosf(BE[j + 6]) - (-BE[j + 4] + y) * sinf(BE[j + 6])) * (-16 * powf(BE[j + 5], 2) - 6 * powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) -
// 5 * BE[j + 5] * ((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) + 11 * powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) -
// 3 * logf(powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) + powf(BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) *
// (-powf(BE[j + 5], 3) + 3 * powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) * ((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) -
// powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 3) + 3 * powf(BE[j + 5], 2) * (BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])))) / (36. * powf(BE[j + 5], 2) * M_PI);
// }
// else
// {
// int j = j0 / 2 * (19 + 7);
// Matrixij[index] = -(12 * atanf((BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) / ((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]))) * ((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9])) *
// (powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - 3 * BE[j + 10] * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) -
// 3 * powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) +
// (BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) * (9 * BE[j + 10] * (-BE[j + 10] + 3 * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]))) +
// 2 * (2 * powf(BE[j + 10], 2) - 6 * powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - 5 * BE[j + 10] * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) +
// 11 * powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2))) +
// logf(powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) + powf(BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) *
// (9 * BE[j + 10] * (powf(BE[j + 10], 2) + powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) +
// 6 * (-powf(BE[j + 10], 3) + 3 * powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) -
// powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 3)))) / (144. * powf(BE[j + 10], 2) * M_PI) +
// (12 * atanf((-BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) / ((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]))) * ((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9])) *
// (powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - 3 * BE[j + 10] * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) -
// 3 * powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) +
// (-BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) * (9 * BE[j + 10] * (BE[j + 10] + 3 * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]))) +
// 2 * (2 * powf(BE[j + 10], 2) - 6 * powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) + 5 * BE[j + 10] * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) +
// 11 * powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2))) +
// logf(powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) + powf(-BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) *
// (9 * BE[j + 10] * (powf(BE[j + 10], 2) + powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) +
// 6 * (powf(BE[j + 10], 3) + 3 * powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) -
// powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 3)))) / (144. * powf(BE[j + 10], 2) * M_PI) -
// (-12 * atanf((-BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) / ((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]))) *
// ((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17])) * (powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) +
// 3 * BE[j + 18] * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) - 3 * powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) +
// (-BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) * (9 * BE[j + 18] * (BE[j + 18] + 3 * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]))) -
// 2 * (2 * powf(BE[j + 18], 2) - 6 * powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) + 5 * BE[j + 18] * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) +
// 11 * powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2))) +
// logf(powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) + powf(-BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) *
// (9 * BE[j + 18] * (powf(BE[j + 18], 2) + powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) - powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) +
// 6 * (-powf(BE[j + 18], 3) - 3 * powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) +
// powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 3)))) / (144. * powf(BE[j + 18], 2) * M_PI) +
// (-12 * atanf((BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) / ((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]))) *
// ((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17])) * (powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) +
// 3 * BE[j + 18] * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) - 3 * powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) +
// (BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) * (9 * BE[j + 18] * (-BE[j + 18] + 3 * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]))) -
// 2 * (2 * powf(BE[j + 18], 2) - 6 * powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) - 5 * BE[j + 18] * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) +
// 11 * powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2))) +
// logf(powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) + powf(BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) *
// (9 * BE[j + 18] * (powf(BE[j + 18], 2) + powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) - powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) +
// 6 * (powf(BE[j + 18], 3) - 3 * powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) +
// powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 3)))) / (144. * powf(BE[j + 18], 2) * M_PI);
// }
//}
//
//// cuda function calculate one term for one be coord and add it to value belong to be coord
//__global__ void CalculateNodes(double* Matrixij, double* Coeff, double* BE)
//{
// int i = blockIdx.x; // index by x axis
// int j0 = blockIdx.y; // index by be element
// int k = threadIdx.x; // index by y axis
//
// int index = (i * blockDim.x + k) * 3;
//
// double x = Matrixij[index];
// double y = Matrixij[index + 1];
//
// if (j0 % 2) {
// int j = (j0 - 1) / 2 * (19 + 7) + 19;
// double increment = Coeff[j0] * ((-6 * atanf((-BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) / ((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]))) * ((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6])) *
// (3 * powf(BE[j + 5], 2) + powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) - 3 * powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) +
// (BE[j + 5] - (-BE[j + 3] + x) * cosf(BE[j + 6]) - (-BE[j + 4] + y) * sinf(BE[j + 6])) * (-16 * powf(BE[j + 5], 2) - 6 * powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) +
// 5 * BE[j + 5] * ((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) + 11 * powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) -
// 3 * logf(powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) + powf(-BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) *
// (powf(BE[j + 5], 3) + 3 * powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) * ((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) -
// powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 3) + 3 * powf(BE[j + 5], 2) * (-BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])))) / (36. * powf(BE[j + 5], 2) * M_PI) -
// (-6 * atanf((BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) / ((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]))) * ((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6])) *
// (3 * powf(BE[j + 5], 2) + powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) - 3 * powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) +
// (-BE[j + 5] - (-BE[j + 3] + x) * cosf(BE[j + 6]) - (-BE[j + 4] + y) * sinf(BE[j + 6])) * (-16 * powf(BE[j + 5], 2) - 6 * powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) -
// 5 * BE[j + 5] * ((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) + 11 * powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) -
// 3 * logf(powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) + powf(BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) *
// (-powf(BE[j + 5], 3) + 3 * powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) * ((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) -
// powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 3) + 3 * powf(BE[j + 5], 2) * (BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])))) / (36. * powf(BE[j + 5], 2) * M_PI));
// atomicAdd(&(Matrixij[index + 2]), increment);
// }
// else {
// int j = j0 / 2 * (19 + 7);
// double increment = Coeff[j0] * (-(12 * atanf((BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) / ((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]))) * ((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9])) *
// (powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - 3 * BE[j + 10] * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) -
// 3 * powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) +
// (BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) * (9 * BE[j + 10] * (-BE[j + 10] + 3 * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]))) +
// 2 * (2 * powf(BE[j + 10], 2) - 6 * powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - 5 * BE[j + 10] * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) +
// 11 * powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2))) +
// logf(powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) + powf(BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) *
// (9 * BE[j + 10] * (powf(BE[j + 10], 2) + powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) +
// 6 * (-powf(BE[j + 10], 3) + 3 * powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) -
// powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 3)))) / (144. * powf(BE[j + 10], 2) * M_PI) +
// (12 * atanf((-BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) / ((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]))) * ((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9])) *
// (powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - 3 * BE[j + 10] * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) -
// 3 * powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) +
// (-BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) * (9 * BE[j + 10] * (BE[j + 10] + 3 * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]))) +
// 2 * (2 * powf(BE[j + 10], 2) - 6 * powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) + 5 * BE[j + 10] * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) +
// 11 * powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2))) +
// logf(powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) + powf(-BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) *
// (9 * BE[j + 10] * (powf(BE[j + 10], 2) + powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) +
// 6 * (powf(BE[j + 10], 3) + 3 * powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) -
// powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 3)))) / (144. * powf(BE[j + 10], 2) * M_PI) -
// (-12 * atanf((-BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) / ((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]))) *
// ((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17])) * (powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) +
// 3 * BE[j + 18] * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) - 3 * powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) +
// (-BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) * (9 * BE[j + 18] * (BE[j + 18] + 3 * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]))) -
// 2 * (2 * powf(BE[j + 18], 2) - 6 * powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) + 5 * BE[j + 18] * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) +
// 11 * powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2))) +
// logf(powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) + powf(-BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) *
// (9 * BE[j + 18] * (powf(BE[j + 18], 2) + powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) - powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) +
// 6 * (-powf(BE[j + 18], 3) - 3 * powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) +
// powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 3)))) / (144. * powf(BE[j + 18], 2) * M_PI) +
// (-12 * atanf((BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) / ((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]))) *
// ((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17])) * (powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) +
// 3 * BE[j + 18] * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) - 3 * powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) +
// (BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) * (9 * BE[j + 18] * (-BE[j + 18] + 3 * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]))) -
// 2 * (2 * powf(BE[j + 18], 2) - 6 * powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) - 5 * BE[j + 18] * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) +
// 11 * powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2))) +
// logf(powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) + powf(BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) *
// (9 * BE[j + 18] * (powf(BE[j + 18], 2) + powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) - powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) +
// 6 * (powf(BE[j + 18], 3) - 3 * powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) +
// powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 3)))) / (144. * powf(BE[j + 18], 2) * M_PI));
// atomicAdd(&(Matrixij[index + 2]), increment);
// }
//}
//
//// function using CUDA function "MatrixCreation" create influence matrix by pointer Matrixij[size*size]
//void CreateMatrix(double* Matrixij, double* BECoords, double* BE, int BeNumber, int BEInfoSize)
//{
// double* dev_a, * dev_b, * dev_c;
//
// cudaSetDevice(0);
//
// cudaMalloc((void**)&dev_a, BeNumber * BeNumber * sizeof(double));
// cudaMalloc((void**)&dev_b, 2 * BeNumber * sizeof(double));
// cudaMalloc((void**)&dev_c, BEInfoSize * sizeof(double));
// cudaMemcpy(dev_a, Matrixij, BeNumber * BeNumber * sizeof(double), cudaMemcpyHostToDevice);
// cudaMemcpy(dev_b, BECoords, BeNumber * 2 * sizeof(double), cudaMemcpyHostToDevice);
// cudaMemcpy(dev_c, BE, BEInfoSize * sizeof(double), cudaMemcpyHostToDevice);
//
// dim3 blockSize = dim3(BeNumber, 1, 1);
// dim3 gridSize = dim3(BeNumber, 1, 1);
//
// MatrixCreation << <gridSize, blockSize >> > (dev_a, dev_b, dev_c);
//
// cudaEvent_t syncEvent;
// cudaEventCreate(&syncEvent);
// cudaEventRecord(syncEvent, 0);
// cudaEventSynchronize(syncEvent);
//
// cudaMemcpy(Matrixij, dev_a, BeNumber * BeNumber * sizeof(double), cudaMemcpyDeviceToHost);
//}
//
//void CreateNodes(double* Matrixij, int size, double* Coeffs, int BeNumber, double* BE, int BEInfoSize)
//{
// double* dev_a, * dev_b, * dev_c;
//
// cudaSetDevice(0);
//
// cudaMalloc((void**)&dev_a, 3 * size * size * sizeof(double));
// cudaMalloc((void**)&dev_b, BeNumber * sizeof(double));
// cudaMalloc((void**)&dev_c, BEInfoSize * sizeof(double));
// cudaMemcpy(dev_a, Matrixij, 3 * size * size * sizeof(double), cudaMemcpyHostToDevice);
// cudaMemcpy(dev_b, Coeffs, BeNumber * sizeof(double), cudaMemcpyHostToDevice);
// cudaMemcpy(dev_c, BE, BEInfoSize * sizeof(double), cudaMemcpyHostToDevice);
//
// dim3 blockSize = dim3(size, 1, 1);
// dim3 gridSize = dim3(size, BeNumber, 1);
//
// CalculateNodes << < gridSize, blockSize >> > (dev_a, dev_b, dev_c);
//
// cudaEvent_t syncEvent;
// cudaEventCreate(&syncEvent);
// cudaEventRecord(syncEvent, 0);
// cudaEventSynchronize(syncEvent);
//
// cudaMemcpy(Matrixij, dev_a, 3 * size * size * sizeof(double), cudaMemcpyDeviceToHost);
//}
//
//void GetInputAndCalcInfluence()
//{
// double* Coords, * BE;
// double* Matrixij;
//
// int bediscr_array[] = { 5,10,15,20,25,30,35 };
// string input_file_name;
// string output_file_name;
//
// for (int i = 0; i < 7; i++)
// {
// int bediscr = bediscr_array[i];
// int CoordsNumber, BEInfoSize;
//
// input_file_name = "D:/Docs/article_03_20/data/shifted_coords" + to_string(bediscr) + ".txt";
// ifstream in;
// in.open(input_file_name);
//
// in >> CoordsNumber;
// Coords = new double[CoordsNumber];
//
// for (int i = 0; i < CoordsNumber; i++)
// in >> Coords[i];
//
// in.close();
//
// input_file_name = "D:/Docs/article_03_20/data/beinfo" + to_string(bediscr) + ".txt";
// in.open(input_file_name);
//
// in >> BEInfoSize;
// BE = new double[BEInfoSize];
//
// for (int i = 0; i < BEInfoSize; i++)
// in >> BE[i];
//
// in.close();
//
// int benumb = CoordsNumber / 2;
//
// Matrixij = new double[benumb * benumb];
//
// unsigned int start_time;
// unsigned int end_time;
// unsigned int search_time = 0;
//
// /////////////// CUDA method //////////////////////////
// CreateMatrix(Matrixij, Coords, BE, benumb, BEInfoSize);
// start_time = clock();
// CreateMatrix(Matrixij, Coords, BE, benumb, BEInfoSize);
// end_time = clock();
// search_time = end_time - start_time;
//
// output_file_name = "D:/Docs/article_03_20/CUDA_output/matr" + to_string(bediscr) + ".txt";
// ofstream out;
// out.open(output_file_name);
//
// for (int i = 0; i < benumb; i++)
// for (int j = 0; j < benumb; j++)
// out << Matrixij[i * benumb + j] << '\n';
// out << search_time;
// out.close();
//
// /////////////// sequential method ////////////////////
// start_time = clock();
// MatrixCreationSeq(Matrixij, Coords, BE, benumb);
// end_time = clock();
// search_time = end_time - start_time;
//
// output_file_name = "D:/Docs/article_03_20/SEQ_output/matr" + to_string(bediscr) + ".txt";
// out.open(output_file_name);
//
// for (int i = 0; i < benumb; i++)
// for (int j = 0; j < benumb; j++)
// out << Matrixij[i * benumb + j] << '\n';
// out << search_time;
// out.close();
//
// ///////////////////////////////////////////////////////
//
// delete(Matrixij);
// delete(BE);
// delete(Coords);
// }
//}
//
//void GetInputAndCalcDistr()
//{
// int bediscr_array[] = { 5,10,15,20,25,30,35 };
// int areadiscr_array[] = { 10, 20, 30, 40, 50 };
// double* BE, * Coefs;
// int CoefsNumb, BEInfoSize;
// string input_file_name;
// string output_file_name;
// int bediscr, areadiscr;
//
// for (int k = 0; k < 7; k++)
// {
// bediscr = bediscr_array[k];
// input_file_name = "D:/Docs/article_03_20/data/coefs" + to_string(bediscr) + ".txt";
// ifstream in;
// in.open(input_file_name);
//
// in >> CoefsNumb;
// Coefs = new double[CoefsNumb];
//
// for (int i = 0; i < CoefsNumb; i++)
// in >> Coefs[i];
//
// in.close();
//
// input_file_name = "D:/Docs/article_03_20/data/beinfo" + to_string(bediscr) + ".txt";
// in.open(input_file_name);
//
// in >> BEInfoSize;
// BE = new double[BEInfoSize];
//
// for (int i = 0; i < BEInfoSize; i++)
// in >> BE[i];
//
// in.close();
//
// for (int s = 0; s < 5; s++)
// {
// areadiscr = areadiscr_array[s];
// float discrx = (WIDTH - 2 * EPS) / (areadiscr - 1);
// float discry = (HEIGHT - 2 * EPS) / (areadiscr - 1);
//
// int matrixsize = areadiscr * areadiscr * 3;
// double* Matrixij = new double[matrixsize];
//
// for (int i = 0; i < areadiscr; i++)
// for (int j = 0; j < areadiscr; j++)
// {
// int idx = (i * areadiscr + j) * 3;
// Matrixij[idx] = -WIDTH / 2 + EPS + discrx * i;
// Matrixij[idx + 1] = -EPS - discry * j;
// Matrixij[idx + 2] = 0;
// }
//
// unsigned int start_time;
// unsigned int end_time;
// unsigned int search_time = 0;
//
// CreateNodes(Matrixij, areadiscr, Coefs, CoefsNumb, BE, BEInfoSize); // startup calculation to activate cuda memory
// start_time = clock();
// CreateNodes(Matrixij, areadiscr, Coefs, CoefsNumb, BE, BEInfoSize);
// end_time = clock();
// search_time = end_time - start_time;
//
// output_file_name = "D:/Docs/article_03_20/CUDA_Output/node" + to_string(bediscr) + "-" + to_string(areadiscr) + ".txt";
// ofstream out;
// out.open(output_file_name);
//
// for (int i = 0; i < matrixsize; i = i + 3)
// out << Matrixij[i] << " " << Matrixij[i + 1] << " " << Matrixij[i + 2] << '\n';
// out << search_time;
//
// out.close();
//
// /////////////// sequential method ////////////////////
// start_time = clock();
// CalculateNodesSeq(Matrixij, areadiscr, Coefs, CoefsNumb, BE);
// end_time = clock();
// search_time = end_time - start_time;
//
// output_file_name = "D:/Docs/article_03_20/SEQ_output/node" + to_string(bediscr) + "-" + to_string(areadiscr) + ".txt";
// out.open(output_file_name);
//
// for (int i = 0; i < matrixsize; i = i + 3)
// out << Matrixij[i] << " " << Matrixij[i + 1] << " " << Matrixij[i + 2] << '\n';
// out << search_time;
// out.close();
//
// ///////////////////////////////////////////////////////
//
// delete(Matrixij);
// }
//
// delete(Coefs);
// delete(BE);
// }
//} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
//#define _USE_MATH_DEFINES
//
//#include "cuda_runtime.h"
//#include "device_launch_parameters.h"
//
//#include <math.h>
//#include <stdio.h>
//#include <conio.h>
//#include <iostream>
//#include <fstream>
//#include <ctime>
//#include <string>
//
//void GetInputAndCalcInfluence();
//void GetInputAndCalcDistr();
//void CreateMatrix(double* Matrixij, double* BECoords, double* BE, int BeNumber, int BEInfoSize);
//void CreateNodes(double* Matrixij, int size, double* Coeffs, int BeNumber, double* BE, int BEInfoSize);
//
//// cuda function create influence matrix with pointer 'Matrixij' for boundary condition in points with coords 'BECoords',
//// but boundary elements are in coords 'BE'
//__global__ void MatrixCreation(double* Matrixij, double* BECoords, double* BE)
//{
// int i = blockIdx.x;
// int j0 = threadIdx.x;
// int index = i * blockDim.x + j0;
//
// // coords of calculation point which is be coords with shift to avoid undeterminated state
// double x = BECoords[i];
// double y = BECoords[i + 1];
//
// if (j0 % 2)
// {
// int j = (j0 - 1) / 2 * (19 + 7) + 19;
// Matrixij[index] = (-6 * atanf((-BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) / ((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]))) * ((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6])) *
// (3 * powf(BE[j + 5], 2) + powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) - 3 * powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) +
// (BE[j + 5] - (-BE[j + 3] + x) * cosf(BE[j + 6]) - (-BE[j + 4] + y) * sinf(BE[j + 6])) * (-16 * powf(BE[j + 5], 2) - 6 * powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) +
// 5 * BE[j + 5] * ((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) + 11 * powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) -
// 3 * logf(powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) + powf(-BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) *
// (powf(BE[j + 5], 3) + 3 * powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) * ((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) -
// powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 3) + 3 * powf(BE[j + 5], 2) * (-BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])))) / (36. * powf(BE[j + 5], 2) * M_PI) -
// (-6 * atanf((BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) / ((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]))) * ((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6])) *
// (3 * powf(BE[j + 5], 2) + powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) - 3 * powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) +
// (-BE[j + 5] - (-BE[j + 3] + x) * cosf(BE[j + 6]) - (-BE[j + 4] + y) * sinf(BE[j + 6])) * (-16 * powf(BE[j + 5], 2) - 6 * powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) -
// 5 * BE[j + 5] * ((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) + 11 * powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) -
// 3 * logf(powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) + powf(BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) *
// (-powf(BE[j + 5], 3) + 3 * powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) * ((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) -
// powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 3) + 3 * powf(BE[j + 5], 2) * (BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])))) / (36. * powf(BE[j + 5], 2) * M_PI);
// }
// else
// {
// int j = j0 / 2 * (19 + 7);
// Matrixij[index] = -(12 * atanf((BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) / ((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]))) * ((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9])) *
// (powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - 3 * BE[j + 10] * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) -
// 3 * powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) +
// (BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) * (9 * BE[j + 10] * (-BE[j + 10] + 3 * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]))) +
// 2 * (2 * powf(BE[j + 10], 2) - 6 * powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - 5 * BE[j + 10] * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) +
// 11 * powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2))) +
// logf(powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) + powf(BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) *
// (9 * BE[j + 10] * (powf(BE[j + 10], 2) + powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) +
// 6 * (-powf(BE[j + 10], 3) + 3 * powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) -
// powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 3)))) / (144. * powf(BE[j + 10], 2) * M_PI) +
// (12 * atanf((-BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) / ((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]))) * ((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9])) *
// (powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - 3 * BE[j + 10] * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) -
// 3 * powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) +
// (-BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) * (9 * BE[j + 10] * (BE[j + 10] + 3 * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]))) +
// 2 * (2 * powf(BE[j + 10], 2) - 6 * powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) + 5 * BE[j + 10] * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) +
// 11 * powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2))) +
// logf(powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) + powf(-BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) *
// (9 * BE[j + 10] * (powf(BE[j + 10], 2) + powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) +
// 6 * (powf(BE[j + 10], 3) + 3 * powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) -
// powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 3)))) / (144. * powf(BE[j + 10], 2) * M_PI) -
// (-12 * atanf((-BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) / ((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]))) *
// ((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17])) * (powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) +
// 3 * BE[j + 18] * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) - 3 * powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) +
// (-BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) * (9 * BE[j + 18] * (BE[j + 18] + 3 * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]))) -
// 2 * (2 * powf(BE[j + 18], 2) - 6 * powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) + 5 * BE[j + 18] * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) +
// 11 * powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2))) +
// logf(powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) + powf(-BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) *
// (9 * BE[j + 18] * (powf(BE[j + 18], 2) + powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) - powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) +
// 6 * (-powf(BE[j + 18], 3) - 3 * powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) +
// powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 3)))) / (144. * powf(BE[j + 18], 2) * M_PI) +
// (-12 * atanf((BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) / ((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]))) *
// ((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17])) * (powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) +
// 3 * BE[j + 18] * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) - 3 * powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) +
// (BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) * (9 * BE[j + 18] * (-BE[j + 18] + 3 * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]))) -
// 2 * (2 * powf(BE[j + 18], 2) - 6 * powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) - 5 * BE[j + 18] * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) +
// 11 * powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2))) +
// logf(powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) + powf(BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) *
// (9 * BE[j + 18] * (powf(BE[j + 18], 2) + powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) - powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) +
// 6 * (powf(BE[j + 18], 3) - 3 * powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) +
// powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 3)))) / (144. * powf(BE[j + 18], 2) * M_PI);
// }
//}
//
//// cuda function calculate one term for one be coord and add it to value belong to be coord
//__global__ void CalculateNodes(double* Matrixij, double* Coeff, double* BE)
//{
// int i = blockIdx.x; // index by x axis
// int j0 = blockIdx.y; // index by be element
// int k = threadIdx.x; // index by y axis
//
// int index = (i * blockDim.x + k) * 3;
//
// double x = Matrixij[index];
// double y = Matrixij[index + 1];
//
// if (j0 % 2) {
// int j = (j0 - 1) / 2 * (19 + 7) + 19;
// double increment = Coeff[j0] * ((-6 * atanf((-BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) / ((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]))) * ((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6])) *
// (3 * powf(BE[j + 5], 2) + powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) - 3 * powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) +
// (BE[j + 5] - (-BE[j + 3] + x) * cosf(BE[j + 6]) - (-BE[j + 4] + y) * sinf(BE[j + 6])) * (-16 * powf(BE[j + 5], 2) - 6 * powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) +
// 5 * BE[j + 5] * ((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) + 11 * powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) -
// 3 * logf(powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) + powf(-BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) *
// (powf(BE[j + 5], 3) + 3 * powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) * ((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) -
// powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 3) + 3 * powf(BE[j + 5], 2) * (-BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])))) / (36. * powf(BE[j + 5], 2) * M_PI) -
// (-6 * atanf((BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) / ((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]))) * ((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6])) *
// (3 * powf(BE[j + 5], 2) + powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) - 3 * powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) +
// (-BE[j + 5] - (-BE[j + 3] + x) * cosf(BE[j + 6]) - (-BE[j + 4] + y) * sinf(BE[j + 6])) * (-16 * powf(BE[j + 5], 2) - 6 * powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) -
// 5 * BE[j + 5] * ((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) + 11 * powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) -
// 3 * logf(powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) + powf(BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 2)) *
// (-powf(BE[j + 5], 3) + 3 * powf((-BE[j + 4] + y) * cosf(BE[j + 6]) + (BE[j + 3] - x) * sinf(BE[j + 6]), 2) * ((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])) -
// powf((-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6]), 3) + 3 * powf(BE[j + 5], 2) * (BE[j + 5] + (-BE[j + 3] + x) * cosf(BE[j + 6]) + (-BE[j + 4] + y) * sinf(BE[j + 6])))) / (36. * powf(BE[j + 5], 2) * M_PI));
// atomicAdd(&(Matrixij[index + 2]), increment);
// }
// else {
// int j = j0 / 2 * (19 + 7);
// double increment = Coeff[j0] * (-(12 * atanf((BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) / ((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]))) * ((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9])) *
// (powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - 3 * BE[j + 10] * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) -
// 3 * powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) +
// (BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) * (9 * BE[j + 10] * (-BE[j + 10] + 3 * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]))) +
// 2 * (2 * powf(BE[j + 10], 2) - 6 * powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - 5 * BE[j + 10] * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) +
// 11 * powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2))) +
// logf(powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) + powf(BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) *
// (9 * BE[j + 10] * (powf(BE[j + 10], 2) + powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) +
// 6 * (-powf(BE[j + 10], 3) + 3 * powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) -
// powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 3)))) / (144. * powf(BE[j + 10], 2) * M_PI) +
// (12 * atanf((-BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) / ((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]))) * ((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9])) *
// (powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - 3 * BE[j + 10] * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) -
// 3 * powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) +
// (-BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) * (9 * BE[j + 10] * (BE[j + 10] + 3 * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]))) +
// 2 * (2 * powf(BE[j + 10], 2) - 6 * powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) + 5 * BE[j + 10] * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) +
// 11 * powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2))) +
// logf(powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) + powf(-BE[j + 10] + (-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) *
// (9 * BE[j + 10] * (powf(BE[j + 10], 2) + powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) - powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 2)) +
// 6 * (powf(BE[j + 10], 3) + 3 * powf((-BE[j + 6] + y) * cosf(BE[j + 9]) + (BE[j + 5] - x) * sinf(BE[j + 9]), 2) * ((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9])) -
// powf((-BE[j + 5] + x) * cosf(BE[j + 9]) + (-BE[j + 6] + y) * sinf(BE[j + 9]), 3)))) / (144. * powf(BE[j + 10], 2) * M_PI) -
// (-12 * atanf((-BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) / ((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]))) *
// ((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17])) * (powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) +
// 3 * BE[j + 18] * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) - 3 * powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) +
// (-BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) * (9 * BE[j + 18] * (BE[j + 18] + 3 * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]))) -
// 2 * (2 * powf(BE[j + 18], 2) - 6 * powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) + 5 * BE[j + 18] * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) +
// 11 * powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2))) +
// logf(powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) + powf(-BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) *
// (9 * BE[j + 18] * (powf(BE[j + 18], 2) + powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) - powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) +
// 6 * (-powf(BE[j + 18], 3) - 3 * powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) +
// powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 3)))) / (144. * powf(BE[j + 18], 2) * M_PI) +
// (-12 * atanf((BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) / ((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]))) *
// ((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17])) * (powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) +
// 3 * BE[j + 18] * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) - 3 * powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) +
// (BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) * (9 * BE[j + 18] * (-BE[j + 18] + 3 * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]))) -
// 2 * (2 * powf(BE[j + 18], 2) - 6 * powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) - 5 * BE[j + 18] * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) +
// 11 * powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2))) +
// logf(powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) + powf(BE[j + 18] + (-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) *
// (9 * BE[j + 18] * (powf(BE[j + 18], 2) + powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) - powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 2)) +
// 6 * (powf(BE[j + 18], 3) - 3 * powf((-BE[j + 14] + y) * cosf(BE[j + 17]) + (BE[j + 13] - x) * sinf(BE[j + 17]), 2) * ((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17])) +
// powf((-BE[j + 13] + x) * cosf(BE[j + 17]) + (-BE[j + 14] + y) * sinf(BE[j + 17]), 3)))) / (144. * powf(BE[j + 18], 2) * M_PI));
// atomicAdd(&(Matrixij[index + 2]), increment);
// }
//}
//
//// function using CUDA function "MatrixCreation" create influence matrix by pointer Matrixij[size*size]
//void CreateMatrix(double* Matrixij, double* BECoords, double* BE, int BeNumber, int BEInfoSize)
//{
// double* dev_a, * dev_b, * dev_c;
//
// cudaSetDevice(0);
//
// cudaMalloc((void**)&dev_a, BeNumber * BeNumber * sizeof(double));
// cudaMalloc((void**)&dev_b, 2 * BeNumber * sizeof(double));
// cudaMalloc((void**)&dev_c, BEInfoSize * sizeof(double));
// cudaMemcpy(dev_a, Matrixij, BeNumber * BeNumber * sizeof(double), cudaMemcpyHostToDevice);
// cudaMemcpy(dev_b, BECoords, BeNumber * 2 * sizeof(double), cudaMemcpyHostToDevice);
// cudaMemcpy(dev_c, BE, BEInfoSize * sizeof(double), cudaMemcpyHostToDevice);
//
// dim3 blockSize = dim3(BeNumber, 1, 1);
// dim3 gridSize = dim3(BeNumber, 1, 1);
//
// MatrixCreation << <gridSize, blockSize >> > (dev_a, dev_b, dev_c);
//
// cudaEvent_t syncEvent;
// cudaEventCreate(&syncEvent);
// cudaEventRecord(syncEvent, 0);
// cudaEventSynchronize(syncEvent);
//
// cudaMemcpy(Matrixij, dev_a, BeNumber * BeNumber * sizeof(double), cudaMemcpyDeviceToHost);
//}
//
//void CreateNodes(double* Matrixij, int size, double* Coeffs, int BeNumber, double* BE, int BEInfoSize)
//{
// double* dev_a, * dev_b, * dev_c;
//
// cudaSetDevice(0);
//
// cudaMalloc((void**)&dev_a, 3 * size * size * sizeof(double));
// cudaMalloc((void**)&dev_b, BeNumber * sizeof(double));
// cudaMalloc((void**)&dev_c, BEInfoSize * sizeof(double));
// cudaMemcpy(dev_a, Matrixij, 3 * size * size * sizeof(double), cudaMemcpyHostToDevice);
// cudaMemcpy(dev_b, Coeffs, BeNumber * sizeof(double), cudaMemcpyHostToDevice);
// cudaMemcpy(dev_c, BE, BEInfoSize * sizeof(double), cudaMemcpyHostToDevice);
//
// dim3 blockSize = dim3(size, 1, 1);
// dim3 gridSize = dim3(size, BeNumber, 1);
//
// CalculateNodes << < gridSize, blockSize >> > (dev_a, dev_b, dev_c);
//
// cudaEvent_t syncEvent;
// cudaEventCreate(&syncEvent);
// cudaEventRecord(syncEvent, 0);
// cudaEventSynchronize(syncEvent);
//
// cudaMemcpy(Matrixij, dev_a, 3 * size * size * sizeof(double), cudaMemcpyDeviceToHost);
//}
//
//void GetInputAndCalcInfluence()
//{
// double* Coords, * BE;
// double* Matrixij;
//
// int bediscr_array[] = { 5,10,15,20,25,30,35 };
// string input_file_name;
// string output_file_name;
//
// for (int i = 0; i < 7; i++)
// {
// int bediscr = bediscr_array[i];
// int CoordsNumber, BEInfoSize;
//
// input_file_name = "D:/Docs/article_03_20/data/shifted_coords" + to_string(bediscr) + ".txt";
// ifstream in;
// in.open(input_file_name);
//
// in >> CoordsNumber;
// Coords = new double[CoordsNumber];
//
// for (int i = 0; i < CoordsNumber; i++)
// in >> Coords[i];
//
// in.close();
//
// input_file_name = "D:/Docs/article_03_20/data/beinfo" + to_string(bediscr) + ".txt";
// in.open(input_file_name);
//
// in >> BEInfoSize;
// BE = new double[BEInfoSize];
//
// for (int i = 0; i < BEInfoSize; i++)
// in >> BE[i];
//
// in.close();
//
// int benumb = CoordsNumber / 2;
//
// Matrixij = new double[benumb * benumb];
//
// unsigned int start_time;
// unsigned int end_time;
// unsigned int search_time = 0;
//
// /////////////// CUDA method //////////////////////////
// CreateMatrix(Matrixij, Coords, BE, benumb, BEInfoSize);
// start_time = clock();
// CreateMatrix(Matrixij, Coords, BE, benumb, BEInfoSize);
// end_time = clock();
// search_time = end_time - start_time;
//
// output_file_name = "D:/Docs/article_03_20/CUDA_output/matr" + to_string(bediscr) + ".txt";
// ofstream out;
// out.open(output_file_name);
//
// for (int i = 0; i < benumb; i++)
// for (int j = 0; j < benumb; j++)
// out << Matrixij[i * benumb + j] << '\n';
// out << search_time;
// out.close();
//
// /////////////// sequential method ////////////////////
// start_time = clock();
// MatrixCreationSeq(Matrixij, Coords, BE, benumb);
// end_time = clock();
// search_time = end_time - start_time;
//
// output_file_name = "D:/Docs/article_03_20/SEQ_output/matr" + to_string(bediscr) + ".txt";
// out.open(output_file_name);
//
// for (int i = 0; i < benumb; i++)
// for (int j = 0; j < benumb; j++)
// out << Matrixij[i * benumb + j] << '\n';
// out << search_time;
// out.close();
//
// ///////////////////////////////////////////////////////
//
// delete(Matrixij);
// delete(BE);
// delete(Coords);
// }
//}
//
//void GetInputAndCalcDistr()
//{
// int bediscr_array[] = { 5,10,15,20,25,30,35 };
// int areadiscr_array[] = { 10, 20, 30, 40, 50 };
// double* BE, * Coefs;
// int CoefsNumb, BEInfoSize;
// string input_file_name;
// string output_file_name;
// int bediscr, areadiscr;
//
// for (int k = 0; k < 7; k++)
// {
// bediscr = bediscr_array[k];
// input_file_name = "D:/Docs/article_03_20/data/coefs" + to_string(bediscr) + ".txt";
// ifstream in;
// in.open(input_file_name);
//
// in >> CoefsNumb;
// Coefs = new double[CoefsNumb];
//
// for (int i = 0; i < CoefsNumb; i++)
// in >> Coefs[i];
//
// in.close();
//
// input_file_name = "D:/Docs/article_03_20/data/beinfo" + to_string(bediscr) + ".txt";
// in.open(input_file_name);
//
// in >> BEInfoSize;
// BE = new double[BEInfoSize];
//
// for (int i = 0; i < BEInfoSize; i++)
// in >> BE[i];
//
// in.close();
//
// for (int s = 0; s < 5; s++)
// {
// areadiscr = areadiscr_array[s];
// float discrx = (WIDTH - 2 * EPS) / (areadiscr - 1);
// float discry = (HEIGHT - 2 * EPS) / (areadiscr - 1);
//
// int matrixsize = areadiscr * areadiscr * 3;
// double* Matrixij = new double[matrixsize];
//
// for (int i = 0; i < areadiscr; i++)
// for (int j = 0; j < areadiscr; j++)
// {
// int idx = (i * areadiscr + j) * 3;
// Matrixij[idx] = -WIDTH / 2 + EPS + discrx * i;
// Matrixij[idx + 1] = -EPS - discry * j;
// Matrixij[idx + 2] = 0;
// }
//
// unsigned int start_time;
// unsigned int end_time;
// unsigned int search_time = 0;
//
// CreateNodes(Matrixij, areadiscr, Coefs, CoefsNumb, BE, BEInfoSize); // startup calculation to activate cuda memory
// start_time = clock();
// CreateNodes(Matrixij, areadiscr, Coefs, CoefsNumb, BE, BEInfoSize);
// end_time = clock();
// search_time = end_time - start_time;
//
// output_file_name = "D:/Docs/article_03_20/CUDA_Output/node" + to_string(bediscr) + "-" + to_string(areadiscr) + ".txt";
// ofstream out;
// out.open(output_file_name);
//
// for (int i = 0; i < matrixsize; i = i + 3)
// out << Matrixij[i] << " " << Matrixij[i + 1] << " " << Matrixij[i + 2] << '\n';
// out << search_time;
//
// out.close();
//
// /////////////// sequential method ////////////////////
// start_time = clock();
// CalculateNodesSeq(Matrixij, areadiscr, Coefs, CoefsNumb, BE);
// end_time = clock();
// search_time = end_time - start_time;
//
// output_file_name = "D:/Docs/article_03_20/SEQ_output/node" + to_string(bediscr) + "-" + to_string(areadiscr) + ".txt";
// out.open(output_file_name);
//
// for (int i = 0; i < matrixsize; i = i + 3)
// out << Matrixij[i] << " " << Matrixij[i + 1] << " " << Matrixij[i + 2] << '\n';
// out << search_time;
// out.close();
//
// ///////////////////////////////////////////////////////
//
// delete(Matrixij);
// }
//
// delete(Coefs);
// delete(BE);
// }
//} | .text
.file "NonLinThreeFF.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004c921_00000000-6_NonLinThreeFF.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "NonLinThreeFF.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
int main() {
int n;
int i, j, k;
printf("Please enter the size of matrix: \n");
scanf("%d", &n);
int *a, *b, *c;
cudaMallocHost((void**)&a, sizeof(int) * n * n);
cudaMallocHost((void**)&b, sizeof(int) * n * n);
cudaMallocHost((void**)&c, sizeof(int) * n * n);
for (i = 0; i < n; i++){
for (j = 0; j < n; j++){
a[i * n + j] = round(rand() % 2);
b[i * n + j] = round(rand() % 2);
}
}
printf("Start...\n");
clock_t start_time = clock();
for (i = 0; i < n; i++){
for (j = 0; j < n; j++){
int tmp = 0;
for (k = 0; k < n; k++)
tmp += a[i * n + k] * b[k * n + j];
c[i * n + j] = tmp;
}
}
clock_t end_time = clock();
printf("Time of calculating %dx%d matrix using CPU is %f ms.\n", n, n, static_cast<double>(end_time - start_time)/CLOCKS_PER_SEC*1000);
cudaFreeHost(a);
cudaFreeHost(b);
cudaFreeHost(c);
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
int main() {
int n;
int i, j, k;
printf("Please enter the size of matrix: \n");
scanf("%d", &n);
int *a, *b, *c;
cudaMallocHost((void**)&a, sizeof(int) * n * n);
cudaMallocHost((void**)&b, sizeof(int) * n * n);
cudaMallocHost((void**)&c, sizeof(int) * n * n);
for (i = 0; i < n; i++){
for (j = 0; j < n; j++){
a[i * n + j] = round(rand() % 2);
b[i * n + j] = round(rand() % 2);
}
}
printf("Start...\n");
clock_t start_time = clock();
for (i = 0; i < n; i++){
for (j = 0; j < n; j++){
int tmp = 0;
for (k = 0; k < n; k++)
tmp += a[i * n + k] * b[k * n + j];
c[i * n + j] = tmp;
}
}
clock_t end_time = clock();
printf("Time of calculating %dx%d matrix using CPU is %f ms.\n", n, n, static_cast<double>(end_time - start_time)/CLOCKS_PER_SEC*1000);
cudaFreeHost(a);
cudaFreeHost(b);
cudaFreeHost(c);
return 0;
} | .file "tmpxft_000e8064_00000000-6_noncuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Please enter the size of matrix: \n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%d"
.LC2:
.string "Start...\n"
.section .rodata.str1.8
.align 8
.LC5:
.string "Time of calculating %dx%d matrix using CPU is %f ms.\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 12(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movslq 12(%rsp), %rax
imulq %rax, %rax
leaq 0(,%rax,4), %rsi
leaq 16(%rsp), %rdi
call cudaMallocHost@PLT
movslq 12(%rsp), %rax
imulq %rax, %rax
leaq 0(,%rax,4), %rsi
leaq 24(%rsp), %rdi
call cudaMallocHost@PLT
movslq 12(%rsp), %rax
imulq %rax, %rax
leaq 0(,%rax,4), %rsi
leaq 32(%rsp), %rdi
call cudaMallocHost@PLT
movl $0, %ebp
cmpl $0, 12(%rsp)
jg .L4
.L5:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call clock@PLT
movq %rax, %rbp
movl $0, %r11d
cmpl $0, 12(%rsp)
jg .L8
.L9:
call clock@PLT
movl 12(%rsp), %edx
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC3(%rip), %xmm0
mulsd .LC4(%rip), %xmm0
movl %edx, %ecx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaFreeHost@PLT
movq 24(%rsp), %rdi
call cudaFreeHost@PLT
movq 32(%rsp), %rdi
call cudaFreeHost@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L27
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call rand@PLT
movl %ebp, %edx
imull 12(%rsp), %edx
addl %ebx, %edx
movslq %edx, %rdx
movl %eax, %ecx
shrl $31, %ecx
addl %ecx, %eax
andl $1, %eax
subl %ecx, %eax
movq 16(%rsp), %rcx
movl %eax, (%rcx,%rdx,4)
call rand@PLT
movl %ebp, %edx
imull 12(%rsp), %edx
addl %ebx, %edx
movslq %edx, %rdx
movl %eax, %ecx
shrl $31, %ecx
addl %ecx, %eax
andl $1, %eax
subl %ecx, %eax
movq 24(%rsp), %rcx
movl %eax, (%rcx,%rdx,4)
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jg .L6
.L7:
addl $1, %ebp
cmpl %ebp, 12(%rsp)
jle .L5
.L4:
movl $0, %ebx
cmpl $0, 12(%rsp)
jg .L6
jmp .L7
.L28:
movq 16(%rsp), %rsi
movl %edi, %edx
imull %r11d, %edx
movslq %edx, %rdx
leaq (%rsi,%rdx,4), %rax
movslq %edi, %r8
leaq 0(,%r8,4), %r9
movq 24(%rsp), %rcx
leaq (%rcx,%r10,4), %rcx
addq %r8, %rdx
leaq (%rsi,%rdx,4), %r8
movl $0, %esi
.L10:
movl (%rax), %edx
imull (%rcx), %edx
addl %edx, %esi
addq $4, %rax
addq %r9, %rcx
cmpq %r8, %rax
jne .L10
.L13:
imull %r11d, %edi
addl %ebx, %edi
movslq %edi, %rdi
movq 32(%rsp), %rax
movl %esi, (%rax,%rdi,4)
movl 12(%rsp), %edi
addq $1, %r10
cmpl %r10d, %edi
jle .L11
.L14:
movl %r10d, %ebx
movl $0, %esi
testl %edi, %edi
jg .L28
jmp .L13
.L11:
addl $1, %r11d
cmpl %r11d, 12(%rsp)
jle .L9
.L8:
movl 12(%rsp), %edi
movl $0, %r10d
testl %edi, %edi
jg .L14
jmp .L11
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1093567616
.align 8
.LC4:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
int main() {
int n;
int i, j, k;
printf("Please enter the size of matrix: \n");
scanf("%d", &n);
int *a, *b, *c;
cudaMallocHost((void**)&a, sizeof(int) * n * n);
cudaMallocHost((void**)&b, sizeof(int) * n * n);
cudaMallocHost((void**)&c, sizeof(int) * n * n);
for (i = 0; i < n; i++){
for (j = 0; j < n; j++){
a[i * n + j] = round(rand() % 2);
b[i * n + j] = round(rand() % 2);
}
}
printf("Start...\n");
clock_t start_time = clock();
for (i = 0; i < n; i++){
for (j = 0; j < n; j++){
int tmp = 0;
for (k = 0; k < n; k++)
tmp += a[i * n + k] * b[k * n + j];
c[i * n + j] = tmp;
}
}
clock_t end_time = clock();
printf("Time of calculating %dx%d matrix using CPU is %f ms.\n", n, n, static_cast<double>(end_time - start_time)/CLOCKS_PER_SEC*1000);
cudaFreeHost(a);
cudaFreeHost(b);
cudaFreeHost(c);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
int main() {
int n;
int i, j, k;
printf("Please enter the size of matrix: \n");
scanf("%d", &n);
int *a, *b, *c;
hipHostMalloc((void**)&a, sizeof(int) * n * n, hipHostMallocDefault);
hipHostMalloc((void**)&b, sizeof(int) * n * n, hipHostMallocDefault);
hipHostMalloc((void**)&c, sizeof(int) * n * n, hipHostMallocDefault);
for (i = 0; i < n; i++){
for (j = 0; j < n; j++){
a[i * n + j] = round(rand() % 2);
b[i * n + j] = round(rand() % 2);
}
}
printf("Start...\n");
clock_t start_time = clock();
for (i = 0; i < n; i++){
for (j = 0; j < n; j++){
int tmp = 0;
for (k = 0; k < n; k++)
tmp += a[i * n + k] * b[k * n + j];
c[i * n + j] = tmp;
}
}
clock_t end_time = clock();
printf("Time of calculating %dx%d matrix using CPU is %f ms.\n", n, n, static_cast<double>(end_time - start_time)/CLOCKS_PER_SEC*1000);
hipHostFree(a);
hipHostFree(b);
hipHostFree(c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
int main() {
int n;
int i, j, k;
printf("Please enter the size of matrix: \n");
scanf("%d", &n);
int *a, *b, *c;
hipHostMalloc((void**)&a, sizeof(int) * n * n, hipHostMallocDefault);
hipHostMalloc((void**)&b, sizeof(int) * n * n, hipHostMallocDefault);
hipHostMalloc((void**)&c, sizeof(int) * n * n, hipHostMallocDefault);
for (i = 0; i < n; i++){
for (j = 0; j < n; j++){
a[i * n + j] = round(rand() % 2);
b[i * n + j] = round(rand() % 2);
}
}
printf("Start...\n");
clock_t start_time = clock();
for (i = 0; i < n; i++){
for (j = 0; j < n; j++){
int tmp = 0;
for (k = 0; k < n; k++)
tmp += a[i * n + k] * b[k * n + j];
c[i * n + j] = tmp;
}
}
clock_t end_time = clock();
printf("Time of calculating %dx%d matrix using CPU is %f ms.\n", n, n, static_cast<double>(end_time - start_time)/CLOCKS_PER_SEC*1000);
hipHostFree(a);
hipHostFree(b);
hipHostFree(c);
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
int main() {
int n;
int i, j, k;
printf("Please enter the size of matrix: \n");
scanf("%d", &n);
int *a, *b, *c;
hipHostMalloc((void**)&a, sizeof(int) * n * n, hipHostMallocDefault);
hipHostMalloc((void**)&b, sizeof(int) * n * n, hipHostMallocDefault);
hipHostMalloc((void**)&c, sizeof(int) * n * n, hipHostMallocDefault);
for (i = 0; i < n; i++){
for (j = 0; j < n; j++){
a[i * n + j] = round(rand() % 2);
b[i * n + j] = round(rand() % 2);
}
}
printf("Start...\n");
clock_t start_time = clock();
for (i = 0; i < n; i++){
for (j = 0; j < n; j++){
int tmp = 0;
for (k = 0; k < n; k++)
tmp += a[i * n + k] * b[k * n + j];
c[i * n + j] = tmp;
}
}
clock_t end_time = clock();
printf("Time of calculating %dx%d matrix using CPU is %f ms.\n", n, n, static_cast<double>(end_time - start_time)/CLOCKS_PER_SEC*1000);
hipHostFree(a);
hipHostFree(b);
hipHostFree(c);
return 0;
} | .text
.file "noncuda.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI0_1:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
leaq 4(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 4(%rsp), %rsi
imulq %rsi, %rsi
shlq $2, %rsi
leaq 16(%rsp), %rdi
xorl %edx, %edx
callq hipHostMalloc
movslq 4(%rsp), %rsi
imulq %rsi, %rsi
shlq $2, %rsi
leaq 8(%rsp), %rdi
xorl %edx, %edx
callq hipHostMalloc
movslq 4(%rsp), %rsi
imulq %rsi, %rsi
shlq $2, %rsi
leaq 24(%rsp), %rdi
xorl %edx, %edx
callq hipHostMalloc
cmpl $0, 4(%rsp)
jg .LBB0_1
.LBB0_5: # %._crit_edge35
movl $.Lstr.1, %edi
callq puts@PLT
callq clock
movq %rax, %rbx
cmpl $0, 4(%rsp)
jle .LBB0_15
# %bb.6: # %.preheader31.lr.ph
xorl %eax, %eax
movq 24(%rsp), %rcx
jmp .LBB0_7
.p2align 4, 0x90
.LBB0_4: # %._crit_edge
# in Loop: Header=BB0_1 Depth=1
incl %ebx
cmpl 4(%rsp), %ebx
jge .LBB0_5
.LBB0_1: # %.preheader32
# =>This Loop Header: Depth=1
# Child Loop BB0_3 Depth 2
cmpl $0, 4(%rsp)
jle .LBB0_4
# %bb.2: # %.lr.ph.preheader
# in Loop: Header=BB0_1 Depth=1
movslq %ebx, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_3: # %.lr.ph
# Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
andl $-2, %ecx
subl %ecx, %eax
movq 16(%rsp), %rcx
movslq 4(%rsp), %rdx
imulq %r14, %rdx
addq %r15, %rdx
movl %eax, (%rcx,%rdx,4)
callq rand
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
andl $-2, %ecx
subl %ecx, %eax
movq 8(%rsp), %rcx
movslq 4(%rsp), %rdx
imulq %r14, %rdx
addq %r15, %rdx
movl %eax, (%rcx,%rdx,4)
incq %r15
cmpl 4(%rsp), %r15d
jl .LBB0_3
jmp .LBB0_4
.p2align 4, 0x90
.LBB0_14: # %._crit_edge41
# in Loop: Header=BB0_7 Depth=1
incl %eax
cmpl 4(%rsp), %eax
jge .LBB0_15
.LBB0_7: # %.preheader31
# =>This Loop Header: Depth=1
# Child Loop BB0_9 Depth 2
# Child Loop BB0_12 Depth 3
movl 4(%rsp), %esi
testl %esi, %esi
jle .LBB0_14
# %bb.8: # %.preheader.lr.ph
# in Loop: Header=BB0_7 Depth=1
movq 16(%rsp), %rdx
movq 8(%rsp), %rdi
xorl %r8d, %r8d
jmp .LBB0_9
.p2align 4, 0x90
.LBB0_10: # in Loop: Header=BB0_9 Depth=2
xorl %r10d, %r10d
.LBB0_13: # %._crit_edge39
# in Loop: Header=BB0_9 Depth=2
imull %eax, %esi
movslq %esi, %rsi
leaq (%rcx,%r8,4), %r9
movl %r10d, (%r9,%rsi,4)
incq %r8
movslq 4(%rsp), %rsi
addq $4, %rdi
cmpq %rsi, %r8
jge .LBB0_14
.LBB0_9: # %.preheader
# Parent Loop BB0_7 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_12 Depth 3
testl %esi, %esi
jle .LBB0_10
# %bb.11: # %.lr.ph38
# in Loop: Header=BB0_9 Depth=2
movl %esi, %r9d
movl %eax, %r10d
imull %esi, %r10d
leaq (%rdx,%r10,4), %r11
leaq (,%r9,4), %r14
xorl %r15d, %r15d
movq %rdi, %r12
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB0_12: # Parent Loop BB0_7 Depth=1
# Parent Loop BB0_9 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r12), %ebp
imull (%r11,%r15,4), %ebp
addl %ebp, %r10d
incq %r15
addq %r14, %r12
cmpq %r15, %r9
jne .LBB0_12
jmp .LBB0_13
.LBB0_15: # %._crit_edge43
callq clock
movl 4(%rsp), %edx
subq %rbx, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI0_0(%rip), %xmm0
mulsd .LCPI0_1(%rip), %xmm0
movl $.L.str.3, %edi
movl %edx, %esi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipHostFree
movq 8(%rsp), %rdi
callq hipHostFree
movq 24(%rsp), %rdi
callq hipHostFree
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Time of calculating %dx%d matrix using CPU is %f ms.\n"
.size .L.str.3, 54
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Please enter the size of matrix: "
.size .Lstr, 34
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Start..."
.size .Lstr.1, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e8064_00000000-6_noncuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Please enter the size of matrix: \n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%d"
.LC2:
.string "Start...\n"
.section .rodata.str1.8
.align 8
.LC5:
.string "Time of calculating %dx%d matrix using CPU is %f ms.\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 12(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movslq 12(%rsp), %rax
imulq %rax, %rax
leaq 0(,%rax,4), %rsi
leaq 16(%rsp), %rdi
call cudaMallocHost@PLT
movslq 12(%rsp), %rax
imulq %rax, %rax
leaq 0(,%rax,4), %rsi
leaq 24(%rsp), %rdi
call cudaMallocHost@PLT
movslq 12(%rsp), %rax
imulq %rax, %rax
leaq 0(,%rax,4), %rsi
leaq 32(%rsp), %rdi
call cudaMallocHost@PLT
movl $0, %ebp
cmpl $0, 12(%rsp)
jg .L4
.L5:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call clock@PLT
movq %rax, %rbp
movl $0, %r11d
cmpl $0, 12(%rsp)
jg .L8
.L9:
call clock@PLT
movl 12(%rsp), %edx
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC3(%rip), %xmm0
mulsd .LC4(%rip), %xmm0
movl %edx, %ecx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaFreeHost@PLT
movq 24(%rsp), %rdi
call cudaFreeHost@PLT
movq 32(%rsp), %rdi
call cudaFreeHost@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L27
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call rand@PLT
movl %ebp, %edx
imull 12(%rsp), %edx
addl %ebx, %edx
movslq %edx, %rdx
movl %eax, %ecx
shrl $31, %ecx
addl %ecx, %eax
andl $1, %eax
subl %ecx, %eax
movq 16(%rsp), %rcx
movl %eax, (%rcx,%rdx,4)
call rand@PLT
movl %ebp, %edx
imull 12(%rsp), %edx
addl %ebx, %edx
movslq %edx, %rdx
movl %eax, %ecx
shrl $31, %ecx
addl %ecx, %eax
andl $1, %eax
subl %ecx, %eax
movq 24(%rsp), %rcx
movl %eax, (%rcx,%rdx,4)
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jg .L6
.L7:
addl $1, %ebp
cmpl %ebp, 12(%rsp)
jle .L5
.L4:
movl $0, %ebx
cmpl $0, 12(%rsp)
jg .L6
jmp .L7
.L28:
movq 16(%rsp), %rsi
movl %edi, %edx
imull %r11d, %edx
movslq %edx, %rdx
leaq (%rsi,%rdx,4), %rax
movslq %edi, %r8
leaq 0(,%r8,4), %r9
movq 24(%rsp), %rcx
leaq (%rcx,%r10,4), %rcx
addq %r8, %rdx
leaq (%rsi,%rdx,4), %r8
movl $0, %esi
.L10:
movl (%rax), %edx
imull (%rcx), %edx
addl %edx, %esi
addq $4, %rax
addq %r9, %rcx
cmpq %r8, %rax
jne .L10
.L13:
imull %r11d, %edi
addl %ebx, %edi
movslq %edi, %rdi
movq 32(%rsp), %rax
movl %esi, (%rax,%rdi,4)
movl 12(%rsp), %edi
addq $1, %r10
cmpl %r10d, %edi
jle .L11
.L14:
movl %r10d, %ebx
movl $0, %esi
testl %edi, %edi
jg .L28
jmp .L13
.L11:
addl $1, %r11d
cmpl %r11d, 12(%rsp)
jle .L9
.L8:
movl 12(%rsp), %edi
movl $0, %r10d
testl %edi, %edi
jg .L14
jmp .L11
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1093567616
.align 8
.LC4:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "noncuda.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI0_1:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
leaq 4(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 4(%rsp), %rsi
imulq %rsi, %rsi
shlq $2, %rsi
leaq 16(%rsp), %rdi
xorl %edx, %edx
callq hipHostMalloc
movslq 4(%rsp), %rsi
imulq %rsi, %rsi
shlq $2, %rsi
leaq 8(%rsp), %rdi
xorl %edx, %edx
callq hipHostMalloc
movslq 4(%rsp), %rsi
imulq %rsi, %rsi
shlq $2, %rsi
leaq 24(%rsp), %rdi
xorl %edx, %edx
callq hipHostMalloc
cmpl $0, 4(%rsp)
jg .LBB0_1
.LBB0_5: # %._crit_edge35
movl $.Lstr.1, %edi
callq puts@PLT
callq clock
movq %rax, %rbx
cmpl $0, 4(%rsp)
jle .LBB0_15
# %bb.6: # %.preheader31.lr.ph
xorl %eax, %eax
movq 24(%rsp), %rcx
jmp .LBB0_7
.p2align 4, 0x90
.LBB0_4: # %._crit_edge
# in Loop: Header=BB0_1 Depth=1
incl %ebx
cmpl 4(%rsp), %ebx
jge .LBB0_5
.LBB0_1: # %.preheader32
# =>This Loop Header: Depth=1
# Child Loop BB0_3 Depth 2
cmpl $0, 4(%rsp)
jle .LBB0_4
# %bb.2: # %.lr.ph.preheader
# in Loop: Header=BB0_1 Depth=1
movslq %ebx, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_3: # %.lr.ph
# Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
andl $-2, %ecx
subl %ecx, %eax
movq 16(%rsp), %rcx
movslq 4(%rsp), %rdx
imulq %r14, %rdx
addq %r15, %rdx
movl %eax, (%rcx,%rdx,4)
callq rand
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
andl $-2, %ecx
subl %ecx, %eax
movq 8(%rsp), %rcx
movslq 4(%rsp), %rdx
imulq %r14, %rdx
addq %r15, %rdx
movl %eax, (%rcx,%rdx,4)
incq %r15
cmpl 4(%rsp), %r15d
jl .LBB0_3
jmp .LBB0_4
.p2align 4, 0x90
.LBB0_14: # %._crit_edge41
# in Loop: Header=BB0_7 Depth=1
incl %eax
cmpl 4(%rsp), %eax
jge .LBB0_15
.LBB0_7: # %.preheader31
# =>This Loop Header: Depth=1
# Child Loop BB0_9 Depth 2
# Child Loop BB0_12 Depth 3
movl 4(%rsp), %esi
testl %esi, %esi
jle .LBB0_14
# %bb.8: # %.preheader.lr.ph
# in Loop: Header=BB0_7 Depth=1
movq 16(%rsp), %rdx
movq 8(%rsp), %rdi
xorl %r8d, %r8d
jmp .LBB0_9
.p2align 4, 0x90
.LBB0_10: # in Loop: Header=BB0_9 Depth=2
xorl %r10d, %r10d
.LBB0_13: # %._crit_edge39
# in Loop: Header=BB0_9 Depth=2
imull %eax, %esi
movslq %esi, %rsi
leaq (%rcx,%r8,4), %r9
movl %r10d, (%r9,%rsi,4)
incq %r8
movslq 4(%rsp), %rsi
addq $4, %rdi
cmpq %rsi, %r8
jge .LBB0_14
.LBB0_9: # %.preheader
# Parent Loop BB0_7 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_12 Depth 3
testl %esi, %esi
jle .LBB0_10
# %bb.11: # %.lr.ph38
# in Loop: Header=BB0_9 Depth=2
movl %esi, %r9d
movl %eax, %r10d
imull %esi, %r10d
leaq (%rdx,%r10,4), %r11
leaq (,%r9,4), %r14
xorl %r15d, %r15d
movq %rdi, %r12
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB0_12: # Parent Loop BB0_7 Depth=1
# Parent Loop BB0_9 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r12), %ebp
imull (%r11,%r15,4), %ebp
addl %ebp, %r10d
incq %r15
addq %r14, %r12
cmpq %r15, %r9
jne .LBB0_12
jmp .LBB0_13
.LBB0_15: # %._crit_edge43
callq clock
movl 4(%rsp), %edx
subq %rbx, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI0_0(%rip), %xmm0
mulsd .LCPI0_1(%rip), %xmm0
movl $.L.str.3, %edi
movl %edx, %esi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipHostFree
movq 8(%rsp), %rdi
callq hipHostFree
movq 24(%rsp), %rdi
callq hipHostFree
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Time of calculating %dx%d matrix using CPU is %f ms.\n"
.size .L.str.3, 54
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Please enter the size of matrix: "
.size .Lstr, 34
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Start..."
.size .Lstr.1, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void apply_gaussian(const unsigned char *input_channel, unsigned char *output_channel,
const unsigned int width, const unsigned int height, const float *kernel, const unsigned int filter_width) {
const unsigned int row = threadIdx.y + blockIdx.y * blockDim.y;
const unsigned int col = threadIdx.x + blockIdx.x * blockDim.x;
if(row < height && col < width) {
const int filter_half = filter_width / 2;
float result = 0.0;
for(int i = -filter_half; i <= filter_half; i++) {
for(int j = -filter_half; j <= filter_half; j++) {
const unsigned int y = max(0, min(height - 1, row + i));
const unsigned int x = max(0, min(width - 1, col + j));
const float w = kernel[(j + filter_half) + (i + filter_half) * filter_width];
result += w * input_channel[x + y * width];
}
}
output_channel[col + row * width] = static_cast<unsigned char>(result);
}
} | code for sm_80
Function : _Z14apply_gaussianPKhPhjjPKfj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R3, R2, c[0x0][0x0], R5 ; /* 0x0000000002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R3, c[0x0][0x170], P0 ; /* 0x00005c0003007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff067624 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R29, RZ, RZ, RZ ; /* 0x000000ffff1d7224 */
/* 0x000fc600078e00ff */
/*00d0*/ SHF.R.U32.HI R2, RZ, 0x1, R6 ; /* 0x00000001ff027819 */
/* 0x000fca0000011606 */
/*00e0*/ IMAD.MOV R5, RZ, RZ, -R2 ; /* 0x000000ffff057224 */
/* 0x000fca00078e0a02 */
/*00f0*/ ISETP.GE.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fda0003f06270 */
/*0100*/ @!P0 BRA 0x7d0 ; /* 0x000006c000008947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R8, -R2, 0x1, RZ ; /* 0x0000000102087810 */
/* 0x000fe20007ffe1ff */
/*0120*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe20000000a00 */
/*0130*/ LOP3.LUT R6, R6, 0xfffffffe, RZ, 0xc0, !PT ; /* 0xfffffffe06067812 */
/* 0x000fe200078ec0ff */
/*0140*/ UIADD3 UR5, UR6, -0x1, URZ ; /* 0xffffffff06057890 */
/* 0x000fe2000fffe03f */
/*0150*/ IMAD.IADD R19, R3.reuse, 0x1, -R2 ; /* 0x0000000103137824 */
/* 0x040fe200078e0a02 */
/*0160*/ IADD3 R7, -R2, 0x3, RZ ; /* 0x0000000302077810 */
/* 0x000fe20007ffe1ff */
/*0170*/ IMAD.IADD R11, R3, 0x1, R8 ; /* 0x00000001030b7824 */
/* 0x000fe200078e0208 */
/*0180*/ LOP3.LUT R18, R6, 0x1, RZ, 0xfc, !PT ; /* 0x0000000106127812 */
/* 0x000fe200078efcff */
/*0190*/ IMAD.MOV.U32 R29, RZ, RZ, RZ ; /* 0x000000ffff1d7224 */
/* 0x000fe200078e00ff */
/*01a0*/ IADD3 R9, R2, 0x3, RZ ; /* 0x0000000302097810 */
/* 0x000fe20007ffe0ff */
/*01b0*/ UIADD3 UR4, UR7, -0x1, URZ ; /* 0xffffffff07047890 */
/* 0x000fe2000fffe03f */
/*01c0*/ IADD3 R24, R11, 0x1, RZ ; /* 0x000000010b187810 */
/* 0x000fc40007ffe0ff */
/*01d0*/ IADD3 R10, R3, 0x3, RZ ; /* 0x00000003030a7810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ IMNMX.U32 R11, R11, UR5, PT ; /* 0x000000050b0b7c17 */
/* 0x000fe4000b800000 */
/*01f0*/ LOP3.LUT R18, R18, 0x3, RZ, 0xc0, !PT ; /* 0x0000000312127812 */
/* 0x000fe400078ec0ff */
/*0200*/ IMNMX.U32 R19, R19, UR5, PT ; /* 0x0000000513137c17 */
/* 0x000fe4000b800000 */
/*0210*/ IMNMX.U32 R24, R24, UR5, PT ; /* 0x0000000518187c17 */
/* 0x000fe4000b800000 */
/*0220*/ IMAD.IADD R26, R0, 0x1, R5 ; /* 0x00000001001a7824 */
/* 0x000fe200078e0205 */
/*0230*/ ISETP.NE.AND P1, PT, R18, 0x1, PT ; /* 0x000000011200780c */
/* 0x000fc80003f25270 */
/*0240*/ IMNMX.U32 R26, R26, UR4, PT ; /* 0x000000041a1a7c17 */
/* 0x000fca000b800000 */
/*0250*/ IMAD R16, R26, c[0x0][0x170], R19 ; /* 0x00005c001a107a24 */
/* 0x000fc800078e0213 */
/*0260*/ @P1 IMAD R14, R26, c[0x0][0x170], R11 ; /* 0x00005c001a0e1a24 */
/* 0x000fe200078e020b */
/*0270*/ IADD3 R16, P2, R16, c[0x0][0x160], RZ ; /* 0x0000580010107a10 */
/* 0x000fe20007f5e0ff */
/*0280*/ @P1 IMAD R12, R26, c[0x0][0x170], R24 ; /* 0x00005c001a0c1a24 */
/* 0x000fc600078e0218 */
/*0290*/ @P1 IADD3 R14, P0, R14, c[0x0][0x160], RZ ; /* 0x000058000e0e1a10 */
/* 0x000fe20007f1e0ff */
/*02a0*/ IMAD.X R17, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff117624 */
/* 0x000fe200010e06ff */
/*02b0*/ @P1 IADD3 R12, P2, R12, c[0x0][0x160], RZ ; /* 0x000058000c0c1a10 */
/* 0x000fe20007f5e0ff */
/*02c0*/ IMAD.IADD R27, R2, 0x1, R5 ; /* 0x00000001021b7824 */
/* 0x000fe400078e0205 */
/*02d0*/ @P1 IMAD.X R15, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff0f1624 */
/* 0x000fe200000e06ff */
/*02e0*/ LDG.E.U8 R4, [R16.64] ; /* 0x0000000810047981 */
/* 0x0000a2000c1e1100 */
/*02f0*/ @P1 IMAD.X R13, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff0d1624 */
/* 0x000fe400010e06ff */
/*0300*/ IMAD R27, R27, c[0x0][0x180], RZ ; /* 0x000060001b1b7a24 */
/* 0x000fe200078e02ff */
/*0310*/ @P1 LDG.E.U8 R14, [R14.64] ; /* 0x000000080e0e1981 */
/* 0x000ee2000c1e1100 */
/*0320*/ IMAD.MOV.U32 R25, RZ, RZ, 0x4 ; /* 0x00000004ff197424 */
/* 0x000fc600078e00ff */
/*0330*/ @P1 LDG.E.U8 R12, [R12.64] ; /* 0x000000080c0c1981 */
/* 0x000f22000c1e1100 */
/*0340*/ @P1 IADD3 R20, R27.reuse, 0x1, RZ ; /* 0x000000011b141810 */
/* 0x040fe20007ffe0ff */
/*0350*/ IMAD.WIDE.U32 R22, R27.reuse, R25, c[0x0][0x178] ; /* 0x00005e001b167625 */
/* 0x040fe200078e0019 */
/*0360*/ @P1 IADD3 R28, R27, 0x2, RZ ; /* 0x000000021b1c1810 */
/* 0x000fc60007ffe0ff */
/*0370*/ @P1 IMAD.WIDE.U32 R20, R20, R25.reuse, c[0x0][0x178] ; /* 0x00005e0014141625 */
/* 0x080fe400078e0019 */
/*0380*/ LDG.E R22, [R22.64] ; /* 0x0000000816167981 */
/* 0x000f64000c1e1900 */
/*0390*/ @P1 IMAD.WIDE.U32 R16, R28, R25, c[0x0][0x178] ; /* 0x00005e001c101625 */
/* 0x001fe400078e0019 */
/*03a0*/ @P1 LDG.E R20, [R20.64] ; /* 0x0000000814141981 */
/* 0x000f68000c1e1900 */
/*03b0*/ @P1 LDG.E R16, [R16.64] ; /* 0x0000000810101981 */
/* 0x000f62000c1e1900 */
/*03c0*/ ISETP.GE.U32.AND P2, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fc40003f46070 */
/*03d0*/ ISETP.GE.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x000fe20003f06270 */
/*03e0*/ I2F.U16 R4, R4 ; /* 0x0000000400047306 */
/* 0x004f700000101000 */
/*03f0*/ @P1 I2F.U16 R14, R14 ; /* 0x0000000e000e1306 */
/* 0x008e300000101000 */
/*0400*/ @P1 I2F.U16 R12, R12 ; /* 0x0000000c000c1306 */
/* 0x010e620000101000 */
/*0410*/ FFMA R29, R4, R22, R29 ; /* 0x00000016041d7223 */
/* 0x020fc4000000001d */
/*0420*/ IMAD.MOV.U32 R22, RZ, RZ, R8 ; /* 0x000000ffff167224 */
/* 0x000fe400078e0008 */
/*0430*/ @P1 IMAD.MOV.U32 R22, RZ, RZ, R7 ; /* 0x000000ffff161224 */
/* 0x000fe400078e0007 */
/*0440*/ @P1 FFMA R13, R14, R20, R29 ; /* 0x000000140e0d1223 */
/* 0x001fc8000000001d */
/*0450*/ @P1 FFMA R29, R12, R16, R13 ; /* 0x000000100c1d1223 */
/* 0x002fe2000000000d */
/*0460*/ @!P2 BRA 0x7b0 ; /* 0x000003400000a947 */
/* 0x000fea0003800000 */
/*0470*/ IADD3 R28, R27.reuse, R9, R22.reuse ; /* 0x000000091b1c7210 */
/* 0x140fe20007ffe016 */
/*0480*/ IMAD.IADD R4, R10, 0x1, R22.reuse ; /* 0x000000010a047824 */
/* 0x100fe200078e0216 */
/*0490*/ IADD3 R14, R27, R2, R22 ; /* 0x000000021b0e7210 */
/* 0x000fe40007ffe016 */
/*04a0*/ IADD3 R27, R22, -0x1, RZ ; /* 0xffffffff161b7810 */
/* 0x000fe40007ffe0ff */
/*04b0*/ IADD3 R12, R4, -0x3, RZ ; /* 0xfffffffd040c7810 */
/* 0x000fc80007ffe0ff */
/*04c0*/ IMNMX.U32 R13, R12, UR5, PT ; /* 0x000000050c0d7c17 */
/* 0x000fca000b800000 */
/*04d0*/ IMAD R13, R26, c[0x0][0x170], R13 ; /* 0x00005c001a0d7a24 */
/* 0x000fca00078e020d */
/*04e0*/ IADD3 R12, P1, R13, c[0x0][0x160], RZ ; /* 0x000058000d0c7a10 */
/* 0x000fca0007f3e0ff */
/*04f0*/ IMAD.X R13, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff0d7624 */
/* 0x000fca00008e06ff */
/*0500*/ LDG.E.U8 R20, [R12.64] ; /* 0x000000080c147981 */
/* 0x0000a2000c1e1100 */
/*0510*/ IMAD.WIDE.U32 R14, R14, R25, c[0x0][0x178] ; /* 0x00005e000e0e7625 */
/* 0x000fca00078e0019 */
/*0520*/ LDG.E R16, [R14.64] ; /* 0x000000080e107981 */
/* 0x0002e2000c1e1900 */
/*0530*/ IADD3 R17, R4.reuse, -0x2, RZ ; /* 0xfffffffe04117810 */
/* 0x040fe40007ffe0ff */
/*0540*/ IADD3 R22, R4, -0x1, RZ ; /* 0xffffffff04167810 */
/* 0x000fe40007ffe0ff */
/*0550*/ IMNMX.U32 R21, R17, UR5, PT ; /* 0x0000000511157c17 */
/* 0x000fe4000b800000 */
/*0560*/ IMNMX.U32 R23, R22, UR5, PT ; /* 0x0000000516177c17 */
/* 0x000fe4000b800000 */
/*0570*/ IMNMX.U32 R22, R4, UR5, PT ; /* 0x0000000504167c17 */
/* 0x000fe2000b800000 */
/*0580*/ IMAD R21, R26, c[0x0][0x170], R21 ; /* 0x00005c001a157a24 */
/* 0x000fc400078e0215 */
/*0590*/ IMAD R23, R26.reuse, c[0x0][0x170], R23 ; /* 0x00005c001a177a24 */
/* 0x040fe400078e0217 */
/*05a0*/ IMAD R22, R26, c[0x0][0x170], R22 ; /* 0x00005c001a167a24 */
/* 0x000fe200078e0216 */
/*05b0*/ IADD3 R12, P2, R21, c[0x0][0x160], RZ ; /* 0x00005800150c7a10 */
/* 0x001fe40007f5e0ff */
/*05c0*/ IADD3 R14, P1, R23, c[0x0][0x160], RZ ; /* 0x00005800170e7a10 */
/* 0x002fc60007f3e0ff */
/*05d0*/ IMAD.X R13, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff0d7624 */
/* 0x000fe400010e06ff */
/*05e0*/ IMAD.X R15, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff0f7624 */
/* 0x000fc600008e06ff */
/*05f0*/ LDG.E.U8 R12, [R12.64] ; /* 0x000000080c0c7981 */
/* 0x000128000c1e1100 */
/*0600*/ LDG.E.U8 R13, [R14.64] ; /* 0x000000080e0d7981 */
/* 0x001162000c1e1100 */
/*0610*/ I2F.U16 R17, R20 ; /* 0x0000001400117306 */
/* 0x0042e40000101000 */
/*0620*/ IADD3 R20, R28, -0x2, RZ ; /* 0xfffffffe1c147810 */
/* 0x002fe20007ffe0ff */
/*0630*/ FFMA R29, R17, R16, R29 ; /* 0x00000010111d7223 */
/* 0x008fe2000000001d */
/*0640*/ IADD3 R16, P2, R22, c[0x0][0x160], RZ ; /* 0x0000580016107a10 */
/* 0x000fca0007f5e0ff */
/*0650*/ IMAD.X R17, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff117624 */
/* 0x000fe400010e06ff */
/*0660*/ IMAD.WIDE.U32 R14, R20, R25.reuse, c[0x0][0x178] ; /* 0x00005e00140e7625 */
/* 0x081fe200078e0019 */
/*0670*/ IADD3 R20, R28, -0x1, RZ ; /* 0xffffffff1c147810 */
/* 0x000fe40007ffe0ff */
/*0680*/ LDG.E.U8 R16, [R16.64] ; /* 0x0000000810107981 */
/* 0x000ea6000c1e1100 */
/*0690*/ IMAD.WIDE.U32 R20, R20, R25.reuse, c[0x0][0x178] ; /* 0x00005e0014147625 */
/* 0x080fe200078e0019 */
/*06a0*/ LDG.E R14, [R14.64] ; /* 0x000000080e0e7981 */
/* 0x0000e6000c1e1900 */
/*06b0*/ IMAD.WIDE.U32 R22, R28, R25, c[0x0][0x178] ; /* 0x00005e001c167625 */
/* 0x000fc400078e0019 */
/*06c0*/ LDG.E R20, [R20.64] ; /* 0x0000000814147981 */
/* 0x000ee8000c1e1900 */
/*06d0*/ LDG.E R22, [R22.64] ; /* 0x0000000816167981 */
/* 0x000ee2000c1e1900 */
/*06e0*/ I2F.U16 R12, R12 ; /* 0x0000000c000c7306 */
/* 0x010ee20000101000 */
/*06f0*/ IADD3 R27, R27, 0x4, RZ ; /* 0x000000041b1b7810 */
/* 0x000fce0007ffe0ff */
/*0700*/ I2F.U16 R13, R13 ; /* 0x0000000d000d7306 */
/* 0x020e620000101000 */
/*0710*/ ISETP.GE.AND P1, PT, R27, R2, PT ; /* 0x000000021b00720c */
/* 0x000fe40003f26270 */
/*0720*/ IADD3 R15, R28, 0x4, RZ ; /* 0x000000041c0f7810 */
/* 0x001fe40007ffe0ff */
/*0730*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0740*/ I2F.U16 R16, R16 ; /* 0x0000001000107306 */
/* 0x004e220000101000 */
/*0750*/ FFMA R29, R12, R14, R29 ; /* 0x0000000e0c1d7223 */
/* 0x008fe2000000001d */
/*0760*/ IADD3 R14, R28, 0x1, RZ ; /* 0x000000011c0e7810 */
/* 0x000fc60007ffe0ff */
/*0770*/ FFMA R29, R13, R20, R29 ; /* 0x000000140d1d7223 */
/* 0x002fe4000000001d */
/*0780*/ IMAD.MOV.U32 R28, RZ, RZ, R15 ; /* 0x000000ffff1c7224 */
/* 0x000fe400078e000f */
/*0790*/ FFMA R29, R16, R22, R29 ; /* 0x00000016101d7223 */
/* 0x001fe2000000001d */
/*07a0*/ @!P1 BRA 0x4b0 ; /* 0xfffffd0000009947 */
/* 0x000fea000383ffff */
/*07b0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe20007ffe0ff */
/*07c0*/ @!P0 BRA 0x220 ; /* 0xfffffa5000008947 */
/* 0x000fea000383ffff */
/*07d0*/ F2I.U32.TRUNC.NTZ R29, R29 ; /* 0x0000001d001d7305 */
/* 0x000e22000020f000 */
/*07e0*/ IMAD R3, R0, c[0x0][0x170], R3 ; /* 0x00005c0000037a24 */
/* 0x000fca00078e0203 */
/*07f0*/ IADD3 R2, P0, R3, c[0x0][0x168], RZ ; /* 0x00005a0003027a10 */
/* 0x000fca0007f1e0ff */
/*0800*/ IMAD.X R3, RZ, RZ, c[0x0][0x16c], P0 ; /* 0x00005b00ff037624 */
/* 0x000fca00000e06ff */
/*0810*/ STG.E.U8 [R2.64], R29 ; /* 0x0000001d02007986 */
/* 0x001fe2000c101108 */
/*0820*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0830*/ BRA 0x830; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void apply_gaussian(const unsigned char *input_channel, unsigned char *output_channel,
const unsigned int width, const unsigned int height, const float *kernel, const unsigned int filter_width) {
const unsigned int row = threadIdx.y + blockIdx.y * blockDim.y;
const unsigned int col = threadIdx.x + blockIdx.x * blockDim.x;
if(row < height && col < width) {
const int filter_half = filter_width / 2;
float result = 0.0;
for(int i = -filter_half; i <= filter_half; i++) {
for(int j = -filter_half; j <= filter_half; j++) {
const unsigned int y = max(0, min(height - 1, row + i));
const unsigned int x = max(0, min(width - 1, col + j));
const float w = kernel[(j + filter_half) + (i + filter_half) * filter_width];
result += w * input_channel[x + y * width];
}
}
output_channel[col + row * width] = static_cast<unsigned char>(result);
}
} | .file "tmpxft_001b7d9d_00000000-6_gaussian.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z14apply_gaussianPKhPhjjPKfjPKhPhjjPKfj
.type _Z43__device_stub__Z14apply_gaussianPKhPhjjPKfjPKhPhjjPKfj, @function
_Z43__device_stub__Z14apply_gaussianPKhPhjjPKfjPKhPhjjPKfj:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14apply_gaussianPKhPhjjPKfj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z14apply_gaussianPKhPhjjPKfjPKhPhjjPKfj, .-_Z43__device_stub__Z14apply_gaussianPKhPhjjPKfjPKhPhjjPKfj
.globl _Z14apply_gaussianPKhPhjjPKfj
.type _Z14apply_gaussianPKhPhjjPKfj, @function
_Z14apply_gaussianPKhPhjjPKfj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z14apply_gaussianPKhPhjjPKfjPKhPhjjPKfj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14apply_gaussianPKhPhjjPKfj, .-_Z14apply_gaussianPKhPhjjPKfj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14apply_gaussianPKhPhjjPKfj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14apply_gaussianPKhPhjjPKfj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void apply_gaussian(const unsigned char *input_channel, unsigned char *output_channel,
const unsigned int width, const unsigned int height, const float *kernel, const unsigned int filter_width) {
const unsigned int row = threadIdx.y + blockIdx.y * blockDim.y;
const unsigned int col = threadIdx.x + blockIdx.x * blockDim.x;
if(row < height && col < width) {
const int filter_half = filter_width / 2;
float result = 0.0;
for(int i = -filter_half; i <= filter_half; i++) {
for(int j = -filter_half; j <= filter_half; j++) {
const unsigned int y = max(0, min(height - 1, row + i));
const unsigned int x = max(0, min(width - 1, col + j));
const float w = kernel[(j + filter_half) + (i + filter_half) * filter_width];
result += w * input_channel[x + y * width];
}
}
output_channel[col + row * width] = static_cast<unsigned char>(result);
}
} | #include <hip/hip_runtime.h>
__global__ void apply_gaussian(const unsigned char *input_channel, unsigned char *output_channel,
const unsigned int width, const unsigned int height, const float *kernel, const unsigned int filter_width) {
const unsigned int row = threadIdx.y + blockIdx.y * blockDim.y;
const unsigned int col = threadIdx.x + blockIdx.x * blockDim.x;
if(row < height && col < width) {
const int filter_half = filter_width / 2;
float result = 0.0;
for(int i = -filter_half; i <= filter_half; i++) {
for(int j = -filter_half; j <= filter_half; j++) {
const unsigned int y = max(0, min(height - 1, row + i));
const unsigned int x = max(0, min(width - 1, col + j));
const float w = kernel[(j + filter_half) + (i + filter_half) * filter_width];
result += w * input_channel[x + y * width];
}
}
output_channel[col + row * width] = static_cast<unsigned char>(result);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void apply_gaussian(const unsigned char *input_channel, unsigned char *output_channel,
const unsigned int width, const unsigned int height, const float *kernel, const unsigned int filter_width) {
const unsigned int row = threadIdx.y + blockIdx.y * blockDim.y;
const unsigned int col = threadIdx.x + blockIdx.x * blockDim.x;
if(row < height && col < width) {
const int filter_half = filter_width / 2;
float result = 0.0;
for(int i = -filter_half; i <= filter_half; i++) {
for(int j = -filter_half; j <= filter_half; j++) {
const unsigned int y = max(0, min(height - 1, row + i));
const unsigned int x = max(0, min(width - 1, col + j));
const float w = kernel[(j + filter_half) + (i + filter_half) * filter_width];
result += w * input_channel[x + y * width];
}
}
output_channel[col + row * width] = static_cast<unsigned char>(result);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14apply_gaussianPKhPhjjPKfj
.globl _Z14apply_gaussianPKhPhjjPKfj
.p2align 8
.type _Z14apply_gaussianPKhPhjjPKfj,@function
_Z14apply_gaussianPKhPhjjPKfj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
s_mul_i32 s14, s14, s2
v_add_nc_u32_e32 v1, s14, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_u32_e32 vcc_lo, s5, v0
v_cmp_gt_u32_e64 s2, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_7
s_clause 0x2
s_load_b32 s10, s[0:1], 0x20
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[6:7], s[0:1], 0x18
v_mov_b32_e32 v2, 0
s_mov_b32 s9, 0
s_add_i32 s5, s5, -1
s_add_i32 s12, s4, -1
s_mov_b32 s15, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s11, s10, 1
s_or_b32 s14, s10, 1
v_subrev_nc_u32_e32 v3, s11, v1
s_sub_i32 s13, 0, s11
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v4, s13, v0
s_mov_b32 s8, s15
s_mov_b32 s16, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v4, s5, v4
v_cvt_f64_u32_e32 v[4:5], v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_f64 v[4:5], v[4:5], 0
v_cvt_u32_f64_e32 v4, v[4:5]
v_mov_b32_e32 v5, v3
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v4, v4, s4
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_min_u32_e32 v6, s12, v5
s_lshl_b64 s[18:19], s[8:9], 2
s_add_u32 s18, s6, s18
s_addc_u32 s19, s7, s19
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_cvt_f64_u32_e32 v[6:7], v6
s_load_b32 s17, s[18:19], 0x0
s_add_i32 s16, s16, -1
s_add_i32 s8, s8, 1
s_cmp_eq_u32 s16, 0
v_max_f64 v[6:7], v[6:7], 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f64_e32 v6, v[6:7]
v_add_nc_u32_e32 v6, v4, v6
global_load_u8 v6, v6, s[2:3]
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v6, v6
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_dual_fmac_f32 v2, s17, v6 :: v_dual_add_nc_u32 v5, 1, v5
s_cbranch_scc0 .LBB0_3
s_add_i32 s8, s13, 1
s_add_i32 s15, s15, s10
s_cmp_eq_u32 s13, s11
s_cbranch_scc1 .LBB0_6
s_mov_b32 s13, s8
s_branch .LBB0_2
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x8
v_mad_u64_u32 v[3:4], null, v0, s4, v[1:2]
v_cvt_i32_f32_e32 v0, v2
s_waitcnt lgkmcnt(0)
global_store_b8 v3, v0, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14apply_gaussianPKhPhjjPKfj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14apply_gaussianPKhPhjjPKfj, .Lfunc_end0-_Z14apply_gaussianPKhPhjjPKfj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14apply_gaussianPKhPhjjPKfj
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z14apply_gaussianPKhPhjjPKfj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void apply_gaussian(const unsigned char *input_channel, unsigned char *output_channel,
const unsigned int width, const unsigned int height, const float *kernel, const unsigned int filter_width) {
const unsigned int row = threadIdx.y + blockIdx.y * blockDim.y;
const unsigned int col = threadIdx.x + blockIdx.x * blockDim.x;
if(row < height && col < width) {
const int filter_half = filter_width / 2;
float result = 0.0;
for(int i = -filter_half; i <= filter_half; i++) {
for(int j = -filter_half; j <= filter_half; j++) {
const unsigned int y = max(0, min(height - 1, row + i));
const unsigned int x = max(0, min(width - 1, col + j));
const float w = kernel[(j + filter_half) + (i + filter_half) * filter_width];
result += w * input_channel[x + y * width];
}
}
output_channel[col + row * width] = static_cast<unsigned char>(result);
}
} | .text
.file "gaussian.hip"
.globl _Z29__device_stub__apply_gaussianPKhPhjjPKfj # -- Begin function _Z29__device_stub__apply_gaussianPKhPhjjPKfj
.p2align 4, 0x90
.type _Z29__device_stub__apply_gaussianPKhPhjjPKfj,@function
_Z29__device_stub__apply_gaussianPKhPhjjPKfj: # @_Z29__device_stub__apply_gaussianPKhPhjjPKfj
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movq %r8, 72(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14apply_gaussianPKhPhjjPKfj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z29__device_stub__apply_gaussianPKhPhjjPKfj, .Lfunc_end0-_Z29__device_stub__apply_gaussianPKhPhjjPKfj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14apply_gaussianPKhPhjjPKfj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14apply_gaussianPKhPhjjPKfj,@object # @_Z14apply_gaussianPKhPhjjPKfj
.section .rodata,"a",@progbits
.globl _Z14apply_gaussianPKhPhjjPKfj
.p2align 3, 0x0
_Z14apply_gaussianPKhPhjjPKfj:
.quad _Z29__device_stub__apply_gaussianPKhPhjjPKfj
.size _Z14apply_gaussianPKhPhjjPKfj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14apply_gaussianPKhPhjjPKfj"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__apply_gaussianPKhPhjjPKfj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14apply_gaussianPKhPhjjPKfj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14apply_gaussianPKhPhjjPKfj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R3, R2, c[0x0][0x0], R5 ; /* 0x0000000002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R3, c[0x0][0x170], P0 ; /* 0x00005c0003007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff067624 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R29, RZ, RZ, RZ ; /* 0x000000ffff1d7224 */
/* 0x000fc600078e00ff */
/*00d0*/ SHF.R.U32.HI R2, RZ, 0x1, R6 ; /* 0x00000001ff027819 */
/* 0x000fca0000011606 */
/*00e0*/ IMAD.MOV R5, RZ, RZ, -R2 ; /* 0x000000ffff057224 */
/* 0x000fca00078e0a02 */
/*00f0*/ ISETP.GE.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fda0003f06270 */
/*0100*/ @!P0 BRA 0x7d0 ; /* 0x000006c000008947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R8, -R2, 0x1, RZ ; /* 0x0000000102087810 */
/* 0x000fe20007ffe1ff */
/*0120*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe20000000a00 */
/*0130*/ LOP3.LUT R6, R6, 0xfffffffe, RZ, 0xc0, !PT ; /* 0xfffffffe06067812 */
/* 0x000fe200078ec0ff */
/*0140*/ UIADD3 UR5, UR6, -0x1, URZ ; /* 0xffffffff06057890 */
/* 0x000fe2000fffe03f */
/*0150*/ IMAD.IADD R19, R3.reuse, 0x1, -R2 ; /* 0x0000000103137824 */
/* 0x040fe200078e0a02 */
/*0160*/ IADD3 R7, -R2, 0x3, RZ ; /* 0x0000000302077810 */
/* 0x000fe20007ffe1ff */
/*0170*/ IMAD.IADD R11, R3, 0x1, R8 ; /* 0x00000001030b7824 */
/* 0x000fe200078e0208 */
/*0180*/ LOP3.LUT R18, R6, 0x1, RZ, 0xfc, !PT ; /* 0x0000000106127812 */
/* 0x000fe200078efcff */
/*0190*/ IMAD.MOV.U32 R29, RZ, RZ, RZ ; /* 0x000000ffff1d7224 */
/* 0x000fe200078e00ff */
/*01a0*/ IADD3 R9, R2, 0x3, RZ ; /* 0x0000000302097810 */
/* 0x000fe20007ffe0ff */
/*01b0*/ UIADD3 UR4, UR7, -0x1, URZ ; /* 0xffffffff07047890 */
/* 0x000fe2000fffe03f */
/*01c0*/ IADD3 R24, R11, 0x1, RZ ; /* 0x000000010b187810 */
/* 0x000fc40007ffe0ff */
/*01d0*/ IADD3 R10, R3, 0x3, RZ ; /* 0x00000003030a7810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ IMNMX.U32 R11, R11, UR5, PT ; /* 0x000000050b0b7c17 */
/* 0x000fe4000b800000 */
/*01f0*/ LOP3.LUT R18, R18, 0x3, RZ, 0xc0, !PT ; /* 0x0000000312127812 */
/* 0x000fe400078ec0ff */
/*0200*/ IMNMX.U32 R19, R19, UR5, PT ; /* 0x0000000513137c17 */
/* 0x000fe4000b800000 */
/*0210*/ IMNMX.U32 R24, R24, UR5, PT ; /* 0x0000000518187c17 */
/* 0x000fe4000b800000 */
/*0220*/ IMAD.IADD R26, R0, 0x1, R5 ; /* 0x00000001001a7824 */
/* 0x000fe200078e0205 */
/*0230*/ ISETP.NE.AND P1, PT, R18, 0x1, PT ; /* 0x000000011200780c */
/* 0x000fc80003f25270 */
/*0240*/ IMNMX.U32 R26, R26, UR4, PT ; /* 0x000000041a1a7c17 */
/* 0x000fca000b800000 */
/*0250*/ IMAD R16, R26, c[0x0][0x170], R19 ; /* 0x00005c001a107a24 */
/* 0x000fc800078e0213 */
/*0260*/ @P1 IMAD R14, R26, c[0x0][0x170], R11 ; /* 0x00005c001a0e1a24 */
/* 0x000fe200078e020b */
/*0270*/ IADD3 R16, P2, R16, c[0x0][0x160], RZ ; /* 0x0000580010107a10 */
/* 0x000fe20007f5e0ff */
/*0280*/ @P1 IMAD R12, R26, c[0x0][0x170], R24 ; /* 0x00005c001a0c1a24 */
/* 0x000fc600078e0218 */
/*0290*/ @P1 IADD3 R14, P0, R14, c[0x0][0x160], RZ ; /* 0x000058000e0e1a10 */
/* 0x000fe20007f1e0ff */
/*02a0*/ IMAD.X R17, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff117624 */
/* 0x000fe200010e06ff */
/*02b0*/ @P1 IADD3 R12, P2, R12, c[0x0][0x160], RZ ; /* 0x000058000c0c1a10 */
/* 0x000fe20007f5e0ff */
/*02c0*/ IMAD.IADD R27, R2, 0x1, R5 ; /* 0x00000001021b7824 */
/* 0x000fe400078e0205 */
/*02d0*/ @P1 IMAD.X R15, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff0f1624 */
/* 0x000fe200000e06ff */
/*02e0*/ LDG.E.U8 R4, [R16.64] ; /* 0x0000000810047981 */
/* 0x0000a2000c1e1100 */
/*02f0*/ @P1 IMAD.X R13, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff0d1624 */
/* 0x000fe400010e06ff */
/*0300*/ IMAD R27, R27, c[0x0][0x180], RZ ; /* 0x000060001b1b7a24 */
/* 0x000fe200078e02ff */
/*0310*/ @P1 LDG.E.U8 R14, [R14.64] ; /* 0x000000080e0e1981 */
/* 0x000ee2000c1e1100 */
/*0320*/ IMAD.MOV.U32 R25, RZ, RZ, 0x4 ; /* 0x00000004ff197424 */
/* 0x000fc600078e00ff */
/*0330*/ @P1 LDG.E.U8 R12, [R12.64] ; /* 0x000000080c0c1981 */
/* 0x000f22000c1e1100 */
/*0340*/ @P1 IADD3 R20, R27.reuse, 0x1, RZ ; /* 0x000000011b141810 */
/* 0x040fe20007ffe0ff */
/*0350*/ IMAD.WIDE.U32 R22, R27.reuse, R25, c[0x0][0x178] ; /* 0x00005e001b167625 */
/* 0x040fe200078e0019 */
/*0360*/ @P1 IADD3 R28, R27, 0x2, RZ ; /* 0x000000021b1c1810 */
/* 0x000fc60007ffe0ff */
/*0370*/ @P1 IMAD.WIDE.U32 R20, R20, R25.reuse, c[0x0][0x178] ; /* 0x00005e0014141625 */
/* 0x080fe400078e0019 */
/*0380*/ LDG.E R22, [R22.64] ; /* 0x0000000816167981 */
/* 0x000f64000c1e1900 */
/*0390*/ @P1 IMAD.WIDE.U32 R16, R28, R25, c[0x0][0x178] ; /* 0x00005e001c101625 */
/* 0x001fe400078e0019 */
/*03a0*/ @P1 LDG.E R20, [R20.64] ; /* 0x0000000814141981 */
/* 0x000f68000c1e1900 */
/*03b0*/ @P1 LDG.E R16, [R16.64] ; /* 0x0000000810101981 */
/* 0x000f62000c1e1900 */
/*03c0*/ ISETP.GE.U32.AND P2, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fc40003f46070 */
/*03d0*/ ISETP.GE.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x000fe20003f06270 */
/*03e0*/ I2F.U16 R4, R4 ; /* 0x0000000400047306 */
/* 0x004f700000101000 */
/*03f0*/ @P1 I2F.U16 R14, R14 ; /* 0x0000000e000e1306 */
/* 0x008e300000101000 */
/*0400*/ @P1 I2F.U16 R12, R12 ; /* 0x0000000c000c1306 */
/* 0x010e620000101000 */
/*0410*/ FFMA R29, R4, R22, R29 ; /* 0x00000016041d7223 */
/* 0x020fc4000000001d */
/*0420*/ IMAD.MOV.U32 R22, RZ, RZ, R8 ; /* 0x000000ffff167224 */
/* 0x000fe400078e0008 */
/*0430*/ @P1 IMAD.MOV.U32 R22, RZ, RZ, R7 ; /* 0x000000ffff161224 */
/* 0x000fe400078e0007 */
/*0440*/ @P1 FFMA R13, R14, R20, R29 ; /* 0x000000140e0d1223 */
/* 0x001fc8000000001d */
/*0450*/ @P1 FFMA R29, R12, R16, R13 ; /* 0x000000100c1d1223 */
/* 0x002fe2000000000d */
/*0460*/ @!P2 BRA 0x7b0 ; /* 0x000003400000a947 */
/* 0x000fea0003800000 */
/*0470*/ IADD3 R28, R27.reuse, R9, R22.reuse ; /* 0x000000091b1c7210 */
/* 0x140fe20007ffe016 */
/*0480*/ IMAD.IADD R4, R10, 0x1, R22.reuse ; /* 0x000000010a047824 */
/* 0x100fe200078e0216 */
/*0490*/ IADD3 R14, R27, R2, R22 ; /* 0x000000021b0e7210 */
/* 0x000fe40007ffe016 */
/*04a0*/ IADD3 R27, R22, -0x1, RZ ; /* 0xffffffff161b7810 */
/* 0x000fe40007ffe0ff */
/*04b0*/ IADD3 R12, R4, -0x3, RZ ; /* 0xfffffffd040c7810 */
/* 0x000fc80007ffe0ff */
/*04c0*/ IMNMX.U32 R13, R12, UR5, PT ; /* 0x000000050c0d7c17 */
/* 0x000fca000b800000 */
/*04d0*/ IMAD R13, R26, c[0x0][0x170], R13 ; /* 0x00005c001a0d7a24 */
/* 0x000fca00078e020d */
/*04e0*/ IADD3 R12, P1, R13, c[0x0][0x160], RZ ; /* 0x000058000d0c7a10 */
/* 0x000fca0007f3e0ff */
/*04f0*/ IMAD.X R13, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff0d7624 */
/* 0x000fca00008e06ff */
/*0500*/ LDG.E.U8 R20, [R12.64] ; /* 0x000000080c147981 */
/* 0x0000a2000c1e1100 */
/*0510*/ IMAD.WIDE.U32 R14, R14, R25, c[0x0][0x178] ; /* 0x00005e000e0e7625 */
/* 0x000fca00078e0019 */
/*0520*/ LDG.E R16, [R14.64] ; /* 0x000000080e107981 */
/* 0x0002e2000c1e1900 */
/*0530*/ IADD3 R17, R4.reuse, -0x2, RZ ; /* 0xfffffffe04117810 */
/* 0x040fe40007ffe0ff */
/*0540*/ IADD3 R22, R4, -0x1, RZ ; /* 0xffffffff04167810 */
/* 0x000fe40007ffe0ff */
/*0550*/ IMNMX.U32 R21, R17, UR5, PT ; /* 0x0000000511157c17 */
/* 0x000fe4000b800000 */
/*0560*/ IMNMX.U32 R23, R22, UR5, PT ; /* 0x0000000516177c17 */
/* 0x000fe4000b800000 */
/*0570*/ IMNMX.U32 R22, R4, UR5, PT ; /* 0x0000000504167c17 */
/* 0x000fe2000b800000 */
/*0580*/ IMAD R21, R26, c[0x0][0x170], R21 ; /* 0x00005c001a157a24 */
/* 0x000fc400078e0215 */
/*0590*/ IMAD R23, R26.reuse, c[0x0][0x170], R23 ; /* 0x00005c001a177a24 */
/* 0x040fe400078e0217 */
/*05a0*/ IMAD R22, R26, c[0x0][0x170], R22 ; /* 0x00005c001a167a24 */
/* 0x000fe200078e0216 */
/*05b0*/ IADD3 R12, P2, R21, c[0x0][0x160], RZ ; /* 0x00005800150c7a10 */
/* 0x001fe40007f5e0ff */
/*05c0*/ IADD3 R14, P1, R23, c[0x0][0x160], RZ ; /* 0x00005800170e7a10 */
/* 0x002fc60007f3e0ff */
/*05d0*/ IMAD.X R13, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff0d7624 */
/* 0x000fe400010e06ff */
/*05e0*/ IMAD.X R15, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff0f7624 */
/* 0x000fc600008e06ff */
/*05f0*/ LDG.E.U8 R12, [R12.64] ; /* 0x000000080c0c7981 */
/* 0x000128000c1e1100 */
/*0600*/ LDG.E.U8 R13, [R14.64] ; /* 0x000000080e0d7981 */
/* 0x001162000c1e1100 */
/*0610*/ I2F.U16 R17, R20 ; /* 0x0000001400117306 */
/* 0x0042e40000101000 */
/*0620*/ IADD3 R20, R28, -0x2, RZ ; /* 0xfffffffe1c147810 */
/* 0x002fe20007ffe0ff */
/*0630*/ FFMA R29, R17, R16, R29 ; /* 0x00000010111d7223 */
/* 0x008fe2000000001d */
/*0640*/ IADD3 R16, P2, R22, c[0x0][0x160], RZ ; /* 0x0000580016107a10 */
/* 0x000fca0007f5e0ff */
/*0650*/ IMAD.X R17, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff117624 */
/* 0x000fe400010e06ff */
/*0660*/ IMAD.WIDE.U32 R14, R20, R25.reuse, c[0x0][0x178] ; /* 0x00005e00140e7625 */
/* 0x081fe200078e0019 */
/*0670*/ IADD3 R20, R28, -0x1, RZ ; /* 0xffffffff1c147810 */
/* 0x000fe40007ffe0ff */
/*0680*/ LDG.E.U8 R16, [R16.64] ; /* 0x0000000810107981 */
/* 0x000ea6000c1e1100 */
/*0690*/ IMAD.WIDE.U32 R20, R20, R25.reuse, c[0x0][0x178] ; /* 0x00005e0014147625 */
/* 0x080fe200078e0019 */
/*06a0*/ LDG.E R14, [R14.64] ; /* 0x000000080e0e7981 */
/* 0x0000e6000c1e1900 */
/*06b0*/ IMAD.WIDE.U32 R22, R28, R25, c[0x0][0x178] ; /* 0x00005e001c167625 */
/* 0x000fc400078e0019 */
/*06c0*/ LDG.E R20, [R20.64] ; /* 0x0000000814147981 */
/* 0x000ee8000c1e1900 */
/*06d0*/ LDG.E R22, [R22.64] ; /* 0x0000000816167981 */
/* 0x000ee2000c1e1900 */
/*06e0*/ I2F.U16 R12, R12 ; /* 0x0000000c000c7306 */
/* 0x010ee20000101000 */
/*06f0*/ IADD3 R27, R27, 0x4, RZ ; /* 0x000000041b1b7810 */
/* 0x000fce0007ffe0ff */
/*0700*/ I2F.U16 R13, R13 ; /* 0x0000000d000d7306 */
/* 0x020e620000101000 */
/*0710*/ ISETP.GE.AND P1, PT, R27, R2, PT ; /* 0x000000021b00720c */
/* 0x000fe40003f26270 */
/*0720*/ IADD3 R15, R28, 0x4, RZ ; /* 0x000000041c0f7810 */
/* 0x001fe40007ffe0ff */
/*0730*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0740*/ I2F.U16 R16, R16 ; /* 0x0000001000107306 */
/* 0x004e220000101000 */
/*0750*/ FFMA R29, R12, R14, R29 ; /* 0x0000000e0c1d7223 */
/* 0x008fe2000000001d */
/*0760*/ IADD3 R14, R28, 0x1, RZ ; /* 0x000000011c0e7810 */
/* 0x000fc60007ffe0ff */
/*0770*/ FFMA R29, R13, R20, R29 ; /* 0x000000140d1d7223 */
/* 0x002fe4000000001d */
/*0780*/ IMAD.MOV.U32 R28, RZ, RZ, R15 ; /* 0x000000ffff1c7224 */
/* 0x000fe400078e000f */
/*0790*/ FFMA R29, R16, R22, R29 ; /* 0x00000016101d7223 */
/* 0x001fe2000000001d */
/*07a0*/ @!P1 BRA 0x4b0 ; /* 0xfffffd0000009947 */
/* 0x000fea000383ffff */
/*07b0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe20007ffe0ff */
/*07c0*/ @!P0 BRA 0x220 ; /* 0xfffffa5000008947 */
/* 0x000fea000383ffff */
/*07d0*/ F2I.U32.TRUNC.NTZ R29, R29 ; /* 0x0000001d001d7305 */
/* 0x000e22000020f000 */
/*07e0*/ IMAD R3, R0, c[0x0][0x170], R3 ; /* 0x00005c0000037a24 */
/* 0x000fca00078e0203 */
/*07f0*/ IADD3 R2, P0, R3, c[0x0][0x168], RZ ; /* 0x00005a0003027a10 */
/* 0x000fca0007f1e0ff */
/*0800*/ IMAD.X R3, RZ, RZ, c[0x0][0x16c], P0 ; /* 0x00005b00ff037624 */
/* 0x000fca00000e06ff */
/*0810*/ STG.E.U8 [R2.64], R29 ; /* 0x0000001d02007986 */
/* 0x001fe2000c101108 */
/*0820*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0830*/ BRA 0x830; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14apply_gaussianPKhPhjjPKfj
.globl _Z14apply_gaussianPKhPhjjPKfj
.p2align 8
.type _Z14apply_gaussianPKhPhjjPKfj,@function
_Z14apply_gaussianPKhPhjjPKfj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
s_mul_i32 s14, s14, s2
v_add_nc_u32_e32 v1, s14, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_u32_e32 vcc_lo, s5, v0
v_cmp_gt_u32_e64 s2, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_7
s_clause 0x2
s_load_b32 s10, s[0:1], 0x20
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[6:7], s[0:1], 0x18
v_mov_b32_e32 v2, 0
s_mov_b32 s9, 0
s_add_i32 s5, s5, -1
s_add_i32 s12, s4, -1
s_mov_b32 s15, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s11, s10, 1
s_or_b32 s14, s10, 1
v_subrev_nc_u32_e32 v3, s11, v1
s_sub_i32 s13, 0, s11
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v4, s13, v0
s_mov_b32 s8, s15
s_mov_b32 s16, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v4, s5, v4
v_cvt_f64_u32_e32 v[4:5], v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_f64 v[4:5], v[4:5], 0
v_cvt_u32_f64_e32 v4, v[4:5]
v_mov_b32_e32 v5, v3
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v4, v4, s4
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_min_u32_e32 v6, s12, v5
s_lshl_b64 s[18:19], s[8:9], 2
s_add_u32 s18, s6, s18
s_addc_u32 s19, s7, s19
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_cvt_f64_u32_e32 v[6:7], v6
s_load_b32 s17, s[18:19], 0x0
s_add_i32 s16, s16, -1
s_add_i32 s8, s8, 1
s_cmp_eq_u32 s16, 0
v_max_f64 v[6:7], v[6:7], 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f64_e32 v6, v[6:7]
v_add_nc_u32_e32 v6, v4, v6
global_load_u8 v6, v6, s[2:3]
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v6, v6
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_dual_fmac_f32 v2, s17, v6 :: v_dual_add_nc_u32 v5, 1, v5
s_cbranch_scc0 .LBB0_3
s_add_i32 s8, s13, 1
s_add_i32 s15, s15, s10
s_cmp_eq_u32 s13, s11
s_cbranch_scc1 .LBB0_6
s_mov_b32 s13, s8
s_branch .LBB0_2
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x8
v_mad_u64_u32 v[3:4], null, v0, s4, v[1:2]
v_cvt_i32_f32_e32 v0, v2
s_waitcnt lgkmcnt(0)
global_store_b8 v3, v0, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14apply_gaussianPKhPhjjPKfj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14apply_gaussianPKhPhjjPKfj, .Lfunc_end0-_Z14apply_gaussianPKhPhjjPKfj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14apply_gaussianPKhPhjjPKfj
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z14apply_gaussianPKhPhjjPKfj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b7d9d_00000000-6_gaussian.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z14apply_gaussianPKhPhjjPKfjPKhPhjjPKfj
.type _Z43__device_stub__Z14apply_gaussianPKhPhjjPKfjPKhPhjjPKfj, @function
_Z43__device_stub__Z14apply_gaussianPKhPhjjPKfjPKhPhjjPKfj:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14apply_gaussianPKhPhjjPKfj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z14apply_gaussianPKhPhjjPKfjPKhPhjjPKfj, .-_Z43__device_stub__Z14apply_gaussianPKhPhjjPKfjPKhPhjjPKfj
.globl _Z14apply_gaussianPKhPhjjPKfj
.type _Z14apply_gaussianPKhPhjjPKfj, @function
_Z14apply_gaussianPKhPhjjPKfj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z14apply_gaussianPKhPhjjPKfjPKhPhjjPKfj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14apply_gaussianPKhPhjjPKfj, .-_Z14apply_gaussianPKhPhjjPKfj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14apply_gaussianPKhPhjjPKfj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14apply_gaussianPKhPhjjPKfj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gaussian.hip"
.globl _Z29__device_stub__apply_gaussianPKhPhjjPKfj # -- Begin function _Z29__device_stub__apply_gaussianPKhPhjjPKfj
.p2align 4, 0x90
.type _Z29__device_stub__apply_gaussianPKhPhjjPKfj,@function
_Z29__device_stub__apply_gaussianPKhPhjjPKfj: # @_Z29__device_stub__apply_gaussianPKhPhjjPKfj
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movq %r8, 72(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14apply_gaussianPKhPhjjPKfj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z29__device_stub__apply_gaussianPKhPhjjPKfj, .Lfunc_end0-_Z29__device_stub__apply_gaussianPKhPhjjPKfj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14apply_gaussianPKhPhjjPKfj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14apply_gaussianPKhPhjjPKfj,@object # @_Z14apply_gaussianPKhPhjjPKfj
.section .rodata,"a",@progbits
.globl _Z14apply_gaussianPKhPhjjPKfj
.p2align 3, 0x0
_Z14apply_gaussianPKhPhjjPKfj:
.quad _Z29__device_stub__apply_gaussianPKhPhjjPKfj
.size _Z14apply_gaussianPKhPhjjPKfj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14apply_gaussianPKhPhjjPKfj"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__apply_gaussianPKhPhjjPKfj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14apply_gaussianPKhPhjjPKfj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void _softback(int nrows, int ncols, float *y, float *dy) {
/* y is layer output, i.e. unnormalized log probabilities.
On output y will contain normalized probabilities.
Conceptually this is a forward calculation but we do it here for efficiency.
dy is the label matrix: each column is a one-hot vector indicating the correct label.
On output dy will be the gradient of softmax loss wrt probabilities.
*/
float y0, sum;
int i0, i1;
int col = threadIdx.x + blockIdx.x * blockDim.x;
while (col < ncols) {
i0 = col * nrows;
i1 = i0 + nrows;
y0 = -INFINITY;
//y0 = y[i0];
for (int i=i0; i<i1; i++) {
if (y[i] > y0) {
y0 = y[i];
}
}
sum = 0;
for (int i=i0; i<i1; i++) {
y[i] = exp(y[i]-y0);
sum += y[i];
}
for (int i=i0; i<i1; i++) {
y[i] /= sum;
dy[i] = (y[i] - dy[i]) / ncols;
}
col += blockDim.x * gridDim.x;
}
} | .file "tmpxft_00150c4d_00000000-6__softback.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9_softbackiiPfS_iiPfS_
.type _Z32__device_stub__Z9_softbackiiPfS_iiPfS_, @function
_Z32__device_stub__Z9_softbackiiPfS_iiPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9_softbackiiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z9_softbackiiPfS_iiPfS_, .-_Z32__device_stub__Z9_softbackiiPfS_iiPfS_
.globl _Z9_softbackiiPfS_
.type _Z9_softbackiiPfS_, @function
_Z9_softbackiiPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9_softbackiiPfS_iiPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9_softbackiiPfS_, .-_Z9_softbackiiPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9_softbackiiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9_softbackiiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void _softback(int nrows, int ncols, float *y, float *dy) {
/* y is layer output, i.e. unnormalized log probabilities.
On output y will contain normalized probabilities.
Conceptually this is a forward calculation but we do it here for efficiency.
dy is the label matrix: each column is a one-hot vector indicating the correct label.
On output dy will be the gradient of softmax loss wrt probabilities.
*/
float y0, sum;
int i0, i1;
int col = threadIdx.x + blockIdx.x * blockDim.x;
while (col < ncols) {
i0 = col * nrows;
i1 = i0 + nrows;
y0 = -INFINITY;
//y0 = y[i0];
for (int i=i0; i<i1; i++) {
if (y[i] > y0) {
y0 = y[i];
}
}
sum = 0;
for (int i=i0; i<i1; i++) {
y[i] = exp(y[i]-y0);
sum += y[i];
}
for (int i=i0; i<i1; i++) {
y[i] /= sum;
dy[i] = (y[i] - dy[i]) / ncols;
}
col += blockDim.x * gridDim.x;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void _softback(int nrows, int ncols, float *y, float *dy) {
/* y is layer output, i.e. unnormalized log probabilities.
On output y will contain normalized probabilities.
Conceptually this is a forward calculation but we do it here for efficiency.
dy is the label matrix: each column is a one-hot vector indicating the correct label.
On output dy will be the gradient of softmax loss wrt probabilities.
*/
float y0, sum;
int i0, i1;
int col = threadIdx.x + blockIdx.x * blockDim.x;
while (col < ncols) {
i0 = col * nrows;
i1 = i0 + nrows;
y0 = -INFINITY;
//y0 = y[i0];
for (int i=i0; i<i1; i++) {
if (y[i] > y0) {
y0 = y[i];
}
}
sum = 0;
for (int i=i0; i<i1; i++) {
y[i] = exp(y[i]-y0);
sum += y[i];
}
for (int i=i0; i<i1; i++) {
y[i] /= sum;
dy[i] = (y[i] - dy[i]) / ncols;
}
col += blockDim.x * gridDim.x;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void _softback(int nrows, int ncols, float *y, float *dy) {
/* y is layer output, i.e. unnormalized log probabilities.
On output y will contain normalized probabilities.
Conceptually this is a forward calculation but we do it here for efficiency.
dy is the label matrix: each column is a one-hot vector indicating the correct label.
On output dy will be the gradient of softmax loss wrt probabilities.
*/
float y0, sum;
int i0, i1;
int col = threadIdx.x + blockIdx.x * blockDim.x;
while (col < ncols) {
i0 = col * nrows;
i1 = i0 + nrows;
y0 = -INFINITY;
//y0 = y[i0];
for (int i=i0; i<i1; i++) {
if (y[i] > y0) {
y0 = y[i];
}
}
sum = 0;
for (int i=i0; i<i1; i++) {
y[i] = exp(y[i]-y0);
sum += y[i];
}
for (int i=i0; i<i1; i++) {
y[i] /= sum;
dy[i] = (y[i] - dy[i]) / ncols;
}
col += blockDim.x * gridDim.x;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9_softbackiiPfS_
.globl _Z9_softbackiiPfS_
.p2align 8
.type _Z9_softbackiiPfS_,@function
_Z9_softbackiiPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x4
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_15
s_load_b32 s9, s[0:1], 0x0
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
v_cvt_f32_i32_e32 v0, s8
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v2, s9, v1
s_cmp_gt_i32 s9, 0
s_mul_i32 s2, s2, s10
s_cselect_b32 s1, -1, 0
s_mul_i32 s10, s2, s9
s_branch .LBB0_4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s11
.LBB0_3:
v_add_nc_u32_e32 v1, s2, v1
v_add_nc_u32_e32 v2, s10, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s8, v1
s_or_b32 s3, vcc_lo, s3
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_15
.LBB0_4:
v_mul_lo_u32 v7, v1, s9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
s_and_not1_b32 vcc_lo, exec_lo, s1
v_add_nc_u32_e32 v8, s9, v7
s_cbranch_vccnz .LBB0_11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_dual_mov_b32 v6, 0xff800000 :: v_dual_mov_b32 v9, v7
s_mov_b32 s11, 0
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.LBB0_6:
global_load_b32 v10, v[4:5], off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, v10, v6
v_dual_cndmask_b32 v6, v6, v10 :: v_dual_add_nc_u32 v9, 1, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s0, v9, v8
s_or_b32 s11, s0, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_6
s_or_b32 exec_lo, exec_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_12
.LBB0_8:
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v10, v7
s_mov_b32 s11, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_9:
global_load_b32 v11, v[4:5], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v11, v11, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v12, 0x3fb8aa3b, v11
v_fma_f32 v13, v11, 0x3fb8aa3b, -v12
v_rndne_f32_e32 v14, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmac_f32 v13, 0x32a5705f, v11 :: v_dual_sub_f32 v12, v12, v14
v_add_f32_e32 v12, v12, v13
v_cvt_i32_f32_e32 v13, v14
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v12, v12
s_waitcnt_depctr 0xfff
v_ldexp_f32 v12, v12, v13
v_cndmask_b32_e32 v12, 0, v12, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v11, 0x7f800000, v12 :: v_dual_add_nc_u32 v10, 1, v10
v_cmp_ge_i32_e32 vcc_lo, v10, v8
global_store_b32 v[4:5], v11, off
v_add_co_u32 v4, s0, v4, 4
v_add_f32_e32 v9, v9, v11
v_add_co_ci_u32_e64 v5, s0, 0, v5, s0
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_9
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccz .LBB0_13
s_branch .LBB0_3
.LBB0_11:
v_mov_b32_e32 v6, 0xff800000
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccz .LBB0_8
.LBB0_12:
v_mov_b32_e32 v9, 0
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_3
.LBB0_13:
v_lshlrev_b64 v[5:6], 2, v[2:3]
s_mov_b32 s11, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
.LBB0_14:
global_load_b32 v10, v[3:4], off
v_add_nc_u32_e32 v7, 1, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s0, v7, v8
s_or_b32 s11, s0, s11
s_waitcnt vmcnt(0)
v_div_scale_f32 v11, null, v9, v9, v10
v_div_scale_f32 v13, vcc_lo, v10, v9, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v12, v11
s_waitcnt_depctr 0xfff
v_fma_f32 v14, -v11, v12, 1.0
v_fmac_f32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v14, v13, v12
v_fma_f32 v15, -v11, v14, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v14, v15, v12
v_fma_f32 v11, -v11, v14, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v11, v11, v12, v14
v_div_fixup_f32 v10, v11, v9, v10
global_store_b32 v[3:4], v10, off
global_load_b32 v11, v[5:6], off
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v10, v10, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v11, null, v0, v0, v10
v_div_scale_f32 v13, vcc_lo, v10, v0, v10
v_rcp_f32_e32 v12, v11
s_waitcnt_depctr 0xfff
v_fma_f32 v14, -v11, v12, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v12, v14, v12
v_mul_f32_e32 v14, v13, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v15, -v11, v14, v13
v_fmac_f32_e32 v14, v15, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v11, -v11, v14, v13
v_div_fmas_f32 v11, v11, v12, v14
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v10, v11, v0, v10
global_store_b32 v[5:6], v10, off
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_14
s_branch .LBB0_2
.LBB0_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9_softbackiiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9_softbackiiPfS_, .Lfunc_end0-_Z9_softbackiiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9_softbackiiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9_softbackiiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void _softback(int nrows, int ncols, float *y, float *dy) {
/* y is layer output, i.e. unnormalized log probabilities.
On output y will contain normalized probabilities.
Conceptually this is a forward calculation but we do it here for efficiency.
dy is the label matrix: each column is a one-hot vector indicating the correct label.
On output dy will be the gradient of softmax loss wrt probabilities.
*/
float y0, sum;
int i0, i1;
int col = threadIdx.x + blockIdx.x * blockDim.x;
while (col < ncols) {
i0 = col * nrows;
i1 = i0 + nrows;
y0 = -INFINITY;
//y0 = y[i0];
for (int i=i0; i<i1; i++) {
if (y[i] > y0) {
y0 = y[i];
}
}
sum = 0;
for (int i=i0; i<i1; i++) {
y[i] = exp(y[i]-y0);
sum += y[i];
}
for (int i=i0; i<i1; i++) {
y[i] /= sum;
dy[i] = (y[i] - dy[i]) / ncols;
}
col += blockDim.x * gridDim.x;
}
} | .text
.file "_softback.hip"
.globl _Z24__device_stub___softbackiiPfS_ # -- Begin function _Z24__device_stub___softbackiiPfS_
.p2align 4, 0x90
.type _Z24__device_stub___softbackiiPfS_,@function
_Z24__device_stub___softbackiiPfS_: # @_Z24__device_stub___softbackiiPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9_softbackiiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub___softbackiiPfS_, .Lfunc_end0-_Z24__device_stub___softbackiiPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9_softbackiiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9_softbackiiPfS_,@object # @_Z9_softbackiiPfS_
.section .rodata,"a",@progbits
.globl _Z9_softbackiiPfS_
.p2align 3, 0x0
_Z9_softbackiiPfS_:
.quad _Z24__device_stub___softbackiiPfS_
.size _Z9_softbackiiPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9_softbackiiPfS_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub___softbackiiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9_softbackiiPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00150c4d_00000000-6__softback.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9_softbackiiPfS_iiPfS_
.type _Z32__device_stub__Z9_softbackiiPfS_iiPfS_, @function
_Z32__device_stub__Z9_softbackiiPfS_iiPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9_softbackiiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z9_softbackiiPfS_iiPfS_, .-_Z32__device_stub__Z9_softbackiiPfS_iiPfS_
.globl _Z9_softbackiiPfS_
.type _Z9_softbackiiPfS_, @function
_Z9_softbackiiPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9_softbackiiPfS_iiPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9_softbackiiPfS_, .-_Z9_softbackiiPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9_softbackiiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9_softbackiiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "_softback.hip"
.globl _Z24__device_stub___softbackiiPfS_ # -- Begin function _Z24__device_stub___softbackiiPfS_
.p2align 4, 0x90
.type _Z24__device_stub___softbackiiPfS_,@function
_Z24__device_stub___softbackiiPfS_: # @_Z24__device_stub___softbackiiPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9_softbackiiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub___softbackiiPfS_, .Lfunc_end0-_Z24__device_stub___softbackiiPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9_softbackiiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9_softbackiiPfS_,@object # @_Z9_softbackiiPfS_
.section .rodata,"a",@progbits
.globl _Z9_softbackiiPfS_
.p2align 3, 0x0
_Z9_softbackiiPfS_:
.quad _Z24__device_stub___softbackiiPfS_
.size _Z9_softbackiiPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9_softbackiiPfS_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub___softbackiiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9_softbackiiPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
#include <unistd.h>
__global__ void add(int *a, int *b, int *c){
c[blockIdx.x] = a[blockIdx.x] + b[blockIdx.x];
}
#define N 512*512*1024
int random_ints(int *p, int n){
int i;
for(i=0;i<n;i++)
*p++ = rand();
return 0;
}
int main(){
int *a, *b, *c;
int *d_a, *d_b, *d_c;
int size = N*sizeof(int);
cudaSetDevice(1);
cudaMalloc((void**)&d_a, size);
cudaMalloc((void**)&d_b, size);
cudaMalloc((void**)&d_c, size);
a = (int*)malloc(size);
b = (int*)malloc(size);
c = (int*)malloc(size);
random_ints(a,N);
random_ints(b,N);
a[N-1] = 100;
b[N-1] = 200;
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
add<<<N,1>>>(d_a, d_b, d_c);
cudaDeviceSynchronize();
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
printf("result = %d\n",c[N-1]);
free(a);
free(b);
free(c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0007 */
/*0050*/ IMAD.WIDE.U32 R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0007 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0007 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
#include <unistd.h>
__global__ void add(int *a, int *b, int *c){
c[blockIdx.x] = a[blockIdx.x] + b[blockIdx.x];
}
#define N 512*512*1024
int random_ints(int *p, int n){
int i;
for(i=0;i<n;i++)
*p++ = rand();
return 0;
}
int main(){
int *a, *b, *c;
int *d_a, *d_b, *d_c;
int size = N*sizeof(int);
cudaSetDevice(1);
cudaMalloc((void**)&d_a, size);
cudaMalloc((void**)&d_b, size);
cudaMalloc((void**)&d_c, size);
a = (int*)malloc(size);
b = (int*)malloc(size);
c = (int*)malloc(size);
random_ints(a,N);
random_ints(b,N);
a[N-1] = 100;
b[N-1] = 200;
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
add<<<N,1>>>(d_a, d_b, d_c);
cudaDeviceSynchronize();
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
printf("result = %d\n",c[N-1]);
free(a);
free(b);
free(c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | .file "tmpxft_00110e37_00000000-6_block.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2074:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2074:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11random_intsPii
.type _Z11random_intsPii, @function
_Z11random_intsPii:
.LFB2070:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
addq $4, %rbx
movl %eax, -4(%rbx)
cmpq %rbp, %rbx
jne .L5
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
movl $0, %eax
ret
.cfi_endproc
.LFE2070:
.size _Z11random_intsPii, .-_Z11random_intsPii
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2096:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2096:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "result = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2071:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1, %edi
call cudaSetDevice@PLT
leaq 8(%rsp), %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
movl $1073741824, %edi
call malloc@PLT
movq %rax, %rbp
movl $1073741824, %edi
call malloc@PLT
movq %rax, %rbx
movl $1073741824, %edi
call malloc@PLT
movq %rax, %r12
movl $268435456, %esi
movq %rbp, %rdi
call _Z11random_intsPii
movl $268435456, %esi
movq %rbx, %rdi
call _Z11random_intsPii
movl $100, 1073741820(%rbp)
movl $200, 1073741820(%rbx)
movl $1, %ecx
movl $1073741824, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1073741824, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $268435456, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $1073741824, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl 1073741820(%r12), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L20
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2071:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
#include <unistd.h>
__global__ void add(int *a, int *b, int *c){
c[blockIdx.x] = a[blockIdx.x] + b[blockIdx.x];
}
#define N 512*512*1024
int random_ints(int *p, int n){
int i;
for(i=0;i<n;i++)
*p++ = rand();
return 0;
}
int main(){
int *a, *b, *c;
int *d_a, *d_b, *d_c;
int size = N*sizeof(int);
cudaSetDevice(1);
cudaMalloc((void**)&d_a, size);
cudaMalloc((void**)&d_b, size);
cudaMalloc((void**)&d_c, size);
a = (int*)malloc(size);
b = (int*)malloc(size);
c = (int*)malloc(size);
random_ints(a,N);
random_ints(b,N);
a[N-1] = 100;
b[N-1] = 200;
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
add<<<N,1>>>(d_a, d_b, d_c);
cudaDeviceSynchronize();
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
printf("result = %d\n",c[N-1]);
free(a);
free(b);
free(c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <unistd.h>
__global__ void add(int *a, int *b, int *c){
c[blockIdx.x] = a[blockIdx.x] + b[blockIdx.x];
}
#define N 512*512*1024
int random_ints(int *p, int n){
int i;
for(i=0;i<n;i++)
*p++ = rand();
return 0;
}
int main(){
int *a, *b, *c;
int *d_a, *d_b, *d_c;
int size = N*sizeof(int);
hipSetDevice(1);
hipMalloc((void**)&d_a, size);
hipMalloc((void**)&d_b, size);
hipMalloc((void**)&d_c, size);
a = (int*)malloc(size);
b = (int*)malloc(size);
c = (int*)malloc(size);
random_ints(a,N);
random_ints(b,N);
a[N-1] = 100;
b[N-1] = 200;
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
add<<<N,1>>>(d_a, d_b, d_c);
hipDeviceSynchronize();
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
printf("result = %d\n",c[N-1]);
free(a);
free(b);
free(c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <unistd.h>
__global__ void add(int *a, int *b, int *c){
c[blockIdx.x] = a[blockIdx.x] + b[blockIdx.x];
}
#define N 512*512*1024
int random_ints(int *p, int n){
int i;
for(i=0;i<n;i++)
*p++ = rand();
return 0;
}
int main(){
int *a, *b, *c;
int *d_a, *d_b, *d_c;
int size = N*sizeof(int);
hipSetDevice(1);
hipMalloc((void**)&d_a, size);
hipMalloc((void**)&d_b, size);
hipMalloc((void**)&d_c, size);
a = (int*)malloc(size);
b = (int*)malloc(size);
c = (int*)malloc(size);
random_ints(a,N);
random_ints(b,N);
a[N-1] = 100;
b[N-1] = 200;
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
add<<<N,1>>>(d_a, d_b, d_c);
hipDeviceSynchronize();
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
printf("result = %d\n",c[N-1]);
free(a);
free(b);
free(c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_mov_b32 s3, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <unistd.h>
__global__ void add(int *a, int *b, int *c){
c[blockIdx.x] = a[blockIdx.x] + b[blockIdx.x];
}
#define N 512*512*1024
int random_ints(int *p, int n){
int i;
for(i=0;i<n;i++)
*p++ = rand();
return 0;
}
int main(){
int *a, *b, *c;
int *d_a, *d_b, *d_c;
int size = N*sizeof(int);
hipSetDevice(1);
hipMalloc((void**)&d_a, size);
hipMalloc((void**)&d_b, size);
hipMalloc((void**)&d_c, size);
a = (int*)malloc(size);
b = (int*)malloc(size);
c = (int*)malloc(size);
random_ints(a,N);
random_ints(b,N);
a[N-1] = 100;
b[N-1] = 200;
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
add<<<N,1>>>(d_a, d_b, d_c);
hipDeviceSynchronize();
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
printf("result = %d\n",c[N-1]);
free(a);
free(b);
free(c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.file "block.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl _Z11random_intsPii # -- Begin function _Z11random_intsPii
.p2align 4, 0x90
.type _Z11random_intsPii,@function
_Z11random_intsPii: # @_Z11random_intsPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
movl %eax, (%rbx,%r15,4)
incq %r15
cmpl %r15d, %r14d
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
xorl %eax, %eax
retq
.Lfunc_end1:
.size _Z11random_intsPii, .Lfunc_end1-_Z11random_intsPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $1, %edi
callq hipSetDevice
leaq 16(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
movq %rsp, %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
movl $1073741824, %edi # imm = 0x40000000
callq malloc
movq %rax, %rbx
movl $1073741824, %edi # imm = 0x40000000
callq malloc
movq %rax, %r14
movl $1073741824, %edi # imm = 0x40000000
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
movl %eax, (%rbx,%r12,4)
incq %r12
cmpl $268435456, %r12d # imm = 0x10000000
jne .LBB2_1
# %bb.2: # %.lr.ph.i21.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i21
# =>This Inner Loop Header: Depth=1
callq rand
movl %eax, (%r14,%r12,4)
incq %r12
cmpl $268435456, %r12d # imm = 0x10000000
jne .LBB2_3
# %bb.4: # %_Z11random_intsPii.exit25
movl $100, 1073741820(%rbx)
movl $200, 1073741820(%r14)
movq 16(%rsp), %rdi
movl $1073741824, %edx # imm = 0x40000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $1073741824, %edx # imm = 0x40000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 268435455(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
callq hipDeviceSynchronize
movq (%rsp), %rsi
movl $1073741824, %edx # imm = 0x40000000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl 1073741820(%r15), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "result = %d\n"
.size .L.str, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0007 */
/*0050*/ IMAD.WIDE.U32 R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0007 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0007 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_mov_b32 s3, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00110e37_00000000-6_block.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2074:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2074:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11random_intsPii
.type _Z11random_intsPii, @function
_Z11random_intsPii:
.LFB2070:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
addq $4, %rbx
movl %eax, -4(%rbx)
cmpq %rbp, %rbx
jne .L5
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
movl $0, %eax
ret
.cfi_endproc
.LFE2070:
.size _Z11random_intsPii, .-_Z11random_intsPii
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2096:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2096:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "result = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2071:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1, %edi
call cudaSetDevice@PLT
leaq 8(%rsp), %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
movl $1073741824, %edi
call malloc@PLT
movq %rax, %rbp
movl $1073741824, %edi
call malloc@PLT
movq %rax, %rbx
movl $1073741824, %edi
call malloc@PLT
movq %rax, %r12
movl $268435456, %esi
movq %rbp, %rdi
call _Z11random_intsPii
movl $268435456, %esi
movq %rbx, %rdi
call _Z11random_intsPii
movl $100, 1073741820(%rbp)
movl $200, 1073741820(%rbx)
movl $1, %ecx
movl $1073741824, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1073741824, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $268435456, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $1073741824, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl 1073741820(%r12), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L20
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2071:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "block.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl _Z11random_intsPii # -- Begin function _Z11random_intsPii
.p2align 4, 0x90
.type _Z11random_intsPii,@function
_Z11random_intsPii: # @_Z11random_intsPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
movl %eax, (%rbx,%r15,4)
incq %r15
cmpl %r15d, %r14d
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
xorl %eax, %eax
retq
.Lfunc_end1:
.size _Z11random_intsPii, .Lfunc_end1-_Z11random_intsPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $1, %edi
callq hipSetDevice
leaq 16(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
movq %rsp, %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
movl $1073741824, %edi # imm = 0x40000000
callq malloc
movq %rax, %rbx
movl $1073741824, %edi # imm = 0x40000000
callq malloc
movq %rax, %r14
movl $1073741824, %edi # imm = 0x40000000
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
movl %eax, (%rbx,%r12,4)
incq %r12
cmpl $268435456, %r12d # imm = 0x10000000
jne .LBB2_1
# %bb.2: # %.lr.ph.i21.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i21
# =>This Inner Loop Header: Depth=1
callq rand
movl %eax, (%r14,%r12,4)
incq %r12
cmpl $268435456, %r12d # imm = 0x10000000
jne .LBB2_3
# %bb.4: # %_Z11random_intsPii.exit25
movl $100, 1073741820(%rbx)
movl $200, 1073741820(%r14)
movq 16(%rsp), %rdi
movl $1073741824, %edx # imm = 0x40000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $1073741824, %edx # imm = 0x40000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 268435455(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
callq hipDeviceSynchronize
movq (%rsp), %rsi
movl $1073741824, %edx # imm = 0x40000000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl 1073741820(%r15), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "result = %d\n"
.size .L.str, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void end_coloring_mark() {} | code for sm_80
Function : _Z17end_coloring_markv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void end_coloring_mark() {} | .file "tmpxft_0008dc53_00000000-6_end_coloring_mark.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z17end_coloring_markvv
.type _Z36__device_stub__Z17end_coloring_markvv, @function
_Z36__device_stub__Z17end_coloring_markvv:
.LFB2051:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z17end_coloring_markv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z17end_coloring_markvv, .-_Z36__device_stub__Z17end_coloring_markvv
.globl _Z17end_coloring_markv
.type _Z17end_coloring_markv, @function
_Z17end_coloring_markv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z17end_coloring_markvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17end_coloring_markv, .-_Z17end_coloring_markv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17end_coloring_markv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17end_coloring_markv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void end_coloring_mark() {} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void end_coloring_mark() {} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void end_coloring_mark() {} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17end_coloring_markv
.globl _Z17end_coloring_markv
.p2align 8
.type _Z17end_coloring_markv,@function
_Z17end_coloring_markv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17end_coloring_markv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17end_coloring_markv, .Lfunc_end0-_Z17end_coloring_markv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17end_coloring_markv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z17end_coloring_markv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void end_coloring_mark() {} | .text
.file "end_coloring_mark.hip"
.globl _Z32__device_stub__end_coloring_markv # -- Begin function _Z32__device_stub__end_coloring_markv
.p2align 4, 0x90
.type _Z32__device_stub__end_coloring_markv,@function
_Z32__device_stub__end_coloring_markv: # @_Z32__device_stub__end_coloring_markv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z17end_coloring_markv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z32__device_stub__end_coloring_markv, .Lfunc_end0-_Z32__device_stub__end_coloring_markv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17end_coloring_markv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17end_coloring_markv,@object # @_Z17end_coloring_markv
.section .rodata,"a",@progbits
.globl _Z17end_coloring_markv
.p2align 3, 0x0
_Z17end_coloring_markv:
.quad _Z32__device_stub__end_coloring_markv
.size _Z17end_coloring_markv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17end_coloring_markv"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__end_coloring_markv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17end_coloring_markv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17end_coloring_markv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17end_coloring_markv
.globl _Z17end_coloring_markv
.p2align 8
.type _Z17end_coloring_markv,@function
_Z17end_coloring_markv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17end_coloring_markv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17end_coloring_markv, .Lfunc_end0-_Z17end_coloring_markv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17end_coloring_markv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z17end_coloring_markv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008dc53_00000000-6_end_coloring_mark.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z17end_coloring_markvv
.type _Z36__device_stub__Z17end_coloring_markvv, @function
_Z36__device_stub__Z17end_coloring_markvv:
.LFB2051:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z17end_coloring_markv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z17end_coloring_markvv, .-_Z36__device_stub__Z17end_coloring_markvv
.globl _Z17end_coloring_markv
.type _Z17end_coloring_markv, @function
_Z17end_coloring_markv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z17end_coloring_markvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17end_coloring_markv, .-_Z17end_coloring_markv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17end_coloring_markv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17end_coloring_markv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "end_coloring_mark.hip"
.globl _Z32__device_stub__end_coloring_markv # -- Begin function _Z32__device_stub__end_coloring_markv
.p2align 4, 0x90
.type _Z32__device_stub__end_coloring_markv,@function
_Z32__device_stub__end_coloring_markv: # @_Z32__device_stub__end_coloring_markv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z17end_coloring_markv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z32__device_stub__end_coloring_markv, .Lfunc_end0-_Z32__device_stub__end_coloring_markv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17end_coloring_markv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17end_coloring_markv,@object # @_Z17end_coloring_markv
.section .rodata,"a",@progbits
.globl _Z17end_coloring_markv
.p2align 3, 0x0
_Z17end_coloring_markv:
.quad _Z32__device_stub__end_coloring_markv
.size _Z17end_coloring_markv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17end_coloring_markv"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__end_coloring_markv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17end_coloring_markv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "date.hh"
#include <chrono>
namespace date
{
long now()
{
return std::chrono::duration_cast<std::chrono::milliseconds>(
std::chrono::system_clock::now().time_since_epoch()
).count();
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "date.hh"
#include <chrono>
namespace date
{
long now()
{
return std::chrono::duration_cast<std::chrono::milliseconds>(
std::chrono::system_clock::now().time_since_epoch()
).count();
}
} | .file "tmpxft_0017bd2c_00000000-6_date.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2129:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2129:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _ZN4date3nowEv
.type _ZN4date3nowEv, @function
_ZN4date3nowEv:
.LFB2126:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rcx
movabsq $4835703278458516699, %rdx
imulq %rdx
sarq $18, %rdx
sarq $63, %rcx
movq %rdx, %rax
subq %rcx, %rax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2126:
.size _ZN4date3nowEv, .-_ZN4date3nowEv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2152:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2152:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "date.hh"
#include <chrono>
namespace date
{
long now()
{
return std::chrono::duration_cast<std::chrono::milliseconds>(
std::chrono::system_clock::now().time_since_epoch()
).count();
}
} | #include <hip/hip_runtime.h>
#include "date.hh"
#include <chrono>
namespace date
{
long now()
{
return std::chrono::duration_cast<std::chrono::milliseconds>(
std::chrono::system_clock::now().time_since_epoch()
).count();
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "date.hh"
#include <chrono>
namespace date
{
long now()
{
return std::chrono::duration_cast<std::chrono::milliseconds>(
std::chrono::system_clock::now().time_since_epoch()
).count();
}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "date.hh"
#include <chrono>
namespace date
{
long now()
{
return std::chrono::duration_cast<std::chrono::milliseconds>(
std::chrono::system_clock::now().time_since_epoch()
).count();
}
} | .text
.file "date.hip"
.globl _ZN4date3nowEv # -- Begin function _ZN4date3nowEv
.p2align 4, 0x90
.type _ZN4date3nowEv,@function
_ZN4date3nowEv: # @_ZN4date3nowEv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _ZNSt6chrono3_V212system_clock3nowEv
movabsq $4835703278458516699, %rcx # imm = 0x431BDE82D7B634DB
imulq %rcx
movq %rdx, %rax
shrq $63, %rax
sarq $18, %rdx
addq %rdx, %rax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _ZN4date3nowEv, .Lfunc_end0-_ZN4date3nowEv
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017bd2c_00000000-6_date.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2129:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2129:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _ZN4date3nowEv
.type _ZN4date3nowEv, @function
_ZN4date3nowEv:
.LFB2126:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rcx
movabsq $4835703278458516699, %rdx
imulq %rdx
sarq $18, %rdx
sarq $63, %rcx
movq %rdx, %rax
subq %rcx, %rax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2126:
.size _ZN4date3nowEv, .-_ZN4date3nowEv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2152:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2152:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "date.hip"
.globl _ZN4date3nowEv # -- Begin function _ZN4date3nowEv
.p2align 4, 0x90
.type _ZN4date3nowEv,@function
_ZN4date3nowEv: # @_ZN4date3nowEv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _ZNSt6chrono3_V212system_clock3nowEv
movabsq $4835703278458516699, %rcx # imm = 0x431BDE82D7B634DB
imulq %rcx
movq %rdx, %rax
shrq $63, %rax
sarq $18, %rdx
addq %rdx, %rax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _ZN4date3nowEv, .Lfunc_end0-_ZN4date3nowEv
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<stdlib.h>
__global__ void transpose(int *a,int *t)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
int flag=0,comp,j=1;
if(blockIdx.x==0 || (blockIdx.x+1)%gridDim.x == 0 || threadIdx.x==0 || (threadIdx.x+1)%blockDim.x==0)
flag=1;
if(!flag)
{
t[id]=0;
while(a[id]!=0){
comp=a[id]%2;
if(comp)
comp=0;
else
comp=1;
t[id]+=(comp*j);
j*=10;
a[id]/=2;
}
}
else
{
t[id]=a[id];
}
}
int main(void)
{
int *t,m,n,i,j;
int *d_a,*d_t,*d_m;
m=4;
n=4;
int a[]={1,2,3,4,5,5,8,8,9,4,10,12,13,14,15,16};
int size=sizeof(int)*m*n;
t=(int*)malloc(m*n*sizeof(int));
cudaMalloc((void**)&d_a,size);
cudaMalloc((void**)&d_t,size);
cudaMemcpy(d_a,a,size,cudaMemcpyHostToDevice);
transpose<<<m,n>>>(d_a,d_t);
cudaMemcpy(t,d_t,size,cudaMemcpyDeviceToHost);
printf("result vector is:\n");
for(i=0;i<m;i++)
{
for(j=0;j<n;j++)
{
printf("%d\t",t[i*n+j] );
}
printf("\n");
}
cudaFree(d_a);
cudaFree(d_t);
return 0;
} | code for sm_80
Function : _Z9transposePiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ PLOP3.LUT P1, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f2e170 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0050*/ ISETP.NE.AND P0, PT, R11.reuse, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x041fe20003f05270 */
/*0060*/ IMAD R4, R11, c[0x0][0x0], R0 ; /* 0x000000000b047a24 */
/* 0x002fc800078e0200 */
/*0070*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fc800078e0205 */
/*0080*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0205 */
/*0090*/ @!P0 BRA 0x340 ; /* 0x000002a000008947 */
/* 0x000fea0003800000 */
/*00a0*/ I2F.U32.RP R8, c[0x0][0xc] ; /* 0x0000030000087b06 */
/* 0x000e220000209000 */
/*00b0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*00c0*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0xc], PT ; /* 0x00000300ff007a0c */
/* 0x000fe20003f45070 */
/*00d0*/ BSSY B0, 0x340 ; /* 0x0000026000007945 */
/* 0x000fea0003800000 */
/*00e0*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x001e240000001000 */
/*00f0*/ IADD3 R7, R8, 0xffffffe, RZ ; /* 0x0ffffffe08077810 */
/* 0x001fcc0007ffe0ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e24000021f000 */
/*0110*/ IMAD.MOV R9, RZ, RZ, -R7 ; /* 0x000000ffff097224 */
/* 0x001fc800078e0a07 */
/*0120*/ IMAD R9, R9, c[0x0][0xc], RZ ; /* 0x0000030009097a24 */
/* 0x000fc800078e02ff */
/*0130*/ IMAD.HI.U32 R9, R7, R9, R6 ; /* 0x0000000907097227 */
/* 0x000fe200078e0006 */
/*0140*/ IADD3 R6, R11, 0x1, RZ ; /* 0x000000010b067810 */
/* 0x000fca0007ffe0ff */
/*0150*/ IMAD.HI.U32 R9, R9, R6, RZ ; /* 0x0000000609097227 */
/* 0x000fc800078e00ff */
/*0160*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fc800078e0a09 */
/*0170*/ IMAD R6, R9, c[0x0][0xc], R6 ; /* 0x0000030009067a24 */
/* 0x000fca00078e0206 */
/*0180*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0xc], PT ; /* 0x0000030006007a0c */
/* 0x000fda0003f06070 */
/*0190*/ @P0 IADD3 R6, R6, -c[0x0][0xc], RZ ; /* 0x8000030006060a10 */
/* 0x000fc80007ffe0ff */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0xc], PT ; /* 0x0000030006007a0c */
/* 0x000fda0003f06070 */
/*01b0*/ @P0 IADD3 R6, R6, -c[0x0][0xc], RZ ; /* 0x8000030006060a10 */
/* 0x000fe40007ffe0ff */
/*01c0*/ @!P2 LOP3.LUT R6, RZ, c[0x0][0xc], RZ, 0x33, !PT ; /* 0x00000300ff06aa12 */
/* 0x000fc800078e33ff */
/*01d0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc80003f05270 */
/*01e0*/ ISETP.EQ.OR P0, PT, R0, RZ, !P0 ; /* 0x000000ff0000720c */
/* 0x000fda0004702670 */
/*01f0*/ @P0 BRA 0x330 ; /* 0x0000013000000947 */
/* 0x000fea0003800000 */
/*0200*/ I2F.U32.RP R8, c[0x0][0x0] ; /* 0x0000000000087b06 */
/* 0x000e220000209000 */
/*0210*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe40007ffe0ff */
/*0220*/ ISETP.NE.U32.AND P1, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fca0003f25070 */
/*0230*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x001e240000001000 */
/*0240*/ IADD3 R6, R8, 0xffffffe, RZ ; /* 0x0ffffffe08067810 */
/* 0x001fcc0007ffe0ff */
/*0250*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0260*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*0270*/ IMAD.MOV R9, RZ, RZ, -R7 ; /* 0x000000ffff097224 */
/* 0x002fc800078e0a07 */
/*0280*/ IMAD R9, R9, c[0x0][0x0], RZ ; /* 0x0000000009097a24 */
/* 0x000fc800078e02ff */
/*0290*/ IMAD.HI.U32 R7, R7, R9, R6 ; /* 0x0000000907077227 */
/* 0x000fcc00078e0006 */
/*02a0*/ IMAD.HI.U32 R7, R7, R0, RZ ; /* 0x0000000007077227 */
/* 0x000fc800078e00ff */
/*02b0*/ IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0a07 */
/*02c0*/ IMAD R0, R7, c[0x0][0x0], R0 ; /* 0x0000000007007a24 */
/* 0x000fca00078e0200 */
/*02d0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x0], PT ; /* 0x0000000000007a0c */
/* 0x000fda0003f06070 */
/*02e0*/ @P0 IADD3 R0, R0, -c[0x0][0x0], RZ ; /* 0x8000000000000a10 */
/* 0x000fc80007ffe0ff */
/*02f0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x0], PT ; /* 0x0000000000007a0c */
/* 0x000fda0003f06070 */
/*0300*/ @P0 IADD3 R0, R0, -c[0x0][0x0], RZ ; /* 0x8000000000000a10 */
/* 0x000fe40007ffe0ff */
/*0310*/ @!P1 LOP3.LUT R0, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff009a12 */
/* 0x000fc800078e33ff */
/*0320*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fd00003f25270 */
/*0330*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0340*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0350*/ @P1 BRA 0x390 ; /* 0x0000003000001947 */
/* 0x000fea0003800000 */
/*0360*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0370*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0380*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0390*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x0001e8000c101904 */
/*03a0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*03b0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x004fda0003f05270 */
/*03c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*03d0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x001fe400078e00ff */
/*03e0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x001ea2000c1e1900 */
/*03f0*/ LOP3.LUT R0, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100007812 */
/* 0x000fc800078ec0ff */
/*0400*/ ISETP.NE.U32.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc80003f05070 */
/*0410*/ SEL R0, R6, RZ, P0 ; /* 0x000000ff06007207 */
/* 0x000fca0000000000 */
/*0420*/ IMAD.IADD R7, R0, 0x1, R7 ; /* 0x0000000100077824 */
/* 0x004fca00078e0207 */
/*0430*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e8000c101904 */
/*0440*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea2000c1e1900 */
/*0450*/ IMAD R6, R6, 0xa, RZ ; /* 0x0000000a06067824 */
/* 0x000fe200078e02ff */
/*0460*/ LEA.HI R0, R8.reuse, R8, RZ, 0x1 ; /* 0x0000000808007211 */
/* 0x044fe400078f08ff */
/*0470*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe40007ffe0ff */
/*0480*/ SHF.R.S32.HI R0, RZ, 0x1, R0 ; /* 0x00000001ff007819 */
/* 0x000fc40000011400 */
/*0490*/ ISETP.GT.U32.AND P0, PT, R8, 0x2, PT ; /* 0x000000020800780c */
/* 0x000fc60003f04070 */
/*04a0*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x0001f4000c101904 */
/*04b0*/ @P0 BRA 0x3e0 ; /* 0xffffff2000000947 */
/* 0x000fea000383ffff */
/*04c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04d0*/ BRA 0x4d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<stdlib.h>
__global__ void transpose(int *a,int *t)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
int flag=0,comp,j=1;
if(blockIdx.x==0 || (blockIdx.x+1)%gridDim.x == 0 || threadIdx.x==0 || (threadIdx.x+1)%blockDim.x==0)
flag=1;
if(!flag)
{
t[id]=0;
while(a[id]!=0){
comp=a[id]%2;
if(comp)
comp=0;
else
comp=1;
t[id]+=(comp*j);
j*=10;
a[id]/=2;
}
}
else
{
t[id]=a[id];
}
}
int main(void)
{
int *t,m,n,i,j;
int *d_a,*d_t,*d_m;
m=4;
n=4;
int a[]={1,2,3,4,5,5,8,8,9,4,10,12,13,14,15,16};
int size=sizeof(int)*m*n;
t=(int*)malloc(m*n*sizeof(int));
cudaMalloc((void**)&d_a,size);
cudaMalloc((void**)&d_t,size);
cudaMemcpy(d_a,a,size,cudaMemcpyHostToDevice);
transpose<<<m,n>>>(d_a,d_t);
cudaMemcpy(t,d_t,size,cudaMemcpyDeviceToHost);
printf("result vector is:\n");
for(i=0;i<m;i++)
{
for(j=0;j<n;j++)
{
printf("%d\t",t[i*n+j] );
}
printf("\n");
}
cudaFree(d_a);
cudaFree(d_t);
return 0;
} | .file "tmpxft_0015ac38_00000000-6_q4.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9transposePiS_PiS_
.type _Z30__device_stub__Z9transposePiS_PiS_, @function
_Z30__device_stub__Z9transposePiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9transposePiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z9transposePiS_PiS_, .-_Z30__device_stub__Z9transposePiS_PiS_
.globl _Z9transposePiS_
.type _Z9transposePiS_, @function
_Z9transposePiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9transposePiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9transposePiS_, .-_Z9transposePiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "result vector is:\n"
.LC1:
.string "%d\t"
.LC2:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
addq $-128, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $1, 48(%rsp)
movl $2, 52(%rsp)
movl $3, 56(%rsp)
movl $4, 60(%rsp)
movl $5, 64(%rsp)
movl $5, 68(%rsp)
movl $8, 72(%rsp)
movl $8, 76(%rsp)
movl $9, 80(%rsp)
movl $4, 84(%rsp)
movl $10, 88(%rsp)
movl $12, 92(%rsp)
movl $13, 96(%rsp)
movl $14, 100(%rsp)
movl $15, 104(%rsp)
movl $16, 108(%rsp)
movl $64, %edi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 36(%rsp)
movl $1, 40(%rsp)
movl $4, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L12:
movl $2, %ecx
movl $64, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rbp
movl $0, %r13d
leaq .LC1(%rip), %r12
leaq .LC2(%rip), %r14
.L13:
leaq -16(%rbp), %rbx
.L14:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L14
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $4, %r13d
addq $16, %rbp
cmpl $16, %r13d
jne .L13
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
subq $-128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z9transposePiS_PiS_
jmp .L12
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z9transposePiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9transposePiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<stdlib.h>
__global__ void transpose(int *a,int *t)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
int flag=0,comp,j=1;
if(blockIdx.x==0 || (blockIdx.x+1)%gridDim.x == 0 || threadIdx.x==0 || (threadIdx.x+1)%blockDim.x==0)
flag=1;
if(!flag)
{
t[id]=0;
while(a[id]!=0){
comp=a[id]%2;
if(comp)
comp=0;
else
comp=1;
t[id]+=(comp*j);
j*=10;
a[id]/=2;
}
}
else
{
t[id]=a[id];
}
}
int main(void)
{
int *t,m,n,i,j;
int *d_a,*d_t,*d_m;
m=4;
n=4;
int a[]={1,2,3,4,5,5,8,8,9,4,10,12,13,14,15,16};
int size=sizeof(int)*m*n;
t=(int*)malloc(m*n*sizeof(int));
cudaMalloc((void**)&d_a,size);
cudaMalloc((void**)&d_t,size);
cudaMemcpy(d_a,a,size,cudaMemcpyHostToDevice);
transpose<<<m,n>>>(d_a,d_t);
cudaMemcpy(t,d_t,size,cudaMemcpyDeviceToHost);
printf("result vector is:\n");
for(i=0;i<m;i++)
{
for(j=0;j<n;j++)
{
printf("%d\t",t[i*n+j] );
}
printf("\n");
}
cudaFree(d_a);
cudaFree(d_t);
return 0;
} | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
__global__ void transpose(int *a,int *t)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
int flag=0,comp,j=1;
if(blockIdx.x==0 || (blockIdx.x+1)%gridDim.x == 0 || threadIdx.x==0 || (threadIdx.x+1)%blockDim.x==0)
flag=1;
if(!flag)
{
t[id]=0;
while(a[id]!=0){
comp=a[id]%2;
if(comp)
comp=0;
else
comp=1;
t[id]+=(comp*j);
j*=10;
a[id]/=2;
}
}
else
{
t[id]=a[id];
}
}
int main(void)
{
int *t,m,n,i,j;
int *d_a,*d_t,*d_m;
m=4;
n=4;
int a[]={1,2,3,4,5,5,8,8,9,4,10,12,13,14,15,16};
int size=sizeof(int)*m*n;
t=(int*)malloc(m*n*sizeof(int));
hipMalloc((void**)&d_a,size);
hipMalloc((void**)&d_t,size);
hipMemcpy(d_a,a,size,hipMemcpyHostToDevice);
transpose<<<m,n>>>(d_a,d_t);
hipMemcpy(t,d_t,size,hipMemcpyDeviceToHost);
printf("result vector is:\n");
for(i=0;i<m;i++)
{
for(j=0;j<n;j++)
{
printf("%d\t",t[i*n+j] );
}
printf("\n");
}
hipFree(d_a);
hipFree(d_t);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
__global__ void transpose(int *a,int *t)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
int flag=0,comp,j=1;
if(blockIdx.x==0 || (blockIdx.x+1)%gridDim.x == 0 || threadIdx.x==0 || (threadIdx.x+1)%blockDim.x==0)
flag=1;
if(!flag)
{
t[id]=0;
while(a[id]!=0){
comp=a[id]%2;
if(comp)
comp=0;
else
comp=1;
t[id]+=(comp*j);
j*=10;
a[id]/=2;
}
}
else
{
t[id]=a[id];
}
}
int main(void)
{
int *t,m,n,i,j;
int *d_a,*d_t,*d_m;
m=4;
n=4;
int a[]={1,2,3,4,5,5,8,8,9,4,10,12,13,14,15,16};
int size=sizeof(int)*m*n;
t=(int*)malloc(m*n*sizeof(int));
hipMalloc((void**)&d_a,size);
hipMalloc((void**)&d_t,size);
hipMemcpy(d_a,a,size,hipMemcpyHostToDevice);
transpose<<<m,n>>>(d_a,d_t);
hipMemcpy(t,d_t,size,hipMemcpyDeviceToHost);
printf("result vector is:\n");
for(i=0;i<m;i++)
{
for(j=0;j<n;j++)
{
printf("%d\t",t[i*n+j] );
}
printf("\n");
}
hipFree(d_a);
hipFree(d_t);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9transposePiS_
.globl _Z9transposePiS_
.p2align 8
.type _Z9transposePiS_,@function
_Z9transposePiS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
s_add_u32 s0, s0, 16
s_addc_u32 s1, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_cmp_eq_u32 s15, 0
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccz .LBB0_3
s_and_saveexec_b32 s0, s2
s_cbranch_execnz .LBB0_11
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_3:
s_load_b32 s0, s[0:1], 0x0
s_add_i32 s15, s15, 1
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_mov_b32 s8, -1
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v2, s0
s_sub_i32 s2, 0, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_mul_i32 s2, s2, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s2, s1, s2
s_add_i32 s1, s1, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s1, s15, s1
s_mul_i32 s1, s1, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_sub_i32 s1, s15, s1
s_sub_i32 s2, s1, s0
s_cmp_ge_u32 s1, s0
s_cselect_b32 s1, s2, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_sub_i32 s2, s1, s0
s_cmp_ge_u32 s1, s0
s_cselect_b32 s0, s2, s1
s_cmp_eq_u32 s0, 0
s_cselect_b32 s0, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, vcc_lo, s0
s_xor_b32 s1, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_10
v_cvt_f32_u32_e32 v2, s3
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v3, v2
v_add_nc_u32_e32 v0, 1, v0
v_cvt_f32_u32_e32 v4, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_trunc_f32_e32 v3, v3
v_fma_f32 v4, -v3, v2, v4
v_cvt_u32_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ge_f32_e64 vcc_lo, |v4|, |v2|
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, s3
v_sub_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v0, 0xffff, v0
v_cmpx_ne_u32_e32 0, v0
s_cbranch_execz .LBB0_9
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v0, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_store_b32 v[2:3], v0, off
global_load_b32 v0, v[4:5], off
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e32 0, v0
s_cbranch_execz .LBB0_8
s_mov_b32 s8, 1
s_mov_b32 s9, 0
.p2align 6
.LBB0_7:
global_load_b32 v6, v[2:3], off
v_not_b32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v0, 1, v0
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[7:8], null, v0, s8, v[6:7]
s_mul_i32 s8, s8, 10
global_store_b32 v[2:3], v7, off
global_load_b32 v0, v[4:5], off
s_waitcnt vmcnt(0)
v_lshrrev_b32_e32 v6, 31, v0
v_add_nc_u32_e32 v7, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v0, v0, v6
v_cmp_gt_u32_e32 vcc_lo, 3, v7
s_delay_alu instid0(VALU_DEP_2)
v_ashrrev_i32_e32 v0, 1, v0
s_or_b32 s9, vcc_lo, s9
global_store_b32 v[4:5], v0, off
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_7
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s8, exec_lo, -1
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s1, s2, exec_lo
s_and_b32 s2, s8, exec_lo
s_or_b32 s2, s1, s2
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s0
s_and_saveexec_b32 s0, s2
s_cbranch_execz .LBB0_2
.LBB0_11:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9transposePiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9transposePiS_, .Lfunc_end0-_Z9transposePiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9transposePiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9transposePiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
__global__ void transpose(int *a,int *t)
{
int id=blockIdx.x*blockDim.x+threadIdx.x;
int flag=0,comp,j=1;
if(blockIdx.x==0 || (blockIdx.x+1)%gridDim.x == 0 || threadIdx.x==0 || (threadIdx.x+1)%blockDim.x==0)
flag=1;
if(!flag)
{
t[id]=0;
while(a[id]!=0){
comp=a[id]%2;
if(comp)
comp=0;
else
comp=1;
t[id]+=(comp*j);
j*=10;
a[id]/=2;
}
}
else
{
t[id]=a[id];
}
}
int main(void)
{
int *t,m,n,i,j;
int *d_a,*d_t,*d_m;
m=4;
n=4;
int a[]={1,2,3,4,5,5,8,8,9,4,10,12,13,14,15,16};
int size=sizeof(int)*m*n;
t=(int*)malloc(m*n*sizeof(int));
hipMalloc((void**)&d_a,size);
hipMalloc((void**)&d_t,size);
hipMemcpy(d_a,a,size,hipMemcpyHostToDevice);
transpose<<<m,n>>>(d_a,d_t);
hipMemcpy(t,d_t,size,hipMemcpyDeviceToHost);
printf("result vector is:\n");
for(i=0;i<m;i++)
{
for(j=0;j<n;j++)
{
printf("%d\t",t[i*n+j] );
}
printf("\n");
}
hipFree(d_a);
hipFree(d_t);
return 0;
} | .text
.file "q4.hip"
.globl _Z24__device_stub__transposePiS_ # -- Begin function _Z24__device_stub__transposePiS_
.p2align 4, 0x90
.type _Z24__device_stub__transposePiS_,@function
_Z24__device_stub__transposePiS_: # @_Z24__device_stub__transposePiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9transposePiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__transposePiS_, .Lfunc_end0-_Z24__device_stub__transposePiS_
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 1 # 0x1
.long 2 # 0x2
.long 3 # 0x3
.long 4 # 0x4
.LCPI1_1:
.long 5 # 0x5
.long 5 # 0x5
.long 8 # 0x8
.long 8 # 0x8
.LCPI1_2:
.long 9 # 0x9
.long 4 # 0x4
.long 10 # 0xa
.long 12 # 0xc
.LCPI1_3:
.long 13 # 0xd
.long 14 # 0xe
.long 15 # 0xf
.long 16 # 0x10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $160, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [1,2,3,4]
movaps %xmm0, 96(%rsp)
movaps .LCPI1_1(%rip), %xmm0 # xmm0 = [5,5,8,8]
movaps %xmm0, 112(%rsp)
movaps .LCPI1_2(%rip), %xmm0 # xmm0 = [9,4,10,12]
movaps %xmm0, 128(%rsp)
movaps .LCPI1_3(%rip), %xmm0 # xmm0 = [13,14,15,16]
movaps %xmm0, 144(%rsp)
movl $64, %edi
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq %rsp, %rdi
movl $64, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 96(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967300, %rdi # imm = 0x100000004
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9transposePiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
movl $64, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_3 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $4, %r15
jne .LBB1_4
# %bb.5: # in Loop: Header=BB1_3 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $16, %rbx
cmpq $4, %r14
jne .LBB1_3
# %bb.6:
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $160, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9transposePiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9transposePiS_,@object # @_Z9transposePiS_
.section .rodata,"a",@progbits
.globl _Z9transposePiS_
.p2align 3, 0x0
_Z9transposePiS_:
.quad _Z24__device_stub__transposePiS_
.size _Z9transposePiS_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d\t"
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9transposePiS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "result vector is:"
.size .Lstr, 18
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__transposePiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9transposePiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9transposePiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ PLOP3.LUT P1, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f2e170 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0050*/ ISETP.NE.AND P0, PT, R11.reuse, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x041fe20003f05270 */
/*0060*/ IMAD R4, R11, c[0x0][0x0], R0 ; /* 0x000000000b047a24 */
/* 0x002fc800078e0200 */
/*0070*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fc800078e0205 */
/*0080*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0205 */
/*0090*/ @!P0 BRA 0x340 ; /* 0x000002a000008947 */
/* 0x000fea0003800000 */
/*00a0*/ I2F.U32.RP R8, c[0x0][0xc] ; /* 0x0000030000087b06 */
/* 0x000e220000209000 */
/*00b0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*00c0*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0xc], PT ; /* 0x00000300ff007a0c */
/* 0x000fe20003f45070 */
/*00d0*/ BSSY B0, 0x340 ; /* 0x0000026000007945 */
/* 0x000fea0003800000 */
/*00e0*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x001e240000001000 */
/*00f0*/ IADD3 R7, R8, 0xffffffe, RZ ; /* 0x0ffffffe08077810 */
/* 0x001fcc0007ffe0ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e24000021f000 */
/*0110*/ IMAD.MOV R9, RZ, RZ, -R7 ; /* 0x000000ffff097224 */
/* 0x001fc800078e0a07 */
/*0120*/ IMAD R9, R9, c[0x0][0xc], RZ ; /* 0x0000030009097a24 */
/* 0x000fc800078e02ff */
/*0130*/ IMAD.HI.U32 R9, R7, R9, R6 ; /* 0x0000000907097227 */
/* 0x000fe200078e0006 */
/*0140*/ IADD3 R6, R11, 0x1, RZ ; /* 0x000000010b067810 */
/* 0x000fca0007ffe0ff */
/*0150*/ IMAD.HI.U32 R9, R9, R6, RZ ; /* 0x0000000609097227 */
/* 0x000fc800078e00ff */
/*0160*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fc800078e0a09 */
/*0170*/ IMAD R6, R9, c[0x0][0xc], R6 ; /* 0x0000030009067a24 */
/* 0x000fca00078e0206 */
/*0180*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0xc], PT ; /* 0x0000030006007a0c */
/* 0x000fda0003f06070 */
/*0190*/ @P0 IADD3 R6, R6, -c[0x0][0xc], RZ ; /* 0x8000030006060a10 */
/* 0x000fc80007ffe0ff */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0xc], PT ; /* 0x0000030006007a0c */
/* 0x000fda0003f06070 */
/*01b0*/ @P0 IADD3 R6, R6, -c[0x0][0xc], RZ ; /* 0x8000030006060a10 */
/* 0x000fe40007ffe0ff */
/*01c0*/ @!P2 LOP3.LUT R6, RZ, c[0x0][0xc], RZ, 0x33, !PT ; /* 0x00000300ff06aa12 */
/* 0x000fc800078e33ff */
/*01d0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc80003f05270 */
/*01e0*/ ISETP.EQ.OR P0, PT, R0, RZ, !P0 ; /* 0x000000ff0000720c */
/* 0x000fda0004702670 */
/*01f0*/ @P0 BRA 0x330 ; /* 0x0000013000000947 */
/* 0x000fea0003800000 */
/*0200*/ I2F.U32.RP R8, c[0x0][0x0] ; /* 0x0000000000087b06 */
/* 0x000e220000209000 */
/*0210*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe40007ffe0ff */
/*0220*/ ISETP.NE.U32.AND P1, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fca0003f25070 */
/*0230*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x001e240000001000 */
/*0240*/ IADD3 R6, R8, 0xffffffe, RZ ; /* 0x0ffffffe08067810 */
/* 0x001fcc0007ffe0ff */
/*0250*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0260*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*0270*/ IMAD.MOV R9, RZ, RZ, -R7 ; /* 0x000000ffff097224 */
/* 0x002fc800078e0a07 */
/*0280*/ IMAD R9, R9, c[0x0][0x0], RZ ; /* 0x0000000009097a24 */
/* 0x000fc800078e02ff */
/*0290*/ IMAD.HI.U32 R7, R7, R9, R6 ; /* 0x0000000907077227 */
/* 0x000fcc00078e0006 */
/*02a0*/ IMAD.HI.U32 R7, R7, R0, RZ ; /* 0x0000000007077227 */
/* 0x000fc800078e00ff */
/*02b0*/ IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0a07 */
/*02c0*/ IMAD R0, R7, c[0x0][0x0], R0 ; /* 0x0000000007007a24 */
/* 0x000fca00078e0200 */
/*02d0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x0], PT ; /* 0x0000000000007a0c */
/* 0x000fda0003f06070 */
/*02e0*/ @P0 IADD3 R0, R0, -c[0x0][0x0], RZ ; /* 0x8000000000000a10 */
/* 0x000fc80007ffe0ff */
/*02f0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x0], PT ; /* 0x0000000000007a0c */
/* 0x000fda0003f06070 */
/*0300*/ @P0 IADD3 R0, R0, -c[0x0][0x0], RZ ; /* 0x8000000000000a10 */
/* 0x000fe40007ffe0ff */
/*0310*/ @!P1 LOP3.LUT R0, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff009a12 */
/* 0x000fc800078e33ff */
/*0320*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fd00003f25270 */
/*0330*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0340*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0350*/ @P1 BRA 0x390 ; /* 0x0000003000001947 */
/* 0x000fea0003800000 */
/*0360*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0370*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0380*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0390*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x0001e8000c101904 */
/*03a0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*03b0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x004fda0003f05270 */
/*03c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*03d0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x001fe400078e00ff */
/*03e0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x001ea2000c1e1900 */
/*03f0*/ LOP3.LUT R0, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100007812 */
/* 0x000fc800078ec0ff */
/*0400*/ ISETP.NE.U32.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc80003f05070 */
/*0410*/ SEL R0, R6, RZ, P0 ; /* 0x000000ff06007207 */
/* 0x000fca0000000000 */
/*0420*/ IMAD.IADD R7, R0, 0x1, R7 ; /* 0x0000000100077824 */
/* 0x004fca00078e0207 */
/*0430*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e8000c101904 */
/*0440*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea2000c1e1900 */
/*0450*/ IMAD R6, R6, 0xa, RZ ; /* 0x0000000a06067824 */
/* 0x000fe200078e02ff */
/*0460*/ LEA.HI R0, R8.reuse, R8, RZ, 0x1 ; /* 0x0000000808007211 */
/* 0x044fe400078f08ff */
/*0470*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe40007ffe0ff */
/*0480*/ SHF.R.S32.HI R0, RZ, 0x1, R0 ; /* 0x00000001ff007819 */
/* 0x000fc40000011400 */
/*0490*/ ISETP.GT.U32.AND P0, PT, R8, 0x2, PT ; /* 0x000000020800780c */
/* 0x000fc60003f04070 */
/*04a0*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x0001f4000c101904 */
/*04b0*/ @P0 BRA 0x3e0 ; /* 0xffffff2000000947 */
/* 0x000fea000383ffff */
/*04c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04d0*/ BRA 0x4d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9transposePiS_
.globl _Z9transposePiS_
.p2align 8
.type _Z9transposePiS_,@function
_Z9transposePiS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
s_add_u32 s0, s0, 16
s_addc_u32 s1, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_cmp_eq_u32 s15, 0
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccz .LBB0_3
s_and_saveexec_b32 s0, s2
s_cbranch_execnz .LBB0_11
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_3:
s_load_b32 s0, s[0:1], 0x0
s_add_i32 s15, s15, 1
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_mov_b32 s8, -1
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v2, s0
s_sub_i32 s2, 0, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_mul_i32 s2, s2, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s2, s1, s2
s_add_i32 s1, s1, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s1, s15, s1
s_mul_i32 s1, s1, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_sub_i32 s1, s15, s1
s_sub_i32 s2, s1, s0
s_cmp_ge_u32 s1, s0
s_cselect_b32 s1, s2, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_sub_i32 s2, s1, s0
s_cmp_ge_u32 s1, s0
s_cselect_b32 s0, s2, s1
s_cmp_eq_u32 s0, 0
s_cselect_b32 s0, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, vcc_lo, s0
s_xor_b32 s1, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_10
v_cvt_f32_u32_e32 v2, s3
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v3, v2
v_add_nc_u32_e32 v0, 1, v0
v_cvt_f32_u32_e32 v4, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_trunc_f32_e32 v3, v3
v_fma_f32 v4, -v3, v2, v4
v_cvt_u32_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ge_f32_e64 vcc_lo, |v4|, |v2|
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, s3
v_sub_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v0, 0xffff, v0
v_cmpx_ne_u32_e32 0, v0
s_cbranch_execz .LBB0_9
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v0, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_store_b32 v[2:3], v0, off
global_load_b32 v0, v[4:5], off
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e32 0, v0
s_cbranch_execz .LBB0_8
s_mov_b32 s8, 1
s_mov_b32 s9, 0
.p2align 6
.LBB0_7:
global_load_b32 v6, v[2:3], off
v_not_b32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v0, 1, v0
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[7:8], null, v0, s8, v[6:7]
s_mul_i32 s8, s8, 10
global_store_b32 v[2:3], v7, off
global_load_b32 v0, v[4:5], off
s_waitcnt vmcnt(0)
v_lshrrev_b32_e32 v6, 31, v0
v_add_nc_u32_e32 v7, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v0, v0, v6
v_cmp_gt_u32_e32 vcc_lo, 3, v7
s_delay_alu instid0(VALU_DEP_2)
v_ashrrev_i32_e32 v0, 1, v0
s_or_b32 s9, vcc_lo, s9
global_store_b32 v[4:5], v0, off
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_7
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s8, exec_lo, -1
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s1, s2, exec_lo
s_and_b32 s2, s8, exec_lo
s_or_b32 s2, s1, s2
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s0
s_and_saveexec_b32 s0, s2
s_cbranch_execz .LBB0_2
.LBB0_11:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9transposePiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9transposePiS_, .Lfunc_end0-_Z9transposePiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9transposePiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9transposePiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015ac38_00000000-6_q4.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9transposePiS_PiS_
.type _Z30__device_stub__Z9transposePiS_PiS_, @function
_Z30__device_stub__Z9transposePiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9transposePiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z9transposePiS_PiS_, .-_Z30__device_stub__Z9transposePiS_PiS_
.globl _Z9transposePiS_
.type _Z9transposePiS_, @function
_Z9transposePiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9transposePiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9transposePiS_, .-_Z9transposePiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "result vector is:\n"
.LC1:
.string "%d\t"
.LC2:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
addq $-128, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $1, 48(%rsp)
movl $2, 52(%rsp)
movl $3, 56(%rsp)
movl $4, 60(%rsp)
movl $5, 64(%rsp)
movl $5, 68(%rsp)
movl $8, 72(%rsp)
movl $8, 76(%rsp)
movl $9, 80(%rsp)
movl $4, 84(%rsp)
movl $10, 88(%rsp)
movl $12, 92(%rsp)
movl $13, 96(%rsp)
movl $14, 100(%rsp)
movl $15, 104(%rsp)
movl $16, 108(%rsp)
movl $64, %edi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 36(%rsp)
movl $1, 40(%rsp)
movl $4, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L12:
movl $2, %ecx
movl $64, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rbp
movl $0, %r13d
leaq .LC1(%rip), %r12
leaq .LC2(%rip), %r14
.L13:
leaq -16(%rbp), %rbx
.L14:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L14
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $4, %r13d
addq $16, %rbp
cmpl $16, %r13d
jne .L13
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
subq $-128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z9transposePiS_PiS_
jmp .L12
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z9transposePiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9transposePiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "q4.hip"
.globl _Z24__device_stub__transposePiS_ # -- Begin function _Z24__device_stub__transposePiS_
.p2align 4, 0x90
.type _Z24__device_stub__transposePiS_,@function
_Z24__device_stub__transposePiS_: # @_Z24__device_stub__transposePiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9transposePiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__transposePiS_, .Lfunc_end0-_Z24__device_stub__transposePiS_
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 1 # 0x1
.long 2 # 0x2
.long 3 # 0x3
.long 4 # 0x4
.LCPI1_1:
.long 5 # 0x5
.long 5 # 0x5
.long 8 # 0x8
.long 8 # 0x8
.LCPI1_2:
.long 9 # 0x9
.long 4 # 0x4
.long 10 # 0xa
.long 12 # 0xc
.LCPI1_3:
.long 13 # 0xd
.long 14 # 0xe
.long 15 # 0xf
.long 16 # 0x10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $160, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [1,2,3,4]
movaps %xmm0, 96(%rsp)
movaps .LCPI1_1(%rip), %xmm0 # xmm0 = [5,5,8,8]
movaps %xmm0, 112(%rsp)
movaps .LCPI1_2(%rip), %xmm0 # xmm0 = [9,4,10,12]
movaps %xmm0, 128(%rsp)
movaps .LCPI1_3(%rip), %xmm0 # xmm0 = [13,14,15,16]
movaps %xmm0, 144(%rsp)
movl $64, %edi
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq %rsp, %rdi
movl $64, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 96(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967300, %rdi # imm = 0x100000004
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9transposePiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
movl $64, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_3 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $4, %r15
jne .LBB1_4
# %bb.5: # in Loop: Header=BB1_3 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $16, %rbx
cmpq $4, %r14
jne .LBB1_3
# %bb.6:
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $160, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9transposePiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9transposePiS_,@object # @_Z9transposePiS_
.section .rodata,"a",@progbits
.globl _Z9transposePiS_
.p2align 3, 0x0
_Z9transposePiS_:
.quad _Z24__device_stub__transposePiS_
.size _Z9transposePiS_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d\t"
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9transposePiS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "result vector is:"
.size .Lstr, 18
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__transposePiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9transposePiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#define THREAD_PER_BLOCK 1024.0
#define CUDAMALLOC_ERROR(_err) \
do { \
if (_err != cudaSuccess) { \
printf("%s in %s at line %d\n", cudaGetErrorString(_err),__FILE__,__LINE__); \
exit(EXIT_FAILURE); \
} \
}while(0)
void init_array(float *array, long size, float value) {
for (size_t i = 0; i < size; ++i) {
array[i] = value;
}
}
__global__
void vecAddKernel(float *A, float *B, float *C, long n) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < n) {
C[i] = A[i] + B[i];
}
}
void vecAdd(float *h_A, float *h_B, float *h_C, long n) {
float *d_A, *d_B, *d_C;
long size = n * sizeof (float);
cudaError_t err = cudaMalloc((void **) &d_A, size);
CUDAMALLOC_ERROR(err);
err = cudaMalloc((void **) &d_B, size);
CUDAMALLOC_ERROR(err);
err = cudaMalloc((void **) &d_C, size);
CUDAMALLOC_ERROR(err);
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_C, h_C, size, cudaMemcpyHostToDevice);
dim3 dimGrid{(uint) ceil(n/THREAD_PER_BLOCK),1,1};
dim3 dimBlock = {(uint) THREAD_PER_BLOCK,1,1};
// KERNEL LAUNCH
vecAddKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C, n);
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
}
int main() {
clock_t begin = clock();
long nbElements = 10e7;
long size = nbElements * sizeof(float);
float *h_A, *h_B, *h_C;
h_A = (float *) malloc(size);
h_B = (float *) malloc(size);
h_C = (float *) malloc(size);
init_array(h_A, nbElements, 1);
init_array(h_B, nbElements, 2);
init_array(h_C, nbElements, 0);
vecAdd(h_A, h_B, h_C, nbElements);
for (int i = 10e6; i < 10e7; ++i) {
std::cout << h_C[i] << std::endl;
}
free(h_A); free(h_B); free(h_C);
clock_t end = clock();
double elapsed_time = (double)(end - begin) / CLOCKS_PER_SEC;
std::cout << elapsed_time << "s" << std::endl;
return 0;
} | code for sm_80
Function : _Z12vecAddKernelPfS_S_l
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.AND.EX P0, PT, R3, c[0x0][0x17c], PT, P0 ; /* 0x00005f0003007a0c */
/* 0x000fda0003f06300 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.SHL.U32 R6, R0.reuse, 0x4, RZ ; /* 0x0000000400067824 */
/* 0x040fe200078e00ff */
/*0090*/ SHF.L.U64.HI R0, R0, 0x2, R3 ; /* 0x0000000200007819 */
/* 0x000fe20000010203 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00b0*/ IADD3 R4, P0, R6.reuse, c[0x0][0x160], RZ ; /* 0x0000580006047a10 */
/* 0x040fe40007f1e0ff */
/*00c0*/ IADD3 R2, P1, R6, c[0x0][0x168], RZ ; /* 0x00005a0006027a10 */
/* 0x000fe40007f3e0ff */
/*00d0*/ IADD3.X R5, R0.reuse, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000057a10 */
/* 0x040fe400007fe4ff */
/*00e0*/ IADD3.X R3, R0, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000037a10 */
/* 0x000fc80000ffe4ff */
/*00f0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IADD3 R6, P0, R6, c[0x0][0x170], RZ ; /* 0x00005c0006067a10 */
/* 0x000fc80007f1e0ff */
/*0120*/ IADD3.X R7, R0, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0000077a10 */
/* 0x000fe200007fe4ff */
/*0130*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*0140*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#define THREAD_PER_BLOCK 1024.0
#define CUDAMALLOC_ERROR(_err) \
do { \
if (_err != cudaSuccess) { \
printf("%s in %s at line %d\n", cudaGetErrorString(_err),__FILE__,__LINE__); \
exit(EXIT_FAILURE); \
} \
}while(0)
void init_array(float *array, long size, float value) {
for (size_t i = 0; i < size; ++i) {
array[i] = value;
}
}
__global__
void vecAddKernel(float *A, float *B, float *C, long n) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < n) {
C[i] = A[i] + B[i];
}
}
void vecAdd(float *h_A, float *h_B, float *h_C, long n) {
float *d_A, *d_B, *d_C;
long size = n * sizeof (float);
cudaError_t err = cudaMalloc((void **) &d_A, size);
CUDAMALLOC_ERROR(err);
err = cudaMalloc((void **) &d_B, size);
CUDAMALLOC_ERROR(err);
err = cudaMalloc((void **) &d_C, size);
CUDAMALLOC_ERROR(err);
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_C, h_C, size, cudaMemcpyHostToDevice);
dim3 dimGrid{(uint) ceil(n/THREAD_PER_BLOCK),1,1};
dim3 dimBlock = {(uint) THREAD_PER_BLOCK,1,1};
// KERNEL LAUNCH
vecAddKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C, n);
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
}
int main() {
clock_t begin = clock();
long nbElements = 10e7;
long size = nbElements * sizeof(float);
float *h_A, *h_B, *h_C;
h_A = (float *) malloc(size);
h_B = (float *) malloc(size);
h_C = (float *) malloc(size);
init_array(h_A, nbElements, 1);
init_array(h_B, nbElements, 2);
init_array(h_C, nbElements, 0);
vecAdd(h_A, h_B, h_C, nbElements);
for (int i = 10e6; i < 10e7; ++i) {
std::cout << h_C[i] << std::endl;
}
free(h_A); free(h_B); free(h_C);
clock_t end = clock();
double elapsed_time = (double)(end - begin) / CLOCKS_PER_SEC;
std::cout << elapsed_time << "s" << std::endl;
return 0;
} | .file "tmpxft_00047a2a_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10init_arrayPflf
.type _Z10init_arrayPflf, @function
_Z10init_arrayPflf:
.LFB3669:
.cfi_startproc
endbr64
testq %rsi, %rsi
je .L3
movq %rdi, %rax
leaq (%rdi,%rsi,4), %rdx
.L5:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE3669:
.size _Z10init_arrayPflf, .-_Z10init_arrayPflf
.globl _Z37__device_stub__Z12vecAddKernelPfS_S_lPfS_S_l
.type _Z37__device_stub__Z12vecAddKernelPfS_S_lPfS_S_l, @function
_Z37__device_stub__Z12vecAddKernelPfS_S_lPfS_S_l:
.LFB3696:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12vecAddKernelPfS_S_l(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z37__device_stub__Z12vecAddKernelPfS_S_lPfS_S_l, .-_Z37__device_stub__Z12vecAddKernelPfS_S_lPfS_S_l
.globl _Z12vecAddKernelPfS_S_l
.type _Z12vecAddKernelPfS_S_l, @function
_Z12vecAddKernelPfS_S_l:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12vecAddKernelPfS_S_lPfS_S_l
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z12vecAddKernelPfS_S_l, .-_Z12vecAddKernelPfS_S_l
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/KarlEmm/gpu_paralell/main/first_program/main.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%s in %s at line %d\n"
.text
.globl _Z6vecAddPfS_S_l
.type _Z6vecAddPfS_S_l, @function
_Z6vecAddPfS_S_l:
.LFB3670:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %r12
movq %rcx, %rbp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 0(,%rcx,4), %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L23
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L24
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L25
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rbp, %xmm0
mulsd .LC2(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC6(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC3(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L19
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC5(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L19:
cvttsd2siq %xmm3, %rax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L20:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $33, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L24:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $35, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L25:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $37, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L26:
movq %rbp, %rcx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z37__device_stub__Z12vecAddKernelPfS_S_lPfS_S_l
jmp .L20
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size _Z6vecAddPfS_S_l, .-_Z6vecAddPfS_S_l
.section .rodata.str1.1
.LC11:
.string "s"
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
call clock@PLT
movq %rax, 8(%rsp)
movl $400000000, %edi
call malloc@PLT
movq %rax, %r14
movq %rax, 16(%rsp)
movl $400000000, %edi
call malloc@PLT
movq %rax, %rbx
movq %rax, 24(%rsp)
movl $400000000, %edi
call malloc@PLT
movq %rax, %r15
movss .LC7(%rip), %xmm0
movl $100000000, %esi
movq %r14, %rdi
call _Z10init_arrayPflf
movss .LC8(%rip), %xmm0
movl $100000000, %esi
movq %rbx, %rdi
call _Z10init_arrayPflf
pxor %xmm0, %xmm0
movl $100000000, %esi
movq %r15, %rdi
call _Z10init_arrayPflf
movl $100000000, %ecx
movq %r15, %rdx
movq %rbx, %rsi
movq %r14, %rdi
call _Z6vecAddPfS_S_l
leaq 40000000(%r15), %r12
leaq 400000000(%r15), %r14
leaq _ZSt4cout(%rip), %r13
jmp .L32
.L36:
call _ZSt16__throw_bad_castv@PLT
.L37:
movzbl 67(%rbp), %esi
.L31:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $4, %r12
cmpq %r12, %r14
je .L35
.L32:
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L36
cmpb $0, 56(%rbp)
jne .L37
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L31
.L35:
movq 16(%rsp), %rdi
call free@PLT
movq 24(%rsp), %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
call clock@PLT
movq 8(%rsp), %rdx
subq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC10(%rip), %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC11(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %eax
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3671:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z12vecAddKernelPfS_S_l"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z12vecAddKernelPfS_S_l(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1062207488
.align 8
.LC3:
.long 0
.long 1127219200
.align 8
.LC5:
.long 0
.long 1072693248
.align 8
.LC6:
.long -1
.long 2147483647
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC7:
.long 1065353216
.align 4
.LC8:
.long 1073741824
.section .rodata.cst8
.align 8
.LC10:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#define THREAD_PER_BLOCK 1024.0
#define CUDAMALLOC_ERROR(_err) \
do { \
if (_err != cudaSuccess) { \
printf("%s in %s at line %d\n", cudaGetErrorString(_err),__FILE__,__LINE__); \
exit(EXIT_FAILURE); \
} \
}while(0)
void init_array(float *array, long size, float value) {
for (size_t i = 0; i < size; ++i) {
array[i] = value;
}
}
__global__
void vecAddKernel(float *A, float *B, float *C, long n) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < n) {
C[i] = A[i] + B[i];
}
}
void vecAdd(float *h_A, float *h_B, float *h_C, long n) {
float *d_A, *d_B, *d_C;
long size = n * sizeof (float);
cudaError_t err = cudaMalloc((void **) &d_A, size);
CUDAMALLOC_ERROR(err);
err = cudaMalloc((void **) &d_B, size);
CUDAMALLOC_ERROR(err);
err = cudaMalloc((void **) &d_C, size);
CUDAMALLOC_ERROR(err);
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_C, h_C, size, cudaMemcpyHostToDevice);
dim3 dimGrid{(uint) ceil(n/THREAD_PER_BLOCK),1,1};
dim3 dimBlock = {(uint) THREAD_PER_BLOCK,1,1};
// KERNEL LAUNCH
vecAddKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C, n);
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
}
int main() {
clock_t begin = clock();
long nbElements = 10e7;
long size = nbElements * sizeof(float);
float *h_A, *h_B, *h_C;
h_A = (float *) malloc(size);
h_B = (float *) malloc(size);
h_C = (float *) malloc(size);
init_array(h_A, nbElements, 1);
init_array(h_B, nbElements, 2);
init_array(h_C, nbElements, 0);
vecAdd(h_A, h_B, h_C, nbElements);
for (int i = 10e6; i < 10e7; ++i) {
std::cout << h_C[i] << std::endl;
}
free(h_A); free(h_B); free(h_C);
clock_t end = clock();
double elapsed_time = (double)(end - begin) / CLOCKS_PER_SEC;
std::cout << elapsed_time << "s" << std::endl;
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#define THREAD_PER_BLOCK 1024.0
#define CUDAMALLOC_ERROR(_err) \
do { \
if (_err != hipSuccess) { \
printf("%s in %s at line %d\n", hipGetErrorString(_err),__FILE__,__LINE__); \
exit(EXIT_FAILURE); \
} \
}while(0)
void init_array(float *array, long size, float value) {
for (size_t i = 0; i < size; ++i) {
array[i] = value;
}
}
__global__
void vecAddKernel(float *A, float *B, float *C, long n) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < n) {
C[i] = A[i] + B[i];
}
}
void vecAdd(float *h_A, float *h_B, float *h_C, long n) {
float *d_A, *d_B, *d_C;
long size = n * sizeof (float);
hipError_t err = hipMalloc((void **) &d_A, size);
CUDAMALLOC_ERROR(err);
err = hipMalloc((void **) &d_B, size);
CUDAMALLOC_ERROR(err);
err = hipMalloc((void **) &d_C, size);
CUDAMALLOC_ERROR(err);
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
hipMemcpy(d_C, h_C, size, hipMemcpyHostToDevice);
dim3 dimGrid{(uint) ceil(n/THREAD_PER_BLOCK),1,1};
dim3 dimBlock = {(uint) THREAD_PER_BLOCK,1,1};
// KERNEL LAUNCH
vecAddKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C, n);
hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
}
int main() {
clock_t begin = clock();
long nbElements = 10e7;
long size = nbElements * sizeof(float);
float *h_A, *h_B, *h_C;
h_A = (float *) malloc(size);
h_B = (float *) malloc(size);
h_C = (float *) malloc(size);
init_array(h_A, nbElements, 1);
init_array(h_B, nbElements, 2);
init_array(h_C, nbElements, 0);
vecAdd(h_A, h_B, h_C, nbElements);
for (int i = 10e6; i < 10e7; ++i) {
std::cout << h_C[i] << std::endl;
}
free(h_A); free(h_B); free(h_C);
clock_t end = clock();
double elapsed_time = (double)(end - begin) / CLOCKS_PER_SEC;
std::cout << elapsed_time << "s" << std::endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#define THREAD_PER_BLOCK 1024.0
#define CUDAMALLOC_ERROR(_err) \
do { \
if (_err != hipSuccess) { \
printf("%s in %s at line %d\n", hipGetErrorString(_err),__FILE__,__LINE__); \
exit(EXIT_FAILURE); \
} \
}while(0)
void init_array(float *array, long size, float value) {
for (size_t i = 0; i < size; ++i) {
array[i] = value;
}
}
__global__
void vecAddKernel(float *A, float *B, float *C, long n) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < n) {
C[i] = A[i] + B[i];
}
}
void vecAdd(float *h_A, float *h_B, float *h_C, long n) {
float *d_A, *d_B, *d_C;
long size = n * sizeof (float);
hipError_t err = hipMalloc((void **) &d_A, size);
CUDAMALLOC_ERROR(err);
err = hipMalloc((void **) &d_B, size);
CUDAMALLOC_ERROR(err);
err = hipMalloc((void **) &d_C, size);
CUDAMALLOC_ERROR(err);
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
hipMemcpy(d_C, h_C, size, hipMemcpyHostToDevice);
dim3 dimGrid{(uint) ceil(n/THREAD_PER_BLOCK),1,1};
dim3 dimBlock = {(uint) THREAD_PER_BLOCK,1,1};
// KERNEL LAUNCH
vecAddKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C, n);
hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
}
int main() {
clock_t begin = clock();
long nbElements = 10e7;
long size = nbElements * sizeof(float);
float *h_A, *h_B, *h_C;
h_A = (float *) malloc(size);
h_B = (float *) malloc(size);
h_C = (float *) malloc(size);
init_array(h_A, nbElements, 1);
init_array(h_B, nbElements, 2);
init_array(h_C, nbElements, 0);
vecAdd(h_A, h_B, h_C, nbElements);
for (int i = 10e6; i < 10e7; ++i) {
std::cout << h_C[i] << std::endl;
}
free(h_A); free(h_B); free(h_C);
clock_t end = clock();
double elapsed_time = (double)(end - begin) / CLOCKS_PER_SEC;
std::cout << elapsed_time << "s" << std::endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12vecAddKernelPfS_S_l
.globl _Z12vecAddKernelPfS_S_l
.p2align 8
.type _Z12vecAddKernelPfS_S_l,@function
_Z12vecAddKernelPfS_S_l:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12vecAddKernelPfS_S_l
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12vecAddKernelPfS_S_l, .Lfunc_end0-_Z12vecAddKernelPfS_S_l
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12vecAddKernelPfS_S_l
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12vecAddKernelPfS_S_l.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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