system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <cuda_runtime_api.h>
#include <stdio.h>
__global__ void kernel( int *a, int dimx, int dimy ) {
int ix = blockIdx.x*blockDim.x + threadIdx.x;
int iy = blockIdx.y*blockDim.y + threadIdx.y;
int idx = iy*dimx + ix;
a[idx] = a[idx]+1;
}
int main() {
int dimx = 16, dimy = 16;
int num_bytes = dimx*dimy*sizeof(int);
int *d_a=0, *h_a=0; // device and host pointers h_a = (int*)malloc(num_bytes);
cudaMalloc( (void**)&d_a, num_bytes );
if( 0==h_a || 0==d_a ) {
printf("couldn't allocate memory\n"); return 1;
}
cudaMemset( d_a, 0, num_bytes );
dim3 grid, block;
block.x = 4; block.y = 4;
grid.x = dimx / block.x;
grid.y = dimy / block.y;
kernel<<<grid, block>>>( d_a, dimx, dimy );
cudaMemcpy(h_a, d_a, num_bytes, cudaMemcpyDeviceToHost );
free( h_a ); cudaFree( d_a );
return 0;
} | code for sm_80
Function : _Z6kernelPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0040*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fe200078e0205 */
/*0080*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fc600000001ff */
/*0090*/ IMAD R3, R3, c[0x0][0x168], R0 ; /* 0x00005a0003037a24 */
/* 0x000fce00078e0200 */
/*00a0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*00b0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ IADD3 R5, R0, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x004fca0007ffe0ff */
/*00d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cuda_runtime_api.h>
#include <stdio.h>
__global__ void kernel( int *a, int dimx, int dimy ) {
int ix = blockIdx.x*blockDim.x + threadIdx.x;
int iy = blockIdx.y*blockDim.y + threadIdx.y;
int idx = iy*dimx + ix;
a[idx] = a[idx]+1;
}
int main() {
int dimx = 16, dimy = 16;
int num_bytes = dimx*dimy*sizeof(int);
int *d_a=0, *h_a=0; // device and host pointers h_a = (int*)malloc(num_bytes);
cudaMalloc( (void**)&d_a, num_bytes );
if( 0==h_a || 0==d_a ) {
printf("couldn't allocate memory\n"); return 1;
}
cudaMemset( d_a, 0, num_bytes );
dim3 grid, block;
block.x = 4; block.y = 4;
grid.x = dimx / block.x;
grid.y = dimy / block.y;
kernel<<<grid, block>>>( d_a, dimx, dimy );
cudaMemcpy(h_a, d_a, num_bytes, cudaMemcpyDeviceToHost );
free( h_a ); cudaFree( d_a );
return 0;
} | .file "tmpxft_001b5f56_00000000-6_example.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "couldn't allocate memory\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq %rsp, %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $1, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z27__device_stub__Z6kernelPiiiPiii
.type _Z27__device_stub__Z6kernelPiiiPiii, @function
_Z27__device_stub__Z6kernelPiiiPiii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z6kernelPiiiPiii, .-_Z27__device_stub__Z6kernelPiiiPiii
.globl _Z6kernelPiii
.type _Z6kernelPiii, @function
_Z6kernelPiii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6kernelPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelPiii, .-_Z6kernelPiii
.section .rodata.str1.1
.LC1:
.string "_Z6kernelPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cuda_runtime_api.h>
#include <stdio.h>
__global__ void kernel( int *a, int dimx, int dimy ) {
int ix = blockIdx.x*blockDim.x + threadIdx.x;
int iy = blockIdx.y*blockDim.y + threadIdx.y;
int idx = iy*dimx + ix;
a[idx] = a[idx]+1;
}
int main() {
int dimx = 16, dimy = 16;
int num_bytes = dimx*dimy*sizeof(int);
int *d_a=0, *h_a=0; // device and host pointers h_a = (int*)malloc(num_bytes);
cudaMalloc( (void**)&d_a, num_bytes );
if( 0==h_a || 0==d_a ) {
printf("couldn't allocate memory\n"); return 1;
}
cudaMemset( d_a, 0, num_bytes );
dim3 grid, block;
block.x = 4; block.y = 4;
grid.x = dimx / block.x;
grid.y = dimy / block.y;
kernel<<<grid, block>>>( d_a, dimx, dimy );
cudaMemcpy(h_a, d_a, num_bytes, cudaMemcpyDeviceToHost );
free( h_a ); cudaFree( d_a );
return 0;
} | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <stdio.h>
__global__ void kernel( int *a, int dimx, int dimy ) {
int ix = blockIdx.x*blockDim.x + threadIdx.x;
int iy = blockIdx.y*blockDim.y + threadIdx.y;
int idx = iy*dimx + ix;
a[idx] = a[idx]+1;
}
int main() {
int dimx = 16, dimy = 16;
int num_bytes = dimx*dimy*sizeof(int);
int *d_a=0, *h_a=0; // device and host pointers h_a = (int*)malloc(num_bytes);
hipMalloc( (void**)&d_a, num_bytes );
if( 0==h_a || 0==d_a ) {
printf("couldn't allocate memory\n"); return 1;
}
hipMemset( d_a, 0, num_bytes );
dim3 grid, block;
block.x = 4; block.y = 4;
grid.x = dimx / block.x;
grid.y = dimy / block.y;
kernel<<<grid, block>>>( d_a, dimx, dimy );
hipMemcpy(h_a, d_a, num_bytes, hipMemcpyDeviceToHost );
free( h_a ); hipFree( d_a );
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <stdio.h>
__global__ void kernel( int *a, int dimx, int dimy ) {
int ix = blockIdx.x*blockDim.x + threadIdx.x;
int iy = blockIdx.y*blockDim.y + threadIdx.y;
int idx = iy*dimx + ix;
a[idx] = a[idx]+1;
}
int main() {
int dimx = 16, dimy = 16;
int num_bytes = dimx*dimy*sizeof(int);
int *d_a=0, *h_a=0; // device and host pointers h_a = (int*)malloc(num_bytes);
hipMalloc( (void**)&d_a, num_bytes );
if( 0==h_a || 0==d_a ) {
printf("couldn't allocate memory\n"); return 1;
}
hipMemset( d_a, 0, num_bytes );
dim3 grid, block;
block.x = 4; block.y = 4;
grid.x = dimx / block.x;
grid.y = dimy / block.y;
kernel<<<grid, block>>>( d_a, dimx, dimy );
hipMemcpy(h_a, d_a, num_bytes, hipMemcpyDeviceToHost );
free( h_a ); hipFree( d_a );
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPiii
.globl _Z6kernelPiii
.p2align 8
.type _Z6kernelPiii,@function
_Z6kernelPiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_mul_i32 s14, s14, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v2, s3
v_add3_u32 v0, s14, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, 1, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPiii, .Lfunc_end0-_Z6kernelPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <stdio.h>
__global__ void kernel( int *a, int dimx, int dimy ) {
int ix = blockIdx.x*blockDim.x + threadIdx.x;
int iy = blockIdx.y*blockDim.y + threadIdx.y;
int idx = iy*dimx + ix;
a[idx] = a[idx]+1;
}
int main() {
int dimx = 16, dimy = 16;
int num_bytes = dimx*dimy*sizeof(int);
int *d_a=0, *h_a=0; // device and host pointers h_a = (int*)malloc(num_bytes);
hipMalloc( (void**)&d_a, num_bytes );
if( 0==h_a || 0==d_a ) {
printf("couldn't allocate memory\n"); return 1;
}
hipMemset( d_a, 0, num_bytes );
dim3 grid, block;
block.x = 4; block.y = 4;
grid.x = dimx / block.x;
grid.y = dimy / block.y;
kernel<<<grid, block>>>( d_a, dimx, dimy );
hipMemcpy(h_a, d_a, num_bytes, hipMemcpyDeviceToHost );
free( h_a ); hipFree( d_a );
return 0;
} | .text
.file "example.hip"
.globl _Z21__device_stub__kernelPiii # -- Begin function _Z21__device_stub__kernelPiii
.p2align 4, 0x90
.type _Z21__device_stub__kernelPiii,@function
_Z21__device_stub__kernelPiii: # @_Z21__device_stub__kernelPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPiii, .Lfunc_end0-_Z21__device_stub__kernelPiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq $0, (%rsp)
movq %rsp, %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movl $.Lstr, %edi
callq puts@PLT
movl $1, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPiii,@object # @_Z6kernelPiii
.section .rodata,"a",@progbits
.globl _Z6kernelPiii
.p2align 3, 0x0
_Z6kernelPiii:
.quad _Z21__device_stub__kernelPiii
.size _Z6kernelPiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelPiii"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "couldn't allocate memory"
.size .Lstr, 25
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0040*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fe200078e0205 */
/*0080*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fc600000001ff */
/*0090*/ IMAD R3, R3, c[0x0][0x168], R0 ; /* 0x00005a0003037a24 */
/* 0x000fce00078e0200 */
/*00a0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*00b0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ IADD3 R5, R0, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x004fca0007ffe0ff */
/*00d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPiii
.globl _Z6kernelPiii
.p2align 8
.type _Z6kernelPiii,@function
_Z6kernelPiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_mul_i32 s14, s14, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v2, s3
v_add3_u32 v0, s14, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, 1, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPiii, .Lfunc_end0-_Z6kernelPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b5f56_00000000-6_example.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "couldn't allocate memory\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq %rsp, %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $1, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z27__device_stub__Z6kernelPiiiPiii
.type _Z27__device_stub__Z6kernelPiiiPiii, @function
_Z27__device_stub__Z6kernelPiiiPiii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z6kernelPiiiPiii, .-_Z27__device_stub__Z6kernelPiiiPiii
.globl _Z6kernelPiii
.type _Z6kernelPiii, @function
_Z6kernelPiii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6kernelPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelPiii, .-_Z6kernelPiii
.section .rodata.str1.1
.LC1:
.string "_Z6kernelPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "example.hip"
.globl _Z21__device_stub__kernelPiii # -- Begin function _Z21__device_stub__kernelPiii
.p2align 4, 0x90
.type _Z21__device_stub__kernelPiii,@function
_Z21__device_stub__kernelPiii: # @_Z21__device_stub__kernelPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPiii, .Lfunc_end0-_Z21__device_stub__kernelPiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq $0, (%rsp)
movq %rsp, %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movl $.Lstr, %edi
callq puts@PLT
movl $1, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPiii,@object # @_Z6kernelPiii
.section .rodata,"a",@progbits
.globl _Z6kernelPiii
.p2align 3, 0x0
_Z6kernelPiii:
.quad _Z21__device_stub__kernelPiii
.size _Z6kernelPiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelPiii"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "couldn't allocate memory"
.size .Lstr, 25
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C"
__global__ void setDomainPoolKernel(
int nBatch, int rbs, int nDegree, int nD, int dScale, int rScale,
int expansion, int isCenAlign, float regularize,
float *data,float *dataRev, // array of data and reverse data
// arrays pointer
float *DA,
float *AA,
float *IA,
// pointer of array of pointer to pointer of array in arrays, nevermind i just stun you.
// p(i) = data(i + size(data))
float **DP,
float **AP,
float **IP
)
{
int taskIdx = blockIdx.x * blockDim.x + threadIdx.x;
if (taskIdx < nBatch){
// initialize domain arrays
// array structure
// DA = rbs-rows , 1 + D_1^1 + D_2^1 + D_3^1 + ... + D_ds^2
// nCoeff is power of Domains. start from power 0
// nDegree determine the number of degree (maximum degree + 1)
// nD determine the number of domain blocks
// dScale determing the scale of domain size compare to rbs
// dpOffset determine the number of bytes padded for each Array
int nCoeff = ((nDegree - 1) * nD + 1);
// pointing array of pointers to array
const int daOffset = taskIdx * rbs * rScale * nCoeff;
const int aaOffset = taskIdx * nCoeff * nCoeff;
const int iaOffset = taskIdx * nCoeff * nCoeff;
DP[taskIdx] = &DA[daOffset];
AP[taskIdx] = &AA[aaOffset];
IP[taskIdx] = &IA[iaOffset];
// initialize covariance matrix with regularization
for(int i = 0; i < nCoeff * nCoeff; i++){
AA[aaOffset + i] = 0.0f;
}
for(int i = 0; i < nCoeff * nCoeff; i+= nCoeff+1){
// set diagonal to regularization parameter
AA[aaOffset + i] = regularize * regularize;
}
// initialize first column covariance matrix
for(int i = 0; i < rbs * rScale; i++){
DA[daOffset + i] = 1.0f; // power 0
}
int dIdx = taskIdx % (nBatch/2);
// for each block number dn
for(int dn = 1; dn <= nD; dn++){
// set reference domain block
// compute sumScale
int sumScale = 0;
for(int k = 1; k <= nD && k < dn; k++){
sumScale += (int) powf( (float) dScale, (float) (1 + expansion * (k - 1))) ;
}
int dnScale = (int) powf( (float) dScale, (float) (1 + expansion * (dn - 1)));
//int dnIdx = dIdx + rbs * sumScale; // * domian location factor
int dnIdx = dIdx;
if( isCenAlign == 0 ){
// if left aligned
dnIdx = dIdx + rbs * sumScale + 1;
} else {
// if center aligned
dnIdx = dIdx + rbs/2 * (1 - dnScale) + 1;
}
int padDA = rbs * rScale * dn; // number of row of DA
// initialize column dn-th index
for(int i = 0; i < rbs * rScale; i++){
DA[daOffset + padDA + i] = 0.0f; // power 1
}
// construct DA from domain blocks at power 1
// copy elements
for(int i = 0; i < rbs * rScale; i++){
int datIdx = dnIdx + i*dnScale/rScale;
if(datIdx >=0 && datIdx < (nBatch/2)){
if(taskIdx < (nBatch/2)){
DA[daOffset + padDA + i] =
DA[daOffset + padDA + i] + data[datIdx];
}else{ // gen reverse domain
DA[daOffset + padDA + i] =
DA[daOffset + padDA + i] + dataRev[datIdx];
}
}
}
// // handling if domain blocks are larger than rbs (by downsample)
for(int ds = 1; ds < dnScale / rScale; ds++){
// vec sumation
for(int i = 0; i < rbs * rScale; i++){
int datIdx = dnIdx + ds + i*dnScale/rScale;
if(datIdx >=0 && datIdx < (nBatch/2)){
if(taskIdx < (nBatch/2)){
DA[daOffset + padDA + i] =
DA[daOffset + padDA + i] + data[datIdx];
}else{ // gen reverse domain
DA[daOffset + padDA + i] =
DA[daOffset + padDA + i] + dataRev[datIdx];
}
}
}
}
// vec scalig after resample
for(int i = 0; i < rbs * rScale; i++){
DA[daOffset + padDA + i] = DA[daOffset + padDA + i] / (dnScale/rScale);
}
// calculate next degree
for(int deg = 2; deg <= nDegree - 1; deg++){
int degPad = rbs * nD * (deg - 2) + rbs * dn;
int nextDegPad = rbs * nD * (deg - 1) + rbs * dn;
for(int i = 0; i < rbs * rScale; i++){
// power n>=2
// D^n = D^1 * D^(n-1)
DA[daOffset + nextDegPad + i] =
DA[daOffset + rbs*dn + i] * DA[daOffset + degPad + i] ;
}
}
}
}
} | .file "tmpxft_000c1457_00000000-6_setDomainPoolKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z65__device_stub__Z19setDomainPoolKerneliiiiiiiifPfS_S_S_S_PS_S0_S0_iiiiiiiifPfS_S_S_S_PS_S0_S0_
.type _Z65__device_stub__Z19setDomainPoolKerneliiiiiiiifPfS_S_S_S_PS_S0_S0_iiiiiiiifPfS_S_S_S_PS_S0_S0_, @function
_Z65__device_stub__Z19setDomainPoolKerneliiiiiiiifPfS_S_S_S_PS_S0_S0_iiiiiiiifPfS_S_S_S_PS_S0_S0_:
.LFB2051:
.cfi_startproc
endbr64
subq $312, %rsp
.cfi_def_cfa_offset 320
movl %edi, 92(%rsp)
movl %esi, 88(%rsp)
movl %edx, 84(%rsp)
movl %ecx, 80(%rsp)
movl %r8d, 76(%rsp)
movl %r9d, 72(%rsp)
movss %xmm0, 68(%rsp)
movq 336(%rsp), %rax
movq %rax, 56(%rsp)
movq 344(%rsp), %rax
movq %rax, 48(%rsp)
movq 352(%rsp), %rax
movq %rax, 40(%rsp)
movq 360(%rsp), %rax
movq %rax, 32(%rsp)
movq 368(%rsp), %rax
movq %rax, 24(%rsp)
movq 376(%rsp), %rax
movq %rax, 16(%rsp)
movq 384(%rsp), %rax
movq %rax, 8(%rsp)
movq 392(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 296(%rsp)
xorl %eax, %eax
leaq 92(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rax
movq %rax, 168(%rsp)
leaq 84(%rsp), %rax
movq %rax, 176(%rsp)
leaq 80(%rsp), %rax
movq %rax, 184(%rsp)
leaq 76(%rsp), %rax
movq %rax, 192(%rsp)
leaq 72(%rsp), %rax
movq %rax, 200(%rsp)
leaq 320(%rsp), %rax
movq %rax, 208(%rsp)
leaq 328(%rsp), %rax
movq %rax, 216(%rsp)
leaq 68(%rsp), %rax
movq %rax, 224(%rsp)
leaq 56(%rsp), %rax
movq %rax, 232(%rsp)
leaq 48(%rsp), %rax
movq %rax, 240(%rsp)
leaq 40(%rsp), %rax
movq %rax, 248(%rsp)
leaq 32(%rsp), %rax
movq %rax, 256(%rsp)
leaq 24(%rsp), %rax
movq %rax, 264(%rsp)
leaq 16(%rsp), %rax
movq %rax, 272(%rsp)
leaq 8(%rsp), %rax
movq %rax, 280(%rsp)
movq %rsp, %rax
movq %rax, 288(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
leaq 104(%rsp), %rcx
leaq 96(%rsp), %rdx
leaq 124(%rsp), %rsi
leaq 112(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 296(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $312, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 328
pushq 104(%rsp)
.cfi_def_cfa_offset 336
leaq 176(%rsp), %r9
movq 140(%rsp), %rcx
movl 148(%rsp), %r8d
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
leaq setDomainPoolKernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 320
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z65__device_stub__Z19setDomainPoolKerneliiiiiiiifPfS_S_S_S_PS_S0_S0_iiiiiiiifPfS_S_S_S_PS_S0_S0_, .-_Z65__device_stub__Z19setDomainPoolKerneliiiiiiiifPfS_S_S_S_PS_S0_S0_iiiiiiiifPfS_S_S_S_PS_S0_S0_
.globl setDomainPoolKernel
.type setDomainPoolKernel, @function
setDomainPoolKernel:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 88(%rsp)
.cfi_def_cfa_offset 24
pushq 88(%rsp)
.cfi_def_cfa_offset 32
pushq 88(%rsp)
.cfi_def_cfa_offset 40
pushq 88(%rsp)
.cfi_def_cfa_offset 48
pushq 88(%rsp)
.cfi_def_cfa_offset 56
pushq 88(%rsp)
.cfi_def_cfa_offset 64
pushq 88(%rsp)
.cfi_def_cfa_offset 72
pushq 88(%rsp)
.cfi_def_cfa_offset 80
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 88
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 96
call _Z65__device_stub__Z19setDomainPoolKerneliiiiiiiifPfS_S_S_S_PS_S0_S0_iiiiiiiifPfS_S_S_S_PS_S0_S0_
addq $88, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size setDomainPoolKernel, .-setDomainPoolKernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "setDomainPoolKernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq setDomainPoolKernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C"
__global__ void setDomainPoolKernel(
int nBatch, int rbs, int nDegree, int nD, int dScale, int rScale,
int expansion, int isCenAlign, float regularize,
float *data,float *dataRev, // array of data and reverse data
// arrays pointer
float *DA,
float *AA,
float *IA,
// pointer of array of pointer to pointer of array in arrays, nevermind i just stun you.
// p(i) = data(i + size(data))
float **DP,
float **AP,
float **IP
)
{
int taskIdx = blockIdx.x * blockDim.x + threadIdx.x;
if (taskIdx < nBatch){
// initialize domain arrays
// array structure
// DA = rbs-rows , 1 + D_1^1 + D_2^1 + D_3^1 + ... + D_ds^2
// nCoeff is power of Domains. start from power 0
// nDegree determine the number of degree (maximum degree + 1)
// nD determine the number of domain blocks
// dScale determing the scale of domain size compare to rbs
// dpOffset determine the number of bytes padded for each Array
int nCoeff = ((nDegree - 1) * nD + 1);
// pointing array of pointers to array
const int daOffset = taskIdx * rbs * rScale * nCoeff;
const int aaOffset = taskIdx * nCoeff * nCoeff;
const int iaOffset = taskIdx * nCoeff * nCoeff;
DP[taskIdx] = &DA[daOffset];
AP[taskIdx] = &AA[aaOffset];
IP[taskIdx] = &IA[iaOffset];
// initialize covariance matrix with regularization
for(int i = 0; i < nCoeff * nCoeff; i++){
AA[aaOffset + i] = 0.0f;
}
for(int i = 0; i < nCoeff * nCoeff; i+= nCoeff+1){
// set diagonal to regularization parameter
AA[aaOffset + i] = regularize * regularize;
}
// initialize first column covariance matrix
for(int i = 0; i < rbs * rScale; i++){
DA[daOffset + i] = 1.0f; // power 0
}
int dIdx = taskIdx % (nBatch/2);
// for each block number dn
for(int dn = 1; dn <= nD; dn++){
// set reference domain block
// compute sumScale
int sumScale = 0;
for(int k = 1; k <= nD && k < dn; k++){
sumScale += (int) powf( (float) dScale, (float) (1 + expansion * (k - 1))) ;
}
int dnScale = (int) powf( (float) dScale, (float) (1 + expansion * (dn - 1)));
//int dnIdx = dIdx + rbs * sumScale; // * domian location factor
int dnIdx = dIdx;
if( isCenAlign == 0 ){
// if left aligned
dnIdx = dIdx + rbs * sumScale + 1;
} else {
// if center aligned
dnIdx = dIdx + rbs/2 * (1 - dnScale) + 1;
}
int padDA = rbs * rScale * dn; // number of row of DA
// initialize column dn-th index
for(int i = 0; i < rbs * rScale; i++){
DA[daOffset + padDA + i] = 0.0f; // power 1
}
// construct DA from domain blocks at power 1
// copy elements
for(int i = 0; i < rbs * rScale; i++){
int datIdx = dnIdx + i*dnScale/rScale;
if(datIdx >=0 && datIdx < (nBatch/2)){
if(taskIdx < (nBatch/2)){
DA[daOffset + padDA + i] =
DA[daOffset + padDA + i] + data[datIdx];
}else{ // gen reverse domain
DA[daOffset + padDA + i] =
DA[daOffset + padDA + i] + dataRev[datIdx];
}
}
}
// // handling if domain blocks are larger than rbs (by downsample)
for(int ds = 1; ds < dnScale / rScale; ds++){
// vec sumation
for(int i = 0; i < rbs * rScale; i++){
int datIdx = dnIdx + ds + i*dnScale/rScale;
if(datIdx >=0 && datIdx < (nBatch/2)){
if(taskIdx < (nBatch/2)){
DA[daOffset + padDA + i] =
DA[daOffset + padDA + i] + data[datIdx];
}else{ // gen reverse domain
DA[daOffset + padDA + i] =
DA[daOffset + padDA + i] + dataRev[datIdx];
}
}
}
}
// vec scalig after resample
for(int i = 0; i < rbs * rScale; i++){
DA[daOffset + padDA + i] = DA[daOffset + padDA + i] / (dnScale/rScale);
}
// calculate next degree
for(int deg = 2; deg <= nDegree - 1; deg++){
int degPad = rbs * nD * (deg - 2) + rbs * dn;
int nextDegPad = rbs * nD * (deg - 1) + rbs * dn;
for(int i = 0; i < rbs * rScale; i++){
// power n>=2
// D^n = D^1 * D^(n-1)
DA[daOffset + nextDegPad + i] =
DA[daOffset + rbs*dn + i] * DA[daOffset + degPad + i] ;
}
}
}
}
} | #include <hip/hip_runtime.h>
extern "C"
__global__ void setDomainPoolKernel(
int nBatch, int rbs, int nDegree, int nD, int dScale, int rScale,
int expansion, int isCenAlign, float regularize,
float *data,float *dataRev, // array of data and reverse data
// arrays pointer
float *DA,
float *AA,
float *IA,
// pointer of array of pointer to pointer of array in arrays, nevermind i just stun you.
// p(i) = data(i + size(data))
float **DP,
float **AP,
float **IP
)
{
int taskIdx = blockIdx.x * blockDim.x + threadIdx.x;
if (taskIdx < nBatch){
// initialize domain arrays
// array structure
// DA = rbs-rows , 1 + D_1^1 + D_2^1 + D_3^1 + ... + D_ds^2
// nCoeff is power of Domains. start from power 0
// nDegree determine the number of degree (maximum degree + 1)
// nD determine the number of domain blocks
// dScale determing the scale of domain size compare to rbs
// dpOffset determine the number of bytes padded for each Array
int nCoeff = ((nDegree - 1) * nD + 1);
// pointing array of pointers to array
const int daOffset = taskIdx * rbs * rScale * nCoeff;
const int aaOffset = taskIdx * nCoeff * nCoeff;
const int iaOffset = taskIdx * nCoeff * nCoeff;
DP[taskIdx] = &DA[daOffset];
AP[taskIdx] = &AA[aaOffset];
IP[taskIdx] = &IA[iaOffset];
// initialize covariance matrix with regularization
for(int i = 0; i < nCoeff * nCoeff; i++){
AA[aaOffset + i] = 0.0f;
}
for(int i = 0; i < nCoeff * nCoeff; i+= nCoeff+1){
// set diagonal to regularization parameter
AA[aaOffset + i] = regularize * regularize;
}
// initialize first column covariance matrix
for(int i = 0; i < rbs * rScale; i++){
DA[daOffset + i] = 1.0f; // power 0
}
int dIdx = taskIdx % (nBatch/2);
// for each block number dn
for(int dn = 1; dn <= nD; dn++){
// set reference domain block
// compute sumScale
int sumScale = 0;
for(int k = 1; k <= nD && k < dn; k++){
sumScale += (int) powf( (float) dScale, (float) (1 + expansion * (k - 1))) ;
}
int dnScale = (int) powf( (float) dScale, (float) (1 + expansion * (dn - 1)));
//int dnIdx = dIdx + rbs * sumScale; // * domian location factor
int dnIdx = dIdx;
if( isCenAlign == 0 ){
// if left aligned
dnIdx = dIdx + rbs * sumScale + 1;
} else {
// if center aligned
dnIdx = dIdx + rbs/2 * (1 - dnScale) + 1;
}
int padDA = rbs * rScale * dn; // number of row of DA
// initialize column dn-th index
for(int i = 0; i < rbs * rScale; i++){
DA[daOffset + padDA + i] = 0.0f; // power 1
}
// construct DA from domain blocks at power 1
// copy elements
for(int i = 0; i < rbs * rScale; i++){
int datIdx = dnIdx + i*dnScale/rScale;
if(datIdx >=0 && datIdx < (nBatch/2)){
if(taskIdx < (nBatch/2)){
DA[daOffset + padDA + i] =
DA[daOffset + padDA + i] + data[datIdx];
}else{ // gen reverse domain
DA[daOffset + padDA + i] =
DA[daOffset + padDA + i] + dataRev[datIdx];
}
}
}
// // handling if domain blocks are larger than rbs (by downsample)
for(int ds = 1; ds < dnScale / rScale; ds++){
// vec sumation
for(int i = 0; i < rbs * rScale; i++){
int datIdx = dnIdx + ds + i*dnScale/rScale;
if(datIdx >=0 && datIdx < (nBatch/2)){
if(taskIdx < (nBatch/2)){
DA[daOffset + padDA + i] =
DA[daOffset + padDA + i] + data[datIdx];
}else{ // gen reverse domain
DA[daOffset + padDA + i] =
DA[daOffset + padDA + i] + dataRev[datIdx];
}
}
}
}
// vec scalig after resample
for(int i = 0; i < rbs * rScale; i++){
DA[daOffset + padDA + i] = DA[daOffset + padDA + i] / (dnScale/rScale);
}
// calculate next degree
for(int deg = 2; deg <= nDegree - 1; deg++){
int degPad = rbs * nD * (deg - 2) + rbs * dn;
int nextDegPad = rbs * nD * (deg - 1) + rbs * dn;
for(int i = 0; i < rbs * rScale; i++){
// power n>=2
// D^n = D^1 * D^(n-1)
DA[daOffset + nextDegPad + i] =
DA[daOffset + rbs*dn + i] * DA[daOffset + degPad + i] ;
}
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__ void setDomainPoolKernel(
int nBatch, int rbs, int nDegree, int nD, int dScale, int rScale,
int expansion, int isCenAlign, float regularize,
float *data,float *dataRev, // array of data and reverse data
// arrays pointer
float *DA,
float *AA,
float *IA,
// pointer of array of pointer to pointer of array in arrays, nevermind i just stun you.
// p(i) = data(i + size(data))
float **DP,
float **AP,
float **IP
)
{
int taskIdx = blockIdx.x * blockDim.x + threadIdx.x;
if (taskIdx < nBatch){
// initialize domain arrays
// array structure
// DA = rbs-rows , 1 + D_1^1 + D_2^1 + D_3^1 + ... + D_ds^2
// nCoeff is power of Domains. start from power 0
// nDegree determine the number of degree (maximum degree + 1)
// nD determine the number of domain blocks
// dScale determing the scale of domain size compare to rbs
// dpOffset determine the number of bytes padded for each Array
int nCoeff = ((nDegree - 1) * nD + 1);
// pointing array of pointers to array
const int daOffset = taskIdx * rbs * rScale * nCoeff;
const int aaOffset = taskIdx * nCoeff * nCoeff;
const int iaOffset = taskIdx * nCoeff * nCoeff;
DP[taskIdx] = &DA[daOffset];
AP[taskIdx] = &AA[aaOffset];
IP[taskIdx] = &IA[iaOffset];
// initialize covariance matrix with regularization
for(int i = 0; i < nCoeff * nCoeff; i++){
AA[aaOffset + i] = 0.0f;
}
for(int i = 0; i < nCoeff * nCoeff; i+= nCoeff+1){
// set diagonal to regularization parameter
AA[aaOffset + i] = regularize * regularize;
}
// initialize first column covariance matrix
for(int i = 0; i < rbs * rScale; i++){
DA[daOffset + i] = 1.0f; // power 0
}
int dIdx = taskIdx % (nBatch/2);
// for each block number dn
for(int dn = 1; dn <= nD; dn++){
// set reference domain block
// compute sumScale
int sumScale = 0;
for(int k = 1; k <= nD && k < dn; k++){
sumScale += (int) powf( (float) dScale, (float) (1 + expansion * (k - 1))) ;
}
int dnScale = (int) powf( (float) dScale, (float) (1 + expansion * (dn - 1)));
//int dnIdx = dIdx + rbs * sumScale; // * domian location factor
int dnIdx = dIdx;
if( isCenAlign == 0 ){
// if left aligned
dnIdx = dIdx + rbs * sumScale + 1;
} else {
// if center aligned
dnIdx = dIdx + rbs/2 * (1 - dnScale) + 1;
}
int padDA = rbs * rScale * dn; // number of row of DA
// initialize column dn-th index
for(int i = 0; i < rbs * rScale; i++){
DA[daOffset + padDA + i] = 0.0f; // power 1
}
// construct DA from domain blocks at power 1
// copy elements
for(int i = 0; i < rbs * rScale; i++){
int datIdx = dnIdx + i*dnScale/rScale;
if(datIdx >=0 && datIdx < (nBatch/2)){
if(taskIdx < (nBatch/2)){
DA[daOffset + padDA + i] =
DA[daOffset + padDA + i] + data[datIdx];
}else{ // gen reverse domain
DA[daOffset + padDA + i] =
DA[daOffset + padDA + i] + dataRev[datIdx];
}
}
}
// // handling if domain blocks are larger than rbs (by downsample)
for(int ds = 1; ds < dnScale / rScale; ds++){
// vec sumation
for(int i = 0; i < rbs * rScale; i++){
int datIdx = dnIdx + ds + i*dnScale/rScale;
if(datIdx >=0 && datIdx < (nBatch/2)){
if(taskIdx < (nBatch/2)){
DA[daOffset + padDA + i] =
DA[daOffset + padDA + i] + data[datIdx];
}else{ // gen reverse domain
DA[daOffset + padDA + i] =
DA[daOffset + padDA + i] + dataRev[datIdx];
}
}
}
}
// vec scalig after resample
for(int i = 0; i < rbs * rScale; i++){
DA[daOffset + padDA + i] = DA[daOffset + padDA + i] / (dnScale/rScale);
}
// calculate next degree
for(int deg = 2; deg <= nDegree - 1; deg++){
int degPad = rbs * nD * (deg - 2) + rbs * dn;
int nextDegPad = rbs * nD * (deg - 1) + rbs * dn;
for(int i = 0; i < rbs * rScale; i++){
// power n>=2
// D^n = D^1 * D^(n-1)
DA[daOffset + nextDegPad + i] =
DA[daOffset + rbs*dn + i] * DA[daOffset + degPad + i] ;
}
}
}
}
} | .text
.file "setDomainPoolKernel.hip"
.globl __device_stub__setDomainPoolKernel # -- Begin function __device_stub__setDomainPoolKernel
.p2align 4, 0x90
.type __device_stub__setDomainPoolKernel,@function
__device_stub__setDomainPoolKernel: # @__device_stub__setDomainPoolKernel
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movss %xmm0, 4(%rsp)
leaq 28(%rsp), %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rax
movq %rax, 88(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 224(%rsp), %rax
movq %rax, 128(%rsp)
leaq 232(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 240(%rsp), %rax
movq %rax, 152(%rsp)
leaq 248(%rsp), %rax
movq %rax, 160(%rsp)
leaq 256(%rsp), %rax
movq %rax, 168(%rsp)
leaq 264(%rsp), %rax
movq %rax, 176(%rsp)
leaq 272(%rsp), %rax
movq %rax, 184(%rsp)
leaq 280(%rsp), %rax
movq %rax, 192(%rsp)
leaq 288(%rsp), %rax
movq %rax, 200(%rsp)
leaq 296(%rsp), %rax
movq %rax, 208(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 80(%rsp), %r9
movl $setDomainPoolKernel, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size __device_stub__setDomainPoolKernel, .Lfunc_end0-__device_stub__setDomainPoolKernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $setDomainPoolKernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type setDomainPoolKernel,@object # @setDomainPoolKernel
.section .rodata,"a",@progbits
.globl setDomainPoolKernel
.p2align 3, 0x0
setDomainPoolKernel:
.quad __device_stub__setDomainPoolKernel
.size setDomainPoolKernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "setDomainPoolKernel"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__setDomainPoolKernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym setDomainPoolKernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c1457_00000000-6_setDomainPoolKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z65__device_stub__Z19setDomainPoolKerneliiiiiiiifPfS_S_S_S_PS_S0_S0_iiiiiiiifPfS_S_S_S_PS_S0_S0_
.type _Z65__device_stub__Z19setDomainPoolKerneliiiiiiiifPfS_S_S_S_PS_S0_S0_iiiiiiiifPfS_S_S_S_PS_S0_S0_, @function
_Z65__device_stub__Z19setDomainPoolKerneliiiiiiiifPfS_S_S_S_PS_S0_S0_iiiiiiiifPfS_S_S_S_PS_S0_S0_:
.LFB2051:
.cfi_startproc
endbr64
subq $312, %rsp
.cfi_def_cfa_offset 320
movl %edi, 92(%rsp)
movl %esi, 88(%rsp)
movl %edx, 84(%rsp)
movl %ecx, 80(%rsp)
movl %r8d, 76(%rsp)
movl %r9d, 72(%rsp)
movss %xmm0, 68(%rsp)
movq 336(%rsp), %rax
movq %rax, 56(%rsp)
movq 344(%rsp), %rax
movq %rax, 48(%rsp)
movq 352(%rsp), %rax
movq %rax, 40(%rsp)
movq 360(%rsp), %rax
movq %rax, 32(%rsp)
movq 368(%rsp), %rax
movq %rax, 24(%rsp)
movq 376(%rsp), %rax
movq %rax, 16(%rsp)
movq 384(%rsp), %rax
movq %rax, 8(%rsp)
movq 392(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 296(%rsp)
xorl %eax, %eax
leaq 92(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rax
movq %rax, 168(%rsp)
leaq 84(%rsp), %rax
movq %rax, 176(%rsp)
leaq 80(%rsp), %rax
movq %rax, 184(%rsp)
leaq 76(%rsp), %rax
movq %rax, 192(%rsp)
leaq 72(%rsp), %rax
movq %rax, 200(%rsp)
leaq 320(%rsp), %rax
movq %rax, 208(%rsp)
leaq 328(%rsp), %rax
movq %rax, 216(%rsp)
leaq 68(%rsp), %rax
movq %rax, 224(%rsp)
leaq 56(%rsp), %rax
movq %rax, 232(%rsp)
leaq 48(%rsp), %rax
movq %rax, 240(%rsp)
leaq 40(%rsp), %rax
movq %rax, 248(%rsp)
leaq 32(%rsp), %rax
movq %rax, 256(%rsp)
leaq 24(%rsp), %rax
movq %rax, 264(%rsp)
leaq 16(%rsp), %rax
movq %rax, 272(%rsp)
leaq 8(%rsp), %rax
movq %rax, 280(%rsp)
movq %rsp, %rax
movq %rax, 288(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
leaq 104(%rsp), %rcx
leaq 96(%rsp), %rdx
leaq 124(%rsp), %rsi
leaq 112(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 296(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $312, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 328
pushq 104(%rsp)
.cfi_def_cfa_offset 336
leaq 176(%rsp), %r9
movq 140(%rsp), %rcx
movl 148(%rsp), %r8d
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
leaq setDomainPoolKernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 320
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z65__device_stub__Z19setDomainPoolKerneliiiiiiiifPfS_S_S_S_PS_S0_S0_iiiiiiiifPfS_S_S_S_PS_S0_S0_, .-_Z65__device_stub__Z19setDomainPoolKerneliiiiiiiifPfS_S_S_S_PS_S0_S0_iiiiiiiifPfS_S_S_S_PS_S0_S0_
.globl setDomainPoolKernel
.type setDomainPoolKernel, @function
setDomainPoolKernel:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 88(%rsp)
.cfi_def_cfa_offset 24
pushq 88(%rsp)
.cfi_def_cfa_offset 32
pushq 88(%rsp)
.cfi_def_cfa_offset 40
pushq 88(%rsp)
.cfi_def_cfa_offset 48
pushq 88(%rsp)
.cfi_def_cfa_offset 56
pushq 88(%rsp)
.cfi_def_cfa_offset 64
pushq 88(%rsp)
.cfi_def_cfa_offset 72
pushq 88(%rsp)
.cfi_def_cfa_offset 80
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 88
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 96
call _Z65__device_stub__Z19setDomainPoolKerneliiiiiiiifPfS_S_S_S_PS_S0_S0_iiiiiiiifPfS_S_S_S_PS_S0_S0_
addq $88, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size setDomainPoolKernel, .-setDomainPoolKernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "setDomainPoolKernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq setDomainPoolKernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "setDomainPoolKernel.hip"
.globl __device_stub__setDomainPoolKernel # -- Begin function __device_stub__setDomainPoolKernel
.p2align 4, 0x90
.type __device_stub__setDomainPoolKernel,@function
__device_stub__setDomainPoolKernel: # @__device_stub__setDomainPoolKernel
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movss %xmm0, 4(%rsp)
leaq 28(%rsp), %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rax
movq %rax, 88(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 224(%rsp), %rax
movq %rax, 128(%rsp)
leaq 232(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 240(%rsp), %rax
movq %rax, 152(%rsp)
leaq 248(%rsp), %rax
movq %rax, 160(%rsp)
leaq 256(%rsp), %rax
movq %rax, 168(%rsp)
leaq 264(%rsp), %rax
movq %rax, 176(%rsp)
leaq 272(%rsp), %rax
movq %rax, 184(%rsp)
leaq 280(%rsp), %rax
movq %rax, 192(%rsp)
leaq 288(%rsp), %rax
movq %rax, 200(%rsp)
leaq 296(%rsp), %rax
movq %rax, 208(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 80(%rsp), %r9
movl $setDomainPoolKernel, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size __device_stub__setDomainPoolKernel, .Lfunc_end0-__device_stub__setDomainPoolKernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $setDomainPoolKernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type setDomainPoolKernel,@object # @setDomainPoolKernel
.section .rodata,"a",@progbits
.globl setDomainPoolKernel
.p2align 3, 0x0
setDomainPoolKernel:
.quad __device_stub__setDomainPoolKernel
.size setDomainPoolKernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "setDomainPoolKernel"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__setDomainPoolKernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym setDomainPoolKernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define REORDER 1
#define GOOD_WEATHER 0
#define BAD_WEATHER 1
#define TAG_Car 0
#define TAG_Pedestrian 1
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
//#include <random>
//#include <array>
#include <algorithm>
#define NUM_CARS 4096
#define NUM_PEDS 16384
#define NUM_STREETS 500
#define MAX_CONNECTIONS 10
#define MAX_LEN 25
using namespace std;
// Define this to turn on error checking
#define CUDA_ERROR_CHECK
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CudaCheckError() __cudaCheckError( __FILE__, __LINE__ )
inline void __cudaSafeCall( cudaError err, const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
cudaError err = cudaGetLastError();
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment away if needed.
err = cudaDeviceSynchronize();
if( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
__device__ float *d_Actor_progress;
__device__ int *d_Actor_street;
__device__ float *d_Car_max_velocity;
__device__ float *d_Street_length;
__device__ float *d_Street_max_velocity;
__device__ int *d_Street_neighbors;
__device__ int *d_Array_Street_size;
__device__ int *d_Array_Street_offset;
__device__ int *d_Array_Street_arrays;
__device__ int *d_input_actor_tag;
__device__ int *d_input_actor_id;
__device__ int *d_jobs;
__device__ int *d_randomn;
__device__ void method_Car_move(int actor_id, int weather)
{
float weather_multiplier;
if (weather == GOOD_WEATHER)
{
weather_multiplier = 1.0;
}
else if (weather == BAD_WEATHER)
{
weather_multiplier = 0.75;
}
float speed = min(d_Car_max_velocity[actor_id], d_Street_max_velocity[d_Actor_street[actor_id]]) * weather_multiplier;
d_Actor_progress[actor_id] = d_Actor_progress[actor_id] + (speed / 60.0); /* 1 tick = 1 minute */
if (d_Actor_progress[actor_id] >= d_Street_length[d_Actor_street[actor_id]])
{
// move to different street
int array_id = d_Street_neighbors[d_Actor_street[actor_id]];
int neighbor_index = d_randomn[d_Actor_street[actor_id]] % d_Array_Street_size[array_id];
d_Actor_street[actor_id] = d_Array_Street_arrays[d_Array_Street_offset[array_id] + neighbor_index];
d_Actor_progress[actor_id] = 0.0f;
}
}
__device__ void method_Pedestrian_move(int actor_id, int weather)
{
float speed = d_randomn[((int) (d_Actor_progress[actor_id]*d_Actor_progress[actor_id])) % NUM_STREETS] % 7 - 2;
d_Actor_progress[actor_id] = d_Actor_progress[actor_id] + (speed / 60.0);
if (d_Actor_progress[actor_id] >= d_Street_length[d_Actor_street[actor_id]])
{
// move to different street
int array_id = d_Street_neighbors[d_Actor_street[actor_id]];
int neighbor_index = d_randomn[d_Actor_street[actor_id]] % d_Array_Street_size[array_id];
d_Actor_street[actor_id] = d_Array_Street_arrays[d_Array_Street_offset[array_id] + neighbor_index];
d_Actor_progress[actor_id] = 0.0f;
}
}
__device__ void block(int actor_tag, int actor_id, int weather, int ticks)
{
for (int i = 0; i < ticks; i++)
{
switch (actor_tag)
{
case TAG_Car:
method_Car_move(actor_id, weather);
break;
case TAG_Pedestrian:
method_Pedestrian_move(actor_id, weather);
break;
}
}
}
__global__ void kernel(int weather, int ticks,
float *v_d_Actor_progress, int *v_d_Actor_street, float *v_d_Car_max_velocity,
float *v_d_Street_length, float *v_d_Street_max_velocity, int *v_d_Street_neighbors,
int *v_d_Array_Street_size, int *v_d_Array_Street_offset, int *v_d_Array_Street_arrays,
int *v_d_input_actor_tag, int *v_d_input_actor_id, int *v_d_jobs, int *v_d_randomn)
{
d_Actor_progress = v_d_Actor_progress;
d_Actor_street = v_d_Actor_street;
d_Car_max_velocity = v_d_Car_max_velocity;
d_Street_length = v_d_Street_length;
d_Street_max_velocity = v_d_Street_max_velocity;
d_Street_neighbors = v_d_Street_neighbors;
d_Array_Street_size = v_d_Array_Street_size;
d_Array_Street_offset = v_d_Array_Street_offset;
d_Array_Street_arrays = v_d_Array_Street_arrays;
d_input_actor_tag = v_d_input_actor_tag;
d_input_actor_id = v_d_input_actor_id;
d_jobs = v_d_jobs;
d_randomn = v_d_randomn;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
__syncthreads();
#if (REORDER)
block(d_input_actor_tag[d_jobs[tid]], d_input_actor_id[d_jobs[tid]], weather, ticks);
#else
block(d_input_actor_tag[tid], d_input_actor_id[tid], weather, ticks);
#endif
}
int main()
{
printf("Setting up scenario...\n");
srand(42);
// streets
float *Street_length = new float[NUM_STREETS];
float *Street_max_velocity = new float[NUM_STREETS];
int *Street_neighbors = new int[NUM_STREETS];
for (int i = 0; i < NUM_STREETS; i++)
{
Street_length[i] = rand() % MAX_LEN + 1;
Street_max_velocity[i] = rand() % 40 + 45; /* speed between 45 and 105 */
Street_neighbors[i] = i;
}
// neighbors
int *Array_Street_offset = new int[NUM_STREETS];
int *Array_Street_size = new int[NUM_STREETS];
int num_connections = 0;
for (int i = 0; i < NUM_STREETS; i++)
{
Array_Street_offset[i] = num_connections;
int connections = rand() % MAX_CONNECTIONS + 1;
Array_Street_size[i] = connections;
num_connections += connections;
}
int *Array_Street_arrays = new int[num_connections];
for (int i = 0; i < num_connections; i++)
{
Array_Street_arrays[i] = rand() % NUM_STREETS;
}
// actors
int *Actor_street = new int[NUM_PEDS + NUM_CARS];
float *Actor_progress = new float[NUM_PEDS + NUM_CARS];
float *Car_max_velocity = new float[NUM_CARS + NUM_PEDS];
int *Actor_tag = new int[NUM_PEDS + NUM_CARS];
int *Actor_id = new int[NUM_PEDS + NUM_CARS];
for (int i = 0; i < NUM_PEDS + NUM_CARS; i++)
{
Actor_street[i] = rand() % NUM_STREETS;
Actor_progress[i] = rand() % 10;
Car_max_velocity[i] = rand() % 20 + 65;
}
for (int i = 0; i < NUM_PEDS; i++)
{
Actor_tag[i] = TAG_Pedestrian;
Actor_id[i] = i;
}
for (int i = NUM_PEDS; i < NUM_PEDS + NUM_CARS; i++)
{
Actor_tag[i] = TAG_Car;
Actor_id[i] = i;
}
std::srand(42);
#if !(REORDER)
random_shuffle(Actor_tag, Actor_tag + NUM_CARS + NUM_PEDS);
#endif
// jobs (dummy)
int *jobs = new int[NUM_PEDS + NUM_CARS];
for (int i = 0; i < NUM_CARS + NUM_PEDS; i++)
{
jobs[i] = i;
}
// random numbers
int *randomn = new int[NUM_STREETS];
for (int i = 0; i < NUM_STREETS; i++)
{
randomn[i] = rand() % NUM_STREETS;
}
printf("Scenario set up.\n");
printf("Copying data to GPU...\n");
float *v_d_Actor_progress;
int *v_d_Actor_street;
float *v_d_Car_max_velocity;
float *v_d_Street_length;
float *v_d_Street_max_velocity;
int *v_d_Street_neighbors;
int *v_d_Array_Street_size;
int *v_d_Array_Street_offset;
int *v_d_Array_Street_arrays;
int *v_d_input_actor_tag;
int *v_d_input_actor_id;
int *v_d_jobs;
int *v_d_randomn;
CudaSafeCall(cudaMalloc((void**) &v_d_Actor_progress, sizeof(float) * (NUM_PEDS + NUM_CARS)));
CudaSafeCall(cudaMalloc((void**) &v_d_Actor_street, sizeof(int) * (NUM_PEDS + NUM_CARS)));
CudaSafeCall(cudaMalloc((void**) &v_d_Car_max_velocity, sizeof(float) * (NUM_PEDS + NUM_CARS)));
CudaSafeCall(cudaMalloc((void**) &v_d_Street_length, sizeof(float) * NUM_STREETS));
CudaSafeCall(cudaMalloc((void**) &v_d_Street_max_velocity, sizeof(float) * NUM_STREETS));
CudaSafeCall(cudaMalloc((void**) &v_d_Street_neighbors, sizeof(int) * NUM_STREETS));
CudaSafeCall(cudaMalloc((void**) &v_d_Array_Street_size, sizeof(int) * NUM_STREETS));
CudaSafeCall(cudaMalloc((void**) &v_d_Array_Street_offset, sizeof(int) * NUM_STREETS));
CudaSafeCall(cudaMalloc((void**) &v_d_Array_Street_arrays, sizeof(int) * num_connections));
CudaSafeCall(cudaMalloc((void**) &v_d_input_actor_tag, sizeof(int) * (NUM_PEDS + NUM_CARS)));
CudaSafeCall(cudaMalloc((void**) &v_d_input_actor_id, sizeof(int) * (NUM_PEDS + NUM_CARS)));
CudaSafeCall(cudaMalloc((void**) &v_d_jobs, sizeof(int) * (NUM_PEDS + NUM_CARS)));
CudaSafeCall(cudaMalloc((void**) &v_d_randomn, sizeof(int) * NUM_STREETS));
CudaSafeCall(cudaMemcpy(v_d_Actor_progress, &Actor_progress[0], sizeof(float) * (NUM_PEDS + NUM_CARS), cudaMemcpyHostToDevice));
CudaSafeCall(cudaMemcpy(v_d_Actor_street, &Actor_street[0], sizeof(int) * (NUM_PEDS + NUM_CARS), cudaMemcpyHostToDevice));
CudaSafeCall(cudaMemcpy(v_d_Car_max_velocity, &Car_max_velocity[0], sizeof(float) * (NUM_PEDS + NUM_CARS), cudaMemcpyHostToDevice));
CudaSafeCall(cudaMemcpy(v_d_Street_length, &Street_length[0], sizeof(float) * NUM_STREETS, cudaMemcpyHostToDevice));
CudaSafeCall(cudaMemcpy(v_d_Street_max_velocity, &Street_max_velocity[0], sizeof(float) * NUM_STREETS, cudaMemcpyHostToDevice));
CudaSafeCall(cudaMemcpy(v_d_Street_neighbors, &Street_neighbors[0], sizeof(int) * NUM_STREETS, cudaMemcpyHostToDevice));
CudaSafeCall(cudaMemcpy(v_d_Array_Street_size, &Array_Street_size[0], sizeof(int) * NUM_STREETS, cudaMemcpyHostToDevice));
CudaSafeCall(cudaMemcpy(v_d_Array_Street_offset, &Array_Street_offset[0], sizeof(int) * NUM_STREETS, cudaMemcpyHostToDevice));
CudaSafeCall(cudaMemcpy(v_d_Array_Street_arrays, &Array_Street_arrays[0], sizeof(int) * num_connections, cudaMemcpyHostToDevice));
CudaSafeCall(cudaMemcpy(v_d_input_actor_tag, &Actor_tag[0], sizeof(int) * (NUM_PEDS + NUM_CARS), cudaMemcpyHostToDevice));
CudaSafeCall(cudaMemcpy(v_d_input_actor_id, &Actor_id[0], sizeof(int) * (NUM_PEDS + NUM_CARS), cudaMemcpyHostToDevice));
CudaSafeCall(cudaMemcpy(v_d_jobs, &jobs[0], sizeof(int) * (NUM_PEDS + NUM_CARS), cudaMemcpyHostToDevice));
CudaSafeCall(cudaMemcpy(v_d_randomn, &randomn[0], sizeof(int) * NUM_STREETS, cudaMemcpyHostToDevice));
printf("Finished copying data.\n");
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
printf("Launching kernel...\n");
cudaEventRecord(start);
kernel<<<dim3(32), dim3((NUM_PEDS + NUM_CARS) / 32)>>>(GOOD_WEATHER, 1000000,
v_d_Actor_progress, v_d_Actor_street, v_d_Car_max_velocity, v_d_Street_length, v_d_Street_max_velocity,
v_d_Street_neighbors, v_d_Array_Street_size, v_d_Array_Street_offset, v_d_Array_Street_arrays, v_d_input_actor_tag,
v_d_input_actor_id, v_d_jobs, v_d_randomn);
CudaCheckError();
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
CudaCheckError();
printf("Kernel finished.\n");
cudaMemcpy(Actor_progress, v_d_Actor_progress, sizeof(float) * (NUM_PEDS + NUM_CARS), cudaMemcpyDeviceToHost);
for (int i = 0; i < NUM_PEDS + NUM_CARS; i++)
{
// printf(" %f ", Actor_progress[i]);
}
cudaMemcpy(Actor_street, v_d_Actor_street, sizeof(int) * (NUM_PEDS + NUM_CARS), cudaMemcpyDeviceToHost);
for (int i = 0; i < NUM_PEDS + NUM_CARS; i++)
{
// printf(" %i ", Actor_street[i]);
}
printf("\n\n\nElapsed time millis: %f\n", milliseconds);
} | .file "tmpxft_0009e46a_00000000-6_benchmark_column_reorder.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2345:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2345:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z14__cudaSafeCall9cudaErrorPKci.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "cudaSafeCall() failed at %s:%i : %s\n"
.section .text._Z14__cudaSafeCall9cudaErrorPKci,"axG",@progbits,_Z14__cudaSafeCall9cudaErrorPKci,comdat
.weak _Z14__cudaSafeCall9cudaErrorPKci
.type _Z14__cudaSafeCall9cudaErrorPKci, @function
_Z14__cudaSafeCall9cudaErrorPKci:
.LFB2337:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
ret
.L8:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
movl %edx, %ebp
call cudaGetErrorString@PLT
movq %rax, %r9
movl %ebp, %r8d
movq %rbx, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2337:
.size _Z14__cudaSafeCall9cudaErrorPKci, .-_Z14__cudaSafeCall9cudaErrorPKci
.section .rodata._Z16__cudaCheckErrorPKci.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "cudaCheckError() failed at %s:%i : %s\n"
.align 8
.LC2:
.string "cudaCheckError() with sync failed at %s:%i : %s\n"
.section .text._Z16__cudaCheckErrorPKci,"axG",@progbits,_Z16__cudaCheckErrorPKci,comdat
.weak _Z16__cudaCheckErrorPKci
.type _Z16__cudaCheckErrorPKci, @function
_Z16__cudaCheckErrorPKci:
.LFB2338:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movl %esi, %ebp
call cudaGetLastError@PLT
testl %eax, %eax
jne .L13
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L14
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl %ebp, %r8d
movq %rbx, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L14:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl %ebp, %r8d
movq %rbx, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2338:
.size _Z16__cudaCheckErrorPKci, .-_Z16__cudaCheckErrorPKci
.text
.globl _Z15method_Car_moveii
.type _Z15method_Car_moveii, @function
_Z15method_Car_moveii:
.LFB2339:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2339:
.size _Z15method_Car_moveii, .-_Z15method_Car_moveii
.globl _Z22method_Pedestrian_moveii
.type _Z22method_Pedestrian_moveii, @function
_Z22method_Pedestrian_moveii:
.LFB2340:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2340:
.size _Z22method_Pedestrian_moveii, .-_Z22method_Pedestrian_moveii
.globl _Z5blockiiii
.type _Z5blockiiii, @function
_Z5blockiiii:
.LFB2341:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2341:
.size _Z5blockiiii, .-_Z5blockiiii
.globl _Z59__device_stub__Z6kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_iiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_
.type _Z59__device_stub__Z6kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_iiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_, @function
_Z59__device_stub__Z6kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_iiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_:
.LFB2367:
.cfi_startproc
endbr64
subq $312, %rsp
.cfi_def_cfa_offset 320
movl %edi, 108(%rsp)
movl %esi, 104(%rsp)
movq %rdx, 96(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
movq 320(%rsp), %rax
movq %rax, 64(%rsp)
movq 328(%rsp), %rax
movq %rax, 56(%rsp)
movq 336(%rsp), %rax
movq %rax, 48(%rsp)
movq 344(%rsp), %rax
movq %rax, 40(%rsp)
movq 352(%rsp), %rax
movq %rax, 32(%rsp)
movq 360(%rsp), %rax
movq %rax, 24(%rsp)
movq 368(%rsp), %rax
movq %rax, 16(%rsp)
movq 376(%rsp), %rax
movq %rax, 8(%rsp)
movq 384(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 296(%rsp)
xorl %eax, %eax
leaq 108(%rsp), %rax
movq %rax, 176(%rsp)
leaq 104(%rsp), %rax
movq %rax, 184(%rsp)
leaq 96(%rsp), %rax
movq %rax, 192(%rsp)
leaq 88(%rsp), %rax
movq %rax, 200(%rsp)
leaq 80(%rsp), %rax
movq %rax, 208(%rsp)
leaq 72(%rsp), %rax
movq %rax, 216(%rsp)
leaq 64(%rsp), %rax
movq %rax, 224(%rsp)
leaq 56(%rsp), %rax
movq %rax, 232(%rsp)
leaq 48(%rsp), %rax
movq %rax, 240(%rsp)
leaq 40(%rsp), %rax
movq %rax, 248(%rsp)
leaq 32(%rsp), %rax
movq %rax, 256(%rsp)
leaq 24(%rsp), %rax
movq %rax, 264(%rsp)
leaq 16(%rsp), %rax
movq %rax, 272(%rsp)
leaq 8(%rsp), %rax
movq %rax, 280(%rsp)
movq %rsp, %rax
movq %rax, 288(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
leaq 120(%rsp), %rcx
leaq 112(%rsp), %rdx
leaq 140(%rsp), %rsi
leaq 128(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 296(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $312, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 120(%rsp)
.cfi_def_cfa_offset 328
pushq 120(%rsp)
.cfi_def_cfa_offset 336
leaq 192(%rsp), %r9
movq 156(%rsp), %rcx
movl 164(%rsp), %r8d
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
leaq _Z6kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 320
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2367:
.size _Z59__device_stub__Z6kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_iiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_, .-_Z59__device_stub__Z6kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_iiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_
.globl _Z6kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_
.type _Z6kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_, @function
_Z6kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_:
.LFB2368:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 88(%rsp)
.cfi_def_cfa_offset 32
pushq 88(%rsp)
.cfi_def_cfa_offset 40
pushq 88(%rsp)
.cfi_def_cfa_offset 48
pushq 88(%rsp)
.cfi_def_cfa_offset 56
pushq 88(%rsp)
.cfi_def_cfa_offset 64
pushq 88(%rsp)
.cfi_def_cfa_offset 72
pushq 88(%rsp)
.cfi_def_cfa_offset 80
pushq 88(%rsp)
.cfi_def_cfa_offset 88
pushq 88(%rsp)
.cfi_def_cfa_offset 96
call _Z59__device_stub__Z6kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_iiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_
addq $88, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2368:
.size _Z6kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_, .-_Z6kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Setting up scenario...\n"
.LC4:
.string "Scenario set up.\n"
.LC5:
.string "Copying data to GPU...\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "/home/ubuntu/Datasets/stackv2/train-structured/prg-titech/array2016-paper/master/benchmarks/benchmark_column_reorder.cu"
.section .rodata.str1.1
.LC7:
.string "Finished copying data.\n"
.LC8:
.string "Launching kernel...\n"
.LC10:
.string "Kernel finished.\n"
.LC11:
.string "\n\n\nElapsed time millis: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2342:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $248, %rsp
.cfi_def_cfa_offset 304
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $42, %edi
call srand@PLT
movl $2000, %edi
call _Znam@PLT
movq %rax, %rbp
movq %rax, 8(%rsp)
movl $2000, %edi
call _Znam@PLT
movq %rax, %r12
movq %rax, 16(%rsp)
movl $2000, %edi
call _Znam@PLT
movq %rax, %r13
movq %rax, 24(%rsp)
movl $0, %ebx
.L30:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $35, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
leal (%rdx,%rdx,4), %edx
subl %edx, %eax
addl $1, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rbx,4)
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $36, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
sall $3, %edx
subl %edx, %eax
addl $45, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r12,%rbx,4)
movl %ebx, 0(%r13,%rbx,4)
addq $1, %rbx
cmpq $500, %rbx
jne .L30
movl $2000, %edi
call _Znam@PLT
movq %rax, %r12
movq %rax, 32(%rsp)
movl $2000, %edi
call _Znam@PLT
movq %rax, %r13
movq %rax, 40(%rsp)
movl $0, %ebx
movl $0, %ebp
.L31:
movl %ebp, (%r12,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
addl $1, %eax
movl %eax, 0(%r13,%rbx)
addl %eax, %ebp
addq $4, %rbx
cmpq $2000, %rbx
jne .L31
movslq %ebp, %rax
movabsq $2305843009213693950, %rdx
cmpq %rax, %rdx
jb .L32
leaq 0(,%rax,4), %r14
movq %r14, (%rsp)
movq %r14, %rdi
call _Znam@PLT
movq %rax, 48(%rsp)
movq %rax, %rbx
leaq (%r14,%rax), %r12
testl %ebp, %ebp
jle .L34
.L36:
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $500, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L36
.L34:
movl $81920, %edi
call _Znam@PLT
movq %rax, %r15
movl $81920, %edi
call _Znam@PLT
movq %rax, %r13
movl $81920, %edi
call _Znam@PLT
movq %rax, %r14
movl $81920, %edi
call _Znam@PLT
movq %rax, %r12
movl $81920, %edi
call _Znam@PLT
movq %rax, %rbp
movl $0, %ebx
.L37:
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $500, %edx, %edx
subl %edx, %eax
movl %eax, (%r15,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%r13,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $35, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
sall $2, %edx
subl %edx, %eax
addl $65, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r14,%rbx)
addq $4, %rbx
cmpq $81920, %rbx
jne .L37
movl $0, %eax
.L38:
movl $1, (%r12,%rax,4)
movl %eax, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $16384, %rax
jne .L38
.L39:
movl $0, (%r12,%rax,4)
movl %eax, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $20480, %rax
jne .L39
movl $42, %edi
call srand@PLT
movl $81920, %edi
call _Znam@PLT
movq %rax, %rdx
movq %rax, 56(%rsp)
movl $0, %eax
.L40:
movl %eax, (%rdx,%rax,4)
addq $1, %rax
cmpq $20480, %rax
jne .L40
movl $2000, %edi
call _Znam@PLT
movq %rax, 64(%rsp)
movq %rax, %rbx
addq $2000, %rax
movq %r15, 72(%rsp)
movq %rax, %r15
.L41:
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $500, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbx, %r15
jne .L41
movq 72(%rsp), %r15
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 88(%rsp), %rdi
movl $81920, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $269, %edx
leaq .LC6(%rip), %rbx
movq %rbx, %rsi
call _Z14__cudaSafeCall9cudaErrorPKci
leaq 96(%rsp), %rdi
movl $81920, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $270, %edx
movq %rbx, %rsi
call _Z14__cudaSafeCall9cudaErrorPKci
leaq 104(%rsp), %rdi
movl $81920, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $271, %edx
movq %rbx, %rsi
call _Z14__cudaSafeCall9cudaErrorPKci
leaq 112(%rsp), %rdi
movl $2000, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $272, %edx
movq %rbx, %rsi
call _Z14__cudaSafeCall9cudaErrorPKci
leaq 120(%rsp), %rdi
movl $2000, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $273, %edx
movq %rbx, %rsi
call _Z14__cudaSafeCall9cudaErrorPKci
leaq 128(%rsp), %rdi
movl $2000, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $274, %edx
movq %rbx, %rsi
call _Z14__cudaSafeCall9cudaErrorPKci
leaq 136(%rsp), %rdi
movl $2000, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $275, %edx
movq %rbx, %rsi
call _Z14__cudaSafeCall9cudaErrorPKci
leaq 144(%rsp), %rdi
movl $2000, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $276, %edx
movq %rbx, %rsi
call _Z14__cudaSafeCall9cudaErrorPKci
leaq 152(%rsp), %rdi
movq (%rsp), %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $277, %edx
movq %rbx, %rsi
call _Z14__cudaSafeCall9cudaErrorPKci
leaq 160(%rsp), %rdi
movl $81920, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $278, %edx
movq %rbx, %rsi
call _Z14__cudaSafeCall9cudaErrorPKci
leaq 168(%rsp), %rdi
movl $81920, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $279, %edx
movq %rbx, %rsi
call _Z14__cudaSafeCall9cudaErrorPKci
leaq 176(%rsp), %rdi
movl $81920, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $280, %edx
movq %rbx, %rsi
call _Z14__cudaSafeCall9cudaErrorPKci
leaq 184(%rsp), %rdi
movl $2000, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $281, %edx
movq %rbx, %rsi
call _Z14__cudaSafeCall9cudaErrorPKci
movl $1, %ecx
movl $81920, %edx
movq %r13, %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $283, %edx
movq %rbx, %rsi
call _Z14__cudaSafeCall9cudaErrorPKci
movl $1, %ecx
movl $81920, %edx
movq %r15, %rsi
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $284, %edx
movq %rbx, %rsi
call _Z14__cudaSafeCall9cudaErrorPKci
movl $1, %ecx
movl $81920, %edx
movq %r14, %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $285, %edx
movq %rbx, %rsi
call _Z14__cudaSafeCall9cudaErrorPKci
movl $1, %ecx
movl $2000, %edx
movq 8(%rsp), %rsi
movq 112(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $286, %edx
movq %rbx, %rsi
call _Z14__cudaSafeCall9cudaErrorPKci
movl $1, %ecx
movl $2000, %edx
movq 16(%rsp), %rsi
movq 120(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $287, %edx
movq %rbx, %rsi
call _Z14__cudaSafeCall9cudaErrorPKci
movl $1, %ecx
movl $2000, %edx
movq 24(%rsp), %rsi
movq 128(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $288, %edx
movq %rbx, %rsi
call _Z14__cudaSafeCall9cudaErrorPKci
movl $1, %ecx
movl $2000, %edx
movq 40(%rsp), %rsi
movq 136(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $289, %edx
movq %rbx, %rsi
call _Z14__cudaSafeCall9cudaErrorPKci
movl $1, %ecx
movl $2000, %edx
movq 32(%rsp), %rsi
movq 144(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $290, %edx
movq %rbx, %rsi
call _Z14__cudaSafeCall9cudaErrorPKci
movl $1, %ecx
movq (%rsp), %rdx
movq 48(%rsp), %rsi
movq 152(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $291, %edx
movq %rbx, %rsi
call _Z14__cudaSafeCall9cudaErrorPKci
movl $1, %ecx
movl $81920, %edx
movq %r12, %rsi
movq 160(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $292, %edx
movq %rbx, %rsi
call _Z14__cudaSafeCall9cudaErrorPKci
movl $1, %ecx
movl $81920, %edx
movq %rbp, %rsi
movq 168(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $293, %edx
movq %rbx, %rsi
call _Z14__cudaSafeCall9cudaErrorPKci
movl $1, %ecx
movl $81920, %edx
movq 56(%rsp), %rsi
movq 176(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $294, %edx
movq %rbx, %rsi
call _Z14__cudaSafeCall9cudaErrorPKci
movl $1, %ecx
movl $2000, %edx
movq 64(%rsp), %rsi
movq 184(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $295, %edx
movq %rbx, %rsi
call _Z14__cudaSafeCall9cudaErrorPKci
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 192(%rsp), %rdi
call cudaEventCreate@PLT
leaq 200(%rsp), %rdi
call cudaEventCreate@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 192(%rsp), %rdi
call cudaEventRecord@PLT
movl $640, 220(%rsp)
movl $1, 224(%rsp)
movl $1, 228(%rsp)
movl $32, 208(%rsp)
movl $1, 212(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 220(%rsp), %rdx
movl $1, %ecx
movq 208(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L59
.L42:
movl $309, %esi
leaq .LC6(%rip), %rbx
movq %rbx, %rdi
call _Z16__cudaCheckErrorPKci
movl $0, %esi
movq 200(%rsp), %rdi
call cudaEventRecord@PLT
movq 200(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 220(%rsp)
leaq 220(%rsp), %rdi
movq 200(%rsp), %rdx
movq 192(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $316, %esi
movq %rbx, %rdi
call _Z16__cudaCheckErrorPKci
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $81920, %edx
movq 88(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $20480, %eax
.L43:
subl $1, %eax
jne .L43
movl $2, %ecx
movl $81920, %edx
movq 96(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl $20480, %eax
.L44:
subl $1, %eax
jne .L44
pxor %xmm0, %xmm0
cvtss2sd 220(%rsp), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L60
movl $0, %eax
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movq 232(%rsp), %rax
subq %fs:40, %rax
je .L35
call __stack_chk_fail@PLT
.L35:
call __cxa_throw_bad_array_new_length@PLT
.L59:
subq $8, %rsp
.cfi_def_cfa_offset 312
pushq 192(%rsp)
.cfi_def_cfa_offset 320
pushq 192(%rsp)
.cfi_def_cfa_offset 328
pushq 192(%rsp)
.cfi_def_cfa_offset 336
pushq 192(%rsp)
.cfi_def_cfa_offset 344
pushq 192(%rsp)
.cfi_def_cfa_offset 352
pushq 192(%rsp)
.cfi_def_cfa_offset 360
pushq 192(%rsp)
.cfi_def_cfa_offset 368
pushq 192(%rsp)
.cfi_def_cfa_offset 376
pushq 192(%rsp)
.cfi_def_cfa_offset 384
movq 192(%rsp), %r9
movq 184(%rsp), %r8
movq 176(%rsp), %rcx
movq 168(%rsp), %rdx
movl $1000000, %esi
movl $0, %edi
call _Z59__device_stub__Z6kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_iiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_
addq $80, %rsp
.cfi_def_cfa_offset 304
jmp .L42
.L60:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2342:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC12:
.string "_Z6kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_"
.section .rodata.str1.1
.LC13:
.string "d_Actor_progress"
.LC14:
.string "d_Actor_street"
.LC15:
.string "d_Car_max_velocity"
.LC16:
.string "d_Street_length"
.LC17:
.string "d_Street_max_velocity"
.LC18:
.string "d_Street_neighbors"
.LC19:
.string "d_Array_Street_size"
.LC20:
.string "d_Array_Street_offset"
.LC21:
.string "d_Array_Street_arrays"
.LC22:
.string "d_input_actor_tag"
.LC23:
.string "d_input_actor_id"
.LC24:
.string "d_jobs"
.LC25:
.string "d_randomn"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2370:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16d_Actor_progress(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL14d_Actor_street(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL18d_Car_max_velocity(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZL15d_Street_length(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21d_Street_max_velocity(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _ZL18d_Street_neighbors(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _ZL19d_Array_Street_size(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21d_Array_Street_offset(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21d_Array_Street_arrays(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17d_input_actor_tag(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC23(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16d_input_actor_id(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC24(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6d_jobs(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC25(%rip), %rdx
movq %rdx, %rcx
leaq _ZL9d_randomn(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2370:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL9d_randomn
.comm _ZL9d_randomn,8,8
.local _ZL6d_jobs
.comm _ZL6d_jobs,8,8
.local _ZL16d_input_actor_id
.comm _ZL16d_input_actor_id,8,8
.local _ZL17d_input_actor_tag
.comm _ZL17d_input_actor_tag,8,8
.local _ZL21d_Array_Street_arrays
.comm _ZL21d_Array_Street_arrays,8,8
.local _ZL21d_Array_Street_offset
.comm _ZL21d_Array_Street_offset,8,8
.local _ZL19d_Array_Street_size
.comm _ZL19d_Array_Street_size,8,8
.local _ZL18d_Street_neighbors
.comm _ZL18d_Street_neighbors,8,8
.local _ZL21d_Street_max_velocity
.comm _ZL21d_Street_max_velocity,8,8
.local _ZL15d_Street_length
.comm _ZL15d_Street_length,8,8
.local _ZL18d_Car_max_velocity
.comm _ZL18d_Car_max_velocity,8,8
.local _ZL14d_Actor_street
.comm _ZL14d_Actor_street,8,8
.local _ZL16d_Actor_progress
.comm _ZL16d_Actor_progress,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define REORDER 1
#define GOOD_WEATHER 0
#define BAD_WEATHER 1
#define TAG_Car 0
#define TAG_Pedestrian 1
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
//#include <random>
//#include <array>
#include <algorithm>
#define NUM_CARS 4096
#define NUM_PEDS 16384
#define NUM_STREETS 500
#define MAX_CONNECTIONS 10
#define MAX_LEN 25
using namespace std;
// Define this to turn on error checking
#define CUDA_ERROR_CHECK
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CudaCheckError() __cudaCheckError( __FILE__, __LINE__ )
inline void __cudaSafeCall( cudaError err, const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
cudaError err = cudaGetLastError();
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment away if needed.
err = cudaDeviceSynchronize();
if( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
__device__ float *d_Actor_progress;
__device__ int *d_Actor_street;
__device__ float *d_Car_max_velocity;
__device__ float *d_Street_length;
__device__ float *d_Street_max_velocity;
__device__ int *d_Street_neighbors;
__device__ int *d_Array_Street_size;
__device__ int *d_Array_Street_offset;
__device__ int *d_Array_Street_arrays;
__device__ int *d_input_actor_tag;
__device__ int *d_input_actor_id;
__device__ int *d_jobs;
__device__ int *d_randomn;
__device__ void method_Car_move(int actor_id, int weather)
{
float weather_multiplier;
if (weather == GOOD_WEATHER)
{
weather_multiplier = 1.0;
}
else if (weather == BAD_WEATHER)
{
weather_multiplier = 0.75;
}
float speed = min(d_Car_max_velocity[actor_id], d_Street_max_velocity[d_Actor_street[actor_id]]) * weather_multiplier;
d_Actor_progress[actor_id] = d_Actor_progress[actor_id] + (speed / 60.0); /* 1 tick = 1 minute */
if (d_Actor_progress[actor_id] >= d_Street_length[d_Actor_street[actor_id]])
{
// move to different street
int array_id = d_Street_neighbors[d_Actor_street[actor_id]];
int neighbor_index = d_randomn[d_Actor_street[actor_id]] % d_Array_Street_size[array_id];
d_Actor_street[actor_id] = d_Array_Street_arrays[d_Array_Street_offset[array_id] + neighbor_index];
d_Actor_progress[actor_id] = 0.0f;
}
}
__device__ void method_Pedestrian_move(int actor_id, int weather)
{
float speed = d_randomn[((int) (d_Actor_progress[actor_id]*d_Actor_progress[actor_id])) % NUM_STREETS] % 7 - 2;
d_Actor_progress[actor_id] = d_Actor_progress[actor_id] + (speed / 60.0);
if (d_Actor_progress[actor_id] >= d_Street_length[d_Actor_street[actor_id]])
{
// move to different street
int array_id = d_Street_neighbors[d_Actor_street[actor_id]];
int neighbor_index = d_randomn[d_Actor_street[actor_id]] % d_Array_Street_size[array_id];
d_Actor_street[actor_id] = d_Array_Street_arrays[d_Array_Street_offset[array_id] + neighbor_index];
d_Actor_progress[actor_id] = 0.0f;
}
}
__device__ void block(int actor_tag, int actor_id, int weather, int ticks)
{
for (int i = 0; i < ticks; i++)
{
switch (actor_tag)
{
case TAG_Car:
method_Car_move(actor_id, weather);
break;
case TAG_Pedestrian:
method_Pedestrian_move(actor_id, weather);
break;
}
}
}
__global__ void kernel(int weather, int ticks,
float *v_d_Actor_progress, int *v_d_Actor_street, float *v_d_Car_max_velocity,
float *v_d_Street_length, float *v_d_Street_max_velocity, int *v_d_Street_neighbors,
int *v_d_Array_Street_size, int *v_d_Array_Street_offset, int *v_d_Array_Street_arrays,
int *v_d_input_actor_tag, int *v_d_input_actor_id, int *v_d_jobs, int *v_d_randomn)
{
d_Actor_progress = v_d_Actor_progress;
d_Actor_street = v_d_Actor_street;
d_Car_max_velocity = v_d_Car_max_velocity;
d_Street_length = v_d_Street_length;
d_Street_max_velocity = v_d_Street_max_velocity;
d_Street_neighbors = v_d_Street_neighbors;
d_Array_Street_size = v_d_Array_Street_size;
d_Array_Street_offset = v_d_Array_Street_offset;
d_Array_Street_arrays = v_d_Array_Street_arrays;
d_input_actor_tag = v_d_input_actor_tag;
d_input_actor_id = v_d_input_actor_id;
d_jobs = v_d_jobs;
d_randomn = v_d_randomn;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
__syncthreads();
#if (REORDER)
block(d_input_actor_tag[d_jobs[tid]], d_input_actor_id[d_jobs[tid]], weather, ticks);
#else
block(d_input_actor_tag[tid], d_input_actor_id[tid], weather, ticks);
#endif
}
int main()
{
printf("Setting up scenario...\n");
srand(42);
// streets
float *Street_length = new float[NUM_STREETS];
float *Street_max_velocity = new float[NUM_STREETS];
int *Street_neighbors = new int[NUM_STREETS];
for (int i = 0; i < NUM_STREETS; i++)
{
Street_length[i] = rand() % MAX_LEN + 1;
Street_max_velocity[i] = rand() % 40 + 45; /* speed between 45 and 105 */
Street_neighbors[i] = i;
}
// neighbors
int *Array_Street_offset = new int[NUM_STREETS];
int *Array_Street_size = new int[NUM_STREETS];
int num_connections = 0;
for (int i = 0; i < NUM_STREETS; i++)
{
Array_Street_offset[i] = num_connections;
int connections = rand() % MAX_CONNECTIONS + 1;
Array_Street_size[i] = connections;
num_connections += connections;
}
int *Array_Street_arrays = new int[num_connections];
for (int i = 0; i < num_connections; i++)
{
Array_Street_arrays[i] = rand() % NUM_STREETS;
}
// actors
int *Actor_street = new int[NUM_PEDS + NUM_CARS];
float *Actor_progress = new float[NUM_PEDS + NUM_CARS];
float *Car_max_velocity = new float[NUM_CARS + NUM_PEDS];
int *Actor_tag = new int[NUM_PEDS + NUM_CARS];
int *Actor_id = new int[NUM_PEDS + NUM_CARS];
for (int i = 0; i < NUM_PEDS + NUM_CARS; i++)
{
Actor_street[i] = rand() % NUM_STREETS;
Actor_progress[i] = rand() % 10;
Car_max_velocity[i] = rand() % 20 + 65;
}
for (int i = 0; i < NUM_PEDS; i++)
{
Actor_tag[i] = TAG_Pedestrian;
Actor_id[i] = i;
}
for (int i = NUM_PEDS; i < NUM_PEDS + NUM_CARS; i++)
{
Actor_tag[i] = TAG_Car;
Actor_id[i] = i;
}
std::srand(42);
#if !(REORDER)
random_shuffle(Actor_tag, Actor_tag + NUM_CARS + NUM_PEDS);
#endif
// jobs (dummy)
int *jobs = new int[NUM_PEDS + NUM_CARS];
for (int i = 0; i < NUM_CARS + NUM_PEDS; i++)
{
jobs[i] = i;
}
// random numbers
int *randomn = new int[NUM_STREETS];
for (int i = 0; i < NUM_STREETS; i++)
{
randomn[i] = rand() % NUM_STREETS;
}
printf("Scenario set up.\n");
printf("Copying data to GPU...\n");
float *v_d_Actor_progress;
int *v_d_Actor_street;
float *v_d_Car_max_velocity;
float *v_d_Street_length;
float *v_d_Street_max_velocity;
int *v_d_Street_neighbors;
int *v_d_Array_Street_size;
int *v_d_Array_Street_offset;
int *v_d_Array_Street_arrays;
int *v_d_input_actor_tag;
int *v_d_input_actor_id;
int *v_d_jobs;
int *v_d_randomn;
CudaSafeCall(cudaMalloc((void**) &v_d_Actor_progress, sizeof(float) * (NUM_PEDS + NUM_CARS)));
CudaSafeCall(cudaMalloc((void**) &v_d_Actor_street, sizeof(int) * (NUM_PEDS + NUM_CARS)));
CudaSafeCall(cudaMalloc((void**) &v_d_Car_max_velocity, sizeof(float) * (NUM_PEDS + NUM_CARS)));
CudaSafeCall(cudaMalloc((void**) &v_d_Street_length, sizeof(float) * NUM_STREETS));
CudaSafeCall(cudaMalloc((void**) &v_d_Street_max_velocity, sizeof(float) * NUM_STREETS));
CudaSafeCall(cudaMalloc((void**) &v_d_Street_neighbors, sizeof(int) * NUM_STREETS));
CudaSafeCall(cudaMalloc((void**) &v_d_Array_Street_size, sizeof(int) * NUM_STREETS));
CudaSafeCall(cudaMalloc((void**) &v_d_Array_Street_offset, sizeof(int) * NUM_STREETS));
CudaSafeCall(cudaMalloc((void**) &v_d_Array_Street_arrays, sizeof(int) * num_connections));
CudaSafeCall(cudaMalloc((void**) &v_d_input_actor_tag, sizeof(int) * (NUM_PEDS + NUM_CARS)));
CudaSafeCall(cudaMalloc((void**) &v_d_input_actor_id, sizeof(int) * (NUM_PEDS + NUM_CARS)));
CudaSafeCall(cudaMalloc((void**) &v_d_jobs, sizeof(int) * (NUM_PEDS + NUM_CARS)));
CudaSafeCall(cudaMalloc((void**) &v_d_randomn, sizeof(int) * NUM_STREETS));
CudaSafeCall(cudaMemcpy(v_d_Actor_progress, &Actor_progress[0], sizeof(float) * (NUM_PEDS + NUM_CARS), cudaMemcpyHostToDevice));
CudaSafeCall(cudaMemcpy(v_d_Actor_street, &Actor_street[0], sizeof(int) * (NUM_PEDS + NUM_CARS), cudaMemcpyHostToDevice));
CudaSafeCall(cudaMemcpy(v_d_Car_max_velocity, &Car_max_velocity[0], sizeof(float) * (NUM_PEDS + NUM_CARS), cudaMemcpyHostToDevice));
CudaSafeCall(cudaMemcpy(v_d_Street_length, &Street_length[0], sizeof(float) * NUM_STREETS, cudaMemcpyHostToDevice));
CudaSafeCall(cudaMemcpy(v_d_Street_max_velocity, &Street_max_velocity[0], sizeof(float) * NUM_STREETS, cudaMemcpyHostToDevice));
CudaSafeCall(cudaMemcpy(v_d_Street_neighbors, &Street_neighbors[0], sizeof(int) * NUM_STREETS, cudaMemcpyHostToDevice));
CudaSafeCall(cudaMemcpy(v_d_Array_Street_size, &Array_Street_size[0], sizeof(int) * NUM_STREETS, cudaMemcpyHostToDevice));
CudaSafeCall(cudaMemcpy(v_d_Array_Street_offset, &Array_Street_offset[0], sizeof(int) * NUM_STREETS, cudaMemcpyHostToDevice));
CudaSafeCall(cudaMemcpy(v_d_Array_Street_arrays, &Array_Street_arrays[0], sizeof(int) * num_connections, cudaMemcpyHostToDevice));
CudaSafeCall(cudaMemcpy(v_d_input_actor_tag, &Actor_tag[0], sizeof(int) * (NUM_PEDS + NUM_CARS), cudaMemcpyHostToDevice));
CudaSafeCall(cudaMemcpy(v_d_input_actor_id, &Actor_id[0], sizeof(int) * (NUM_PEDS + NUM_CARS), cudaMemcpyHostToDevice));
CudaSafeCall(cudaMemcpy(v_d_jobs, &jobs[0], sizeof(int) * (NUM_PEDS + NUM_CARS), cudaMemcpyHostToDevice));
CudaSafeCall(cudaMemcpy(v_d_randomn, &randomn[0], sizeof(int) * NUM_STREETS, cudaMemcpyHostToDevice));
printf("Finished copying data.\n");
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
printf("Launching kernel...\n");
cudaEventRecord(start);
kernel<<<dim3(32), dim3((NUM_PEDS + NUM_CARS) / 32)>>>(GOOD_WEATHER, 1000000,
v_d_Actor_progress, v_d_Actor_street, v_d_Car_max_velocity, v_d_Street_length, v_d_Street_max_velocity,
v_d_Street_neighbors, v_d_Array_Street_size, v_d_Array_Street_offset, v_d_Array_Street_arrays, v_d_input_actor_tag,
v_d_input_actor_id, v_d_jobs, v_d_randomn);
CudaCheckError();
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
CudaCheckError();
printf("Kernel finished.\n");
cudaMemcpy(Actor_progress, v_d_Actor_progress, sizeof(float) * (NUM_PEDS + NUM_CARS), cudaMemcpyDeviceToHost);
for (int i = 0; i < NUM_PEDS + NUM_CARS; i++)
{
// printf(" %f ", Actor_progress[i]);
}
cudaMemcpy(Actor_street, v_d_Actor_street, sizeof(int) * (NUM_PEDS + NUM_CARS), cudaMemcpyDeviceToHost);
for (int i = 0; i < NUM_PEDS + NUM_CARS; i++)
{
// printf(" %i ", Actor_street[i]);
}
printf("\n\n\nElapsed time millis: %f\n", milliseconds);
} | #define REORDER 1
#define GOOD_WEATHER 0
#define BAD_WEATHER 1
#define TAG_Car 0
#define TAG_Pedestrian 1
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
//#include <random>
//#include <array>
#include <algorithm>
#define NUM_CARS 4096
#define NUM_PEDS 16384
#define NUM_STREETS 500
#define MAX_CONNECTIONS 10
#define MAX_LEN 25
using namespace std;
// Define this to turn on error checking
#define CUDA_ERROR_CHECK
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CudaCheckError() __cudaCheckError( __FILE__, __LINE__ )
inline void __cudaSafeCall( hipError_t err, const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
if ( hipSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
hipError_t err = hipGetLastError();
if ( hipSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment away if needed.
err = hipDeviceSynchronize();
if( hipSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
__device__ float *d_Actor_progress;
__device__ int *d_Actor_street;
__device__ float *d_Car_max_velocity;
__device__ float *d_Street_length;
__device__ float *d_Street_max_velocity;
__device__ int *d_Street_neighbors;
__device__ int *d_Array_Street_size;
__device__ int *d_Array_Street_offset;
__device__ int *d_Array_Street_arrays;
__device__ int *d_input_actor_tag;
__device__ int *d_input_actor_id;
__device__ int *d_jobs;
__device__ int *d_randomn;
__device__ void method_Car_move(int actor_id, int weather)
{
float weather_multiplier;
if (weather == GOOD_WEATHER)
{
weather_multiplier = 1.0;
}
else if (weather == BAD_WEATHER)
{
weather_multiplier = 0.75;
}
float speed = min(d_Car_max_velocity[actor_id], d_Street_max_velocity[d_Actor_street[actor_id]]) * weather_multiplier;
d_Actor_progress[actor_id] = d_Actor_progress[actor_id] + (speed / 60.0); /* 1 tick = 1 minute */
if (d_Actor_progress[actor_id] >= d_Street_length[d_Actor_street[actor_id]])
{
// move to different street
int array_id = d_Street_neighbors[d_Actor_street[actor_id]];
int neighbor_index = d_randomn[d_Actor_street[actor_id]] % d_Array_Street_size[array_id];
d_Actor_street[actor_id] = d_Array_Street_arrays[d_Array_Street_offset[array_id] + neighbor_index];
d_Actor_progress[actor_id] = 0.0f;
}
}
__device__ void method_Pedestrian_move(int actor_id, int weather)
{
float speed = d_randomn[((int) (d_Actor_progress[actor_id]*d_Actor_progress[actor_id])) % NUM_STREETS] % 7 - 2;
d_Actor_progress[actor_id] = d_Actor_progress[actor_id] + (speed / 60.0);
if (d_Actor_progress[actor_id] >= d_Street_length[d_Actor_street[actor_id]])
{
// move to different street
int array_id = d_Street_neighbors[d_Actor_street[actor_id]];
int neighbor_index = d_randomn[d_Actor_street[actor_id]] % d_Array_Street_size[array_id];
d_Actor_street[actor_id] = d_Array_Street_arrays[d_Array_Street_offset[array_id] + neighbor_index];
d_Actor_progress[actor_id] = 0.0f;
}
}
__device__ void block(int actor_tag, int actor_id, int weather, int ticks)
{
for (int i = 0; i < ticks; i++)
{
switch (actor_tag)
{
case TAG_Car:
method_Car_move(actor_id, weather);
break;
case TAG_Pedestrian:
method_Pedestrian_move(actor_id, weather);
break;
}
}
}
__global__ void kernel(int weather, int ticks,
float *v_d_Actor_progress, int *v_d_Actor_street, float *v_d_Car_max_velocity,
float *v_d_Street_length, float *v_d_Street_max_velocity, int *v_d_Street_neighbors,
int *v_d_Array_Street_size, int *v_d_Array_Street_offset, int *v_d_Array_Street_arrays,
int *v_d_input_actor_tag, int *v_d_input_actor_id, int *v_d_jobs, int *v_d_randomn)
{
d_Actor_progress = v_d_Actor_progress;
d_Actor_street = v_d_Actor_street;
d_Car_max_velocity = v_d_Car_max_velocity;
d_Street_length = v_d_Street_length;
d_Street_max_velocity = v_d_Street_max_velocity;
d_Street_neighbors = v_d_Street_neighbors;
d_Array_Street_size = v_d_Array_Street_size;
d_Array_Street_offset = v_d_Array_Street_offset;
d_Array_Street_arrays = v_d_Array_Street_arrays;
d_input_actor_tag = v_d_input_actor_tag;
d_input_actor_id = v_d_input_actor_id;
d_jobs = v_d_jobs;
d_randomn = v_d_randomn;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
__syncthreads();
#if (REORDER)
block(d_input_actor_tag[d_jobs[tid]], d_input_actor_id[d_jobs[tid]], weather, ticks);
#else
block(d_input_actor_tag[tid], d_input_actor_id[tid], weather, ticks);
#endif
}
int main()
{
printf("Setting up scenario...\n");
srand(42);
// streets
float *Street_length = new float[NUM_STREETS];
float *Street_max_velocity = new float[NUM_STREETS];
int *Street_neighbors = new int[NUM_STREETS];
for (int i = 0; i < NUM_STREETS; i++)
{
Street_length[i] = rand() % MAX_LEN + 1;
Street_max_velocity[i] = rand() % 40 + 45; /* speed between 45 and 105 */
Street_neighbors[i] = i;
}
// neighbors
int *Array_Street_offset = new int[NUM_STREETS];
int *Array_Street_size = new int[NUM_STREETS];
int num_connections = 0;
for (int i = 0; i < NUM_STREETS; i++)
{
Array_Street_offset[i] = num_connections;
int connections = rand() % MAX_CONNECTIONS + 1;
Array_Street_size[i] = connections;
num_connections += connections;
}
int *Array_Street_arrays = new int[num_connections];
for (int i = 0; i < num_connections; i++)
{
Array_Street_arrays[i] = rand() % NUM_STREETS;
}
// actors
int *Actor_street = new int[NUM_PEDS + NUM_CARS];
float *Actor_progress = new float[NUM_PEDS + NUM_CARS];
float *Car_max_velocity = new float[NUM_CARS + NUM_PEDS];
int *Actor_tag = new int[NUM_PEDS + NUM_CARS];
int *Actor_id = new int[NUM_PEDS + NUM_CARS];
for (int i = 0; i < NUM_PEDS + NUM_CARS; i++)
{
Actor_street[i] = rand() % NUM_STREETS;
Actor_progress[i] = rand() % 10;
Car_max_velocity[i] = rand() % 20 + 65;
}
for (int i = 0; i < NUM_PEDS; i++)
{
Actor_tag[i] = TAG_Pedestrian;
Actor_id[i] = i;
}
for (int i = NUM_PEDS; i < NUM_PEDS + NUM_CARS; i++)
{
Actor_tag[i] = TAG_Car;
Actor_id[i] = i;
}
std::srand(42);
#if !(REORDER)
random_shuffle(Actor_tag, Actor_tag + NUM_CARS + NUM_PEDS);
#endif
// jobs (dummy)
int *jobs = new int[NUM_PEDS + NUM_CARS];
for (int i = 0; i < NUM_CARS + NUM_PEDS; i++)
{
jobs[i] = i;
}
// random numbers
int *randomn = new int[NUM_STREETS];
for (int i = 0; i < NUM_STREETS; i++)
{
randomn[i] = rand() % NUM_STREETS;
}
printf("Scenario set up.\n");
printf("Copying data to GPU...\n");
float *v_d_Actor_progress;
int *v_d_Actor_street;
float *v_d_Car_max_velocity;
float *v_d_Street_length;
float *v_d_Street_max_velocity;
int *v_d_Street_neighbors;
int *v_d_Array_Street_size;
int *v_d_Array_Street_offset;
int *v_d_Array_Street_arrays;
int *v_d_input_actor_tag;
int *v_d_input_actor_id;
int *v_d_jobs;
int *v_d_randomn;
CudaSafeCall(hipMalloc((void**) &v_d_Actor_progress, sizeof(float) * (NUM_PEDS + NUM_CARS)));
CudaSafeCall(hipMalloc((void**) &v_d_Actor_street, sizeof(int) * (NUM_PEDS + NUM_CARS)));
CudaSafeCall(hipMalloc((void**) &v_d_Car_max_velocity, sizeof(float) * (NUM_PEDS + NUM_CARS)));
CudaSafeCall(hipMalloc((void**) &v_d_Street_length, sizeof(float) * NUM_STREETS));
CudaSafeCall(hipMalloc((void**) &v_d_Street_max_velocity, sizeof(float) * NUM_STREETS));
CudaSafeCall(hipMalloc((void**) &v_d_Street_neighbors, sizeof(int) * NUM_STREETS));
CudaSafeCall(hipMalloc((void**) &v_d_Array_Street_size, sizeof(int) * NUM_STREETS));
CudaSafeCall(hipMalloc((void**) &v_d_Array_Street_offset, sizeof(int) * NUM_STREETS));
CudaSafeCall(hipMalloc((void**) &v_d_Array_Street_arrays, sizeof(int) * num_connections));
CudaSafeCall(hipMalloc((void**) &v_d_input_actor_tag, sizeof(int) * (NUM_PEDS + NUM_CARS)));
CudaSafeCall(hipMalloc((void**) &v_d_input_actor_id, sizeof(int) * (NUM_PEDS + NUM_CARS)));
CudaSafeCall(hipMalloc((void**) &v_d_jobs, sizeof(int) * (NUM_PEDS + NUM_CARS)));
CudaSafeCall(hipMalloc((void**) &v_d_randomn, sizeof(int) * NUM_STREETS));
CudaSafeCall(hipMemcpy(v_d_Actor_progress, &Actor_progress[0], sizeof(float) * (NUM_PEDS + NUM_CARS), hipMemcpyHostToDevice));
CudaSafeCall(hipMemcpy(v_d_Actor_street, &Actor_street[0], sizeof(int) * (NUM_PEDS + NUM_CARS), hipMemcpyHostToDevice));
CudaSafeCall(hipMemcpy(v_d_Car_max_velocity, &Car_max_velocity[0], sizeof(float) * (NUM_PEDS + NUM_CARS), hipMemcpyHostToDevice));
CudaSafeCall(hipMemcpy(v_d_Street_length, &Street_length[0], sizeof(float) * NUM_STREETS, hipMemcpyHostToDevice));
CudaSafeCall(hipMemcpy(v_d_Street_max_velocity, &Street_max_velocity[0], sizeof(float) * NUM_STREETS, hipMemcpyHostToDevice));
CudaSafeCall(hipMemcpy(v_d_Street_neighbors, &Street_neighbors[0], sizeof(int) * NUM_STREETS, hipMemcpyHostToDevice));
CudaSafeCall(hipMemcpy(v_d_Array_Street_size, &Array_Street_size[0], sizeof(int) * NUM_STREETS, hipMemcpyHostToDevice));
CudaSafeCall(hipMemcpy(v_d_Array_Street_offset, &Array_Street_offset[0], sizeof(int) * NUM_STREETS, hipMemcpyHostToDevice));
CudaSafeCall(hipMemcpy(v_d_Array_Street_arrays, &Array_Street_arrays[0], sizeof(int) * num_connections, hipMemcpyHostToDevice));
CudaSafeCall(hipMemcpy(v_d_input_actor_tag, &Actor_tag[0], sizeof(int) * (NUM_PEDS + NUM_CARS), hipMemcpyHostToDevice));
CudaSafeCall(hipMemcpy(v_d_input_actor_id, &Actor_id[0], sizeof(int) * (NUM_PEDS + NUM_CARS), hipMemcpyHostToDevice));
CudaSafeCall(hipMemcpy(v_d_jobs, &jobs[0], sizeof(int) * (NUM_PEDS + NUM_CARS), hipMemcpyHostToDevice));
CudaSafeCall(hipMemcpy(v_d_randomn, &randomn[0], sizeof(int) * NUM_STREETS, hipMemcpyHostToDevice));
printf("Finished copying data.\n");
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
printf("Launching kernel...\n");
hipEventRecord(start);
kernel<<<dim3(32), dim3((NUM_PEDS + NUM_CARS) / 32)>>>(GOOD_WEATHER, 1000000,
v_d_Actor_progress, v_d_Actor_street, v_d_Car_max_velocity, v_d_Street_length, v_d_Street_max_velocity,
v_d_Street_neighbors, v_d_Array_Street_size, v_d_Array_Street_offset, v_d_Array_Street_arrays, v_d_input_actor_tag,
v_d_input_actor_id, v_d_jobs, v_d_randomn);
CudaCheckError();
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
CudaCheckError();
printf("Kernel finished.\n");
hipMemcpy(Actor_progress, v_d_Actor_progress, sizeof(float) * (NUM_PEDS + NUM_CARS), hipMemcpyDeviceToHost);
for (int i = 0; i < NUM_PEDS + NUM_CARS; i++)
{
// printf(" %f ", Actor_progress[i]);
}
hipMemcpy(Actor_street, v_d_Actor_street, sizeof(int) * (NUM_PEDS + NUM_CARS), hipMemcpyDeviceToHost);
for (int i = 0; i < NUM_PEDS + NUM_CARS; i++)
{
// printf(" %i ", Actor_street[i]);
}
printf("\n\n\nElapsed time millis: %f\n", milliseconds);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #define REORDER 1
#define GOOD_WEATHER 0
#define BAD_WEATHER 1
#define TAG_Car 0
#define TAG_Pedestrian 1
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
//#include <random>
//#include <array>
#include <algorithm>
#define NUM_CARS 4096
#define NUM_PEDS 16384
#define NUM_STREETS 500
#define MAX_CONNECTIONS 10
#define MAX_LEN 25
using namespace std;
// Define this to turn on error checking
#define CUDA_ERROR_CHECK
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CudaCheckError() __cudaCheckError( __FILE__, __LINE__ )
inline void __cudaSafeCall( hipError_t err, const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
if ( hipSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
hipError_t err = hipGetLastError();
if ( hipSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment away if needed.
err = hipDeviceSynchronize();
if( hipSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
__device__ float *d_Actor_progress;
__device__ int *d_Actor_street;
__device__ float *d_Car_max_velocity;
__device__ float *d_Street_length;
__device__ float *d_Street_max_velocity;
__device__ int *d_Street_neighbors;
__device__ int *d_Array_Street_size;
__device__ int *d_Array_Street_offset;
__device__ int *d_Array_Street_arrays;
__device__ int *d_input_actor_tag;
__device__ int *d_input_actor_id;
__device__ int *d_jobs;
__device__ int *d_randomn;
__device__ void method_Car_move(int actor_id, int weather)
{
float weather_multiplier;
if (weather == GOOD_WEATHER)
{
weather_multiplier = 1.0;
}
else if (weather == BAD_WEATHER)
{
weather_multiplier = 0.75;
}
float speed = min(d_Car_max_velocity[actor_id], d_Street_max_velocity[d_Actor_street[actor_id]]) * weather_multiplier;
d_Actor_progress[actor_id] = d_Actor_progress[actor_id] + (speed / 60.0); /* 1 tick = 1 minute */
if (d_Actor_progress[actor_id] >= d_Street_length[d_Actor_street[actor_id]])
{
// move to different street
int array_id = d_Street_neighbors[d_Actor_street[actor_id]];
int neighbor_index = d_randomn[d_Actor_street[actor_id]] % d_Array_Street_size[array_id];
d_Actor_street[actor_id] = d_Array_Street_arrays[d_Array_Street_offset[array_id] + neighbor_index];
d_Actor_progress[actor_id] = 0.0f;
}
}
__device__ void method_Pedestrian_move(int actor_id, int weather)
{
float speed = d_randomn[((int) (d_Actor_progress[actor_id]*d_Actor_progress[actor_id])) % NUM_STREETS] % 7 - 2;
d_Actor_progress[actor_id] = d_Actor_progress[actor_id] + (speed / 60.0);
if (d_Actor_progress[actor_id] >= d_Street_length[d_Actor_street[actor_id]])
{
// move to different street
int array_id = d_Street_neighbors[d_Actor_street[actor_id]];
int neighbor_index = d_randomn[d_Actor_street[actor_id]] % d_Array_Street_size[array_id];
d_Actor_street[actor_id] = d_Array_Street_arrays[d_Array_Street_offset[array_id] + neighbor_index];
d_Actor_progress[actor_id] = 0.0f;
}
}
__device__ void block(int actor_tag, int actor_id, int weather, int ticks)
{
for (int i = 0; i < ticks; i++)
{
switch (actor_tag)
{
case TAG_Car:
method_Car_move(actor_id, weather);
break;
case TAG_Pedestrian:
method_Pedestrian_move(actor_id, weather);
break;
}
}
}
__global__ void kernel(int weather, int ticks,
float *v_d_Actor_progress, int *v_d_Actor_street, float *v_d_Car_max_velocity,
float *v_d_Street_length, float *v_d_Street_max_velocity, int *v_d_Street_neighbors,
int *v_d_Array_Street_size, int *v_d_Array_Street_offset, int *v_d_Array_Street_arrays,
int *v_d_input_actor_tag, int *v_d_input_actor_id, int *v_d_jobs, int *v_d_randomn)
{
d_Actor_progress = v_d_Actor_progress;
d_Actor_street = v_d_Actor_street;
d_Car_max_velocity = v_d_Car_max_velocity;
d_Street_length = v_d_Street_length;
d_Street_max_velocity = v_d_Street_max_velocity;
d_Street_neighbors = v_d_Street_neighbors;
d_Array_Street_size = v_d_Array_Street_size;
d_Array_Street_offset = v_d_Array_Street_offset;
d_Array_Street_arrays = v_d_Array_Street_arrays;
d_input_actor_tag = v_d_input_actor_tag;
d_input_actor_id = v_d_input_actor_id;
d_jobs = v_d_jobs;
d_randomn = v_d_randomn;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
__syncthreads();
#if (REORDER)
block(d_input_actor_tag[d_jobs[tid]], d_input_actor_id[d_jobs[tid]], weather, ticks);
#else
block(d_input_actor_tag[tid], d_input_actor_id[tid], weather, ticks);
#endif
}
int main()
{
printf("Setting up scenario...\n");
srand(42);
// streets
float *Street_length = new float[NUM_STREETS];
float *Street_max_velocity = new float[NUM_STREETS];
int *Street_neighbors = new int[NUM_STREETS];
for (int i = 0; i < NUM_STREETS; i++)
{
Street_length[i] = rand() % MAX_LEN + 1;
Street_max_velocity[i] = rand() % 40 + 45; /* speed between 45 and 105 */
Street_neighbors[i] = i;
}
// neighbors
int *Array_Street_offset = new int[NUM_STREETS];
int *Array_Street_size = new int[NUM_STREETS];
int num_connections = 0;
for (int i = 0; i < NUM_STREETS; i++)
{
Array_Street_offset[i] = num_connections;
int connections = rand() % MAX_CONNECTIONS + 1;
Array_Street_size[i] = connections;
num_connections += connections;
}
int *Array_Street_arrays = new int[num_connections];
for (int i = 0; i < num_connections; i++)
{
Array_Street_arrays[i] = rand() % NUM_STREETS;
}
// actors
int *Actor_street = new int[NUM_PEDS + NUM_CARS];
float *Actor_progress = new float[NUM_PEDS + NUM_CARS];
float *Car_max_velocity = new float[NUM_CARS + NUM_PEDS];
int *Actor_tag = new int[NUM_PEDS + NUM_CARS];
int *Actor_id = new int[NUM_PEDS + NUM_CARS];
for (int i = 0; i < NUM_PEDS + NUM_CARS; i++)
{
Actor_street[i] = rand() % NUM_STREETS;
Actor_progress[i] = rand() % 10;
Car_max_velocity[i] = rand() % 20 + 65;
}
for (int i = 0; i < NUM_PEDS; i++)
{
Actor_tag[i] = TAG_Pedestrian;
Actor_id[i] = i;
}
for (int i = NUM_PEDS; i < NUM_PEDS + NUM_CARS; i++)
{
Actor_tag[i] = TAG_Car;
Actor_id[i] = i;
}
std::srand(42);
#if !(REORDER)
random_shuffle(Actor_tag, Actor_tag + NUM_CARS + NUM_PEDS);
#endif
// jobs (dummy)
int *jobs = new int[NUM_PEDS + NUM_CARS];
for (int i = 0; i < NUM_CARS + NUM_PEDS; i++)
{
jobs[i] = i;
}
// random numbers
int *randomn = new int[NUM_STREETS];
for (int i = 0; i < NUM_STREETS; i++)
{
randomn[i] = rand() % NUM_STREETS;
}
printf("Scenario set up.\n");
printf("Copying data to GPU...\n");
float *v_d_Actor_progress;
int *v_d_Actor_street;
float *v_d_Car_max_velocity;
float *v_d_Street_length;
float *v_d_Street_max_velocity;
int *v_d_Street_neighbors;
int *v_d_Array_Street_size;
int *v_d_Array_Street_offset;
int *v_d_Array_Street_arrays;
int *v_d_input_actor_tag;
int *v_d_input_actor_id;
int *v_d_jobs;
int *v_d_randomn;
CudaSafeCall(hipMalloc((void**) &v_d_Actor_progress, sizeof(float) * (NUM_PEDS + NUM_CARS)));
CudaSafeCall(hipMalloc((void**) &v_d_Actor_street, sizeof(int) * (NUM_PEDS + NUM_CARS)));
CudaSafeCall(hipMalloc((void**) &v_d_Car_max_velocity, sizeof(float) * (NUM_PEDS + NUM_CARS)));
CudaSafeCall(hipMalloc((void**) &v_d_Street_length, sizeof(float) * NUM_STREETS));
CudaSafeCall(hipMalloc((void**) &v_d_Street_max_velocity, sizeof(float) * NUM_STREETS));
CudaSafeCall(hipMalloc((void**) &v_d_Street_neighbors, sizeof(int) * NUM_STREETS));
CudaSafeCall(hipMalloc((void**) &v_d_Array_Street_size, sizeof(int) * NUM_STREETS));
CudaSafeCall(hipMalloc((void**) &v_d_Array_Street_offset, sizeof(int) * NUM_STREETS));
CudaSafeCall(hipMalloc((void**) &v_d_Array_Street_arrays, sizeof(int) * num_connections));
CudaSafeCall(hipMalloc((void**) &v_d_input_actor_tag, sizeof(int) * (NUM_PEDS + NUM_CARS)));
CudaSafeCall(hipMalloc((void**) &v_d_input_actor_id, sizeof(int) * (NUM_PEDS + NUM_CARS)));
CudaSafeCall(hipMalloc((void**) &v_d_jobs, sizeof(int) * (NUM_PEDS + NUM_CARS)));
CudaSafeCall(hipMalloc((void**) &v_d_randomn, sizeof(int) * NUM_STREETS));
CudaSafeCall(hipMemcpy(v_d_Actor_progress, &Actor_progress[0], sizeof(float) * (NUM_PEDS + NUM_CARS), hipMemcpyHostToDevice));
CudaSafeCall(hipMemcpy(v_d_Actor_street, &Actor_street[0], sizeof(int) * (NUM_PEDS + NUM_CARS), hipMemcpyHostToDevice));
CudaSafeCall(hipMemcpy(v_d_Car_max_velocity, &Car_max_velocity[0], sizeof(float) * (NUM_PEDS + NUM_CARS), hipMemcpyHostToDevice));
CudaSafeCall(hipMemcpy(v_d_Street_length, &Street_length[0], sizeof(float) * NUM_STREETS, hipMemcpyHostToDevice));
CudaSafeCall(hipMemcpy(v_d_Street_max_velocity, &Street_max_velocity[0], sizeof(float) * NUM_STREETS, hipMemcpyHostToDevice));
CudaSafeCall(hipMemcpy(v_d_Street_neighbors, &Street_neighbors[0], sizeof(int) * NUM_STREETS, hipMemcpyHostToDevice));
CudaSafeCall(hipMemcpy(v_d_Array_Street_size, &Array_Street_size[0], sizeof(int) * NUM_STREETS, hipMemcpyHostToDevice));
CudaSafeCall(hipMemcpy(v_d_Array_Street_offset, &Array_Street_offset[0], sizeof(int) * NUM_STREETS, hipMemcpyHostToDevice));
CudaSafeCall(hipMemcpy(v_d_Array_Street_arrays, &Array_Street_arrays[0], sizeof(int) * num_connections, hipMemcpyHostToDevice));
CudaSafeCall(hipMemcpy(v_d_input_actor_tag, &Actor_tag[0], sizeof(int) * (NUM_PEDS + NUM_CARS), hipMemcpyHostToDevice));
CudaSafeCall(hipMemcpy(v_d_input_actor_id, &Actor_id[0], sizeof(int) * (NUM_PEDS + NUM_CARS), hipMemcpyHostToDevice));
CudaSafeCall(hipMemcpy(v_d_jobs, &jobs[0], sizeof(int) * (NUM_PEDS + NUM_CARS), hipMemcpyHostToDevice));
CudaSafeCall(hipMemcpy(v_d_randomn, &randomn[0], sizeof(int) * NUM_STREETS, hipMemcpyHostToDevice));
printf("Finished copying data.\n");
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
printf("Launching kernel...\n");
hipEventRecord(start);
kernel<<<dim3(32), dim3((NUM_PEDS + NUM_CARS) / 32)>>>(GOOD_WEATHER, 1000000,
v_d_Actor_progress, v_d_Actor_street, v_d_Car_max_velocity, v_d_Street_length, v_d_Street_max_velocity,
v_d_Street_neighbors, v_d_Array_Street_size, v_d_Array_Street_offset, v_d_Array_Street_arrays, v_d_input_actor_tag,
v_d_input_actor_id, v_d_jobs, v_d_randomn);
CudaCheckError();
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
CudaCheckError();
printf("Kernel finished.\n");
hipMemcpy(Actor_progress, v_d_Actor_progress, sizeof(float) * (NUM_PEDS + NUM_CARS), hipMemcpyDeviceToHost);
for (int i = 0; i < NUM_PEDS + NUM_CARS; i++)
{
// printf(" %f ", Actor_progress[i]);
}
hipMemcpy(Actor_street, v_d_Actor_street, sizeof(int) * (NUM_PEDS + NUM_CARS), hipMemcpyDeviceToHost);
for (int i = 0; i < NUM_PEDS + NUM_CARS; i++)
{
// printf(" %i ", Actor_street[i]);
}
printf("\n\n\nElapsed time millis: %f\n", milliseconds);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_
.globl _Z6kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_
.p2align 8
.type _Z6kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_,@function
_Z6kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_:
s_clause 0x4
s_load_b256 s[4:11], s[0:1], 0x8
s_load_b256 s[16:23], s[0:1], 0x28
s_load_b256 s[40:47], s[0:1], 0x48
s_load_b32 s14, s[0:1], 0x4
s_load_b64 s[38:39], s[0:1], 0x68
s_getpc_b64 s[36:37]
s_add_u32 s36, s36, d_Actor_progress@rel32@lo+4
s_addc_u32 s37, s37, d_Actor_progress@rel32@hi+12
s_getpc_b64 s[30:31]
s_add_u32 s30, s30, d_Actor_street@rel32@lo+4
s_addc_u32 s31, s31, d_Actor_street@rel32@hi+12
s_getpc_b64 s[12:13]
s_add_u32 s12, s12, d_Car_max_velocity@rel32@lo+4
s_addc_u32 s13, s13, d_Car_max_velocity@rel32@hi+12
v_mov_b32_e32 v22, 0
s_getpc_b64 s[26:27]
s_add_u32 s26, s26, d_Street_length@rel32@lo+4
s_addc_u32 s27, s27, d_Street_length@rel32@hi+12
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, d_Street_max_velocity@rel32@lo+4
s_addc_u32 s3, s3, d_Street_max_velocity@rel32@hi+12
s_getpc_b64 s[24:25]
s_add_u32 s24, s24, d_Street_neighbors@rel32@lo+4
s_addc_u32 s25, s25, d_Street_neighbors@rel32@hi+12
s_getpc_b64 s[28:29]
s_add_u32 s28, s28, d_Array_Street_size@rel32@lo+4
s_addc_u32 s29, s29, d_Array_Street_size@rel32@hi+12
s_getpc_b64 s[34:35]
s_add_u32 s34, s34, d_Array_Street_offset@rel32@lo+4
s_addc_u32 s35, s35, d_Array_Street_offset@rel32@hi+12
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v1, s4 :: v_dual_mov_b32 v2, s5
v_dual_mov_b32 v3, s6 :: v_dual_mov_b32 v4, s7
v_dual_mov_b32 v5, s8 :: v_dual_mov_b32 v6, s9
v_dual_mov_b32 v7, s10 :: v_dual_mov_b32 v8, s11
v_dual_mov_b32 v9, s16 :: v_dual_mov_b32 v10, s17
v_mov_b32_e32 v11, s18
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, d_Array_Street_arrays@rel32@lo+4
s_addc_u32 s5, s5, d_Array_Street_arrays@rel32@hi+12
v_dual_mov_b32 v12, s19 :: v_dual_mov_b32 v13, s20
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, d_input_actor_tag@rel32@lo+4
s_addc_u32 s9, s9, d_input_actor_tag@rel32@hi+12
v_dual_mov_b32 v14, s21 :: v_dual_mov_b32 v15, s22
s_getpc_b64 s[10:11]
s_add_u32 s10, s10, d_input_actor_id@rel32@lo+4
s_addc_u32 s11, s11, d_input_actor_id@rel32@hi+12
v_mov_b32_e32 v16, s23
s_clause 0x7
global_store_b64 v22, v[1:2], s[36:37]
global_store_b64 v22, v[3:4], s[30:31]
global_store_b64 v22, v[5:6], s[12:13]
global_store_b64 v22, v[7:8], s[26:27]
global_store_b64 v22, v[9:10], s[2:3]
global_store_b64 v22, v[11:12], s[24:25]
global_store_b64 v22, v[13:14], s[28:29]
global_store_b64 v22, v[15:16], s[34:35]
v_mov_b32_e32 v1, s40
s_getpc_b64 s[16:17]
s_add_u32 s16, s16, d_jobs@rel32@lo+4
s_addc_u32 s17, s17, d_jobs@rel32@hi+12
v_dual_mov_b32 v2, s41 :: v_dual_mov_b32 v3, s42
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, d_randomn@rel32@lo+4
s_addc_u32 s7, s7, d_randomn@rel32@hi+12
v_dual_mov_b32 v4, s43 :: v_dual_mov_b32 v5, s44
s_add_u32 s18, s0, 0x70
v_dual_mov_b32 v6, s45 :: v_dual_mov_b32 v7, s46
s_addc_u32 s19, s1, 0
v_dual_mov_b32 v8, s47 :: v_dual_mov_b32 v9, s38
s_cmp_lt_i32 s14, 1
v_mov_b32_e32 v10, s39
s_clause 0x4
global_store_b64 v22, v[1:2], s[4:5]
global_store_b64 v22, v[3:4], s[8:9]
global_store_b64 v22, v[5:6], s[10:11]
global_store_b64 v22, v[7:8], s[16:17]
global_store_b64 v22, v[9:10], s[6:7]
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_13
s_clause 0x1
global_load_b64 v[1:2], v22, s[16:17]
global_load_b64 v[5:6], v22, s[10:11]
s_load_b32 s16, s[18:19], 0xc
s_load_b32 s0, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s16, s16, 0xffff
s_cmp_eq_u32 s0, 1
s_cselect_b32 s0, -1, 0
s_waitcnt vmcnt(1)
v_mad_u64_u32 v[3:4], null, s15, s16, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v1, v3
v_add_co_ci_u32_e32 v1, vcc_lo, v2, v4, vcc_lo
flat_load_b32 v0, v[0:1]
global_load_b64 v[7:8], v22, s[8:9]
s_waitcnt vmcnt(1) lgkmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, v5, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, v6, v10, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v23, vcc_lo, v7, v9
v_add_co_ci_u32_e32 v24, vcc_lo, v8, v10, vcc_lo
flat_load_b32 v14, v[0:1]
s_clause 0x9
global_load_b64 v[16:17], v22, s[36:37]
global_load_b64 v[0:1], v22, s[6:7]
global_load_b64 v[18:19], v22, s[30:31]
global_load_b64 v[2:3], v22, s[4:5]
global_load_b64 v[4:5], v22, s[26:27]
global_load_b64 v[20:21], v22, s[12:13]
global_load_b64 v[6:7], v22, s[28:29]
global_load_b64 v[8:9], v22, s[34:35]
global_load_b64 v[10:11], v22, s[24:25]
global_load_b64 v[12:13], v22, s[2:3]
flat_load_b32 v23, v[23:24]
v_cndmask_b32_e64 v24, 1.0, 0x3f400000, s0
s_waitcnt vmcnt(11) lgkmcnt(1)
v_ashrrev_i32_e32 v15, 31, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[25:26], 2, v[14:15]
s_waitcnt vmcnt(10)
v_add_co_u32 v14, vcc_lo, v16, v25
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v15, vcc_lo, v17, v26, vcc_lo
s_waitcnt vmcnt(8)
v_add_co_u32 v16, vcc_lo, v18, v25
v_add_co_ci_u32_e32 v17, vcc_lo, v19, v26, vcc_lo
s_waitcnt vmcnt(5)
v_add_co_u32 v18, vcc_lo, v20, v25
v_add_co_ci_u32_e32 v19, vcc_lo, v21, v26, vcc_lo
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
s_add_i32 s14, s14, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s14, 0
s_cbranch_scc0 .LBB0_13
.LBB0_3:
s_mov_b32 s1, 0
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmpx_lt_i32_e32 0, v23
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_7
s_mov_b32 s2, 0
s_mov_b32 s1, exec_lo
v_cmpx_eq_u32_e32 1, v23
s_cbranch_execz .LBB0_6
flat_load_b32 v35, v[14:15]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mul_f32_e32 v20, v35, v35
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f32_e32 v20, v20
v_mul_hi_i32 v21, v20, 0x10624dd3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v25, 31, v21
v_ashrrev_i32_e32 v21, 5, v21
v_add_nc_u32_e32 v21, v21, v25
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v21, v21, 0x1f4
v_sub_nc_u32_e32 v20, v20, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v21, 31, v20
v_lshlrev_b64 v[20:21], 2, v[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v20, vcc_lo, v0, v20
v_add_co_ci_u32_e32 v21, vcc_lo, v1, v21, vcc_lo
flat_load_b32 v20, v[20:21]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mul_hi_i32 v21, v20, 0x92492493
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v21, v21, v20
v_lshrrev_b32_e32 v25, 31, v21
v_ashrrev_i32_e32 v21, 2, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v21, v21, v25
v_mul_lo_u32 v21, v21, 7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v20, v20, v21
v_add_nc_u32_e32 v20, -2, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v20, v20
v_cvt_f64_f32_e32 v[25:26], v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[27:28], null, 0x404e0000, 0x404e0000, v[25:26]
v_rcp_f64_e32 v[20:21], v[27:28]
s_waitcnt_depctr 0xfff
v_fma_f64 v[29:30], -v[27:28], v[20:21], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_fma_f64 v[29:30], v[20:21], v[29:30], v[20:21]
flat_load_b32 v20, v[16:17]
v_fma_f64 v[31:32], -v[27:28], v[29:30], 1.0
v_fma_f64 v[29:30], v[29:30], v[31:32], v[29:30]
v_div_scale_f64 v[31:32], vcc_lo, v[25:26], 0x404e0000, v[25:26]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[33:34], v[31:32], v[29:30]
v_fma_f64 v[27:28], -v[27:28], v[33:34], v[31:32]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[27:28], v[27:28], v[29:30], v[33:34]
v_cvt_f64_f32_e32 v[29:30], v35
v_div_fixup_f64 v[25:26], v[27:28], 0x404e0000, v[25:26]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[25:26], v[25:26], v[29:30]
v_cvt_f32_f64_e32 v27, v[25:26]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_ashrrev_i32_e32 v21, 31, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[25:26], 2, v[20:21]
v_add_co_u32 v25, vcc_lo, v4, v25
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v26, vcc_lo, v5, v26, vcc_lo
flat_store_b32 v[14:15], v27
flat_load_b32 v25, v[25:26]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_le_f32_e32 vcc_lo, v25, v27
s_and_b32 s2, vcc_lo, exec_lo
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s1, s2, exec_lo
.LBB0_7:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_11
s_mov_b32 s3, s1
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v23
s_cbranch_execz .LBB0_10
flat_load_b32 v20, v[16:17]
s_and_not1_b32 s3, s1, exec_lo
s_waitcnt vmcnt(0) lgkmcnt(0)
v_ashrrev_i32_e32 v21, 31, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[25:26], 2, v[20:21]
v_add_co_u32 v27, vcc_lo, v12, v25
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v28, vcc_lo, v13, v26, vcc_lo
flat_load_b32 v29, v[18:19]
flat_load_b32 v27, v[27:28]
flat_load_b32 v37, v[14:15]
s_waitcnt vmcnt(1) lgkmcnt(1)
v_dual_max_f32 v28, v29, v29 :: v_dual_max_f32 v27, v27, v27
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_f32_e32 v27, v28, v27
v_mul_f32_e32 v27, v24, v27
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[27:28], v27
v_div_scale_f64 v[29:30], null, 0x404e0000, 0x404e0000, v[27:28]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[31:32], v[29:30]
s_waitcnt_depctr 0xfff
v_fma_f64 v[33:34], -v[29:30], v[31:32], 1.0
v_fma_f64 v[31:32], v[31:32], v[33:34], v[31:32]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[33:34], -v[29:30], v[31:32], 1.0
v_fma_f64 v[31:32], v[31:32], v[33:34], v[31:32]
v_div_scale_f64 v[33:34], vcc_lo, v[27:28], 0x404e0000, v[27:28]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[35:36], v[33:34], v[31:32]
v_fma_f64 v[29:30], -v[29:30], v[35:36], v[33:34]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_div_fmas_f64 v[29:30], v[29:30], v[31:32], v[35:36]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cvt_f64_f32_e32 v[31:32], v37
v_add_co_u32 v25, vcc_lo, v4, v25
v_add_co_ci_u32_e32 v26, vcc_lo, v5, v26, vcc_lo
v_div_fixup_f64 v[27:28], v[29:30], 0x404e0000, v[27:28]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[27:28], v[27:28], v[31:32]
v_cvt_f32_f64_e32 v27, v[27:28]
flat_store_b32 v[14:15], v27
flat_load_b32 v25, v[25:26]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_le_f32_e32 vcc_lo, v25, v27
s_and_b32 s4, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s3, s3, s4
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s1, s1, exec_lo
s_and_b32 s2, s3, exec_lo
s_or_b32 s1, s1, s2
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s0
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_2
v_lshlrev_b64 v[20:21], 2, v[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v25, vcc_lo, v10, v20
v_add_co_ci_u32_e32 v26, vcc_lo, v11, v21, vcc_lo
flat_load_b32 v25, v[25:26]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_ashrrev_i32_e32 v26, 31, v25
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[25:26], 2, v[25:26]
v_add_co_u32 v27, vcc_lo, v6, v25
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v28, vcc_lo, v7, v26, vcc_lo
v_add_co_u32 v20, vcc_lo, v0, v20
v_add_co_ci_u32_e32 v21, vcc_lo, v1, v21, vcc_lo
flat_load_b32 v27, v[27:28]
flat_load_b32 v28, v[20:21]
v_add_co_u32 v20, vcc_lo, v8, v25
v_add_co_ci_u32_e32 v21, vcc_lo, v9, v26, vcc_lo
flat_load_b32 v20, v[20:21]
s_waitcnt vmcnt(2) lgkmcnt(2)
v_ashrrev_i32_e32 v21, 31, v27
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v25, v27, v21
s_waitcnt vmcnt(1) lgkmcnt(1)
v_ashrrev_i32_e32 v27, 31, v28
v_xor_b32_e32 v21, v25, v21
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v28, v28, v27
v_cvt_f32_u32_e32 v25, v21
v_sub_nc_u32_e32 v26, 0, v21
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v28, v28, v27
v_rcp_iflag_f32_e32 v25, v25
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v25, 0x4f7ffffe, v25
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v25, v25
v_mul_lo_u32 v26, v26, v25
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v26, v25, v26
v_add_nc_u32_e32 v25, v25, v26
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v25, v28, v25
v_mul_lo_u32 v25, v25, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v25, v28, v25
v_sub_nc_u32_e32 v26, v25, v21
v_cmp_ge_u32_e32 vcc_lo, v25, v21
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v25, v25, v26, vcc_lo
v_sub_nc_u32_e32 v26, v25, v21
v_cmp_ge_u32_e32 vcc_lo, v25, v21
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v21, v25, v26, vcc_lo
v_xor_b32_e32 v21, v21, v27
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v21, v21, v27
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v20, v20, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v21, 31, v20
v_lshlrev_b64 v[20:21], 2, v[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v20, vcc_lo, v2, v20
v_add_co_ci_u32_e32 v21, vcc_lo, v3, v21, vcc_lo
flat_load_b32 v20, v[20:21]
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_store_b32 v[16:17], v20
flat_store_b32 v[14:15], v22
s_branch .LBB0_2
.LBB0_13:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 368
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 38
.amdhsa_next_free_sgpr 48
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_, .Lfunc_end0-_Z6kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected d_Actor_progress
.type d_Actor_progress,@object
.section .bss,"aw",@nobits
.globl d_Actor_progress
.p2align 3, 0x0
d_Actor_progress:
.quad 0
.size d_Actor_progress, 8
.protected d_Actor_street
.type d_Actor_street,@object
.globl d_Actor_street
.p2align 3, 0x0
d_Actor_street:
.quad 0
.size d_Actor_street, 8
.protected d_Car_max_velocity
.type d_Car_max_velocity,@object
.globl d_Car_max_velocity
.p2align 3, 0x0
d_Car_max_velocity:
.quad 0
.size d_Car_max_velocity, 8
.protected d_Street_length
.type d_Street_length,@object
.globl d_Street_length
.p2align 3, 0x0
d_Street_length:
.quad 0
.size d_Street_length, 8
.protected d_Street_max_velocity
.type d_Street_max_velocity,@object
.globl d_Street_max_velocity
.p2align 3, 0x0
d_Street_max_velocity:
.quad 0
.size d_Street_max_velocity, 8
.protected d_Street_neighbors
.type d_Street_neighbors,@object
.globl d_Street_neighbors
.p2align 3, 0x0
d_Street_neighbors:
.quad 0
.size d_Street_neighbors, 8
.protected d_Array_Street_size
.type d_Array_Street_size,@object
.globl d_Array_Street_size
.p2align 3, 0x0
d_Array_Street_size:
.quad 0
.size d_Array_Street_size, 8
.protected d_Array_Street_offset
.type d_Array_Street_offset,@object
.globl d_Array_Street_offset
.p2align 3, 0x0
d_Array_Street_offset:
.quad 0
.size d_Array_Street_offset, 8
.protected d_Array_Street_arrays
.type d_Array_Street_arrays,@object
.globl d_Array_Street_arrays
.p2align 3, 0x0
d_Array_Street_arrays:
.quad 0
.size d_Array_Street_arrays, 8
.protected d_input_actor_tag
.type d_input_actor_tag,@object
.globl d_input_actor_tag
.p2align 3, 0x0
d_input_actor_tag:
.quad 0
.size d_input_actor_tag, 8
.protected d_input_actor_id
.type d_input_actor_id,@object
.globl d_input_actor_id
.p2align 3, 0x0
d_input_actor_id:
.quad 0
.size d_input_actor_id, 8
.protected d_jobs
.type d_jobs,@object
.globl d_jobs
.p2align 3, 0x0
d_jobs:
.quad 0
.size d_jobs, 8
.protected d_randomn
.type d_randomn,@object
.globl d_randomn
.p2align 3, 0x0
d_randomn:
.quad 0
.size d_randomn, 8
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym d_Actor_progress
.addrsig_sym d_Actor_street
.addrsig_sym d_Car_max_velocity
.addrsig_sym d_Street_length
.addrsig_sym d_Street_max_velocity
.addrsig_sym d_Street_neighbors
.addrsig_sym d_Array_Street_size
.addrsig_sym d_Array_Street_offset
.addrsig_sym d_Array_Street_arrays
.addrsig_sym d_input_actor_tag
.addrsig_sym d_input_actor_id
.addrsig_sym d_jobs
.addrsig_sym d_randomn
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 80
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 88
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 96
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 104
.size: 8
.value_kind: global_buffer
- .offset: 112
.size: 4
.value_kind: hidden_block_count_x
- .offset: 116
.size: 4
.value_kind: hidden_block_count_y
- .offset: 120
.size: 4
.value_kind: hidden_block_count_z
- .offset: 124
.size: 2
.value_kind: hidden_group_size_x
- .offset: 126
.size: 2
.value_kind: hidden_group_size_y
- .offset: 128
.size: 2
.value_kind: hidden_group_size_z
- .offset: 130
.size: 2
.value_kind: hidden_remainder_x
- .offset: 132
.size: 2
.value_kind: hidden_remainder_y
- .offset: 134
.size: 2
.value_kind: hidden_remainder_z
- .offset: 152
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 160
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 168
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 176
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 368
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_
.private_segment_fixed_size: 0
.sgpr_count: 50
.sgpr_spill_count: 0
.symbol: _Z6kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 38
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #define REORDER 1
#define GOOD_WEATHER 0
#define BAD_WEATHER 1
#define TAG_Car 0
#define TAG_Pedestrian 1
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
//#include <random>
//#include <array>
#include <algorithm>
#define NUM_CARS 4096
#define NUM_PEDS 16384
#define NUM_STREETS 500
#define MAX_CONNECTIONS 10
#define MAX_LEN 25
using namespace std;
// Define this to turn on error checking
#define CUDA_ERROR_CHECK
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CudaCheckError() __cudaCheckError( __FILE__, __LINE__ )
inline void __cudaSafeCall( hipError_t err, const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
if ( hipSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
hipError_t err = hipGetLastError();
if ( hipSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment away if needed.
err = hipDeviceSynchronize();
if( hipSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
__device__ float *d_Actor_progress;
__device__ int *d_Actor_street;
__device__ float *d_Car_max_velocity;
__device__ float *d_Street_length;
__device__ float *d_Street_max_velocity;
__device__ int *d_Street_neighbors;
__device__ int *d_Array_Street_size;
__device__ int *d_Array_Street_offset;
__device__ int *d_Array_Street_arrays;
__device__ int *d_input_actor_tag;
__device__ int *d_input_actor_id;
__device__ int *d_jobs;
__device__ int *d_randomn;
__device__ void method_Car_move(int actor_id, int weather)
{
float weather_multiplier;
if (weather == GOOD_WEATHER)
{
weather_multiplier = 1.0;
}
else if (weather == BAD_WEATHER)
{
weather_multiplier = 0.75;
}
float speed = min(d_Car_max_velocity[actor_id], d_Street_max_velocity[d_Actor_street[actor_id]]) * weather_multiplier;
d_Actor_progress[actor_id] = d_Actor_progress[actor_id] + (speed / 60.0); /* 1 tick = 1 minute */
if (d_Actor_progress[actor_id] >= d_Street_length[d_Actor_street[actor_id]])
{
// move to different street
int array_id = d_Street_neighbors[d_Actor_street[actor_id]];
int neighbor_index = d_randomn[d_Actor_street[actor_id]] % d_Array_Street_size[array_id];
d_Actor_street[actor_id] = d_Array_Street_arrays[d_Array_Street_offset[array_id] + neighbor_index];
d_Actor_progress[actor_id] = 0.0f;
}
}
__device__ void method_Pedestrian_move(int actor_id, int weather)
{
float speed = d_randomn[((int) (d_Actor_progress[actor_id]*d_Actor_progress[actor_id])) % NUM_STREETS] % 7 - 2;
d_Actor_progress[actor_id] = d_Actor_progress[actor_id] + (speed / 60.0);
if (d_Actor_progress[actor_id] >= d_Street_length[d_Actor_street[actor_id]])
{
// move to different street
int array_id = d_Street_neighbors[d_Actor_street[actor_id]];
int neighbor_index = d_randomn[d_Actor_street[actor_id]] % d_Array_Street_size[array_id];
d_Actor_street[actor_id] = d_Array_Street_arrays[d_Array_Street_offset[array_id] + neighbor_index];
d_Actor_progress[actor_id] = 0.0f;
}
}
__device__ void block(int actor_tag, int actor_id, int weather, int ticks)
{
for (int i = 0; i < ticks; i++)
{
switch (actor_tag)
{
case TAG_Car:
method_Car_move(actor_id, weather);
break;
case TAG_Pedestrian:
method_Pedestrian_move(actor_id, weather);
break;
}
}
}
__global__ void kernel(int weather, int ticks,
float *v_d_Actor_progress, int *v_d_Actor_street, float *v_d_Car_max_velocity,
float *v_d_Street_length, float *v_d_Street_max_velocity, int *v_d_Street_neighbors,
int *v_d_Array_Street_size, int *v_d_Array_Street_offset, int *v_d_Array_Street_arrays,
int *v_d_input_actor_tag, int *v_d_input_actor_id, int *v_d_jobs, int *v_d_randomn)
{
d_Actor_progress = v_d_Actor_progress;
d_Actor_street = v_d_Actor_street;
d_Car_max_velocity = v_d_Car_max_velocity;
d_Street_length = v_d_Street_length;
d_Street_max_velocity = v_d_Street_max_velocity;
d_Street_neighbors = v_d_Street_neighbors;
d_Array_Street_size = v_d_Array_Street_size;
d_Array_Street_offset = v_d_Array_Street_offset;
d_Array_Street_arrays = v_d_Array_Street_arrays;
d_input_actor_tag = v_d_input_actor_tag;
d_input_actor_id = v_d_input_actor_id;
d_jobs = v_d_jobs;
d_randomn = v_d_randomn;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
__syncthreads();
#if (REORDER)
block(d_input_actor_tag[d_jobs[tid]], d_input_actor_id[d_jobs[tid]], weather, ticks);
#else
block(d_input_actor_tag[tid], d_input_actor_id[tid], weather, ticks);
#endif
}
int main()
{
printf("Setting up scenario...\n");
srand(42);
// streets
float *Street_length = new float[NUM_STREETS];
float *Street_max_velocity = new float[NUM_STREETS];
int *Street_neighbors = new int[NUM_STREETS];
for (int i = 0; i < NUM_STREETS; i++)
{
Street_length[i] = rand() % MAX_LEN + 1;
Street_max_velocity[i] = rand() % 40 + 45; /* speed between 45 and 105 */
Street_neighbors[i] = i;
}
// neighbors
int *Array_Street_offset = new int[NUM_STREETS];
int *Array_Street_size = new int[NUM_STREETS];
int num_connections = 0;
for (int i = 0; i < NUM_STREETS; i++)
{
Array_Street_offset[i] = num_connections;
int connections = rand() % MAX_CONNECTIONS + 1;
Array_Street_size[i] = connections;
num_connections += connections;
}
int *Array_Street_arrays = new int[num_connections];
for (int i = 0; i < num_connections; i++)
{
Array_Street_arrays[i] = rand() % NUM_STREETS;
}
// actors
int *Actor_street = new int[NUM_PEDS + NUM_CARS];
float *Actor_progress = new float[NUM_PEDS + NUM_CARS];
float *Car_max_velocity = new float[NUM_CARS + NUM_PEDS];
int *Actor_tag = new int[NUM_PEDS + NUM_CARS];
int *Actor_id = new int[NUM_PEDS + NUM_CARS];
for (int i = 0; i < NUM_PEDS + NUM_CARS; i++)
{
Actor_street[i] = rand() % NUM_STREETS;
Actor_progress[i] = rand() % 10;
Car_max_velocity[i] = rand() % 20 + 65;
}
for (int i = 0; i < NUM_PEDS; i++)
{
Actor_tag[i] = TAG_Pedestrian;
Actor_id[i] = i;
}
for (int i = NUM_PEDS; i < NUM_PEDS + NUM_CARS; i++)
{
Actor_tag[i] = TAG_Car;
Actor_id[i] = i;
}
std::srand(42);
#if !(REORDER)
random_shuffle(Actor_tag, Actor_tag + NUM_CARS + NUM_PEDS);
#endif
// jobs (dummy)
int *jobs = new int[NUM_PEDS + NUM_CARS];
for (int i = 0; i < NUM_CARS + NUM_PEDS; i++)
{
jobs[i] = i;
}
// random numbers
int *randomn = new int[NUM_STREETS];
for (int i = 0; i < NUM_STREETS; i++)
{
randomn[i] = rand() % NUM_STREETS;
}
printf("Scenario set up.\n");
printf("Copying data to GPU...\n");
float *v_d_Actor_progress;
int *v_d_Actor_street;
float *v_d_Car_max_velocity;
float *v_d_Street_length;
float *v_d_Street_max_velocity;
int *v_d_Street_neighbors;
int *v_d_Array_Street_size;
int *v_d_Array_Street_offset;
int *v_d_Array_Street_arrays;
int *v_d_input_actor_tag;
int *v_d_input_actor_id;
int *v_d_jobs;
int *v_d_randomn;
CudaSafeCall(hipMalloc((void**) &v_d_Actor_progress, sizeof(float) * (NUM_PEDS + NUM_CARS)));
CudaSafeCall(hipMalloc((void**) &v_d_Actor_street, sizeof(int) * (NUM_PEDS + NUM_CARS)));
CudaSafeCall(hipMalloc((void**) &v_d_Car_max_velocity, sizeof(float) * (NUM_PEDS + NUM_CARS)));
CudaSafeCall(hipMalloc((void**) &v_d_Street_length, sizeof(float) * NUM_STREETS));
CudaSafeCall(hipMalloc((void**) &v_d_Street_max_velocity, sizeof(float) * NUM_STREETS));
CudaSafeCall(hipMalloc((void**) &v_d_Street_neighbors, sizeof(int) * NUM_STREETS));
CudaSafeCall(hipMalloc((void**) &v_d_Array_Street_size, sizeof(int) * NUM_STREETS));
CudaSafeCall(hipMalloc((void**) &v_d_Array_Street_offset, sizeof(int) * NUM_STREETS));
CudaSafeCall(hipMalloc((void**) &v_d_Array_Street_arrays, sizeof(int) * num_connections));
CudaSafeCall(hipMalloc((void**) &v_d_input_actor_tag, sizeof(int) * (NUM_PEDS + NUM_CARS)));
CudaSafeCall(hipMalloc((void**) &v_d_input_actor_id, sizeof(int) * (NUM_PEDS + NUM_CARS)));
CudaSafeCall(hipMalloc((void**) &v_d_jobs, sizeof(int) * (NUM_PEDS + NUM_CARS)));
CudaSafeCall(hipMalloc((void**) &v_d_randomn, sizeof(int) * NUM_STREETS));
CudaSafeCall(hipMemcpy(v_d_Actor_progress, &Actor_progress[0], sizeof(float) * (NUM_PEDS + NUM_CARS), hipMemcpyHostToDevice));
CudaSafeCall(hipMemcpy(v_d_Actor_street, &Actor_street[0], sizeof(int) * (NUM_PEDS + NUM_CARS), hipMemcpyHostToDevice));
CudaSafeCall(hipMemcpy(v_d_Car_max_velocity, &Car_max_velocity[0], sizeof(float) * (NUM_PEDS + NUM_CARS), hipMemcpyHostToDevice));
CudaSafeCall(hipMemcpy(v_d_Street_length, &Street_length[0], sizeof(float) * NUM_STREETS, hipMemcpyHostToDevice));
CudaSafeCall(hipMemcpy(v_d_Street_max_velocity, &Street_max_velocity[0], sizeof(float) * NUM_STREETS, hipMemcpyHostToDevice));
CudaSafeCall(hipMemcpy(v_d_Street_neighbors, &Street_neighbors[0], sizeof(int) * NUM_STREETS, hipMemcpyHostToDevice));
CudaSafeCall(hipMemcpy(v_d_Array_Street_size, &Array_Street_size[0], sizeof(int) * NUM_STREETS, hipMemcpyHostToDevice));
CudaSafeCall(hipMemcpy(v_d_Array_Street_offset, &Array_Street_offset[0], sizeof(int) * NUM_STREETS, hipMemcpyHostToDevice));
CudaSafeCall(hipMemcpy(v_d_Array_Street_arrays, &Array_Street_arrays[0], sizeof(int) * num_connections, hipMemcpyHostToDevice));
CudaSafeCall(hipMemcpy(v_d_input_actor_tag, &Actor_tag[0], sizeof(int) * (NUM_PEDS + NUM_CARS), hipMemcpyHostToDevice));
CudaSafeCall(hipMemcpy(v_d_input_actor_id, &Actor_id[0], sizeof(int) * (NUM_PEDS + NUM_CARS), hipMemcpyHostToDevice));
CudaSafeCall(hipMemcpy(v_d_jobs, &jobs[0], sizeof(int) * (NUM_PEDS + NUM_CARS), hipMemcpyHostToDevice));
CudaSafeCall(hipMemcpy(v_d_randomn, &randomn[0], sizeof(int) * NUM_STREETS, hipMemcpyHostToDevice));
printf("Finished copying data.\n");
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
printf("Launching kernel...\n");
hipEventRecord(start);
kernel<<<dim3(32), dim3((NUM_PEDS + NUM_CARS) / 32)>>>(GOOD_WEATHER, 1000000,
v_d_Actor_progress, v_d_Actor_street, v_d_Car_max_velocity, v_d_Street_length, v_d_Street_max_velocity,
v_d_Street_neighbors, v_d_Array_Street_size, v_d_Array_Street_offset, v_d_Array_Street_arrays, v_d_input_actor_tag,
v_d_input_actor_id, v_d_jobs, v_d_randomn);
CudaCheckError();
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
CudaCheckError();
printf("Kernel finished.\n");
hipMemcpy(Actor_progress, v_d_Actor_progress, sizeof(float) * (NUM_PEDS + NUM_CARS), hipMemcpyDeviceToHost);
for (int i = 0; i < NUM_PEDS + NUM_CARS; i++)
{
// printf(" %f ", Actor_progress[i]);
}
hipMemcpy(Actor_street, v_d_Actor_street, sizeof(int) * (NUM_PEDS + NUM_CARS), hipMemcpyDeviceToHost);
for (int i = 0; i < NUM_PEDS + NUM_CARS; i++)
{
// printf(" %i ", Actor_street[i]);
}
printf("\n\n\nElapsed time millis: %f\n", milliseconds);
} | .text
.file "benchmark_column_reorder.hip"
.globl _Z21__device_stub__kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_ # -- Begin function _Z21__device_stub__kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_
.p2align 4, 0x90
.type _Z21__device_stub__kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_,@function
_Z21__device_stub__kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_: # @_Z21__device_stub__kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 224(%rsp), %rax
movq %rax, 144(%rsp)
leaq 232(%rsp), %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 264(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 280(%rsp), %rax
movq %rax, 200(%rsp)
leaq 288(%rsp), %rax
movq %rax, 208(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size _Z21__device_stub__kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_, .Lfunc_end0-_Z21__device_stub__kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $472, %rsp # imm = 0x1D8
.cfi_def_cfa_offset 528
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.Lstr, %edi
callq puts@PLT
movl $42, %edi
callq srand
movl $2000, %edi # imm = 0x7D0
callq _Znam
movq %rax, %r12
movl $2000, %edi # imm = 0x7D0
callq _Znam
movq %rax, %r15
movl $2000, %edi # imm = 0x7D0
callq _Znam
movq %rax, %r14
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %ecx
leal (%rcx,%rcx,4), %ecx
negl %ecx
addl %ecx, %eax
incl %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r12,%rbx,4)
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $36, %rcx
addl %edx, %ecx
shll $3, %ecx
leal (%rcx,%rcx,4), %ecx
negl %ecx
addl %ecx, %eax
addl $45, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r15,%rbx,4)
movl %ebx, (%r14,%rbx,4)
incq %rbx
cmpq $500, %rbx # imm = 0x1F4
jne .LBB1_1
# %bb.2:
movq %r15, 184(%rsp) # 8-byte Spill
movq %r14, 176(%rsp) # 8-byte Spill
movl $2000, %edi # imm = 0x7D0
callq _Znam
movq %rax, %rbx
movl $2000, %edi # imm = 0x7D0
callq _Znam
movq %rax, %r13
xorl %r15d, %r15d
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl %r14d, (%rbx,%r15,4)
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
movl %eax, %edx
subl %ecx, %edx
negl %ecx
addl %ecx, %eax
incl %eax
movl %eax, (%r13,%r15,4)
addl %edx, %r14d
incl %r14d
incq %r15
cmpq $500, %r15 # imm = 0x1F4
jne .LBB1_3
# %bb.4:
movq %r13, 168(%rsp) # 8-byte Spill
movq %rbx, 160(%rsp) # 8-byte Spill
movq %r12, 192(%rsp) # 8-byte Spill
movslq %r14d, %rbx
leaq (,%rbx,4), %rax
testl %ebx, %ebx
movq $-1, %rdi
movq %rax, 48(%rsp) # 8-byte Spill
cmovnsq %rax, %rdi
callq _Znam
movq %rax, %r15
testl %ebx, %ebx
jle .LBB1_7
# %bb.5: # %.lr.ph.preheader
movl %r14d, %r14d
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_6: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $500, %ecx, %ecx # imm = 0x1F4
subl %ecx, %eax
movl %eax, (%r15,%rbx,4)
incq %rbx
cmpq %rbx, %r14
jne .LBB1_6
.LBB1_7: # %._crit_edge
movq %r15, 152(%rsp) # 8-byte Spill
movl $81920, %edi # imm = 0x14000
callq _Znam
movq %rax, %rbx
movl $81920, %edi # imm = 0x14000
callq _Znam
movq %rax, %rbp
movl $81920, %edi # imm = 0x14000
callq _Znam
movq %rax, %r12
movl $81920, %edi # imm = 0x14000
callq _Znam
movq %rax, %r15
movl $81920, %edi # imm = 0x14000
callq _Znam
movq %rax, %r14
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_8: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $500, %ecx, %ecx # imm = 0x1F4
subl %ecx, %eax
movl %eax, (%rbx,%r13,4)
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbp,%r13,4)
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
shll $2, %ecx
leal (%rcx,%rcx,4), %ecx
negl %ecx
addl %ecx, %eax
addl $65, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r12,%r13,4)
incq %r13
cmpq $20480, %r13 # imm = 0x5000
jne .LBB1_8
# %bb.9: # %.preheader151.preheader
movq %rbx, 32(%rsp) # 8-byte Spill
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_10: # %.preheader151
# =>This Inner Loop Header: Depth=1
movl $1, (%r15,%rax,4)
movl %eax, (%r14,%rax,4)
incq %rax
cmpq $16384, %rax # imm = 0x4000
jne .LBB1_10
# %bb.11: # %.preheader.preheader
movq %r15, %rdi
addq $65536, %rdi # imm = 0x10000
movl $16384, %ebx # imm = 0x4000
movl $16384, %edx # imm = 0x4000
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB1_12: # %.preheader
# =>This Inner Loop Header: Depth=1
movl %ebx, (%r14,%rbx,4)
incq %rbx
cmpq $20480, %rbx # imm = 0x5000
jne .LBB1_12
# %bb.13:
movq %rbp, 40(%rsp) # 8-byte Spill
movl $42, %edi
callq srand
movl $81920, %edi # imm = 0x14000
callq _Znam
movq %rax, %r13
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_14: # =>This Inner Loop Header: Depth=1
movl %eax, (%r13,%rax,4)
incq %rax
cmpq $20480, %rax # imm = 0x5000
jne .LBB1_14
# %bb.15:
movl $2000, %edi # imm = 0x7D0
callq _Znam
movq %rax, %rbp
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_16: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $500, %ecx, %ecx # imm = 0x1F4
subl %ecx, %eax
movl %eax, (%rbp,%rbx,4)
incq %rbx
cmpq $500, %rbx # imm = 0x1F4
jne .LBB1_16
# %bb.17:
movl $.Lstr.1, %edi
callq puts@PLT
movl $.Lstr.2, %edi
callq puts@PLT
leaq 16(%rsp), %rdi
movl $81920, %esi # imm = 0x14000
callq hipMalloc
testl %eax, %eax
jne .LBB1_18
# %bb.19: # %_Z14__cudaSafeCall10hipError_tPKci.exit
leaq 8(%rsp), %rdi
movl $81920, %esi # imm = 0x14000
callq hipMalloc
testl %eax, %eax
movq 32(%rsp), %rbx # 8-byte Reload
jne .LBB1_20
# %bb.21: # %_Z14__cudaSafeCall10hipError_tPKci.exit95
leaq 144(%rsp), %rdi
movl $81920, %esi # imm = 0x14000
callq hipMalloc
testl %eax, %eax
jne .LBB1_22
# %bb.23: # %_Z14__cudaSafeCall10hipError_tPKci.exit97
leaq 136(%rsp), %rdi
movl $2000, %esi # imm = 0x7D0
callq hipMalloc
testl %eax, %eax
jne .LBB1_24
# %bb.25: # %_Z14__cudaSafeCall10hipError_tPKci.exit99
leaq 128(%rsp), %rdi
movl $2000, %esi # imm = 0x7D0
callq hipMalloc
testl %eax, %eax
jne .LBB1_26
# %bb.27: # %_Z14__cudaSafeCall10hipError_tPKci.exit101
leaq 120(%rsp), %rdi
movl $2000, %esi # imm = 0x7D0
callq hipMalloc
testl %eax, %eax
jne .LBB1_28
# %bb.29: # %_Z14__cudaSafeCall10hipError_tPKci.exit103
leaq 112(%rsp), %rdi
movl $2000, %esi # imm = 0x7D0
callq hipMalloc
testl %eax, %eax
jne .LBB1_30
# %bb.31: # %_Z14__cudaSafeCall10hipError_tPKci.exit105
leaq 104(%rsp), %rdi
movl $2000, %esi # imm = 0x7D0
callq hipMalloc
testl %eax, %eax
jne .LBB1_32
# %bb.33: # %_Z14__cudaSafeCall10hipError_tPKci.exit107
leaq 96(%rsp), %rdi
movq 48(%rsp), %rsi # 8-byte Reload
callq hipMalloc
testl %eax, %eax
jne .LBB1_34
# %bb.35: # %_Z14__cudaSafeCall10hipError_tPKci.exit109
leaq 88(%rsp), %rdi
movl $81920, %esi # imm = 0x14000
callq hipMalloc
testl %eax, %eax
jne .LBB1_36
# %bb.37: # %_Z14__cudaSafeCall10hipError_tPKci.exit111
leaq 80(%rsp), %rdi
movl $81920, %esi # imm = 0x14000
callq hipMalloc
testl %eax, %eax
jne .LBB1_38
# %bb.39: # %_Z14__cudaSafeCall10hipError_tPKci.exit113
leaq 72(%rsp), %rdi
movl $81920, %esi # imm = 0x14000
callq hipMalloc
testl %eax, %eax
jne .LBB1_40
# %bb.41: # %_Z14__cudaSafeCall10hipError_tPKci.exit115
leaq 64(%rsp), %rdi
movl $2000, %esi # imm = 0x7D0
callq hipMalloc
testl %eax, %eax
jne .LBB1_42
# %bb.43: # %_Z14__cudaSafeCall10hipError_tPKci.exit117
movq 16(%rsp), %rdi
movl $81920, %edx # imm = 0x14000
movq 40(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_44
# %bb.45: # %_Z14__cudaSafeCall10hipError_tPKci.exit119
movq 8(%rsp), %rdi
movl $81920, %edx # imm = 0x14000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_46
# %bb.47: # %_Z14__cudaSafeCall10hipError_tPKci.exit121
movq 144(%rsp), %rdi
movl $81920, %edx # imm = 0x14000
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_48
# %bb.49: # %_Z14__cudaSafeCall10hipError_tPKci.exit123
movq 136(%rsp), %rdi
movl $2000, %edx # imm = 0x7D0
movq 192(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_50
# %bb.51: # %_Z14__cudaSafeCall10hipError_tPKci.exit125
movq 128(%rsp), %rdi
movl $2000, %edx # imm = 0x7D0
movq 184(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_52
# %bb.53: # %_Z14__cudaSafeCall10hipError_tPKci.exit127
movq 120(%rsp), %rdi
movl $2000, %edx # imm = 0x7D0
movq 176(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_54
# %bb.55: # %_Z14__cudaSafeCall10hipError_tPKci.exit129
movq 112(%rsp), %rdi
movl $2000, %edx # imm = 0x7D0
movq 168(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_56
# %bb.57: # %_Z14__cudaSafeCall10hipError_tPKci.exit131
movq 104(%rsp), %rdi
movl $2000, %edx # imm = 0x7D0
movq 160(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_58
# %bb.59: # %_Z14__cudaSafeCall10hipError_tPKci.exit133
movq 96(%rsp), %rdi
movq 152(%rsp), %rsi # 8-byte Reload
movq 48(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_60
# %bb.61: # %_Z14__cudaSafeCall10hipError_tPKci.exit135
movq 88(%rsp), %rdi
movl $81920, %edx # imm = 0x14000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_62
# %bb.63: # %_Z14__cudaSafeCall10hipError_tPKci.exit137
movq 80(%rsp), %rdi
movl $81920, %edx # imm = 0x14000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_64
# %bb.65: # %_Z14__cudaSafeCall10hipError_tPKci.exit139
movq 72(%rsp), %rdi
movl $81920, %edx # imm = 0x14000
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_66
# %bb.67: # %_Z14__cudaSafeCall10hipError_tPKci.exit141
movq 64(%rsp), %rdi
movl $2000, %edx # imm = 0x7D0
movq %rbp, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_68
# %bb.69: # %_Z14__cudaSafeCall10hipError_tPKci.exit143
movl $.Lstr.3, %edi
callq puts@PLT
leaq 56(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movl $.Lstr.4, %edi
callq puts@PLT
movq 56(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967328, %rdi # imm = 0x100000020
leaq 608(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq 40(%rsp), %r13 # 8-byte Reload
jne .LBB1_71
# %bb.70:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 144(%rsp), %rdx
movq 136(%rsp), %rsi
movq 128(%rsp), %rdi
movq 120(%rsp), %r8
movq 112(%rsp), %r9
movq 104(%rsp), %r10
movq 96(%rsp), %r11
movq 88(%rsp), %rbx
movq 80(%rsp), %r14
movq 72(%rsp), %r15
movq 64(%rsp), %r12
movl $0, 28(%rsp)
movl $1000000, 24(%rsp) # imm = 0xF4240
movq %rax, 344(%rsp)
movq %rcx, 336(%rsp)
movq %rdx, 328(%rsp)
movq %rsi, 320(%rsp)
movq %rdi, 312(%rsp)
movq %r8, 304(%rsp)
movq %r9, 296(%rsp)
movq %r10, 288(%rsp)
movq %r11, 280(%rsp)
movq %rbx, 272(%rsp)
movq 32(%rsp), %rbx # 8-byte Reload
movq %r14, 264(%rsp)
movq %r15, 256(%rsp)
movq %r12, 248(%rsp)
leaq 28(%rsp), %rax
movq %rax, 352(%rsp)
leaq 24(%rsp), %rax
movq %rax, 360(%rsp)
leaq 344(%rsp), %rax
movq %rax, 368(%rsp)
leaq 336(%rsp), %rax
movq %rax, 376(%rsp)
leaq 328(%rsp), %rax
movq %rax, 384(%rsp)
leaq 320(%rsp), %rax
movq %rax, 392(%rsp)
leaq 312(%rsp), %rax
movq %rax, 400(%rsp)
leaq 304(%rsp), %rax
movq %rax, 408(%rsp)
leaq 296(%rsp), %rax
movq %rax, 416(%rsp)
leaq 288(%rsp), %rax
movq %rax, 424(%rsp)
leaq 280(%rsp), %rax
movq %rax, 432(%rsp)
leaq 272(%rsp), %rax
movq %rax, 440(%rsp)
leaq 264(%rsp), %rax
movq %rax, 448(%rsp)
leaq 256(%rsp), %rax
movq %rax, 456(%rsp)
leaq 248(%rsp), %rax
movq %rax, 464(%rsp)
leaq 232(%rsp), %rdi
leaq 216(%rsp), %rsi
leaq 208(%rsp), %rdx
leaq 200(%rsp), %rcx
callq __hipPopCallConfiguration
movq 232(%rsp), %rsi
movl 240(%rsp), %edx
movq 216(%rsp), %rcx
movl 224(%rsp), %r8d
leaq 352(%rsp), %r9
movl $_Z6kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_, %edi
pushq 200(%rsp)
.cfi_adjust_cfa_offset 8
pushq 216(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_71:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_72
# %bb.75:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_76
# %bb.77: # %_Z16__cudaCheckErrorPKci.exit
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movl $0, 352(%rsp)
movq 56(%rsp), %rsi
movq (%rsp), %rdx
leaq 352(%rsp), %rdi
callq hipEventElapsedTime
callq hipGetLastError
testl %eax, %eax
jne .LBB1_78
# %bb.80:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_81
# %bb.82: # %_Z16__cudaCheckErrorPKci.exit147
movl $.Lstr.5, %edi
callq puts@PLT
movq 16(%rsp), %rsi
movl $81920, %edx # imm = 0x14000
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
movl $81920, %edx # imm = 0x14000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movss 352(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $472, %rsp # imm = 0x1D8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_18:
.cfi_def_cfa_offset 528
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $271, %ecx # imm = 0x10F
jmp .LBB1_74
.LBB1_20:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $272, %ecx # imm = 0x110
jmp .LBB1_74
.LBB1_22:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $273, %ecx # imm = 0x111
jmp .LBB1_74
.LBB1_24:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $274, %ecx # imm = 0x112
jmp .LBB1_74
.LBB1_26:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $275, %ecx # imm = 0x113
jmp .LBB1_74
.LBB1_28:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $276, %ecx # imm = 0x114
jmp .LBB1_74
.LBB1_30:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $277, %ecx # imm = 0x115
jmp .LBB1_74
.LBB1_32:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $278, %ecx # imm = 0x116
jmp .LBB1_74
.LBB1_34:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $279, %ecx # imm = 0x117
jmp .LBB1_74
.LBB1_36:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $280, %ecx # imm = 0x118
jmp .LBB1_74
.LBB1_38:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $281, %ecx # imm = 0x119
jmp .LBB1_74
.LBB1_40:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $282, %ecx # imm = 0x11A
jmp .LBB1_74
.LBB1_42:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $283, %ecx # imm = 0x11B
jmp .LBB1_74
.LBB1_44:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $285, %ecx # imm = 0x11D
jmp .LBB1_74
.LBB1_46:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $286, %ecx # imm = 0x11E
jmp .LBB1_74
.LBB1_48:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $287, %ecx # imm = 0x11F
jmp .LBB1_74
.LBB1_50:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $288, %ecx # imm = 0x120
jmp .LBB1_74
.LBB1_52:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $289, %ecx # imm = 0x121
jmp .LBB1_74
.LBB1_54:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $290, %ecx # imm = 0x122
jmp .LBB1_74
.LBB1_56:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $291, %ecx # imm = 0x123
jmp .LBB1_74
.LBB1_58:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $292, %ecx # imm = 0x124
jmp .LBB1_74
.LBB1_60:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $293, %ecx # imm = 0x125
jmp .LBB1_74
.LBB1_62:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $294, %ecx # imm = 0x126
jmp .LBB1_74
.LBB1_64:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $295, %ecx # imm = 0x127
jmp .LBB1_74
.LBB1_66:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $296, %ecx # imm = 0x128
jmp .LBB1_74
.LBB1_68:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $297, %ecx # imm = 0x129
jmp .LBB1_74
.LBB1_72:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.9, %esi
jmp .LBB1_73
.LBB1_76:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
.LBB1_73:
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $311, %ecx # imm = 0x137
jmp .LBB1_74
.LBB1_78:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.9, %esi
jmp .LBB1_79
.LBB1_81:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
.LBB1_79:
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $318, %ecx # imm = 0x13E
.LBB1_74:
movq %rax, %r8
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $d_Actor_progress, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $d_Actor_street, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $d_Car_max_velocity, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $d_Street_length, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $d_Street_max_velocity, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $d_Street_neighbors, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $d_Array_Street_size, %esi
movl $.L__unnamed_8, %edx
movl $.L__unnamed_8, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $d_Array_Street_offset, %esi
movl $.L__unnamed_9, %edx
movl $.L__unnamed_9, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $d_Array_Street_arrays, %esi
movl $.L__unnamed_10, %edx
movl $.L__unnamed_10, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $d_input_actor_tag, %esi
movl $.L__unnamed_11, %edx
movl $.L__unnamed_11, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $d_input_actor_id, %esi
movl $.L__unnamed_12, %edx
movl $.L__unnamed_12, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $d_jobs, %esi
movl $.L__unnamed_13, %edx
movl $.L__unnamed_13, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $d_randomn, %esi
movl $.L__unnamed_14, %edx
movl $.L__unnamed_14, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type d_Actor_progress,@object # @d_Actor_progress
.local d_Actor_progress
.comm d_Actor_progress,8,8
.type d_Actor_street,@object # @d_Actor_street
.local d_Actor_street
.comm d_Actor_street,8,8
.type d_Car_max_velocity,@object # @d_Car_max_velocity
.local d_Car_max_velocity
.comm d_Car_max_velocity,8,8
.type d_Street_length,@object # @d_Street_length
.local d_Street_length
.comm d_Street_length,8,8
.type d_Street_max_velocity,@object # @d_Street_max_velocity
.local d_Street_max_velocity
.comm d_Street_max_velocity,8,8
.type d_Street_neighbors,@object # @d_Street_neighbors
.local d_Street_neighbors
.comm d_Street_neighbors,8,8
.type d_Array_Street_size,@object # @d_Array_Street_size
.local d_Array_Street_size
.comm d_Array_Street_size,8,8
.type d_Array_Street_offset,@object # @d_Array_Street_offset
.local d_Array_Street_offset
.comm d_Array_Street_offset,8,8
.type d_Array_Street_arrays,@object # @d_Array_Street_arrays
.local d_Array_Street_arrays
.comm d_Array_Street_arrays,8,8
.type d_input_actor_tag,@object # @d_input_actor_tag
.local d_input_actor_tag
.comm d_input_actor_tag,8,8
.type d_input_actor_id,@object # @d_input_actor_id
.local d_input_actor_id
.comm d_input_actor_id,8,8
.type d_jobs,@object # @d_jobs
.local d_jobs
.comm d_jobs,8,8
.type d_randomn,@object # @d_randomn
.local d_randomn
.comm d_randomn,8,8
.type _Z6kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_,@object # @_Z6kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_
.section .rodata,"a",@progbits
.globl _Z6kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_
.p2align 3, 0x0
_Z6kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_:
.quad _Z21__device_stub__kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_
.size _Z6kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/prg-titech/array2016-paper/master/benchmarks/benchmark_column_reorder.hip"
.size .L.str.3, 131
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\n\n\nElapsed time millis: %f\n"
.size .L.str.7, 28
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "cudaSafeCall() failed at %s:%i : %s\n"
.size .L.str.8, 37
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "cudaCheckError() failed at %s:%i : %s\n"
.size .L.str.9, 39
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "cudaCheckError() with sync failed at %s:%i : %s\n"
.size .L.str.10, 49
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_"
.size .L__unnamed_1, 46
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "d_Actor_progress"
.size .L__unnamed_2, 17
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "d_Actor_street"
.size .L__unnamed_3, 15
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "d_Car_max_velocity"
.size .L__unnamed_4, 19
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "d_Street_length"
.size .L__unnamed_5, 16
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "d_Street_max_velocity"
.size .L__unnamed_6, 22
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "d_Street_neighbors"
.size .L__unnamed_7, 19
.type .L__unnamed_8,@object # @7
.L__unnamed_8:
.asciz "d_Array_Street_size"
.size .L__unnamed_8, 20
.type .L__unnamed_9,@object # @8
.L__unnamed_9:
.asciz "d_Array_Street_offset"
.size .L__unnamed_9, 22
.type .L__unnamed_10,@object # @9
.L__unnamed_10:
.asciz "d_Array_Street_arrays"
.size .L__unnamed_10, 22
.type .L__unnamed_11,@object # @10
.L__unnamed_11:
.asciz "d_input_actor_tag"
.size .L__unnamed_11, 18
.type .L__unnamed_12,@object # @11
.L__unnamed_12:
.asciz "d_input_actor_id"
.size .L__unnamed_12, 17
.type .L__unnamed_13,@object # @12
.L__unnamed_13:
.asciz "d_jobs"
.size .L__unnamed_13, 7
.type .L__unnamed_14,@object # @13
.L__unnamed_14:
.asciz "d_randomn"
.size .L__unnamed_14, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Setting up scenario..."
.size .Lstr, 23
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Scenario set up."
.size .Lstr.1, 17
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Copying data to GPU..."
.size .Lstr.2, 23
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Finished copying data."
.size .Lstr.3, 23
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Launching kernel..."
.size .Lstr.4, 20
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "Kernel finished."
.size .Lstr.5, 17
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym d_Actor_progress
.addrsig_sym d_Actor_street
.addrsig_sym d_Car_max_velocity
.addrsig_sym d_Street_length
.addrsig_sym d_Street_max_velocity
.addrsig_sym d_Street_neighbors
.addrsig_sym d_Array_Street_size
.addrsig_sym d_Array_Street_offset
.addrsig_sym d_Array_Street_arrays
.addrsig_sym d_input_actor_tag
.addrsig_sym d_input_actor_id
.addrsig_sym d_jobs
.addrsig_sym d_randomn
.addrsig_sym _Z6kerneliiPfPiS_S_S_S0_S0_S0_S0_S0_S0_S0_S0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <complex>
#include <cmath>
#include <iomanip>
#include <string>
#include <fstream>
using namespace std;
__global__
void z_funct(double * d_mat_re, double * d_mat_im, int *d_img, int nb_ite)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
double c_re = d_mat_re[i];
double c_im = d_mat_im[i];
double z_re = 0, z_im =0;
double z_re_tmp = 0;
int t=0;
while ((z_re*z_re+z_im*z_im <= 4) && (t<nb_ite))
{
z_re_tmp = z_re*z_re - z_im*z_im + c_re;
z_im = 2*z_im*z_re + c_im;
z_re = z_re_tmp;
t++;
}
d_img[i] = t;
}
int main(int argc, char * argv[])
{
if (argc == 1)
{
cout << "Help" << endl
<< " 8 args :" << endl << endl
<< "arg1 = min real part | arg2 = min imaginary part " << endl
<< "arg3 = max real part | arg4 = max imaginary part " << endl
<< "arg5 = number of points on the real axe | arg6 = number of points on the imaginary axe " << endl
<< "arg7 = nb of iterations | arg8 = limit convergence"
<< endl << endl
<< " 4 args :" << endl << endl
<< "arg1 = number of points on the real axe | arg2 = number of points on the imaginary axe " << endl
<< "arg3 = nb of iterations "
<< endl << endl ;
return 1;
}
double max_re, max_im, min_re, min_im;
int nb_pts_re, nb_pts_im, nb_ite;
if (argc == 8)
{
try
{
min_re = stod(argv[1]);
min_im = stod(argv[2]);
max_re = stod(argv[3]);
max_im = stod(argv[4]);
nb_pts_re = stoi(argv[5]);
nb_pts_im = stoi(argv[6]);
nb_ite = stoi(argv[7]);
}
catch (...)
{
cout << "Bad Args : see help (type nameofprogram without args)" << endl << endl;
return 1;
}
}
if (argc == 4 )
{
min_re = -2;
min_im = -1;
max_re = 1;
max_im = 1;
try
{
nb_pts_re = stoi(argv[1]);
nb_pts_im = stoi(argv[2]);
nb_ite = stoi(argv[3]);
}
catch (...)
{
cout << "Bad Args : see help (type nameofprogram without args)" << endl << endl;
return 1;
}
}
cout << "Initializing..." << endl;
int size_d = sizeof(double)*nb_pts_re*nb_pts_im;
int size_i = sizeof(int)*nb_pts_re*nb_pts_im;
double * mat_re = (double *)malloc(size_d);
double * mat_im = (double *)malloc(size_d);
double re, im;
for (int i=0; i<nb_pts_im; i++)
{
im = max_im - (max_im-min_im)/nb_pts_im*i;
for (int j=0; j<nb_pts_re; j++)
{
re = max_re - (max_re-min_re)/nb_pts_re*j;
mat_re[i*nb_pts_re+j] = re;
mat_im[i*nb_pts_re+j] = im;
}
}
double *d_mat_re, *d_mat_im;
int *d_img;
cudaMalloc(&d_mat_re,size_d);
cudaMalloc(&d_mat_im,size_d);
cudaMalloc(&d_img,size_i);
cudaMemcpy(d_mat_re, mat_re, size_d, cudaMemcpyHostToDevice);
cudaMemcpy(d_mat_im, mat_im, size_d, cudaMemcpyHostToDevice);
cout << "Running on GPU..." << endl;
dim3 blockDim = 1024;
dim3 gridDim = (nb_pts_re*nb_pts_im)/1024 + 1;
z_funct<<<gridDim,blockDim>>>(d_mat_re, d_mat_im, d_img, nb_ite);
cout << "Fetching datas..." << endl;
int * img = (int*) malloc(size_i);
cudaMemcpy(mat_re, d_mat_re, size_d, cudaMemcpyDeviceToHost);
cudaMemcpy(mat_im, d_mat_im, size_d, cudaMemcpyDeviceToHost);
cudaMemcpy(img, d_img, size_i, cudaMemcpyDeviceToHost);
cout << "Writing on the disk..." << endl;
ofstream file; file.open("conv");
for (int i=0; i<nb_pts_im; i++)
{
for (int j=0; j<nb_pts_re; j++)
{
file << setw(15) << img[i*nb_pts_re+j] ;
}
file << endl ;
}
file.close();
/*
file.open("val");
for (int i=0; i<nb_pts_im; i++)
{
for (int j=0; j<nb_pts_re; j++)
{
file << setw(15) << pow(mat_re[i*nb_pts_re+j],2) + pow(mat_im[i*nb_pts_re+j],2) ;
}
file << endl ;
}
file.close();
*/
cout << "Done !" << endl;
return 0;
} | code for sm_80
Function : _Z7z_functPdS_Pii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R19, -RZ, RZ, 0, 0 ; /* 0x00000000ff137435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0080*/ SHF.R.S32.HI R3, RZ, 0x1f, R6 ; /* 0x0000001fff037819 */
/* 0x000fe40000011406 */
/*0090*/ LEA R2, P1, R6, c[0x0][0x170], 0x2 ; /* 0x00005c0006027a11 */
/* 0x000fc800078210ff */
/*00a0*/ LEA.HI.X R3, R6, c[0x0][0x174], R3, 0x2, P1 ; /* 0x00005d0006037a11 */
/* 0x000fe200008f1403 */
/*00b0*/ @!P0 BRA 0x250 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fc800078e00ff */
/*00d0*/ IMAD.WIDE R4, R6, R7, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fe400078e0207 */
/*00f0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000f68000c1e1b00 */
/*0100*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f62000c1e1b00 */
/*0110*/ BSSY B0, 0x250 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*0120*/ MOV R19, RZ ; /* 0x000000ff00137202 */
/* 0x000fe20000000f00 */
/*0130*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*0140*/ CS2R R10, SRZ ; /* 0x00000000000a7805 */
/* 0x000fe2000001ff00 */
/*0150*/ CS2R R12, SRZ ; /* 0x00000000000c7805 */
/* 0x000fe2000001ff00 */
/*0160*/ CS2R R14, SRZ ; /* 0x00000000000e7805 */
/* 0x000fc8000001ff00 */
/*0170*/ DADD R8, R10, -R8 ; /* 0x000000000a087229 */
/* 0x000e220000000808 */
/*0180*/ IADD3 R19, R19, 0x1, RZ ; /* 0x0000000113137810 */
/* 0x000fc60007ffe0ff */
/*0190*/ DADD R12, R12, R12 ; /* 0x000000000c0c7229 */
/* 0x000e62000000000c */
/*01a0*/ ISETP.GE.AND P0, PT, R19, c[0x0][0x178], PT ; /* 0x00005e0013007a0c */
/* 0x000fc60003f06270 */
/*01b0*/ DADD R16, R4, R8 ; /* 0x0000000004107229 */
/* 0x021e080000000008 */
/*01c0*/ DFMA R12, R12, R14, R6 ; /* 0x0000000e0c0c722b */
/* 0x002e480000000006 */
/*01d0*/ DMUL R10, R16, R16 ; /* 0x00000010100a7228 */
/* 0x001fc80000000000 */
/*01e0*/ DMUL R8, R12, R12 ; /* 0x0000000c0c087228 */
/* 0x002e0c0000000000 */
/*01f0*/ DADD R14, R10, R8 ; /* 0x000000000a0e7229 */
/* 0x001e0c0000000008 */
/*0200*/ DSETP.LE.AND P1, PT, R14, 4, PT ; /* 0x401000000e00742a */
/* 0x0010640003f23000 */
/*0210*/ IMAD.MOV.U32 R14, RZ, RZ, R16 ; /* 0x000000ffff0e7224 */
/* 0x001fe200078e0010 */
/*0220*/ MOV R15, R17 ; /* 0x00000011000f7202 */
/* 0x000fd60000000f00 */
/*0230*/ @!P0 BRA P1, 0x170 ; /* 0xffffff3000008947 */
/* 0x002fea000083ffff */
/*0240*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0250*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x000fe2000c101904 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <complex>
#include <cmath>
#include <iomanip>
#include <string>
#include <fstream>
using namespace std;
__global__
void z_funct(double * d_mat_re, double * d_mat_im, int *d_img, int nb_ite)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
double c_re = d_mat_re[i];
double c_im = d_mat_im[i];
double z_re = 0, z_im =0;
double z_re_tmp = 0;
int t=0;
while ((z_re*z_re+z_im*z_im <= 4) && (t<nb_ite))
{
z_re_tmp = z_re*z_re - z_im*z_im + c_re;
z_im = 2*z_im*z_re + c_im;
z_re = z_re_tmp;
t++;
}
d_img[i] = t;
}
int main(int argc, char * argv[])
{
if (argc == 1)
{
cout << "Help" << endl
<< " 8 args :" << endl << endl
<< "arg1 = min real part | arg2 = min imaginary part " << endl
<< "arg3 = max real part | arg4 = max imaginary part " << endl
<< "arg5 = number of points on the real axe | arg6 = number of points on the imaginary axe " << endl
<< "arg7 = nb of iterations | arg8 = limit convergence"
<< endl << endl
<< " 4 args :" << endl << endl
<< "arg1 = number of points on the real axe | arg2 = number of points on the imaginary axe " << endl
<< "arg3 = nb of iterations "
<< endl << endl ;
return 1;
}
double max_re, max_im, min_re, min_im;
int nb_pts_re, nb_pts_im, nb_ite;
if (argc == 8)
{
try
{
min_re = stod(argv[1]);
min_im = stod(argv[2]);
max_re = stod(argv[3]);
max_im = stod(argv[4]);
nb_pts_re = stoi(argv[5]);
nb_pts_im = stoi(argv[6]);
nb_ite = stoi(argv[7]);
}
catch (...)
{
cout << "Bad Args : see help (type nameofprogram without args)" << endl << endl;
return 1;
}
}
if (argc == 4 )
{
min_re = -2;
min_im = -1;
max_re = 1;
max_im = 1;
try
{
nb_pts_re = stoi(argv[1]);
nb_pts_im = stoi(argv[2]);
nb_ite = stoi(argv[3]);
}
catch (...)
{
cout << "Bad Args : see help (type nameofprogram without args)" << endl << endl;
return 1;
}
}
cout << "Initializing..." << endl;
int size_d = sizeof(double)*nb_pts_re*nb_pts_im;
int size_i = sizeof(int)*nb_pts_re*nb_pts_im;
double * mat_re = (double *)malloc(size_d);
double * mat_im = (double *)malloc(size_d);
double re, im;
for (int i=0; i<nb_pts_im; i++)
{
im = max_im - (max_im-min_im)/nb_pts_im*i;
for (int j=0; j<nb_pts_re; j++)
{
re = max_re - (max_re-min_re)/nb_pts_re*j;
mat_re[i*nb_pts_re+j] = re;
mat_im[i*nb_pts_re+j] = im;
}
}
double *d_mat_re, *d_mat_im;
int *d_img;
cudaMalloc(&d_mat_re,size_d);
cudaMalloc(&d_mat_im,size_d);
cudaMalloc(&d_img,size_i);
cudaMemcpy(d_mat_re, mat_re, size_d, cudaMemcpyHostToDevice);
cudaMemcpy(d_mat_im, mat_im, size_d, cudaMemcpyHostToDevice);
cout << "Running on GPU..." << endl;
dim3 blockDim = 1024;
dim3 gridDim = (nb_pts_re*nb_pts_im)/1024 + 1;
z_funct<<<gridDim,blockDim>>>(d_mat_re, d_mat_im, d_img, nb_ite);
cout << "Fetching datas..." << endl;
int * img = (int*) malloc(size_i);
cudaMemcpy(mat_re, d_mat_re, size_d, cudaMemcpyDeviceToHost);
cudaMemcpy(mat_im, d_mat_im, size_d, cudaMemcpyDeviceToHost);
cudaMemcpy(img, d_img, size_i, cudaMemcpyDeviceToHost);
cout << "Writing on the disk..." << endl;
ofstream file; file.open("conv");
for (int i=0; i<nb_pts_im; i++)
{
for (int j=0; j<nb_pts_re; j++)
{
file << setw(15) << img[i*nb_pts_re+j] ;
}
file << endl ;
}
file.close();
/*
file.open("val");
for (int i=0; i<nb_pts_im; i++)
{
for (int j=0; j<nb_pts_re; j++)
{
file << setw(15) << pow(mat_re[i*nb_pts_re+j],2) + pow(mat_im[i*nb_pts_re+j],2) ;
}
file << endl ;
}
file.close();
*/
cout << "Done !" << endl;
return 0;
} | .file "tmpxft_0009ed35_00000000-6_cu_mandelbrot.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4285:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4285:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z7z_functPdS_PiiPdS_Pii
.type _Z31__device_stub__Z7z_functPdS_PiiPdS_Pii, @function
_Z31__device_stub__Z7z_functPdS_PiiPdS_Pii:
.LFB4307:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7z_functPdS_Pii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4307:
.size _Z31__device_stub__Z7z_functPdS_PiiPdS_Pii, .-_Z31__device_stub__Z7z_functPdS_PiiPdS_Pii
.globl _Z7z_functPdS_Pii
.type _Z7z_functPdS_Pii, @function
_Z7z_functPdS_Pii:
.LFB4308:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z7z_functPdS_PiiPdS_Pii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4308:
.size _Z7z_functPdS_Pii, .-_Z7z_functPdS_Pii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7z_functPdS_Pii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4310:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7z_functPdS_Pii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4310:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"axG",@progbits,_ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat
.weak _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.type _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_, @function
_ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_:
.LFB4384:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4384
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r13
movq %rsi, 8(%rsp)
movq %rdx, %rbp
movq %rcx, %r12
movl %r8d, %r14d
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
call __errno_location@PLT
movq %rax, %rbx
movl (%rax), %r15d
movl $0, (%rax)
leaq 16(%rsp), %rsi
movl %r14d, %edx
movq %rbp, %rdi
.LEHB0:
call *%r13
movq 16(%rsp), %rcx
cmpq %rbp, %rcx
je .L27
cmpl $34, (%rbx)
je .L16
movl $2147483648, %edx
addq %rax, %rdx
shrq $32, %rdx
jne .L16
testq %r12, %r12
je .L19
subq %rbp, %rcx
movq %rcx, (%r12)
.L19:
cmpl $0, (%rbx)
jne .L13
movl %r15d, (%rbx)
.L13:
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L28
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L29
movq 8(%rsp), %rdi
call _ZSt24__throw_invalid_argumentPKc@PLT
.L29:
call __stack_chk_fail@PLT
.L16:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L30
movq 8(%rsp), %rdi
call _ZSt20__throw_out_of_rangePKc@PLT
.LEHE0:
.L25:
endbr64
movq %rax, %rdi
cmpl $0, (%rbx)
jne .L22
movl %r15d, (%rbx)
.L22:
movq 24(%rsp), %rax
subq %fs:40, %rax
je .L23
call __stack_chk_fail@PLT
.L30:
call __stack_chk_fail@PLT
.L23:
.LEHB1:
call _Unwind_Resume@PLT
.LEHE1:
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4384:
.globl __gxx_personality_v0
.section .gcc_except_table._ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"aG",@progbits,_ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat
.LLSDA4384:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4384-.LLSDACSB4384
.LLSDACSB4384:
.uleb128 .LEHB0-.LFB4384
.uleb128 .LEHE0-.LEHB0
.uleb128 .L25-.LFB4384
.uleb128 0
.uleb128 .LEHB1-.LFB4384
.uleb128 .LEHE1-.LEHB1
.uleb128 0
.uleb128 0
.LLSDACSE4384:
.section .text._ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"axG",@progbits,_ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat
.size _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_, .-_ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.section .text._ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"axG",@progbits,_ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat
.weak _ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.type _ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_, @function
_ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_:
.LFB4438:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4438
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r15
movq %rsi, %r14
movq %rdx, %rbp
movq %rcx, %r12
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
call __errno_location@PLT
movq %rax, %rbx
movl (%rax), %r13d
movl $0, (%rax)
movq %rsp, %rsi
movq %rbp, %rdi
.LEHB2:
call *%r15
movq (%rsp), %rax
cmpq %rbp, %rax
je .L44
cmpl $34, (%rbx)
je .L45
testq %r12, %r12
je .L36
subq %rbp, %rax
movq %rax, (%r12)
.L36:
cmpl $0, (%rbx)
jne .L31
movl %r13d, (%rbx)
.L31:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L47
movq %r14, %rdi
call _ZSt24__throw_invalid_argumentPKc@PLT
.L42:
endbr64
movq %rax, %rdi
cmpl $0, (%rbx)
jne .L39
movl %r13d, (%rbx)
.L39:
movq 8(%rsp), %rax
subq %fs:40, %rax
je .L40
call __stack_chk_fail@PLT
.L47:
call __stack_chk_fail@PLT
.L45:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L48
movq %r14, %rdi
call _ZSt20__throw_out_of_rangePKc@PLT
.LEHE2:
.L48:
call __stack_chk_fail@PLT
.L40:
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4438:
.section .gcc_except_table._ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"aG",@progbits,_ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat
.LLSDA4438:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4438-.LLSDACSB4438
.LLSDACSB4438:
.uleb128 .LEHB2-.LFB4438
.uleb128 .LEHE2-.LEHB2
.uleb128 .L42-.LFB4438
.uleb128 0
.uleb128 .LEHB3-.LFB4438
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE4438:
.section .text._ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"axG",@progbits,_ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat
.size _ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_, .-_ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.section .rodata._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "basic_string: construction from null is not valid"
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC5IS3_EEPKcRKS3_,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_:
.LFB4630:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 16(%rdi), %r12
movq %r12, (%rdi)
testq %rsi, %rsi
je .L58
movq %rdi, %rbx
movq %rsi, %r13
movq %rsi, %rdi
call strlen@PLT
movq %rax, %rbp
movq %rax, (%rsp)
cmpq $15, %rax
ja .L59
cmpq $1, %rax
jne .L54
movzbl 0(%r13), %eax
movb %al, 16(%rbx)
.L55:
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L60
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L61
leaq .LC1(%rip), %rdi
call _ZSt19__throw_logic_errorPKc@PLT
.L61:
call __stack_chk_fail@PLT
.L59:
movq %rsp, %rsi
movl $0, %edx
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %r12
movq %rax, (%rbx)
movq (%rsp), %rax
movq %rax, 16(%rbx)
.L53:
movq %rbp, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memcpy@PLT
jmp .L55
.L54:
testq %rax, %rax
je .L55
jmp .L53
.L60:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4630:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.set _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.section .rodata.str1.1
.LC5:
.string "Help"
.LC6:
.string " 8 args :"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "arg1 = min real part | arg2 = min imaginary part "
.align 8
.LC8:
.string "arg3 = max real part | arg4 = max imaginary part "
.align 8
.LC9:
.string "arg5 = number of points on the real axe | arg6 = number of points on the imaginary axe "
.align 8
.LC10:
.string "arg7 = nb of iterations | arg8 = limit convergence"
.section .rodata.str1.1
.LC11:
.string " 4 args :"
.section .rodata.str1.8
.align 8
.LC12:
.string "arg1 = number of points on the real axe | arg2 = number of points on the imaginary axe "
.section .rodata.str1.1
.LC13:
.string "arg3 = nb of iterations "
.LC14:
.string "stod"
.LC15:
.string "stoi"
.LC16:
.string "Initializing..."
.LC17:
.string "Running on GPU..."
.LC18:
.string "Fetching datas..."
.LC19:
.string "Writing on the disk..."
.LC20:
.string "conv"
.LC21:
.string "Done !"
.section .rodata.str1.8
.align 8
.LC22:
.string "Bad Args : see help (type nameofprogram without args)"
.text
.globl main
.type main, @function
main:
.LFB4282:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4282
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $632, %rsp
.cfi_def_cfa_offset 688
movl %edi, %ebx
movq %fs:40, %rax
movq %rax, 616(%rsp)
xorl %eax, %eax
cmpl $1, %edi
je .L119
movq %rsi, %r12
cmpl $8, %edi
je .L120
cmpl $4, %edi
je .L121
.L66:
leaq .LC16(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB4:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl 16(%rsp), %r9d
movslq %r9d, %r15
movl 20(%rsp), %eax
imull %r9d, %eax
leal 0(,%rax,4), %ebx
sall $3, %eax
movslq %eax, %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %r12
movq %r14, %rdi
call malloc@PLT
movq %rax, %r13
movl 20(%rsp), %r10d
testl %r10d, %r10d
jle .L67
movsd 32(%rsp), %xmm5
movapd %xmm5, %xmm4
subsd 40(%rsp), %xmm4
pxor %xmm0, %xmm0
cvtsi2sdl %r10d, %xmm0
divsd %xmm0, %xmm4
movl 16(%rsp), %r9d
movl %r9d, %edi
movl $0, %esi
movl $0, %ecx
.L70:
pxor %xmm0, %xmm0
cvtsi2sdl %ecx, %xmm0
mulsd %xmm4, %xmm0
movapd %xmm5, %xmm3
subsd %xmm0, %xmm3
testl %r9d, %r9d
jle .L68
pxor %xmm0, %xmm0
cvtsi2sdl %r9d, %xmm0
movsd 8(%rsp), %xmm2
subsd 24(%rsp), %xmm2
divsd %xmm0, %xmm2
movslq %esi, %rdx
salq $3, %rdx
leaq (%r12,%rdx), %r8
addq %r13, %rdx
movl $0, %eax
.L69:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd %xmm2, %xmm0
movsd 8(%rsp), %xmm1
subsd %xmm0, %xmm1
movsd %xmm1, (%r8,%rax,8)
movsd %xmm3, (%rdx,%rax,8)
addq $1, %rax
cmpq %rax, %r15
jne .L69
.L68:
addl $1, %ecx
addl %edi, %esi
cmpl %ecx, %r10d
jne .L70
.L67:
leaq 48(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movslq %ebx, %rbx
leaq 64(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r12, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r13, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC17(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1024, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl 16(%rsp), %edx
movl 20(%rsp), %eax
imull %eax, %edx
leal 1023(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $10, %eax
addl $1, %eax
movl %eax, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 72(%rsp), %rdx
movl $1, %ecx
movq 84(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L122
.L71:
leaq .LC18(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbx, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movl $2, %ecx
movq %r14, %rdx
movq 48(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %r14, %rdx
movq 56(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 64(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC19(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 96(%rsp), %rbx
movq %rbx, %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE4:
movl $16, %edx
leaq .LC20(%rip), %rsi
movq %rbx, %rdi
.LEHB5:
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
.LEHE5:
jmp .L123
.L119:
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB6:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC7(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC8(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC9(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC10(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC11(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC12(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC13(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE6:
movl %ebx, %eax
jmp .L62
.L120:
leaq 84(%rsp), %rdx
movq 8(%rsi), %rsi
leaq 96(%rsp), %rdi
.LEHB7:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE7:
movl $0, %ecx
movq 96(%rsp), %rdx
leaq .LC14(%rip), %rsi
movq strtod@GOTPCREL(%rip), %rdi
.LEHB8:
call _ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.LEHE8:
movsd %xmm0, 24(%rsp)
leaq 96(%rsp), %rbx
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 84(%rsp), %rdx
movq 16(%r12), %rsi
movq %rbx, %rdi
.LEHB9:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE9:
movl $0, %ecx
movq 96(%rsp), %rdx
leaq .LC14(%rip), %rsi
movq strtod@GOTPCREL(%rip), %rdi
.LEHB10:
call _ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.LEHE10:
movsd %xmm0, 40(%rsp)
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 84(%rsp), %rdx
movq 24(%r12), %rsi
movq %rbx, %rdi
.LEHB11:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE11:
movl $0, %ecx
movq 96(%rsp), %rdx
leaq .LC14(%rip), %rsi
movq strtod@GOTPCREL(%rip), %rdi
.LEHB12:
call _ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.LEHE12:
movsd %xmm0, 8(%rsp)
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 84(%rsp), %rdx
movq 32(%r12), %rsi
movq %rbx, %rdi
.LEHB13:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE13:
movl $0, %ecx
movq 96(%rsp), %rdx
leaq .LC14(%rip), %rsi
movq strtod@GOTPCREL(%rip), %rdi
.LEHB14:
call _ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.LEHE14:
movsd %xmm0, 32(%rsp)
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 84(%rsp), %rdx
movq 40(%r12), %rsi
movq %rbx, %rdi
.LEHB15:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE15:
movl $10, %r8d
movl $0, %ecx
movq 96(%rsp), %rdx
leaq .LC15(%rip), %rsi
movq __isoc23_strtol@GOTPCREL(%rip), %rdi
.LEHB16:
call _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.LEHE16:
movl %eax, 16(%rsp)
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 84(%rsp), %rdx
movq 48(%r12), %rsi
movq %rbx, %rdi
.LEHB17:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE17:
movl $10, %r8d
movl $0, %ecx
movq 96(%rsp), %rdx
leaq .LC15(%rip), %rsi
movq __isoc23_strtol@GOTPCREL(%rip), %rdi
.LEHB18:
call _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.LEHE18:
movl %eax, 20(%rsp)
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 84(%rsp), %rdx
movq 56(%r12), %rsi
movq %rbx, %rdi
.LEHB19:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE19:
movl $10, %r8d
movl $0, %ecx
movq 96(%rsp), %rdx
leaq .LC15(%rip), %rsi
movq __isoc23_strtol@GOTPCREL(%rip), %rdi
.LEHB20:
call _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.LEHE20:
movl %eax, %ebp
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
jmp .L66
.L121:
leaq 84(%rsp), %rdx
movq 8(%rsi), %rsi
leaq 96(%rsp), %rdi
.LEHB21:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE21:
movl $10, %r8d
movl $0, %ecx
movq 96(%rsp), %rdx
leaq .LC15(%rip), %rsi
movq __isoc23_strtol@GOTPCREL(%rip), %rdi
.LEHB22:
call _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.LEHE22:
movl %eax, 16(%rsp)
leaq 96(%rsp), %rbx
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 84(%rsp), %rdx
movq 16(%r12), %rsi
movq %rbx, %rdi
.LEHB23:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE23:
movl $10, %r8d
movl $0, %ecx
movq 96(%rsp), %rdx
leaq .LC15(%rip), %rsi
movq __isoc23_strtol@GOTPCREL(%rip), %rdi
.LEHB24:
call _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.LEHE24:
movl %eax, 20(%rsp)
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 84(%rsp), %rdx
movq 24(%r12), %rsi
movq %rbx, %rdi
.LEHB25:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE25:
movl $10, %r8d
movl $0, %ecx
movq 96(%rsp), %rdx
leaq .LC15(%rip), %rsi
movq __isoc23_strtol@GOTPCREL(%rip), %rdi
.LEHB26:
call _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.LEHE26:
movl %eax, %ebp
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movsd .LC2(%rip), %xmm7
movsd %xmm7, 40(%rsp)
movsd .LC3(%rip), %xmm7
movsd %xmm7, 24(%rsp)
movsd .LC4(%rip), %xmm7
movsd %xmm7, 32(%rsp)
movsd %xmm7, 8(%rsp)
jmp .L66
.L122:
movl %ebp, %ecx
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
.LEHB27:
call _Z31__device_stub__Z7z_functPdS_PiiPdS_Pii
.LEHE27:
jmp .L71
.L123:
cmpl $0, 20(%rsp)
jle .L72
movl 16(%rsp), %eax
movl %eax, 24(%rsp)
movl $0, %r14d
movl $0, %r13d
movq %rbx, %rbp
jmp .L73
.L124:
addq $4, %rbx
cmpq %r12, %rbx
je .L80
.L74:
movq 96(%rsp), %rax
movq -24(%rax), %rax
movq $15, 112(%rsp,%rax)
movl (%rbx), %esi
movq %rbp, %rdi
.LEHB28:
call _ZNSolsEi@PLT
jmp .L124
.L80:
movq 96(%rsp), %rax
movq -24(%rax), %rax
movq 336(%rsp,%rax), %rbx
testq %rbx, %rbx
je .L125
cmpb $0, 56(%rbx)
je .L77
movzbl 67(%rbx), %esi
.L78:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
jmp .L126
.L125:
movq 616(%rsp), %rax
subq %fs:40, %rax
jne .L127
call _ZSt16__throw_bad_castv@PLT
.L114:
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 616(%rsp), %rax
subq %fs:40, %rax
je .L98
call __stack_chk_fail@PLT
.L127:
call __stack_chk_fail@PLT
.L77:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L78
.L126:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %r13d
movl 24(%rsp), %eax
addl %eax, %r14d
cmpl %r13d, 20(%rsp)
je .L72
.L73:
cmpl $0, 16(%rsp)
jle .L80
movslq %r14d, %rax
movq 8(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
addq %r15, %rax
leaq (%rcx,%rax,4), %r12
jmp .L74
.L72:
leaq 96(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
leaq .LC21(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE28:
leaq 96(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movl $0, %eax
.L62:
movq 616(%rsp), %rdx
subq %fs:40, %rdx
jne .L128
addq $632, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L100:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L82:
movq %rbx, %rdi
call __cxa_begin_catch@PLT
leaq .LC22(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB29:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L129
.L102:
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
jmp .L82
.L103:
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
jmp .L82
.L104:
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
jmp .L82
.L105:
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
jmp .L82
.L106:
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
jmp .L82
.L107:
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
jmp .L82
.L101:
endbr64
movq %rax, %rbx
jmp .L82
.L129:
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE29:
.LEHB30:
call __cxa_end_catch@PLT
.LEHE30:
movl $1, %eax
jmp .L62
.L108:
endbr64
movq %rax, %rbx
call __cxa_end_catch@PLT
movq 616(%rsp), %rax
subq %fs:40, %rax
je .L90
call __stack_chk_fail@PLT
.L90:
movq %rbx, %rdi
.LEHB31:
call _Unwind_Resume@PLT
.LEHE31:
.L109:
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L92:
movq %rbx, %rdi
call __cxa_begin_catch@PLT
leaq .LC22(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB32:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L130
.L111:
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
jmp .L92
.L112:
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
jmp .L92
.L110:
endbr64
movq %rax, %rbx
jmp .L92
.L130:
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE32:
.LEHB33:
call __cxa_end_catch@PLT
.LEHE33:
movl $1, %eax
jmp .L62
.L113:
endbr64
movq %rax, %rbx
call __cxa_end_catch@PLT
movq 616(%rsp), %rax
subq %fs:40, %rax
je .L96
call __stack_chk_fail@PLT
.L96:
movq %rbx, %rdi
.LEHB34:
call _Unwind_Resume@PLT
.L98:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE34:
.L128:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4282:
.section .gcc_except_table,"a",@progbits
.align 4
.LLSDA4282:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT4282-.LLSDATTD4282
.LLSDATTD4282:
.byte 0x1
.uleb128 .LLSDACSE4282-.LLSDACSB4282
.LLSDACSB4282:
.uleb128 .LEHB4-.LFB4282
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.uleb128 .LEHB5-.LFB4282
.uleb128 .LEHE5-.LEHB5
.uleb128 .L114-.LFB4282
.uleb128 0
.uleb128 .LEHB6-.LFB4282
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.uleb128 .LEHB7-.LFB4282
.uleb128 .LEHE7-.LEHB7
.uleb128 .L101-.LFB4282
.uleb128 0x1
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.uleb128 .LEHE8-.LEHB8
.uleb128 .L100-.LFB4282
.uleb128 0x3
.uleb128 .LEHB9-.LFB4282
.uleb128 .LEHE9-.LEHB9
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.uleb128 0x1
.uleb128 .LEHB10-.LFB4282
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.uleb128 0x3
.uleb128 .LEHB11-.LFB4282
.uleb128 .LEHE11-.LEHB11
.uleb128 .L101-.LFB4282
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.uleb128 .LEHE12-.LEHB12
.uleb128 .L103-.LFB4282
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.uleb128 .L104-.LFB4282
.uleb128 0x3
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.uleb128 .L106-.LFB4282
.uleb128 0x3
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.uleb128 .LEHE19-.LEHB19
.uleb128 .L101-.LFB4282
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.uleb128 .LEHE20-.LEHB20
.uleb128 .L107-.LFB4282
.uleb128 0x3
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.uleb128 .LEHE21-.LEHB21
.uleb128 .L110-.LFB4282
.uleb128 0x1
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.uleb128 .LEHE22-.LEHB22
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.uleb128 0x3
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.uleb128 .LEHE23-.LEHB23
.uleb128 .L110-.LFB4282
.uleb128 0x1
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.uleb128 .LEHE24-.LEHB24
.uleb128 .L111-.LFB4282
.uleb128 0x3
.uleb128 .LEHB25-.LFB4282
.uleb128 .LEHE25-.LEHB25
.uleb128 .L110-.LFB4282
.uleb128 0x1
.uleb128 .LEHB26-.LFB4282
.uleb128 .LEHE26-.LEHB26
.uleb128 .L112-.LFB4282
.uleb128 0x3
.uleb128 .LEHB27-.LFB4282
.uleb128 .LEHE27-.LEHB27
.uleb128 0
.uleb128 0
.uleb128 .LEHB28-.LFB4282
.uleb128 .LEHE28-.LEHB28
.uleb128 .L114-.LFB4282
.uleb128 0
.uleb128 .LEHB29-.LFB4282
.uleb128 .LEHE29-.LEHB29
.uleb128 .L108-.LFB4282
.uleb128 0
.uleb128 .LEHB30-.LFB4282
.uleb128 .LEHE30-.LEHB30
.uleb128 0
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.uleb128 .LEHB31-.LFB4282
.uleb128 .LEHE31-.LEHB31
.uleb128 0
.uleb128 0
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.uleb128 .LEHE32-.LEHB32
.uleb128 .L113-.LFB4282
.uleb128 0
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.uleb128 .LEHE33-.LEHB33
.uleb128 0
.uleb128 0
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.uleb128 .LEHE34-.LEHB34
.uleb128 0
.uleb128 0
.LLSDACSE4282:
.byte 0x1
.byte 0
.byte 0
.byte 0x7d
.align 4
.long 0
.LLSDATT4282:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long -1074790400
.align 8
.LC3:
.long 0
.long -1073741824
.align 8
.LC4:
.long 0
.long 1072693248
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <complex>
#include <cmath>
#include <iomanip>
#include <string>
#include <fstream>
using namespace std;
__global__
void z_funct(double * d_mat_re, double * d_mat_im, int *d_img, int nb_ite)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
double c_re = d_mat_re[i];
double c_im = d_mat_im[i];
double z_re = 0, z_im =0;
double z_re_tmp = 0;
int t=0;
while ((z_re*z_re+z_im*z_im <= 4) && (t<nb_ite))
{
z_re_tmp = z_re*z_re - z_im*z_im + c_re;
z_im = 2*z_im*z_re + c_im;
z_re = z_re_tmp;
t++;
}
d_img[i] = t;
}
int main(int argc, char * argv[])
{
if (argc == 1)
{
cout << "Help" << endl
<< " 8 args :" << endl << endl
<< "arg1 = min real part | arg2 = min imaginary part " << endl
<< "arg3 = max real part | arg4 = max imaginary part " << endl
<< "arg5 = number of points on the real axe | arg6 = number of points on the imaginary axe " << endl
<< "arg7 = nb of iterations | arg8 = limit convergence"
<< endl << endl
<< " 4 args :" << endl << endl
<< "arg1 = number of points on the real axe | arg2 = number of points on the imaginary axe " << endl
<< "arg3 = nb of iterations "
<< endl << endl ;
return 1;
}
double max_re, max_im, min_re, min_im;
int nb_pts_re, nb_pts_im, nb_ite;
if (argc == 8)
{
try
{
min_re = stod(argv[1]);
min_im = stod(argv[2]);
max_re = stod(argv[3]);
max_im = stod(argv[4]);
nb_pts_re = stoi(argv[5]);
nb_pts_im = stoi(argv[6]);
nb_ite = stoi(argv[7]);
}
catch (...)
{
cout << "Bad Args : see help (type nameofprogram without args)" << endl << endl;
return 1;
}
}
if (argc == 4 )
{
min_re = -2;
min_im = -1;
max_re = 1;
max_im = 1;
try
{
nb_pts_re = stoi(argv[1]);
nb_pts_im = stoi(argv[2]);
nb_ite = stoi(argv[3]);
}
catch (...)
{
cout << "Bad Args : see help (type nameofprogram without args)" << endl << endl;
return 1;
}
}
cout << "Initializing..." << endl;
int size_d = sizeof(double)*nb_pts_re*nb_pts_im;
int size_i = sizeof(int)*nb_pts_re*nb_pts_im;
double * mat_re = (double *)malloc(size_d);
double * mat_im = (double *)malloc(size_d);
double re, im;
for (int i=0; i<nb_pts_im; i++)
{
im = max_im - (max_im-min_im)/nb_pts_im*i;
for (int j=0; j<nb_pts_re; j++)
{
re = max_re - (max_re-min_re)/nb_pts_re*j;
mat_re[i*nb_pts_re+j] = re;
mat_im[i*nb_pts_re+j] = im;
}
}
double *d_mat_re, *d_mat_im;
int *d_img;
cudaMalloc(&d_mat_re,size_d);
cudaMalloc(&d_mat_im,size_d);
cudaMalloc(&d_img,size_i);
cudaMemcpy(d_mat_re, mat_re, size_d, cudaMemcpyHostToDevice);
cudaMemcpy(d_mat_im, mat_im, size_d, cudaMemcpyHostToDevice);
cout << "Running on GPU..." << endl;
dim3 blockDim = 1024;
dim3 gridDim = (nb_pts_re*nb_pts_im)/1024 + 1;
z_funct<<<gridDim,blockDim>>>(d_mat_re, d_mat_im, d_img, nb_ite);
cout << "Fetching datas..." << endl;
int * img = (int*) malloc(size_i);
cudaMemcpy(mat_re, d_mat_re, size_d, cudaMemcpyDeviceToHost);
cudaMemcpy(mat_im, d_mat_im, size_d, cudaMemcpyDeviceToHost);
cudaMemcpy(img, d_img, size_i, cudaMemcpyDeviceToHost);
cout << "Writing on the disk..." << endl;
ofstream file; file.open("conv");
for (int i=0; i<nb_pts_im; i++)
{
for (int j=0; j<nb_pts_re; j++)
{
file << setw(15) << img[i*nb_pts_re+j] ;
}
file << endl ;
}
file.close();
/*
file.open("val");
for (int i=0; i<nb_pts_im; i++)
{
for (int j=0; j<nb_pts_re; j++)
{
file << setw(15) << pow(mat_re[i*nb_pts_re+j],2) + pow(mat_im[i*nb_pts_re+j],2) ;
}
file << endl ;
}
file.close();
*/
cout << "Done !" << endl;
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <complex>
#include <cmath>
#include <iomanip>
#include <string>
#include <fstream>
using namespace std;
__global__
void z_funct(double * d_mat_re, double * d_mat_im, int *d_img, int nb_ite)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
double c_re = d_mat_re[i];
double c_im = d_mat_im[i];
double z_re = 0, z_im =0;
double z_re_tmp = 0;
int t=0;
while ((z_re*z_re+z_im*z_im <= 4) && (t<nb_ite))
{
z_re_tmp = z_re*z_re - z_im*z_im + c_re;
z_im = 2*z_im*z_re + c_im;
z_re = z_re_tmp;
t++;
}
d_img[i] = t;
}
int main(int argc, char * argv[])
{
if (argc == 1)
{
cout << "Help" << endl
<< " 8 args :" << endl << endl
<< "arg1 = min real part | arg2 = min imaginary part " << endl
<< "arg3 = max real part | arg4 = max imaginary part " << endl
<< "arg5 = number of points on the real axe | arg6 = number of points on the imaginary axe " << endl
<< "arg7 = nb of iterations | arg8 = limit convergence"
<< endl << endl
<< " 4 args :" << endl << endl
<< "arg1 = number of points on the real axe | arg2 = number of points on the imaginary axe " << endl
<< "arg3 = nb of iterations "
<< endl << endl ;
return 1;
}
double max_re, max_im, min_re, min_im;
int nb_pts_re, nb_pts_im, nb_ite;
if (argc == 8)
{
try
{
min_re = stod(argv[1]);
min_im = stod(argv[2]);
max_re = stod(argv[3]);
max_im = stod(argv[4]);
nb_pts_re = stoi(argv[5]);
nb_pts_im = stoi(argv[6]);
nb_ite = stoi(argv[7]);
}
catch (...)
{
cout << "Bad Args : see help (type nameofprogram without args)" << endl << endl;
return 1;
}
}
if (argc == 4 )
{
min_re = -2;
min_im = -1;
max_re = 1;
max_im = 1;
try
{
nb_pts_re = stoi(argv[1]);
nb_pts_im = stoi(argv[2]);
nb_ite = stoi(argv[3]);
}
catch (...)
{
cout << "Bad Args : see help (type nameofprogram without args)" << endl << endl;
return 1;
}
}
cout << "Initializing..." << endl;
int size_d = sizeof(double)*nb_pts_re*nb_pts_im;
int size_i = sizeof(int)*nb_pts_re*nb_pts_im;
double * mat_re = (double *)malloc(size_d);
double * mat_im = (double *)malloc(size_d);
double re, im;
for (int i=0; i<nb_pts_im; i++)
{
im = max_im - (max_im-min_im)/nb_pts_im*i;
for (int j=0; j<nb_pts_re; j++)
{
re = max_re - (max_re-min_re)/nb_pts_re*j;
mat_re[i*nb_pts_re+j] = re;
mat_im[i*nb_pts_re+j] = im;
}
}
double *d_mat_re, *d_mat_im;
int *d_img;
hipMalloc(&d_mat_re,size_d);
hipMalloc(&d_mat_im,size_d);
hipMalloc(&d_img,size_i);
hipMemcpy(d_mat_re, mat_re, size_d, hipMemcpyHostToDevice);
hipMemcpy(d_mat_im, mat_im, size_d, hipMemcpyHostToDevice);
cout << "Running on GPU..." << endl;
dim3 blockDim = 1024;
dim3 gridDim = (nb_pts_re*nb_pts_im)/1024 + 1;
z_funct<<<gridDim,blockDim>>>(d_mat_re, d_mat_im, d_img, nb_ite);
cout << "Fetching datas..." << endl;
int * img = (int*) malloc(size_i);
hipMemcpy(mat_re, d_mat_re, size_d, hipMemcpyDeviceToHost);
hipMemcpy(mat_im, d_mat_im, size_d, hipMemcpyDeviceToHost);
hipMemcpy(img, d_img, size_i, hipMemcpyDeviceToHost);
cout << "Writing on the disk..." << endl;
ofstream file; file.open("conv");
for (int i=0; i<nb_pts_im; i++)
{
for (int j=0; j<nb_pts_re; j++)
{
file << setw(15) << img[i*nb_pts_re+j] ;
}
file << endl ;
}
file.close();
/*
file.open("val");
for (int i=0; i<nb_pts_im; i++)
{
for (int j=0; j<nb_pts_re; j++)
{
file << setw(15) << pow(mat_re[i*nb_pts_re+j],2) + pow(mat_im[i*nb_pts_re+j],2) ;
}
file << endl ;
}
file.close();
*/
cout << "Done !" << endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <complex>
#include <cmath>
#include <iomanip>
#include <string>
#include <fstream>
using namespace std;
__global__
void z_funct(double * d_mat_re, double * d_mat_im, int *d_img, int nb_ite)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
double c_re = d_mat_re[i];
double c_im = d_mat_im[i];
double z_re = 0, z_im =0;
double z_re_tmp = 0;
int t=0;
while ((z_re*z_re+z_im*z_im <= 4) && (t<nb_ite))
{
z_re_tmp = z_re*z_re - z_im*z_im + c_re;
z_im = 2*z_im*z_re + c_im;
z_re = z_re_tmp;
t++;
}
d_img[i] = t;
}
int main(int argc, char * argv[])
{
if (argc == 1)
{
cout << "Help" << endl
<< " 8 args :" << endl << endl
<< "arg1 = min real part | arg2 = min imaginary part " << endl
<< "arg3 = max real part | arg4 = max imaginary part " << endl
<< "arg5 = number of points on the real axe | arg6 = number of points on the imaginary axe " << endl
<< "arg7 = nb of iterations | arg8 = limit convergence"
<< endl << endl
<< " 4 args :" << endl << endl
<< "arg1 = number of points on the real axe | arg2 = number of points on the imaginary axe " << endl
<< "arg3 = nb of iterations "
<< endl << endl ;
return 1;
}
double max_re, max_im, min_re, min_im;
int nb_pts_re, nb_pts_im, nb_ite;
if (argc == 8)
{
try
{
min_re = stod(argv[1]);
min_im = stod(argv[2]);
max_re = stod(argv[3]);
max_im = stod(argv[4]);
nb_pts_re = stoi(argv[5]);
nb_pts_im = stoi(argv[6]);
nb_ite = stoi(argv[7]);
}
catch (...)
{
cout << "Bad Args : see help (type nameofprogram without args)" << endl << endl;
return 1;
}
}
if (argc == 4 )
{
min_re = -2;
min_im = -1;
max_re = 1;
max_im = 1;
try
{
nb_pts_re = stoi(argv[1]);
nb_pts_im = stoi(argv[2]);
nb_ite = stoi(argv[3]);
}
catch (...)
{
cout << "Bad Args : see help (type nameofprogram without args)" << endl << endl;
return 1;
}
}
cout << "Initializing..." << endl;
int size_d = sizeof(double)*nb_pts_re*nb_pts_im;
int size_i = sizeof(int)*nb_pts_re*nb_pts_im;
double * mat_re = (double *)malloc(size_d);
double * mat_im = (double *)malloc(size_d);
double re, im;
for (int i=0; i<nb_pts_im; i++)
{
im = max_im - (max_im-min_im)/nb_pts_im*i;
for (int j=0; j<nb_pts_re; j++)
{
re = max_re - (max_re-min_re)/nb_pts_re*j;
mat_re[i*nb_pts_re+j] = re;
mat_im[i*nb_pts_re+j] = im;
}
}
double *d_mat_re, *d_mat_im;
int *d_img;
hipMalloc(&d_mat_re,size_d);
hipMalloc(&d_mat_im,size_d);
hipMalloc(&d_img,size_i);
hipMemcpy(d_mat_re, mat_re, size_d, hipMemcpyHostToDevice);
hipMemcpy(d_mat_im, mat_im, size_d, hipMemcpyHostToDevice);
cout << "Running on GPU..." << endl;
dim3 blockDim = 1024;
dim3 gridDim = (nb_pts_re*nb_pts_im)/1024 + 1;
z_funct<<<gridDim,blockDim>>>(d_mat_re, d_mat_im, d_img, nb_ite);
cout << "Fetching datas..." << endl;
int * img = (int*) malloc(size_i);
hipMemcpy(mat_re, d_mat_re, size_d, hipMemcpyDeviceToHost);
hipMemcpy(mat_im, d_mat_im, size_d, hipMemcpyDeviceToHost);
hipMemcpy(img, d_img, size_i, hipMemcpyDeviceToHost);
cout << "Writing on the disk..." << endl;
ofstream file; file.open("conv");
for (int i=0; i<nb_pts_im; i++)
{
for (int j=0; j<nb_pts_re; j++)
{
file << setw(15) << img[i*nb_pts_re+j] ;
}
file << endl ;
}
file.close();
/*
file.open("val");
for (int i=0; i<nb_pts_im; i++)
{
for (int j=0; j<nb_pts_re; j++)
{
file << setw(15) << pow(mat_re[i*nb_pts_re+j],2) + pow(mat_im[i*nb_pts_re+j],2) ;
}
file << endl ;
}
file.close();
*/
cout << "Done !" << endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7z_functPdS_Pii
.globl _Z7z_functPdS_Pii
.p2align 8
.type _Z7z_functPdS_Pii,@function
_Z7z_functPdS_Pii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_cmp_lt_i32 s2, 1
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[1:2]
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v4, vcc_lo
s_mov_b32 s4, 0
global_load_b64 v[3:4], v[5:6], off
global_load_b64 v[5:6], v[7:8], off
v_mov_b32_e32 v7, 0
v_mov_b32_e32 v8, 0
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v12, v8 :: v_dual_mov_b32 v11, v7
v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v9, v7
v_dual_mov_b32 v14, v8 :: v_dual_mov_b32 v13, v7
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[9:10], v[9:10], v[9:10]
v_add_f64 v[7:8], v[11:12], -v[7:8]
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
s_cmp_ge_i32 s4, s2
v_mov_b32_e32 v0, s4
s_cselect_b32 s5, -1, 0
s_waitcnt vmcnt(0)
v_fma_f64 v[9:10], v[13:14], v[9:10], v[5:6]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[13:14], v[3:4], v[7:8]
v_mul_f64 v[7:8], v[9:10], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], v[13:14], v[13:14], v[7:8]
v_cmp_nge_f64_e32 vcc_lo, 4.0, v[11:12]
v_mul_f64 v[11:12], v[13:14], v[13:14]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s5, exec_lo, s5
s_or_b32 s3, s5, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v0, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7z_functPdS_Pii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7z_functPdS_Pii, .Lfunc_end0-_Z7z_functPdS_Pii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7z_functPdS_Pii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7z_functPdS_Pii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7z_functPdS_Pii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R19, -RZ, RZ, 0, 0 ; /* 0x00000000ff137435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0080*/ SHF.R.S32.HI R3, RZ, 0x1f, R6 ; /* 0x0000001fff037819 */
/* 0x000fe40000011406 */
/*0090*/ LEA R2, P1, R6, c[0x0][0x170], 0x2 ; /* 0x00005c0006027a11 */
/* 0x000fc800078210ff */
/*00a0*/ LEA.HI.X R3, R6, c[0x0][0x174], R3, 0x2, P1 ; /* 0x00005d0006037a11 */
/* 0x000fe200008f1403 */
/*00b0*/ @!P0 BRA 0x250 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fc800078e00ff */
/*00d0*/ IMAD.WIDE R4, R6, R7, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fe400078e0207 */
/*00f0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000f68000c1e1b00 */
/*0100*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f62000c1e1b00 */
/*0110*/ BSSY B0, 0x250 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*0120*/ MOV R19, RZ ; /* 0x000000ff00137202 */
/* 0x000fe20000000f00 */
/*0130*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*0140*/ CS2R R10, SRZ ; /* 0x00000000000a7805 */
/* 0x000fe2000001ff00 */
/*0150*/ CS2R R12, SRZ ; /* 0x00000000000c7805 */
/* 0x000fe2000001ff00 */
/*0160*/ CS2R R14, SRZ ; /* 0x00000000000e7805 */
/* 0x000fc8000001ff00 */
/*0170*/ DADD R8, R10, -R8 ; /* 0x000000000a087229 */
/* 0x000e220000000808 */
/*0180*/ IADD3 R19, R19, 0x1, RZ ; /* 0x0000000113137810 */
/* 0x000fc60007ffe0ff */
/*0190*/ DADD R12, R12, R12 ; /* 0x000000000c0c7229 */
/* 0x000e62000000000c */
/*01a0*/ ISETP.GE.AND P0, PT, R19, c[0x0][0x178], PT ; /* 0x00005e0013007a0c */
/* 0x000fc60003f06270 */
/*01b0*/ DADD R16, R4, R8 ; /* 0x0000000004107229 */
/* 0x021e080000000008 */
/*01c0*/ DFMA R12, R12, R14, R6 ; /* 0x0000000e0c0c722b */
/* 0x002e480000000006 */
/*01d0*/ DMUL R10, R16, R16 ; /* 0x00000010100a7228 */
/* 0x001fc80000000000 */
/*01e0*/ DMUL R8, R12, R12 ; /* 0x0000000c0c087228 */
/* 0x002e0c0000000000 */
/*01f0*/ DADD R14, R10, R8 ; /* 0x000000000a0e7229 */
/* 0x001e0c0000000008 */
/*0200*/ DSETP.LE.AND P1, PT, R14, 4, PT ; /* 0x401000000e00742a */
/* 0x0010640003f23000 */
/*0210*/ IMAD.MOV.U32 R14, RZ, RZ, R16 ; /* 0x000000ffff0e7224 */
/* 0x001fe200078e0010 */
/*0220*/ MOV R15, R17 ; /* 0x00000011000f7202 */
/* 0x000fd60000000f00 */
/*0230*/ @!P0 BRA P1, 0x170 ; /* 0xffffff3000008947 */
/* 0x002fea000083ffff */
/*0240*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0250*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x000fe2000c101904 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7z_functPdS_Pii
.globl _Z7z_functPdS_Pii
.p2align 8
.type _Z7z_functPdS_Pii,@function
_Z7z_functPdS_Pii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_cmp_lt_i32 s2, 1
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[1:2]
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v4, vcc_lo
s_mov_b32 s4, 0
global_load_b64 v[3:4], v[5:6], off
global_load_b64 v[5:6], v[7:8], off
v_mov_b32_e32 v7, 0
v_mov_b32_e32 v8, 0
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v12, v8 :: v_dual_mov_b32 v11, v7
v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v9, v7
v_dual_mov_b32 v14, v8 :: v_dual_mov_b32 v13, v7
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[9:10], v[9:10], v[9:10]
v_add_f64 v[7:8], v[11:12], -v[7:8]
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
s_cmp_ge_i32 s4, s2
v_mov_b32_e32 v0, s4
s_cselect_b32 s5, -1, 0
s_waitcnt vmcnt(0)
v_fma_f64 v[9:10], v[13:14], v[9:10], v[5:6]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[13:14], v[3:4], v[7:8]
v_mul_f64 v[7:8], v[9:10], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], v[13:14], v[13:14], v[7:8]
v_cmp_nge_f64_e32 vcc_lo, 4.0, v[11:12]
v_mul_f64 v[11:12], v[13:14], v[13:14]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s5, exec_lo, s5
s_or_b32 s3, s5, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v0, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7z_functPdS_Pii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7z_functPdS_Pii, .Lfunc_end0-_Z7z_functPdS_Pii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7z_functPdS_Pii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7z_functPdS_Pii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <math.h>
void __global__ kernel_linearInterpolation(float* array_device, int* rowArray, int rowArrayLength, int col, int colArrayLength, int totalCols, int totalRows, float* originalTimes, int originalTimesLength, float* newTimes, int newTimesLength, float* results_device)
{
// where original times and new times should probably be unix time? but technically won't matter probably
int n = blockIdx.x * blockDim.x + threadIdx.x;
//int m = blockIdx.y * blockDim.y + threadIdx.y;
int m = col;
if (n < newTimesLength && m < colArrayLength)
{
// so we created a row-wise thread per element in the newTimes, with m being number of columns
float newTime = newTimes[n];
int resultsInd = n*colArrayLength + m;
// need to potentially handle the first and last points in a special way ,,,
if (n==0 && newTimes[0] < originalTimes[0])
{
// lets say if newTimes[0] is prior to originalTimes[0] less than the distance from originalTimes[1] to originalTimes[2], we'll accept it
// otherwise call it a NaN
if ( originalTimes[0] - newTimes[0] < originalTimes[1] - originalTimes[0] )
{
// continue slope from points 0 to 1?
// ie assume there's a previous point at same slope and same sample rate
int arrayInd1 = (0)*totalCols + m;
int arrayInd2 = (1)*totalCols + m;
float valueChange = array_device[arrayInd2] - array_device[arrayInd1];
float timeDiff = originalTimes[1] - originalTimes[0];
float pseudoPointTime = originalTimes[0] - timeDiff;
float pseudoPointValue = array_device[arrayInd1] - valueChange;
float perc = (newTime - pseudoPointTime) / timeDiff;
results_device[resultsInd] = pseudoPointValue + perc*valueChange;
}
else
results_device[resultsInd] = NAN;
return;
}
// ================================================
// ================================================
// ===== DO THIS SAME LOGIC FOR LAST POINT? =======
// ================================================
// ================================================
// we now need to find the points before and after ...
// do we need to iterate through the entire originalTimes vector or is there some way we can approximate the starting location?
//float origSampleRate = (originalTimes[originalTimesLength-1] - originalTimes[0]) / originalTimesLength;
//float newSampleRate = (newTimes[newTimesLength-1] - newTimes[0]) / newTimesLength;
//int originalTimeLoc = (newTime - newTimes[0]) / (originalTimes[originalTimesLength-1] - originalTimes)
float newTimePerc = (newTime - newTimes[0]) / (newTimes[newTimesLength-1] - newTimes[0]);
int estimation = newTimePerc * originalTimesLength; // start at approximately the correct point
int iterationsToFindMatch = 0;
int originalTimeLoc;
if (originalTimes[estimation] > newTime)
{
// time we guessed is greater than the time we want ... so walk backwards?
for (originalTimeLoc=estimation; originalTimeLoc>0; originalTimeLoc--)
{
if (originalTimes[originalTimeLoc] < newTime)
break;
iterationsToFindMatch++;
}
}
else
{
// the time we guessed is greater than the time we want ... so walk forwards?
for (originalTimeLoc=estimation; originalTimeLoc<originalTimesLength; originalTimeLoc++)
{
if (originalTimes[originalTimeLoc] > newTime)
{
originalTimeLoc--; // want the left side point
break;
}
iterationsToFindMatch++;
}
}
printf("Loc %i needed %i iterations, starting from %i -> %i\n", n, iterationsToFindMatch, estimation, originalTimeLoc);
int arrayInd1 = originalTimeLoc*totalCols + m;
int arrayInd2 = (originalTimeLoc+1)*totalCols + m;
float valueChange = (array_device[arrayInd2] - array_device[arrayInd1]);
// we need to figure out what percentage the newTime is between the two points
float origTime1 = originalTimes[originalTimeLoc];
float origTime2 = originalTimes[originalTimeLoc+1];
float perc = (newTime - origTime1) / (origTime2 - origTime1);
results_device[resultsInd] = array_device[arrayInd1] + perc*valueChange;
}
} | code for sm_80
Function : _Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc600078e00ff */
/*0010*/ S2R R16, SR_CTAID.X ; /* 0x0000000000107919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff077624 */
/* 0x000fe200078e00ff */
/*0030*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */
/* 0x000fe40007ffe0ff */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R16, R16, c[0x0][0x0], R3 ; /* 0x0000000010107a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R16, c[0x0][0x1a0], PT ; /* 0x0000680010007a0c */
/* 0x000fc80003f06270 */
/*0070*/ ISETP.GE.OR P0, PT, R7, c[0x0][0x178], P0 ; /* 0x00005e0007007a0c */
/* 0x000fda0000706670 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*00a0*/ MOV R3, c[0x0][0x19c] ; /* 0x0000670000037a02 */
/* 0x000fe20000000f00 */
/*00b0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x198] ; /* 0x00006600ff027624 */
/* 0x000fe200078e00ff */
/*00c0*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ IMAD.WIDE R24, R16, R9, c[0x0][0x198] ; /* 0x0000660010187625 */
/* 0x000fc600078e0209 */
/*00e0*/ LDG.E R5, [R2.64] ; /* 0x0000002402057981 */
/* 0x000168000c1e1900 */
/*00f0*/ LDG.E R24, [R24.64] ; /* 0x0000002418187981 */
/* 0x000162000c1e1900 */
/*0100*/ ISETP.NE.AND P0, PT, R16.reuse, RZ, PT ; /* 0x000000ff1000720c */
/* 0x040fe20003f05270 */
/*0110*/ IMAD R22, R16, c[0x0][0x178], R7 ; /* 0x00005e0010167a24 */
/* 0x000fe200078e0207 */
/*0120*/ BSSY B0, 0x1b0 ; /* 0x0000008000007945 */
/* 0x000fe60003800000 */
/*0130*/ IMAD.WIDE R22, R22, R9, c[0x0][0x1a8] ; /* 0x00006a0016167625 */
/* 0x000fd000078e0209 */
/*0140*/ @P0 BRA 0x1a0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0150*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff027624 */
/* 0x001fe400078e00ff */
/*0160*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff037624 */
/* 0x000fca00078e00ff */
/*0170*/ LDG.E R0, [R2.64] ; /* 0x0000002402007981 */
/* 0x000ea4000c1e1900 */
/*0180*/ FSETP.GEU.AND P0, PT, R5, R0, PT ; /* 0x000000000500720b */
/* 0x024fda0003f0e000 */
/*0190*/ @!P0 BRA 0x890 ; /* 0x000006f000008947 */
/* 0x000fea0003800000 */
/*01a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*01b0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x1a0] ; /* 0x00006800ff027624 */
/* 0x000fca00078e00ff */
/*01c0*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fca0007ffe0ff */
/*01d0*/ IMAD.WIDE R2, R2, R9, c[0x0][0x198] ; /* 0x0000660002027625 */
/* 0x000fcc00078e0209 */
/*01e0*/ LDG.E R2, [R2.64] ; /* 0x0000002402027981 */
/* 0x000ea2000c1e1900 */
/*01f0*/ BSSY B0, 0x300 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*0200*/ FADD R0, -R5, R2 ; /* 0x0000000205007221 */
/* 0x024fe40000000100 */
/*0210*/ FADD R5, R24, -R5 ; /* 0x8000000518057221 */
/* 0x000fe40000000000 */
/*0220*/ MUFU.RCP R7, R0 ; /* 0x0000000000077308 */
/* 0x000e300000001000 */
/*0230*/ FCHK P0, R5, R0 ; /* 0x0000000005007302 */
/* 0x000e620000000000 */
/*0240*/ FFMA R4, -R0, R7, 1 ; /* 0x3f80000000047423 */
/* 0x001fc80000000107 */
/*0250*/ FFMA R4, R7, R4, R7 ; /* 0x0000000407047223 */
/* 0x000fc80000000007 */
/*0260*/ FFMA R7, R5, R4, RZ ; /* 0x0000000405077223 */
/* 0x000fc800000000ff */
/*0270*/ FFMA R6, -R0, R7, R5 ; /* 0x0000000700067223 */
/* 0x000fc80000000105 */
/*0280*/ FFMA R4, R4, R6, R7 ; /* 0x0000000604047223 */
/* 0x000fe20000000007 */
/*0290*/ @!P0 BRA 0x2f0 ; /* 0x0000005000008947 */
/* 0x002fea0003800000 */
/*02a0*/ IMAD.MOV.U32 R8, RZ, RZ, R5 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0005 */
/*02b0*/ MOV R7, R0 ; /* 0x0000000000077202 */
/* 0x000fe40000000f00 */
/*02c0*/ MOV R2, 0x2e0 ; /* 0x000002e000027802 */
/* 0x000fe40000000f00 */
/*02d0*/ CALL.REL.NOINC 0xab0 ; /* 0x000007d000007944 */
/* 0x000fea0003c00000 */
/*02e0*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0008 */
/*02f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0300*/ I2F R3, c[0x0][0x190] ; /* 0x0000640000037b06 */
/* 0x000e240000201400 */
/*0310*/ FMUL R4, R3, R4 ; /* 0x0000000403047220 */
/* 0x001fe40000400000 */
/*0320*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0330*/ F2I.TRUNC.NTZ R18, R4 ; /* 0x0000000400127305 */
/* 0x000e24000020f100 */
/*0340*/ IMAD.WIDE R2, R18, R3, c[0x0][0x188] ; /* 0x0000620012027625 */
/* 0x001fcc00078e0203 */
/*0350*/ LDG.E R3, [R2.64] ; /* 0x0000002402037981 */
/* 0x000ea2000c1e1900 */
/*0360*/ IADD3 R6, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f3e0ff */
/*0370*/ BSSY B0, 0x5d0 ; /* 0x0000025000007945 */
/* 0x000fe80003800000 */
/*0380*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff077624 */
/* 0x000fe200008e06ff */
/*0390*/ FSETP.GT.AND P0, PT, R3, R24, PT ; /* 0x000000180300720b */
/* 0x004fda0003f04000 */
/*03a0*/ @P0 BRA 0x4d0 ; /* 0x0000012000000947 */
/* 0x000fea0003800000 */
/*03b0*/ ISETP.GE.AND P0, PT, R18, c[0x0][0x190], PT ; /* 0x0000640012007a0c */
/* 0x000fe20003f06270 */
/*03c0*/ IMAD.MOV.U32 R17, RZ, RZ, RZ ; /* 0x000000ffff117224 */
/* 0x000fe200078e00ff */
/*03d0*/ MOV R19, R18 ; /* 0x0000001200137202 */
/* 0x000fd60000000f00 */
/*03e0*/ @P0 BRA 0x5c0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*03f0*/ IMAD.MOV.U32 R17, RZ, RZ, RZ ; /* 0x000000ffff117224 */
/* 0x000fe400078e00ff */
/*0400*/ IMAD.MOV.U32 R19, RZ, RZ, R18 ; /* 0x000000ffff137224 */
/* 0x000fe400078e0012 */
/*0410*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc800078e00ff */
/*0420*/ IMAD.WIDE R2, R19, R2, c[0x0][0x188] ; /* 0x0000620013027625 */
/* 0x000fcc00078e0202 */
/*0430*/ LDG.E R3, [R2.64] ; /* 0x0000002402037981 */
/* 0x000ea4000c1e1900 */
/*0440*/ FSETP.GT.AND P0, PT, R3, R24, PT ; /* 0x000000180300720b */
/* 0x004fda0003f04000 */
/*0450*/ @P0 BRA 0x4b0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0460*/ IADD3 R19, R19, 0x1, RZ ; /* 0x0000000113137810 */
/* 0x000fe40007ffe0ff */
/*0470*/ IADD3 R17, R17, 0x1, RZ ; /* 0x0000000111117810 */
/* 0x000fe40007ffe0ff */
/*0480*/ ISETP.GE.AND P0, PT, R19, c[0x0][0x190], PT ; /* 0x0000640013007a0c */
/* 0x000fda0003f06270 */
/*0490*/ @!P0 BRA 0x410 ; /* 0xffffff7000008947 */
/* 0x000fea000383ffff */
/*04a0*/ BRA 0x5c0 ; /* 0x0000011000007947 */
/* 0x000fea0003800000 */
/*04b0*/ IADD3 R19, R19, -0x1, RZ ; /* 0xffffffff13137810 */
/* 0x000fe20007ffe0ff */
/*04c0*/ BRA 0x5c0 ; /* 0x000000f000007947 */
/* 0x000fea0003800000 */
/*04d0*/ ISETP.GE.AND P0, PT, R18, 0x1, PT ; /* 0x000000011200780c */
/* 0x000fe20003f06270 */
/*04e0*/ IMAD.MOV.U32 R17, RZ, RZ, RZ ; /* 0x000000ffff117224 */
/* 0x000fe200078e00ff */
/*04f0*/ MOV R19, R18 ; /* 0x0000001200137202 */
/* 0x000fd60000000f00 */
/*0500*/ @!P0 BRA 0x5c0 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0510*/ IMAD.MOV.U32 R17, RZ, RZ, RZ ; /* 0x000000ffff117224 */
/* 0x000fe400078e00ff */
/*0520*/ IMAD.MOV.U32 R19, RZ, RZ, R18 ; /* 0x000000ffff137224 */
/* 0x000fe400078e0012 */
/*0530*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc800078e00ff */
/*0540*/ IMAD.WIDE R2, R19, R2, c[0x0][0x188] ; /* 0x0000620013027625 */
/* 0x000fcc00078e0202 */
/*0550*/ LDG.E R3, [R2.64] ; /* 0x0000002402037981 */
/* 0x000ea4000c1e1900 */
/*0560*/ FSETP.GEU.AND P0, PT, R3, R24, PT ; /* 0x000000180300720b */
/* 0x004fda0003f0e000 */
/*0570*/ @!P0 BRA 0x5c0 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0580*/ ISETP.GT.AND P0, PT, R19.reuse, 0x1, PT ; /* 0x000000011300780c */
/* 0x040fe40003f04270 */
/*0590*/ IADD3 R19, R19, -0x1, RZ ; /* 0xffffffff13137810 */
/* 0x000fe40007ffe0ff */
/*05a0*/ IADD3 R17, R17, 0x1, RZ ; /* 0x0000000111117810 */
/* 0x000fd20007ffe0ff */
/*05b0*/ @P0 BRA 0x530 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*05c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05d0*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*05e0*/ STL.128 [R1], R16 ; /* 0x0000001001007387 */
/* 0x0001e20000100c00 */
/*05f0*/ MOV R4, c[0x4][0x8] ; /* 0x0100020000047a02 */
/* 0x000fe20000000f00 */
/*0600*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fc600078e00ff */
/*0610*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e680000000a00 */
/*0620*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe20000000000 */
/*0630*/ MOV R11, 0x6a0 ; /* 0x000006a0000b7802 */
/* 0x000fe40000000f00 */
/*0640*/ MOV R20, 0x620 ; /* 0x0000062000147802 */
/* 0x000fe40000000f00 */
/*0650*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0660*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0670*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0680*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0690*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x003fea0003c00000 */
/*06a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*06b0*/ IMAD.WIDE R2, R19, R5, c[0x0][0x188] ; /* 0x0000620013027625 */
/* 0x000fca00078e0205 */
/*06c0*/ LDG.E R9, [R2.64] ; /* 0x0000002402097981 */
/* 0x000ea8000c1e1900 */
/*06d0*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000042402087981 */
/* 0x000ea2000c1e1900 */
/*06e0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff067624 */
/* 0x000fc800078e00ff */
/*06f0*/ IMAD R6, R19, R6, c[0x0][0x174] ; /* 0x00005d0013067624 */
/* 0x000fca00078e0206 */
/*0700*/ IADD3 R4, R6.reuse, c[0x0][0x17c], RZ ; /* 0x00005f0006047a10 */
/* 0x040fe20007ffe0ff */
/*0710*/ IMAD.WIDE R6, R6, R5, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0205 */
/*0720*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e0205 */
/*0730*/ LDG.E R0, [R6.64] ; /* 0x0000002406007981 */
/* 0x0004ea000c1e1900 */
/*0740*/ LDG.E R5, [R4.64] ; /* 0x0000002404057981 */
/* 0x000ee2000c1e1900 */
/*0750*/ BSSY B0, 0x860 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*0760*/ FADD R7, -R9, R8 ; /* 0x0000000809077221 */
/* 0x004fe40000000100 */
/*0770*/ FADD R9, R24, -R9 ; /* 0x8000000918097221 */
/* 0x000fc40000000000 */
/*0780*/ MUFU.RCP R8, R7 ; /* 0x0000000700087308 */
/* 0x000e300000001000 */
/*0790*/ FCHK P0, R9, R7 ; /* 0x0000000709007302 */
/* 0x000e620000000000 */
/*07a0*/ FFMA R11, -R7, R8, 1 ; /* 0x3f800000070b7423 */
/* 0x001fe40000000108 */
/*07b0*/ FADD R3, -R0, R5 ; /* 0x0000000500037221 */
/* 0x008fc40000000100 */
/*07c0*/ FFMA R11, R8, R11, R8 ; /* 0x0000000b080b7223 */
/* 0x000fc80000000008 */
/*07d0*/ FFMA R2, R9, R11, RZ ; /* 0x0000000b09027223 */
/* 0x000fc800000000ff */
/*07e0*/ FFMA R8, -R7, R2, R9 ; /* 0x0000000207087223 */
/* 0x000fc80000000109 */
/*07f0*/ FFMA R2, R11, R8, R2 ; /* 0x000000080b027223 */
/* 0x000fe20000000002 */
/*0800*/ @!P0 BRA 0x850 ; /* 0x0000004000008947 */
/* 0x002fea0003800000 */
/*0810*/ MOV R8, R9 ; /* 0x0000000900087202 */
/* 0x000fe40000000f00 */
/*0820*/ MOV R2, 0x840 ; /* 0x0000084000027802 */
/* 0x000fe40000000f00 */
/*0830*/ CALL.REL.NOINC 0xab0 ; /* 0x0000027000007944 */
/* 0x000fea0003c00000 */
/*0840*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0008 */
/*0850*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0860*/ FFMA R3, R3, R2, R0 ; /* 0x0000000203037223 */
/* 0x000fca0000000000 */
/*0870*/ STG.E [R22.64], R3 ; /* 0x0000000316007986 */
/* 0x000fe2000c101924 */
/*0880*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0890*/ LDG.E R3, [R2.64+0x4] ; /* 0x0000042402037981 */
/* 0x000ea2000c1e1900 */
/*08a0*/ FADD R5, -R5, R0 ; /* 0x0000000005057221 */
/* 0x000fe40000000100 */
/*08b0*/ FADD R6, -R0, R3 ; /* 0x0000000300067221 */
/* 0x004fca0000000100 */
/*08c0*/ FSETP.GEU.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fda0003f0e000 */
/*08d0*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, 0x7fc00000 ; /* 0x7fc00000ff050424 */
/* 0x000fca00078e00ff */
/*08e0*/ @P0 STG.E [R22.64], R5 ; /* 0x0000000516000986 */
/* 0x0001e2000c101924 */
/*08f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0900*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff027624 */
/* 0x000fe400078e00ff */
/*0910*/ IMAD.WIDE R4, R7, R9, c[0x0][0x160] ; /* 0x0000580007047625 */
/* 0x001fc600078e0209 */
/*0920*/ IADD3 R2, R2, c[0x0][0x174], RZ ; /* 0x00005d0002027a10 */
/* 0x000fc60007ffe0ff */
/*0930*/ LDG.E R5, [R4.64] ; /* 0x0000002404057981 */
/* 0x000ea4000c1e1900 */
/*0940*/ IMAD.WIDE R2, R2, R9, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0209 */
/*0950*/ LDG.E R2, [R2.64] ; /* 0x0000002402027981 */
/* 0x000ea2000c1e1900 */
/*0960*/ MUFU.RCP R9, R6 ; /* 0x0000000600097308 */
/* 0x000e220000001000 */
/*0970*/ FADD R7, R0, -R6 ; /* 0x8000000600077221 */
/* 0x000fc80000000000 */
/*0980*/ FADD R7, R24, -R7 ; /* 0x8000000718077221 */
/* 0x000fc80000000000 */
/*0990*/ FCHK P0, R7, R6 ; /* 0x0000000607007302 */
/* 0x000e620000000000 */
/*09a0*/ FFMA R0, -R6, R9, 1 ; /* 0x3f80000006007423 */
/* 0x001fc80000000109 */
/*09b0*/ FFMA R8, R9, R0, R9 ; /* 0x0000000009087223 */
/* 0x000fc80000000009 */
/*09c0*/ FFMA R9, R7, R8, RZ ; /* 0x0000000807097223 */
/* 0x000fe200000000ff */
/*09d0*/ BSSY B1, 0xa80 ; /* 0x000000a000017945 */
/* 0x000fe60003800000 */
/*09e0*/ FFMA R10, -R6, R9, R7 ; /* 0x00000009060a7223 */
/* 0x000fc80000000107 */
/*09f0*/ FFMA R8, R8, R10, R9 ; /* 0x0000000a08087223 */
/* 0x000fe40000000009 */
/*0a00*/ FADD R0, -R5, R2 ; /* 0x0000000205007221 */
/* 0x004fc80000000100 */
/*0a10*/ FADD R3, R5, -R0 ; /* 0x8000000005037221 */
/* 0x000fe20000000000 */
/*0a20*/ @!P0 BRA 0xa70 ; /* 0x0000004000008947 */
/* 0x002fea0003800000 */
/*0a30*/ MOV R8, R7 ; /* 0x0000000700087202 */
/* 0x000fe20000000f00 */
/*0a40*/ IMAD.MOV.U32 R7, RZ, RZ, R6 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0006 */
/*0a50*/ MOV R2, 0xa70 ; /* 0x00000a7000027802 */
/* 0x000fe40000000f00 */
/*0a60*/ CALL.REL.NOINC 0xab0 ; /* 0x0000004000007944 */
/* 0x000fea0003c00000 */
/*0a70*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0a80*/ FFMA R3, R0, R8, R3 ; /* 0x0000000800037223 */
/* 0x000fca0000000003 */
/*0a90*/ STG.E [R22.64], R3 ; /* 0x0000000316007986 */
/* 0x000fe2000c101924 */
/*0aa0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ab0*/ SHF.R.U32.HI R6, RZ, 0x17, R7 ; /* 0x00000017ff067819 */
/* 0x000fe20000011607 */
/*0ac0*/ BSSY B2, 0x1100 ; /* 0x0000063000027945 */
/* 0x000fe20003800000 */
/*0ad0*/ SHF.R.U32.HI R4, RZ, 0x17, R8.reuse ; /* 0x00000017ff047819 */
/* 0x100fe40000011608 */
/*0ae0*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fe400078ec0ff */
/*0af0*/ LOP3.LUT R10, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff040a7812 */
/* 0x000fe200078ec0ff */
/*0b00*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0008 */
/*0b10*/ IADD3 R11, R6, -0x1, RZ ; /* 0xffffffff060b7810 */
/* 0x000fe40007ffe0ff */
/*0b20*/ IADD3 R9, R10, -0x1, RZ ; /* 0xffffffff0a097810 */
/* 0x000fc40007ffe0ff */
/*0b30*/ ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; /* 0x000000fd0b00780c */
/* 0x000fc80003f04070 */
/*0b40*/ ISETP.GT.U32.OR P0, PT, R9, 0xfd, P0 ; /* 0x000000fd0900780c */
/* 0x000fda0000704470 */
/*0b50*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff058224 */
/* 0x000fe200078e00ff */
/*0b60*/ @!P0 BRA 0xce0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0b70*/ FSETP.GTU.FTZ.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fe40003f1c200 */
/*0b80*/ FSETP.GTU.FTZ.AND P1, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fc80003f3c200 */
/*0b90*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0ba0*/ @P0 BRA 0x10e0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0bb0*/ LOP3.LUT P0, RZ, R7, 0x7fffffff, R4, 0xc8, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fda000780c804 */
/*0bc0*/ @!P0 BRA 0x10c0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0bd0*/ FSETP.NEU.FTZ.AND P2, PT, |R8|.reuse, +INF , PT ; /* 0x7f8000000800780b */
/* 0x040fe40003f5d200 */
/*0be0*/ FSETP.NEU.FTZ.AND P1, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fe40003f3d200 */
/*0bf0*/ FSETP.NEU.FTZ.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fd60003f1d200 */
/*0c00*/ @!P1 BRA !P2, 0x10c0 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0c10*/ LOP3.LUT P2, RZ, R4, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff04ff7812 */
/* 0x000fc8000784c0ff */
/*0c20*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0c30*/ @P1 BRA 0x10a0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0c40*/ LOP3.LUT P1, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000782c0ff */
/*0c50*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0c60*/ @P0 BRA 0x1070 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0c70*/ ISETP.GE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f06270 */
/*0c80*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f26270 */
/*0c90*/ @P0 MOV R5, RZ ; /* 0x000000ff00050202 */
/* 0x000fe20000000f00 */
/*0ca0*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, -0x40 ; /* 0xffffffc0ff058424 */
/* 0x000fe400078e00ff */
/*0cb0*/ @!P0 FFMA R4, R8, 1.84467440737095516160e+19, RZ ; /* 0x5f80000008048823 */
/* 0x000fe400000000ff */
/*0cc0*/ @!P1 FFMA R7, R7, 1.84467440737095516160e+19, RZ ; /* 0x5f80000007079823 */
/* 0x000fe200000000ff */
/*0cd0*/ @!P1 IADD3 R5, R5, 0x40, RZ ; /* 0x0000004005059810 */
/* 0x000fe40007ffe0ff */
/*0ce0*/ LEA R8, R6, 0xc0800000, 0x17 ; /* 0xc080000006087811 */
/* 0x000fe200078eb8ff */
/*0cf0*/ BSSY B3, 0x1060 ; /* 0x0000036000037945 */
/* 0x000fe80003800000 */
/*0d00*/ IMAD.IADD R8, R7, 0x1, -R8 ; /* 0x0000000107087824 */
/* 0x000fe200078e0a08 */
/*0d10*/ IADD3 R7, R10, -0x7f, RZ ; /* 0xffffff810a077810 */
/* 0x000fc60007ffe0ff */
/*0d20*/ MUFU.RCP R9, R8 ; /* 0x0000000800097308 */
/* 0x0000620000001000 */
/*0d30*/ FADD.FTZ R11, -R8, -RZ ; /* 0x800000ff080b7221 */
/* 0x000fe40000010100 */
/*0d40*/ IMAD R4, R7.reuse, -0x800000, R4 ; /* 0xff80000007047824 */
/* 0x040fe200078e0204 */
/*0d50*/ IADD3 R8, R7, 0x7f, -R6 ; /* 0x0000007f07087810 */
/* 0x001fca0007ffe806 */
/*0d60*/ IMAD.IADD R5, R8, 0x1, R5 ; /* 0x0000000108057824 */
/* 0x000fe400078e0205 */
/*0d70*/ FFMA R10, R9, R11, 1 ; /* 0x3f800000090a7423 */
/* 0x002fc8000000000b */
/*0d80*/ FFMA R13, R9, R10, R9 ; /* 0x0000000a090d7223 */
/* 0x000fc80000000009 */
/*0d90*/ FFMA R9, R4, R13, RZ ; /* 0x0000000d04097223 */
/* 0x000fc800000000ff */
/*0da0*/ FFMA R10, R11, R9, R4 ; /* 0x000000090b0a7223 */
/* 0x000fc80000000004 */
/*0db0*/ FFMA R10, R13, R10, R9 ; /* 0x0000000a0d0a7223 */
/* 0x000fc80000000009 */
/*0dc0*/ FFMA R11, R11, R10, R4 ; /* 0x0000000a0b0b7223 */
/* 0x000fc80000000004 */
/*0dd0*/ FFMA R4, R13, R11, R10 ; /* 0x0000000b0d047223 */
/* 0x000fca000000000a */
/*0de0*/ SHF.R.U32.HI R6, RZ, 0x17, R4 ; /* 0x00000017ff067819 */
/* 0x000fc80000011604 */
/*0df0*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fc800078ec0ff */
/*0e00*/ IADD3 R9, R6, R5, RZ ; /* 0x0000000506097210 */
/* 0x000fc80007ffe0ff */
/*0e10*/ IADD3 R6, R9, -0x1, RZ ; /* 0xffffffff09067810 */
/* 0x000fc80007ffe0ff */
/*0e20*/ ISETP.GE.U32.AND P0, PT, R6, 0xfe, PT ; /* 0x000000fe0600780c */
/* 0x000fda0003f06070 */
/*0e30*/ @!P0 BRA 0x1040 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0e40*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*0e50*/ @P0 BRA 0x1010 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0e60*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*0e70*/ @P0 BRA 0x1050 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0e80*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*0e90*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fd600078ec0ff */
/*0ea0*/ @!P0 BRA 0x1050 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0eb0*/ FFMA.RZ R5, R13, R11.reuse, R10.reuse ; /* 0x0000000b0d057223 */
/* 0x180fe2000000c00a */
/*0ec0*/ IADD3 R8, R9, 0x20, RZ ; /* 0x0000002009087810 */
/* 0x000fe20007ffe0ff */
/*0ed0*/ FFMA.RM R6, R13, R11.reuse, R10.reuse ; /* 0x0000000b0d067223 */
/* 0x180fe2000000400a */
/*0ee0*/ ISETP.NE.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f45270 */
/*0ef0*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*0f00*/ FFMA.RP R5, R13, R11, R10 ; /* 0x0000000b0d057223 */
/* 0x000fe2000000800a */
/*0f10*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f25270 */
/*0f20*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a09 */
/*0f30*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*0f40*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fc40003f1d000 */
/*0f50*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*0f60*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*0f70*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*0f80*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*0f90*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0fa0*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*0fb0*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0fc0*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*0fd0*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*0fe0*/ IMAD.IADD R5, R8, 0x1, R5 ; /* 0x0000000108057824 */
/* 0x000fca00078e0205 */
/*0ff0*/ LOP3.LUT R4, R5, R4, RZ, 0xfc, !PT ; /* 0x0000000405047212 */
/* 0x000fe200078efcff */
/*1000*/ BRA 0x1050 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*1010*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fc800078ec0ff */
/*1020*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*1030*/ BRA 0x1050 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*1040*/ IMAD R4, R5, 0x800000, R4 ; /* 0x0080000005047824 */
/* 0x000fe400078e0204 */
/*1050*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*1060*/ BRA 0x10f0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*1070*/ LOP3.LUT R4, R7, 0x80000000, R4, 0x48, !PT ; /* 0x8000000007047812 */
/* 0x000fc800078e4804 */
/*1080*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*1090*/ BRA 0x10f0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*10a0*/ LOP3.LUT R4, R7, 0x80000000, R4, 0x48, !PT ; /* 0x8000000007047812 */
/* 0x000fe200078e4804 */
/*10b0*/ BRA 0x10f0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*10c0*/ MUFU.RSQ R4, -QNAN ; /* 0xffc0000000047908 */
/* 0x000e220000001400 */
/*10d0*/ BRA 0x10f0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*10e0*/ FADD.FTZ R4, R8, R7 ; /* 0x0000000708047221 */
/* 0x000fe40000010000 */
/*10f0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*1100*/ MOV R8, R4 ; /* 0x0000000400087202 */
/* 0x001fe20000000f00 */
/*1110*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0002 */
/*1120*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*1130*/ RET.REL.NODEC R4 0x0 ; /* 0xffffeec004007950 */
/* 0x000fea0003c3ffff */
/*1140*/ BRA 0x1140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <math.h>
void __global__ kernel_linearInterpolation(float* array_device, int* rowArray, int rowArrayLength, int col, int colArrayLength, int totalCols, int totalRows, float* originalTimes, int originalTimesLength, float* newTimes, int newTimesLength, float* results_device)
{
// where original times and new times should probably be unix time? but technically won't matter probably
int n = blockIdx.x * blockDim.x + threadIdx.x;
//int m = blockIdx.y * blockDim.y + threadIdx.y;
int m = col;
if (n < newTimesLength && m < colArrayLength)
{
// so we created a row-wise thread per element in the newTimes, with m being number of columns
float newTime = newTimes[n];
int resultsInd = n*colArrayLength + m;
// need to potentially handle the first and last points in a special way ,,,
if (n==0 && newTimes[0] < originalTimes[0])
{
// lets say if newTimes[0] is prior to originalTimes[0] less than the distance from originalTimes[1] to originalTimes[2], we'll accept it
// otherwise call it a NaN
if ( originalTimes[0] - newTimes[0] < originalTimes[1] - originalTimes[0] )
{
// continue slope from points 0 to 1?
// ie assume there's a previous point at same slope and same sample rate
int arrayInd1 = (0)*totalCols + m;
int arrayInd2 = (1)*totalCols + m;
float valueChange = array_device[arrayInd2] - array_device[arrayInd1];
float timeDiff = originalTimes[1] - originalTimes[0];
float pseudoPointTime = originalTimes[0] - timeDiff;
float pseudoPointValue = array_device[arrayInd1] - valueChange;
float perc = (newTime - pseudoPointTime) / timeDiff;
results_device[resultsInd] = pseudoPointValue + perc*valueChange;
}
else
results_device[resultsInd] = NAN;
return;
}
// ================================================
// ================================================
// ===== DO THIS SAME LOGIC FOR LAST POINT? =======
// ================================================
// ================================================
// we now need to find the points before and after ...
// do we need to iterate through the entire originalTimes vector or is there some way we can approximate the starting location?
//float origSampleRate = (originalTimes[originalTimesLength-1] - originalTimes[0]) / originalTimesLength;
//float newSampleRate = (newTimes[newTimesLength-1] - newTimes[0]) / newTimesLength;
//int originalTimeLoc = (newTime - newTimes[0]) / (originalTimes[originalTimesLength-1] - originalTimes)
float newTimePerc = (newTime - newTimes[0]) / (newTimes[newTimesLength-1] - newTimes[0]);
int estimation = newTimePerc * originalTimesLength; // start at approximately the correct point
int iterationsToFindMatch = 0;
int originalTimeLoc;
if (originalTimes[estimation] > newTime)
{
// time we guessed is greater than the time we want ... so walk backwards?
for (originalTimeLoc=estimation; originalTimeLoc>0; originalTimeLoc--)
{
if (originalTimes[originalTimeLoc] < newTime)
break;
iterationsToFindMatch++;
}
}
else
{
// the time we guessed is greater than the time we want ... so walk forwards?
for (originalTimeLoc=estimation; originalTimeLoc<originalTimesLength; originalTimeLoc++)
{
if (originalTimes[originalTimeLoc] > newTime)
{
originalTimeLoc--; // want the left side point
break;
}
iterationsToFindMatch++;
}
}
printf("Loc %i needed %i iterations, starting from %i -> %i\n", n, iterationsToFindMatch, estimation, originalTimeLoc);
int arrayInd1 = originalTimeLoc*totalCols + m;
int arrayInd2 = (originalTimeLoc+1)*totalCols + m;
float valueChange = (array_device[arrayInd2] - array_device[arrayInd1]);
// we need to figure out what percentage the newTime is between the two points
float origTime1 = originalTimes[originalTimeLoc];
float origTime2 = originalTimes[originalTimeLoc+1];
float perc = (newTime - origTime1) / (origTime2 - origTime1);
results_device[resultsInd] = array_device[arrayInd1] + perc*valueChange;
}
} | .file "tmpxft_0012dc61_00000000-6_kernel_interpolate.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z61__device_stub__Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_PfPiiiiiiS_iS_iS_
.type _Z61__device_stub__Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_PfPiiiiiiS_iS_iS_, @function
_Z61__device_stub__Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_PfPiiiiiiS_iS_iS_:
.LFB2081:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movl %edx, 44(%rsp)
movl %ecx, 40(%rsp)
movl %r8d, 36(%rsp)
movl %r9d, 32(%rsp)
movq 264(%rsp), %rax
movq %rax, 24(%rsp)
movq 280(%rsp), %rax
movq %rax, 16(%rsp)
movq 296(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 36(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 24(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 288(%rsp), %rax
movq %rax, 208(%rsp)
leaq 8(%rsp), %rax
movq %rax, 216(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 264
pushq 72(%rsp)
.cfi_def_cfa_offset 272
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z61__device_stub__Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_PfPiiiiiiS_iS_iS_, .-_Z61__device_stub__Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_PfPiiiiiiS_iS_iS_
.globl _Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_
.type _Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_, @function
_Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 56(%rsp)
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z61__device_stub__Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_PfPiiiiiiS_iS_iS_
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_, .-_Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <math.h>
void __global__ kernel_linearInterpolation(float* array_device, int* rowArray, int rowArrayLength, int col, int colArrayLength, int totalCols, int totalRows, float* originalTimes, int originalTimesLength, float* newTimes, int newTimesLength, float* results_device)
{
// where original times and new times should probably be unix time? but technically won't matter probably
int n = blockIdx.x * blockDim.x + threadIdx.x;
//int m = blockIdx.y * blockDim.y + threadIdx.y;
int m = col;
if (n < newTimesLength && m < colArrayLength)
{
// so we created a row-wise thread per element in the newTimes, with m being number of columns
float newTime = newTimes[n];
int resultsInd = n*colArrayLength + m;
// need to potentially handle the first and last points in a special way ,,,
if (n==0 && newTimes[0] < originalTimes[0])
{
// lets say if newTimes[0] is prior to originalTimes[0] less than the distance from originalTimes[1] to originalTimes[2], we'll accept it
// otherwise call it a NaN
if ( originalTimes[0] - newTimes[0] < originalTimes[1] - originalTimes[0] )
{
// continue slope from points 0 to 1?
// ie assume there's a previous point at same slope and same sample rate
int arrayInd1 = (0)*totalCols + m;
int arrayInd2 = (1)*totalCols + m;
float valueChange = array_device[arrayInd2] - array_device[arrayInd1];
float timeDiff = originalTimes[1] - originalTimes[0];
float pseudoPointTime = originalTimes[0] - timeDiff;
float pseudoPointValue = array_device[arrayInd1] - valueChange;
float perc = (newTime - pseudoPointTime) / timeDiff;
results_device[resultsInd] = pseudoPointValue + perc*valueChange;
}
else
results_device[resultsInd] = NAN;
return;
}
// ================================================
// ================================================
// ===== DO THIS SAME LOGIC FOR LAST POINT? =======
// ================================================
// ================================================
// we now need to find the points before and after ...
// do we need to iterate through the entire originalTimes vector or is there some way we can approximate the starting location?
//float origSampleRate = (originalTimes[originalTimesLength-1] - originalTimes[0]) / originalTimesLength;
//float newSampleRate = (newTimes[newTimesLength-1] - newTimes[0]) / newTimesLength;
//int originalTimeLoc = (newTime - newTimes[0]) / (originalTimes[originalTimesLength-1] - originalTimes)
float newTimePerc = (newTime - newTimes[0]) / (newTimes[newTimesLength-1] - newTimes[0]);
int estimation = newTimePerc * originalTimesLength; // start at approximately the correct point
int iterationsToFindMatch = 0;
int originalTimeLoc;
if (originalTimes[estimation] > newTime)
{
// time we guessed is greater than the time we want ... so walk backwards?
for (originalTimeLoc=estimation; originalTimeLoc>0; originalTimeLoc--)
{
if (originalTimes[originalTimeLoc] < newTime)
break;
iterationsToFindMatch++;
}
}
else
{
// the time we guessed is greater than the time we want ... so walk forwards?
for (originalTimeLoc=estimation; originalTimeLoc<originalTimesLength; originalTimeLoc++)
{
if (originalTimes[originalTimeLoc] > newTime)
{
originalTimeLoc--; // want the left side point
break;
}
iterationsToFindMatch++;
}
}
printf("Loc %i needed %i iterations, starting from %i -> %i\n", n, iterationsToFindMatch, estimation, originalTimeLoc);
int arrayInd1 = originalTimeLoc*totalCols + m;
int arrayInd2 = (originalTimeLoc+1)*totalCols + m;
float valueChange = (array_device[arrayInd2] - array_device[arrayInd1]);
// we need to figure out what percentage the newTime is between the two points
float origTime1 = originalTimes[originalTimeLoc];
float origTime2 = originalTimes[originalTimeLoc+1];
float perc = (newTime - origTime1) / (origTime2 - origTime1);
results_device[resultsInd] = array_device[arrayInd1] + perc*valueChange;
}
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
void __global__ kernel_linearInterpolation(float* array_device, int* rowArray, int rowArrayLength, int col, int colArrayLength, int totalCols, int totalRows, float* originalTimes, int originalTimesLength, float* newTimes, int newTimesLength, float* results_device)
{
// where original times and new times should probably be unix time? but technically won't matter probably
int n = blockIdx.x * blockDim.x + threadIdx.x;
//int m = blockIdx.y * blockDim.y + threadIdx.y;
int m = col;
if (n < newTimesLength && m < colArrayLength)
{
// so we created a row-wise thread per element in the newTimes, with m being number of columns
float newTime = newTimes[n];
int resultsInd = n*colArrayLength + m;
// need to potentially handle the first and last points in a special way ,,,
if (n==0 && newTimes[0] < originalTimes[0])
{
// lets say if newTimes[0] is prior to originalTimes[0] less than the distance from originalTimes[1] to originalTimes[2], we'll accept it
// otherwise call it a NaN
if ( originalTimes[0] - newTimes[0] < originalTimes[1] - originalTimes[0] )
{
// continue slope from points 0 to 1?
// ie assume there's a previous point at same slope and same sample rate
int arrayInd1 = (0)*totalCols + m;
int arrayInd2 = (1)*totalCols + m;
float valueChange = array_device[arrayInd2] - array_device[arrayInd1];
float timeDiff = originalTimes[1] - originalTimes[0];
float pseudoPointTime = originalTimes[0] - timeDiff;
float pseudoPointValue = array_device[arrayInd1] - valueChange;
float perc = (newTime - pseudoPointTime) / timeDiff;
results_device[resultsInd] = pseudoPointValue + perc*valueChange;
}
else
results_device[resultsInd] = NAN;
return;
}
// ================================================
// ================================================
// ===== DO THIS SAME LOGIC FOR LAST POINT? =======
// ================================================
// ================================================
// we now need to find the points before and after ...
// do we need to iterate through the entire originalTimes vector or is there some way we can approximate the starting location?
//float origSampleRate = (originalTimes[originalTimesLength-1] - originalTimes[0]) / originalTimesLength;
//float newSampleRate = (newTimes[newTimesLength-1] - newTimes[0]) / newTimesLength;
//int originalTimeLoc = (newTime - newTimes[0]) / (originalTimes[originalTimesLength-1] - originalTimes)
float newTimePerc = (newTime - newTimes[0]) / (newTimes[newTimesLength-1] - newTimes[0]);
int estimation = newTimePerc * originalTimesLength; // start at approximately the correct point
int iterationsToFindMatch = 0;
int originalTimeLoc;
if (originalTimes[estimation] > newTime)
{
// time we guessed is greater than the time we want ... so walk backwards?
for (originalTimeLoc=estimation; originalTimeLoc>0; originalTimeLoc--)
{
if (originalTimes[originalTimeLoc] < newTime)
break;
iterationsToFindMatch++;
}
}
else
{
// the time we guessed is greater than the time we want ... so walk forwards?
for (originalTimeLoc=estimation; originalTimeLoc<originalTimesLength; originalTimeLoc++)
{
if (originalTimes[originalTimeLoc] > newTime)
{
originalTimeLoc--; // want the left side point
break;
}
iterationsToFindMatch++;
}
}
printf("Loc %i needed %i iterations, starting from %i -> %i\n", n, iterationsToFindMatch, estimation, originalTimeLoc);
int arrayInd1 = originalTimeLoc*totalCols + m;
int arrayInd2 = (originalTimeLoc+1)*totalCols + m;
float valueChange = (array_device[arrayInd2] - array_device[arrayInd1]);
// we need to figure out what percentage the newTime is between the two points
float origTime1 = originalTimes[originalTimeLoc];
float origTime2 = originalTimes[originalTimeLoc+1];
float perc = (newTime - origTime1) / (origTime2 - origTime1);
results_device[resultsInd] = array_device[arrayInd1] + perc*valueChange;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
void __global__ kernel_linearInterpolation(float* array_device, int* rowArray, int rowArrayLength, int col, int colArrayLength, int totalCols, int totalRows, float* originalTimes, int originalTimesLength, float* newTimes, int newTimesLength, float* results_device)
{
// where original times and new times should probably be unix time? but technically won't matter probably
int n = blockIdx.x * blockDim.x + threadIdx.x;
//int m = blockIdx.y * blockDim.y + threadIdx.y;
int m = col;
if (n < newTimesLength && m < colArrayLength)
{
// so we created a row-wise thread per element in the newTimes, with m being number of columns
float newTime = newTimes[n];
int resultsInd = n*colArrayLength + m;
// need to potentially handle the first and last points in a special way ,,,
if (n==0 && newTimes[0] < originalTimes[0])
{
// lets say if newTimes[0] is prior to originalTimes[0] less than the distance from originalTimes[1] to originalTimes[2], we'll accept it
// otherwise call it a NaN
if ( originalTimes[0] - newTimes[0] < originalTimes[1] - originalTimes[0] )
{
// continue slope from points 0 to 1?
// ie assume there's a previous point at same slope and same sample rate
int arrayInd1 = (0)*totalCols + m;
int arrayInd2 = (1)*totalCols + m;
float valueChange = array_device[arrayInd2] - array_device[arrayInd1];
float timeDiff = originalTimes[1] - originalTimes[0];
float pseudoPointTime = originalTimes[0] - timeDiff;
float pseudoPointValue = array_device[arrayInd1] - valueChange;
float perc = (newTime - pseudoPointTime) / timeDiff;
results_device[resultsInd] = pseudoPointValue + perc*valueChange;
}
else
results_device[resultsInd] = NAN;
return;
}
// ================================================
// ================================================
// ===== DO THIS SAME LOGIC FOR LAST POINT? =======
// ================================================
// ================================================
// we now need to find the points before and after ...
// do we need to iterate through the entire originalTimes vector or is there some way we can approximate the starting location?
//float origSampleRate = (originalTimes[originalTimesLength-1] - originalTimes[0]) / originalTimesLength;
//float newSampleRate = (newTimes[newTimesLength-1] - newTimes[0]) / newTimesLength;
//int originalTimeLoc = (newTime - newTimes[0]) / (originalTimes[originalTimesLength-1] - originalTimes)
float newTimePerc = (newTime - newTimes[0]) / (newTimes[newTimesLength-1] - newTimes[0]);
int estimation = newTimePerc * originalTimesLength; // start at approximately the correct point
int iterationsToFindMatch = 0;
int originalTimeLoc;
if (originalTimes[estimation] > newTime)
{
// time we guessed is greater than the time we want ... so walk backwards?
for (originalTimeLoc=estimation; originalTimeLoc>0; originalTimeLoc--)
{
if (originalTimes[originalTimeLoc] < newTime)
break;
iterationsToFindMatch++;
}
}
else
{
// the time we guessed is greater than the time we want ... so walk forwards?
for (originalTimeLoc=estimation; originalTimeLoc<originalTimesLength; originalTimeLoc++)
{
if (originalTimes[originalTimeLoc] > newTime)
{
originalTimeLoc--; // want the left side point
break;
}
iterationsToFindMatch++;
}
}
printf("Loc %i needed %i iterations, starting from %i -> %i\n", n, iterationsToFindMatch, estimation, originalTimeLoc);
int arrayInd1 = originalTimeLoc*totalCols + m;
int arrayInd2 = (originalTimeLoc+1)*totalCols + m;
float valueChange = (array_device[arrayInd2] - array_device[arrayInd1]);
// we need to figure out what percentage the newTime is between the two points
float origTime1 = originalTimes[originalTimeLoc];
float origTime2 = originalTimes[originalTimeLoc+1];
float perc = (newTime - origTime1) / (origTime2 - origTime1);
results_device[resultsInd] = array_device[arrayInd1] + perc*valueChange;
}
} | .text
.file "kernel_interpolate.hip"
.globl _Z41__device_stub__kernel_linearInterpolationPfPiiiiiiS_iS_iS_ # -- Begin function _Z41__device_stub__kernel_linearInterpolationPfPiiiiiiS_iS_iS_
.p2align 4, 0x90
.type _Z41__device_stub__kernel_linearInterpolationPfPiiiiiiS_iS_iS_,@function
_Z41__device_stub__kernel_linearInterpolationPfPiiiiiiS_iS_iS_: # @_Z41__device_stub__kernel_linearInterpolationPfPiiiiiiS_iS_iS_
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 192(%rsp), %rax
movq %rax, 128(%rsp)
leaq 200(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z41__device_stub__kernel_linearInterpolationPfPiiiiiiS_iS_iS_, .Lfunc_end0-_Z41__device_stub__kernel_linearInterpolationPfPiiiiiiS_iS_iS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_,@object # @_Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_
.section .rodata,"a",@progbits
.globl _Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_
.p2align 3, 0x0
_Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_:
.quad _Z41__device_stub__kernel_linearInterpolationPfPiiiiiiS_iS_iS_
.size _Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_"
.size .L__unnamed_1, 48
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__kernel_linearInterpolationPfPiiiiiiS_iS_iS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012dc61_00000000-6_kernel_interpolate.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z61__device_stub__Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_PfPiiiiiiS_iS_iS_
.type _Z61__device_stub__Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_PfPiiiiiiS_iS_iS_, @function
_Z61__device_stub__Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_PfPiiiiiiS_iS_iS_:
.LFB2081:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movl %edx, 44(%rsp)
movl %ecx, 40(%rsp)
movl %r8d, 36(%rsp)
movl %r9d, 32(%rsp)
movq 264(%rsp), %rax
movq %rax, 24(%rsp)
movq 280(%rsp), %rax
movq %rax, 16(%rsp)
movq 296(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 36(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 24(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 288(%rsp), %rax
movq %rax, 208(%rsp)
leaq 8(%rsp), %rax
movq %rax, 216(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 264
pushq 72(%rsp)
.cfi_def_cfa_offset 272
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z61__device_stub__Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_PfPiiiiiiS_iS_iS_, .-_Z61__device_stub__Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_PfPiiiiiiS_iS_iS_
.globl _Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_
.type _Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_, @function
_Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 56(%rsp)
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z61__device_stub__Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_PfPiiiiiiS_iS_iS_
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_, .-_Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel_interpolate.hip"
.globl _Z41__device_stub__kernel_linearInterpolationPfPiiiiiiS_iS_iS_ # -- Begin function _Z41__device_stub__kernel_linearInterpolationPfPiiiiiiS_iS_iS_
.p2align 4, 0x90
.type _Z41__device_stub__kernel_linearInterpolationPfPiiiiiiS_iS_iS_,@function
_Z41__device_stub__kernel_linearInterpolationPfPiiiiiiS_iS_iS_: # @_Z41__device_stub__kernel_linearInterpolationPfPiiiiiiS_iS_iS_
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 192(%rsp), %rax
movq %rax, 128(%rsp)
leaq 200(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z41__device_stub__kernel_linearInterpolationPfPiiiiiiS_iS_iS_, .Lfunc_end0-_Z41__device_stub__kernel_linearInterpolationPfPiiiiiiS_iS_iS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_,@object # @_Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_
.section .rodata,"a",@progbits
.globl _Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_
.p2align 3, 0x0
_Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_:
.quad _Z41__device_stub__kernel_linearInterpolationPfPiiiiiiS_iS_iS_
.size _Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_"
.size .L__unnamed_1, 48
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__kernel_linearInterpolationPfPiiiiiiS_iS_iS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26kernel_linearInterpolationPfPiiiiiiS_iS_iS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Some useful utilities
// system includes
#include <stdio.h>
#include <assert.h>
#include <cuda.h>
// External function definitions
void checkCUDAError(const char *msg)
{
cudaError_t err = cudaGetLastError();
if( cudaSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg,
cudaGetErrorString( err) );
exit(EXIT_FAILURE);
}
}
// When there is more than one device,
// select the fastest device and report characteristics
void selectAndReport(int *major, int *minor)
{
int best_gpu = 0;
// Use the device with the most cores
int number_of_devices;
cudaGetDeviceCount(&number_of_devices);
checkCUDAError("Get Count");
printf("\n%d Devices\n",number_of_devices);
if (number_of_devices > 1) {
int max_cores = 0;
int device_number;
for (device_number = 0; device_number < number_of_devices;
device_number++) {
cudaDeviceProp device_properties;
cudaGetDeviceProperties(&device_properties, device_number);
printf("Device # %d has %d cores\n",device_number, device_properties.multiProcessorCount);
double gb = 1024*1024*1024;
printf("Device # %d has %f GB global memory\n",device_number, ((double)device_properties.totalGlobalMem)/gb);
if (max_cores < device_properties.multiProcessorCount) {
max_cores = device_properties.multiProcessorCount;
best_gpu = device_number;
}
}
printf("\n *** Best GPU is: %d\n",best_gpu);
cudaSetDevice(best_gpu);
checkCUDAError("Can't set device\n");
}
printf("\n");
// get number of SMs on this GPU
int devID;
cudaGetDevice(&devID);
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, devID);
printf("Device %d has %d cores\n", best_gpu, deviceProp.multiProcessorCount);
double gb = 1024*1024*1024;
printf("Device # %d has %f GB global memory\n",best_gpu, ((double)deviceProp.totalGlobalMem)/gb);
if (deviceProp.major == 9999 && deviceProp.minor == 9999) {
printf("There is no device supporting CUDA.\n");
cudaThreadExit();
} else {
printf("Device is a %s, capability: %d.%d\n", deviceProp.name, deviceProp.major, deviceProp.minor);
*major = deviceProp.major;
*minor = deviceProp.minor;
}
int driverVersion, runtimeVersion;
assert(cudaSuccess == cudaDriverGetVersion(&driverVersion));
assert(cudaSuccess == cudaRuntimeGetVersion(&runtimeVersion));
printf("CUDA Driver version: %d, runtime version: %d\n\n", driverVersion, runtimeVersion);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Some useful utilities
// system includes
#include <stdio.h>
#include <assert.h>
#include <cuda.h>
// External function definitions
void checkCUDAError(const char *msg)
{
cudaError_t err = cudaGetLastError();
if( cudaSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg,
cudaGetErrorString( err) );
exit(EXIT_FAILURE);
}
}
// When there is more than one device,
// select the fastest device and report characteristics
void selectAndReport(int *major, int *minor)
{
int best_gpu = 0;
// Use the device with the most cores
int number_of_devices;
cudaGetDeviceCount(&number_of_devices);
checkCUDAError("Get Count");
printf("\n%d Devices\n",number_of_devices);
if (number_of_devices > 1) {
int max_cores = 0;
int device_number;
for (device_number = 0; device_number < number_of_devices;
device_number++) {
cudaDeviceProp device_properties;
cudaGetDeviceProperties(&device_properties, device_number);
printf("Device # %d has %d cores\n",device_number, device_properties.multiProcessorCount);
double gb = 1024*1024*1024;
printf("Device # %d has %f GB global memory\n",device_number, ((double)device_properties.totalGlobalMem)/gb);
if (max_cores < device_properties.multiProcessorCount) {
max_cores = device_properties.multiProcessorCount;
best_gpu = device_number;
}
}
printf("\n *** Best GPU is: %d\n",best_gpu);
cudaSetDevice(best_gpu);
checkCUDAError("Can't set device\n");
}
printf("\n");
// get number of SMs on this GPU
int devID;
cudaGetDevice(&devID);
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, devID);
printf("Device %d has %d cores\n", best_gpu, deviceProp.multiProcessorCount);
double gb = 1024*1024*1024;
printf("Device # %d has %f GB global memory\n",best_gpu, ((double)deviceProp.totalGlobalMem)/gb);
if (deviceProp.major == 9999 && deviceProp.minor == 9999) {
printf("There is no device supporting CUDA.\n");
cudaThreadExit();
} else {
printf("Device is a %s, capability: %d.%d\n", deviceProp.name, deviceProp.major, deviceProp.minor);
*major = deviceProp.major;
*minor = deviceProp.minor;
}
int driverVersion, runtimeVersion;
assert(cudaSuccess == cudaDriverGetVersion(&driverVersion));
assert(cudaSuccess == cudaRuntimeGetVersion(&runtimeVersion));
printf("CUDA Driver version: %d, runtime version: %d\n\n", driverVersion, runtimeVersion);
} | .file "tmpxft_00122abd_00000000-6_utils.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Cuda error: %s: %s.\n"
.text
.globl _Z14checkCUDAErrorPKc
.type _Z14checkCUDAErrorPKc, @function
_Z14checkCUDAErrorPKc:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movq %rbx, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z14checkCUDAErrorPKc, .-_Z14checkCUDAErrorPKc
.section .rodata.str1.1
.LC1:
.string "Get Count"
.LC2:
.string "\n%d Devices\n"
.LC3:
.string "Device # %d has %d cores\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "Device # %d has %f GB global memory\n"
.section .rodata.str1.1
.LC6:
.string "\n *** Best GPU is: %d\n"
.LC7:
.string "Can't set device\n"
.LC8:
.string "\n"
.LC9:
.string "Device %d has %d cores\n"
.section .rodata.str1.8
.align 8
.LC10:
.string "There is no device supporting CUDA.\n"
.align 8
.LC11:
.string "Device is a %s, capability: %d.%d\n"
.align 8
.LC12:
.string "CUDA Driver version: %d, runtime version: %d\n\n"
.text
.globl _Z15selectAndReportPiS_
.type _Z15selectAndReportPiS_, @function
_Z15selectAndReportPiS_:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1080, %rsp
.cfi_def_cfa_offset 1136
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 1064(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
call cudaGetDeviceCount@PLT
leaq .LC1(%rip), %rdi
call _Z14checkCUDAErrorPKc
movl 24(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r12d
cmpl $1, 24(%rsp)
jle .L8
movl $0, %ebx
movl $0, %ebp
leaq 32(%rsp), %r15
leaq .LC3(%rip), %r14
leaq .LC5(%rip), %r13
jmp .L12
.L9:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
jmp .L10
.L11:
addl $1, %ebx
cmpl %ebx, 24(%rsp)
jle .L22
.L12:
movl %ebx, %esi
movq %r15, %rdi
call cudaGetDeviceProperties_v2@PLT
movl 420(%rsp), %ecx
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 320(%rsp), %rax
testq %rax, %rax
js .L9
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
.L10:
mulsd .LC4(%rip), %xmm0
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 420(%rsp), %eax
cmpl %ebp, %eax
jle .L11
movl %eax, %ebp
movl %ebx, %r12d
jmp .L11
.L22:
movl %r12d, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edi
call cudaSetDevice@PLT
leaq .LC7(%rip), %rdi
call _Z14checkCUDAErrorPKc
.L8:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 28(%rsp), %rdi
call cudaGetDevice@PLT
leaq 32(%rsp), %rdi
movl 28(%rsp), %esi
call cudaGetDeviceProperties_v2@PLT
movl 420(%rsp), %ecx
movl %r12d, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 320(%rsp), %rax
testq %rax, %rax
js .L13
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
.L14:
mulsd .LC4(%rip), %xmm0
movl %r12d, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movabsq $42945378002703, %rax
cmpq %rax, 392(%rsp)
je .L23
leaq 32(%rsp), %rdx
movl 396(%rsp), %r8d
movl 392(%rsp), %ecx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 392(%rsp), %eax
movq (%rsp), %rcx
movl %eax, (%rcx)
movl 396(%rsp), %eax
movq 8(%rsp), %rcx
movl %eax, (%rcx)
.L16:
movl $0, %ecx
movl $0, %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1064(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $1080, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
jmp .L14
.L23:
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaThreadExit@PLT
jmp .L16
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z15selectAndReportPiS_, .-_Z15selectAndReportPiS_
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1041235968
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Some useful utilities
// system includes
#include <stdio.h>
#include <assert.h>
#include <cuda.h>
// External function definitions
void checkCUDAError(const char *msg)
{
cudaError_t err = cudaGetLastError();
if( cudaSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg,
cudaGetErrorString( err) );
exit(EXIT_FAILURE);
}
}
// When there is more than one device,
// select the fastest device and report characteristics
void selectAndReport(int *major, int *minor)
{
int best_gpu = 0;
// Use the device with the most cores
int number_of_devices;
cudaGetDeviceCount(&number_of_devices);
checkCUDAError("Get Count");
printf("\n%d Devices\n",number_of_devices);
if (number_of_devices > 1) {
int max_cores = 0;
int device_number;
for (device_number = 0; device_number < number_of_devices;
device_number++) {
cudaDeviceProp device_properties;
cudaGetDeviceProperties(&device_properties, device_number);
printf("Device # %d has %d cores\n",device_number, device_properties.multiProcessorCount);
double gb = 1024*1024*1024;
printf("Device # %d has %f GB global memory\n",device_number, ((double)device_properties.totalGlobalMem)/gb);
if (max_cores < device_properties.multiProcessorCount) {
max_cores = device_properties.multiProcessorCount;
best_gpu = device_number;
}
}
printf("\n *** Best GPU is: %d\n",best_gpu);
cudaSetDevice(best_gpu);
checkCUDAError("Can't set device\n");
}
printf("\n");
// get number of SMs on this GPU
int devID;
cudaGetDevice(&devID);
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, devID);
printf("Device %d has %d cores\n", best_gpu, deviceProp.multiProcessorCount);
double gb = 1024*1024*1024;
printf("Device # %d has %f GB global memory\n",best_gpu, ((double)deviceProp.totalGlobalMem)/gb);
if (deviceProp.major == 9999 && deviceProp.minor == 9999) {
printf("There is no device supporting CUDA.\n");
cudaThreadExit();
} else {
printf("Device is a %s, capability: %d.%d\n", deviceProp.name, deviceProp.major, deviceProp.minor);
*major = deviceProp.major;
*minor = deviceProp.minor;
}
int driverVersion, runtimeVersion;
assert(cudaSuccess == cudaDriverGetVersion(&driverVersion));
assert(cudaSuccess == cudaRuntimeGetVersion(&runtimeVersion));
printf("CUDA Driver version: %d, runtime version: %d\n\n", driverVersion, runtimeVersion);
} | // Some useful utilities
// system includes
#include <stdio.h>
#include <assert.h>
#include <hip/hip_runtime.h>
// External function definitions
void checkCUDAError(const char *msg)
{
hipError_t err = hipGetLastError();
if( hipSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg,
hipGetErrorString( err) );
exit(EXIT_FAILURE);
}
}
// When there is more than one device,
// select the fastest device and report characteristics
void selectAndReport(int *major, int *minor)
{
int best_gpu = 0;
// Use the device with the most cores
int number_of_devices;
hipGetDeviceCount(&number_of_devices);
checkCUDAError("Get Count");
printf("\n%d Devices\n",number_of_devices);
if (number_of_devices > 1) {
int max_cores = 0;
int device_number;
for (device_number = 0; device_number < number_of_devices;
device_number++) {
hipDeviceProp_t device_properties;
hipGetDeviceProperties(&device_properties, device_number);
printf("Device # %d has %d cores\n",device_number, device_properties.multiProcessorCount);
double gb = 1024*1024*1024;
printf("Device # %d has %f GB global memory\n",device_number, ((double)device_properties.totalGlobalMem)/gb);
if (max_cores < device_properties.multiProcessorCount) {
max_cores = device_properties.multiProcessorCount;
best_gpu = device_number;
}
}
printf("\n *** Best GPU is: %d\n",best_gpu);
hipSetDevice(best_gpu);
checkCUDAError("Can't set device\n");
}
printf("\n");
// get number of SMs on this GPU
int devID;
hipGetDevice(&devID);
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, devID);
printf("Device %d has %d cores\n", best_gpu, deviceProp.multiProcessorCount);
double gb = 1024*1024*1024;
printf("Device # %d has %f GB global memory\n",best_gpu, ((double)deviceProp.totalGlobalMem)/gb);
if (deviceProp.major == 9999 && deviceProp.minor == 9999) {
printf("There is no device supporting CUDA.\n");
hipDeviceReset();
} else {
printf("Device is a %s, capability: %d.%d\n", deviceProp.name, deviceProp.major, deviceProp.minor);
*major = deviceProp.major;
*minor = deviceProp.minor;
}
int driverVersion, runtimeVersion;
assert(hipSuccess == hipDriverGetVersion(&driverVersion));
assert(hipSuccess == hipRuntimeGetVersion(&runtimeVersion));
printf("CUDA Driver version: %d, runtime version: %d\n\n", driverVersion, runtimeVersion);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Some useful utilities
// system includes
#include <stdio.h>
#include <assert.h>
#include <hip/hip_runtime.h>
// External function definitions
void checkCUDAError(const char *msg)
{
hipError_t err = hipGetLastError();
if( hipSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg,
hipGetErrorString( err) );
exit(EXIT_FAILURE);
}
}
// When there is more than one device,
// select the fastest device and report characteristics
void selectAndReport(int *major, int *minor)
{
int best_gpu = 0;
// Use the device with the most cores
int number_of_devices;
hipGetDeviceCount(&number_of_devices);
checkCUDAError("Get Count");
printf("\n%d Devices\n",number_of_devices);
if (number_of_devices > 1) {
int max_cores = 0;
int device_number;
for (device_number = 0; device_number < number_of_devices;
device_number++) {
hipDeviceProp_t device_properties;
hipGetDeviceProperties(&device_properties, device_number);
printf("Device # %d has %d cores\n",device_number, device_properties.multiProcessorCount);
double gb = 1024*1024*1024;
printf("Device # %d has %f GB global memory\n",device_number, ((double)device_properties.totalGlobalMem)/gb);
if (max_cores < device_properties.multiProcessorCount) {
max_cores = device_properties.multiProcessorCount;
best_gpu = device_number;
}
}
printf("\n *** Best GPU is: %d\n",best_gpu);
hipSetDevice(best_gpu);
checkCUDAError("Can't set device\n");
}
printf("\n");
// get number of SMs on this GPU
int devID;
hipGetDevice(&devID);
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, devID);
printf("Device %d has %d cores\n", best_gpu, deviceProp.multiProcessorCount);
double gb = 1024*1024*1024;
printf("Device # %d has %f GB global memory\n",best_gpu, ((double)deviceProp.totalGlobalMem)/gb);
if (deviceProp.major == 9999 && deviceProp.minor == 9999) {
printf("There is no device supporting CUDA.\n");
hipDeviceReset();
} else {
printf("Device is a %s, capability: %d.%d\n", deviceProp.name, deviceProp.major, deviceProp.minor);
*major = deviceProp.major;
*minor = deviceProp.minor;
}
int driverVersion, runtimeVersion;
assert(hipSuccess == hipDriverGetVersion(&driverVersion));
assert(hipSuccess == hipRuntimeGetVersion(&runtimeVersion));
printf("CUDA Driver version: %d, runtime version: %d\n\n", driverVersion, runtimeVersion);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Some useful utilities
// system includes
#include <stdio.h>
#include <assert.h>
#include <hip/hip_runtime.h>
// External function definitions
void checkCUDAError(const char *msg)
{
hipError_t err = hipGetLastError();
if( hipSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg,
hipGetErrorString( err) );
exit(EXIT_FAILURE);
}
}
// When there is more than one device,
// select the fastest device and report characteristics
void selectAndReport(int *major, int *minor)
{
int best_gpu = 0;
// Use the device with the most cores
int number_of_devices;
hipGetDeviceCount(&number_of_devices);
checkCUDAError("Get Count");
printf("\n%d Devices\n",number_of_devices);
if (number_of_devices > 1) {
int max_cores = 0;
int device_number;
for (device_number = 0; device_number < number_of_devices;
device_number++) {
hipDeviceProp_t device_properties;
hipGetDeviceProperties(&device_properties, device_number);
printf("Device # %d has %d cores\n",device_number, device_properties.multiProcessorCount);
double gb = 1024*1024*1024;
printf("Device # %d has %f GB global memory\n",device_number, ((double)device_properties.totalGlobalMem)/gb);
if (max_cores < device_properties.multiProcessorCount) {
max_cores = device_properties.multiProcessorCount;
best_gpu = device_number;
}
}
printf("\n *** Best GPU is: %d\n",best_gpu);
hipSetDevice(best_gpu);
checkCUDAError("Can't set device\n");
}
printf("\n");
// get number of SMs on this GPU
int devID;
hipGetDevice(&devID);
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, devID);
printf("Device %d has %d cores\n", best_gpu, deviceProp.multiProcessorCount);
double gb = 1024*1024*1024;
printf("Device # %d has %f GB global memory\n",best_gpu, ((double)deviceProp.totalGlobalMem)/gb);
if (deviceProp.major == 9999 && deviceProp.minor == 9999) {
printf("There is no device supporting CUDA.\n");
hipDeviceReset();
} else {
printf("Device is a %s, capability: %d.%d\n", deviceProp.name, deviceProp.major, deviceProp.minor);
*major = deviceProp.major;
*minor = deviceProp.minor;
}
int driverVersion, runtimeVersion;
assert(hipSuccess == hipDriverGetVersion(&driverVersion));
assert(hipSuccess == hipRuntimeGetVersion(&runtimeVersion));
printf("CUDA Driver version: %d, runtime version: %d\n\n", driverVersion, runtimeVersion);
} | .text
.file "utils.hip"
.globl _Z14checkCUDAErrorPKc # -- Begin function _Z14checkCUDAErrorPKc
.p2align 4, 0x90
.type _Z14checkCUDAErrorPKc,@function
_Z14checkCUDAErrorPKc: # @_Z14checkCUDAErrorPKc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB0_2
# %bb.1:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 32
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movq %r14, %rdi
movq %rbx, %rdx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z14checkCUDAErrorPKc, .Lfunc_end0-_Z14checkCUDAErrorPKc
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z15selectAndReportPiS_
.LCPI1_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI1_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_2:
.quad 0x3e10000000000000 # double 9.3132257461547852E-10
.text
.globl _Z15selectAndReportPiS_
.p2align 4, 0x90
.type _Z15selectAndReportPiS_,@function
_Z15selectAndReportPiS_: # @_Z15selectAndReportPiS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1536
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq %rdi, %r14
movq %rsp, %rdi
callq hipGetDeviceCount
callq hipGetLastError
testl %eax, %eax
jne .LBB1_1
# %bb.3: # %_Z14checkCUDAErrorPKc.exit
movl (%rsp), %esi
xorl %ebp, %ebp
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
cmpl $2, (%rsp)
jl .LBB1_10
# %bb.4: # %.preheader
cmpl $0, (%rsp)
jle .LBB1_5
# %bb.6: # %.lr.ph
leaq 8(%rsp), %r15
xorl %ebp, %ebp
xorl %r13d, %r13d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl %r12d, %esi
callq hipGetDevicePropertiesR0600
movl 396(%rsp), %edx
movl $.L.str.3, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
movsd 296(%rsp), %xmm1 # xmm1 = mem[0],zero
unpcklps .LCPI1_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI1_1(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
mulsd .LCPI1_2(%rip), %xmm0
movl $.L.str.4, %edi
movl %r12d, %esi
movb $1, %al
callq printf
movl 396(%rsp), %eax
cmpl %eax, %r13d
cmovlel %eax, %r13d
cmovll %r12d, %ebp
incl %r12d
cmpl (%rsp), %r12d
jl .LBB1_7
jmp .LBB1_8
.LBB1_5:
xorl %ebp, %ebp
.LBB1_8: # %._crit_edge
movl $.L.str.5, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl %ebp, %edi
callq hipSetDevice
callq hipGetLastError
testl %eax, %eax
jne .LBB1_9
.LBB1_10: # %_Z14checkCUDAErrorPKc.exit24
movl $10, %edi
callq putchar@PLT
leaq 4(%rsp), %rdi
callq hipGetDevice
movl 4(%rsp), %esi
leaq 8(%rsp), %rdi
callq hipGetDevicePropertiesR0600
movl 396(%rsp), %edx
movl $.L.str.8, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movsd 296(%rsp), %xmm1 # xmm1 = mem[0],zero
unpcklps .LCPI1_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI1_1(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
mulsd .LCPI1_2(%rip), %xmm0
movl $.L.str.4, %edi
movl %ebp, %esi
movb $1, %al
callq printf
movl 368(%rsp), %edx
movl 372(%rsp), %ecx
cmpl $9999, %edx # imm = 0x270F
jne .LBB1_13
# %bb.11: # %_Z14checkCUDAErrorPKc.exit24
cmpl $9999, %ecx # imm = 0x270F
jne .LBB1_13
# %bb.12:
movl $.Lstr, %edi
callq puts@PLT
callq hipDeviceReset
jmp .LBB1_14
.LBB1_13:
leaq 8(%rsp), %rsi
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl 368(%rsp), %eax
movl %eax, (%r14)
movl 372(%rsp), %eax
movl %eax, (%rbx)
.LBB1_14:
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 1536
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
jmp .LBB1_2
.LBB1_9:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.6, %edx
.LBB1_2:
movq %rbx, %rdi
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z15selectAndReportPiS_, .Lfunc_end1-_Z15selectAndReportPiS_
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Cuda error: %s: %s.\n"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Get Count"
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n%d Devices\n"
.size .L.str.2, 13
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Device # %d has %d cores\n"
.size .L.str.3, 26
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Device # %d has %f GB global memory\n"
.size .L.str.4, 37
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\n *** Best GPU is: %d\n"
.size .L.str.5, 23
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Can't set device\n"
.size .L.str.6, 18
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Device %d has %d cores\n"
.size .L.str.8, 24
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Device is a %s, capability: %d.%d\n"
.size .L.str.10, 35
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "CUDA Driver version: %d, runtime version: %d\n\n"
.size .L.str.11, 47
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "There is no device supporting CUDA."
.size .Lstr, 36
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00122abd_00000000-6_utils.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Cuda error: %s: %s.\n"
.text
.globl _Z14checkCUDAErrorPKc
.type _Z14checkCUDAErrorPKc, @function
_Z14checkCUDAErrorPKc:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movq %rbx, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z14checkCUDAErrorPKc, .-_Z14checkCUDAErrorPKc
.section .rodata.str1.1
.LC1:
.string "Get Count"
.LC2:
.string "\n%d Devices\n"
.LC3:
.string "Device # %d has %d cores\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "Device # %d has %f GB global memory\n"
.section .rodata.str1.1
.LC6:
.string "\n *** Best GPU is: %d\n"
.LC7:
.string "Can't set device\n"
.LC8:
.string "\n"
.LC9:
.string "Device %d has %d cores\n"
.section .rodata.str1.8
.align 8
.LC10:
.string "There is no device supporting CUDA.\n"
.align 8
.LC11:
.string "Device is a %s, capability: %d.%d\n"
.align 8
.LC12:
.string "CUDA Driver version: %d, runtime version: %d\n\n"
.text
.globl _Z15selectAndReportPiS_
.type _Z15selectAndReportPiS_, @function
_Z15selectAndReportPiS_:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1080, %rsp
.cfi_def_cfa_offset 1136
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 1064(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
call cudaGetDeviceCount@PLT
leaq .LC1(%rip), %rdi
call _Z14checkCUDAErrorPKc
movl 24(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r12d
cmpl $1, 24(%rsp)
jle .L8
movl $0, %ebx
movl $0, %ebp
leaq 32(%rsp), %r15
leaq .LC3(%rip), %r14
leaq .LC5(%rip), %r13
jmp .L12
.L9:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
jmp .L10
.L11:
addl $1, %ebx
cmpl %ebx, 24(%rsp)
jle .L22
.L12:
movl %ebx, %esi
movq %r15, %rdi
call cudaGetDeviceProperties_v2@PLT
movl 420(%rsp), %ecx
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 320(%rsp), %rax
testq %rax, %rax
js .L9
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
.L10:
mulsd .LC4(%rip), %xmm0
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 420(%rsp), %eax
cmpl %ebp, %eax
jle .L11
movl %eax, %ebp
movl %ebx, %r12d
jmp .L11
.L22:
movl %r12d, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edi
call cudaSetDevice@PLT
leaq .LC7(%rip), %rdi
call _Z14checkCUDAErrorPKc
.L8:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 28(%rsp), %rdi
call cudaGetDevice@PLT
leaq 32(%rsp), %rdi
movl 28(%rsp), %esi
call cudaGetDeviceProperties_v2@PLT
movl 420(%rsp), %ecx
movl %r12d, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 320(%rsp), %rax
testq %rax, %rax
js .L13
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
.L14:
mulsd .LC4(%rip), %xmm0
movl %r12d, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movabsq $42945378002703, %rax
cmpq %rax, 392(%rsp)
je .L23
leaq 32(%rsp), %rdx
movl 396(%rsp), %r8d
movl 392(%rsp), %ecx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 392(%rsp), %eax
movq (%rsp), %rcx
movl %eax, (%rcx)
movl 396(%rsp), %eax
movq 8(%rsp), %rcx
movl %eax, (%rcx)
.L16:
movl $0, %ecx
movl $0, %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1064(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $1080, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
jmp .L14
.L23:
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaThreadExit@PLT
jmp .L16
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z15selectAndReportPiS_, .-_Z15selectAndReportPiS_
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1041235968
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "utils.hip"
.globl _Z14checkCUDAErrorPKc # -- Begin function _Z14checkCUDAErrorPKc
.p2align 4, 0x90
.type _Z14checkCUDAErrorPKc,@function
_Z14checkCUDAErrorPKc: # @_Z14checkCUDAErrorPKc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB0_2
# %bb.1:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 32
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movq %r14, %rdi
movq %rbx, %rdx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z14checkCUDAErrorPKc, .Lfunc_end0-_Z14checkCUDAErrorPKc
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z15selectAndReportPiS_
.LCPI1_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI1_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_2:
.quad 0x3e10000000000000 # double 9.3132257461547852E-10
.text
.globl _Z15selectAndReportPiS_
.p2align 4, 0x90
.type _Z15selectAndReportPiS_,@function
_Z15selectAndReportPiS_: # @_Z15selectAndReportPiS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1536
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq %rdi, %r14
movq %rsp, %rdi
callq hipGetDeviceCount
callq hipGetLastError
testl %eax, %eax
jne .LBB1_1
# %bb.3: # %_Z14checkCUDAErrorPKc.exit
movl (%rsp), %esi
xorl %ebp, %ebp
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
cmpl $2, (%rsp)
jl .LBB1_10
# %bb.4: # %.preheader
cmpl $0, (%rsp)
jle .LBB1_5
# %bb.6: # %.lr.ph
leaq 8(%rsp), %r15
xorl %ebp, %ebp
xorl %r13d, %r13d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl %r12d, %esi
callq hipGetDevicePropertiesR0600
movl 396(%rsp), %edx
movl $.L.str.3, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
movsd 296(%rsp), %xmm1 # xmm1 = mem[0],zero
unpcklps .LCPI1_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI1_1(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
mulsd .LCPI1_2(%rip), %xmm0
movl $.L.str.4, %edi
movl %r12d, %esi
movb $1, %al
callq printf
movl 396(%rsp), %eax
cmpl %eax, %r13d
cmovlel %eax, %r13d
cmovll %r12d, %ebp
incl %r12d
cmpl (%rsp), %r12d
jl .LBB1_7
jmp .LBB1_8
.LBB1_5:
xorl %ebp, %ebp
.LBB1_8: # %._crit_edge
movl $.L.str.5, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl %ebp, %edi
callq hipSetDevice
callq hipGetLastError
testl %eax, %eax
jne .LBB1_9
.LBB1_10: # %_Z14checkCUDAErrorPKc.exit24
movl $10, %edi
callq putchar@PLT
leaq 4(%rsp), %rdi
callq hipGetDevice
movl 4(%rsp), %esi
leaq 8(%rsp), %rdi
callq hipGetDevicePropertiesR0600
movl 396(%rsp), %edx
movl $.L.str.8, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movsd 296(%rsp), %xmm1 # xmm1 = mem[0],zero
unpcklps .LCPI1_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI1_1(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
mulsd .LCPI1_2(%rip), %xmm0
movl $.L.str.4, %edi
movl %ebp, %esi
movb $1, %al
callq printf
movl 368(%rsp), %edx
movl 372(%rsp), %ecx
cmpl $9999, %edx # imm = 0x270F
jne .LBB1_13
# %bb.11: # %_Z14checkCUDAErrorPKc.exit24
cmpl $9999, %ecx # imm = 0x270F
jne .LBB1_13
# %bb.12:
movl $.Lstr, %edi
callq puts@PLT
callq hipDeviceReset
jmp .LBB1_14
.LBB1_13:
leaq 8(%rsp), %rsi
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl 368(%rsp), %eax
movl %eax, (%r14)
movl 372(%rsp), %eax
movl %eax, (%rbx)
.LBB1_14:
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 1536
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
jmp .LBB1_2
.LBB1_9:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.6, %edx
.LBB1_2:
movq %rbx, %rdi
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z15selectAndReportPiS_, .Lfunc_end1-_Z15selectAndReportPiS_
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Cuda error: %s: %s.\n"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Get Count"
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n%d Devices\n"
.size .L.str.2, 13
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Device # %d has %d cores\n"
.size .L.str.3, 26
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Device # %d has %f GB global memory\n"
.size .L.str.4, 37
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\n *** Best GPU is: %d\n"
.size .L.str.5, 23
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Can't set device\n"
.size .L.str.6, 18
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Device %d has %d cores\n"
.size .L.str.8, 24
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Device is a %s, capability: %d.%d\n"
.size .L.str.10, 35
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "CUDA Driver version: %d, runtime version: %d\n\n"
.size .L.str.11, 47
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "There is no device supporting CUDA."
.size .Lstr, 36
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ float sigmoid(float x) {
return 1 / (1 + expf(-x));
}
__global__ void produceState2(const float* arguments, const int argsSize, const float* weights, const int* topology, const int topSize, float* outStates) {
const int tid = threadIdx.x;
const int dim = argsSize + topSize;
extern __shared__ float s[];
float* states = s;
bool* ready = (bool*)&states[dim];
__shared__ int counter[1];
int r = tid;
while(r < dim) {
ready[r] = false;
r += blockDim.x;
}
if (tid == 0) {
counter[tid] = argsSize;
}
if (tid < argsSize) {
states[tid] = arguments[tid];
ready[tid] = true;
}
__syncthreads();
while(counter[0] < dim) {
const int index = counter[0] + tid;
const int topIndex = index - argsSize;
if (topIndex < topSize) {
const int leftBorder = topology[topIndex*3];
const int rightBorder = topology[topIndex*3 + 1];
const int weightsStart = topology[topIndex*3 + 2];
if (rightBorder <= counter[0]) {
float sum = 0;
for (int i = leftBorder; i < rightBorder; i++) {
sum += states[i] * weights[weightsStart + i - leftBorder];
}
states[index] = sigmoid(sum);
ready[index] = true;
}
}
__syncthreads();
if (tid == 0) {
int total = counter[0];
for (int i = total; i < total + blockDim.x && i < dim; i++) {
if (ready[i]) {
counter[0]++;
}
}
}
__syncthreads();
}
int n = tid;
while(n < dim) {
outStates[n] = states[n];
n += blockDim.x;
}
} | .file "tmpxft_000a7ab7_00000000-6_produceState2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7sigmoidf
.type _Z7sigmoidf, @function
_Z7sigmoidf:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z7sigmoidf, .-_Z7sigmoidf
.globl _Z44__device_stub__Z13produceState2PKfiS0_PKiiPfPKfiS0_PKiiPf
.type _Z44__device_stub__Z13produceState2PKfiS0_PKiiPfPKfiS0_PKiiPf, @function
_Z44__device_stub__Z13produceState2PKfiS0_PKiiPfPKfiS0_PKiiPf:
.LFB2052:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 32(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13produceState2PKfiS0_PKiiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z44__device_stub__Z13produceState2PKfiS0_PKiiPfPKfiS0_PKiiPf, .-_Z44__device_stub__Z13produceState2PKfiS0_PKiiPfPKfiS0_PKiiPf
.globl _Z13produceState2PKfiS0_PKiiPf
.type _Z13produceState2PKfiS0_PKiiPf, @function
_Z13produceState2PKfiS0_PKiiPf:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z13produceState2PKfiS0_PKiiPfPKfiS0_PKiiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z13produceState2PKfiS0_PKiiPf, .-_Z13produceState2PKfiS0_PKiiPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z13produceState2PKfiS0_PKiiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13produceState2PKfiS0_PKiiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ float sigmoid(float x) {
return 1 / (1 + expf(-x));
}
__global__ void produceState2(const float* arguments, const int argsSize, const float* weights, const int* topology, const int topSize, float* outStates) {
const int tid = threadIdx.x;
const int dim = argsSize + topSize;
extern __shared__ float s[];
float* states = s;
bool* ready = (bool*)&states[dim];
__shared__ int counter[1];
int r = tid;
while(r < dim) {
ready[r] = false;
r += blockDim.x;
}
if (tid == 0) {
counter[tid] = argsSize;
}
if (tid < argsSize) {
states[tid] = arguments[tid];
ready[tid] = true;
}
__syncthreads();
while(counter[0] < dim) {
const int index = counter[0] + tid;
const int topIndex = index - argsSize;
if (topIndex < topSize) {
const int leftBorder = topology[topIndex*3];
const int rightBorder = topology[topIndex*3 + 1];
const int weightsStart = topology[topIndex*3 + 2];
if (rightBorder <= counter[0]) {
float sum = 0;
for (int i = leftBorder; i < rightBorder; i++) {
sum += states[i] * weights[weightsStart + i - leftBorder];
}
states[index] = sigmoid(sum);
ready[index] = true;
}
}
__syncthreads();
if (tid == 0) {
int total = counter[0];
for (int i = total; i < total + blockDim.x && i < dim; i++) {
if (ready[i]) {
counter[0]++;
}
}
}
__syncthreads();
}
int n = tid;
while(n < dim) {
outStates[n] = states[n];
n += blockDim.x;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ float sigmoid(float x) {
return 1 / (1 + expf(-x));
}
__global__ void produceState2(const float* arguments, const int argsSize, const float* weights, const int* topology, const int topSize, float* outStates) {
const int tid = threadIdx.x;
const int dim = argsSize + topSize;
extern __shared__ float s[];
float* states = s;
bool* ready = (bool*)&states[dim];
__shared__ int counter[1];
int r = tid;
while(r < dim) {
ready[r] = false;
r += blockDim.x;
}
if (tid == 0) {
counter[tid] = argsSize;
}
if (tid < argsSize) {
states[tid] = arguments[tid];
ready[tid] = true;
}
__syncthreads();
while(counter[0] < dim) {
const int index = counter[0] + tid;
const int topIndex = index - argsSize;
if (topIndex < topSize) {
const int leftBorder = topology[topIndex*3];
const int rightBorder = topology[topIndex*3 + 1];
const int weightsStart = topology[topIndex*3 + 2];
if (rightBorder <= counter[0]) {
float sum = 0;
for (int i = leftBorder; i < rightBorder; i++) {
sum += states[i] * weights[weightsStart + i - leftBorder];
}
states[index] = sigmoid(sum);
ready[index] = true;
}
}
__syncthreads();
if (tid == 0) {
int total = counter[0];
for (int i = total; i < total + blockDim.x && i < dim; i++) {
if (ready[i]) {
counter[0]++;
}
}
}
__syncthreads();
}
int n = tid;
while(n < dim) {
outStates[n] = states[n];
n += blockDim.x;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ float sigmoid(float x) {
return 1 / (1 + expf(-x));
}
__global__ void produceState2(const float* arguments, const int argsSize, const float* weights, const int* topology, const int topSize, float* outStates) {
const int tid = threadIdx.x;
const int dim = argsSize + topSize;
extern __shared__ float s[];
float* states = s;
bool* ready = (bool*)&states[dim];
__shared__ int counter[1];
int r = tid;
while(r < dim) {
ready[r] = false;
r += blockDim.x;
}
if (tid == 0) {
counter[tid] = argsSize;
}
if (tid < argsSize) {
states[tid] = arguments[tid];
ready[tid] = true;
}
__syncthreads();
while(counter[0] < dim) {
const int index = counter[0] + tid;
const int topIndex = index - argsSize;
if (topIndex < topSize) {
const int leftBorder = topology[topIndex*3];
const int rightBorder = topology[topIndex*3 + 1];
const int weightsStart = topology[topIndex*3 + 2];
if (rightBorder <= counter[0]) {
float sum = 0;
for (int i = leftBorder; i < rightBorder; i++) {
sum += states[i] * weights[weightsStart + i - leftBorder];
}
states[index] = sigmoid(sum);
ready[index] = true;
}
}
__syncthreads();
if (tid == 0) {
int total = counter[0];
for (int i = total; i < total + blockDim.x && i < dim; i++) {
if (ready[i]) {
counter[0]++;
}
}
}
__syncthreads();
}
int n = tid;
while(n < dim) {
outStates[n] = states[n];
n += blockDim.x;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13produceState2PKfiS0_PKiiPf
.globl _Z13produceState2PKfiS0_PKiiPf
.p2align 8
.type _Z13produceState2PKfiS0_PKiiPf,@function
_Z13produceState2PKfiS0_PKiiPf:
s_clause 0x1
s_load_b32 s11, s[0:1], 0x8
s_load_b32 s12, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_add_i32 s10, s12, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b32 s2, s10, 2
s_add_i32 s13, s2, 4
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s10, v0
s_cbranch_execz .LBB0_3
s_load_b32 s3, s[0:1], 0x3c
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, v0
s_mov_b32 s4, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v3, s13, v2
v_add_nc_u32_e32 v2, s3, v2
ds_store_b8 v3, v1
v_cmp_le_i32_e32 vcc_lo, s10, v2
s_or_b32 s4, vcc_lo, s4
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
v_cmp_eq_u32_e64 s2, 0, v0
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_5
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s11
ds_store_b32 v1, v2
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s11, v0
s_cbranch_execz .LBB0_7
s_load_b64 s[4:5], s[0:1], 0x0
v_dual_mov_b32 v4, 1 :: v_dual_lshlrev_b32 v1, 2, v0
v_add_nc_u32_e32 v3, s13, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v1, s[4:5]
v_add_nc_u32_e32 v1, 4, v1
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
ds_store_b8 v3, v4
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s3
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v5, v3
s_waitcnt lgkmcnt(0)
v_cmp_le_i32_e32 vcc_lo, s10, v5
s_cbranch_vccnz .LBB0_22
s_load_b128 s[4:7], s[0:1], 0x10
s_add_u32 s8, s0, 48
s_addc_u32 s9, s1, 0
s_branch .LBB0_10
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v5, v3
s_waitcnt lgkmcnt(0)
v_cmp_le_i32_e32 vcc_lo, s10, v5
s_cbranch_vccnz .LBB0_22
.LBB0_10:
v_add_nc_u32_e32 v4, v5, v0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v1, s11, v4
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB0_17
v_lshl_add_u32 v1, v1, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v6, v[1:2], off offset:4
s_waitcnt vmcnt(0)
v_cmp_le_i32_e32 vcc_lo, v6, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_17
global_load_b32 v7, v[1:2], off
v_mov_b32_e32 v5, 0
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v7, v6
s_cbranch_execz .LBB0_16
global_load_b32 v1, v[1:2], off offset:8
v_lshl_add_u32 v8, v7, 2, 4
v_mov_b32_e32 v5, 0
s_mov_b32 s15, 0
.p2align 6
.LBB0_14:
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v7, 1, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], 2, v[1:2]
v_add_nc_u32_e32 v1, 1, v1
v_add_co_u32 v9, vcc_lo, s4, v9
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
v_cmp_ge_i32_e32 vcc_lo, v7, v6
global_load_b32 v2, v[9:10], off
ds_load_b32 v9, v8
v_add_nc_u32_e32 v8, 4, v8
s_or_b32 s15, vcc_lo, s15
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v5, v9, v2
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_14
s_or_b32 exec_lo, exec_lo, s15
.LBB0_16:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s14
v_mul_f32_e32 v1, 0xbfb8aa3b, v5
v_cmp_nlt_f32_e32 vcc_lo, 0x42ce8ed0, v5
v_rndne_f32_e32 v2, v1
v_fma_f32 v6, v5, 0xbfb8aa3b, -v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_sub_f32 v1, v1, v2 :: v_dual_fmac_f32 v6, 0xb2a5705f, v5
v_cvt_i32_f32_e32 v2, v2
v_add_f32_e32 v1, v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_ldexp_f32 v1, v1, v2
v_cndmask_b32_e32 v1, 0, v1, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2b17218, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, 0x7f800000, v1, vcc_lo
v_add_f32_e32 v1, 1.0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v2, null, v1, v1, 1.0
v_div_scale_f32 v7, vcc_lo, 1.0, v1, 1.0
v_rcp_f32_e32 v5, v2
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v2, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_mul_f32_e32 v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v2, v6, v7
v_fmac_f32_e32 v6, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v2, -v2, v6, v7
v_div_fmas_f32 v2, v2, v5, v6
v_lshl_add_u32 v5, v4, 2, 4
v_add_nc_u32_e32 v4, s13, v4
s_delay_alu instid0(VALU_DEP_3)
v_div_fixup_f32 v1, v2, v1, 1.0
v_mov_b32_e32 v2, 1
ds_store_b32 v5, v1
ds_store_b8 v4, v2
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s14, s2
s_cbranch_execz .LBB0_9
s_load_b32 s3, s[8:9], 0xc
ds_load_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
v_cmp_le_i32_e32 vcc_lo, s10, v1
v_add_nc_u32_e32 v2, s3, v1
v_mov_b32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_u32_e64 s3, v1, v2
s_or_b32 s3, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccz .LBB0_20
s_branch .LBB0_9
.p2align 6
.LBB0_19:
v_add_nc_u32_e32 v1, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_u32_e32 vcc_lo, v1, v2
v_cmp_gt_i32_e64 s3, s10, v1
s_and_b32 s3, s3, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccz .LBB0_9
.LBB0_20:
v_add_nc_u32_e32 v5, s13, v1
ds_load_u8 v5, v5
s_waitcnt lgkmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, 0, v5
s_cbranch_vccnz .LBB0_19
v_add_nc_u32_e32 v4, 1, v4
ds_store_b32 v3, v4
s_branch .LBB0_19
.LBB0_22:
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s10, v0
s_cbranch_execz .LBB0_25
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b64 s[2:3], s[0:1], 0x28
v_lshl_add_u32 v2, v0, 2, 4
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s4, s1, 2
.p2align 6
.LBB0_24:
ds_load_b32 v5, v2
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v2, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_add_nc_u32_e32 v0, s1, v0
v_cmp_le_i32_e32 vcc_lo, s10, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s0, s2, v3
v_add_co_ci_u32_e64 v4, s0, s3, v4, s0
s_or_b32 s5, vcc_lo, s5
s_waitcnt lgkmcnt(0)
global_store_b32 v[3:4], v5, off
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_24
.LBB0_25:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13produceState2PKfiS0_PKiiPf
.amdhsa_group_segment_fixed_size 4
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13produceState2PKfiS0_PKiiPf, .Lfunc_end0-_Z13produceState2PKfiS0_PKiiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
- .offset: 168
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 4
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13produceState2PKfiS0_PKiiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13produceState2PKfiS0_PKiiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ float sigmoid(float x) {
return 1 / (1 + expf(-x));
}
__global__ void produceState2(const float* arguments, const int argsSize, const float* weights, const int* topology, const int topSize, float* outStates) {
const int tid = threadIdx.x;
const int dim = argsSize + topSize;
extern __shared__ float s[];
float* states = s;
bool* ready = (bool*)&states[dim];
__shared__ int counter[1];
int r = tid;
while(r < dim) {
ready[r] = false;
r += blockDim.x;
}
if (tid == 0) {
counter[tid] = argsSize;
}
if (tid < argsSize) {
states[tid] = arguments[tid];
ready[tid] = true;
}
__syncthreads();
while(counter[0] < dim) {
const int index = counter[0] + tid;
const int topIndex = index - argsSize;
if (topIndex < topSize) {
const int leftBorder = topology[topIndex*3];
const int rightBorder = topology[topIndex*3 + 1];
const int weightsStart = topology[topIndex*3 + 2];
if (rightBorder <= counter[0]) {
float sum = 0;
for (int i = leftBorder; i < rightBorder; i++) {
sum += states[i] * weights[weightsStart + i - leftBorder];
}
states[index] = sigmoid(sum);
ready[index] = true;
}
}
__syncthreads();
if (tid == 0) {
int total = counter[0];
for (int i = total; i < total + blockDim.x && i < dim; i++) {
if (ready[i]) {
counter[0]++;
}
}
}
__syncthreads();
}
int n = tid;
while(n < dim) {
outStates[n] = states[n];
n += blockDim.x;
}
} | .text
.file "produceState2.hip"
.globl _Z28__device_stub__produceState2PKfiS0_PKiiPf # -- Begin function _Z28__device_stub__produceState2PKfiS0_PKiiPf
.p2align 4, 0x90
.type _Z28__device_stub__produceState2PKfiS0_PKiiPf,@function
_Z28__device_stub__produceState2PKfiS0_PKiiPf: # @_Z28__device_stub__produceState2PKfiS0_PKiiPf
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movl %r8d, 8(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13produceState2PKfiS0_PKiiPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z28__device_stub__produceState2PKfiS0_PKiiPf, .Lfunc_end0-_Z28__device_stub__produceState2PKfiS0_PKiiPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13produceState2PKfiS0_PKiiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13produceState2PKfiS0_PKiiPf,@object # @_Z13produceState2PKfiS0_PKiiPf
.section .rodata,"a",@progbits
.globl _Z13produceState2PKfiS0_PKiiPf
.p2align 3, 0x0
_Z13produceState2PKfiS0_PKiiPf:
.quad _Z28__device_stub__produceState2PKfiS0_PKiiPf
.size _Z13produceState2PKfiS0_PKiiPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13produceState2PKfiS0_PKiiPf"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__produceState2PKfiS0_PKiiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13produceState2PKfiS0_PKiiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a7ab7_00000000-6_produceState2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7sigmoidf
.type _Z7sigmoidf, @function
_Z7sigmoidf:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z7sigmoidf, .-_Z7sigmoidf
.globl _Z44__device_stub__Z13produceState2PKfiS0_PKiiPfPKfiS0_PKiiPf
.type _Z44__device_stub__Z13produceState2PKfiS0_PKiiPfPKfiS0_PKiiPf, @function
_Z44__device_stub__Z13produceState2PKfiS0_PKiiPfPKfiS0_PKiiPf:
.LFB2052:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 32(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13produceState2PKfiS0_PKiiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z44__device_stub__Z13produceState2PKfiS0_PKiiPfPKfiS0_PKiiPf, .-_Z44__device_stub__Z13produceState2PKfiS0_PKiiPfPKfiS0_PKiiPf
.globl _Z13produceState2PKfiS0_PKiiPf
.type _Z13produceState2PKfiS0_PKiiPf, @function
_Z13produceState2PKfiS0_PKiiPf:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z13produceState2PKfiS0_PKiiPfPKfiS0_PKiiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z13produceState2PKfiS0_PKiiPf, .-_Z13produceState2PKfiS0_PKiiPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z13produceState2PKfiS0_PKiiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13produceState2PKfiS0_PKiiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "produceState2.hip"
.globl _Z28__device_stub__produceState2PKfiS0_PKiiPf # -- Begin function _Z28__device_stub__produceState2PKfiS0_PKiiPf
.p2align 4, 0x90
.type _Z28__device_stub__produceState2PKfiS0_PKiiPf,@function
_Z28__device_stub__produceState2PKfiS0_PKiiPf: # @_Z28__device_stub__produceState2PKfiS0_PKiiPf
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movl %r8d, 8(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13produceState2PKfiS0_PKiiPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z28__device_stub__produceState2PKfiS0_PKiiPf, .Lfunc_end0-_Z28__device_stub__produceState2PKfiS0_PKiiPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13produceState2PKfiS0_PKiiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13produceState2PKfiS0_PKiiPf,@object # @_Z13produceState2PKfiS0_PKiiPf
.section .rodata,"a",@progbits
.globl _Z13produceState2PKfiS0_PKiiPf
.p2align 3, 0x0
_Z13produceState2PKfiS0_PKiiPf:
.quad _Z28__device_stub__produceState2PKfiS0_PKiiPf
.size _Z13produceState2PKfiS0_PKiiPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13produceState2PKfiS0_PKiiPf"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__produceState2PKfiS0_PKiiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13produceState2PKfiS0_PKiiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
# define MAX(a, b) ((a) > (b) ? (a) : (b))
# define GAUSSIAN_KERNEL_SIZE 3
# define SOBEL_KERNEL_SIZE 5
# define TILE_WIDTH 32
# define SMEM_SIZE 128
__global__ void initializeSobel(float *d_sobelKernelX, float *d_sobelKernelY) {
int ix = threadIdx.x;
int iy = threadIdx.y;
int weight = SOBEL_KERNEL_SIZE / 2;
if (ix < SOBEL_KERNEL_SIZE && iy < SOBEL_KERNEL_SIZE) {
int index = iy * SOBEL_KERNEL_SIZE + ix;
float sx = ix - SOBEL_KERNEL_SIZE / 2;
float sy = iy - SOBEL_KERNEL_SIZE / 2;
float norm = sx * sx + sy *sy;
if (norm == 0.0f) {
d_sobelKernelX[index] = 0.0f;
d_sobelKernelY[index] = 0.0f;
}
else {
d_sobelKernelX[index] = sx * weight / norm;
d_sobelKernelY[index] = sy * weight / norm;
}
}
} | code for sm_80
Function : _Z15initializeSobelPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0020*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e620000002100 */
/*0030*/ ISETP.GT.AND P0, PT, R3, 0x4, PT ; /* 0x000000040300780c */
/* 0x001fc80003f04270 */
/*0040*/ ISETP.GT.OR P0, PT, R4, 0x4, P0 ; /* 0x000000040400780c */
/* 0x002fda0000704670 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R6, R3.reuse, -0x2, RZ ; /* 0xfffffffe03067810 */
/* 0x040fe20007ffe0ff */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0080*/ IADD3 R7, R4, -0x2, RZ ; /* 0xfffffffe04077810 */
/* 0x000fe20007ffe0ff */
/*0090*/ IMAD R4, R3, 0x5, R4 ; /* 0x0000000503047824 */
/* 0x000fe200078e0204 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00b0*/ I2F R6, R6 ; /* 0x0000000600067306 */
/* 0x000e220000201400 */
/*00c0*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fc800078e0205 */
/*00d0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc600078e0205 */
/*00e0*/ I2F R7, R7 ; /* 0x0000000700077306 */
/* 0x000e620000201400 */
/*00f0*/ FMUL R0, R6, R6 ; /* 0x0000000606007220 */
/* 0x001fc80000400000 */
/*0100*/ FFMA R0, R7, R7, R0 ; /* 0x0000000707007223 */
/* 0x002fca0000000000 */
/*0110*/ FSETP.NEU.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720b */
/* 0x000fda0003f0d000 */
/*0120*/ @!P0 BRA 0x340 ; /* 0x0000021000008947 */
/* 0x000fea0003800000 */
/*0130*/ MUFU.RCP R9, R0 ; /* 0x0000000000097308 */
/* 0x000e220000001000 */
/*0140*/ FADD R7, R7, R7 ; /* 0x0000000707077221 */
/* 0x000fe20000000000 */
/*0150*/ BSSY B0, 0x220 ; /* 0x000000c000007945 */
/* 0x000fec0003800000 */
/*0160*/ FCHK P0, R7, R0 ; /* 0x0000000007007302 */
/* 0x000e620000000000 */
/*0170*/ FFMA R8, -R0, R9, 1 ; /* 0x3f80000000087423 */
/* 0x001fc80000000109 */
/*0180*/ FFMA R8, R9, R8, R9 ; /* 0x0000000809087223 */
/* 0x000fc80000000009 */
/*0190*/ FFMA R9, R7, R8, RZ ; /* 0x0000000807097223 */
/* 0x000fc800000000ff */
/*01a0*/ FFMA R10, -R0, R9, R7 ; /* 0x00000009000a7223 */
/* 0x000fc80000000107 */
/*01b0*/ FFMA R9, R8, R10, R9 ; /* 0x0000000a08097223 */
/* 0x000fe20000000009 */
/*01c0*/ @!P0 BRA 0x210 ; /* 0x0000004000008947 */
/* 0x002fea0003800000 */
/*01d0*/ IMAD.MOV.U32 R11, RZ, RZ, R7 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0007 */
/*01e0*/ MOV R8, 0x200 ; /* 0x0000020000087802 */
/* 0x000fe40000000f00 */
/*01f0*/ CALL.REL.NOINC 0x370 ; /* 0x0000017000007944 */
/* 0x000fea0003c00000 */
/*0200*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x001fe400078e0007 */
/*0210*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0220*/ MUFU.RCP R11, R0 ; /* 0x00000000000b7308 */
/* 0x000e220000001000 */
/*0230*/ FADD R7, R6, R6 ; /* 0x0000000606077221 */
/* 0x000fe20000000000 */
/*0240*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e2000c101904 */
/*0250*/ BSSY B0, 0x320 ; /* 0x000000c000007945 */
/* 0x000fea0003800000 */
/*0260*/ FCHK P0, R7, R0 ; /* 0x0000000007007302 */
/* 0x000ea20000000000 */
/*0270*/ FFMA R8, -R0, R11, 1 ; /* 0x3f80000000087423 */
/* 0x001fc8000000010b */
/*0280*/ FFMA R8, R11, R8, R11 ; /* 0x000000080b087223 */
/* 0x000fc8000000000b */
/*0290*/ FFMA R6, R8, R7, RZ ; /* 0x0000000708067223 */
/* 0x000fc800000000ff */
/*02a0*/ FFMA R11, -R0, R6, R7 ; /* 0x00000006000b7223 */
/* 0x000fc80000000107 */
/*02b0*/ FFMA R11, R8, R11, R6 ; /* 0x0000000b080b7223 */
/* 0x000fe20000000006 */
/*02c0*/ @!P0 BRA 0x310 ; /* 0x0000004000008947 */
/* 0x004fea0003800000 */
/*02d0*/ IMAD.MOV.U32 R11, RZ, RZ, R7 ; /* 0x000000ffff0b7224 */
/* 0x002fe200078e0007 */
/*02e0*/ MOV R8, 0x300 ; /* 0x0000030000087802 */
/* 0x000fe40000000f00 */
/*02f0*/ CALL.REL.NOINC 0x370 ; /* 0x0000007000007944 */
/* 0x000fea0003c00000 */
/*0300*/ IMAD.MOV.U32 R11, RZ, RZ, R7 ; /* 0x000000ffff0b7224 */
/* 0x001fe400078e0007 */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0320*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x000fe2000c101904 */
/*0330*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0340*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe8000c101904 */
/*0350*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe2000c101904 */
/*0360*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0370*/ SHF.R.U32.HI R10, RZ, 0x17, R0.reuse ; /* 0x00000017ff0a7819 */
/* 0x100fe20000011600 */
/*0380*/ BSSY B1, 0x9d0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0390*/ SHF.R.U32.HI R7, RZ, 0x17, R11 ; /* 0x00000017ff077819 */
/* 0x000fe2000001160b */
/*03a0*/ IMAD.MOV.U32 R12, RZ, RZ, R0 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0000 */
/*03b0*/ LOP3.LUT R10, R10, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0a0a7812 */
/* 0x000fc400078ec0ff */
/*03c0*/ LOP3.LUT R15, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff070f7812 */
/* 0x000fe200078ec0ff */
/*03d0*/ IMAD.MOV.U32 R7, RZ, RZ, R11 ; /* 0x000000ffff077224 */
/* 0x000fe200078e000b */
/*03e0*/ IADD3 R14, R10, -0x1, RZ ; /* 0xffffffff0a0e7810 */
/* 0x000fe40007ffe0ff */
/*03f0*/ IADD3 R13, R15, -0x1, RZ ; /* 0xffffffff0f0d7810 */
/* 0x000fe40007ffe0ff */
/*0400*/ ISETP.GT.U32.AND P0, PT, R14, 0xfd, PT ; /* 0x000000fd0e00780c */
/* 0x000fc80003f04070 */
/*0410*/ ISETP.GT.U32.OR P0, PT, R13, 0xfd, P0 ; /* 0x000000fd0d00780c */
/* 0x000fda0000704470 */
/*0420*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*0430*/ @!P0 BRA 0x5b0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0440*/ FSETP.GTU.FTZ.AND P0, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fe40003f1c200 */
/*0450*/ FSETP.GTU.FTZ.AND P1, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fc80003f3c200 */
/*0460*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0470*/ @P0 BRA 0x9b0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0480*/ LOP3.LUT P0, RZ, R12, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff0cff7812 */
/* 0x000fda000780c807 */
/*0490*/ @!P0 BRA 0x990 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*04a0*/ FSETP.NEU.FTZ.AND P2, PT, |R11|.reuse, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x040fe40003f5d200 */
/*04b0*/ FSETP.NEU.FTZ.AND P1, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fe40003f3d200 */
/*04c0*/ FSETP.NEU.FTZ.AND P0, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fd60003f1d200 */
/*04d0*/ @!P1 BRA !P2, 0x990 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*04e0*/ LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000784c0ff */
/*04f0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0500*/ @P1 BRA 0x970 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0510*/ LOP3.LUT P1, RZ, R12, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0cff7812 */
/* 0x000fc8000782c0ff */
/*0520*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0530*/ @P0 BRA 0x940 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0540*/ ISETP.GE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe40003f06270 */
/*0550*/ ISETP.GE.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fd60003f26270 */
/*0560*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*0570*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*0580*/ @!P0 FFMA R7, R11, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000b078823 */
/* 0x000fe400000000ff */
/*0590*/ @!P1 FFMA R12, R0, 1.84467440737095516160e+19, RZ ; /* 0x5f800000000c9823 */
/* 0x000fe200000000ff */
/*05a0*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*05b0*/ LEA R11, R10, 0xc0800000, 0x17 ; /* 0xc08000000a0b7811 */
/* 0x000fe200078eb8ff */
/*05c0*/ BSSY B2, 0x930 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*05d0*/ IMAD.IADD R12, R12, 0x1, -R11 ; /* 0x000000010c0c7824 */
/* 0x000fe200078e0a0b */
/*05e0*/ IADD3 R11, R15, -0x7f, RZ ; /* 0xffffff810f0b7810 */
/* 0x000fc60007ffe0ff */
/*05f0*/ MUFU.RCP R13, R12 ; /* 0x0000000c000d7308 */
/* 0x0000620000001000 */
/*0600*/ FADD.FTZ R14, -R12, -RZ ; /* 0x800000ff0c0e7221 */
/* 0x000fe40000010100 */
/*0610*/ IMAD R7, R11.reuse, -0x800000, R7 ; /* 0xff8000000b077824 */
/* 0x040fe200078e0207 */
/*0620*/ IADD3 R12, R11, 0x7f, -R10 ; /* 0x0000007f0b0c7810 */
/* 0x001fca0007ffe80a */
/*0630*/ IMAD.IADD R12, R12, 0x1, R9 ; /* 0x000000010c0c7824 */
/* 0x000fe400078e0209 */
/*0640*/ FFMA R16, R13, R14, 1 ; /* 0x3f8000000d107423 */
/* 0x002fc8000000000e */
/*0650*/ FFMA R18, R13, R16, R13 ; /* 0x000000100d127223 */
/* 0x000fc8000000000d */
/*0660*/ FFMA R13, R7, R18, RZ ; /* 0x00000012070d7223 */
/* 0x000fc800000000ff */
/*0670*/ FFMA R16, R14, R13, R7 ; /* 0x0000000d0e107223 */
/* 0x000fc80000000007 */
/*0680*/ FFMA R13, R18, R16, R13 ; /* 0x00000010120d7223 */
/* 0x000fc8000000000d */
/*0690*/ FFMA R14, R14, R13, R7 ; /* 0x0000000d0e0e7223 */
/* 0x000fc80000000007 */
/*06a0*/ FFMA R7, R18, R14, R13 ; /* 0x0000000e12077223 */
/* 0x000fca000000000d */
/*06b0*/ SHF.R.U32.HI R10, RZ, 0x17, R7 ; /* 0x00000017ff0a7819 */
/* 0x000fc80000011607 */
/*06c0*/ LOP3.LUT R10, R10, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0a0a7812 */
/* 0x000fca00078ec0ff */
/*06d0*/ IMAD.IADD R15, R10, 0x1, R12 ; /* 0x000000010a0f7824 */
/* 0x000fca00078e020c */
/*06e0*/ IADD3 R9, R15, -0x1, RZ ; /* 0xffffffff0f097810 */
/* 0x000fc80007ffe0ff */
/*06f0*/ ISETP.GE.U32.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f06070 */
/*0700*/ @!P0 BRA 0x910 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0710*/ ISETP.GT.AND P0, PT, R15, 0xfe, PT ; /* 0x000000fe0f00780c */
/* 0x000fda0003f04270 */
/*0720*/ @P0 BRA 0x8e0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0730*/ ISETP.GE.AND P0, PT, R15, 0x1, PT ; /* 0x000000010f00780c */
/* 0x000fda0003f06270 */
/*0740*/ @P0 BRA 0x920 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0750*/ ISETP.GE.AND P0, PT, R15, -0x18, PT ; /* 0xffffffe80f00780c */
/* 0x000fe40003f06270 */
/*0760*/ LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fd600078ec0ff */
/*0770*/ @!P0 BRA 0x920 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0780*/ FFMA.RZ R9, R18.reuse, R14.reuse, R13.reuse ; /* 0x0000000e12097223 */
/* 0x1c0fe2000000c00d */
/*0790*/ IADD3 R12, R15.reuse, 0x20, RZ ; /* 0x000000200f0c7810 */
/* 0x040fe20007ffe0ff */
/*07a0*/ FFMA.RM R10, R18.reuse, R14.reuse, R13.reuse ; /* 0x0000000e120a7223 */
/* 0x1c0fe2000000400d */
/*07b0*/ ISETP.NE.AND P2, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe40003f45270 */
/*07c0*/ LOP3.LUT R11, R9, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff090b7812 */
/* 0x000fe200078ec0ff */
/*07d0*/ FFMA.RP R9, R18, R14, R13 ; /* 0x0000000e12097223 */
/* 0x000fe2000000800d */
/*07e0*/ ISETP.NE.AND P1, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe20003f25270 */
/*07f0*/ IMAD.MOV R13, RZ, RZ, -R15 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0a0f */
/*0800*/ LOP3.LUT R11, R11, 0x800000, RZ, 0xfc, !PT ; /* 0x008000000b0b7812 */
/* 0x000fe400078efcff */
/*0810*/ FSETP.NEU.FTZ.AND P0, PT, R9, R10, PT ; /* 0x0000000a0900720b */
/* 0x000fc40003f1d000 */
/*0820*/ SHF.L.U32 R12, R11, R12, RZ ; /* 0x0000000c0b0c7219 */
/* 0x000fe400000006ff */
/*0830*/ SEL R10, R13, RZ, P2 ; /* 0x000000ff0d0a7207 */
/* 0x000fe40001000000 */
/*0840*/ ISETP.NE.AND P1, PT, R12, RZ, P1 ; /* 0x000000ff0c00720c */
/* 0x000fe40000f25270 */
/*0850*/ SHF.R.U32.HI R10, RZ, R10, R11 ; /* 0x0000000aff0a7219 */
/* 0x000fe4000001160b */
/*0860*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0870*/ SHF.R.U32.HI R12, RZ, 0x1, R10 ; /* 0x00000001ff0c7819 */
/* 0x000fc4000001160a */
/*0880*/ SEL R9, RZ, 0x1, !P0 ; /* 0x00000001ff097807 */
/* 0x000fc80004000000 */
/*0890*/ LOP3.LUT R9, R9, 0x1, R12, 0xf8, !PT ; /* 0x0000000109097812 */
/* 0x000fc800078ef80c */
/*08a0*/ LOP3.LUT R9, R9, R10, RZ, 0xc0, !PT ; /* 0x0000000a09097212 */
/* 0x000fca00078ec0ff */
/*08b0*/ IMAD.IADD R12, R12, 0x1, R9 ; /* 0x000000010c0c7824 */
/* 0x000fca00078e0209 */
/*08c0*/ LOP3.LUT R7, R12, R7, RZ, 0xfc, !PT ; /* 0x000000070c077212 */
/* 0x000fe200078efcff */
/*08d0*/ BRA 0x920 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*08e0*/ LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fc800078ec0ff */
/*08f0*/ LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000007077812 */
/* 0x000fe200078efcff */
/*0900*/ BRA 0x920 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0910*/ IMAD R7, R12, 0x800000, R7 ; /* 0x008000000c077824 */
/* 0x000fe400078e0207 */
/*0920*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0930*/ BRA 0x9c0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0940*/ LOP3.LUT R7, R12, 0x80000000, R7, 0x48, !PT ; /* 0x800000000c077812 */
/* 0x000fc800078e4807 */
/*0950*/ LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000007077812 */
/* 0x000fe200078efcff */
/*0960*/ BRA 0x9c0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0970*/ LOP3.LUT R7, R12, 0x80000000, R7, 0x48, !PT ; /* 0x800000000c077812 */
/* 0x000fe200078e4807 */
/*0980*/ BRA 0x9c0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0990*/ MUFU.RSQ R7, -QNAN ; /* 0xffc0000000077908 */
/* 0x000e220000001400 */
/*09a0*/ BRA 0x9c0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*09b0*/ FADD.FTZ R7, R11, R0 ; /* 0x000000000b077221 */
/* 0x000fe40000010000 */
/*09c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*09d0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x0 ; /* 0x00000000ff097424 */
/* 0x000fc800078e00ff */
/*09e0*/ RET.REL.NODEC R8 0x0 ; /* 0xfffff61008007950 */
/* 0x000fea0003c3ffff */
/*09f0*/ BRA 0x9f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
# define MAX(a, b) ((a) > (b) ? (a) : (b))
# define GAUSSIAN_KERNEL_SIZE 3
# define SOBEL_KERNEL_SIZE 5
# define TILE_WIDTH 32
# define SMEM_SIZE 128
__global__ void initializeSobel(float *d_sobelKernelX, float *d_sobelKernelY) {
int ix = threadIdx.x;
int iy = threadIdx.y;
int weight = SOBEL_KERNEL_SIZE / 2;
if (ix < SOBEL_KERNEL_SIZE && iy < SOBEL_KERNEL_SIZE) {
int index = iy * SOBEL_KERNEL_SIZE + ix;
float sx = ix - SOBEL_KERNEL_SIZE / 2;
float sy = iy - SOBEL_KERNEL_SIZE / 2;
float norm = sx * sx + sy *sy;
if (norm == 0.0f) {
d_sobelKernelX[index] = 0.0f;
d_sobelKernelY[index] = 0.0f;
}
else {
d_sobelKernelX[index] = sx * weight / norm;
d_sobelKernelY[index] = sy * weight / norm;
}
}
} | .file "tmpxft_0000b160_00000000-6_initializeSobel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z15initializeSobelPfS_PfS_
.type _Z37__device_stub__Z15initializeSobelPfS_PfS_, @function
_Z37__device_stub__Z15initializeSobelPfS_PfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15initializeSobelPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z15initializeSobelPfS_PfS_, .-_Z37__device_stub__Z15initializeSobelPfS_PfS_
.globl _Z15initializeSobelPfS_
.type _Z15initializeSobelPfS_, @function
_Z15initializeSobelPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z15initializeSobelPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15initializeSobelPfS_, .-_Z15initializeSobelPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15initializeSobelPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15initializeSobelPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
# define MAX(a, b) ((a) > (b) ? (a) : (b))
# define GAUSSIAN_KERNEL_SIZE 3
# define SOBEL_KERNEL_SIZE 5
# define TILE_WIDTH 32
# define SMEM_SIZE 128
__global__ void initializeSobel(float *d_sobelKernelX, float *d_sobelKernelY) {
int ix = threadIdx.x;
int iy = threadIdx.y;
int weight = SOBEL_KERNEL_SIZE / 2;
if (ix < SOBEL_KERNEL_SIZE && iy < SOBEL_KERNEL_SIZE) {
int index = iy * SOBEL_KERNEL_SIZE + ix;
float sx = ix - SOBEL_KERNEL_SIZE / 2;
float sy = iy - SOBEL_KERNEL_SIZE / 2;
float norm = sx * sx + sy *sy;
if (norm == 0.0f) {
d_sobelKernelX[index] = 0.0f;
d_sobelKernelY[index] = 0.0f;
}
else {
d_sobelKernelX[index] = sx * weight / norm;
d_sobelKernelY[index] = sy * weight / norm;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
# define MAX(a, b) ((a) > (b) ? (a) : (b))
# define GAUSSIAN_KERNEL_SIZE 3
# define SOBEL_KERNEL_SIZE 5
# define TILE_WIDTH 32
# define SMEM_SIZE 128
__global__ void initializeSobel(float *d_sobelKernelX, float *d_sobelKernelY) {
int ix = threadIdx.x;
int iy = threadIdx.y;
int weight = SOBEL_KERNEL_SIZE / 2;
if (ix < SOBEL_KERNEL_SIZE && iy < SOBEL_KERNEL_SIZE) {
int index = iy * SOBEL_KERNEL_SIZE + ix;
float sx = ix - SOBEL_KERNEL_SIZE / 2;
float sy = iy - SOBEL_KERNEL_SIZE / 2;
float norm = sx * sx + sy *sy;
if (norm == 0.0f) {
d_sobelKernelX[index] = 0.0f;
d_sobelKernelY[index] = 0.0f;
}
else {
d_sobelKernelX[index] = sx * weight / norm;
d_sobelKernelY[index] = sy * weight / norm;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
# define MAX(a, b) ((a) > (b) ? (a) : (b))
# define GAUSSIAN_KERNEL_SIZE 3
# define SOBEL_KERNEL_SIZE 5
# define TILE_WIDTH 32
# define SMEM_SIZE 128
__global__ void initializeSobel(float *d_sobelKernelX, float *d_sobelKernelY) {
int ix = threadIdx.x;
int iy = threadIdx.y;
int weight = SOBEL_KERNEL_SIZE / 2;
if (ix < SOBEL_KERNEL_SIZE && iy < SOBEL_KERNEL_SIZE) {
int index = iy * SOBEL_KERNEL_SIZE + ix;
float sx = ix - SOBEL_KERNEL_SIZE / 2;
float sy = iy - SOBEL_KERNEL_SIZE / 2;
float norm = sx * sx + sy *sy;
if (norm == 0.0f) {
d_sobelKernelX[index] = 0.0f;
d_sobelKernelY[index] = 0.0f;
}
else {
d_sobelKernelX[index] = sx * weight / norm;
d_sobelKernelY[index] = sy * weight / norm;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15initializeSobelPfS_
.globl _Z15initializeSobelPfS_
.p2align 8
.type _Z15initializeSobelPfS_,@function
_Z15initializeSobelPfS_:
v_and_b32_e32 v3, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_u32_e32 v1, v3, v0
v_cmpx_gt_u32_e32 5, v1
s_cbranch_execz .LBB0_6
v_add_nc_u32_e32 v1, -2, v0
s_load_b64 s[4:5], s[0:1], 0x0
v_add_nc_u32_e32 v2, -2, v3
v_mad_u32_u24 v0, v0, 5, v3
s_mov_b32 s2, exec_lo
v_cvt_f32_i32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v4, v2
v_mul_f32_e32 v2, v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, v4, v4
v_cmpx_neq_f32_e32 0, v2
s_xor_b32 s3, exec_lo, s2
s_cbranch_execz .LBB0_3
v_dual_add_f32 v3, v4, v4 :: v_dual_add_f32 v4, v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_scale_f32 v1, null, v2, v2, v3
v_div_scale_f32 v5, null, v2, v2, v4
v_div_scale_f32 v10, vcc_lo, v3, v2, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v6, v1
v_rcp_f32_e32 v7, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v1, v6, 1.0
v_fma_f32 v9, -v5, v7, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v6, v8, v6 :: v_dual_fmac_f32 v7, v9, v7
v_div_scale_f32 v8, s2, v4, v2, v4
v_mul_f32_e32 v9, v10, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v11, v8, v7
v_fma_f32 v12, -v1, v9, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v13, -v5, v11, v8
v_fmac_f32_e32 v9, v12, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v11, v13, v7
v_fma_f32 v1, -v1, v9, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v5, -v5, v11, v8
v_div_fmas_f32 v1, v1, v6, v9
s_mov_b32 vcc_lo, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_fmas_f32 v5, v5, v7, v11
v_lshlrev_b32_e32 v7, 2, v0
v_div_fixup_f32 v6, v1, v2, v3
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_4)
v_div_fixup_f32 v3, v5, v2, v4
s_waitcnt lgkmcnt(0)
global_store_b32 v7, v6, s[4:5]
.LBB0_3:
s_and_not1_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_5
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v2, 2, v0
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v3, v1
s_waitcnt lgkmcnt(0)
global_store_b32 v2, v1, s[4:5]
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15initializeSobelPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15initializeSobelPfS_, .Lfunc_end0-_Z15initializeSobelPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15initializeSobelPfS_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z15initializeSobelPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
# define MAX(a, b) ((a) > (b) ? (a) : (b))
# define GAUSSIAN_KERNEL_SIZE 3
# define SOBEL_KERNEL_SIZE 5
# define TILE_WIDTH 32
# define SMEM_SIZE 128
__global__ void initializeSobel(float *d_sobelKernelX, float *d_sobelKernelY) {
int ix = threadIdx.x;
int iy = threadIdx.y;
int weight = SOBEL_KERNEL_SIZE / 2;
if (ix < SOBEL_KERNEL_SIZE && iy < SOBEL_KERNEL_SIZE) {
int index = iy * SOBEL_KERNEL_SIZE + ix;
float sx = ix - SOBEL_KERNEL_SIZE / 2;
float sy = iy - SOBEL_KERNEL_SIZE / 2;
float norm = sx * sx + sy *sy;
if (norm == 0.0f) {
d_sobelKernelX[index] = 0.0f;
d_sobelKernelY[index] = 0.0f;
}
else {
d_sobelKernelX[index] = sx * weight / norm;
d_sobelKernelY[index] = sy * weight / norm;
}
}
} | .text
.file "initializeSobel.hip"
.globl _Z30__device_stub__initializeSobelPfS_ # -- Begin function _Z30__device_stub__initializeSobelPfS_
.p2align 4, 0x90
.type _Z30__device_stub__initializeSobelPfS_,@function
_Z30__device_stub__initializeSobelPfS_: # @_Z30__device_stub__initializeSobelPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z15initializeSobelPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z30__device_stub__initializeSobelPfS_, .Lfunc_end0-_Z30__device_stub__initializeSobelPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15initializeSobelPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15initializeSobelPfS_,@object # @_Z15initializeSobelPfS_
.section .rodata,"a",@progbits
.globl _Z15initializeSobelPfS_
.p2align 3, 0x0
_Z15initializeSobelPfS_:
.quad _Z30__device_stub__initializeSobelPfS_
.size _Z15initializeSobelPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15initializeSobelPfS_"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__initializeSobelPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15initializeSobelPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15initializeSobelPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0020*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e620000002100 */
/*0030*/ ISETP.GT.AND P0, PT, R3, 0x4, PT ; /* 0x000000040300780c */
/* 0x001fc80003f04270 */
/*0040*/ ISETP.GT.OR P0, PT, R4, 0x4, P0 ; /* 0x000000040400780c */
/* 0x002fda0000704670 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R6, R3.reuse, -0x2, RZ ; /* 0xfffffffe03067810 */
/* 0x040fe20007ffe0ff */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0080*/ IADD3 R7, R4, -0x2, RZ ; /* 0xfffffffe04077810 */
/* 0x000fe20007ffe0ff */
/*0090*/ IMAD R4, R3, 0x5, R4 ; /* 0x0000000503047824 */
/* 0x000fe200078e0204 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00b0*/ I2F R6, R6 ; /* 0x0000000600067306 */
/* 0x000e220000201400 */
/*00c0*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fc800078e0205 */
/*00d0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc600078e0205 */
/*00e0*/ I2F R7, R7 ; /* 0x0000000700077306 */
/* 0x000e620000201400 */
/*00f0*/ FMUL R0, R6, R6 ; /* 0x0000000606007220 */
/* 0x001fc80000400000 */
/*0100*/ FFMA R0, R7, R7, R0 ; /* 0x0000000707007223 */
/* 0x002fca0000000000 */
/*0110*/ FSETP.NEU.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720b */
/* 0x000fda0003f0d000 */
/*0120*/ @!P0 BRA 0x340 ; /* 0x0000021000008947 */
/* 0x000fea0003800000 */
/*0130*/ MUFU.RCP R9, R0 ; /* 0x0000000000097308 */
/* 0x000e220000001000 */
/*0140*/ FADD R7, R7, R7 ; /* 0x0000000707077221 */
/* 0x000fe20000000000 */
/*0150*/ BSSY B0, 0x220 ; /* 0x000000c000007945 */
/* 0x000fec0003800000 */
/*0160*/ FCHK P0, R7, R0 ; /* 0x0000000007007302 */
/* 0x000e620000000000 */
/*0170*/ FFMA R8, -R0, R9, 1 ; /* 0x3f80000000087423 */
/* 0x001fc80000000109 */
/*0180*/ FFMA R8, R9, R8, R9 ; /* 0x0000000809087223 */
/* 0x000fc80000000009 */
/*0190*/ FFMA R9, R7, R8, RZ ; /* 0x0000000807097223 */
/* 0x000fc800000000ff */
/*01a0*/ FFMA R10, -R0, R9, R7 ; /* 0x00000009000a7223 */
/* 0x000fc80000000107 */
/*01b0*/ FFMA R9, R8, R10, R9 ; /* 0x0000000a08097223 */
/* 0x000fe20000000009 */
/*01c0*/ @!P0 BRA 0x210 ; /* 0x0000004000008947 */
/* 0x002fea0003800000 */
/*01d0*/ IMAD.MOV.U32 R11, RZ, RZ, R7 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0007 */
/*01e0*/ MOV R8, 0x200 ; /* 0x0000020000087802 */
/* 0x000fe40000000f00 */
/*01f0*/ CALL.REL.NOINC 0x370 ; /* 0x0000017000007944 */
/* 0x000fea0003c00000 */
/*0200*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x001fe400078e0007 */
/*0210*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0220*/ MUFU.RCP R11, R0 ; /* 0x00000000000b7308 */
/* 0x000e220000001000 */
/*0230*/ FADD R7, R6, R6 ; /* 0x0000000606077221 */
/* 0x000fe20000000000 */
/*0240*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e2000c101904 */
/*0250*/ BSSY B0, 0x320 ; /* 0x000000c000007945 */
/* 0x000fea0003800000 */
/*0260*/ FCHK P0, R7, R0 ; /* 0x0000000007007302 */
/* 0x000ea20000000000 */
/*0270*/ FFMA R8, -R0, R11, 1 ; /* 0x3f80000000087423 */
/* 0x001fc8000000010b */
/*0280*/ FFMA R8, R11, R8, R11 ; /* 0x000000080b087223 */
/* 0x000fc8000000000b */
/*0290*/ FFMA R6, R8, R7, RZ ; /* 0x0000000708067223 */
/* 0x000fc800000000ff */
/*02a0*/ FFMA R11, -R0, R6, R7 ; /* 0x00000006000b7223 */
/* 0x000fc80000000107 */
/*02b0*/ FFMA R11, R8, R11, R6 ; /* 0x0000000b080b7223 */
/* 0x000fe20000000006 */
/*02c0*/ @!P0 BRA 0x310 ; /* 0x0000004000008947 */
/* 0x004fea0003800000 */
/*02d0*/ IMAD.MOV.U32 R11, RZ, RZ, R7 ; /* 0x000000ffff0b7224 */
/* 0x002fe200078e0007 */
/*02e0*/ MOV R8, 0x300 ; /* 0x0000030000087802 */
/* 0x000fe40000000f00 */
/*02f0*/ CALL.REL.NOINC 0x370 ; /* 0x0000007000007944 */
/* 0x000fea0003c00000 */
/*0300*/ IMAD.MOV.U32 R11, RZ, RZ, R7 ; /* 0x000000ffff0b7224 */
/* 0x001fe400078e0007 */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0320*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x000fe2000c101904 */
/*0330*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0340*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe8000c101904 */
/*0350*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe2000c101904 */
/*0360*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0370*/ SHF.R.U32.HI R10, RZ, 0x17, R0.reuse ; /* 0x00000017ff0a7819 */
/* 0x100fe20000011600 */
/*0380*/ BSSY B1, 0x9d0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0390*/ SHF.R.U32.HI R7, RZ, 0x17, R11 ; /* 0x00000017ff077819 */
/* 0x000fe2000001160b */
/*03a0*/ IMAD.MOV.U32 R12, RZ, RZ, R0 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0000 */
/*03b0*/ LOP3.LUT R10, R10, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0a0a7812 */
/* 0x000fc400078ec0ff */
/*03c0*/ LOP3.LUT R15, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff070f7812 */
/* 0x000fe200078ec0ff */
/*03d0*/ IMAD.MOV.U32 R7, RZ, RZ, R11 ; /* 0x000000ffff077224 */
/* 0x000fe200078e000b */
/*03e0*/ IADD3 R14, R10, -0x1, RZ ; /* 0xffffffff0a0e7810 */
/* 0x000fe40007ffe0ff */
/*03f0*/ IADD3 R13, R15, -0x1, RZ ; /* 0xffffffff0f0d7810 */
/* 0x000fe40007ffe0ff */
/*0400*/ ISETP.GT.U32.AND P0, PT, R14, 0xfd, PT ; /* 0x000000fd0e00780c */
/* 0x000fc80003f04070 */
/*0410*/ ISETP.GT.U32.OR P0, PT, R13, 0xfd, P0 ; /* 0x000000fd0d00780c */
/* 0x000fda0000704470 */
/*0420*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*0430*/ @!P0 BRA 0x5b0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0440*/ FSETP.GTU.FTZ.AND P0, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fe40003f1c200 */
/*0450*/ FSETP.GTU.FTZ.AND P1, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fc80003f3c200 */
/*0460*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0470*/ @P0 BRA 0x9b0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0480*/ LOP3.LUT P0, RZ, R12, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff0cff7812 */
/* 0x000fda000780c807 */
/*0490*/ @!P0 BRA 0x990 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*04a0*/ FSETP.NEU.FTZ.AND P2, PT, |R11|.reuse, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x040fe40003f5d200 */
/*04b0*/ FSETP.NEU.FTZ.AND P1, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fe40003f3d200 */
/*04c0*/ FSETP.NEU.FTZ.AND P0, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fd60003f1d200 */
/*04d0*/ @!P1 BRA !P2, 0x990 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*04e0*/ LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000784c0ff */
/*04f0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0500*/ @P1 BRA 0x970 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0510*/ LOP3.LUT P1, RZ, R12, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0cff7812 */
/* 0x000fc8000782c0ff */
/*0520*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0530*/ @P0 BRA 0x940 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0540*/ ISETP.GE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe40003f06270 */
/*0550*/ ISETP.GE.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fd60003f26270 */
/*0560*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*0570*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*0580*/ @!P0 FFMA R7, R11, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000b078823 */
/* 0x000fe400000000ff */
/*0590*/ @!P1 FFMA R12, R0, 1.84467440737095516160e+19, RZ ; /* 0x5f800000000c9823 */
/* 0x000fe200000000ff */
/*05a0*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*05b0*/ LEA R11, R10, 0xc0800000, 0x17 ; /* 0xc08000000a0b7811 */
/* 0x000fe200078eb8ff */
/*05c0*/ BSSY B2, 0x930 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*05d0*/ IMAD.IADD R12, R12, 0x1, -R11 ; /* 0x000000010c0c7824 */
/* 0x000fe200078e0a0b */
/*05e0*/ IADD3 R11, R15, -0x7f, RZ ; /* 0xffffff810f0b7810 */
/* 0x000fc60007ffe0ff */
/*05f0*/ MUFU.RCP R13, R12 ; /* 0x0000000c000d7308 */
/* 0x0000620000001000 */
/*0600*/ FADD.FTZ R14, -R12, -RZ ; /* 0x800000ff0c0e7221 */
/* 0x000fe40000010100 */
/*0610*/ IMAD R7, R11.reuse, -0x800000, R7 ; /* 0xff8000000b077824 */
/* 0x040fe200078e0207 */
/*0620*/ IADD3 R12, R11, 0x7f, -R10 ; /* 0x0000007f0b0c7810 */
/* 0x001fca0007ffe80a */
/*0630*/ IMAD.IADD R12, R12, 0x1, R9 ; /* 0x000000010c0c7824 */
/* 0x000fe400078e0209 */
/*0640*/ FFMA R16, R13, R14, 1 ; /* 0x3f8000000d107423 */
/* 0x002fc8000000000e */
/*0650*/ FFMA R18, R13, R16, R13 ; /* 0x000000100d127223 */
/* 0x000fc8000000000d */
/*0660*/ FFMA R13, R7, R18, RZ ; /* 0x00000012070d7223 */
/* 0x000fc800000000ff */
/*0670*/ FFMA R16, R14, R13, R7 ; /* 0x0000000d0e107223 */
/* 0x000fc80000000007 */
/*0680*/ FFMA R13, R18, R16, R13 ; /* 0x00000010120d7223 */
/* 0x000fc8000000000d */
/*0690*/ FFMA R14, R14, R13, R7 ; /* 0x0000000d0e0e7223 */
/* 0x000fc80000000007 */
/*06a0*/ FFMA R7, R18, R14, R13 ; /* 0x0000000e12077223 */
/* 0x000fca000000000d */
/*06b0*/ SHF.R.U32.HI R10, RZ, 0x17, R7 ; /* 0x00000017ff0a7819 */
/* 0x000fc80000011607 */
/*06c0*/ LOP3.LUT R10, R10, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0a0a7812 */
/* 0x000fca00078ec0ff */
/*06d0*/ IMAD.IADD R15, R10, 0x1, R12 ; /* 0x000000010a0f7824 */
/* 0x000fca00078e020c */
/*06e0*/ IADD3 R9, R15, -0x1, RZ ; /* 0xffffffff0f097810 */
/* 0x000fc80007ffe0ff */
/*06f0*/ ISETP.GE.U32.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f06070 */
/*0700*/ @!P0 BRA 0x910 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0710*/ ISETP.GT.AND P0, PT, R15, 0xfe, PT ; /* 0x000000fe0f00780c */
/* 0x000fda0003f04270 */
/*0720*/ @P0 BRA 0x8e0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0730*/ ISETP.GE.AND P0, PT, R15, 0x1, PT ; /* 0x000000010f00780c */
/* 0x000fda0003f06270 */
/*0740*/ @P0 BRA 0x920 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0750*/ ISETP.GE.AND P0, PT, R15, -0x18, PT ; /* 0xffffffe80f00780c */
/* 0x000fe40003f06270 */
/*0760*/ LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fd600078ec0ff */
/*0770*/ @!P0 BRA 0x920 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0780*/ FFMA.RZ R9, R18.reuse, R14.reuse, R13.reuse ; /* 0x0000000e12097223 */
/* 0x1c0fe2000000c00d */
/*0790*/ IADD3 R12, R15.reuse, 0x20, RZ ; /* 0x000000200f0c7810 */
/* 0x040fe20007ffe0ff */
/*07a0*/ FFMA.RM R10, R18.reuse, R14.reuse, R13.reuse ; /* 0x0000000e120a7223 */
/* 0x1c0fe2000000400d */
/*07b0*/ ISETP.NE.AND P2, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe40003f45270 */
/*07c0*/ LOP3.LUT R11, R9, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff090b7812 */
/* 0x000fe200078ec0ff */
/*07d0*/ FFMA.RP R9, R18, R14, R13 ; /* 0x0000000e12097223 */
/* 0x000fe2000000800d */
/*07e0*/ ISETP.NE.AND P1, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe20003f25270 */
/*07f0*/ IMAD.MOV R13, RZ, RZ, -R15 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0a0f */
/*0800*/ LOP3.LUT R11, R11, 0x800000, RZ, 0xfc, !PT ; /* 0x008000000b0b7812 */
/* 0x000fe400078efcff */
/*0810*/ FSETP.NEU.FTZ.AND P0, PT, R9, R10, PT ; /* 0x0000000a0900720b */
/* 0x000fc40003f1d000 */
/*0820*/ SHF.L.U32 R12, R11, R12, RZ ; /* 0x0000000c0b0c7219 */
/* 0x000fe400000006ff */
/*0830*/ SEL R10, R13, RZ, P2 ; /* 0x000000ff0d0a7207 */
/* 0x000fe40001000000 */
/*0840*/ ISETP.NE.AND P1, PT, R12, RZ, P1 ; /* 0x000000ff0c00720c */
/* 0x000fe40000f25270 */
/*0850*/ SHF.R.U32.HI R10, RZ, R10, R11 ; /* 0x0000000aff0a7219 */
/* 0x000fe4000001160b */
/*0860*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0870*/ SHF.R.U32.HI R12, RZ, 0x1, R10 ; /* 0x00000001ff0c7819 */
/* 0x000fc4000001160a */
/*0880*/ SEL R9, RZ, 0x1, !P0 ; /* 0x00000001ff097807 */
/* 0x000fc80004000000 */
/*0890*/ LOP3.LUT R9, R9, 0x1, R12, 0xf8, !PT ; /* 0x0000000109097812 */
/* 0x000fc800078ef80c */
/*08a0*/ LOP3.LUT R9, R9, R10, RZ, 0xc0, !PT ; /* 0x0000000a09097212 */
/* 0x000fca00078ec0ff */
/*08b0*/ IMAD.IADD R12, R12, 0x1, R9 ; /* 0x000000010c0c7824 */
/* 0x000fca00078e0209 */
/*08c0*/ LOP3.LUT R7, R12, R7, RZ, 0xfc, !PT ; /* 0x000000070c077212 */
/* 0x000fe200078efcff */
/*08d0*/ BRA 0x920 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*08e0*/ LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fc800078ec0ff */
/*08f0*/ LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000007077812 */
/* 0x000fe200078efcff */
/*0900*/ BRA 0x920 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0910*/ IMAD R7, R12, 0x800000, R7 ; /* 0x008000000c077824 */
/* 0x000fe400078e0207 */
/*0920*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0930*/ BRA 0x9c0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0940*/ LOP3.LUT R7, R12, 0x80000000, R7, 0x48, !PT ; /* 0x800000000c077812 */
/* 0x000fc800078e4807 */
/*0950*/ LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000007077812 */
/* 0x000fe200078efcff */
/*0960*/ BRA 0x9c0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0970*/ LOP3.LUT R7, R12, 0x80000000, R7, 0x48, !PT ; /* 0x800000000c077812 */
/* 0x000fe200078e4807 */
/*0980*/ BRA 0x9c0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0990*/ MUFU.RSQ R7, -QNAN ; /* 0xffc0000000077908 */
/* 0x000e220000001400 */
/*09a0*/ BRA 0x9c0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*09b0*/ FADD.FTZ R7, R11, R0 ; /* 0x000000000b077221 */
/* 0x000fe40000010000 */
/*09c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*09d0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x0 ; /* 0x00000000ff097424 */
/* 0x000fc800078e00ff */
/*09e0*/ RET.REL.NODEC R8 0x0 ; /* 0xfffff61008007950 */
/* 0x000fea0003c3ffff */
/*09f0*/ BRA 0x9f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15initializeSobelPfS_
.globl _Z15initializeSobelPfS_
.p2align 8
.type _Z15initializeSobelPfS_,@function
_Z15initializeSobelPfS_:
v_and_b32_e32 v3, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_u32_e32 v1, v3, v0
v_cmpx_gt_u32_e32 5, v1
s_cbranch_execz .LBB0_6
v_add_nc_u32_e32 v1, -2, v0
s_load_b64 s[4:5], s[0:1], 0x0
v_add_nc_u32_e32 v2, -2, v3
v_mad_u32_u24 v0, v0, 5, v3
s_mov_b32 s2, exec_lo
v_cvt_f32_i32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v4, v2
v_mul_f32_e32 v2, v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, v4, v4
v_cmpx_neq_f32_e32 0, v2
s_xor_b32 s3, exec_lo, s2
s_cbranch_execz .LBB0_3
v_dual_add_f32 v3, v4, v4 :: v_dual_add_f32 v4, v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_scale_f32 v1, null, v2, v2, v3
v_div_scale_f32 v5, null, v2, v2, v4
v_div_scale_f32 v10, vcc_lo, v3, v2, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v6, v1
v_rcp_f32_e32 v7, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v1, v6, 1.0
v_fma_f32 v9, -v5, v7, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v6, v8, v6 :: v_dual_fmac_f32 v7, v9, v7
v_div_scale_f32 v8, s2, v4, v2, v4
v_mul_f32_e32 v9, v10, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v11, v8, v7
v_fma_f32 v12, -v1, v9, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v13, -v5, v11, v8
v_fmac_f32_e32 v9, v12, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v11, v13, v7
v_fma_f32 v1, -v1, v9, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v5, -v5, v11, v8
v_div_fmas_f32 v1, v1, v6, v9
s_mov_b32 vcc_lo, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_fmas_f32 v5, v5, v7, v11
v_lshlrev_b32_e32 v7, 2, v0
v_div_fixup_f32 v6, v1, v2, v3
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_4)
v_div_fixup_f32 v3, v5, v2, v4
s_waitcnt lgkmcnt(0)
global_store_b32 v7, v6, s[4:5]
.LBB0_3:
s_and_not1_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_5
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v2, 2, v0
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v3, v1
s_waitcnt lgkmcnt(0)
global_store_b32 v2, v1, s[4:5]
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15initializeSobelPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15initializeSobelPfS_, .Lfunc_end0-_Z15initializeSobelPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15initializeSobelPfS_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z15initializeSobelPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000b160_00000000-6_initializeSobel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z15initializeSobelPfS_PfS_
.type _Z37__device_stub__Z15initializeSobelPfS_PfS_, @function
_Z37__device_stub__Z15initializeSobelPfS_PfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15initializeSobelPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z15initializeSobelPfS_PfS_, .-_Z37__device_stub__Z15initializeSobelPfS_PfS_
.globl _Z15initializeSobelPfS_
.type _Z15initializeSobelPfS_, @function
_Z15initializeSobelPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z15initializeSobelPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15initializeSobelPfS_, .-_Z15initializeSobelPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15initializeSobelPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15initializeSobelPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "initializeSobel.hip"
.globl _Z30__device_stub__initializeSobelPfS_ # -- Begin function _Z30__device_stub__initializeSobelPfS_
.p2align 4, 0x90
.type _Z30__device_stub__initializeSobelPfS_,@function
_Z30__device_stub__initializeSobelPfS_: # @_Z30__device_stub__initializeSobelPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z15initializeSobelPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z30__device_stub__initializeSobelPfS_, .Lfunc_end0-_Z30__device_stub__initializeSobelPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15initializeSobelPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15initializeSobelPfS_,@object # @_Z15initializeSobelPfS_
.section .rodata,"a",@progbits
.globl _Z15initializeSobelPfS_
.p2align 3, 0x0
_Z15initializeSobelPfS_:
.quad _Z30__device_stub__initializeSobelPfS_
.size _Z15initializeSobelPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15initializeSobelPfS_"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__initializeSobelPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15initializeSobelPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdio.h>
#include <math.h>
#define NUM_BANKS 8
#define LOG_NUM_BANKS 3
#define CONFLICT_FREE_OFFSET(n) \
((n) >> NUM_BANKS + (n) >> (2 * LOG_NUM_BANKS))
// Print device properties
void printDevProp(cudaDeviceProp devProp)
{
printf("Major revision number: %d\n", devProp.major);
printf("Minor revision number: %d\n", devProp.minor);
printf("Name: %s\n", devProp.name);
printf("Total global memory: %u\n", devProp.totalGlobalMem);
printf("Total shared memory per block: %u\n", devProp.sharedMemPerBlock);
printf("Total registers per block: %d\n", devProp.regsPerBlock);
printf("Warp size: %d\n", devProp.warpSize);
printf("Maximum memory pitch: %u\n", devProp.memPitch);
printf("Maximum threads per block: %d\n", devProp.maxThreadsPerBlock);
for (int i = 0; i < 3; ++i)
printf("Maximum dimension %d of block: %d\n", i, devProp.maxThreadsDim[i]);
for (int i = 0; i < 3; ++i)
printf("Maximum dimension %d of grid: %d\n", i, devProp.maxGridSize[i]);
printf("Clock rate: %d\n", devProp.clockRate);
printf("Total constant memory: %u\n", devProp.totalConstMem);
printf("Texture alignment: %u\n", devProp.textureAlignment);
printf("Concurrent copy and execution: %s\n", (devProp.deviceOverlap ? "Yes" : "No"));
printf("Number of multiprocessors: %d\n", devProp.multiProcessorCount);
printf("Kernel execution timeout: %s\n", (devProp.kernelExecTimeoutEnabled ? "Yes" : "No"));
return;
}
void proprietati()
{
int devCount;
cudaGetDeviceCount(&devCount);
printf("Avem %d device-uri.\n", devCount);
for (int i = 0; i < devCount; ++i)
{
// Get device properties
printf("\nCUDA Device #%d\n", i);
cudaDeviceProp devProp;
cudaGetDeviceProperties(&devProp, i);
printDevProp(devProp);
}
}
__global__ void vecDiv(float *a, float *b, float *c, unsigned int n)
{
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] / b[id];
}
__global__ void vecProd(float *a, float *b, float *c, unsigned int n)
{
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] * b[id];
}
__global__ void vecAdd(float *a, float *b, float *c, unsigned int n)
{
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] + b[id];
}
__global__ void vecSub(float *a, float *b, float *c, unsigned int n)
{
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] - b[id];
}
__global__ void eulVector(float *a, float *b,float *c, unsigned int n)
{
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id < n){
c[id] = a[id] - b[id];
c[id]*= c[id];
}
}
__global__ void smallSum(unsigned char *out, unsigned char *in, int n)
{
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(threadIdx.x == 1023) {
out[id/1024] = id;
}
}
// reduction sum
__global__ void reductionSum(float *in_array, float *out_array, unsigned long size)
{
extern __shared__ float shared[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
shared[tid] = in_array[i];
__syncthreads();
for(unsigned int s=blockDim.x/2; s>0; s>>=1) {
if (tid < s) {
shared[tid] += shared[tid + s];
}
__syncthreads();
}
if(tid==0) //first thread, last sum
{
out_array[blockIdx.x]=shared[0];
}
}
__global__ void cumSum(float *in_array, float *out_array, unsigned long size)
{
extern __shared__ float shared[];
unsigned int tid = threadIdx.x;
unsigned int b_offset = blockIdx.x * blockDim.x;
unsigned int offset = 1;
int i = tid;
int j = tid + blockDim.x / 2;
int offset_i = CONFLICT_FREE_OFFSET(i);
int offset_j = CONFLICT_FREE_OFFSET(j);
shared[i + offset_i] = in_array[i + b_offset];
shared[j + offset_j] = in_array[j + b_offset];
// scan up
for (int s = (blockDim.x >> 1); s > 0; s >>= 1) {
__syncthreads();
if (tid < s) {
int i = offset * (2 * tid + 1) - 1;
int j = offset * (2 * tid + 2) - 1;
i += CONFLICT_FREE_OFFSET(i);
j += CONFLICT_FREE_OFFSET(j);
shared[j] += shared[i];
}
offset <<= 1;
}
if (tid == 0) {
shared[blockDim.x - 1 + CONFLICT_FREE_OFFSET(blockDim.x - 1)] =
0;
}
// scan down
for (int s = 1; s < blockDim.x; s <<= 1) {
offset >>= 1;
__syncthreads();
if (tid < s) {
int i = offset * (2 * tid + 1) - 1;
int j = offset * (2 * tid + 2) - 1;
i += CONFLICT_FREE_OFFSET(i);
j += CONFLICT_FREE_OFFSET(j);
float tmp = shared[i];
shared[i] = shared[j];
shared[j] += tmp;
}
}
__syncthreads();
out_array[i] = shared[i + offset_i];
out_array[j] = shared[j + offset_j];
}
void test1(float *a, float *b, unsigned long n)
{
float *d_a, *d_b, *d_rez;
float *rez = (float*) malloc(n*sizeof(float));
cudaMalloc((void **)&d_a,n*sizeof(float));
cudaMalloc((void **)&d_b,n*sizeof(float));
cudaMalloc((void **)&d_rez,n*sizeof(float));
cudaMemcpy(d_a,a,n*sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,n*sizeof(float),cudaMemcpyHostToDevice);
vecAdd<<<161,64>>>(d_a,d_b,d_rez,n);
cudaMemcpy(rez,d_rez,10304*sizeof(float),cudaMemcpyDeviceToHost);
printf("\n REZULTAT TEST: %f \n",rez[0]);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_rez);
free(rez);
}
// a imagini
// b imagine
void euclideanNormAsync(float *a, float *b, unsigned long n, float *result, unsigned long nrPoze)
{
float *d_a,*d_b,*d_rez,*d_temp;
float *sum;
cudaStream_t stream;
cudaStreamCreate(&stream);
cudaHostRegister((void **)&a, n*nrPoze*sizeof(float), cudaHostRegisterPortable);
cudaHostAlloc((void **)&sum, nrPoze*sizeof(float), cudaHostAllocDefault);
cudaMalloc((void **)&d_a,n*sizeof(float));
cudaMalloc((void **)&d_b,n*sizeof(float));
cudaMalloc((void **)&d_temp,n*sizeof(float));
cudaMalloc((void **)&d_rez,(n/64+(256-n/64))*sizeof(float));
//cudaMemcpy(d_a,a,n*sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,n*sizeof(float),cudaMemcpyHostToDevice);
for(unsigned long int i=0, k=0; i<n, k< nrPoze; i+= n, k++)
{
cudaMemcpyAsync(d_a,a+i,n*sizeof(float),cudaMemcpyHostToDevice, stream);
eulVector<<<n/64, 64, n*sizeof(float), stream>>>(d_a,d_b,d_temp, n);
reductionSum<<<n/64, 64, n*sizeof(float), stream>>>(d_temp,d_rez, n);
cudaMemsetAsync(d_rez+n/64,0,95*sizeof(float),stream);
reductionSum<<<1,256, n*sizeof(float), stream>>>(d_rez,d_temp,n);
//cumSum<<<n/64, n/64, n*sizeof(float)>>>(d_rez,d_temp, n/64);
cudaMemcpyAsync(sum+k,d_temp,sizeof(float),cudaMemcpyDeviceToHost, stream);
}
cudaStreamSynchronize(stream);
for(int i=0;i<nrPoze;i++)
{
result[i] = sum[i];
}
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_temp);
cudaFree(d_rez);
cudaFreeHost(sum);
cudaHostUnregister(a);
cudaStreamDestroy(stream);
}
// a imagini
// b imagine
void cityblockNormAsync(float *a, float *b, unsigned long n, float *result, unsigned long nrPoze)
{
float *d_a,*d_b,*d_rez,*d_temp;
float *sum;
cudaStream_t stream;
cudaStreamCreate(&stream);
cudaHostRegister((void **)&a, n*nrPoze*sizeof(float), cudaHostRegisterPortable);
cudaHostAlloc((void **)&sum, nrPoze*sizeof(float), cudaHostAllocDefault);
cudaMalloc((void **)&d_a,n*sizeof(float));
cudaMalloc((void **)&d_b,n*sizeof(float));
cudaMalloc((void **)&d_temp,n*sizeof(float));
cudaMalloc((void **)&d_rez,(n/64+(256-n/64))*sizeof(float));
//cudaMemcpy(d_a,a,n*sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,n*sizeof(float),cudaMemcpyHostToDevice);
for(unsigned long int i=0, k=0; i<n, k< nrPoze; i+= n, k++)
{
cudaMemcpyAsync(d_a,a+i,n*sizeof(float),cudaMemcpyHostToDevice, stream);
vecSub<<<n/64, 64, n*sizeof(float), stream>>>(d_a,d_b,d_temp, n);
reductionSum<<<n/64, 64, n*sizeof(float), stream>>>(d_temp,d_rez, n);
cudaMemsetAsync(d_rez+n/64,0,95*sizeof(float),stream);
reductionSum<<<1,256, n*sizeof(float), stream>>>(d_rez,d_temp,n);
//cumSum<<<n/64, n/64, n*sizeof(float)>>>(d_rez,d_temp, n/64);
cudaMemcpyAsync(sum+k,d_temp,sizeof(float),cudaMemcpyDeviceToHost, stream);
}
cudaStreamSynchronize(stream);
for(int i=0;i<nrPoze;i++)
{
result[i] = sum[i];
}
//printf("%f ", min);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_temp);
cudaFree(d_rez);
cudaFreeHost(sum);
cudaHostUnregister(a);
cudaStreamDestroy(stream);
}
// a imagini
// b imagine
void cosNormAsync(float *a, float *b, unsigned long n, float *result, unsigned long nrPoze)
{
float *d_a,*d_b,*d_rez,*d_temp;
float *d_a1,*d_b1,*d_rez1, *d_temp1;
float *d_a2,*d_b2,*d_rez2, *d_temp2;
float *dotProd, *normA, *normB;
cudaStream_t stream, stream1, stream2;
cudaStreamCreate(&stream);
cudaStreamCreate(&stream1);
cudaStreamCreate(&stream2);
cudaHostRegister((void **)&a, n*nrPoze*sizeof(float), cudaHostRegisterPortable);
cudaHostAlloc((void **)&dotProd, nrPoze*sizeof(float), cudaHostAllocDefault);
cudaHostAlloc((void **)&normA, nrPoze*sizeof(float), cudaHostAllocDefault);
cudaHostAlloc((void **)&normB, nrPoze*sizeof(float), cudaHostAllocDefault);
cudaMalloc((void **)&d_a,n*sizeof(float));
cudaMalloc((void **)&d_b,n*sizeof(float));
cudaMalloc((void **)&d_temp,n*sizeof(float));
cudaMalloc((void **)&d_rez,(n/64+(256-n/64))*sizeof(float));
cudaMalloc((void **)&d_a1,n*sizeof(float));
cudaMalloc((void **)&d_b1,n*sizeof(float));
cudaMalloc((void **)&d_temp1,n*sizeof(float));
cudaMalloc((void **)&d_rez1,(n/64+(256-n/64))*sizeof(float));
cudaMalloc((void **)&d_a2,n*sizeof(float));
cudaMalloc((void **)&d_b2,n*sizeof(float));
cudaMalloc((void **)&d_temp2,n*sizeof(float));
cudaMalloc((void **)&d_rez2,(n/64+(256-n/64))*sizeof(float));
//cudaMemcpy(d_a,a,n*sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,n*sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(d_b1,b,n*sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(d_b2,b,n*sizeof(float),cudaMemcpyHostToDevice);
for(unsigned long int i=0, k=0; i<n, k< nrPoze; i+= n, k++)
{
cudaMemcpyAsync(d_a,a+i,n*sizeof(float),cudaMemcpyHostToDevice, stream);
cudaMemcpyAsync(d_a1,a+i,n*sizeof(float),cudaMemcpyHostToDevice, stream1);
cudaMemcpyAsync(d_a2,a+i,n*sizeof(float),cudaMemcpyHostToDevice, stream1);
vecProd<<<n/64, 64, n*sizeof(float), stream>>>(d_a,d_b,d_temp, n);
vecProd<<<n/64, 64, n*sizeof(float), stream1>>>(d_a1,d_a2,d_temp1, n);
if(i==0)
vecProd<<<n/64, 64, n*sizeof(float), stream2>>>(d_b1,d_b2,d_temp2, n);
reductionSum<<<n/64, 64, n*sizeof(float), stream>>>(d_temp,d_rez, n);
reductionSum<<<n/64, 64, n*sizeof(float), stream1>>>(d_temp1,d_rez1, n);
if(i==0)
reductionSum<<<n/64, 64, n*sizeof(float), stream2>>>(d_temp2,d_rez2, n);
cudaMemsetAsync(d_rez+n/64,0,95*sizeof(float),stream);
cudaMemsetAsync(d_rez1+n/64,0,95*sizeof(float),stream1);
if(i==0)
cudaMemsetAsync(d_rez2+n/64,0,95*sizeof(float),stream2);
reductionSum<<<1,256, n*sizeof(float), stream>>>(d_rez,d_temp,n);
reductionSum<<<1,256, n*sizeof(float), stream1>>>(d_rez1,d_temp1,n);
if(i==0)
reductionSum<<<1,256, n*sizeof(float), stream2>>>(d_rez2,d_temp2,n);
// we now have in d_temp - dot product, d_temp1 - norm of a, d_temp2 norm of b
cudaMemcpyAsync(dotProd+k,d_temp,sizeof(float),cudaMemcpyDeviceToHost, stream);
cudaMemcpyAsync(normA+k,d_temp1,sizeof(float),cudaMemcpyDeviceToHost, stream1);
cudaMemcpyAsync(normB+k,d_temp2,sizeof(float),cudaMemcpyDeviceToHost, stream2);
}
cudaStreamSynchronize(stream);
cudaStreamSynchronize(stream1);
cudaStreamSynchronize(stream2);
for(int i=0;i<nrPoze;i++)
{
float calc = 1 - dotProd[i]/(sqrtf(normA[i])*sqrtf(normB[i]));
result[i] = isnan(calc)?1:calc;
}
//printf("%f ",result[0]);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_temp);
cudaFree(d_rez);
cudaFree(d_a1);
cudaFree(d_b2);
cudaFree(d_temp1);
cudaFree(d_rez1);
cudaFree(d_a2);
cudaFree(d_b2);
cudaFree(d_temp2);
cudaFree(d_rez2);
cudaFreeHost(dotProd);
cudaFreeHost(normA);
cudaFreeHost(normB);
cudaHostUnregister(a);
cudaStreamDestroy(stream);
cudaStreamDestroy(stream1);
cudaStreamDestroy(stream2);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#define NUM_BANKS 8
#define LOG_NUM_BANKS 3
#define CONFLICT_FREE_OFFSET(n) \
((n) >> NUM_BANKS + (n) >> (2 * LOG_NUM_BANKS))
// Print device properties
void printDevProp(hipDeviceProp_t devProp)
{
printf("Major revision number: %d\n", devProp.major);
printf("Minor revision number: %d\n", devProp.minor);
printf("Name: %s\n", devProp.name);
printf("Total global memory: %u\n", devProp.totalGlobalMem);
printf("Total shared memory per block: %u\n", devProp.sharedMemPerBlock);
printf("Total registers per block: %d\n", devProp.regsPerBlock);
printf("Warp size: %d\n", devProp.warpSize);
printf("Maximum memory pitch: %u\n", devProp.memPitch);
printf("Maximum threads per block: %d\n", devProp.maxThreadsPerBlock);
for (int i = 0; i < 3; ++i)
printf("Maximum dimension %d of block: %d\n", i, devProp.maxThreadsDim[i]);
for (int i = 0; i < 3; ++i)
printf("Maximum dimension %d of grid: %d\n", i, devProp.maxGridSize[i]);
printf("Clock rate: %d\n", devProp.clockRate);
printf("Total constant memory: %u\n", devProp.totalConstMem);
printf("Texture alignment: %u\n", devProp.textureAlignment);
printf("Concurrent copy and execution: %s\n", (devProp.deviceOverlap ? "Yes" : "No"));
printf("Number of multiprocessors: %d\n", devProp.multiProcessorCount);
printf("Kernel execution timeout: %s\n", (devProp.kernelExecTimeoutEnabled ? "Yes" : "No"));
return;
}
void proprietati()
{
int devCount;
hipGetDeviceCount(&devCount);
printf("Avem %d device-uri.\n", devCount);
for (int i = 0; i < devCount; ++i)
{
// Get device properties
printf("\nCUDA Device #%d\n", i);
hipDeviceProp_t devProp;
hipGetDeviceProperties(&devProp, i);
printDevProp(devProp);
}
}
__global__ void vecDiv(float *a, float *b, float *c, unsigned int n)
{
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] / b[id];
}
__global__ void vecProd(float *a, float *b, float *c, unsigned int n)
{
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] * b[id];
}
__global__ void vecAdd(float *a, float *b, float *c, unsigned int n)
{
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] + b[id];
}
__global__ void vecSub(float *a, float *b, float *c, unsigned int n)
{
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] - b[id];
}
__global__ void eulVector(float *a, float *b,float *c, unsigned int n)
{
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id < n){
c[id] = a[id] - b[id];
c[id]*= c[id];
}
}
__global__ void smallSum(unsigned char *out, unsigned char *in, int n)
{
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(threadIdx.x == 1023) {
out[id/1024] = id;
}
}
// reduction sum
__global__ void reductionSum(float *in_array, float *out_array, unsigned long size)
{
extern __shared__ float shared[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
shared[tid] = in_array[i];
__syncthreads();
for(unsigned int s=blockDim.x/2; s>0; s>>=1) {
if (tid < s) {
shared[tid] += shared[tid + s];
}
__syncthreads();
}
if(tid==0) //first thread, last sum
{
out_array[blockIdx.x]=shared[0];
}
}
__global__ void cumSum(float *in_array, float *out_array, unsigned long size)
{
extern __shared__ float shared[];
unsigned int tid = threadIdx.x;
unsigned int b_offset = blockIdx.x * blockDim.x;
unsigned int offset = 1;
int i = tid;
int j = tid + blockDim.x / 2;
int offset_i = CONFLICT_FREE_OFFSET(i);
int offset_j = CONFLICT_FREE_OFFSET(j);
shared[i + offset_i] = in_array[i + b_offset];
shared[j + offset_j] = in_array[j + b_offset];
// scan up
for (int s = (blockDim.x >> 1); s > 0; s >>= 1) {
__syncthreads();
if (tid < s) {
int i = offset * (2 * tid + 1) - 1;
int j = offset * (2 * tid + 2) - 1;
i += CONFLICT_FREE_OFFSET(i);
j += CONFLICT_FREE_OFFSET(j);
shared[j] += shared[i];
}
offset <<= 1;
}
if (tid == 0) {
shared[blockDim.x - 1 + CONFLICT_FREE_OFFSET(blockDim.x - 1)] =
0;
}
// scan down
for (int s = 1; s < blockDim.x; s <<= 1) {
offset >>= 1;
__syncthreads();
if (tid < s) {
int i = offset * (2 * tid + 1) - 1;
int j = offset * (2 * tid + 2) - 1;
i += CONFLICT_FREE_OFFSET(i);
j += CONFLICT_FREE_OFFSET(j);
float tmp = shared[i];
shared[i] = shared[j];
shared[j] += tmp;
}
}
__syncthreads();
out_array[i] = shared[i + offset_i];
out_array[j] = shared[j + offset_j];
}
void test1(float *a, float *b, unsigned long n)
{
float *d_a, *d_b, *d_rez;
float *rez = (float*) malloc(n*sizeof(float));
hipMalloc((void **)&d_a,n*sizeof(float));
hipMalloc((void **)&d_b,n*sizeof(float));
hipMalloc((void **)&d_rez,n*sizeof(float));
hipMemcpy(d_a,a,n*sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(d_b,b,n*sizeof(float),hipMemcpyHostToDevice);
vecAdd<<<161,64>>>(d_a,d_b,d_rez,n);
hipMemcpy(rez,d_rez,10304*sizeof(float),hipMemcpyDeviceToHost);
printf("\n REZULTAT TEST: %f \n",rez[0]);
hipFree(d_a);
hipFree(d_b);
hipFree(d_rez);
free(rez);
}
// a imagini
// b imagine
void euclideanNormAsync(float *a, float *b, unsigned long n, float *result, unsigned long nrPoze)
{
float *d_a,*d_b,*d_rez,*d_temp;
float *sum;
hipStream_t stream;
hipStreamCreate(&stream);
hipHostRegister((void **)&a, n*nrPoze*sizeof(float), hipHostRegisterPortable);
hipHostAlloc((void **)&sum, nrPoze*sizeof(float), hipHostMallocDefault);
hipMalloc((void **)&d_a,n*sizeof(float));
hipMalloc((void **)&d_b,n*sizeof(float));
hipMalloc((void **)&d_temp,n*sizeof(float));
hipMalloc((void **)&d_rez,(n/64+(256-n/64))*sizeof(float));
//cudaMemcpy(d_a,a,n*sizeof(float),cudaMemcpyHostToDevice);
hipMemcpy(d_b,b,n*sizeof(float),hipMemcpyHostToDevice);
for(unsigned long int i=0, k=0; i<n, k< nrPoze; i+= n, k++)
{
hipMemcpyAsync(d_a,a+i,n*sizeof(float),hipMemcpyHostToDevice, stream);
eulVector<<<n/64, 64, n*sizeof(float), stream>>>(d_a,d_b,d_temp, n);
reductionSum<<<n/64, 64, n*sizeof(float), stream>>>(d_temp,d_rez, n);
hipMemsetAsync(d_rez+n/64,0,95*sizeof(float),stream);
reductionSum<<<1,256, n*sizeof(float), stream>>>(d_rez,d_temp,n);
//cumSum<<<n/64, n/64, n*sizeof(float)>>>(d_rez,d_temp, n/64);
hipMemcpyAsync(sum+k,d_temp,sizeof(float),hipMemcpyDeviceToHost, stream);
}
hipStreamSynchronize(stream);
for(int i=0;i<nrPoze;i++)
{
result[i] = sum[i];
}
hipFree(d_a);
hipFree(d_b);
hipFree(d_temp);
hipFree(d_rez);
hipHostFree(sum);
hipHostUnregister(a);
hipStreamDestroy(stream);
}
// a imagini
// b imagine
void cityblockNormAsync(float *a, float *b, unsigned long n, float *result, unsigned long nrPoze)
{
float *d_a,*d_b,*d_rez,*d_temp;
float *sum;
hipStream_t stream;
hipStreamCreate(&stream);
hipHostRegister((void **)&a, n*nrPoze*sizeof(float), hipHostRegisterPortable);
hipHostAlloc((void **)&sum, nrPoze*sizeof(float), hipHostMallocDefault);
hipMalloc((void **)&d_a,n*sizeof(float));
hipMalloc((void **)&d_b,n*sizeof(float));
hipMalloc((void **)&d_temp,n*sizeof(float));
hipMalloc((void **)&d_rez,(n/64+(256-n/64))*sizeof(float));
//cudaMemcpy(d_a,a,n*sizeof(float),cudaMemcpyHostToDevice);
hipMemcpy(d_b,b,n*sizeof(float),hipMemcpyHostToDevice);
for(unsigned long int i=0, k=0; i<n, k< nrPoze; i+= n, k++)
{
hipMemcpyAsync(d_a,a+i,n*sizeof(float),hipMemcpyHostToDevice, stream);
vecSub<<<n/64, 64, n*sizeof(float), stream>>>(d_a,d_b,d_temp, n);
reductionSum<<<n/64, 64, n*sizeof(float), stream>>>(d_temp,d_rez, n);
hipMemsetAsync(d_rez+n/64,0,95*sizeof(float),stream);
reductionSum<<<1,256, n*sizeof(float), stream>>>(d_rez,d_temp,n);
//cumSum<<<n/64, n/64, n*sizeof(float)>>>(d_rez,d_temp, n/64);
hipMemcpyAsync(sum+k,d_temp,sizeof(float),hipMemcpyDeviceToHost, stream);
}
hipStreamSynchronize(stream);
for(int i=0;i<nrPoze;i++)
{
result[i] = sum[i];
}
//printf("%f ", min);
hipFree(d_a);
hipFree(d_b);
hipFree(d_temp);
hipFree(d_rez);
hipHostFree(sum);
hipHostUnregister(a);
hipStreamDestroy(stream);
}
// a imagini
// b imagine
void cosNormAsync(float *a, float *b, unsigned long n, float *result, unsigned long nrPoze)
{
float *d_a,*d_b,*d_rez,*d_temp;
float *d_a1,*d_b1,*d_rez1, *d_temp1;
float *d_a2,*d_b2,*d_rez2, *d_temp2;
float *dotProd, *normA, *normB;
hipStream_t stream, stream1, stream2;
hipStreamCreate(&stream);
hipStreamCreate(&stream1);
hipStreamCreate(&stream2);
hipHostRegister((void **)&a, n*nrPoze*sizeof(float), hipHostRegisterPortable);
hipHostAlloc((void **)&dotProd, nrPoze*sizeof(float), hipHostMallocDefault);
hipHostAlloc((void **)&normA, nrPoze*sizeof(float), hipHostMallocDefault);
hipHostAlloc((void **)&normB, nrPoze*sizeof(float), hipHostMallocDefault);
hipMalloc((void **)&d_a,n*sizeof(float));
hipMalloc((void **)&d_b,n*sizeof(float));
hipMalloc((void **)&d_temp,n*sizeof(float));
hipMalloc((void **)&d_rez,(n/64+(256-n/64))*sizeof(float));
hipMalloc((void **)&d_a1,n*sizeof(float));
hipMalloc((void **)&d_b1,n*sizeof(float));
hipMalloc((void **)&d_temp1,n*sizeof(float));
hipMalloc((void **)&d_rez1,(n/64+(256-n/64))*sizeof(float));
hipMalloc((void **)&d_a2,n*sizeof(float));
hipMalloc((void **)&d_b2,n*sizeof(float));
hipMalloc((void **)&d_temp2,n*sizeof(float));
hipMalloc((void **)&d_rez2,(n/64+(256-n/64))*sizeof(float));
//cudaMemcpy(d_a,a,n*sizeof(float),cudaMemcpyHostToDevice);
hipMemcpy(d_b,b,n*sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(d_b1,b,n*sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(d_b2,b,n*sizeof(float),hipMemcpyHostToDevice);
for(unsigned long int i=0, k=0; i<n, k< nrPoze; i+= n, k++)
{
hipMemcpyAsync(d_a,a+i,n*sizeof(float),hipMemcpyHostToDevice, stream);
hipMemcpyAsync(d_a1,a+i,n*sizeof(float),hipMemcpyHostToDevice, stream1);
hipMemcpyAsync(d_a2,a+i,n*sizeof(float),hipMemcpyHostToDevice, stream1);
vecProd<<<n/64, 64, n*sizeof(float), stream>>>(d_a,d_b,d_temp, n);
vecProd<<<n/64, 64, n*sizeof(float), stream1>>>(d_a1,d_a2,d_temp1, n);
if(i==0)
vecProd<<<n/64, 64, n*sizeof(float), stream2>>>(d_b1,d_b2,d_temp2, n);
reductionSum<<<n/64, 64, n*sizeof(float), stream>>>(d_temp,d_rez, n);
reductionSum<<<n/64, 64, n*sizeof(float), stream1>>>(d_temp1,d_rez1, n);
if(i==0)
reductionSum<<<n/64, 64, n*sizeof(float), stream2>>>(d_temp2,d_rez2, n);
hipMemsetAsync(d_rez+n/64,0,95*sizeof(float),stream);
hipMemsetAsync(d_rez1+n/64,0,95*sizeof(float),stream1);
if(i==0)
hipMemsetAsync(d_rez2+n/64,0,95*sizeof(float),stream2);
reductionSum<<<1,256, n*sizeof(float), stream>>>(d_rez,d_temp,n);
reductionSum<<<1,256, n*sizeof(float), stream1>>>(d_rez1,d_temp1,n);
if(i==0)
reductionSum<<<1,256, n*sizeof(float), stream2>>>(d_rez2,d_temp2,n);
// we now have in d_temp - dot product, d_temp1 - norm of a, d_temp2 norm of b
hipMemcpyAsync(dotProd+k,d_temp,sizeof(float),hipMemcpyDeviceToHost, stream);
hipMemcpyAsync(normA+k,d_temp1,sizeof(float),hipMemcpyDeviceToHost, stream1);
hipMemcpyAsync(normB+k,d_temp2,sizeof(float),hipMemcpyDeviceToHost, stream2);
}
hipStreamSynchronize(stream);
hipStreamSynchronize(stream1);
hipStreamSynchronize(stream2);
for(int i=0;i<nrPoze;i++)
{
float calc = 1 - dotProd[i]/(sqrtf(normA[i])*sqrtf(normB[i]));
result[i] = isnan(calc)?1:calc;
}
//printf("%f ",result[0]);
hipFree(d_a);
hipFree(d_b);
hipFree(d_temp);
hipFree(d_rez);
hipFree(d_a1);
hipFree(d_b2);
hipFree(d_temp1);
hipFree(d_rez1);
hipFree(d_a2);
hipFree(d_b2);
hipFree(d_temp2);
hipFree(d_rez2);
hipHostFree(dotProd);
hipHostFree(normA);
hipHostFree(normB);
hipHostUnregister(a);
hipStreamDestroy(stream);
hipStreamDestroy(stream1);
hipStreamDestroy(stream2);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#define NUM_BANKS 8
#define LOG_NUM_BANKS 3
#define CONFLICT_FREE_OFFSET(n) \
((n) >> NUM_BANKS + (n) >> (2 * LOG_NUM_BANKS))
// Print device properties
void printDevProp(hipDeviceProp_t devProp)
{
printf("Major revision number: %d\n", devProp.major);
printf("Minor revision number: %d\n", devProp.minor);
printf("Name: %s\n", devProp.name);
printf("Total global memory: %u\n", devProp.totalGlobalMem);
printf("Total shared memory per block: %u\n", devProp.sharedMemPerBlock);
printf("Total registers per block: %d\n", devProp.regsPerBlock);
printf("Warp size: %d\n", devProp.warpSize);
printf("Maximum memory pitch: %u\n", devProp.memPitch);
printf("Maximum threads per block: %d\n", devProp.maxThreadsPerBlock);
for (int i = 0; i < 3; ++i)
printf("Maximum dimension %d of block: %d\n", i, devProp.maxThreadsDim[i]);
for (int i = 0; i < 3; ++i)
printf("Maximum dimension %d of grid: %d\n", i, devProp.maxGridSize[i]);
printf("Clock rate: %d\n", devProp.clockRate);
printf("Total constant memory: %u\n", devProp.totalConstMem);
printf("Texture alignment: %u\n", devProp.textureAlignment);
printf("Concurrent copy and execution: %s\n", (devProp.deviceOverlap ? "Yes" : "No"));
printf("Number of multiprocessors: %d\n", devProp.multiProcessorCount);
printf("Kernel execution timeout: %s\n", (devProp.kernelExecTimeoutEnabled ? "Yes" : "No"));
return;
}
void proprietati()
{
int devCount;
hipGetDeviceCount(&devCount);
printf("Avem %d device-uri.\n", devCount);
for (int i = 0; i < devCount; ++i)
{
// Get device properties
printf("\nCUDA Device #%d\n", i);
hipDeviceProp_t devProp;
hipGetDeviceProperties(&devProp, i);
printDevProp(devProp);
}
}
__global__ void vecDiv(float *a, float *b, float *c, unsigned int n)
{
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] / b[id];
}
__global__ void vecProd(float *a, float *b, float *c, unsigned int n)
{
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] * b[id];
}
__global__ void vecAdd(float *a, float *b, float *c, unsigned int n)
{
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] + b[id];
}
__global__ void vecSub(float *a, float *b, float *c, unsigned int n)
{
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] - b[id];
}
__global__ void eulVector(float *a, float *b,float *c, unsigned int n)
{
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id < n){
c[id] = a[id] - b[id];
c[id]*= c[id];
}
}
__global__ void smallSum(unsigned char *out, unsigned char *in, int n)
{
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(threadIdx.x == 1023) {
out[id/1024] = id;
}
}
// reduction sum
__global__ void reductionSum(float *in_array, float *out_array, unsigned long size)
{
extern __shared__ float shared[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
shared[tid] = in_array[i];
__syncthreads();
for(unsigned int s=blockDim.x/2; s>0; s>>=1) {
if (tid < s) {
shared[tid] += shared[tid + s];
}
__syncthreads();
}
if(tid==0) //first thread, last sum
{
out_array[blockIdx.x]=shared[0];
}
}
__global__ void cumSum(float *in_array, float *out_array, unsigned long size)
{
extern __shared__ float shared[];
unsigned int tid = threadIdx.x;
unsigned int b_offset = blockIdx.x * blockDim.x;
unsigned int offset = 1;
int i = tid;
int j = tid + blockDim.x / 2;
int offset_i = CONFLICT_FREE_OFFSET(i);
int offset_j = CONFLICT_FREE_OFFSET(j);
shared[i + offset_i] = in_array[i + b_offset];
shared[j + offset_j] = in_array[j + b_offset];
// scan up
for (int s = (blockDim.x >> 1); s > 0; s >>= 1) {
__syncthreads();
if (tid < s) {
int i = offset * (2 * tid + 1) - 1;
int j = offset * (2 * tid + 2) - 1;
i += CONFLICT_FREE_OFFSET(i);
j += CONFLICT_FREE_OFFSET(j);
shared[j] += shared[i];
}
offset <<= 1;
}
if (tid == 0) {
shared[blockDim.x - 1 + CONFLICT_FREE_OFFSET(blockDim.x - 1)] =
0;
}
// scan down
for (int s = 1; s < blockDim.x; s <<= 1) {
offset >>= 1;
__syncthreads();
if (tid < s) {
int i = offset * (2 * tid + 1) - 1;
int j = offset * (2 * tid + 2) - 1;
i += CONFLICT_FREE_OFFSET(i);
j += CONFLICT_FREE_OFFSET(j);
float tmp = shared[i];
shared[i] = shared[j];
shared[j] += tmp;
}
}
__syncthreads();
out_array[i] = shared[i + offset_i];
out_array[j] = shared[j + offset_j];
}
void test1(float *a, float *b, unsigned long n)
{
float *d_a, *d_b, *d_rez;
float *rez = (float*) malloc(n*sizeof(float));
hipMalloc((void **)&d_a,n*sizeof(float));
hipMalloc((void **)&d_b,n*sizeof(float));
hipMalloc((void **)&d_rez,n*sizeof(float));
hipMemcpy(d_a,a,n*sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(d_b,b,n*sizeof(float),hipMemcpyHostToDevice);
vecAdd<<<161,64>>>(d_a,d_b,d_rez,n);
hipMemcpy(rez,d_rez,10304*sizeof(float),hipMemcpyDeviceToHost);
printf("\n REZULTAT TEST: %f \n",rez[0]);
hipFree(d_a);
hipFree(d_b);
hipFree(d_rez);
free(rez);
}
// a imagini
// b imagine
void euclideanNormAsync(float *a, float *b, unsigned long n, float *result, unsigned long nrPoze)
{
float *d_a,*d_b,*d_rez,*d_temp;
float *sum;
hipStream_t stream;
hipStreamCreate(&stream);
hipHostRegister((void **)&a, n*nrPoze*sizeof(float), hipHostRegisterPortable);
hipHostAlloc((void **)&sum, nrPoze*sizeof(float), hipHostMallocDefault);
hipMalloc((void **)&d_a,n*sizeof(float));
hipMalloc((void **)&d_b,n*sizeof(float));
hipMalloc((void **)&d_temp,n*sizeof(float));
hipMalloc((void **)&d_rez,(n/64+(256-n/64))*sizeof(float));
//cudaMemcpy(d_a,a,n*sizeof(float),cudaMemcpyHostToDevice);
hipMemcpy(d_b,b,n*sizeof(float),hipMemcpyHostToDevice);
for(unsigned long int i=0, k=0; i<n, k< nrPoze; i+= n, k++)
{
hipMemcpyAsync(d_a,a+i,n*sizeof(float),hipMemcpyHostToDevice, stream);
eulVector<<<n/64, 64, n*sizeof(float), stream>>>(d_a,d_b,d_temp, n);
reductionSum<<<n/64, 64, n*sizeof(float), stream>>>(d_temp,d_rez, n);
hipMemsetAsync(d_rez+n/64,0,95*sizeof(float),stream);
reductionSum<<<1,256, n*sizeof(float), stream>>>(d_rez,d_temp,n);
//cumSum<<<n/64, n/64, n*sizeof(float)>>>(d_rez,d_temp, n/64);
hipMemcpyAsync(sum+k,d_temp,sizeof(float),hipMemcpyDeviceToHost, stream);
}
hipStreamSynchronize(stream);
for(int i=0;i<nrPoze;i++)
{
result[i] = sum[i];
}
hipFree(d_a);
hipFree(d_b);
hipFree(d_temp);
hipFree(d_rez);
hipHostFree(sum);
hipHostUnregister(a);
hipStreamDestroy(stream);
}
// a imagini
// b imagine
void cityblockNormAsync(float *a, float *b, unsigned long n, float *result, unsigned long nrPoze)
{
float *d_a,*d_b,*d_rez,*d_temp;
float *sum;
hipStream_t stream;
hipStreamCreate(&stream);
hipHostRegister((void **)&a, n*nrPoze*sizeof(float), hipHostRegisterPortable);
hipHostAlloc((void **)&sum, nrPoze*sizeof(float), hipHostMallocDefault);
hipMalloc((void **)&d_a,n*sizeof(float));
hipMalloc((void **)&d_b,n*sizeof(float));
hipMalloc((void **)&d_temp,n*sizeof(float));
hipMalloc((void **)&d_rez,(n/64+(256-n/64))*sizeof(float));
//cudaMemcpy(d_a,a,n*sizeof(float),cudaMemcpyHostToDevice);
hipMemcpy(d_b,b,n*sizeof(float),hipMemcpyHostToDevice);
for(unsigned long int i=0, k=0; i<n, k< nrPoze; i+= n, k++)
{
hipMemcpyAsync(d_a,a+i,n*sizeof(float),hipMemcpyHostToDevice, stream);
vecSub<<<n/64, 64, n*sizeof(float), stream>>>(d_a,d_b,d_temp, n);
reductionSum<<<n/64, 64, n*sizeof(float), stream>>>(d_temp,d_rez, n);
hipMemsetAsync(d_rez+n/64,0,95*sizeof(float),stream);
reductionSum<<<1,256, n*sizeof(float), stream>>>(d_rez,d_temp,n);
//cumSum<<<n/64, n/64, n*sizeof(float)>>>(d_rez,d_temp, n/64);
hipMemcpyAsync(sum+k,d_temp,sizeof(float),hipMemcpyDeviceToHost, stream);
}
hipStreamSynchronize(stream);
for(int i=0;i<nrPoze;i++)
{
result[i] = sum[i];
}
//printf("%f ", min);
hipFree(d_a);
hipFree(d_b);
hipFree(d_temp);
hipFree(d_rez);
hipHostFree(sum);
hipHostUnregister(a);
hipStreamDestroy(stream);
}
// a imagini
// b imagine
void cosNormAsync(float *a, float *b, unsigned long n, float *result, unsigned long nrPoze)
{
float *d_a,*d_b,*d_rez,*d_temp;
float *d_a1,*d_b1,*d_rez1, *d_temp1;
float *d_a2,*d_b2,*d_rez2, *d_temp2;
float *dotProd, *normA, *normB;
hipStream_t stream, stream1, stream2;
hipStreamCreate(&stream);
hipStreamCreate(&stream1);
hipStreamCreate(&stream2);
hipHostRegister((void **)&a, n*nrPoze*sizeof(float), hipHostRegisterPortable);
hipHostAlloc((void **)&dotProd, nrPoze*sizeof(float), hipHostMallocDefault);
hipHostAlloc((void **)&normA, nrPoze*sizeof(float), hipHostMallocDefault);
hipHostAlloc((void **)&normB, nrPoze*sizeof(float), hipHostMallocDefault);
hipMalloc((void **)&d_a,n*sizeof(float));
hipMalloc((void **)&d_b,n*sizeof(float));
hipMalloc((void **)&d_temp,n*sizeof(float));
hipMalloc((void **)&d_rez,(n/64+(256-n/64))*sizeof(float));
hipMalloc((void **)&d_a1,n*sizeof(float));
hipMalloc((void **)&d_b1,n*sizeof(float));
hipMalloc((void **)&d_temp1,n*sizeof(float));
hipMalloc((void **)&d_rez1,(n/64+(256-n/64))*sizeof(float));
hipMalloc((void **)&d_a2,n*sizeof(float));
hipMalloc((void **)&d_b2,n*sizeof(float));
hipMalloc((void **)&d_temp2,n*sizeof(float));
hipMalloc((void **)&d_rez2,(n/64+(256-n/64))*sizeof(float));
//cudaMemcpy(d_a,a,n*sizeof(float),cudaMemcpyHostToDevice);
hipMemcpy(d_b,b,n*sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(d_b1,b,n*sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(d_b2,b,n*sizeof(float),hipMemcpyHostToDevice);
for(unsigned long int i=0, k=0; i<n, k< nrPoze; i+= n, k++)
{
hipMemcpyAsync(d_a,a+i,n*sizeof(float),hipMemcpyHostToDevice, stream);
hipMemcpyAsync(d_a1,a+i,n*sizeof(float),hipMemcpyHostToDevice, stream1);
hipMemcpyAsync(d_a2,a+i,n*sizeof(float),hipMemcpyHostToDevice, stream1);
vecProd<<<n/64, 64, n*sizeof(float), stream>>>(d_a,d_b,d_temp, n);
vecProd<<<n/64, 64, n*sizeof(float), stream1>>>(d_a1,d_a2,d_temp1, n);
if(i==0)
vecProd<<<n/64, 64, n*sizeof(float), stream2>>>(d_b1,d_b2,d_temp2, n);
reductionSum<<<n/64, 64, n*sizeof(float), stream>>>(d_temp,d_rez, n);
reductionSum<<<n/64, 64, n*sizeof(float), stream1>>>(d_temp1,d_rez1, n);
if(i==0)
reductionSum<<<n/64, 64, n*sizeof(float), stream2>>>(d_temp2,d_rez2, n);
hipMemsetAsync(d_rez+n/64,0,95*sizeof(float),stream);
hipMemsetAsync(d_rez1+n/64,0,95*sizeof(float),stream1);
if(i==0)
hipMemsetAsync(d_rez2+n/64,0,95*sizeof(float),stream2);
reductionSum<<<1,256, n*sizeof(float), stream>>>(d_rez,d_temp,n);
reductionSum<<<1,256, n*sizeof(float), stream1>>>(d_rez1,d_temp1,n);
if(i==0)
reductionSum<<<1,256, n*sizeof(float), stream2>>>(d_rez2,d_temp2,n);
// we now have in d_temp - dot product, d_temp1 - norm of a, d_temp2 norm of b
hipMemcpyAsync(dotProd+k,d_temp,sizeof(float),hipMemcpyDeviceToHost, stream);
hipMemcpyAsync(normA+k,d_temp1,sizeof(float),hipMemcpyDeviceToHost, stream1);
hipMemcpyAsync(normB+k,d_temp2,sizeof(float),hipMemcpyDeviceToHost, stream2);
}
hipStreamSynchronize(stream);
hipStreamSynchronize(stream1);
hipStreamSynchronize(stream2);
for(int i=0;i<nrPoze;i++)
{
float calc = 1 - dotProd[i]/(sqrtf(normA[i])*sqrtf(normB[i]));
result[i] = isnan(calc)?1:calc;
}
//printf("%f ",result[0]);
hipFree(d_a);
hipFree(d_b);
hipFree(d_temp);
hipFree(d_rez);
hipFree(d_a1);
hipFree(d_b2);
hipFree(d_temp1);
hipFree(d_rez1);
hipFree(d_a2);
hipFree(d_b2);
hipFree(d_temp2);
hipFree(d_rez2);
hipHostFree(dotProd);
hipHostFree(normA);
hipHostFree(normB);
hipHostUnregister(a);
hipStreamDestroy(stream);
hipStreamDestroy(stream1);
hipStreamDestroy(stream2);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecDivPfS_S_j
.globl _Z6vecDivPfS_S_j
.p2align 8
.type _Z6vecDivPfS_S_j,@function
_Z6vecDivPfS_S_j:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v4, null, v3, v3, v2
v_div_scale_f32 v7, vcc_lo, v2, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v7, v5
v_fma_f32 v8, -v4, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v8, v5
v_fma_f32 v4, -v4, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f32 v4, v4, v5, v6
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_div_fixup_f32 v2, v4, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecDivPfS_S_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecDivPfS_S_j, .Lfunc_end0-_Z6vecDivPfS_S_j
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7vecProdPfS_S_j
.globl _Z7vecProdPfS_S_j
.p2align 8
.type _Z7vecProdPfS_S_j,@function
_Z7vecProdPfS_S_j:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7vecProdPfS_S_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7vecProdPfS_S_j, .Lfunc_end1-_Z7vecProdPfS_S_j
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6vecAddPfS_S_j
.globl _Z6vecAddPfS_S_j
.p2align 8
.type _Z6vecAddPfS_S_j,@function
_Z6vecAddPfS_S_j:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB2_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecAddPfS_S_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z6vecAddPfS_S_j, .Lfunc_end2-_Z6vecAddPfS_S_j
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6vecSubPfS_S_j
.globl _Z6vecSubPfS_S_j
.p2align 8
.type _Z6vecSubPfS_S_j,@function
_Z6vecSubPfS_S_j:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB3_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB3_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecSubPfS_S_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z6vecSubPfS_S_j, .Lfunc_end3-_Z6vecSubPfS_S_j
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9eulVectorPfS_S_j
.globl _Z9eulVectorPfS_S_j
.p2align 8
.type _Z9eulVectorPfS_S_j,@function
_Z9eulVectorPfS_S_j:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB4_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
.LBB4_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9eulVectorPfS_S_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end4:
.size _Z9eulVectorPfS_S_j, .Lfunc_end4-_Z9eulVectorPfS_S_j
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8smallSumPhS_i
.globl _Z8smallSumPhS_i
.p2align 8
.type _Z8smallSumPhS_i,@function
_Z8smallSumPhS_i:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0x3ff, v0
s_cbranch_execz .LBB5_2
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v0, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v0, 22, v0
v_add_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v0, 10, v0
v_ashrrev_i32_e32 v3, 31, v0
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b8 v[2:3], v1, off
.LBB5_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8smallSumPhS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end5:
.size _Z8smallSumPhS_i, .Lfunc_end5-_Z8smallSumPhS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12reductionSumPfS_m
.globl _Z12reductionSumPfS_m
.p2align 8
.type _Z12reductionSumPfS_m,@function
_Z12reductionSumPfS_m:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mov_b32_e32 v2, 0
s_cmp_lt_u32 s3, 2
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB6_2
.p2align 6
.LBB6_1:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s4
.LBB6_2:
buffer_gl0_inv
s_cbranch_scc1 .LBB6_5
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB6_1
v_add_nc_u32_e32 v2, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB6_1
.LBB6_5:
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB6_7
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB6_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12reductionSumPfS_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end6:
.size _Z12reductionSumPfS_m, .Lfunc_end6-_Z12reductionSumPfS_m
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6cumSumPfS_m
.globl _Z6cumSumPfS_m
.p2align 8
.type _Z6cumSumPfS_m,@function
_Z6cumSumPfS_m:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s3, 0xffff
s_bfe_u32 s3, s3, 0xf0001
s_mul_i32 s15, s15, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v2, s15, v0
v_add_nc_u32_e32 v1, s3, v0
s_cmp_lt_u32 s2, 2
s_mov_b32 s3, 1
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, s15, v1
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_clause 0x1
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[2:3], off
v_add_nc_u32_e32 v2, 8, v1
v_lshl_add_u32 v3, v0, 2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v2, v2, v1
v_lshrrev_b32_e32 v2, 6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v1
v_lshl_add_u32 v2, v2, 2, 0
s_waitcnt vmcnt(1)
ds_store_b32 v3, v4
s_waitcnt vmcnt(0)
ds_store_b32 v2, v5
s_cbranch_scc1 .LBB7_6
v_lshlrev_b32_e32 v5, 1, v0
s_mov_b32 s4, s2
s_delay_alu instid0(VALU_DEP_1)
v_or_b32_e32 v4, 1, v5
v_add_nc_u32_e32 v5, 2, v5
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB7_2:
s_lshr_b32 s5, s4, 1
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s5, v0
s_cbranch_execz .LBB7_4
v_mul_lo_u32 v6, s3, v4
v_mul_lo_u32 v7, s3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v8, -1, v6
v_add_nc_u32_e32 v6, 7, v6
v_add_nc_u32_e32 v9, -1, v7
v_add_nc_u32_e32 v7, 7, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v6, v6, v8
v_ashrrev_i32_e32 v7, v7, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v6, 6, v6
v_ashrrev_i32_e32 v7, 6, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, v6, v8
v_add_nc_u32_e32 v7, v7, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v6, v6, 2, 0
v_lshl_add_u32 v7, v7, 2, 0
ds_load_b32 v6, v6
ds_load_b32 v8, v7
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v6, v6, v8
ds_store_b32 v7, v6
.LBB7_4:
s_or_b32 exec_lo, exec_lo, s6
s_lshl_b32 s3, s3, 1
s_cmp_lt_u32 s4, 4
s_cbranch_scc1 .LBB7_6
s_mov_b32 s4, s5
s_branch .LBB7_2
.LBB7_6:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB7_8
s_add_i32 s5, s2, -1
s_add_i32 s6, s2, 7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshr_b32 s6, s5, s6
s_lshr_b32 s6, s6, 6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s6, s5
s_lshl_b32 s5, s6, 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s5, 0
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, s5
ds_store_b32 v5, v4
.LBB7_8:
s_or_b32 exec_lo, exec_lo, s4
s_cmp_lt_u32 s2, 2
s_cbranch_scc1 .LBB7_13
v_lshlrev_b32_e32 v5, 1, v0
s_mov_b32 s4, 1
s_delay_alu instid0(VALU_DEP_1)
v_or_b32_e32 v4, 1, v5
v_add_nc_u32_e32 v5, 2, v5
s_set_inst_prefetch_distance 0x1
s_branch .LBB7_11
.p2align 6
.LBB7_10:
s_or_b32 exec_lo, exec_lo, s5
s_lshl_b32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_u32 s4, s2
s_cbranch_scc1 .LBB7_13
.LBB7_11:
s_lshr_b32 s3, s3, 1
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB7_10
v_mul_lo_u32 v6, s3, v5
v_mul_lo_u32 v8, s3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v7, -1, v6
v_add_nc_u32_e32 v6, 7, v6
v_ashrrev_i32_e32 v6, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 6, v6
v_add_nc_u32_e32 v6, v6, v7
v_add_nc_u32_e32 v7, -1, v8
v_add_nc_u32_e32 v8, 7, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v6, v6, 2, 0
v_ashrrev_i32_e32 v8, v8, v7
ds_load_b32 v9, v6
v_ashrrev_i32_e32 v8, 6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v7, v8, v7
v_lshl_add_u32 v7, v7, 2, 0
ds_load_b32 v8, v7
s_waitcnt lgkmcnt(1)
ds_store_b32 v7, v9
ds_load_b32 v7, v6
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v7, v8, v7
ds_store_b32 v6, v7
s_branch .LBB7_10
.LBB7_13:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v3
ds_load_b32 v2, v2
v_lshlrev_b32_e32 v0, 2, v0
v_lshlrev_b32_e32 v1, 2, v1
s_waitcnt lgkmcnt(1)
global_store_b32 v0, v3, s[0:1]
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v2, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6cumSumPfS_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end7:
.size _Z6cumSumPfS_m, .Lfunc_end7-_Z6cumSumPfS_m
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecDivPfS_S_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecDivPfS_S_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7vecProdPfS_S_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7vecProdPfS_S_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecAddPfS_S_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecAddPfS_S_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecSubPfS_S_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecSubPfS_S_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
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You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* CUDA implementation of a fully-connected feed forward neural network
*
* Authors: Jevgenija Aksjonova (jevaks@kth.se)
* Beatrice Ionascu (bionascu@kth.se)
*
* Last changed: 04/30/2017
*/
#include <stdio.h>
#include <assert.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#define TOL 0.00000001
#define BATCH_SIZE 100
#define TRAIN_SET_SIZE 60000
#define TEST_SET_SIZE 10000
#define FUNCTION_TYPE 1 // 0 - tanh, 1 - relu
/* Read labels data */
void read_labels(const char filename[], int *array, int data_size) {
memset(array, 0, sizeof(int) * data_size);
FILE *file = fopen(filename, "r");
if (file) {
size_t i;
/* Read each line from the file. */
for (i = 0; i < data_size && !feof(file); i++) {
fscanf(file, "%d", array + i);
}
assert(i == data_size);
fclose(file);
} else {
perror(filename);
}
}
/* Read image data */
void read_images(const char *filename, double *array, int data_size, int batch_size, int batch_ind) {
FILE *file = fopen(filename, "r");
if (file) {
size_t i, j;
char buffer[data_size * 4], *ptr;
/* Read each line from the file. */
for (i = 0; fgets(buffer, sizeof buffer, file); ++i) {
/* Only parse data from desired batch. */
if (i >= batch_ind * batch_size && i < (batch_ind + 1) * batch_size ) {
/* Parse the comma-separated values from each line into 'array'. */
for (j = 0, ptr = buffer; j < data_size; j++, ptr++) {
array[(i - batch_ind * batch_size) * data_size + j] = strtol(ptr, &ptr, 10) / 256.0;
}
}
}
fclose(file);
} else {
perror(filename);
}
}
/* Compute local number of parameters (includes weights and biases) */
int param_size(int *layer_size, int num_layers) {
int size = 0;
size_t i;
for (i = 1; i < num_layers; i++) {
size = size + layer_size[i] * (layer_size[i-1] +1);
}
return size;
}
/* Compute total amount of data (includes the input data features and the layer outputs) */
int data_size(int *layer_size, int num_layers) {
int size = 0;
size_t i;
for (i = 0; i < num_layers; i++) {
size += layer_size[i];
}
return size;
}
/* Compute local starting index of the parameters corresponding to layer */
int param_ind(int layer, int *layer_size) {
int ind = 0;
size_t i;
for (i = 1; i < layer; i++) {
ind += layer_size[i] * (layer_size[i - 1] + 1);
}
return ind;
}
/* Compute local starting index of the data corresponding to layer */
int data_ind(int layer, int *layer_size) {
int ind = 0;
size_t i;
for (i = 0; i < layer; i++) {
ind += layer_size[i];
}
return ind;
}
/* Forward pass */
__global__
void forward(double *input, int inputSize, double *output, int outputSize, double *param, int fun) {
size_t i, j;
double l_output;
i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < outputSize ) {
/* Initialize output with the bias term */
l_output = param[i];
for (j = 0; j < inputSize; j++) {
// Add weighted inputs
l_output += param[(j+1)*outputSize + i] * input[j];
}
/* Activation */
if (fun > 0) {
if (FUNCTION_TYPE == 0) {
l_output = tanh(l_output);
}
else if (FUNCTION_TYPE == 1) { // relu function
if (l_output <= 0) {
l_output = 0.0;
}
}
}
output[i] = l_output;
}
}
/* Backward pass (backpropagate gradients from current_layer to prev_layer) */
__global__
void backward_part1(double *current_layer, int layer_size, double *prev_layer, int prev_layer_size,
double *param, double *grad_param, int layer,double lambda) {
size_t i, j;
double l_current_layer;
i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < layer_size) {
l_current_layer = current_layer[i];
// Update parameters
grad_param[i] += l_current_layer;
for (j = 0; j < prev_layer_size; j++) {
grad_param[(j+1) * layer_size + i ] += l_current_layer * prev_layer[j] +
2.0 * lambda * param[(j+1) * layer_size + i]; // regularization
}
}
}
__global__
void backward_part2(double *current_layer, int layer_size, double *prev_layer, int prev_layer_size,
double *param, double *grad_param, int layer,double lambda) {
size_t i, k;
double l_prev_layer;
i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < prev_layer_size ) {
l_prev_layer = prev_layer[i];
// backprapogate partial derivatives
if (FUNCTION_TYPE == 0) {
double localGrad = (1-pow(l_prev_layer,2)); // tanh derivative
l_prev_layer = 0.0;
for (k = 0; k < layer_size; k++) {
l_prev_layer += current_layer[k] * param[(i+1) * layer_size + k];
}
l_prev_layer *= localGrad;
} else if (FUNCTION_TYPE == 1) {
if (l_prev_layer >0.0) {
l_prev_layer = 0.0;
for (k = 0; k < layer_size; k++) {
l_prev_layer += current_layer[k] * param[(i+1) * layer_size + k];
}
} else {
l_prev_layer = 0.0;
}
}
prev_layer[i] = l_prev_layer;
}
}
__global__
void update_param(double *param, double *grad_param, int num_param, double learning_rate, int batch_size) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < num_param) {
param[i] = param[i] - learning_rate * grad_param[i] / (float)batch_size;
}
}
/* Train the network */
void train(const char filename[], int* label, double *d_param, double *d_grad_param, int *layer_size, int num_layers,
int epochs, double lambda, double learning_rate) {
size_t img, ep = 0;
int i, layer, batch_index;
int input_pointer, output_pointer, param_pointer;
double sum, global_loss = 1;
int image_size = layer_size[0];
int num_param = param_size(layer_size, num_layers);
/* Allocate image data array */
double *images;
images = (double *) malloc(BATCH_SIZE * image_size * sizeof(double));
/* Allocate data array */
double *d_data ;
cudaMalloc( (void**)&d_data, data_size(layer_size, num_layers) * sizeof(double));
/* Loop over epochs (one epoch = loop over all images) */
while (ep++ < epochs && global_loss > TOL) {
/* Loop over batches */
for (batch_index = 0; batch_index < TRAIN_SET_SIZE / BATCH_SIZE; batch_index++) {
/* Initialize loss */
global_loss = 0.0;
/* Reset gradients to 0 */
cudaMemset(d_grad_param, 0.0, num_param * sizeof(double));
/* Load images in batch */
read_images(filename, images, image_size, BATCH_SIZE, batch_index);
/* Loop over images in batch */
for (img = 0; img < BATCH_SIZE; img++) {
/* Copy one image to the 1st layer of the data */
cudaMemcpy(d_data, images + img * image_size, image_size * sizeof(double), cudaMemcpyHostToDevice );
/* Forward pass */
for (layer = 1; layer < num_layers; layer++) {
input_pointer = data_ind(layer - 1, layer_size);
output_pointer = data_ind(layer, layer_size);
param_pointer = param_ind(layer, layer_size);
dim3 dimBlock( 128,1,1 );
dim3 dimGrid(ceil((float)layer_size[layer]/128.0),1,1);
forward<<<dimGrid, dimBlock>>>(d_data + input_pointer, layer_size[layer - 1], d_data + output_pointer, layer_size[layer],
d_param + param_pointer, num_layers - layer - 1);
}
double *probs;
probs = (double * ) malloc(layer_size[num_layers - 1]* sizeof(double));
int probs_pointer = data_ind(num_layers - 1, layer_size);
cudaMemcpy(probs, d_data + probs_pointer, layer_size[num_layers - 1] * sizeof(double), cudaMemcpyDeviceToHost);
/* Softmax */
sum = 0.0;
for ( i = 0; i < layer_size[num_layers - 1]; i++) {
sum += exp(probs[i]);
}
for ( i = 0; i < layer_size[num_layers - 1]; i++) {
probs[i] = exp(probs[i]) / sum;
}
/* Loss computation */
/* Compute the cross-entropy loss by adding the log probabilities assigned to the correct classes */
global_loss += -log(probs[label[batch_index * BATCH_SIZE + img]]);
/* Gradient computation for the last (score) layer */
probs[label[batch_index * BATCH_SIZE + img]] -= 1.0;
cudaMemcpy(d_data+probs_pointer, probs, layer_size[num_layers - 1]*sizeof(double), cudaMemcpyHostToDevice);
/* Backpropagation */
for (layer = num_layers - 1; layer > 0; layer--) {
input_pointer = data_ind(layer, layer_size);
output_pointer = data_ind(layer - 1, layer_size);
param_pointer = param_ind(layer, layer_size);
dim3 dimBlock( 128, 1, 1 );
dim3 dimGrid( ceil((float)layer_size[layer]/128.0), 1, 1 );
backward_part1<<<dimGrid, dimBlock>>>(d_data + input_pointer, layer_size[layer], d_data + output_pointer, layer_size[layer - 1],
d_param + param_pointer, d_grad_param + param_pointer, layer, lambda);
if (layer > 1) {
dim3 dimBlock( 128, 1, 1 );
dim3 dimGrid( ceil((float)layer_size[layer - 1]/128.0), 1, 1 );
backward_part2<<<dimGrid, dimBlock>>>(d_data + input_pointer, layer_size[layer], d_data + output_pointer, layer_size[layer - 1],
d_param + param_pointer, d_grad_param + param_pointer, layer, lambda);
}
}
}
/* Update parameters using gradient averaged over batch)*/
dim3 dimBlock(512, 1, 1 );
dim3 dimGrid( ceil((float)num_param/512.0), 1 ,1 );
update_param<<<dimGrid, dimBlock>>>(d_param, d_grad_param, num_param, learning_rate, BATCH_SIZE);
/* Compute global loss averaged over batch */
global_loss /= BATCH_SIZE;
if (batch_index % 100 == 0) {
printf("Ep: %zu/%d\t batch:%d \t train loss: %f\n", ep, epochs, batch_index, global_loss);
}
}
}
cudaFree(d_data);
free(images);
}
/* Test the network */
void test(const char filename[], int* label, double *d_param, int *layer_size, int num_layers) {
int it, layer, i;
int input_pointer, output_pointer, param_pointer, probs_pointer, predicted_class;
double sum, predicted_class_score, global_loss = 0.0;
int image_size = layer_size[0];
int acc = 0;
/* Allocate image data array */
double *images;
images = (double *) malloc(image_size* sizeof(double));
/* Allocate data array */
double *d_data ;
cudaMalloc( (void**)&d_data, data_size(layer_size,num_layers)*sizeof(double));
/* Loop over batches */
for (it = 0; it < TEST_SET_SIZE; it++) {
/* Load image data */
read_images(filename, images, image_size, 1, it);
/* Copy one image to the 1st layer of the data */
cudaMemcpy(d_data, images, image_size * sizeof(double),cudaMemcpyHostToDevice);
/* Forward pass */
for (layer = 1; layer < num_layers; layer++) {
input_pointer = data_ind(layer - 1, layer_size);
output_pointer = data_ind(layer, layer_size);
param_pointer = param_ind(layer, layer_size);
dim3 dimBlock( 128, 1, 1 );
dim3 dimGrid( ceil((float)layer_size[layer]/128.0), 1, 1 );
forward<<<dimGrid, dimBlock>>>(d_data + input_pointer, layer_size[layer - 1], d_data + output_pointer, layer_size[layer],
d_param + param_pointer, num_layers - layer - 1);
}
/* Softmax and Predict class */
double *probs;
probs = (double * ) malloc(layer_size[num_layers - 1] * sizeof(double));
probs_pointer = data_ind(num_layers - 1, layer_size);
cudaMemcpy(probs, d_data+probs_pointer, layer_size[num_layers - 1]*sizeof(double), cudaMemcpyDeviceToHost);
sum = 0.0;
for (i = 0; i < layer_size[num_layers - 1]; i++) {
sum += exp(probs[i]);
}
predicted_class_score = -1.0;
predicted_class = -1;
for (i = 0; i < layer_size[num_layers - 1]; i++) {
/* Compute normalized probability of the correct class */
probs[i] = exp(probs[i])/sum;
/* Argmax */
if (probs[i] > predicted_class_score) {
predicted_class_score = probs[i];
predicted_class = i;
}
}
/* Compute accuracy */
if (predicted_class == label[it]) {
acc++;
}
/* Compute the cross-entropy loss by adding the log probabilities assigned to the correct classes */
global_loss += -log(probs[label[it]]);
if ((it+1) % 1000 == 0) {
printf("Test set size: %d\tloss: %f\taccuracy:%f\n",
it + 1, global_loss / (it + 1), (float) acc / (float) (it + 1));
}
}
cudaFree(d_data);
free(images);
}
int main(int argc, char **argv) {
/* local variables */
int epochs, W = 28, H = 28;
const char train_images_filename[] = "./mnist_data/train_images.csv";
const char train_labels_filename[] = "./mnist_data/train_labels.csv";
const char test_images_filename[] = "./mnist_data/test_images.csv";
const char test_labels_filename[] = "./mnist_data/test_labels.csv";
/* Read number of epochs from command line */
if (argc < 2) {
printf("Number of epochs is not given \n");
exit(1);
}
epochs = atoi(argv[1]);
/* Set neural network parameters */
double lambda = 0.0005, learning_rate = 0.01;
int num_layers = 4;
int layer_size[4] = {W*H,300,100,10};
int p_size = param_size(layer_size, num_layers) * sizeof(double);
double *h_param, *d_param;
double *h_grad_param, *d_grad_param;
int *train_label, *test_label;
/* Allocate memory and read training labels */
train_label = (int *) malloc(TRAIN_SET_SIZE * sizeof(int));
read_labels(train_labels_filename, train_label, TRAIN_SET_SIZE);
/* Allocate memory for parameters */
h_param = (double *) malloc(p_size);
h_grad_param = (double *) malloc(p_size);
cudaMalloc( (void**)&d_param, p_size);
cudaMalloc( (void**)&d_grad_param, p_size);
srandom(1);
/* Initialize parameters using "xavier" initialization */
int layer, i, j;
for (layer = 1; layer < num_layers; layer++) {
double a = sqrt(3.0/(float)layer_size[layer-1]); // uniform interval limit
int param_pointer = param_ind(layer, layer_size);
for (i = 0; i < layer_size[layer]; i++) {
h_param[param_pointer + i] = 0.0; // bias
}
for (j = 1; j < layer_size[layer - 1] +1; j++) {
for (i = 0; i < layer_size[layer]; i++) {
h_param[param_pointer + j * layer_size[layer] + i] = 2.0 * a * (double) random() / RAND_MAX - a;
}
}
}
/* Initialize gradients with 0 */
memset(h_grad_param, 0, p_size);
cudaMemcpy( d_param, h_param, p_size, cudaMemcpyHostToDevice );
cudaMemcpy( d_grad_param, h_grad_param, p_size, cudaMemcpyHostToDevice );
/* Train network */
train(train_images_filename, train_label, d_param, d_grad_param, layer_size, num_layers, epochs, lambda, learning_rate);
/* Deallocate arrays */
free(h_grad_param);
cudaFree(d_grad_param);
free(train_label);
/* Allocate memory and read testing labels */
test_label = (int *) malloc(TEST_SET_SIZE * sizeof(int));
read_labels(test_labels_filename, test_label, TEST_SET_SIZE);
/* Test network */
test(test_images_filename, test_label, d_param, layer_size, num_layers);
/* Deallocate arrays */
free(h_param);
cudaFree(d_param);
free(test_label);
return 0;
} | /**
* CUDA implementation of a fully-connected feed forward neural network
*
* Authors: Jevgenija Aksjonova (jevaks@kth.se)
* Beatrice Ionascu (bionascu@kth.se)
*
* Last changed: 04/30/2017
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#define TOL 0.00000001
#define BATCH_SIZE 100
#define TRAIN_SET_SIZE 60000
#define TEST_SET_SIZE 10000
#define FUNCTION_TYPE 1 // 0 - tanh, 1 - relu
/* Read labels data */
void read_labels(const char filename[], int *array, int data_size) {
memset(array, 0, sizeof(int) * data_size);
FILE *file = fopen(filename, "r");
if (file) {
size_t i;
/* Read each line from the file. */
for (i = 0; i < data_size && !feof(file); i++) {
fscanf(file, "%d", array + i);
}
assert(i == data_size);
fclose(file);
} else {
perror(filename);
}
}
/* Read image data */
void read_images(const char *filename, double *array, int data_size, int batch_size, int batch_ind) {
FILE *file = fopen(filename, "r");
if (file) {
size_t i, j;
char buffer[data_size * 4], *ptr;
/* Read each line from the file. */
for (i = 0; fgets(buffer, sizeof buffer, file); ++i) {
/* Only parse data from desired batch. */
if (i >= batch_ind * batch_size && i < (batch_ind + 1) * batch_size ) {
/* Parse the comma-separated values from each line into 'array'. */
for (j = 0, ptr = buffer; j < data_size; j++, ptr++) {
array[(i - batch_ind * batch_size) * data_size + j] = strtol(ptr, &ptr, 10) / 256.0;
}
}
}
fclose(file);
} else {
perror(filename);
}
}
/* Compute local number of parameters (includes weights and biases) */
int param_size(int *layer_size, int num_layers) {
int size = 0;
size_t i;
for (i = 1; i < num_layers; i++) {
size = size + layer_size[i] * (layer_size[i-1] +1);
}
return size;
}
/* Compute total amount of data (includes the input data features and the layer outputs) */
int data_size(int *layer_size, int num_layers) {
int size = 0;
size_t i;
for (i = 0; i < num_layers; i++) {
size += layer_size[i];
}
return size;
}
/* Compute local starting index of the parameters corresponding to layer */
int param_ind(int layer, int *layer_size) {
int ind = 0;
size_t i;
for (i = 1; i < layer; i++) {
ind += layer_size[i] * (layer_size[i - 1] + 1);
}
return ind;
}
/* Compute local starting index of the data corresponding to layer */
int data_ind(int layer, int *layer_size) {
int ind = 0;
size_t i;
for (i = 0; i < layer; i++) {
ind += layer_size[i];
}
return ind;
}
/* Forward pass */
__global__
void forward(double *input, int inputSize, double *output, int outputSize, double *param, int fun) {
size_t i, j;
double l_output;
i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < outputSize ) {
/* Initialize output with the bias term */
l_output = param[i];
for (j = 0; j < inputSize; j++) {
// Add weighted inputs
l_output += param[(j+1)*outputSize + i] * input[j];
}
/* Activation */
if (fun > 0) {
if (FUNCTION_TYPE == 0) {
l_output = tanh(l_output);
}
else if (FUNCTION_TYPE == 1) { // relu function
if (l_output <= 0) {
l_output = 0.0;
}
}
}
output[i] = l_output;
}
}
/* Backward pass (backpropagate gradients from current_layer to prev_layer) */
__global__
void backward_part1(double *current_layer, int layer_size, double *prev_layer, int prev_layer_size,
double *param, double *grad_param, int layer,double lambda) {
size_t i, j;
double l_current_layer;
i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < layer_size) {
l_current_layer = current_layer[i];
// Update parameters
grad_param[i] += l_current_layer;
for (j = 0; j < prev_layer_size; j++) {
grad_param[(j+1) * layer_size + i ] += l_current_layer * prev_layer[j] +
2.0 * lambda * param[(j+1) * layer_size + i]; // regularization
}
}
}
__global__
void backward_part2(double *current_layer, int layer_size, double *prev_layer, int prev_layer_size,
double *param, double *grad_param, int layer,double lambda) {
size_t i, k;
double l_prev_layer;
i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < prev_layer_size ) {
l_prev_layer = prev_layer[i];
// backprapogate partial derivatives
if (FUNCTION_TYPE == 0) {
double localGrad = (1-pow(l_prev_layer,2)); // tanh derivative
l_prev_layer = 0.0;
for (k = 0; k < layer_size; k++) {
l_prev_layer += current_layer[k] * param[(i+1) * layer_size + k];
}
l_prev_layer *= localGrad;
} else if (FUNCTION_TYPE == 1) {
if (l_prev_layer >0.0) {
l_prev_layer = 0.0;
for (k = 0; k < layer_size; k++) {
l_prev_layer += current_layer[k] * param[(i+1) * layer_size + k];
}
} else {
l_prev_layer = 0.0;
}
}
prev_layer[i] = l_prev_layer;
}
}
__global__
void update_param(double *param, double *grad_param, int num_param, double learning_rate, int batch_size) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < num_param) {
param[i] = param[i] - learning_rate * grad_param[i] / (float)batch_size;
}
}
/* Train the network */
void train(const char filename[], int* label, double *d_param, double *d_grad_param, int *layer_size, int num_layers,
int epochs, double lambda, double learning_rate) {
size_t img, ep = 0;
int i, layer, batch_index;
int input_pointer, output_pointer, param_pointer;
double sum, global_loss = 1;
int image_size = layer_size[0];
int num_param = param_size(layer_size, num_layers);
/* Allocate image data array */
double *images;
images = (double *) malloc(BATCH_SIZE * image_size * sizeof(double));
/* Allocate data array */
double *d_data ;
hipMalloc( (void**)&d_data, data_size(layer_size, num_layers) * sizeof(double));
/* Loop over epochs (one epoch = loop over all images) */
while (ep++ < epochs && global_loss > TOL) {
/* Loop over batches */
for (batch_index = 0; batch_index < TRAIN_SET_SIZE / BATCH_SIZE; batch_index++) {
/* Initialize loss */
global_loss = 0.0;
/* Reset gradients to 0 */
hipMemset(d_grad_param, 0.0, num_param * sizeof(double));
/* Load images in batch */
read_images(filename, images, image_size, BATCH_SIZE, batch_index);
/* Loop over images in batch */
for (img = 0; img < BATCH_SIZE; img++) {
/* Copy one image to the 1st layer of the data */
hipMemcpy(d_data, images + img * image_size, image_size * sizeof(double), hipMemcpyHostToDevice );
/* Forward pass */
for (layer = 1; layer < num_layers; layer++) {
input_pointer = data_ind(layer - 1, layer_size);
output_pointer = data_ind(layer, layer_size);
param_pointer = param_ind(layer, layer_size);
dim3 dimBlock( 128,1,1 );
dim3 dimGrid(ceil((float)layer_size[layer]/128.0),1,1);
forward<<<dimGrid, dimBlock>>>(d_data + input_pointer, layer_size[layer - 1], d_data + output_pointer, layer_size[layer],
d_param + param_pointer, num_layers - layer - 1);
}
double *probs;
probs = (double * ) malloc(layer_size[num_layers - 1]* sizeof(double));
int probs_pointer = data_ind(num_layers - 1, layer_size);
hipMemcpy(probs, d_data + probs_pointer, layer_size[num_layers - 1] * sizeof(double), hipMemcpyDeviceToHost);
/* Softmax */
sum = 0.0;
for ( i = 0; i < layer_size[num_layers - 1]; i++) {
sum += exp(probs[i]);
}
for ( i = 0; i < layer_size[num_layers - 1]; i++) {
probs[i] = exp(probs[i]) / sum;
}
/* Loss computation */
/* Compute the cross-entropy loss by adding the log probabilities assigned to the correct classes */
global_loss += -log(probs[label[batch_index * BATCH_SIZE + img]]);
/* Gradient computation for the last (score) layer */
probs[label[batch_index * BATCH_SIZE + img]] -= 1.0;
hipMemcpy(d_data+probs_pointer, probs, layer_size[num_layers - 1]*sizeof(double), hipMemcpyHostToDevice);
/* Backpropagation */
for (layer = num_layers - 1; layer > 0; layer--) {
input_pointer = data_ind(layer, layer_size);
output_pointer = data_ind(layer - 1, layer_size);
param_pointer = param_ind(layer, layer_size);
dim3 dimBlock( 128, 1, 1 );
dim3 dimGrid( ceil((float)layer_size[layer]/128.0), 1, 1 );
backward_part1<<<dimGrid, dimBlock>>>(d_data + input_pointer, layer_size[layer], d_data + output_pointer, layer_size[layer - 1],
d_param + param_pointer, d_grad_param + param_pointer, layer, lambda);
if (layer > 1) {
dim3 dimBlock( 128, 1, 1 );
dim3 dimGrid( ceil((float)layer_size[layer - 1]/128.0), 1, 1 );
backward_part2<<<dimGrid, dimBlock>>>(d_data + input_pointer, layer_size[layer], d_data + output_pointer, layer_size[layer - 1],
d_param + param_pointer, d_grad_param + param_pointer, layer, lambda);
}
}
}
/* Update parameters using gradient averaged over batch)*/
dim3 dimBlock(512, 1, 1 );
dim3 dimGrid( ceil((float)num_param/512.0), 1 ,1 );
update_param<<<dimGrid, dimBlock>>>(d_param, d_grad_param, num_param, learning_rate, BATCH_SIZE);
/* Compute global loss averaged over batch */
global_loss /= BATCH_SIZE;
if (batch_index % 100 == 0) {
printf("Ep: %zu/%d\t batch:%d \t train loss: %f\n", ep, epochs, batch_index, global_loss);
}
}
}
hipFree(d_data);
free(images);
}
/* Test the network */
void test(const char filename[], int* label, double *d_param, int *layer_size, int num_layers) {
int it, layer, i;
int input_pointer, output_pointer, param_pointer, probs_pointer, predicted_class;
double sum, predicted_class_score, global_loss = 0.0;
int image_size = layer_size[0];
int acc = 0;
/* Allocate image data array */
double *images;
images = (double *) malloc(image_size* sizeof(double));
/* Allocate data array */
double *d_data ;
hipMalloc( (void**)&d_data, data_size(layer_size,num_layers)*sizeof(double));
/* Loop over batches */
for (it = 0; it < TEST_SET_SIZE; it++) {
/* Load image data */
read_images(filename, images, image_size, 1, it);
/* Copy one image to the 1st layer of the data */
hipMemcpy(d_data, images, image_size * sizeof(double),hipMemcpyHostToDevice);
/* Forward pass */
for (layer = 1; layer < num_layers; layer++) {
input_pointer = data_ind(layer - 1, layer_size);
output_pointer = data_ind(layer, layer_size);
param_pointer = param_ind(layer, layer_size);
dim3 dimBlock( 128, 1, 1 );
dim3 dimGrid( ceil((float)layer_size[layer]/128.0), 1, 1 );
forward<<<dimGrid, dimBlock>>>(d_data + input_pointer, layer_size[layer - 1], d_data + output_pointer, layer_size[layer],
d_param + param_pointer, num_layers - layer - 1);
}
/* Softmax and Predict class */
double *probs;
probs = (double * ) malloc(layer_size[num_layers - 1] * sizeof(double));
probs_pointer = data_ind(num_layers - 1, layer_size);
hipMemcpy(probs, d_data+probs_pointer, layer_size[num_layers - 1]*sizeof(double), hipMemcpyDeviceToHost);
sum = 0.0;
for (i = 0; i < layer_size[num_layers - 1]; i++) {
sum += exp(probs[i]);
}
predicted_class_score = -1.0;
predicted_class = -1;
for (i = 0; i < layer_size[num_layers - 1]; i++) {
/* Compute normalized probability of the correct class */
probs[i] = exp(probs[i])/sum;
/* Argmax */
if (probs[i] > predicted_class_score) {
predicted_class_score = probs[i];
predicted_class = i;
}
}
/* Compute accuracy */
if (predicted_class == label[it]) {
acc++;
}
/* Compute the cross-entropy loss by adding the log probabilities assigned to the correct classes */
global_loss += -log(probs[label[it]]);
if ((it+1) % 1000 == 0) {
printf("Test set size: %d\tloss: %f\taccuracy:%f\n",
it + 1, global_loss / (it + 1), (float) acc / (float) (it + 1));
}
}
hipFree(d_data);
free(images);
}
int main(int argc, char **argv) {
/* local variables */
int epochs, W = 28, H = 28;
const char train_images_filename[] = "./mnist_data/train_images.csv";
const char train_labels_filename[] = "./mnist_data/train_labels.csv";
const char test_images_filename[] = "./mnist_data/test_images.csv";
const char test_labels_filename[] = "./mnist_data/test_labels.csv";
/* Read number of epochs from command line */
if (argc < 2) {
printf("Number of epochs is not given \n");
exit(1);
}
epochs = atoi(argv[1]);
/* Set neural network parameters */
double lambda = 0.0005, learning_rate = 0.01;
int num_layers = 4;
int layer_size[4] = {W*H,300,100,10};
int p_size = param_size(layer_size, num_layers) * sizeof(double);
double *h_param, *d_param;
double *h_grad_param, *d_grad_param;
int *train_label, *test_label;
/* Allocate memory and read training labels */
train_label = (int *) malloc(TRAIN_SET_SIZE * sizeof(int));
read_labels(train_labels_filename, train_label, TRAIN_SET_SIZE);
/* Allocate memory for parameters */
h_param = (double *) malloc(p_size);
h_grad_param = (double *) malloc(p_size);
hipMalloc( (void**)&d_param, p_size);
hipMalloc( (void**)&d_grad_param, p_size);
srandom(1);
/* Initialize parameters using "xavier" initialization */
int layer, i, j;
for (layer = 1; layer < num_layers; layer++) {
double a = sqrt(3.0/(float)layer_size[layer-1]); // uniform interval limit
int param_pointer = param_ind(layer, layer_size);
for (i = 0; i < layer_size[layer]; i++) {
h_param[param_pointer + i] = 0.0; // bias
}
for (j = 1; j < layer_size[layer - 1] +1; j++) {
for (i = 0; i < layer_size[layer]; i++) {
h_param[param_pointer + j * layer_size[layer] + i] = 2.0 * a * (double) random() / RAND_MAX - a;
}
}
}
/* Initialize gradients with 0 */
memset(h_grad_param, 0, p_size);
hipMemcpy( d_param, h_param, p_size, hipMemcpyHostToDevice );
hipMemcpy( d_grad_param, h_grad_param, p_size, hipMemcpyHostToDevice );
/* Train network */
train(train_images_filename, train_label, d_param, d_grad_param, layer_size, num_layers, epochs, lambda, learning_rate);
/* Deallocate arrays */
free(h_grad_param);
hipFree(d_grad_param);
free(train_label);
/* Allocate memory and read testing labels */
test_label = (int *) malloc(TEST_SET_SIZE * sizeof(int));
read_labels(test_labels_filename, test_label, TEST_SET_SIZE);
/* Test network */
test(test_images_filename, test_label, d_param, layer_size, num_layers);
/* Deallocate arrays */
free(h_param);
hipFree(d_param);
free(test_label);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
* CUDA implementation of a fully-connected feed forward neural network
*
* Authors: Jevgenija Aksjonova (jevaks@kth.se)
* Beatrice Ionascu (bionascu@kth.se)
*
* Last changed: 04/30/2017
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#define TOL 0.00000001
#define BATCH_SIZE 100
#define TRAIN_SET_SIZE 60000
#define TEST_SET_SIZE 10000
#define FUNCTION_TYPE 1 // 0 - tanh, 1 - relu
/* Read labels data */
void read_labels(const char filename[], int *array, int data_size) {
memset(array, 0, sizeof(int) * data_size);
FILE *file = fopen(filename, "r");
if (file) {
size_t i;
/* Read each line from the file. */
for (i = 0; i < data_size && !feof(file); i++) {
fscanf(file, "%d", array + i);
}
assert(i == data_size);
fclose(file);
} else {
perror(filename);
}
}
/* Read image data */
void read_images(const char *filename, double *array, int data_size, int batch_size, int batch_ind) {
FILE *file = fopen(filename, "r");
if (file) {
size_t i, j;
char buffer[data_size * 4], *ptr;
/* Read each line from the file. */
for (i = 0; fgets(buffer, sizeof buffer, file); ++i) {
/* Only parse data from desired batch. */
if (i >= batch_ind * batch_size && i < (batch_ind + 1) * batch_size ) {
/* Parse the comma-separated values from each line into 'array'. */
for (j = 0, ptr = buffer; j < data_size; j++, ptr++) {
array[(i - batch_ind * batch_size) * data_size + j] = strtol(ptr, &ptr, 10) / 256.0;
}
}
}
fclose(file);
} else {
perror(filename);
}
}
/* Compute local number of parameters (includes weights and biases) */
int param_size(int *layer_size, int num_layers) {
int size = 0;
size_t i;
for (i = 1; i < num_layers; i++) {
size = size + layer_size[i] * (layer_size[i-1] +1);
}
return size;
}
/* Compute total amount of data (includes the input data features and the layer outputs) */
int data_size(int *layer_size, int num_layers) {
int size = 0;
size_t i;
for (i = 0; i < num_layers; i++) {
size += layer_size[i];
}
return size;
}
/* Compute local starting index of the parameters corresponding to layer */
int param_ind(int layer, int *layer_size) {
int ind = 0;
size_t i;
for (i = 1; i < layer; i++) {
ind += layer_size[i] * (layer_size[i - 1] + 1);
}
return ind;
}
/* Compute local starting index of the data corresponding to layer */
int data_ind(int layer, int *layer_size) {
int ind = 0;
size_t i;
for (i = 0; i < layer; i++) {
ind += layer_size[i];
}
return ind;
}
/* Forward pass */
__global__
void forward(double *input, int inputSize, double *output, int outputSize, double *param, int fun) {
size_t i, j;
double l_output;
i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < outputSize ) {
/* Initialize output with the bias term */
l_output = param[i];
for (j = 0; j < inputSize; j++) {
// Add weighted inputs
l_output += param[(j+1)*outputSize + i] * input[j];
}
/* Activation */
if (fun > 0) {
if (FUNCTION_TYPE == 0) {
l_output = tanh(l_output);
}
else if (FUNCTION_TYPE == 1) { // relu function
if (l_output <= 0) {
l_output = 0.0;
}
}
}
output[i] = l_output;
}
}
/* Backward pass (backpropagate gradients from current_layer to prev_layer) */
__global__
void backward_part1(double *current_layer, int layer_size, double *prev_layer, int prev_layer_size,
double *param, double *grad_param, int layer,double lambda) {
size_t i, j;
double l_current_layer;
i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < layer_size) {
l_current_layer = current_layer[i];
// Update parameters
grad_param[i] += l_current_layer;
for (j = 0; j < prev_layer_size; j++) {
grad_param[(j+1) * layer_size + i ] += l_current_layer * prev_layer[j] +
2.0 * lambda * param[(j+1) * layer_size + i]; // regularization
}
}
}
__global__
void backward_part2(double *current_layer, int layer_size, double *prev_layer, int prev_layer_size,
double *param, double *grad_param, int layer,double lambda) {
size_t i, k;
double l_prev_layer;
i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < prev_layer_size ) {
l_prev_layer = prev_layer[i];
// backprapogate partial derivatives
if (FUNCTION_TYPE == 0) {
double localGrad = (1-pow(l_prev_layer,2)); // tanh derivative
l_prev_layer = 0.0;
for (k = 0; k < layer_size; k++) {
l_prev_layer += current_layer[k] * param[(i+1) * layer_size + k];
}
l_prev_layer *= localGrad;
} else if (FUNCTION_TYPE == 1) {
if (l_prev_layer >0.0) {
l_prev_layer = 0.0;
for (k = 0; k < layer_size; k++) {
l_prev_layer += current_layer[k] * param[(i+1) * layer_size + k];
}
} else {
l_prev_layer = 0.0;
}
}
prev_layer[i] = l_prev_layer;
}
}
__global__
void update_param(double *param, double *grad_param, int num_param, double learning_rate, int batch_size) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < num_param) {
param[i] = param[i] - learning_rate * grad_param[i] / (float)batch_size;
}
}
/* Train the network */
void train(const char filename[], int* label, double *d_param, double *d_grad_param, int *layer_size, int num_layers,
int epochs, double lambda, double learning_rate) {
size_t img, ep = 0;
int i, layer, batch_index;
int input_pointer, output_pointer, param_pointer;
double sum, global_loss = 1;
int image_size = layer_size[0];
int num_param = param_size(layer_size, num_layers);
/* Allocate image data array */
double *images;
images = (double *) malloc(BATCH_SIZE * image_size * sizeof(double));
/* Allocate data array */
double *d_data ;
hipMalloc( (void**)&d_data, data_size(layer_size, num_layers) * sizeof(double));
/* Loop over epochs (one epoch = loop over all images) */
while (ep++ < epochs && global_loss > TOL) {
/* Loop over batches */
for (batch_index = 0; batch_index < TRAIN_SET_SIZE / BATCH_SIZE; batch_index++) {
/* Initialize loss */
global_loss = 0.0;
/* Reset gradients to 0 */
hipMemset(d_grad_param, 0.0, num_param * sizeof(double));
/* Load images in batch */
read_images(filename, images, image_size, BATCH_SIZE, batch_index);
/* Loop over images in batch */
for (img = 0; img < BATCH_SIZE; img++) {
/* Copy one image to the 1st layer of the data */
hipMemcpy(d_data, images + img * image_size, image_size * sizeof(double), hipMemcpyHostToDevice );
/* Forward pass */
for (layer = 1; layer < num_layers; layer++) {
input_pointer = data_ind(layer - 1, layer_size);
output_pointer = data_ind(layer, layer_size);
param_pointer = param_ind(layer, layer_size);
dim3 dimBlock( 128,1,1 );
dim3 dimGrid(ceil((float)layer_size[layer]/128.0),1,1);
forward<<<dimGrid, dimBlock>>>(d_data + input_pointer, layer_size[layer - 1], d_data + output_pointer, layer_size[layer],
d_param + param_pointer, num_layers - layer - 1);
}
double *probs;
probs = (double * ) malloc(layer_size[num_layers - 1]* sizeof(double));
int probs_pointer = data_ind(num_layers - 1, layer_size);
hipMemcpy(probs, d_data + probs_pointer, layer_size[num_layers - 1] * sizeof(double), hipMemcpyDeviceToHost);
/* Softmax */
sum = 0.0;
for ( i = 0; i < layer_size[num_layers - 1]; i++) {
sum += exp(probs[i]);
}
for ( i = 0; i < layer_size[num_layers - 1]; i++) {
probs[i] = exp(probs[i]) / sum;
}
/* Loss computation */
/* Compute the cross-entropy loss by adding the log probabilities assigned to the correct classes */
global_loss += -log(probs[label[batch_index * BATCH_SIZE + img]]);
/* Gradient computation for the last (score) layer */
probs[label[batch_index * BATCH_SIZE + img]] -= 1.0;
hipMemcpy(d_data+probs_pointer, probs, layer_size[num_layers - 1]*sizeof(double), hipMemcpyHostToDevice);
/* Backpropagation */
for (layer = num_layers - 1; layer > 0; layer--) {
input_pointer = data_ind(layer, layer_size);
output_pointer = data_ind(layer - 1, layer_size);
param_pointer = param_ind(layer, layer_size);
dim3 dimBlock( 128, 1, 1 );
dim3 dimGrid( ceil((float)layer_size[layer]/128.0), 1, 1 );
backward_part1<<<dimGrid, dimBlock>>>(d_data + input_pointer, layer_size[layer], d_data + output_pointer, layer_size[layer - 1],
d_param + param_pointer, d_grad_param + param_pointer, layer, lambda);
if (layer > 1) {
dim3 dimBlock( 128, 1, 1 );
dim3 dimGrid( ceil((float)layer_size[layer - 1]/128.0), 1, 1 );
backward_part2<<<dimGrid, dimBlock>>>(d_data + input_pointer, layer_size[layer], d_data + output_pointer, layer_size[layer - 1],
d_param + param_pointer, d_grad_param + param_pointer, layer, lambda);
}
}
}
/* Update parameters using gradient averaged over batch)*/
dim3 dimBlock(512, 1, 1 );
dim3 dimGrid( ceil((float)num_param/512.0), 1 ,1 );
update_param<<<dimGrid, dimBlock>>>(d_param, d_grad_param, num_param, learning_rate, BATCH_SIZE);
/* Compute global loss averaged over batch */
global_loss /= BATCH_SIZE;
if (batch_index % 100 == 0) {
printf("Ep: %zu/%d\t batch:%d \t train loss: %f\n", ep, epochs, batch_index, global_loss);
}
}
}
hipFree(d_data);
free(images);
}
/* Test the network */
void test(const char filename[], int* label, double *d_param, int *layer_size, int num_layers) {
int it, layer, i;
int input_pointer, output_pointer, param_pointer, probs_pointer, predicted_class;
double sum, predicted_class_score, global_loss = 0.0;
int image_size = layer_size[0];
int acc = 0;
/* Allocate image data array */
double *images;
images = (double *) malloc(image_size* sizeof(double));
/* Allocate data array */
double *d_data ;
hipMalloc( (void**)&d_data, data_size(layer_size,num_layers)*sizeof(double));
/* Loop over batches */
for (it = 0; it < TEST_SET_SIZE; it++) {
/* Load image data */
read_images(filename, images, image_size, 1, it);
/* Copy one image to the 1st layer of the data */
hipMemcpy(d_data, images, image_size * sizeof(double),hipMemcpyHostToDevice);
/* Forward pass */
for (layer = 1; layer < num_layers; layer++) {
input_pointer = data_ind(layer - 1, layer_size);
output_pointer = data_ind(layer, layer_size);
param_pointer = param_ind(layer, layer_size);
dim3 dimBlock( 128, 1, 1 );
dim3 dimGrid( ceil((float)layer_size[layer]/128.0), 1, 1 );
forward<<<dimGrid, dimBlock>>>(d_data + input_pointer, layer_size[layer - 1], d_data + output_pointer, layer_size[layer],
d_param + param_pointer, num_layers - layer - 1);
}
/* Softmax and Predict class */
double *probs;
probs = (double * ) malloc(layer_size[num_layers - 1] * sizeof(double));
probs_pointer = data_ind(num_layers - 1, layer_size);
hipMemcpy(probs, d_data+probs_pointer, layer_size[num_layers - 1]*sizeof(double), hipMemcpyDeviceToHost);
sum = 0.0;
for (i = 0; i < layer_size[num_layers - 1]; i++) {
sum += exp(probs[i]);
}
predicted_class_score = -1.0;
predicted_class = -1;
for (i = 0; i < layer_size[num_layers - 1]; i++) {
/* Compute normalized probability of the correct class */
probs[i] = exp(probs[i])/sum;
/* Argmax */
if (probs[i] > predicted_class_score) {
predicted_class_score = probs[i];
predicted_class = i;
}
}
/* Compute accuracy */
if (predicted_class == label[it]) {
acc++;
}
/* Compute the cross-entropy loss by adding the log probabilities assigned to the correct classes */
global_loss += -log(probs[label[it]]);
if ((it+1) % 1000 == 0) {
printf("Test set size: %d\tloss: %f\taccuracy:%f\n",
it + 1, global_loss / (it + 1), (float) acc / (float) (it + 1));
}
}
hipFree(d_data);
free(images);
}
int main(int argc, char **argv) {
/* local variables */
int epochs, W = 28, H = 28;
const char train_images_filename[] = "./mnist_data/train_images.csv";
const char train_labels_filename[] = "./mnist_data/train_labels.csv";
const char test_images_filename[] = "./mnist_data/test_images.csv";
const char test_labels_filename[] = "./mnist_data/test_labels.csv";
/* Read number of epochs from command line */
if (argc < 2) {
printf("Number of epochs is not given \n");
exit(1);
}
epochs = atoi(argv[1]);
/* Set neural network parameters */
double lambda = 0.0005, learning_rate = 0.01;
int num_layers = 4;
int layer_size[4] = {W*H,300,100,10};
int p_size = param_size(layer_size, num_layers) * sizeof(double);
double *h_param, *d_param;
double *h_grad_param, *d_grad_param;
int *train_label, *test_label;
/* Allocate memory and read training labels */
train_label = (int *) malloc(TRAIN_SET_SIZE * sizeof(int));
read_labels(train_labels_filename, train_label, TRAIN_SET_SIZE);
/* Allocate memory for parameters */
h_param = (double *) malloc(p_size);
h_grad_param = (double *) malloc(p_size);
hipMalloc( (void**)&d_param, p_size);
hipMalloc( (void**)&d_grad_param, p_size);
srandom(1);
/* Initialize parameters using "xavier" initialization */
int layer, i, j;
for (layer = 1; layer < num_layers; layer++) {
double a = sqrt(3.0/(float)layer_size[layer-1]); // uniform interval limit
int param_pointer = param_ind(layer, layer_size);
for (i = 0; i < layer_size[layer]; i++) {
h_param[param_pointer + i] = 0.0; // bias
}
for (j = 1; j < layer_size[layer - 1] +1; j++) {
for (i = 0; i < layer_size[layer]; i++) {
h_param[param_pointer + j * layer_size[layer] + i] = 2.0 * a * (double) random() / RAND_MAX - a;
}
}
}
/* Initialize gradients with 0 */
memset(h_grad_param, 0, p_size);
hipMemcpy( d_param, h_param, p_size, hipMemcpyHostToDevice );
hipMemcpy( d_grad_param, h_grad_param, p_size, hipMemcpyHostToDevice );
/* Train network */
train(train_images_filename, train_label, d_param, d_grad_param, layer_size, num_layers, epochs, lambda, learning_rate);
/* Deallocate arrays */
free(h_grad_param);
hipFree(d_grad_param);
free(train_label);
/* Allocate memory and read testing labels */
test_label = (int *) malloc(TEST_SET_SIZE * sizeof(int));
read_labels(test_labels_filename, test_label, TEST_SET_SIZE);
/* Test network */
test(test_images_filename, test_label, d_param, layer_size, num_layers);
/* Deallocate arrays */
free(h_param);
hipFree(d_param);
free(test_label);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7forwardPdiS_iS_i
.globl _Z7forwardPdiS_iS_i
.p2align 8
.type _Z7forwardPdiS_iS_i,@function
_Z7forwardPdiS_iS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s6, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_ashr_i32 s7, s6, 31
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[6:7], v[1:2]
s_cbranch_execz .LBB0_5
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x20
s_load_b32 s2, s[0:1], 0x8
v_lshlrev_b64 v[5:6], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s8, v5
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v6, vcc_lo
s_cmp_eq_u32 s2, 0
global_load_b64 v[3:4], v[3:4], off
s_cbranch_scc1 .LBB0_4
s_load_b64 s[4:5], s[0:1], 0x0
s_lshl_b64 s[6:7], s[6:7], 3
s_ashr_i32 s3, s2, 31
s_add_u32 s8, s8, s6
s_addc_u32 s9, s9, s7
v_add_co_u32 v5, vcc_lo, s8, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
.LBB0_3:
global_load_b64 v[7:8], v[5:6], off
s_waitcnt lgkmcnt(0)
s_load_b64 s[8:9], s[4:5], 0x0
v_add_co_u32 v5, vcc_lo, v5, s6
s_add_u32 s2, s2, -1
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
s_addc_u32 s3, s3, -1
s_add_u32 s4, s4, 8
s_addc_u32 s5, s5, 0
s_cmp_lg_u64 s[2:3], 0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f64 v[3:4], v[7:8], s[8:9], v[3:4]
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ge_f64_e32 vcc_lo, 0, v[3:4]
s_clause 0x1
s_load_b32 s2, s[0:1], 0x28
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s2, 0
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_b32 s2, s2, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_cndmask_b32_e64 v4, v4, 0, s2
v_cndmask_b32_e64 v3, v3, 0, s2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7forwardPdiS_iS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7forwardPdiS_iS_i, .Lfunc_end0-_Z7forwardPdiS_iS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14backward_part1PdiS_iS_S_id
.globl _Z14backward_part1PdiS_iS_S_id
.p2align 8
.type _Z14backward_part1PdiS_iS_S_id,@function
_Z14backward_part1PdiS_iS_S_id:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x4c
s_load_b32 s6, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_ashr_i32 s7, s6, 31
v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1]
v_mov_b32_e32 v5, 0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[6:7], v[4:5]
s_cbranch_execz .LBB1_4
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x28
v_lshlrev_b64 v[0:1], 3, v[4:5]
s_load_b32 s4, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v6, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v1, vcc_lo
s_cmp_eq_u32 s4, 0
global_load_b64 v[0:1], v[2:3], off
global_load_b64 v[2:3], v[6:7], off
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[0:1], v[2:3]
global_store_b64 v[6:7], v[2:3], off
s_cbranch_scc1 .LBB1_4
s_load_b64 s[8:9], s[0:1], 0x38
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
v_mov_b32_e32 v6, 0
s_ashr_i32 s5, s4, 31
s_lshl_b64 s[6:7], s[6:7], 3
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 3, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], s[8:9], s[8:9]
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x20
.p2align 6
.LBB1_3:
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v5, vcc_lo
v_add_co_u32 v11, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v5, vcc_lo
global_load_b64 v[7:8], v[7:8], off
global_load_b64 v[9:10], v6, s[8:9]
v_add_co_u32 v4, vcc_lo, v4, s6
global_load_b64 v[13:14], v[11:12], off
s_add_u32 s4, s4, -1
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
s_addc_u32 s5, s5, -1
s_add_u32 s8, s8, 8
s_addc_u32 s9, s9, 0
s_cmp_lg_u64 s[4:5], 0
s_waitcnt vmcnt(2)
v_mul_f64 v[7:8], v[2:3], v[7:8]
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], v[0:1], v[9:10], v[7:8]
s_waitcnt vmcnt(0)
v_add_f64 v[7:8], v[13:14], v[7:8]
global_store_b64 v[11:12], v[7:8], off
s_cbranch_scc1 .LBB1_3
.LBB1_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14backward_part1PdiS_iS_S_id
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z14backward_part1PdiS_iS_S_id, .Lfunc_end1-_Z14backward_part1PdiS_iS_S_id
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14backward_part2PdiS_iS_S_id
.globl _Z14backward_part2PdiS_iS_S_id
.p2align 8
.type _Z14backward_part2PdiS_iS_S_id,@function
_Z14backward_part2PdiS_iS_S_id:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x4c
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[4:5], null, s15, s3, v[0:1]
v_mov_b32_e32 v5, 0
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[4:5]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB2_7
s_load_b64 s[2:3], s[0:1], 0x10
v_lshlrev_b64 v[0:1], 3, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[2:3], v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_lt_f64_e32 vcc_lo, 0, v[2:3]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB2_6
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB2_5
s_ashr_i32 s3, s2, 31
s_load_b64 s[6:7], s[0:1], 0x20
v_mad_u64_u32 v[2:3], null, s2, v4, s[2:3]
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, s3, v4, v[3:4]
v_mov_b32_e32 v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 3, v[2:3]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
.LBB2_4:
global_load_b64 v[6:7], v[4:5], off
s_load_b64 s[6:7], s[0:1], 0x0
v_add_co_u32 v4, vcc_lo, v4, 8
s_add_u32 s2, s2, -1
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_addc_u32 s3, s3, -1
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
s_cmp_lg_u64 s[2:3], 0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f64 v[2:3], s[6:7], v[6:7], v[2:3]
s_cbranch_scc1 .LBB2_4
s_branch .LBB2_6
.LBB2_5:
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
.LBB2_6:
s_or_b32 exec_lo, exec_lo, s4
global_store_b64 v[0:1], v[2:3], off
.LBB2_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14backward_part2PdiS_iS_S_id
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z14backward_part2PdiS_iS_S_id, .Lfunc_end2-_Z14backward_part2PdiS_iS_S_id
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12update_paramPdS_idi
.globl _Z12update_paramPdS_idi
.p2align 8
.type _Z12update_paramPdS_idi,@function
_Z12update_paramPdS_idi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB3_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_cvt_f32_i32_e32 v4, s0
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b64 v[2:3], v[2:3], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
v_cvt_f64_f32_e32 v[4:5], v4
global_load_b64 v[10:11], v[0:1], off
s_waitcnt vmcnt(1)
v_mul_f64 v[2:3], v[2:3], s[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], v[2:3]
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[12:13], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
v_fma_f64 v[12:13], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
v_div_scale_f64 v[12:13], vcc_lo, v[2:3], v[4:5], v[2:3]
v_mul_f64 v[14:15], v[12:13], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], -v[6:7], v[14:15], v[12:13]
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[2:3], v[6:7], v[4:5], v[2:3]
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[10:11], -v[2:3]
global_store_b64 v[0:1], v[2:3], off
.LBB3_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12update_paramPdS_idi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z12update_paramPdS_idi, .Lfunc_end3-_Z12update_paramPdS_idi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7forwardPdiS_iS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7forwardPdiS_iS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 56
.size: 8
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14backward_part1PdiS_iS_S_id
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14backward_part1PdiS_iS_S_id.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 56
.size: 8
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14backward_part2PdiS_iS_S_id
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14backward_part2PdiS_iS_S_id.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12update_paramPdS_idi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12update_paramPdS_idi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
extern int HI; // the total number of point patterns
extern int HN; // the total number of points
extern int HK_star; // the total number of covariates
extern int Hd; // the dimensionality of the problem
extern int HV; // the total number of elements in the grid
void read_files(int ** foci , float ** Z , int * foci_counts , int * brain , int* author) {
int i , j; // those are for the for loops
// read the file with the points
FILE *file;
file = fopen("./inputs/foci.txt","r");
for (i=0 ; i<HN ; i++) {
for (j=0 ; j<(Hd+1) ; j++) {
if(!fscanf(file,"%d",&foci[i][j]))
break;
}
}
fclose(file);
// read the design matrix
file = fopen("./inputs/Z.txt","r");
for (i=0 ; i<HI ; i++) {
for (j=0 ; j<HK_star ; j++) {
if(!fscanf(file,"%f",&Z[i][j]))
break;
}
}
fclose(file);
// read the total number of points per pattern
file = fopen("./inputs/counts.txt","r");
for (i=0 ; i<HI ; i++) {
if(!fscanf(file,"%d",&foci_counts[i]))
break;
}
fclose(file);
/* Binary vector indicating which voxels in the grid are within the brain mask */
file = fopen("mask.txt","r");
for (i=0 ; i<HV ; i++) {
if(!fscanf(file,"%d",&brain[i]))
break;
}
fclose(file);
/* Read the publication identifier. Studies from the same paper must appear consecutive */
file = fopen("./inputs/paper.txt","r");
for (i=0 ; i<HI ; i++) {
if(!fscanf(file,"%d",&author[i]))
break;
}
fclose(file);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
extern int HI; // the total number of point patterns
extern int HN; // the total number of points
extern int HK_star; // the total number of covariates
extern int Hd; // the dimensionality of the problem
extern int HV; // the total number of elements in the grid
void read_files(int ** foci , float ** Z , int * foci_counts , int * brain , int* author) {
int i , j; // those are for the for loops
// read the file with the points
FILE *file;
file = fopen("./inputs/foci.txt","r");
for (i=0 ; i<HN ; i++) {
for (j=0 ; j<(Hd+1) ; j++) {
if(!fscanf(file,"%d",&foci[i][j]))
break;
}
}
fclose(file);
// read the design matrix
file = fopen("./inputs/Z.txt","r");
for (i=0 ; i<HI ; i++) {
for (j=0 ; j<HK_star ; j++) {
if(!fscanf(file,"%f",&Z[i][j]))
break;
}
}
fclose(file);
// read the total number of points per pattern
file = fopen("./inputs/counts.txt","r");
for (i=0 ; i<HI ; i++) {
if(!fscanf(file,"%d",&foci_counts[i]))
break;
}
fclose(file);
/* Binary vector indicating which voxels in the grid are within the brain mask */
file = fopen("mask.txt","r");
for (i=0 ; i<HV ; i++) {
if(!fscanf(file,"%d",&brain[i]))
break;
}
fclose(file);
/* Read the publication identifier. Studies from the same paper must appear consecutive */
file = fopen("./inputs/paper.txt","r");
for (i=0 ; i<HI ; i++) {
if(!fscanf(file,"%d",&author[i]))
break;
}
fclose(file);
} | .file "tmpxft_000daf33_00000000-6_read_files.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "./inputs/foci.txt"
.LC2:
.string "%d"
.LC3:
.string "./inputs/Z.txt"
.LC4:
.string "%f"
.LC5:
.string "./inputs/counts.txt"
.LC6:
.string "mask.txt"
.LC7:
.string "./inputs/paper.txt"
.text
.globl _Z10read_filesPPiPPfS_S_S_
.type _Z10read_filesPPiPPfS_S_S_, @function
_Z10read_filesPPiPPfS_S_S_:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbp
movq %rsi, 24(%rsp)
movq %rdx, %r13
movq %rcx, 8(%rsp)
movq %r8, 16(%rsp)
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %r12
cmpl $0, HN(%rip)
jle .L4
movl $0, %r15d
leaq .LC2(%rip), %r14
jmp .L5
.L6:
addl $1, %r15d
addq $8, %rbp
cmpl %r15d, HN(%rip)
jle .L4
.L5:
movl $0, %ebx
cmpl $0, Hd(%rip)
js .L6
.L7:
movq 0(%rbp), %rax
leaq (%rax,%rbx,4), %rdx
movq %r14, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
testl %eax, %eax
je .L6
addq $1, %rbx
cmpl %ebx, Hd(%rip)
jge .L7
jmp .L6
.L4:
movq %r12, %rdi
call fclose@PLT
leaq .LC0(%rip), %rsi
leaq .LC3(%rip), %rdi
call fopen@PLT
movq %rax, %r12
cmpl $0, HI(%rip)
jle .L8
movq 24(%rsp), %rbp
movl $0, %r15d
leaq .LC4(%rip), %r14
jmp .L9
.L10:
addl $1, %r15d
addq $8, %rbp
cmpl %r15d, HI(%rip)
jle .L8
.L9:
movl $0, %ebx
cmpl $0, HK_star(%rip)
jle .L10
.L11:
movq 0(%rbp), %rax
leaq (%rax,%rbx,4), %rdx
movq %r14, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
testl %eax, %eax
je .L10
addq $1, %rbx
cmpl %ebx, HK_star(%rip)
jg .L11
jmp .L10
.L8:
movq %r12, %rdi
call fclose@PLT
leaq .LC0(%rip), %rsi
leaq .LC5(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
cmpl $0, HI(%rip)
jle .L12
movl $0, %ebx
leaq .LC2(%rip), %r12
.L13:
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
testl %eax, %eax
je .L12
addl $1, %ebx
addq $4, %r13
cmpl %ebx, HI(%rip)
jg .L13
.L12:
movq %rbp, %rdi
call fclose@PLT
leaq .LC0(%rip), %rsi
leaq .LC6(%rip), %rdi
call fopen@PLT
movq %rax, %r12
cmpl $0, HV(%rip)
jle .L14
movq 8(%rsp), %rbx
movl $0, %ebp
leaq .LC2(%rip), %r13
.L15:
movq %rbx, %rdx
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
testl %eax, %eax
je .L14
addl $1, %ebp
addq $4, %rbx
cmpl %ebp, HV(%rip)
jg .L15
.L14:
movq %r12, %rdi
call fclose@PLT
leaq .LC0(%rip), %rsi
leaq .LC7(%rip), %rdi
call fopen@PLT
movq %rax, %r12
cmpl $0, HI(%rip)
jle .L16
movq 16(%rsp), %rbx
movl $0, %ebp
leaq .LC2(%rip), %r13
.L17:
movq %rbx, %rdx
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
testl %eax, %eax
je .L16
addl $1, %ebp
addq $4, %rbx
cmpl %ebp, HI(%rip)
jg .L17
.L16:
movq %r12, %rdi
call fclose@PLT
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z10read_filesPPiPPfS_S_S_, .-_Z10read_filesPPiPPfS_S_S_
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
extern int HI; // the total number of point patterns
extern int HN; // the total number of points
extern int HK_star; // the total number of covariates
extern int Hd; // the dimensionality of the problem
extern int HV; // the total number of elements in the grid
void read_files(int ** foci , float ** Z , int * foci_counts , int * brain , int* author) {
int i , j; // those are for the for loops
// read the file with the points
FILE *file;
file = fopen("./inputs/foci.txt","r");
for (i=0 ; i<HN ; i++) {
for (j=0 ; j<(Hd+1) ; j++) {
if(!fscanf(file,"%d",&foci[i][j]))
break;
}
}
fclose(file);
// read the design matrix
file = fopen("./inputs/Z.txt","r");
for (i=0 ; i<HI ; i++) {
for (j=0 ; j<HK_star ; j++) {
if(!fscanf(file,"%f",&Z[i][j]))
break;
}
}
fclose(file);
// read the total number of points per pattern
file = fopen("./inputs/counts.txt","r");
for (i=0 ; i<HI ; i++) {
if(!fscanf(file,"%d",&foci_counts[i]))
break;
}
fclose(file);
/* Binary vector indicating which voxels in the grid are within the brain mask */
file = fopen("mask.txt","r");
for (i=0 ; i<HV ; i++) {
if(!fscanf(file,"%d",&brain[i]))
break;
}
fclose(file);
/* Read the publication identifier. Studies from the same paper must appear consecutive */
file = fopen("./inputs/paper.txt","r");
for (i=0 ; i<HI ; i++) {
if(!fscanf(file,"%d",&author[i]))
break;
}
fclose(file);
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
extern int HI; // the total number of point patterns
extern int HN; // the total number of points
extern int HK_star; // the total number of covariates
extern int Hd; // the dimensionality of the problem
extern int HV; // the total number of elements in the grid
void read_files(int ** foci , float ** Z , int * foci_counts , int * brain , int* author) {
int i , j; // those are for the for loops
// read the file with the points
FILE *file;
file = fopen("./inputs/foci.txt","r");
for (i=0 ; i<HN ; i++) {
for (j=0 ; j<(Hd+1) ; j++) {
if(!fscanf(file,"%d",&foci[i][j]))
break;
}
}
fclose(file);
// read the design matrix
file = fopen("./inputs/Z.txt","r");
for (i=0 ; i<HI ; i++) {
for (j=0 ; j<HK_star ; j++) {
if(!fscanf(file,"%f",&Z[i][j]))
break;
}
}
fclose(file);
// read the total number of points per pattern
file = fopen("./inputs/counts.txt","r");
for (i=0 ; i<HI ; i++) {
if(!fscanf(file,"%d",&foci_counts[i]))
break;
}
fclose(file);
/* Binary vector indicating which voxels in the grid are within the brain mask */
file = fopen("mask.txt","r");
for (i=0 ; i<HV ; i++) {
if(!fscanf(file,"%d",&brain[i]))
break;
}
fclose(file);
/* Read the publication identifier. Studies from the same paper must appear consecutive */
file = fopen("./inputs/paper.txt","r");
for (i=0 ; i<HI ; i++) {
if(!fscanf(file,"%d",&author[i]))
break;
}
fclose(file);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
extern int HI; // the total number of point patterns
extern int HN; // the total number of points
extern int HK_star; // the total number of covariates
extern int Hd; // the dimensionality of the problem
extern int HV; // the total number of elements in the grid
void read_files(int ** foci , float ** Z , int * foci_counts , int * brain , int* author) {
int i , j; // those are for the for loops
// read the file with the points
FILE *file;
file = fopen("./inputs/foci.txt","r");
for (i=0 ; i<HN ; i++) {
for (j=0 ; j<(Hd+1) ; j++) {
if(!fscanf(file,"%d",&foci[i][j]))
break;
}
}
fclose(file);
// read the design matrix
file = fopen("./inputs/Z.txt","r");
for (i=0 ; i<HI ; i++) {
for (j=0 ; j<HK_star ; j++) {
if(!fscanf(file,"%f",&Z[i][j]))
break;
}
}
fclose(file);
// read the total number of points per pattern
file = fopen("./inputs/counts.txt","r");
for (i=0 ; i<HI ; i++) {
if(!fscanf(file,"%d",&foci_counts[i]))
break;
}
fclose(file);
/* Binary vector indicating which voxels in the grid are within the brain mask */
file = fopen("mask.txt","r");
for (i=0 ; i<HV ; i++) {
if(!fscanf(file,"%d",&brain[i]))
break;
}
fclose(file);
/* Read the publication identifier. Studies from the same paper must appear consecutive */
file = fopen("./inputs/paper.txt","r");
for (i=0 ; i<HI ; i++) {
if(!fscanf(file,"%d",&author[i]))
break;
}
fclose(file);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
extern int HI; // the total number of point patterns
extern int HN; // the total number of points
extern int HK_star; // the total number of covariates
extern int Hd; // the dimensionality of the problem
extern int HV; // the total number of elements in the grid
void read_files(int ** foci , float ** Z , int * foci_counts , int * brain , int* author) {
int i , j; // those are for the for loops
// read the file with the points
FILE *file;
file = fopen("./inputs/foci.txt","r");
for (i=0 ; i<HN ; i++) {
for (j=0 ; j<(Hd+1) ; j++) {
if(!fscanf(file,"%d",&foci[i][j]))
break;
}
}
fclose(file);
// read the design matrix
file = fopen("./inputs/Z.txt","r");
for (i=0 ; i<HI ; i++) {
for (j=0 ; j<HK_star ; j++) {
if(!fscanf(file,"%f",&Z[i][j]))
break;
}
}
fclose(file);
// read the total number of points per pattern
file = fopen("./inputs/counts.txt","r");
for (i=0 ; i<HI ; i++) {
if(!fscanf(file,"%d",&foci_counts[i]))
break;
}
fclose(file);
/* Binary vector indicating which voxels in the grid are within the brain mask */
file = fopen("mask.txt","r");
for (i=0 ; i<HV ; i++) {
if(!fscanf(file,"%d",&brain[i]))
break;
}
fclose(file);
/* Read the publication identifier. Studies from the same paper must appear consecutive */
file = fopen("./inputs/paper.txt","r");
for (i=0 ; i<HI ; i++) {
if(!fscanf(file,"%d",&author[i]))
break;
}
fclose(file);
} | .text
.file "read_files.hip"
.globl _Z10read_filesPPiPPfS_S_S_ # -- Begin function _Z10read_filesPPiPPfS_S_S_
.p2align 4, 0x90
.type _Z10read_filesPPiPPfS_S_S_,@function
_Z10read_filesPPiPPfS_S_S_: # @_Z10read_filesPPiPPfS_S_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, 16(%rsp) # 8-byte Spill
movq %rcx, 8(%rsp) # 8-byte Spill
movq %rdx, (%rsp) # 8-byte Spill
movq %rsi, %r12
movq %rdi, %r13
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbp
cmpl $0, HN(%rip)
jle .LBB0_7
# %bb.1: # %.preheader42.preheader
xorl %ebx, %ebx
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_6: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
incq %rbx
movslq HN(%rip), %rax
cmpq %rax, %rbx
jge .LBB0_7
.LBB0_2: # %.preheader42
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
cmpl $0, Hd(%rip)
js .LBB0_6
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB0_2 Depth=1
xorl %r14d, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_4: # %.lr.ph
# Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movq (%r13,%rbx,8), %rdx
addq %r14, %rdx
movl $.L.str.2, %esi
movq %rbp, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
testl %eax, %eax
je .LBB0_6
# %bb.5: # %.lr.ph
# in Loop: Header=BB0_4 Depth=2
leaq 1(%r15), %rax
addq $4, %r14
movslq Hd(%rip), %rcx
cmpq %rcx, %r15
movq %rax, %r15
jl .LBB0_4
jmp .LBB0_6
.LBB0_7: # %._crit_edge47
movq %rbp, %rdi
callq fclose
movl $.L.str.3, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r13
cmpl $0, HI(%rip)
jle .LBB0_14
# %bb.8: # %.preheader.preheader
xorl %ebp, %ebp
jmp .LBB0_9
.p2align 4, 0x90
.LBB0_13: # %._crit_edge50
# in Loop: Header=BB0_9 Depth=1
incq %rbp
movslq HI(%rip), %rax
cmpq %rax, %rbp
jge .LBB0_14
.LBB0_9: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_11 Depth 2
cmpl $0, HK_star(%rip)
jle .LBB0_13
# %bb.10: # %.lr.ph49.preheader
# in Loop: Header=BB0_9 Depth=1
movl $1, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_11: # %.lr.ph49
# Parent Loop BB0_9 Depth=1
# => This Inner Loop Header: Depth=2
movq (%r12,%rbp,8), %rdx
addq %r14, %rdx
movl $.L.str.4, %esi
movq %r13, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
testl %eax, %eax
je .LBB0_13
# %bb.12: # %.lr.ph49
# in Loop: Header=BB0_11 Depth=2
addq $4, %r14
leaq 1(%rbx), %rax
movslq HK_star(%rip), %rcx
cmpq %rcx, %rbx
movq %rax, %rbx
jl .LBB0_11
jmp .LBB0_13
.LBB0_14: # %._crit_edge53
movq %r13, %rdi
callq fclose
movl $.L.str.5, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r12
cmpl $0, HI(%rip)
movq (%rsp), %r14 # 8-byte Reload
jle .LBB0_18
# %bb.15: # %.lr.ph56.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_17: # %.lr.ph56
# =>This Inner Loop Header: Depth=1
movl $.L.str.2, %esi
movq %r12, %rdi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
testl %eax, %eax
je .LBB0_18
# %bb.16: # in Loop: Header=BB0_17 Depth=1
incq %rbx
movslq HI(%rip), %rax
addq $4, %r14
cmpq %rax, %rbx
jl .LBB0_17
.LBB0_18: # %._crit_edge57
movq %r12, %rdi
callq fclose
movl $.L.str.6, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r15
cmpl $0, HV(%rip)
movq 8(%rsp), %r14 # 8-byte Reload
jle .LBB0_22
# %bb.19: # %.lr.ph61.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_21: # %.lr.ph61
# =>This Inner Loop Header: Depth=1
movl $.L.str.2, %esi
movq %r15, %rdi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
testl %eax, %eax
je .LBB0_22
# %bb.20: # in Loop: Header=BB0_21 Depth=1
incq %rbx
movslq HV(%rip), %rax
addq $4, %r14
cmpq %rax, %rbx
jl .LBB0_21
.LBB0_22: # %._crit_edge62
movq %r15, %rdi
callq fclose
movl $.L.str.7, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r14
cmpl $0, HI(%rip)
movq 16(%rsp), %r15 # 8-byte Reload
jle .LBB0_26
# %bb.23: # %.lr.ph66.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_25: # %.lr.ph66
# =>This Inner Loop Header: Depth=1
movl $.L.str.2, %esi
movq %r14, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
testl %eax, %eax
je .LBB0_26
# %bb.24: # in Loop: Header=BB0_25 Depth=1
incq %rbx
movslq HI(%rip), %rax
addq $4, %r15
cmpq %rax, %rbx
jl .LBB0_25
.LBB0_26: # %._crit_edge67
movq %r14, %rdi
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end0:
.size _Z10read_filesPPiPPfS_S_S_, .Lfunc_end0-_Z10read_filesPPiPPfS_S_S_
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "./inputs/foci.txt"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "./inputs/Z.txt"
.size .L.str.3, 15
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%f"
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "./inputs/counts.txt"
.size .L.str.5, 20
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "mask.txt"
.size .L.str.6, 9
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "./inputs/paper.txt"
.size .L.str.7, 19
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000daf33_00000000-6_read_files.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "./inputs/foci.txt"
.LC2:
.string "%d"
.LC3:
.string "./inputs/Z.txt"
.LC4:
.string "%f"
.LC5:
.string "./inputs/counts.txt"
.LC6:
.string "mask.txt"
.LC7:
.string "./inputs/paper.txt"
.text
.globl _Z10read_filesPPiPPfS_S_S_
.type _Z10read_filesPPiPPfS_S_S_, @function
_Z10read_filesPPiPPfS_S_S_:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbp
movq %rsi, 24(%rsp)
movq %rdx, %r13
movq %rcx, 8(%rsp)
movq %r8, 16(%rsp)
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %r12
cmpl $0, HN(%rip)
jle .L4
movl $0, %r15d
leaq .LC2(%rip), %r14
jmp .L5
.L6:
addl $1, %r15d
addq $8, %rbp
cmpl %r15d, HN(%rip)
jle .L4
.L5:
movl $0, %ebx
cmpl $0, Hd(%rip)
js .L6
.L7:
movq 0(%rbp), %rax
leaq (%rax,%rbx,4), %rdx
movq %r14, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
testl %eax, %eax
je .L6
addq $1, %rbx
cmpl %ebx, Hd(%rip)
jge .L7
jmp .L6
.L4:
movq %r12, %rdi
call fclose@PLT
leaq .LC0(%rip), %rsi
leaq .LC3(%rip), %rdi
call fopen@PLT
movq %rax, %r12
cmpl $0, HI(%rip)
jle .L8
movq 24(%rsp), %rbp
movl $0, %r15d
leaq .LC4(%rip), %r14
jmp .L9
.L10:
addl $1, %r15d
addq $8, %rbp
cmpl %r15d, HI(%rip)
jle .L8
.L9:
movl $0, %ebx
cmpl $0, HK_star(%rip)
jle .L10
.L11:
movq 0(%rbp), %rax
leaq (%rax,%rbx,4), %rdx
movq %r14, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
testl %eax, %eax
je .L10
addq $1, %rbx
cmpl %ebx, HK_star(%rip)
jg .L11
jmp .L10
.L8:
movq %r12, %rdi
call fclose@PLT
leaq .LC0(%rip), %rsi
leaq .LC5(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
cmpl $0, HI(%rip)
jle .L12
movl $0, %ebx
leaq .LC2(%rip), %r12
.L13:
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
testl %eax, %eax
je .L12
addl $1, %ebx
addq $4, %r13
cmpl %ebx, HI(%rip)
jg .L13
.L12:
movq %rbp, %rdi
call fclose@PLT
leaq .LC0(%rip), %rsi
leaq .LC6(%rip), %rdi
call fopen@PLT
movq %rax, %r12
cmpl $0, HV(%rip)
jle .L14
movq 8(%rsp), %rbx
movl $0, %ebp
leaq .LC2(%rip), %r13
.L15:
movq %rbx, %rdx
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
testl %eax, %eax
je .L14
addl $1, %ebp
addq $4, %rbx
cmpl %ebp, HV(%rip)
jg .L15
.L14:
movq %r12, %rdi
call fclose@PLT
leaq .LC0(%rip), %rsi
leaq .LC7(%rip), %rdi
call fopen@PLT
movq %rax, %r12
cmpl $0, HI(%rip)
jle .L16
movq 16(%rsp), %rbx
movl $0, %ebp
leaq .LC2(%rip), %r13
.L17:
movq %rbx, %rdx
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
testl %eax, %eax
je .L16
addl $1, %ebp
addq $4, %rbx
cmpl %ebp, HI(%rip)
jg .L17
.L16:
movq %r12, %rdi
call fclose@PLT
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z10read_filesPPiPPfS_S_S_, .-_Z10read_filesPPiPPfS_S_S_
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "read_files.hip"
.globl _Z10read_filesPPiPPfS_S_S_ # -- Begin function _Z10read_filesPPiPPfS_S_S_
.p2align 4, 0x90
.type _Z10read_filesPPiPPfS_S_S_,@function
_Z10read_filesPPiPPfS_S_S_: # @_Z10read_filesPPiPPfS_S_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, 16(%rsp) # 8-byte Spill
movq %rcx, 8(%rsp) # 8-byte Spill
movq %rdx, (%rsp) # 8-byte Spill
movq %rsi, %r12
movq %rdi, %r13
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbp
cmpl $0, HN(%rip)
jle .LBB0_7
# %bb.1: # %.preheader42.preheader
xorl %ebx, %ebx
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_6: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
incq %rbx
movslq HN(%rip), %rax
cmpq %rax, %rbx
jge .LBB0_7
.LBB0_2: # %.preheader42
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
cmpl $0, Hd(%rip)
js .LBB0_6
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB0_2 Depth=1
xorl %r14d, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_4: # %.lr.ph
# Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movq (%r13,%rbx,8), %rdx
addq %r14, %rdx
movl $.L.str.2, %esi
movq %rbp, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
testl %eax, %eax
je .LBB0_6
# %bb.5: # %.lr.ph
# in Loop: Header=BB0_4 Depth=2
leaq 1(%r15), %rax
addq $4, %r14
movslq Hd(%rip), %rcx
cmpq %rcx, %r15
movq %rax, %r15
jl .LBB0_4
jmp .LBB0_6
.LBB0_7: # %._crit_edge47
movq %rbp, %rdi
callq fclose
movl $.L.str.3, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r13
cmpl $0, HI(%rip)
jle .LBB0_14
# %bb.8: # %.preheader.preheader
xorl %ebp, %ebp
jmp .LBB0_9
.p2align 4, 0x90
.LBB0_13: # %._crit_edge50
# in Loop: Header=BB0_9 Depth=1
incq %rbp
movslq HI(%rip), %rax
cmpq %rax, %rbp
jge .LBB0_14
.LBB0_9: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_11 Depth 2
cmpl $0, HK_star(%rip)
jle .LBB0_13
# %bb.10: # %.lr.ph49.preheader
# in Loop: Header=BB0_9 Depth=1
movl $1, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_11: # %.lr.ph49
# Parent Loop BB0_9 Depth=1
# => This Inner Loop Header: Depth=2
movq (%r12,%rbp,8), %rdx
addq %r14, %rdx
movl $.L.str.4, %esi
movq %r13, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
testl %eax, %eax
je .LBB0_13
# %bb.12: # %.lr.ph49
# in Loop: Header=BB0_11 Depth=2
addq $4, %r14
leaq 1(%rbx), %rax
movslq HK_star(%rip), %rcx
cmpq %rcx, %rbx
movq %rax, %rbx
jl .LBB0_11
jmp .LBB0_13
.LBB0_14: # %._crit_edge53
movq %r13, %rdi
callq fclose
movl $.L.str.5, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r12
cmpl $0, HI(%rip)
movq (%rsp), %r14 # 8-byte Reload
jle .LBB0_18
# %bb.15: # %.lr.ph56.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_17: # %.lr.ph56
# =>This Inner Loop Header: Depth=1
movl $.L.str.2, %esi
movq %r12, %rdi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
testl %eax, %eax
je .LBB0_18
# %bb.16: # in Loop: Header=BB0_17 Depth=1
incq %rbx
movslq HI(%rip), %rax
addq $4, %r14
cmpq %rax, %rbx
jl .LBB0_17
.LBB0_18: # %._crit_edge57
movq %r12, %rdi
callq fclose
movl $.L.str.6, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r15
cmpl $0, HV(%rip)
movq 8(%rsp), %r14 # 8-byte Reload
jle .LBB0_22
# %bb.19: # %.lr.ph61.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_21: # %.lr.ph61
# =>This Inner Loop Header: Depth=1
movl $.L.str.2, %esi
movq %r15, %rdi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
testl %eax, %eax
je .LBB0_22
# %bb.20: # in Loop: Header=BB0_21 Depth=1
incq %rbx
movslq HV(%rip), %rax
addq $4, %r14
cmpq %rax, %rbx
jl .LBB0_21
.LBB0_22: # %._crit_edge62
movq %r15, %rdi
callq fclose
movl $.L.str.7, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r14
cmpl $0, HI(%rip)
movq 16(%rsp), %r15 # 8-byte Reload
jle .LBB0_26
# %bb.23: # %.lr.ph66.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_25: # %.lr.ph66
# =>This Inner Loop Header: Depth=1
movl $.L.str.2, %esi
movq %r14, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
testl %eax, %eax
je .LBB0_26
# %bb.24: # in Loop: Header=BB0_25 Depth=1
incq %rbx
movslq HI(%rip), %rax
addq $4, %r15
cmpq %rax, %rbx
jl .LBB0_25
.LBB0_26: # %._crit_edge67
movq %r14, %rdi
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end0:
.size _Z10read_filesPPiPPfS_S_S_, .Lfunc_end0-_Z10read_filesPPiPPfS_S_S_
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "./inputs/foci.txt"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "./inputs/Z.txt"
.size .L.str.3, 15
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%f"
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "./inputs/counts.txt"
.size .L.str.5, 20
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "mask.txt"
.size .L.str.6, 9
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "./inputs/paper.txt"
.size .L.str.7, 19
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define MAX_SIZE 1024
#define GET_TIME(now){ \
struct timeval t; \
gettimeofday(&t, NULL); \
now = t.tv_sec * 1000 + t.tv_usec / 1000.0; \
}
int arr[MAX_SIZE * MAX_SIZE];
int brr[MAX_SIZE * MAX_SIZE];
int crr[MAX_SIZE * MAX_SIZE];
__global__ void mp(int *a, int *b, int *c)
{
int i, sum;
int id_0, id_1, id_2;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
sum = 0;
for(i = 0; i < MAX_SIZE; i++){
id_0 = row * MAX_SIZE + i;
id_1 = i * MAX_SIZE + col;
sum += a[id_0] * b[id_1];
}
id_2 = row * MAX_SIZE + col;
c[id_2] = sum;
}
int main(void) {
int *d_a, *d_b, *d_c;
int block_size;
int size = sizeof(int) * MAX_SIZE * MAX_SIZE;
int i, j;
double start_time, end_time;
FILE *fp = fopen("matrix.txt","r");
printf("Input the Block Size: ");
scanf("%d",&block_size);
for(i = 0; i < MAX_SIZE; i++){
for(j = 0; j < MAX_SIZE; j++){
fscanf(fp,"%d",&arr[i * MAX_SIZE + j]);
}
}
for(i = 0; i < MAX_SIZE; i++){
for(j = 0; j < MAX_SIZE; j++){
fscanf(fp,"%d",&brr[i * MAX_SIZE + j]);
}
}
fclose(fp);
cudaMalloc((void **)&d_a, size);
cudaMalloc((void **)&d_b, size);
cudaMalloc((void **)&d_c, size);
cudaMemcpy(d_a, arr, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, brr, size, cudaMemcpyHostToDevice);
GET_TIME(start_time);
dim3 dimBlock (block_size, block_size);
dim3 dimGrid(MAX_SIZE / dimBlock.x, MAX_SIZE/dimBlock.y);
mp<<<dimGrid, dimBlock>>>(d_a, d_b, d_c);
GET_TIME(end_time);
cudaMemcpy(crr, d_c, size, cudaMemcpyDeviceToHost);
fp = fopen("matrix_cu.txt","w");
for(i = 0; i < MAX_SIZE; i++){
for(j = 0; j < MAX_SIZE; j++){
fprintf(fp,"%d ",crr[i * MAX_SIZE + j]);
}
fprintf(fp,"\n");
}
fclose(fp);
printf("Matrix Mulitplication Cuda VER: Elapsed time is %e (msec)\n",end_time - start_time);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | code for sm_80
Function : _Z2mpPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e220000002600 */
/*0020*/ HFMA2.MMA R12, -RZ, RZ, 0, 0 ; /* 0x00000000ff0c7435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002200 */
/*0060*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fe20000000f00 */
/*0090*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*00a0*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*00b0*/ IMAD R9, R9, c[0x0][0x4], R2 ; /* 0x0000010009097a24 */
/* 0x001fca00078e0202 */
/*00c0*/ SHF.L.U32 R9, R9, 0xa, RZ ; /* 0x0000000a09097819 */
/* 0x000fe200000006ff */
/*00d0*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fc600078e0203 */
/*00e0*/ IADD3 R11, R9, 0x1, RZ ; /* 0x00000001090b7810 */
/* 0x000fe40007ffe0ff */
/*00f0*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*0100*/ IMAD.WIDE R14, R9, 0x4, R4 ; /* 0x00000004090e7825 */
/* 0x000fe200078e0204 */
/*0110*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fc60008000f00 */
/*0120*/ IMAD.WIDE R2, R11, 0x4, R4 ; /* 0x000000040b027825 */
/* 0x000fe400078e0204 */
/*0130*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000a4000c1e1900 */
/*0140*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x000fe400078e0206 */
/*0150*/ LDG.E R24, [R2.64] ; /* 0x0000000402187981 */
/* 0x000ee8000c1e1900 */
/*0160*/ LDG.E R17, [R6.64] ; /* 0x0000000406117981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R27, [R6.64+0x1000] ; /* 0x00100004061b7981 */
/* 0x000ee8000c1e1900 */
/*0180*/ LDG.E R16, [R2.64+0x4] ; /* 0x0000040402107981 */
/* 0x000f28000c1e1900 */
/*0190*/ LDG.E R19, [R6.64+0x2000] ; /* 0x0020000406137981 */
/* 0x000f28000c1e1900 */
/*01a0*/ LDG.E R23, [R2.64+0x8] ; /* 0x0000080402177981 */
/* 0x000f68000c1e1900 */
/*01b0*/ LDG.E R20, [R6.64+0x3000] ; /* 0x0030000406147981 */
/* 0x000f68000c1e1900 */
/*01c0*/ LDG.E R22, [R2.64+0xc] ; /* 0x00000c0402167981 */
/* 0x000f68000c1e1900 */
/*01d0*/ LDG.E R25, [R6.64+0x4000] ; /* 0x0040000406197981 */
/* 0x000f68000c1e1900 */
/*01e0*/ LDG.E R18, [R2.64+0x10] ; /* 0x0000100402127981 */
/* 0x000f68000c1e1900 */
/*01f0*/ LDG.E R21, [R6.64+0x5000] ; /* 0x0050000406157981 */
/* 0x000f68000c1e1900 */
/*0200*/ LDG.E R10, [R2.64+0x14] ; /* 0x00001404020a7981 */
/* 0x000f68000c1e1900 */
/*0210*/ LDG.E R13, [R6.64+0x6000] ; /* 0x00600004060d7981 */
/* 0x000f68000c1e1900 */
/*0220*/ LDG.E R15, [R6.64+0x7000] ; /* 0x00700004060f7981 */
/* 0x001f68000c1e1900 */
/*0230*/ LDG.E R26, [R6.64+0xf000] ; /* 0x00f00004061a7981 */
/* 0x000f68000c1e1900 */
/*0240*/ LDG.E R29, [R2.64+0x38] ; /* 0x00003804021d7981 */
/* 0x000f62000c1e1900 */
/*0250*/ IMAD R14, R17, R14, R12 ; /* 0x0000000e110e7224 */
/* 0x004fc600078e020c */
/*0260*/ LDG.E R12, [R2.64+0x18] ; /* 0x00001804020c7981 */
/* 0x000ea2000c1e1900 */
/*0270*/ IMAD R24, R27, R24, R14 ; /* 0x000000181b187224 */
/* 0x008fc600078e020e */
/*0280*/ LDG.E R14, [R2.64+0x1c] ; /* 0x00001c04020e7981 */
/* 0x000ee8000c1e1900 */
/*0290*/ LDG.E R17, [R6.64+0x8000] ; /* 0x0080000406117981 */
/* 0x000ee2000c1e1900 */
/*02a0*/ IMAD R24, R19, R16, R24 ; /* 0x0000001013187224 */
/* 0x010fc600078e0218 */
/*02b0*/ LDG.E R16, [R2.64+0x20] ; /* 0x0000200402107981 */
/* 0x000f28000c1e1900 */
/*02c0*/ LDG.E R19, [R6.64+0x9000] ; /* 0x0090000406137981 */
/* 0x000f22000c1e1900 */
/*02d0*/ IMAD R24, R20, R23, R24 ; /* 0x0000001714187224 */
/* 0x020fc600078e0218 */
/*02e0*/ LDG.E R23, [R2.64+0x24] ; /* 0x0000240402177981 */
/* 0x000f68000c1e1900 */
/*02f0*/ LDG.E R20, [R6.64+0xa000] ; /* 0x00a0000406147981 */
/* 0x000f62000c1e1900 */
/*0300*/ IMAD R24, R25, R22, R24 ; /* 0x0000001619187224 */
/* 0x000fc600078e0218 */
/*0310*/ LDG.E R25, [R2.64+0x28] ; /* 0x0000280402197981 */
/* 0x000f68000c1e1900 */
/*0320*/ LDG.E R22, [R6.64+0xb000] ; /* 0x00b0000406167981 */
/* 0x000f62000c1e1900 */
/*0330*/ IMAD R24, R21, R18, R24 ; /* 0x0000001215187224 */
/* 0x000fc600078e0218 */
/*0340*/ LDG.E R21, [R2.64+0x2c] ; /* 0x00002c0402157981 */
/* 0x000f68000c1e1900 */
/*0350*/ LDG.E R18, [R6.64+0xc000] ; /* 0x00c0000406127981 */
/* 0x000f62000c1e1900 */
/*0360*/ IMAD R28, R13, R10, R24 ; /* 0x0000000a0d1c7224 */
/* 0x000fc600078e0218 */
/*0370*/ LDG.E R24, [R2.64+0x30] ; /* 0x0000300402187981 */
/* 0x000f68000c1e1900 */
/*0380*/ LDG.E R13, [R6.64+0xd000] ; /* 0x00d00004060d7981 */
/* 0x000f68000c1e1900 */
/*0390*/ LDG.E R10, [R6.64+0xe000] ; /* 0x00e00004060a7981 */
/* 0x000f68000c1e1900 */
/*03a0*/ LDG.E R27, [R2.64+0x34] ; /* 0x00003404021b7981 */
/* 0x000f62000c1e1900 */
/*03b0*/ IADD3 R8, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x000fc80007ffe0ff */
/*03c0*/ ISETP.NE.AND P0, PT, R8, 0x400, PT ; /* 0x000004000800780c */
/* 0x000fe20003f05270 */
/*03d0*/ UIADD3 UR6, UP0, UR6, 0x10000, URZ ; /* 0x0001000006067890 */
/* 0x000fe2000ff1e03f */
/*03e0*/ IADD3 R4, P1, R4, 0x40, RZ ; /* 0x0000004004047810 */
/* 0x000fc60007f3e0ff */
/*03f0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0400*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x000fe20000ffe4ff */
/*0410*/ IMAD R12, R15, R12, R28 ; /* 0x0000000c0f0c7224 */
/* 0x004fc800078e021c */
/*0420*/ IMAD R12, R17, R14, R12 ; /* 0x0000000e110c7224 */
/* 0x008fc800078e020c */
/*0430*/ IMAD R12, R19, R16, R12 ; /* 0x00000010130c7224 */
/* 0x010fc800078e020c */
/*0440*/ IMAD R12, R20, R23, R12 ; /* 0x00000017140c7224 */
/* 0x020fc800078e020c */
/*0450*/ IMAD R12, R22, R25, R12 ; /* 0x00000019160c7224 */
/* 0x000fc800078e020c */
/*0460*/ IMAD R12, R18, R21, R12 ; /* 0x00000015120c7224 */
/* 0x000fc800078e020c */
/*0470*/ IMAD R12, R13, R24, R12 ; /* 0x000000180d0c7224 */
/* 0x000fc800078e020c */
/*0480*/ IMAD R12, R10, R27, R12 ; /* 0x0000001b0a0c7224 */
/* 0x000fc800078e020c */
/*0490*/ IMAD R12, R26, R29, R12 ; /* 0x0000001d1a0c7224 */
/* 0x000fe200078e020c */
/*04a0*/ @P0 BRA 0xf0 ; /* 0xfffffc4000000947 */
/* 0x000fea000383ffff */
/*04b0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*04c0*/ IADD3 R2, R0, R9, RZ ; /* 0x0000000900027210 */
/* 0x000fd20007ffe0ff */
/*04d0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*04e0*/ STG.E [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x000fe2000c101904 */
/*04f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0500*/ BRA 0x500; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define MAX_SIZE 1024
#define GET_TIME(now){ \
struct timeval t; \
gettimeofday(&t, NULL); \
now = t.tv_sec * 1000 + t.tv_usec / 1000.0; \
}
int arr[MAX_SIZE * MAX_SIZE];
int brr[MAX_SIZE * MAX_SIZE];
int crr[MAX_SIZE * MAX_SIZE];
__global__ void mp(int *a, int *b, int *c)
{
int i, sum;
int id_0, id_1, id_2;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
sum = 0;
for(i = 0; i < MAX_SIZE; i++){
id_0 = row * MAX_SIZE + i;
id_1 = i * MAX_SIZE + col;
sum += a[id_0] * b[id_1];
}
id_2 = row * MAX_SIZE + col;
c[id_2] = sum;
}
int main(void) {
int *d_a, *d_b, *d_c;
int block_size;
int size = sizeof(int) * MAX_SIZE * MAX_SIZE;
int i, j;
double start_time, end_time;
FILE *fp = fopen("matrix.txt","r");
printf("Input the Block Size: ");
scanf("%d",&block_size);
for(i = 0; i < MAX_SIZE; i++){
for(j = 0; j < MAX_SIZE; j++){
fscanf(fp,"%d",&arr[i * MAX_SIZE + j]);
}
}
for(i = 0; i < MAX_SIZE; i++){
for(j = 0; j < MAX_SIZE; j++){
fscanf(fp,"%d",&brr[i * MAX_SIZE + j]);
}
}
fclose(fp);
cudaMalloc((void **)&d_a, size);
cudaMalloc((void **)&d_b, size);
cudaMalloc((void **)&d_c, size);
cudaMemcpy(d_a, arr, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, brr, size, cudaMemcpyHostToDevice);
GET_TIME(start_time);
dim3 dimBlock (block_size, block_size);
dim3 dimGrid(MAX_SIZE / dimBlock.x, MAX_SIZE/dimBlock.y);
mp<<<dimGrid, dimBlock>>>(d_a, d_b, d_c);
GET_TIME(end_time);
cudaMemcpy(crr, d_c, size, cudaMemcpyDeviceToHost);
fp = fopen("matrix_cu.txt","w");
for(i = 0; i < MAX_SIZE; i++){
for(j = 0; j < MAX_SIZE; j++){
fprintf(fp,"%d ",crr[i * MAX_SIZE + j]);
}
fprintf(fp,"\n");
}
fclose(fp);
printf("Matrix Mulitplication Cuda VER: Elapsed time is %e (msec)\n",end_time - start_time);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | .file "tmpxft_00125d87_00000000-6_mp_cu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z2mpPiS_S_PiS_S_
.type _Z25__device_stub__Z2mpPiS_S_PiS_S_, @function
_Z25__device_stub__Z2mpPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z2mpPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z25__device_stub__Z2mpPiS_S_PiS_S_, .-_Z25__device_stub__Z2mpPiS_S_PiS_S_
.globl _Z2mpPiS_S_
.type _Z2mpPiS_S_, @function
_Z2mpPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z2mpPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z2mpPiS_S_, .-_Z2mpPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "matrix.txt"
.LC2:
.string "Input the Block Size: "
.LC3:
.string "%d"
.LC5:
.string "w"
.LC6:
.string "matrix_cu.txt"
.LC7:
.string "%d "
.LC8:
.string "\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC9:
.string "Matrix Mulitplication Cuda VER: Elapsed time is %e (msec)\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 28(%rsp), %rsi
leaq .LC3(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq 4096+arr(%rip), %r12
leaq 4194304(%r12), %r14
leaq .LC3(%rip), %r13
.L12:
leaq -4096(%r12), %rbx
.L13:
movq %rbx, %rdx
movq %r13, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L13
addq $4096, %r12
cmpq %r14, %r12
jne .L12
leaq 4096+brr(%rip), %r12
leaq 4194304(%r12), %r14
leaq .LC3(%rip), %r13
.L14:
leaq -4096(%r12), %rbx
.L15:
movq %rbx, %rdx
movq %r13, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L15
addq $4096, %r12
cmpq %r14, %r12
jne .L14
movq %rbp, %rdi
call fclose@PLT
leaq 32(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4194304, %edx
leaq arr(%rip), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
leaq brr(%rip), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
imulq $1000, 80(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
pxor %xmm0, %xmm0
cvtsi2sdq 88(%rsp), %xmm0
divsd .LC4(%rip), %xmm0
addsd %xmm0, %xmm1
movsd %xmm1, (%rsp)
movl 28(%rsp), %ecx
movl $1024, %eax
movl $0, %edx
divl %ecx
movl %eax, 68(%rsp)
movl %eax, 72(%rsp)
movl %ecx, 56(%rsp)
movl %ecx, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movl $1, %ecx
movq 68(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L17:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
imulq $1000, 80(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
pxor %xmm0, %xmm0
cvtsi2sdq 88(%rsp), %xmm0
divsd .LC4(%rip), %xmm0
addsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp)
movl $2, %ecx
movl $4194304, %edx
movq 48(%rsp), %rsi
leaq crr(%rip), %rdi
call cudaMemcpy@PLT
leaq .LC5(%rip), %rsi
leaq .LC6(%rip), %rdi
call fopen@PLT
movq %rax, %r12
leaq 4096+crr(%rip), %rbp
leaq 4194304(%rbp), %r15
leaq .LC7(%rip), %r13
leaq .LC8(%rip), %r14
.L18:
leaq -4096(%rbp), %rbx
.L19:
movl (%rbx), %ecx
movq %r13, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L19
movq %r14, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $4096, %rbp
cmpq %r15, %rbp
jne .L18
movq %r12, %rdi
call fclose@PLT
movsd 8(%rsp), %xmm0
subsd (%rsp), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z25__device_stub__Z2mpPiS_S_PiS_S_
jmp .L17
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z2mpPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z2mpPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl crr
.bss
.align 32
.type crr, @object
.size crr, 4194304
crr:
.zero 4194304
.globl brr
.align 32
.type brr, @object
.size brr, 4194304
brr:
.zero 4194304
.globl arr
.align 32
.type arr, @object
.size arr, 4194304
arr:
.zero 4194304
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define MAX_SIZE 1024
#define GET_TIME(now){ \
struct timeval t; \
gettimeofday(&t, NULL); \
now = t.tv_sec * 1000 + t.tv_usec / 1000.0; \
}
int arr[MAX_SIZE * MAX_SIZE];
int brr[MAX_SIZE * MAX_SIZE];
int crr[MAX_SIZE * MAX_SIZE];
__global__ void mp(int *a, int *b, int *c)
{
int i, sum;
int id_0, id_1, id_2;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
sum = 0;
for(i = 0; i < MAX_SIZE; i++){
id_0 = row * MAX_SIZE + i;
id_1 = i * MAX_SIZE + col;
sum += a[id_0] * b[id_1];
}
id_2 = row * MAX_SIZE + col;
c[id_2] = sum;
}
int main(void) {
int *d_a, *d_b, *d_c;
int block_size;
int size = sizeof(int) * MAX_SIZE * MAX_SIZE;
int i, j;
double start_time, end_time;
FILE *fp = fopen("matrix.txt","r");
printf("Input the Block Size: ");
scanf("%d",&block_size);
for(i = 0; i < MAX_SIZE; i++){
for(j = 0; j < MAX_SIZE; j++){
fscanf(fp,"%d",&arr[i * MAX_SIZE + j]);
}
}
for(i = 0; i < MAX_SIZE; i++){
for(j = 0; j < MAX_SIZE; j++){
fscanf(fp,"%d",&brr[i * MAX_SIZE + j]);
}
}
fclose(fp);
cudaMalloc((void **)&d_a, size);
cudaMalloc((void **)&d_b, size);
cudaMalloc((void **)&d_c, size);
cudaMemcpy(d_a, arr, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, brr, size, cudaMemcpyHostToDevice);
GET_TIME(start_time);
dim3 dimBlock (block_size, block_size);
dim3 dimGrid(MAX_SIZE / dimBlock.x, MAX_SIZE/dimBlock.y);
mp<<<dimGrid, dimBlock>>>(d_a, d_b, d_c);
GET_TIME(end_time);
cudaMemcpy(crr, d_c, size, cudaMemcpyDeviceToHost);
fp = fopen("matrix_cu.txt","w");
for(i = 0; i < MAX_SIZE; i++){
for(j = 0; j < MAX_SIZE; j++){
fprintf(fp,"%d ",crr[i * MAX_SIZE + j]);
}
fprintf(fp,"\n");
}
fclose(fp);
printf("Matrix Mulitplication Cuda VER: Elapsed time is %e (msec)\n",end_time - start_time);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define MAX_SIZE 1024
#define GET_TIME(now){ \
struct timeval t; \
gettimeofday(&t, NULL); \
now = t.tv_sec * 1000 + t.tv_usec / 1000.0; \
}
int arr[MAX_SIZE * MAX_SIZE];
int brr[MAX_SIZE * MAX_SIZE];
int crr[MAX_SIZE * MAX_SIZE];
__global__ void mp(int *a, int *b, int *c)
{
int i, sum;
int id_0, id_1, id_2;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
sum = 0;
for(i = 0; i < MAX_SIZE; i++){
id_0 = row * MAX_SIZE + i;
id_1 = i * MAX_SIZE + col;
sum += a[id_0] * b[id_1];
}
id_2 = row * MAX_SIZE + col;
c[id_2] = sum;
}
int main(void) {
int *d_a, *d_b, *d_c;
int block_size;
int size = sizeof(int) * MAX_SIZE * MAX_SIZE;
int i, j;
double start_time, end_time;
FILE *fp = fopen("matrix.txt","r");
printf("Input the Block Size: ");
scanf("%d",&block_size);
for(i = 0; i < MAX_SIZE; i++){
for(j = 0; j < MAX_SIZE; j++){
fscanf(fp,"%d",&arr[i * MAX_SIZE + j]);
}
}
for(i = 0; i < MAX_SIZE; i++){
for(j = 0; j < MAX_SIZE; j++){
fscanf(fp,"%d",&brr[i * MAX_SIZE + j]);
}
}
fclose(fp);
hipMalloc((void **)&d_a, size);
hipMalloc((void **)&d_b, size);
hipMalloc((void **)&d_c, size);
hipMemcpy(d_a, arr, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, brr, size, hipMemcpyHostToDevice);
GET_TIME(start_time);
dim3 dimBlock (block_size, block_size);
dim3 dimGrid(MAX_SIZE / dimBlock.x, MAX_SIZE/dimBlock.y);
mp<<<dimGrid, dimBlock>>>(d_a, d_b, d_c);
GET_TIME(end_time);
hipMemcpy(crr, d_c, size, hipMemcpyDeviceToHost);
fp = fopen("matrix_cu.txt","w");
for(i = 0; i < MAX_SIZE; i++){
for(j = 0; j < MAX_SIZE; j++){
fprintf(fp,"%d ",crr[i * MAX_SIZE + j]);
}
fprintf(fp,"\n");
}
fclose(fp);
printf("Matrix Mulitplication Cuda VER: Elapsed time is %e (msec)\n",end_time - start_time);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define MAX_SIZE 1024
#define GET_TIME(now){ \
struct timeval t; \
gettimeofday(&t, NULL); \
now = t.tv_sec * 1000 + t.tv_usec / 1000.0; \
}
int arr[MAX_SIZE * MAX_SIZE];
int brr[MAX_SIZE * MAX_SIZE];
int crr[MAX_SIZE * MAX_SIZE];
__global__ void mp(int *a, int *b, int *c)
{
int i, sum;
int id_0, id_1, id_2;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
sum = 0;
for(i = 0; i < MAX_SIZE; i++){
id_0 = row * MAX_SIZE + i;
id_1 = i * MAX_SIZE + col;
sum += a[id_0] * b[id_1];
}
id_2 = row * MAX_SIZE + col;
c[id_2] = sum;
}
int main(void) {
int *d_a, *d_b, *d_c;
int block_size;
int size = sizeof(int) * MAX_SIZE * MAX_SIZE;
int i, j;
double start_time, end_time;
FILE *fp = fopen("matrix.txt","r");
printf("Input the Block Size: ");
scanf("%d",&block_size);
for(i = 0; i < MAX_SIZE; i++){
for(j = 0; j < MAX_SIZE; j++){
fscanf(fp,"%d",&arr[i * MAX_SIZE + j]);
}
}
for(i = 0; i < MAX_SIZE; i++){
for(j = 0; j < MAX_SIZE; j++){
fscanf(fp,"%d",&brr[i * MAX_SIZE + j]);
}
}
fclose(fp);
hipMalloc((void **)&d_a, size);
hipMalloc((void **)&d_b, size);
hipMalloc((void **)&d_c, size);
hipMemcpy(d_a, arr, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, brr, size, hipMemcpyHostToDevice);
GET_TIME(start_time);
dim3 dimBlock (block_size, block_size);
dim3 dimGrid(MAX_SIZE / dimBlock.x, MAX_SIZE/dimBlock.y);
mp<<<dimGrid, dimBlock>>>(d_a, d_b, d_c);
GET_TIME(end_time);
hipMemcpy(crr, d_c, size, hipMemcpyDeviceToHost);
fp = fopen("matrix_cu.txt","w");
for(i = 0; i < MAX_SIZE; i++){
for(j = 0; j < MAX_SIZE; j++){
fprintf(fp,"%d ",crr[i * MAX_SIZE + j]);
}
fprintf(fp,"\n");
}
fclose(fp);
printf("Matrix Mulitplication Cuda VER: Elapsed time is %e (msec)\n",end_time - start_time);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z2mpPiS_S_
.globl _Z2mpPiS_S_
.p2align 8
.type _Z2mpPiS_S_,@function
_Z2mpPiS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v2, 10, v1
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_mad_u64_u32 v[2:3], null, s14, s2, v[0:1]
v_mov_b32_e32 v0, 0
s_mov_b64 s[2:3], 0
v_add_co_u32 v6, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v5, vcc_lo
v_mov_b32_e32 v3, v2
.p2align 6
.LBB0_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v4, 31, v3
v_add_co_u32 v8, vcc_lo, v6, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v7, vcc_lo
v_lshlrev_b64 v[4:5], 2, v[3:4]
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmpk_lg_i32 s2, 0x1000
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
global_load_b32 v8, v[8:9], off
global_load_b32 v9, v[4:5], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[4:5], null, v9, v8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v0, v4 :: v_dual_add_nc_u32 v3, 0x400, v3
s_cbranch_scc1 .LBB0_1
s_load_b64 s[0:1], s[0:1], 0x10
v_lshl_add_u32 v0, v1, 10, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z2mpPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z2mpPiS_S_, .Lfunc_end0-_Z2mpPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z2mpPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z2mpPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define MAX_SIZE 1024
#define GET_TIME(now){ \
struct timeval t; \
gettimeofday(&t, NULL); \
now = t.tv_sec * 1000 + t.tv_usec / 1000.0; \
}
int arr[MAX_SIZE * MAX_SIZE];
int brr[MAX_SIZE * MAX_SIZE];
int crr[MAX_SIZE * MAX_SIZE];
__global__ void mp(int *a, int *b, int *c)
{
int i, sum;
int id_0, id_1, id_2;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
sum = 0;
for(i = 0; i < MAX_SIZE; i++){
id_0 = row * MAX_SIZE + i;
id_1 = i * MAX_SIZE + col;
sum += a[id_0] * b[id_1];
}
id_2 = row * MAX_SIZE + col;
c[id_2] = sum;
}
int main(void) {
int *d_a, *d_b, *d_c;
int block_size;
int size = sizeof(int) * MAX_SIZE * MAX_SIZE;
int i, j;
double start_time, end_time;
FILE *fp = fopen("matrix.txt","r");
printf("Input the Block Size: ");
scanf("%d",&block_size);
for(i = 0; i < MAX_SIZE; i++){
for(j = 0; j < MAX_SIZE; j++){
fscanf(fp,"%d",&arr[i * MAX_SIZE + j]);
}
}
for(i = 0; i < MAX_SIZE; i++){
for(j = 0; j < MAX_SIZE; j++){
fscanf(fp,"%d",&brr[i * MAX_SIZE + j]);
}
}
fclose(fp);
hipMalloc((void **)&d_a, size);
hipMalloc((void **)&d_b, size);
hipMalloc((void **)&d_c, size);
hipMemcpy(d_a, arr, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, brr, size, hipMemcpyHostToDevice);
GET_TIME(start_time);
dim3 dimBlock (block_size, block_size);
dim3 dimGrid(MAX_SIZE / dimBlock.x, MAX_SIZE/dimBlock.y);
mp<<<dimGrid, dimBlock>>>(d_a, d_b, d_c);
GET_TIME(end_time);
hipMemcpy(crr, d_c, size, hipMemcpyDeviceToHost);
fp = fopen("matrix_cu.txt","w");
for(i = 0; i < MAX_SIZE; i++){
for(j = 0; j < MAX_SIZE; j++){
fprintf(fp,"%d ",crr[i * MAX_SIZE + j]);
}
fprintf(fp,"\n");
}
fclose(fp);
printf("Matrix Mulitplication Cuda VER: Elapsed time is %e (msec)\n",end_time - start_time);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.file "mp_cu.hip"
.globl _Z17__device_stub__mpPiS_S_ # -- Begin function _Z17__device_stub__mpPiS_S_
.p2align 4, 0x90
.type _Z17__device_stub__mpPiS_S_,@function
_Z17__device_stub__mpPiS_S_: # @_Z17__device_stub__mpPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z2mpPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z17__device_stub__mpPiS_S_, .Lfunc_end0-_Z17__device_stub__mpPiS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbx
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
leaq 44(%rsp), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $arr, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_1: # %.preheader44
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
leaq (%r14,%r12), %rdx
movl $.L.str.3, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %r12
cmpq $4096, %r12 # imm = 0x1000
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %r15
addq $4096, %r14 # imm = 0x1000
cmpq $1024, %r15 # imm = 0x400
jne .LBB1_1
# %bb.4: # %.preheader42.preheader
movl $brr, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_5: # %.preheader42
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
leaq (%r14,%r12), %rdx
movl $.L.str.3, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %r12
cmpq $4096, %r12 # imm = 0x1000
jne .LBB1_6
# %bb.7: # in Loop: Header=BB1_5 Depth=1
incq %r15
addq $4096, %r14 # imm = 0x1000
cmpq $1024, %r15 # imm = 0x400
jne .LBB1_5
# %bb.8:
movq %rbx, %rdi
callq fclose
leaq 32(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq 32(%rsp), %rdi
movl $arr, %esi
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $brr, %esi
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpy
leaq 48(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 48(%rsp), %rax
movq %rax, 72(%rsp) # 8-byte Spill
movq 56(%rsp), %rax
movq %rax, 8(%rsp) # 8-byte Spill
movl 44(%rsp), %esi
movq %rsi, %rcx
shlq $32, %rcx
orq %rsi, %rcx
movl $1024, %eax # imm = 0x400
xorl %edx, %edx
divl %esi
# kill: def $eax killed $eax def $rax
movq %rax, %rdi
shlq $32, %rdi
orq %rax, %rdi
movl $1, %esi
movq %rcx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
leaq 144(%rsp), %rax
movq %rax, 48(%rsp)
leaq 136(%rsp), %rax
movq %rax, 56(%rsp)
leaq 128(%rsp), %rax
movq %rax, 64(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z2mpPiS_S_, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_10:
leaq 48(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 48(%rsp), %r13
movq 56(%rsp), %r12
movq 16(%rsp), %rsi
movl $crr, %ebp
movl $crr, %edi
movl $4194304, %edx # imm = 0x400000
movl $2, %ecx
callq hipMemcpy
movl $.L.str.4, %edi
movl $.L.str.5, %esi
callq fopen
movq %rax, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_11: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_12 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_12: # Parent Loop BB1_11 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbp,%r15,4), %edx
movl $.L.str.6, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq fprintf
incq %r15
cmpq $1024, %r15 # imm = 0x400
jne .LBB1_12
# %bb.13: # in Loop: Header=BB1_11 Depth=1
movl $10, %edi
movq %rbx, %rsi
callq fputc@PLT
incq %r14
addq $4096, %rbp # imm = 0x1000
cmpq $1024, %r14 # imm = 0x400
jne .LBB1_11
# %bb.14:
imulq $1000, %r13, %rax # imm = 0x3E8
cvtsi2sd %rax, %xmm0
cvtsi2sd %r12, %xmm4
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm4
imulq $1000, 72(%rsp), %rax # 8-byte Folded Reload
# imm = 0x3E8
cvtsi2sd %rax, %xmm2
cvtsi2sdq 8(%rsp), %xmm3 # 8-byte Folded Reload
addsd %xmm0, %xmm4
divsd %xmm1, %xmm3
addsd %xmm2, %xmm3
subsd %xmm3, %xmm4
movsd %xmm4, 8(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq fclose
movl $.L.str.8, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2mpPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type arr,@object # @arr
.bss
.globl arr
.p2align 4, 0x0
arr:
.zero 4194304
.size arr, 4194304
.type brr,@object # @brr
.globl brr
.p2align 4, 0x0
brr:
.zero 4194304
.size brr, 4194304
.type crr,@object # @crr
.globl crr
.p2align 4, 0x0
crr:
.zero 4194304
.size crr, 4194304
.type _Z2mpPiS_S_,@object # @_Z2mpPiS_S_
.section .rodata,"a",@progbits
.globl _Z2mpPiS_S_
.p2align 3, 0x0
_Z2mpPiS_S_:
.quad _Z17__device_stub__mpPiS_S_
.size _Z2mpPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "matrix.txt"
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Input the Block Size: "
.size .L.str.2, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "matrix_cu.txt"
.size .L.str.4, 14
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "w"
.size .L.str.5, 2
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d "
.size .L.str.6, 4
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Matrix Mulitplication Cuda VER: Elapsed time is %e (msec)\n"
.size .L.str.8, 59
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z2mpPiS_S_"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z17__device_stub__mpPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym arr
.addrsig_sym brr
.addrsig_sym crr
.addrsig_sym _Z2mpPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z2mpPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e220000002600 */
/*0020*/ HFMA2.MMA R12, -RZ, RZ, 0, 0 ; /* 0x00000000ff0c7435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002200 */
/*0060*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fe20000000f00 */
/*0090*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*00a0*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*00b0*/ IMAD R9, R9, c[0x0][0x4], R2 ; /* 0x0000010009097a24 */
/* 0x001fca00078e0202 */
/*00c0*/ SHF.L.U32 R9, R9, 0xa, RZ ; /* 0x0000000a09097819 */
/* 0x000fe200000006ff */
/*00d0*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fc600078e0203 */
/*00e0*/ IADD3 R11, R9, 0x1, RZ ; /* 0x00000001090b7810 */
/* 0x000fe40007ffe0ff */
/*00f0*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*0100*/ IMAD.WIDE R14, R9, 0x4, R4 ; /* 0x00000004090e7825 */
/* 0x000fe200078e0204 */
/*0110*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fc60008000f00 */
/*0120*/ IMAD.WIDE R2, R11, 0x4, R4 ; /* 0x000000040b027825 */
/* 0x000fe400078e0204 */
/*0130*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000a4000c1e1900 */
/*0140*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x000fe400078e0206 */
/*0150*/ LDG.E R24, [R2.64] ; /* 0x0000000402187981 */
/* 0x000ee8000c1e1900 */
/*0160*/ LDG.E R17, [R6.64] ; /* 0x0000000406117981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R27, [R6.64+0x1000] ; /* 0x00100004061b7981 */
/* 0x000ee8000c1e1900 */
/*0180*/ LDG.E R16, [R2.64+0x4] ; /* 0x0000040402107981 */
/* 0x000f28000c1e1900 */
/*0190*/ LDG.E R19, [R6.64+0x2000] ; /* 0x0020000406137981 */
/* 0x000f28000c1e1900 */
/*01a0*/ LDG.E R23, [R2.64+0x8] ; /* 0x0000080402177981 */
/* 0x000f68000c1e1900 */
/*01b0*/ LDG.E R20, [R6.64+0x3000] ; /* 0x0030000406147981 */
/* 0x000f68000c1e1900 */
/*01c0*/ LDG.E R22, [R2.64+0xc] ; /* 0x00000c0402167981 */
/* 0x000f68000c1e1900 */
/*01d0*/ LDG.E R25, [R6.64+0x4000] ; /* 0x0040000406197981 */
/* 0x000f68000c1e1900 */
/*01e0*/ LDG.E R18, [R2.64+0x10] ; /* 0x0000100402127981 */
/* 0x000f68000c1e1900 */
/*01f0*/ LDG.E R21, [R6.64+0x5000] ; /* 0x0050000406157981 */
/* 0x000f68000c1e1900 */
/*0200*/ LDG.E R10, [R2.64+0x14] ; /* 0x00001404020a7981 */
/* 0x000f68000c1e1900 */
/*0210*/ LDG.E R13, [R6.64+0x6000] ; /* 0x00600004060d7981 */
/* 0x000f68000c1e1900 */
/*0220*/ LDG.E R15, [R6.64+0x7000] ; /* 0x00700004060f7981 */
/* 0x001f68000c1e1900 */
/*0230*/ LDG.E R26, [R6.64+0xf000] ; /* 0x00f00004061a7981 */
/* 0x000f68000c1e1900 */
/*0240*/ LDG.E R29, [R2.64+0x38] ; /* 0x00003804021d7981 */
/* 0x000f62000c1e1900 */
/*0250*/ IMAD R14, R17, R14, R12 ; /* 0x0000000e110e7224 */
/* 0x004fc600078e020c */
/*0260*/ LDG.E R12, [R2.64+0x18] ; /* 0x00001804020c7981 */
/* 0x000ea2000c1e1900 */
/*0270*/ IMAD R24, R27, R24, R14 ; /* 0x000000181b187224 */
/* 0x008fc600078e020e */
/*0280*/ LDG.E R14, [R2.64+0x1c] ; /* 0x00001c04020e7981 */
/* 0x000ee8000c1e1900 */
/*0290*/ LDG.E R17, [R6.64+0x8000] ; /* 0x0080000406117981 */
/* 0x000ee2000c1e1900 */
/*02a0*/ IMAD R24, R19, R16, R24 ; /* 0x0000001013187224 */
/* 0x010fc600078e0218 */
/*02b0*/ LDG.E R16, [R2.64+0x20] ; /* 0x0000200402107981 */
/* 0x000f28000c1e1900 */
/*02c0*/ LDG.E R19, [R6.64+0x9000] ; /* 0x0090000406137981 */
/* 0x000f22000c1e1900 */
/*02d0*/ IMAD R24, R20, R23, R24 ; /* 0x0000001714187224 */
/* 0x020fc600078e0218 */
/*02e0*/ LDG.E R23, [R2.64+0x24] ; /* 0x0000240402177981 */
/* 0x000f68000c1e1900 */
/*02f0*/ LDG.E R20, [R6.64+0xa000] ; /* 0x00a0000406147981 */
/* 0x000f62000c1e1900 */
/*0300*/ IMAD R24, R25, R22, R24 ; /* 0x0000001619187224 */
/* 0x000fc600078e0218 */
/*0310*/ LDG.E R25, [R2.64+0x28] ; /* 0x0000280402197981 */
/* 0x000f68000c1e1900 */
/*0320*/ LDG.E R22, [R6.64+0xb000] ; /* 0x00b0000406167981 */
/* 0x000f62000c1e1900 */
/*0330*/ IMAD R24, R21, R18, R24 ; /* 0x0000001215187224 */
/* 0x000fc600078e0218 */
/*0340*/ LDG.E R21, [R2.64+0x2c] ; /* 0x00002c0402157981 */
/* 0x000f68000c1e1900 */
/*0350*/ LDG.E R18, [R6.64+0xc000] ; /* 0x00c0000406127981 */
/* 0x000f62000c1e1900 */
/*0360*/ IMAD R28, R13, R10, R24 ; /* 0x0000000a0d1c7224 */
/* 0x000fc600078e0218 */
/*0370*/ LDG.E R24, [R2.64+0x30] ; /* 0x0000300402187981 */
/* 0x000f68000c1e1900 */
/*0380*/ LDG.E R13, [R6.64+0xd000] ; /* 0x00d00004060d7981 */
/* 0x000f68000c1e1900 */
/*0390*/ LDG.E R10, [R6.64+0xe000] ; /* 0x00e00004060a7981 */
/* 0x000f68000c1e1900 */
/*03a0*/ LDG.E R27, [R2.64+0x34] ; /* 0x00003404021b7981 */
/* 0x000f62000c1e1900 */
/*03b0*/ IADD3 R8, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x000fc80007ffe0ff */
/*03c0*/ ISETP.NE.AND P0, PT, R8, 0x400, PT ; /* 0x000004000800780c */
/* 0x000fe20003f05270 */
/*03d0*/ UIADD3 UR6, UP0, UR6, 0x10000, URZ ; /* 0x0001000006067890 */
/* 0x000fe2000ff1e03f */
/*03e0*/ IADD3 R4, P1, R4, 0x40, RZ ; /* 0x0000004004047810 */
/* 0x000fc60007f3e0ff */
/*03f0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0400*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x000fe20000ffe4ff */
/*0410*/ IMAD R12, R15, R12, R28 ; /* 0x0000000c0f0c7224 */
/* 0x004fc800078e021c */
/*0420*/ IMAD R12, R17, R14, R12 ; /* 0x0000000e110c7224 */
/* 0x008fc800078e020c */
/*0430*/ IMAD R12, R19, R16, R12 ; /* 0x00000010130c7224 */
/* 0x010fc800078e020c */
/*0440*/ IMAD R12, R20, R23, R12 ; /* 0x00000017140c7224 */
/* 0x020fc800078e020c */
/*0450*/ IMAD R12, R22, R25, R12 ; /* 0x00000019160c7224 */
/* 0x000fc800078e020c */
/*0460*/ IMAD R12, R18, R21, R12 ; /* 0x00000015120c7224 */
/* 0x000fc800078e020c */
/*0470*/ IMAD R12, R13, R24, R12 ; /* 0x000000180d0c7224 */
/* 0x000fc800078e020c */
/*0480*/ IMAD R12, R10, R27, R12 ; /* 0x0000001b0a0c7224 */
/* 0x000fc800078e020c */
/*0490*/ IMAD R12, R26, R29, R12 ; /* 0x0000001d1a0c7224 */
/* 0x000fe200078e020c */
/*04a0*/ @P0 BRA 0xf0 ; /* 0xfffffc4000000947 */
/* 0x000fea000383ffff */
/*04b0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*04c0*/ IADD3 R2, R0, R9, RZ ; /* 0x0000000900027210 */
/* 0x000fd20007ffe0ff */
/*04d0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*04e0*/ STG.E [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x000fe2000c101904 */
/*04f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0500*/ BRA 0x500; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z2mpPiS_S_
.globl _Z2mpPiS_S_
.p2align 8
.type _Z2mpPiS_S_,@function
_Z2mpPiS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v2, 10, v1
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_mad_u64_u32 v[2:3], null, s14, s2, v[0:1]
v_mov_b32_e32 v0, 0
s_mov_b64 s[2:3], 0
v_add_co_u32 v6, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v5, vcc_lo
v_mov_b32_e32 v3, v2
.p2align 6
.LBB0_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v4, 31, v3
v_add_co_u32 v8, vcc_lo, v6, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v7, vcc_lo
v_lshlrev_b64 v[4:5], 2, v[3:4]
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmpk_lg_i32 s2, 0x1000
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
global_load_b32 v8, v[8:9], off
global_load_b32 v9, v[4:5], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[4:5], null, v9, v8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v0, v4 :: v_dual_add_nc_u32 v3, 0x400, v3
s_cbranch_scc1 .LBB0_1
s_load_b64 s[0:1], s[0:1], 0x10
v_lshl_add_u32 v0, v1, 10, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z2mpPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z2mpPiS_S_, .Lfunc_end0-_Z2mpPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z2mpPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z2mpPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00125d87_00000000-6_mp_cu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z2mpPiS_S_PiS_S_
.type _Z25__device_stub__Z2mpPiS_S_PiS_S_, @function
_Z25__device_stub__Z2mpPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z2mpPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z25__device_stub__Z2mpPiS_S_PiS_S_, .-_Z25__device_stub__Z2mpPiS_S_PiS_S_
.globl _Z2mpPiS_S_
.type _Z2mpPiS_S_, @function
_Z2mpPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z2mpPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z2mpPiS_S_, .-_Z2mpPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "matrix.txt"
.LC2:
.string "Input the Block Size: "
.LC3:
.string "%d"
.LC5:
.string "w"
.LC6:
.string "matrix_cu.txt"
.LC7:
.string "%d "
.LC8:
.string "\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC9:
.string "Matrix Mulitplication Cuda VER: Elapsed time is %e (msec)\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 28(%rsp), %rsi
leaq .LC3(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq 4096+arr(%rip), %r12
leaq 4194304(%r12), %r14
leaq .LC3(%rip), %r13
.L12:
leaq -4096(%r12), %rbx
.L13:
movq %rbx, %rdx
movq %r13, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L13
addq $4096, %r12
cmpq %r14, %r12
jne .L12
leaq 4096+brr(%rip), %r12
leaq 4194304(%r12), %r14
leaq .LC3(%rip), %r13
.L14:
leaq -4096(%r12), %rbx
.L15:
movq %rbx, %rdx
movq %r13, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L15
addq $4096, %r12
cmpq %r14, %r12
jne .L14
movq %rbp, %rdi
call fclose@PLT
leaq 32(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4194304, %edx
leaq arr(%rip), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
leaq brr(%rip), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
imulq $1000, 80(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
pxor %xmm0, %xmm0
cvtsi2sdq 88(%rsp), %xmm0
divsd .LC4(%rip), %xmm0
addsd %xmm0, %xmm1
movsd %xmm1, (%rsp)
movl 28(%rsp), %ecx
movl $1024, %eax
movl $0, %edx
divl %ecx
movl %eax, 68(%rsp)
movl %eax, 72(%rsp)
movl %ecx, 56(%rsp)
movl %ecx, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movl $1, %ecx
movq 68(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L17:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
imulq $1000, 80(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
pxor %xmm0, %xmm0
cvtsi2sdq 88(%rsp), %xmm0
divsd .LC4(%rip), %xmm0
addsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp)
movl $2, %ecx
movl $4194304, %edx
movq 48(%rsp), %rsi
leaq crr(%rip), %rdi
call cudaMemcpy@PLT
leaq .LC5(%rip), %rsi
leaq .LC6(%rip), %rdi
call fopen@PLT
movq %rax, %r12
leaq 4096+crr(%rip), %rbp
leaq 4194304(%rbp), %r15
leaq .LC7(%rip), %r13
leaq .LC8(%rip), %r14
.L18:
leaq -4096(%rbp), %rbx
.L19:
movl (%rbx), %ecx
movq %r13, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L19
movq %r14, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $4096, %rbp
cmpq %r15, %rbp
jne .L18
movq %r12, %rdi
call fclose@PLT
movsd 8(%rsp), %xmm0
subsd (%rsp), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z25__device_stub__Z2mpPiS_S_PiS_S_
jmp .L17
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z2mpPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z2mpPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl crr
.bss
.align 32
.type crr, @object
.size crr, 4194304
crr:
.zero 4194304
.globl brr
.align 32
.type brr, @object
.size brr, 4194304
brr:
.zero 4194304
.globl arr
.align 32
.type arr, @object
.size arr, 4194304
arr:
.zero 4194304
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mp_cu.hip"
.globl _Z17__device_stub__mpPiS_S_ # -- Begin function _Z17__device_stub__mpPiS_S_
.p2align 4, 0x90
.type _Z17__device_stub__mpPiS_S_,@function
_Z17__device_stub__mpPiS_S_: # @_Z17__device_stub__mpPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z2mpPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z17__device_stub__mpPiS_S_, .Lfunc_end0-_Z17__device_stub__mpPiS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbx
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
leaq 44(%rsp), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $arr, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_1: # %.preheader44
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
leaq (%r14,%r12), %rdx
movl $.L.str.3, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %r12
cmpq $4096, %r12 # imm = 0x1000
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %r15
addq $4096, %r14 # imm = 0x1000
cmpq $1024, %r15 # imm = 0x400
jne .LBB1_1
# %bb.4: # %.preheader42.preheader
movl $brr, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_5: # %.preheader42
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
leaq (%r14,%r12), %rdx
movl $.L.str.3, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %r12
cmpq $4096, %r12 # imm = 0x1000
jne .LBB1_6
# %bb.7: # in Loop: Header=BB1_5 Depth=1
incq %r15
addq $4096, %r14 # imm = 0x1000
cmpq $1024, %r15 # imm = 0x400
jne .LBB1_5
# %bb.8:
movq %rbx, %rdi
callq fclose
leaq 32(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq 32(%rsp), %rdi
movl $arr, %esi
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $brr, %esi
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpy
leaq 48(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 48(%rsp), %rax
movq %rax, 72(%rsp) # 8-byte Spill
movq 56(%rsp), %rax
movq %rax, 8(%rsp) # 8-byte Spill
movl 44(%rsp), %esi
movq %rsi, %rcx
shlq $32, %rcx
orq %rsi, %rcx
movl $1024, %eax # imm = 0x400
xorl %edx, %edx
divl %esi
# kill: def $eax killed $eax def $rax
movq %rax, %rdi
shlq $32, %rdi
orq %rax, %rdi
movl $1, %esi
movq %rcx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
leaq 144(%rsp), %rax
movq %rax, 48(%rsp)
leaq 136(%rsp), %rax
movq %rax, 56(%rsp)
leaq 128(%rsp), %rax
movq %rax, 64(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z2mpPiS_S_, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_10:
leaq 48(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 48(%rsp), %r13
movq 56(%rsp), %r12
movq 16(%rsp), %rsi
movl $crr, %ebp
movl $crr, %edi
movl $4194304, %edx # imm = 0x400000
movl $2, %ecx
callq hipMemcpy
movl $.L.str.4, %edi
movl $.L.str.5, %esi
callq fopen
movq %rax, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_11: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_12 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_12: # Parent Loop BB1_11 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbp,%r15,4), %edx
movl $.L.str.6, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq fprintf
incq %r15
cmpq $1024, %r15 # imm = 0x400
jne .LBB1_12
# %bb.13: # in Loop: Header=BB1_11 Depth=1
movl $10, %edi
movq %rbx, %rsi
callq fputc@PLT
incq %r14
addq $4096, %rbp # imm = 0x1000
cmpq $1024, %r14 # imm = 0x400
jne .LBB1_11
# %bb.14:
imulq $1000, %r13, %rax # imm = 0x3E8
cvtsi2sd %rax, %xmm0
cvtsi2sd %r12, %xmm4
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm4
imulq $1000, 72(%rsp), %rax # 8-byte Folded Reload
# imm = 0x3E8
cvtsi2sd %rax, %xmm2
cvtsi2sdq 8(%rsp), %xmm3 # 8-byte Folded Reload
addsd %xmm0, %xmm4
divsd %xmm1, %xmm3
addsd %xmm2, %xmm3
subsd %xmm3, %xmm4
movsd %xmm4, 8(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq fclose
movl $.L.str.8, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2mpPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type arr,@object # @arr
.bss
.globl arr
.p2align 4, 0x0
arr:
.zero 4194304
.size arr, 4194304
.type brr,@object # @brr
.globl brr
.p2align 4, 0x0
brr:
.zero 4194304
.size brr, 4194304
.type crr,@object # @crr
.globl crr
.p2align 4, 0x0
crr:
.zero 4194304
.size crr, 4194304
.type _Z2mpPiS_S_,@object # @_Z2mpPiS_S_
.section .rodata,"a",@progbits
.globl _Z2mpPiS_S_
.p2align 3, 0x0
_Z2mpPiS_S_:
.quad _Z17__device_stub__mpPiS_S_
.size _Z2mpPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "matrix.txt"
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Input the Block Size: "
.size .L.str.2, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "matrix_cu.txt"
.size .L.str.4, 14
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "w"
.size .L.str.5, 2
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d "
.size .L.str.6, 4
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Matrix Mulitplication Cuda VER: Elapsed time is %e (msec)\n"
.size .L.str.8, 59
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z2mpPiS_S_"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z17__device_stub__mpPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym arr
.addrsig_sym brr
.addrsig_sym crr
.addrsig_sym _Z2mpPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
__global__
void calc_meanshift2(float* y_new, float* y_old, float* meanshift)
{
int i = blockDim.x*blockIdx.x + threadIdx.x;
float tempY_new = y_new[i];
float tempY_old = y_old[i];
meanshift[i] = (tempY_new-tempY_old)*(tempY_new-tempY_old);
}
__device__
float kernel_fun(float x, float sigma2)
{
if( x > sigma2)
return 0;
else
return exp(-x/2/sigma2);
}
__global__
void calc_Kernel_Matrix(int N, int D, float *x, float *y, float *K, int sigma2)
{
int i = blockDim.x*blockIdx.x + threadIdx.x;
int j = blockDim.y*blockIdx.y + threadIdx.y;
// It is also true that ( k == (N*i + j) )
// Calc Dist...
float dist = 0;
for(int d=0; d<D; d++)
dist+= (y[i*D+d] - x[j*D+d])*(y[i*D+d] - x[j*D+d]);
K[i*N+j] = kernel_fun(dist, sigma2);
}
__global__
void kernel_sum_div(int D, float* y_new, float* K_sum)
{
int i = blockDim.x*blockIdx.x + threadIdx.x;
for(int d=0; d<D; d++)
y_new[i*D+d] = y_new[i*D+d]/K_sum[i];
}
__global__ void kernel_Dvec_mult(int N, int D, float* K, float* x, float* Kx, int d)
{
int i = blockDim.x*blockIdx.x + threadIdx.x;
int j = blockDim.y*blockIdx.y + threadIdx.y;
Kx[i*N+j] = K[i*N+j]*x[j*D+d];
}
__global__ void copy_to_y(int D, float* d_y_new, float* kernelXsum, int d)
{
int i = blockDim.x*blockIdx.x + threadIdx.x;
d_y_new[i*D+d] = kernelXsum[i];
}
__global__ void calc_reduce_meanshift(int N, float* y_new, float* y_old, float* reducted_vec)
{
extern __shared__ float reduction_cache[] ;
//thread ID on each row of blocks
int tid = blockDim.x * blockIdx.x + threadIdx.x;
int cache_i = threadIdx.x;
float temp=0;
float tempY_new; // This are usuful to ensure that only on GB access is gonna happen for each vector
float tempY_old;
while (tid < N)
{
tempY_new = y_new[tid];
tempY_old= y_old[tid];
temp += (tempY_new-tempY_old)*(tempY_new-tempY_old);
tid += blockDim.x * gridDim.x;
}
reduction_cache[cache_i] = temp;
__syncthreads();
// Begin the reduction per shared-memory-block
for(int i=blockDim.x/2; i>0; i>>=1)
{
if(cache_i < i)
reduction_cache[cache_i] += reduction_cache[cache_i+i];
__syncthreads();
}
// Final Sum is stored in global array.
if(cache_i==0)
reducted_vec[blockIdx.x] = reduction_cache[0];
}
// __global__
// void kernelX_dot_product(int N, int D, int d, float* K, float* x, float* reducted_vec)
// {
// extern __shared__ float reduction_cache[] ;
// //thread ID on each row of blocks
// int tid = blockDim.x * blockIdx.x + threadIdx.x;
// int cache_i = threadIdx.x;
// /* This UNROLLS the elements of x, "outside" the grid's index range.
// In the case of N=600, threadsPerBlock=256 and 2 blocks in total,
// we have 600-256*2=88 additions done in parallel, before the reduction of the 512 threads.
// incase the index-range > N, the reduction scheme will simply add some zeros to the vector.
// This allows as to oversubscribe in terms of threads and blocks.
// */
// int offset = N*blockIdx.y;
// float temp=0;
// while (tid < N)
// {
// temp += K[tid+offset]*x[tid*D+d];
// tid += blockDim.x * gridDim.x;
// }
// /* Load x-data into local shared memory.
// As mentioned before, some entries are small sums of
// x's outside the grid's range */
// reduction_cache[cache_i] = temp;
// __syncthreads();
// // Begin the reduction per shared-memory-block
// for(int i=blockDim.x/2; i>0; i>>=1)
// {
// if(cache_i < i)
// reduction_cache[cache_i] += reduction_cache[cache_i+i];
// __syncthreads();
// }
// // Final Sum is stored in global array, with stride d, to match the NxD dimensionality of the input dataset.
// if(cache_i==0)
// reducted_vec[blockIdx.y*gridDim.x + blockIdx.x + d] = reduction_cache[cache_i];
// }
// void WR_kernelX_dow_product(int N, float* d_K, float* d_x, /*out*/ ReductionCache* rc )
// {
// dim3 blockDim2(4, 1, 1);
// dim3 gridDim2(N/4,N,1);
// size_t cache_size = 4*N*sizeof(float);
// kernelX_dot_product<<<gridDim2, blockDim2, cache_size>>>(N,D,0, d_KernelMatrix, d_x, d_y_new);
// kernelX_dot_product<<<gridDim2, blockDim2, cache_size>>>(N,D,1, d_KernelMatrix, d_x, d_y_new);
// //reduction_sum<<<L/256, 256, 256*sizeof(float) >>>(N/4, d_y_new, d_y_new);
// if(rc->blocksNum == 1)
// {
// kernelX_dot_product<<<rc->gridDim, rc->blockDim, rc->cache_size>>>(N,D,0, d_K,d_x, rc->d_sum);
// kernelX_dot_product<<<rc->gridDim, rc->blockDim, rc->cache_size>>>(N,D,1, d_K,d_x, rc->d_sum);
// }
// else
// {
// // We need multiple reduction calls!
// reduction_sum <<<rc->gridDim, rc->blockDim, rc->cache_size>>>(N, d_A, rc->d_reduced_vec);
// /* Reduct the final reduction vector! */
// // Ideally we would like threads_num==length(reduced_vec)/numRow.
// However threads_num2 must be a power of 2. Thus:
// int threads_num2 = exp2f(floor(log2f(rc->reduced_vec_length/rc->rowNum)));
// if(threads_num2>512)
// threads_num2=512;
// //printf("THREADS: %d RED_VEC %d\n", threads_num2, rc->reduced_vec_length/rc->rowNum );
// dim3 gridDim2(1,rc->rowNum,1);
// dim3 blockDim2(threads_num2,1,1);
// reduction_sum<<<gridDim2, blockDim2, threads_num2*sizeof(float)>>>\
// (rc->gridDim.x, rc->d_reduced_vec, rc->d_sum); //
// // WARNING: launching with original thread_num might be too much.
// // SOLUTION: Find power-of-2 nearest to block_num
// }
// } | .file "tmpxft_000c76d3_00000000-6_cuda_meanshift.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10kernel_funff
.type _Z10kernel_funff, @function
_Z10kernel_funff:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z10kernel_funff, .-_Z10kernel_funff
.globl _Z39__device_stub__Z15calc_meanshift2PfS_S_PfS_S_
.type _Z39__device_stub__Z15calc_meanshift2PfS_S_PfS_S_, @function
_Z39__device_stub__Z15calc_meanshift2PfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15calc_meanshift2PfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z39__device_stub__Z15calc_meanshift2PfS_S_PfS_S_, .-_Z39__device_stub__Z15calc_meanshift2PfS_S_PfS_S_
.globl _Z15calc_meanshift2PfS_S_
.type _Z15calc_meanshift2PfS_S_, @function
_Z15calc_meanshift2PfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15calc_meanshift2PfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z15calc_meanshift2PfS_S_, .-_Z15calc_meanshift2PfS_S_
.globl _Z45__device_stub__Z18calc_Kernel_MatrixiiPfS_S_iiiPfS_S_i
.type _Z45__device_stub__Z18calc_Kernel_MatrixiiPfS_S_iiiPfS_S_i, @function
_Z45__device_stub__Z18calc_Kernel_MatrixiiPfS_S_iiiPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18calc_Kernel_MatrixiiPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z45__device_stub__Z18calc_Kernel_MatrixiiPfS_S_iiiPfS_S_i, .-_Z45__device_stub__Z18calc_Kernel_MatrixiiPfS_S_iiiPfS_S_i
.globl _Z18calc_Kernel_MatrixiiPfS_S_i
.type _Z18calc_Kernel_MatrixiiPfS_S_i, @function
_Z18calc_Kernel_MatrixiiPfS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z18calc_Kernel_MatrixiiPfS_S_iiiPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z18calc_Kernel_MatrixiiPfS_S_i, .-_Z18calc_Kernel_MatrixiiPfS_S_i
.globl _Z37__device_stub__Z14kernel_sum_diviPfS_iPfS_
.type _Z37__device_stub__Z14kernel_sum_diviPfS_iPfS_, @function
_Z37__device_stub__Z14kernel_sum_diviPfS_iPfS_:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14kernel_sum_diviPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z37__device_stub__Z14kernel_sum_diviPfS_iPfS_, .-_Z37__device_stub__Z14kernel_sum_diviPfS_iPfS_
.globl _Z14kernel_sum_diviPfS_
.type _Z14kernel_sum_diviPfS_, @function
_Z14kernel_sum_diviPfS_:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z14kernel_sum_diviPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z14kernel_sum_diviPfS_, .-_Z14kernel_sum_diviPfS_
.globl _Z43__device_stub__Z16kernel_Dvec_multiiPfS_S_iiiPfS_S_i
.type _Z43__device_stub__Z16kernel_Dvec_multiiPfS_S_iiiPfS_S_i, @function
_Z43__device_stub__Z16kernel_Dvec_multiiPfS_S_iiiPfS_S_i:
.LFB2088:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16kernel_Dvec_multiiPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z43__device_stub__Z16kernel_Dvec_multiiPfS_S_iiiPfS_S_i, .-_Z43__device_stub__Z16kernel_Dvec_multiiPfS_S_iiiPfS_S_i
.globl _Z16kernel_Dvec_multiiPfS_S_i
.type _Z16kernel_Dvec_multiiPfS_S_i, @function
_Z16kernel_Dvec_multiiPfS_S_i:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z16kernel_Dvec_multiiPfS_S_iiiPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z16kernel_Dvec_multiiPfS_S_i, .-_Z16kernel_Dvec_multiiPfS_S_i
.globl _Z32__device_stub__Z9copy_to_yiPfS_iiPfS_i
.type _Z32__device_stub__Z9copy_to_yiPfS_iiPfS_i, @function
_Z32__device_stub__Z9copy_to_yiPfS_iiPfS_i:
.LFB2090:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 24(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9copy_to_yiPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z32__device_stub__Z9copy_to_yiPfS_iiPfS_i, .-_Z32__device_stub__Z9copy_to_yiPfS_iiPfS_i
.globl _Z9copy_to_yiPfS_i
.type _Z9copy_to_yiPfS_i, @function
_Z9copy_to_yiPfS_i:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9copy_to_yiPfS_iiPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z9copy_to_yiPfS_i, .-_Z9copy_to_yiPfS_i
.globl _Z46__device_stub__Z21calc_reduce_meanshiftiPfS_S_iPfS_S_
.type _Z46__device_stub__Z21calc_reduce_meanshiftiPfS_S_iPfS_S_, @function
_Z46__device_stub__Z21calc_reduce_meanshiftiPfS_S_iPfS_S_:
.LFB2092:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L49
.L45:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L50
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21calc_reduce_meanshiftiPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L45
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2092:
.size _Z46__device_stub__Z21calc_reduce_meanshiftiPfS_S_iPfS_S_, .-_Z46__device_stub__Z21calc_reduce_meanshiftiPfS_S_iPfS_S_
.globl _Z21calc_reduce_meanshiftiPfS_S_
.type _Z21calc_reduce_meanshiftiPfS_S_, @function
_Z21calc_reduce_meanshiftiPfS_S_:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z21calc_reduce_meanshiftiPfS_S_iPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _Z21calc_reduce_meanshiftiPfS_S_, .-_Z21calc_reduce_meanshiftiPfS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z21calc_reduce_meanshiftiPfS_S_"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z9copy_to_yiPfS_i"
.LC2:
.string "_Z16kernel_Dvec_multiiPfS_S_i"
.LC3:
.string "_Z14kernel_sum_diviPfS_"
.section .rodata.str1.8
.align 8
.LC4:
.string "_Z18calc_Kernel_MatrixiiPfS_S_i"
.section .rodata.str1.1
.LC5:
.string "_Z15calc_meanshift2PfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2095:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21calc_reduce_meanshiftiPfS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9copy_to_yiPfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z16kernel_Dvec_multiiPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z14kernel_sum_diviPfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z18calc_Kernel_MatrixiiPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z15calc_meanshift2PfS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
__global__
void calc_meanshift2(float* y_new, float* y_old, float* meanshift)
{
int i = blockDim.x*blockIdx.x + threadIdx.x;
float tempY_new = y_new[i];
float tempY_old = y_old[i];
meanshift[i] = (tempY_new-tempY_old)*(tempY_new-tempY_old);
}
__device__
float kernel_fun(float x, float sigma2)
{
if( x > sigma2)
return 0;
else
return exp(-x/2/sigma2);
}
__global__
void calc_Kernel_Matrix(int N, int D, float *x, float *y, float *K, int sigma2)
{
int i = blockDim.x*blockIdx.x + threadIdx.x;
int j = blockDim.y*blockIdx.y + threadIdx.y;
// It is also true that ( k == (N*i + j) )
// Calc Dist...
float dist = 0;
for(int d=0; d<D; d++)
dist+= (y[i*D+d] - x[j*D+d])*(y[i*D+d] - x[j*D+d]);
K[i*N+j] = kernel_fun(dist, sigma2);
}
__global__
void kernel_sum_div(int D, float* y_new, float* K_sum)
{
int i = blockDim.x*blockIdx.x + threadIdx.x;
for(int d=0; d<D; d++)
y_new[i*D+d] = y_new[i*D+d]/K_sum[i];
}
__global__ void kernel_Dvec_mult(int N, int D, float* K, float* x, float* Kx, int d)
{
int i = blockDim.x*blockIdx.x + threadIdx.x;
int j = blockDim.y*blockIdx.y + threadIdx.y;
Kx[i*N+j] = K[i*N+j]*x[j*D+d];
}
__global__ void copy_to_y(int D, float* d_y_new, float* kernelXsum, int d)
{
int i = blockDim.x*blockIdx.x + threadIdx.x;
d_y_new[i*D+d] = kernelXsum[i];
}
__global__ void calc_reduce_meanshift(int N, float* y_new, float* y_old, float* reducted_vec)
{
extern __shared__ float reduction_cache[] ;
//thread ID on each row of blocks
int tid = blockDim.x * blockIdx.x + threadIdx.x;
int cache_i = threadIdx.x;
float temp=0;
float tempY_new; // This are usuful to ensure that only on GB access is gonna happen for each vector
float tempY_old;
while (tid < N)
{
tempY_new = y_new[tid];
tempY_old= y_old[tid];
temp += (tempY_new-tempY_old)*(tempY_new-tempY_old);
tid += blockDim.x * gridDim.x;
}
reduction_cache[cache_i] = temp;
__syncthreads();
// Begin the reduction per shared-memory-block
for(int i=blockDim.x/2; i>0; i>>=1)
{
if(cache_i < i)
reduction_cache[cache_i] += reduction_cache[cache_i+i];
__syncthreads();
}
// Final Sum is stored in global array.
if(cache_i==0)
reducted_vec[blockIdx.x] = reduction_cache[0];
}
// __global__
// void kernelX_dot_product(int N, int D, int d, float* K, float* x, float* reducted_vec)
// {
// extern __shared__ float reduction_cache[] ;
// //thread ID on each row of blocks
// int tid = blockDim.x * blockIdx.x + threadIdx.x;
// int cache_i = threadIdx.x;
// /* This UNROLLS the elements of x, "outside" the grid's index range.
// In the case of N=600, threadsPerBlock=256 and 2 blocks in total,
// we have 600-256*2=88 additions done in parallel, before the reduction of the 512 threads.
// incase the index-range > N, the reduction scheme will simply add some zeros to the vector.
// This allows as to oversubscribe in terms of threads and blocks.
// */
// int offset = N*blockIdx.y;
// float temp=0;
// while (tid < N)
// {
// temp += K[tid+offset]*x[tid*D+d];
// tid += blockDim.x * gridDim.x;
// }
// /* Load x-data into local shared memory.
// As mentioned before, some entries are small sums of
// x's outside the grid's range */
// reduction_cache[cache_i] = temp;
// __syncthreads();
// // Begin the reduction per shared-memory-block
// for(int i=blockDim.x/2; i>0; i>>=1)
// {
// if(cache_i < i)
// reduction_cache[cache_i] += reduction_cache[cache_i+i];
// __syncthreads();
// }
// // Final Sum is stored in global array, with stride d, to match the NxD dimensionality of the input dataset.
// if(cache_i==0)
// reducted_vec[blockIdx.y*gridDim.x + blockIdx.x + d] = reduction_cache[cache_i];
// }
// void WR_kernelX_dow_product(int N, float* d_K, float* d_x, /*out*/ ReductionCache* rc )
// {
// dim3 blockDim2(4, 1, 1);
// dim3 gridDim2(N/4,N,1);
// size_t cache_size = 4*N*sizeof(float);
// kernelX_dot_product<<<gridDim2, blockDim2, cache_size>>>(N,D,0, d_KernelMatrix, d_x, d_y_new);
// kernelX_dot_product<<<gridDim2, blockDim2, cache_size>>>(N,D,1, d_KernelMatrix, d_x, d_y_new);
// //reduction_sum<<<L/256, 256, 256*sizeof(float) >>>(N/4, d_y_new, d_y_new);
// if(rc->blocksNum == 1)
// {
// kernelX_dot_product<<<rc->gridDim, rc->blockDim, rc->cache_size>>>(N,D,0, d_K,d_x, rc->d_sum);
// kernelX_dot_product<<<rc->gridDim, rc->blockDim, rc->cache_size>>>(N,D,1, d_K,d_x, rc->d_sum);
// }
// else
// {
// // We need multiple reduction calls!
// reduction_sum <<<rc->gridDim, rc->blockDim, rc->cache_size>>>(N, d_A, rc->d_reduced_vec);
// /* Reduct the final reduction vector! */
// // Ideally we would like threads_num==length(reduced_vec)/numRow.
// However threads_num2 must be a power of 2. Thus:
// int threads_num2 = exp2f(floor(log2f(rc->reduced_vec_length/rc->rowNum)));
// if(threads_num2>512)
// threads_num2=512;
// //printf("THREADS: %d RED_VEC %d\n", threads_num2, rc->reduced_vec_length/rc->rowNum );
// dim3 gridDim2(1,rc->rowNum,1);
// dim3 blockDim2(threads_num2,1,1);
// reduction_sum<<<gridDim2, blockDim2, threads_num2*sizeof(float)>>>\
// (rc->gridDim.x, rc->d_reduced_vec, rc->d_sum); //
// // WARNING: launching with original thread_num might be too much.
// // SOLUTION: Find power-of-2 nearest to block_num
// }
// } | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__
void calc_meanshift2(float* y_new, float* y_old, float* meanshift)
{
int i = blockDim.x*blockIdx.x + threadIdx.x;
float tempY_new = y_new[i];
float tempY_old = y_old[i];
meanshift[i] = (tempY_new-tempY_old)*(tempY_new-tempY_old);
}
__device__
float kernel_fun(float x, float sigma2)
{
if( x > sigma2)
return 0;
else
return exp(-x/2/sigma2);
}
__global__
void calc_Kernel_Matrix(int N, int D, float *x, float *y, float *K, int sigma2)
{
int i = blockDim.x*blockIdx.x + threadIdx.x;
int j = blockDim.y*blockIdx.y + threadIdx.y;
// It is also true that ( k == (N*i + j) )
// Calc Dist...
float dist = 0;
for(int d=0; d<D; d++)
dist+= (y[i*D+d] - x[j*D+d])*(y[i*D+d] - x[j*D+d]);
K[i*N+j] = kernel_fun(dist, sigma2);
}
__global__
void kernel_sum_div(int D, float* y_new, float* K_sum)
{
int i = blockDim.x*blockIdx.x + threadIdx.x;
for(int d=0; d<D; d++)
y_new[i*D+d] = y_new[i*D+d]/K_sum[i];
}
__global__ void kernel_Dvec_mult(int N, int D, float* K, float* x, float* Kx, int d)
{
int i = blockDim.x*blockIdx.x + threadIdx.x;
int j = blockDim.y*blockIdx.y + threadIdx.y;
Kx[i*N+j] = K[i*N+j]*x[j*D+d];
}
__global__ void copy_to_y(int D, float* d_y_new, float* kernelXsum, int d)
{
int i = blockDim.x*blockIdx.x + threadIdx.x;
d_y_new[i*D+d] = kernelXsum[i];
}
__global__ void calc_reduce_meanshift(int N, float* y_new, float* y_old, float* reducted_vec)
{
extern __shared__ float reduction_cache[] ;
//thread ID on each row of blocks
int tid = blockDim.x * blockIdx.x + threadIdx.x;
int cache_i = threadIdx.x;
float temp=0;
float tempY_new; // This are usuful to ensure that only on GB access is gonna happen for each vector
float tempY_old;
while (tid < N)
{
tempY_new = y_new[tid];
tempY_old= y_old[tid];
temp += (tempY_new-tempY_old)*(tempY_new-tempY_old);
tid += blockDim.x * gridDim.x;
}
reduction_cache[cache_i] = temp;
__syncthreads();
// Begin the reduction per shared-memory-block
for(int i=blockDim.x/2; i>0; i>>=1)
{
if(cache_i < i)
reduction_cache[cache_i] += reduction_cache[cache_i+i];
__syncthreads();
}
// Final Sum is stored in global array.
if(cache_i==0)
reducted_vec[blockIdx.x] = reduction_cache[0];
}
// __global__
// void kernelX_dot_product(int N, int D, int d, float* K, float* x, float* reducted_vec)
// {
// extern __shared__ float reduction_cache[] ;
// //thread ID on each row of blocks
// int tid = blockDim.x * blockIdx.x + threadIdx.x;
// int cache_i = threadIdx.x;
// /* This UNROLLS the elements of x, "outside" the grid's index range.
// In the case of N=600, threadsPerBlock=256 and 2 blocks in total,
// we have 600-256*2=88 additions done in parallel, before the reduction of the 512 threads.
// incase the index-range > N, the reduction scheme will simply add some zeros to the vector.
// This allows as to oversubscribe in terms of threads and blocks.
// */
// int offset = N*blockIdx.y;
// float temp=0;
// while (tid < N)
// {
// temp += K[tid+offset]*x[tid*D+d];
// tid += blockDim.x * gridDim.x;
// }
// /* Load x-data into local shared memory.
// As mentioned before, some entries are small sums of
// x's outside the grid's range */
// reduction_cache[cache_i] = temp;
// __syncthreads();
// // Begin the reduction per shared-memory-block
// for(int i=blockDim.x/2; i>0; i>>=1)
// {
// if(cache_i < i)
// reduction_cache[cache_i] += reduction_cache[cache_i+i];
// __syncthreads();
// }
// // Final Sum is stored in global array, with stride d, to match the NxD dimensionality of the input dataset.
// if(cache_i==0)
// reducted_vec[blockIdx.y*gridDim.x + blockIdx.x + d] = reduction_cache[cache_i];
// }
// void WR_kernelX_dow_product(int N, float* d_K, float* d_x, /*out*/ ReductionCache* rc )
// {
// dim3 blockDim2(4, 1, 1);
// dim3 gridDim2(N/4,N,1);
// size_t cache_size = 4*N*sizeof(float);
// kernelX_dot_product<<<gridDim2, blockDim2, cache_size>>>(N,D,0, d_KernelMatrix, d_x, d_y_new);
// kernelX_dot_product<<<gridDim2, blockDim2, cache_size>>>(N,D,1, d_KernelMatrix, d_x, d_y_new);
// //reduction_sum<<<L/256, 256, 256*sizeof(float) >>>(N/4, d_y_new, d_y_new);
// if(rc->blocksNum == 1)
// {
// kernelX_dot_product<<<rc->gridDim, rc->blockDim, rc->cache_size>>>(N,D,0, d_K,d_x, rc->d_sum);
// kernelX_dot_product<<<rc->gridDim, rc->blockDim, rc->cache_size>>>(N,D,1, d_K,d_x, rc->d_sum);
// }
// else
// {
// // We need multiple reduction calls!
// reduction_sum <<<rc->gridDim, rc->blockDim, rc->cache_size>>>(N, d_A, rc->d_reduced_vec);
// /* Reduct the final reduction vector! */
// // Ideally we would like threads_num==length(reduced_vec)/numRow.
// However threads_num2 must be a power of 2. Thus:
// int threads_num2 = exp2f(floor(log2f(rc->reduced_vec_length/rc->rowNum)));
// if(threads_num2>512)
// threads_num2=512;
// //printf("THREADS: %d RED_VEC %d\n", threads_num2, rc->reduced_vec_length/rc->rowNum );
// dim3 gridDim2(1,rc->rowNum,1);
// dim3 blockDim2(threads_num2,1,1);
// reduction_sum<<<gridDim2, blockDim2, threads_num2*sizeof(float)>>>\
// (rc->gridDim.x, rc->d_reduced_vec, rc->d_sum); //
// // WARNING: launching with original thread_num might be too much.
// // SOLUTION: Find power-of-2 nearest to block_num
// }
// } |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__
void calc_meanshift2(float* y_new, float* y_old, float* meanshift)
{
int i = blockDim.x*blockIdx.x + threadIdx.x;
float tempY_new = y_new[i];
float tempY_old = y_old[i];
meanshift[i] = (tempY_new-tempY_old)*(tempY_new-tempY_old);
}
__device__
float kernel_fun(float x, float sigma2)
{
if( x > sigma2)
return 0;
else
return exp(-x/2/sigma2);
}
__global__
void calc_Kernel_Matrix(int N, int D, float *x, float *y, float *K, int sigma2)
{
int i = blockDim.x*blockIdx.x + threadIdx.x;
int j = blockDim.y*blockIdx.y + threadIdx.y;
// It is also true that ( k == (N*i + j) )
// Calc Dist...
float dist = 0;
for(int d=0; d<D; d++)
dist+= (y[i*D+d] - x[j*D+d])*(y[i*D+d] - x[j*D+d]);
K[i*N+j] = kernel_fun(dist, sigma2);
}
__global__
void kernel_sum_div(int D, float* y_new, float* K_sum)
{
int i = blockDim.x*blockIdx.x + threadIdx.x;
for(int d=0; d<D; d++)
y_new[i*D+d] = y_new[i*D+d]/K_sum[i];
}
__global__ void kernel_Dvec_mult(int N, int D, float* K, float* x, float* Kx, int d)
{
int i = blockDim.x*blockIdx.x + threadIdx.x;
int j = blockDim.y*blockIdx.y + threadIdx.y;
Kx[i*N+j] = K[i*N+j]*x[j*D+d];
}
__global__ void copy_to_y(int D, float* d_y_new, float* kernelXsum, int d)
{
int i = blockDim.x*blockIdx.x + threadIdx.x;
d_y_new[i*D+d] = kernelXsum[i];
}
__global__ void calc_reduce_meanshift(int N, float* y_new, float* y_old, float* reducted_vec)
{
extern __shared__ float reduction_cache[] ;
//thread ID on each row of blocks
int tid = blockDim.x * blockIdx.x + threadIdx.x;
int cache_i = threadIdx.x;
float temp=0;
float tempY_new; // This are usuful to ensure that only on GB access is gonna happen for each vector
float tempY_old;
while (tid < N)
{
tempY_new = y_new[tid];
tempY_old= y_old[tid];
temp += (tempY_new-tempY_old)*(tempY_new-tempY_old);
tid += blockDim.x * gridDim.x;
}
reduction_cache[cache_i] = temp;
__syncthreads();
// Begin the reduction per shared-memory-block
for(int i=blockDim.x/2; i>0; i>>=1)
{
if(cache_i < i)
reduction_cache[cache_i] += reduction_cache[cache_i+i];
__syncthreads();
}
// Final Sum is stored in global array.
if(cache_i==0)
reducted_vec[blockIdx.x] = reduction_cache[0];
}
// __global__
// void kernelX_dot_product(int N, int D, int d, float* K, float* x, float* reducted_vec)
// {
// extern __shared__ float reduction_cache[] ;
// //thread ID on each row of blocks
// int tid = blockDim.x * blockIdx.x + threadIdx.x;
// int cache_i = threadIdx.x;
// /* This UNROLLS the elements of x, "outside" the grid's index range.
// In the case of N=600, threadsPerBlock=256 and 2 blocks in total,
// we have 600-256*2=88 additions done in parallel, before the reduction of the 512 threads.
// incase the index-range > N, the reduction scheme will simply add some zeros to the vector.
// This allows as to oversubscribe in terms of threads and blocks.
// */
// int offset = N*blockIdx.y;
// float temp=0;
// while (tid < N)
// {
// temp += K[tid+offset]*x[tid*D+d];
// tid += blockDim.x * gridDim.x;
// }
// /* Load x-data into local shared memory.
// As mentioned before, some entries are small sums of
// x's outside the grid's range */
// reduction_cache[cache_i] = temp;
// __syncthreads();
// // Begin the reduction per shared-memory-block
// for(int i=blockDim.x/2; i>0; i>>=1)
// {
// if(cache_i < i)
// reduction_cache[cache_i] += reduction_cache[cache_i+i];
// __syncthreads();
// }
// // Final Sum is stored in global array, with stride d, to match the NxD dimensionality of the input dataset.
// if(cache_i==0)
// reducted_vec[blockIdx.y*gridDim.x + blockIdx.x + d] = reduction_cache[cache_i];
// }
// void WR_kernelX_dow_product(int N, float* d_K, float* d_x, /*out*/ ReductionCache* rc )
// {
// dim3 blockDim2(4, 1, 1);
// dim3 gridDim2(N/4,N,1);
// size_t cache_size = 4*N*sizeof(float);
// kernelX_dot_product<<<gridDim2, blockDim2, cache_size>>>(N,D,0, d_KernelMatrix, d_x, d_y_new);
// kernelX_dot_product<<<gridDim2, blockDim2, cache_size>>>(N,D,1, d_KernelMatrix, d_x, d_y_new);
// //reduction_sum<<<L/256, 256, 256*sizeof(float) >>>(N/4, d_y_new, d_y_new);
// if(rc->blocksNum == 1)
// {
// kernelX_dot_product<<<rc->gridDim, rc->blockDim, rc->cache_size>>>(N,D,0, d_K,d_x, rc->d_sum);
// kernelX_dot_product<<<rc->gridDim, rc->blockDim, rc->cache_size>>>(N,D,1, d_K,d_x, rc->d_sum);
// }
// else
// {
// // We need multiple reduction calls!
// reduction_sum <<<rc->gridDim, rc->blockDim, rc->cache_size>>>(N, d_A, rc->d_reduced_vec);
// /* Reduct the final reduction vector! */
// // Ideally we would like threads_num==length(reduced_vec)/numRow.
// However threads_num2 must be a power of 2. Thus:
// int threads_num2 = exp2f(floor(log2f(rc->reduced_vec_length/rc->rowNum)));
// if(threads_num2>512)
// threads_num2=512;
// //printf("THREADS: %d RED_VEC %d\n", threads_num2, rc->reduced_vec_length/rc->rowNum );
// dim3 gridDim2(1,rc->rowNum,1);
// dim3 blockDim2(threads_num2,1,1);
// reduction_sum<<<gridDim2, blockDim2, threads_num2*sizeof(float)>>>\
// (rc->gridDim.x, rc->d_reduced_vec, rc->d_sum); //
// // WARNING: launching with original thread_num might be too much.
// // SOLUTION: Find power-of-2 nearest to block_num
// }
// } | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15calc_meanshift2PfS_S_
.globl _Z15calc_meanshift2PfS_S_
.p2align 8
.type _Z15calc_meanshift2PfS_S_,@function
_Z15calc_meanshift2PfS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15calc_meanshift2PfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15calc_meanshift2PfS_S_, .Lfunc_end0-_Z15calc_meanshift2PfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z18calc_Kernel_MatrixiiPfS_S_i
.globl _Z18calc_Kernel_MatrixiiPfS_S_i
.p2align 8
.type _Z18calc_Kernel_MatrixiiPfS_S_i,@function
_Z18calc_Kernel_MatrixiiPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x34
s_load_b32 s2, s[0:1], 0x4
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB1_3
s_load_b128 s[4:7], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v2, v1, s2
v_mul_lo_u32 v4, v0, s2
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
.LBB1_2:
global_load_b32 v7, v[4:5], off
global_load_b32 v8, v[2:3], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 0
s_waitcnt vmcnt(0)
v_sub_f32_e32 v7, v7, v8
v_fmac_f32_e32 v6, v7, v7
s_cbranch_scc0 .LBB1_2
s_branch .LBB1_4
.LBB1_3:
v_mov_b32_e32 v6, 0
.LBB1_4:
s_load_b32 s2, s[0:1], 0x20
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
v_cvt_f32_i32_e32 v2, s2
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ngt_f32_e32 v6, v2
s_cbranch_execz .LBB1_6
v_mul_f32_e32 v3, -0.5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v4, null, v2, v2, v3
v_div_scale_f32 v7, vcc_lo, v3, v2, v3
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_mul_f32_e32 v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v6, v7
v_fmac_f32_e32 v6, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v6, v7
v_div_fmas_f32 v4, v4, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v2, v4, v2, v3
v_mul_f32_e32 v3, 0x3fb8aa3b, v2
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v4, v2, 0x3fb8aa3b, -v3
v_rndne_f32_e32 v5, v3
v_dual_fmamk_f32 v4, v2, 0x32a5705f, v4 :: v_dual_sub_f32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v3, v3, v4
v_cvt_i32_f32_e32 v4, v5
v_exp_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_ldexp_f32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v2
v_cndmask_b32_e32 v3, 0x7f800000, v3, vcc_lo
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s2
s_clause 0x1
s_load_b32 s2, s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[4:5], null, v0, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[0:1], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18calc_Kernel_MatrixiiPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z18calc_Kernel_MatrixiiPfS_S_i, .Lfunc_end1-_Z18calc_Kernel_MatrixiiPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14kernel_sum_diviPfS_
.globl _Z14kernel_sum_diviPfS_
.p2align 8
.type _Z14kernel_sum_diviPfS_,@function
_Z14kernel_sum_diviPfS_:
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB2_3
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
v_mul_lo_u32 v3, v1, s2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB2_2:
global_load_b32 v4, v[2:3], off
global_load_b32 v5, v[0:1], off
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s2, 0
s_waitcnt vmcnt(0)
v_div_scale_f32 v6, null, v5, v5, v4
v_div_scale_f32 v9, vcc_lo, v4, v5, v4
v_rcp_f32_e32 v7, v6
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v6, v7, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v7
v_mul_f32_e32 v8, v9, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v10, -v6, v8, v9
v_fmac_f32_e32 v8, v10, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, -v6, v8, v9
v_div_fmas_f32 v6, v6, v7, v8
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v4, v6, v5, v4
global_store_b32 v[2:3], v4, off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_cbranch_scc0 .LBB2_2
.LBB2_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14kernel_sum_diviPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z14kernel_sum_diviPfS_, .Lfunc_end2-_Z14kernel_sum_diviPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16kernel_Dvec_multiiPfS_S_i
.globl _Z16kernel_Dvec_multiiPfS_S_i
.p2align 8
.type _Z16kernel_Dvec_multiiPfS_S_i,@function
_Z16kernel_Dvec_multiiPfS_S_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x20
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s1, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, v2, s4, v[3:4]
v_mad_u64_u32 v[4:5], null, v3, s5, s[0:1]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[4:5]
v_add_co_u32 v4, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s8, v2
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
v_add_co_u32 v0, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v4, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16kernel_Dvec_multiiPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z16kernel_Dvec_multiiPfS_S_i, .Lfunc_end3-_Z16kernel_Dvec_multiiPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9copy_to_yiPfS_i
.globl _Z9copy_to_yiPfS_i
.p2align 8
.type _Z9copy_to_yiPfS_i,@function
_Z9copy_to_yiPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_clause 0x1
s_load_b32 s2, s[0:1], 0x18
s_load_b32 s0, s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v4, v[2:3], off
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s0, s[2:3]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9copy_to_yiPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end4:
.size _Z9copy_to_yiPfS_i, .Lfunc_end4-_Z9copy_to_yiPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z21calc_reduce_meanshiftiPfS_S_
.globl _Z21calc_reduce_meanshiftiPfS_S_
.p2align 8
.type _Z21calc_reduce_meanshiftiPfS_S_,@function
_Z21calc_reduce_meanshiftiPfS_S_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x0
s_add_u32 s4, s0, 32
s_mov_b32 s2, s15
s_addc_u32 s5, s1, 0
v_mov_b32_e32 v3, 0
s_mov_b32 s9, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB5_4
s_load_b32 s11, s[4:5], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
v_mov_b32_e32 v3, 0
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s11, s11, s3
.p2align 6
.LBB5_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_co_u32 v6, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
global_load_b32 v2, v[6:7], off
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_dual_sub_f32 v2, v2, v4 :: v_dual_add_nc_u32 v1, s11, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_i32_e32 vcc_lo, s8, v1
v_fmac_f32_e32 v3, v2, v2
s_or_b32 s10, vcc_lo, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB5_2
s_or_b32 exec_lo, exec_lo, s10
.LBB5_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s9
v_lshl_add_u32 v1, v0, 2, 0
s_cmp_lt_u32 s3, 2
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB5_6
.p2align 6
.LBB5_5:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s4
.LBB5_6:
buffer_gl0_inv
s_cbranch_scc1 .LBB5_9
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB5_5
v_add_nc_u32_e32 v2, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB5_5
.LBB5_9:
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB5_11
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x18
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB5_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21calc_reduce_meanshiftiPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end5:
.size _Z21calc_reduce_meanshiftiPfS_S_, .Lfunc_end5-_Z21calc_reduce_meanshiftiPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15calc_meanshift2PfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15calc_meanshift2PfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
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.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
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.size: 2
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- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18calc_Kernel_MatrixiiPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18calc_Kernel_MatrixiiPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
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.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
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.private_segment_fixed_size: 0
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.sgpr_spill_count: 0
.symbol: _Z14kernel_sum_diviPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
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- .args:
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.name: _Z9copy_to_yiPfS_i
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.sgpr_spill_count: 0
.symbol: _Z9copy_to_yiPfS_i.kd
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- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21calc_reduce_meanshiftiPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21calc_reduce_meanshiftiPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__
void calc_meanshift2(float* y_new, float* y_old, float* meanshift)
{
int i = blockDim.x*blockIdx.x + threadIdx.x;
float tempY_new = y_new[i];
float tempY_old = y_old[i];
meanshift[i] = (tempY_new-tempY_old)*(tempY_new-tempY_old);
}
__device__
float kernel_fun(float x, float sigma2)
{
if( x > sigma2)
return 0;
else
return exp(-x/2/sigma2);
}
__global__
void calc_Kernel_Matrix(int N, int D, float *x, float *y, float *K, int sigma2)
{
int i = blockDim.x*blockIdx.x + threadIdx.x;
int j = blockDim.y*blockIdx.y + threadIdx.y;
// It is also true that ( k == (N*i + j) )
// Calc Dist...
float dist = 0;
for(int d=0; d<D; d++)
dist+= (y[i*D+d] - x[j*D+d])*(y[i*D+d] - x[j*D+d]);
K[i*N+j] = kernel_fun(dist, sigma2);
}
__global__
void kernel_sum_div(int D, float* y_new, float* K_sum)
{
int i = blockDim.x*blockIdx.x + threadIdx.x;
for(int d=0; d<D; d++)
y_new[i*D+d] = y_new[i*D+d]/K_sum[i];
}
__global__ void kernel_Dvec_mult(int N, int D, float* K, float* x, float* Kx, int d)
{
int i = blockDim.x*blockIdx.x + threadIdx.x;
int j = blockDim.y*blockIdx.y + threadIdx.y;
Kx[i*N+j] = K[i*N+j]*x[j*D+d];
}
__global__ void copy_to_y(int D, float* d_y_new, float* kernelXsum, int d)
{
int i = blockDim.x*blockIdx.x + threadIdx.x;
d_y_new[i*D+d] = kernelXsum[i];
}
__global__ void calc_reduce_meanshift(int N, float* y_new, float* y_old, float* reducted_vec)
{
extern __shared__ float reduction_cache[] ;
//thread ID on each row of blocks
int tid = blockDim.x * blockIdx.x + threadIdx.x;
int cache_i = threadIdx.x;
float temp=0;
float tempY_new; // This are usuful to ensure that only on GB access is gonna happen for each vector
float tempY_old;
while (tid < N)
{
tempY_new = y_new[tid];
tempY_old= y_old[tid];
temp += (tempY_new-tempY_old)*(tempY_new-tempY_old);
tid += blockDim.x * gridDim.x;
}
reduction_cache[cache_i] = temp;
__syncthreads();
// Begin the reduction per shared-memory-block
for(int i=blockDim.x/2; i>0; i>>=1)
{
if(cache_i < i)
reduction_cache[cache_i] += reduction_cache[cache_i+i];
__syncthreads();
}
// Final Sum is stored in global array.
if(cache_i==0)
reducted_vec[blockIdx.x] = reduction_cache[0];
}
// __global__
// void kernelX_dot_product(int N, int D, int d, float* K, float* x, float* reducted_vec)
// {
// extern __shared__ float reduction_cache[] ;
// //thread ID on each row of blocks
// int tid = blockDim.x * blockIdx.x + threadIdx.x;
// int cache_i = threadIdx.x;
// /* This UNROLLS the elements of x, "outside" the grid's index range.
// In the case of N=600, threadsPerBlock=256 and 2 blocks in total,
// we have 600-256*2=88 additions done in parallel, before the reduction of the 512 threads.
// incase the index-range > N, the reduction scheme will simply add some zeros to the vector.
// This allows as to oversubscribe in terms of threads and blocks.
// */
// int offset = N*blockIdx.y;
// float temp=0;
// while (tid < N)
// {
// temp += K[tid+offset]*x[tid*D+d];
// tid += blockDim.x * gridDim.x;
// }
// /* Load x-data into local shared memory.
// As mentioned before, some entries are small sums of
// x's outside the grid's range */
// reduction_cache[cache_i] = temp;
// __syncthreads();
// // Begin the reduction per shared-memory-block
// for(int i=blockDim.x/2; i>0; i>>=1)
// {
// if(cache_i < i)
// reduction_cache[cache_i] += reduction_cache[cache_i+i];
// __syncthreads();
// }
// // Final Sum is stored in global array, with stride d, to match the NxD dimensionality of the input dataset.
// if(cache_i==0)
// reducted_vec[blockIdx.y*gridDim.x + blockIdx.x + d] = reduction_cache[cache_i];
// }
// void WR_kernelX_dow_product(int N, float* d_K, float* d_x, /*out*/ ReductionCache* rc )
// {
// dim3 blockDim2(4, 1, 1);
// dim3 gridDim2(N/4,N,1);
// size_t cache_size = 4*N*sizeof(float);
// kernelX_dot_product<<<gridDim2, blockDim2, cache_size>>>(N,D,0, d_KernelMatrix, d_x, d_y_new);
// kernelX_dot_product<<<gridDim2, blockDim2, cache_size>>>(N,D,1, d_KernelMatrix, d_x, d_y_new);
// //reduction_sum<<<L/256, 256, 256*sizeof(float) >>>(N/4, d_y_new, d_y_new);
// if(rc->blocksNum == 1)
// {
// kernelX_dot_product<<<rc->gridDim, rc->blockDim, rc->cache_size>>>(N,D,0, d_K,d_x, rc->d_sum);
// kernelX_dot_product<<<rc->gridDim, rc->blockDim, rc->cache_size>>>(N,D,1, d_K,d_x, rc->d_sum);
// }
// else
// {
// // We need multiple reduction calls!
// reduction_sum <<<rc->gridDim, rc->blockDim, rc->cache_size>>>(N, d_A, rc->d_reduced_vec);
// /* Reduct the final reduction vector! */
// // Ideally we would like threads_num==length(reduced_vec)/numRow.
// However threads_num2 must be a power of 2. Thus:
// int threads_num2 = exp2f(floor(log2f(rc->reduced_vec_length/rc->rowNum)));
// if(threads_num2>512)
// threads_num2=512;
// //printf("THREADS: %d RED_VEC %d\n", threads_num2, rc->reduced_vec_length/rc->rowNum );
// dim3 gridDim2(1,rc->rowNum,1);
// dim3 blockDim2(threads_num2,1,1);
// reduction_sum<<<gridDim2, blockDim2, threads_num2*sizeof(float)>>>\
// (rc->gridDim.x, rc->d_reduced_vec, rc->d_sum); //
// // WARNING: launching with original thread_num might be too much.
// // SOLUTION: Find power-of-2 nearest to block_num
// }
// } | .text
.file "cuda_meanshift.hip"
.globl _Z30__device_stub__calc_meanshift2PfS_S_ # -- Begin function _Z30__device_stub__calc_meanshift2PfS_S_
.p2align 4, 0x90
.type _Z30__device_stub__calc_meanshift2PfS_S_,@function
_Z30__device_stub__calc_meanshift2PfS_S_: # @_Z30__device_stub__calc_meanshift2PfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15calc_meanshift2PfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__calc_meanshift2PfS_S_, .Lfunc_end0-_Z30__device_stub__calc_meanshift2PfS_S_
.cfi_endproc
# -- End function
.globl _Z33__device_stub__calc_Kernel_MatrixiiPfS_S_i # -- Begin function _Z33__device_stub__calc_Kernel_MatrixiiPfS_S_i
.p2align 4, 0x90
.type _Z33__device_stub__calc_Kernel_MatrixiiPfS_S_i,@function
_Z33__device_stub__calc_Kernel_MatrixiiPfS_S_i: # @_Z33__device_stub__calc_Kernel_MatrixiiPfS_S_i
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movl %r9d, 12(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18calc_Kernel_MatrixiiPfS_S_i, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z33__device_stub__calc_Kernel_MatrixiiPfS_S_i, .Lfunc_end1-_Z33__device_stub__calc_Kernel_MatrixiiPfS_S_i
.cfi_endproc
# -- End function
.globl _Z29__device_stub__kernel_sum_diviPfS_ # -- Begin function _Z29__device_stub__kernel_sum_diviPfS_
.p2align 4, 0x90
.type _Z29__device_stub__kernel_sum_diviPfS_,@function
_Z29__device_stub__kernel_sum_diviPfS_: # @_Z29__device_stub__kernel_sum_diviPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14kernel_sum_diviPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z29__device_stub__kernel_sum_diviPfS_, .Lfunc_end2-_Z29__device_stub__kernel_sum_diviPfS_
.cfi_endproc
# -- End function
.globl _Z31__device_stub__kernel_Dvec_multiiPfS_S_i # -- Begin function _Z31__device_stub__kernel_Dvec_multiiPfS_S_i
.p2align 4, 0x90
.type _Z31__device_stub__kernel_Dvec_multiiPfS_S_i,@function
_Z31__device_stub__kernel_Dvec_multiiPfS_S_i: # @_Z31__device_stub__kernel_Dvec_multiiPfS_S_i
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movl %r9d, 12(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16kernel_Dvec_multiiPfS_S_i, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end3:
.size _Z31__device_stub__kernel_Dvec_multiiPfS_S_i, .Lfunc_end3-_Z31__device_stub__kernel_Dvec_multiiPfS_S_i
.cfi_endproc
# -- End function
.globl _Z24__device_stub__copy_to_yiPfS_i # -- Begin function _Z24__device_stub__copy_to_yiPfS_i
.p2align 4, 0x90
.type _Z24__device_stub__copy_to_yiPfS_i,@function
_Z24__device_stub__copy_to_yiPfS_i: # @_Z24__device_stub__copy_to_yiPfS_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9copy_to_yiPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z24__device_stub__copy_to_yiPfS_i, .Lfunc_end4-_Z24__device_stub__copy_to_yiPfS_i
.cfi_endproc
# -- End function
.globl _Z36__device_stub__calc_reduce_meanshiftiPfS_S_ # -- Begin function _Z36__device_stub__calc_reduce_meanshiftiPfS_S_
.p2align 4, 0x90
.type _Z36__device_stub__calc_reduce_meanshiftiPfS_S_,@function
_Z36__device_stub__calc_reduce_meanshiftiPfS_S_: # @_Z36__device_stub__calc_reduce_meanshiftiPfS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21calc_reduce_meanshiftiPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end5:
.size _Z36__device_stub__calc_reduce_meanshiftiPfS_S_, .Lfunc_end5-_Z36__device_stub__calc_reduce_meanshiftiPfS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15calc_meanshift2PfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18calc_Kernel_MatrixiiPfS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14kernel_sum_diviPfS_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16kernel_Dvec_multiiPfS_S_i, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9copy_to_yiPfS_i, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21calc_reduce_meanshiftiPfS_S_, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15calc_meanshift2PfS_S_,@object # @_Z15calc_meanshift2PfS_S_
.section .rodata,"a",@progbits
.globl _Z15calc_meanshift2PfS_S_
.p2align 3, 0x0
_Z15calc_meanshift2PfS_S_:
.quad _Z30__device_stub__calc_meanshift2PfS_S_
.size _Z15calc_meanshift2PfS_S_, 8
.type _Z18calc_Kernel_MatrixiiPfS_S_i,@object # @_Z18calc_Kernel_MatrixiiPfS_S_i
.globl _Z18calc_Kernel_MatrixiiPfS_S_i
.p2align 3, 0x0
_Z18calc_Kernel_MatrixiiPfS_S_i:
.quad _Z33__device_stub__calc_Kernel_MatrixiiPfS_S_i
.size _Z18calc_Kernel_MatrixiiPfS_S_i, 8
.type _Z14kernel_sum_diviPfS_,@object # @_Z14kernel_sum_diviPfS_
.globl _Z14kernel_sum_diviPfS_
.p2align 3, 0x0
_Z14kernel_sum_diviPfS_:
.quad _Z29__device_stub__kernel_sum_diviPfS_
.size _Z14kernel_sum_diviPfS_, 8
.type _Z16kernel_Dvec_multiiPfS_S_i,@object # @_Z16kernel_Dvec_multiiPfS_S_i
.globl _Z16kernel_Dvec_multiiPfS_S_i
.p2align 3, 0x0
_Z16kernel_Dvec_multiiPfS_S_i:
.quad _Z31__device_stub__kernel_Dvec_multiiPfS_S_i
.size _Z16kernel_Dvec_multiiPfS_S_i, 8
.type _Z9copy_to_yiPfS_i,@object # @_Z9copy_to_yiPfS_i
.globl _Z9copy_to_yiPfS_i
.p2align 3, 0x0
_Z9copy_to_yiPfS_i:
.quad _Z24__device_stub__copy_to_yiPfS_i
.size _Z9copy_to_yiPfS_i, 8
.type _Z21calc_reduce_meanshiftiPfS_S_,@object # @_Z21calc_reduce_meanshiftiPfS_S_
.globl _Z21calc_reduce_meanshiftiPfS_S_
.p2align 3, 0x0
_Z21calc_reduce_meanshiftiPfS_S_:
.quad _Z36__device_stub__calc_reduce_meanshiftiPfS_S_
.size _Z21calc_reduce_meanshiftiPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15calc_meanshift2PfS_S_"
.size .L__unnamed_1, 26
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z18calc_Kernel_MatrixiiPfS_S_i"
.size .L__unnamed_2, 32
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z14kernel_sum_diviPfS_"
.size .L__unnamed_3, 24
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z16kernel_Dvec_multiiPfS_S_i"
.size .L__unnamed_4, 30
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z9copy_to_yiPfS_i"
.size .L__unnamed_5, 19
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_Z21calc_reduce_meanshiftiPfS_S_"
.size .L__unnamed_6, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__calc_meanshift2PfS_S_
.addrsig_sym _Z33__device_stub__calc_Kernel_MatrixiiPfS_S_i
.addrsig_sym _Z29__device_stub__kernel_sum_diviPfS_
.addrsig_sym _Z31__device_stub__kernel_Dvec_multiiPfS_S_i
.addrsig_sym _Z24__device_stub__copy_to_yiPfS_i
.addrsig_sym _Z36__device_stub__calc_reduce_meanshiftiPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15calc_meanshift2PfS_S_
.addrsig_sym _Z18calc_Kernel_MatrixiiPfS_S_i
.addrsig_sym _Z14kernel_sum_diviPfS_
.addrsig_sym _Z16kernel_Dvec_multiiPfS_S_i
.addrsig_sym _Z9copy_to_yiPfS_i
.addrsig_sym _Z21calc_reduce_meanshiftiPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c76d3_00000000-6_cuda_meanshift.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10kernel_funff
.type _Z10kernel_funff, @function
_Z10kernel_funff:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z10kernel_funff, .-_Z10kernel_funff
.globl _Z39__device_stub__Z15calc_meanshift2PfS_S_PfS_S_
.type _Z39__device_stub__Z15calc_meanshift2PfS_S_PfS_S_, @function
_Z39__device_stub__Z15calc_meanshift2PfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15calc_meanshift2PfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z39__device_stub__Z15calc_meanshift2PfS_S_PfS_S_, .-_Z39__device_stub__Z15calc_meanshift2PfS_S_PfS_S_
.globl _Z15calc_meanshift2PfS_S_
.type _Z15calc_meanshift2PfS_S_, @function
_Z15calc_meanshift2PfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15calc_meanshift2PfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z15calc_meanshift2PfS_S_, .-_Z15calc_meanshift2PfS_S_
.globl _Z45__device_stub__Z18calc_Kernel_MatrixiiPfS_S_iiiPfS_S_i
.type _Z45__device_stub__Z18calc_Kernel_MatrixiiPfS_S_iiiPfS_S_i, @function
_Z45__device_stub__Z18calc_Kernel_MatrixiiPfS_S_iiiPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18calc_Kernel_MatrixiiPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z45__device_stub__Z18calc_Kernel_MatrixiiPfS_S_iiiPfS_S_i, .-_Z45__device_stub__Z18calc_Kernel_MatrixiiPfS_S_iiiPfS_S_i
.globl _Z18calc_Kernel_MatrixiiPfS_S_i
.type _Z18calc_Kernel_MatrixiiPfS_S_i, @function
_Z18calc_Kernel_MatrixiiPfS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z18calc_Kernel_MatrixiiPfS_S_iiiPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z18calc_Kernel_MatrixiiPfS_S_i, .-_Z18calc_Kernel_MatrixiiPfS_S_i
.globl _Z37__device_stub__Z14kernel_sum_diviPfS_iPfS_
.type _Z37__device_stub__Z14kernel_sum_diviPfS_iPfS_, @function
_Z37__device_stub__Z14kernel_sum_diviPfS_iPfS_:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14kernel_sum_diviPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z37__device_stub__Z14kernel_sum_diviPfS_iPfS_, .-_Z37__device_stub__Z14kernel_sum_diviPfS_iPfS_
.globl _Z14kernel_sum_diviPfS_
.type _Z14kernel_sum_diviPfS_, @function
_Z14kernel_sum_diviPfS_:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z14kernel_sum_diviPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z14kernel_sum_diviPfS_, .-_Z14kernel_sum_diviPfS_
.globl _Z43__device_stub__Z16kernel_Dvec_multiiPfS_S_iiiPfS_S_i
.type _Z43__device_stub__Z16kernel_Dvec_multiiPfS_S_iiiPfS_S_i, @function
_Z43__device_stub__Z16kernel_Dvec_multiiPfS_S_iiiPfS_S_i:
.LFB2088:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16kernel_Dvec_multiiPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z43__device_stub__Z16kernel_Dvec_multiiPfS_S_iiiPfS_S_i, .-_Z43__device_stub__Z16kernel_Dvec_multiiPfS_S_iiiPfS_S_i
.globl _Z16kernel_Dvec_multiiPfS_S_i
.type _Z16kernel_Dvec_multiiPfS_S_i, @function
_Z16kernel_Dvec_multiiPfS_S_i:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z16kernel_Dvec_multiiPfS_S_iiiPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z16kernel_Dvec_multiiPfS_S_i, .-_Z16kernel_Dvec_multiiPfS_S_i
.globl _Z32__device_stub__Z9copy_to_yiPfS_iiPfS_i
.type _Z32__device_stub__Z9copy_to_yiPfS_iiPfS_i, @function
_Z32__device_stub__Z9copy_to_yiPfS_iiPfS_i:
.LFB2090:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 24(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9copy_to_yiPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z32__device_stub__Z9copy_to_yiPfS_iiPfS_i, .-_Z32__device_stub__Z9copy_to_yiPfS_iiPfS_i
.globl _Z9copy_to_yiPfS_i
.type _Z9copy_to_yiPfS_i, @function
_Z9copy_to_yiPfS_i:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9copy_to_yiPfS_iiPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z9copy_to_yiPfS_i, .-_Z9copy_to_yiPfS_i
.globl _Z46__device_stub__Z21calc_reduce_meanshiftiPfS_S_iPfS_S_
.type _Z46__device_stub__Z21calc_reduce_meanshiftiPfS_S_iPfS_S_, @function
_Z46__device_stub__Z21calc_reduce_meanshiftiPfS_S_iPfS_S_:
.LFB2092:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L49
.L45:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L50
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21calc_reduce_meanshiftiPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L45
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2092:
.size _Z46__device_stub__Z21calc_reduce_meanshiftiPfS_S_iPfS_S_, .-_Z46__device_stub__Z21calc_reduce_meanshiftiPfS_S_iPfS_S_
.globl _Z21calc_reduce_meanshiftiPfS_S_
.type _Z21calc_reduce_meanshiftiPfS_S_, @function
_Z21calc_reduce_meanshiftiPfS_S_:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z21calc_reduce_meanshiftiPfS_S_iPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _Z21calc_reduce_meanshiftiPfS_S_, .-_Z21calc_reduce_meanshiftiPfS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z21calc_reduce_meanshiftiPfS_S_"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z9copy_to_yiPfS_i"
.LC2:
.string "_Z16kernel_Dvec_multiiPfS_S_i"
.LC3:
.string "_Z14kernel_sum_diviPfS_"
.section .rodata.str1.8
.align 8
.LC4:
.string "_Z18calc_Kernel_MatrixiiPfS_S_i"
.section .rodata.str1.1
.LC5:
.string "_Z15calc_meanshift2PfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2095:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21calc_reduce_meanshiftiPfS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9copy_to_yiPfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z16kernel_Dvec_multiiPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z14kernel_sum_diviPfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z18calc_Kernel_MatrixiiPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z15calc_meanshift2PfS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_meanshift.hip"
.globl _Z30__device_stub__calc_meanshift2PfS_S_ # -- Begin function _Z30__device_stub__calc_meanshift2PfS_S_
.p2align 4, 0x90
.type _Z30__device_stub__calc_meanshift2PfS_S_,@function
_Z30__device_stub__calc_meanshift2PfS_S_: # @_Z30__device_stub__calc_meanshift2PfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15calc_meanshift2PfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__calc_meanshift2PfS_S_, .Lfunc_end0-_Z30__device_stub__calc_meanshift2PfS_S_
.cfi_endproc
# -- End function
.globl _Z33__device_stub__calc_Kernel_MatrixiiPfS_S_i # -- Begin function _Z33__device_stub__calc_Kernel_MatrixiiPfS_S_i
.p2align 4, 0x90
.type _Z33__device_stub__calc_Kernel_MatrixiiPfS_S_i,@function
_Z33__device_stub__calc_Kernel_MatrixiiPfS_S_i: # @_Z33__device_stub__calc_Kernel_MatrixiiPfS_S_i
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movl %r9d, 12(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18calc_Kernel_MatrixiiPfS_S_i, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z33__device_stub__calc_Kernel_MatrixiiPfS_S_i, .Lfunc_end1-_Z33__device_stub__calc_Kernel_MatrixiiPfS_S_i
.cfi_endproc
# -- End function
.globl _Z29__device_stub__kernel_sum_diviPfS_ # -- Begin function _Z29__device_stub__kernel_sum_diviPfS_
.p2align 4, 0x90
.type _Z29__device_stub__kernel_sum_diviPfS_,@function
_Z29__device_stub__kernel_sum_diviPfS_: # @_Z29__device_stub__kernel_sum_diviPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14kernel_sum_diviPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z29__device_stub__kernel_sum_diviPfS_, .Lfunc_end2-_Z29__device_stub__kernel_sum_diviPfS_
.cfi_endproc
# -- End function
.globl _Z31__device_stub__kernel_Dvec_multiiPfS_S_i # -- Begin function _Z31__device_stub__kernel_Dvec_multiiPfS_S_i
.p2align 4, 0x90
.type _Z31__device_stub__kernel_Dvec_multiiPfS_S_i,@function
_Z31__device_stub__kernel_Dvec_multiiPfS_S_i: # @_Z31__device_stub__kernel_Dvec_multiiPfS_S_i
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movl %r9d, 12(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16kernel_Dvec_multiiPfS_S_i, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end3:
.size _Z31__device_stub__kernel_Dvec_multiiPfS_S_i, .Lfunc_end3-_Z31__device_stub__kernel_Dvec_multiiPfS_S_i
.cfi_endproc
# -- End function
.globl _Z24__device_stub__copy_to_yiPfS_i # -- Begin function _Z24__device_stub__copy_to_yiPfS_i
.p2align 4, 0x90
.type _Z24__device_stub__copy_to_yiPfS_i,@function
_Z24__device_stub__copy_to_yiPfS_i: # @_Z24__device_stub__copy_to_yiPfS_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9copy_to_yiPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z24__device_stub__copy_to_yiPfS_i, .Lfunc_end4-_Z24__device_stub__copy_to_yiPfS_i
.cfi_endproc
# -- End function
.globl _Z36__device_stub__calc_reduce_meanshiftiPfS_S_ # -- Begin function _Z36__device_stub__calc_reduce_meanshiftiPfS_S_
.p2align 4, 0x90
.type _Z36__device_stub__calc_reduce_meanshiftiPfS_S_,@function
_Z36__device_stub__calc_reduce_meanshiftiPfS_S_: # @_Z36__device_stub__calc_reduce_meanshiftiPfS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21calc_reduce_meanshiftiPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end5:
.size _Z36__device_stub__calc_reduce_meanshiftiPfS_S_, .Lfunc_end5-_Z36__device_stub__calc_reduce_meanshiftiPfS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15calc_meanshift2PfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18calc_Kernel_MatrixiiPfS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14kernel_sum_diviPfS_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16kernel_Dvec_multiiPfS_S_i, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9copy_to_yiPfS_i, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21calc_reduce_meanshiftiPfS_S_, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15calc_meanshift2PfS_S_,@object # @_Z15calc_meanshift2PfS_S_
.section .rodata,"a",@progbits
.globl _Z15calc_meanshift2PfS_S_
.p2align 3, 0x0
_Z15calc_meanshift2PfS_S_:
.quad _Z30__device_stub__calc_meanshift2PfS_S_
.size _Z15calc_meanshift2PfS_S_, 8
.type _Z18calc_Kernel_MatrixiiPfS_S_i,@object # @_Z18calc_Kernel_MatrixiiPfS_S_i
.globl _Z18calc_Kernel_MatrixiiPfS_S_i
.p2align 3, 0x0
_Z18calc_Kernel_MatrixiiPfS_S_i:
.quad _Z33__device_stub__calc_Kernel_MatrixiiPfS_S_i
.size _Z18calc_Kernel_MatrixiiPfS_S_i, 8
.type _Z14kernel_sum_diviPfS_,@object # @_Z14kernel_sum_diviPfS_
.globl _Z14kernel_sum_diviPfS_
.p2align 3, 0x0
_Z14kernel_sum_diviPfS_:
.quad _Z29__device_stub__kernel_sum_diviPfS_
.size _Z14kernel_sum_diviPfS_, 8
.type _Z16kernel_Dvec_multiiPfS_S_i,@object # @_Z16kernel_Dvec_multiiPfS_S_i
.globl _Z16kernel_Dvec_multiiPfS_S_i
.p2align 3, 0x0
_Z16kernel_Dvec_multiiPfS_S_i:
.quad _Z31__device_stub__kernel_Dvec_multiiPfS_S_i
.size _Z16kernel_Dvec_multiiPfS_S_i, 8
.type _Z9copy_to_yiPfS_i,@object # @_Z9copy_to_yiPfS_i
.globl _Z9copy_to_yiPfS_i
.p2align 3, 0x0
_Z9copy_to_yiPfS_i:
.quad _Z24__device_stub__copy_to_yiPfS_i
.size _Z9copy_to_yiPfS_i, 8
.type _Z21calc_reduce_meanshiftiPfS_S_,@object # @_Z21calc_reduce_meanshiftiPfS_S_
.globl _Z21calc_reduce_meanshiftiPfS_S_
.p2align 3, 0x0
_Z21calc_reduce_meanshiftiPfS_S_:
.quad _Z36__device_stub__calc_reduce_meanshiftiPfS_S_
.size _Z21calc_reduce_meanshiftiPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15calc_meanshift2PfS_S_"
.size .L__unnamed_1, 26
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z18calc_Kernel_MatrixiiPfS_S_i"
.size .L__unnamed_2, 32
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z14kernel_sum_diviPfS_"
.size .L__unnamed_3, 24
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z16kernel_Dvec_multiiPfS_S_i"
.size .L__unnamed_4, 30
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z9copy_to_yiPfS_i"
.size .L__unnamed_5, 19
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_Z21calc_reduce_meanshiftiPfS_S_"
.size .L__unnamed_6, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__calc_meanshift2PfS_S_
.addrsig_sym _Z33__device_stub__calc_Kernel_MatrixiiPfS_S_i
.addrsig_sym _Z29__device_stub__kernel_sum_diviPfS_
.addrsig_sym _Z31__device_stub__kernel_Dvec_multiiPfS_S_i
.addrsig_sym _Z24__device_stub__copy_to_yiPfS_i
.addrsig_sym _Z36__device_stub__calc_reduce_meanshiftiPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15calc_meanshift2PfS_S_
.addrsig_sym _Z18calc_Kernel_MatrixiiPfS_S_i
.addrsig_sym _Z14kernel_sum_diviPfS_
.addrsig_sym _Z16kernel_Dvec_multiiPfS_S_i
.addrsig_sym _Z9copy_to_yiPfS_i
.addrsig_sym _Z21calc_reduce_meanshiftiPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // includes
#include <stdio.h>
#include <stdlib.h>
//matriz de vecinos
void liberaVecinos(int *vec) {
free(vec);
return;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // includes
#include <stdio.h>
#include <stdlib.h>
//matriz de vecinos
void liberaVecinos(int *vec) {
free(vec);
return;
} | .file "tmpxft_0005107a_00000000-6_libera_vecinos.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13liberaVecinosPi
.type _Z13liberaVecinosPi, @function
_Z13liberaVecinosPi:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call free@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z13liberaVecinosPi, .-_Z13liberaVecinosPi
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // includes
#include <stdio.h>
#include <stdlib.h>
//matriz de vecinos
void liberaVecinos(int *vec) {
free(vec);
return;
} | // includes
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
//matriz de vecinos
void liberaVecinos(int *vec) {
free(vec);
return;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // includes
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
//matriz de vecinos
void liberaVecinos(int *vec) {
free(vec);
return;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // includes
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
//matriz de vecinos
void liberaVecinos(int *vec) {
free(vec);
return;
} | .text
.file "libera_vecinos.hip"
.globl _Z13liberaVecinosPi # -- Begin function _Z13liberaVecinosPi
.p2align 4, 0x90
.type _Z13liberaVecinosPi,@function
_Z13liberaVecinosPi: # @_Z13liberaVecinosPi
.cfi_startproc
# %bb.0:
jmp free # TAILCALL
.Lfunc_end0:
.size _Z13liberaVecinosPi, .Lfunc_end0-_Z13liberaVecinosPi
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005107a_00000000-6_libera_vecinos.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13liberaVecinosPi
.type _Z13liberaVecinosPi, @function
_Z13liberaVecinosPi:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call free@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z13liberaVecinosPi, .-_Z13liberaVecinosPi
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "libera_vecinos.hip"
.globl _Z13liberaVecinosPi # -- Begin function _Z13liberaVecinosPi
.p2align 4, 0x90
.type _Z13liberaVecinosPi,@function
_Z13liberaVecinosPi: # @_Z13liberaVecinosPi
.cfi_startproc
# %bb.0:
jmp free # TAILCALL
.Lfunc_end0:
.size _Z13liberaVecinosPi, .Lfunc_end0-_Z13liberaVecinosPi
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /***************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
***************************************************************************/
#include "common.h"
__global__ void block2D_hybrid_coarsen_x(float c0,float c1,float *A0,float *Anext, int nx, int ny, int nz)
{
//thread coarsening along x direction
const int i = blockIdx.x*blockDim.x*2+threadIdx.x;
const int i2= blockIdx.x*blockDim.x*2+threadIdx.x+blockDim.x;
const int j = blockIdx.y*blockDim.y+threadIdx.y;
const int sh_id=threadIdx.x + threadIdx.y*blockDim.x*2;
const int sh_id2=threadIdx.x +blockDim.x+ threadIdx.y*blockDim.x*2;
//shared memeory
extern __shared__ float sh_A0[];
sh_A0[sh_id]=0.0f;
sh_A0[sh_id2]=0.0f;
__syncthreads();
//get available region for load and store
const bool w_region = i>0 && j>0 &&(i<nx-1) &&(j<ny-1) ;
const bool w_region2 = j>0 &&(i2<nx-1) &&(j<ny-1) ;
const bool x_l_bound = (threadIdx.x==0);
const bool x_h_bound = ((threadIdx.x+blockDim.x)==(blockDim.x*2-1));
const bool y_l_bound = (threadIdx.y==0);
const bool y_h_bound = (threadIdx.y==(blockDim.y-1));
//register for bottom and top planes
//because of thread coarsening, we need to doulbe registers
float bottom=0.0f,bottom2=0.0f,top=0.0f,top2=0.0f;
//load data for bottom and current
if((i<nx) &&(j<ny))
{
bottom=A0[Index3D (nx, ny, i, j, 0)];
sh_A0[sh_id]=A0[Index3D (nx, ny, i, j, 1)];
}
if((i2<nx) &&(j<ny))
{
bottom2=A0[Index3D (nx, ny, i2, j, 0)];
sh_A0[sh_id2]=A0[Index3D (nx, ny, i2, j, 1)];
}
__syncthreads();
for(int k=1;k<nz-1;k++)
{
float a_left_right,a_top,a_down;
//load required data on xy planes
//if it on shared memory, load from shared memory
//if not, load from global memory
if((i<nx) &&(j<ny))
top=A0[Index3D (nx, ny, i, j, k+1)];
if(w_region)
{
a_left_right=x_l_bound?A0[Index3D (nx, ny, i-1, j, k )]:sh_A0[sh_id-1];
a_down=y_l_bound?A0[Index3D (nx, ny, i, j-1, k )]:sh_A0[sh_id-2*blockDim.x];
a_top=y_h_bound?A0[Index3D (nx, ny, i, j+1, k )]:sh_A0[sh_id+2*blockDim.x];
Anext[Index3D (nx, ny, i, j, k)] = (a_left_right + sh_A0[sh_id+1] + a_top + a_down
+ top + bottom)*c1 - sh_A0[sh_id]*c0 ;
}
//load another block
if((i2<nx) &&(j<ny))
top2=A0[Index3D (nx, ny, i2, j, k+1)];
if(w_region2)
{
a_left_right=x_h_bound?A0[Index3D (nx, ny, i2+1, j, k )]:sh_A0[sh_id2+1];
a_down=y_l_bound?A0[Index3D (nx, ny, i2, j-1, k )]:sh_A0[sh_id2-2*blockDim.x];
a_top=y_h_bound?A0[Index3D (nx, ny, i2, j+1, k )]:sh_A0[sh_id2+2*blockDim.x];
Anext[Index3D (nx, ny, i2, j, k)] = (a_left_right + sh_A0[sh_id2-1] + a_top + a_down + top2
+bottom2)*c1 - sh_A0[sh_id2]*c0;
}
//swap data
__syncthreads();
bottom=sh_A0[sh_id];
sh_A0[sh_id]=top;
bottom2=sh_A0[sh_id2];
sh_A0[sh_id2]=top2;
__syncthreads();
}
} | code for sm_80
Function : _Z24block2D_hybrid_coarsen_xffPfS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0020*/ MOV R13, c[0x0][0x0] ; /* 0x00000000000d7a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R21, SR_CTAID.Y ; /* 0x0000000000157919 */
/* 0x000e220000002600 */
/*0050*/ SHF.L.U32 R15, R13, 0x1, RZ ; /* 0x000000010d0f7819 */
/* 0x000fc600000006ff */
/*0060*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e680000002100 */
/*0070*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */
/* 0x000ea20000002500 */
/*0080*/ IMAD R12, R21, c[0x0][0x4], R0 ; /* 0x00000100150c7a24 */
/* 0x001fe200078e0200 */
/*0090*/ IADD3 R14, R3, c[0x0][0x0], RZ ; /* 0x00000000030e7a10 */
/* 0x002fe20007ffe0ff */
/*00a0*/ IMAD R2, R15, R0, R3 ; /* 0x000000000f027224 */
/* 0x000fc600078e0203 */
/*00b0*/ ISETP.GE.AND P0, PT, R12, c[0x0][0x17c], PT ; /* 0x00005f000c007a0c */
/* 0x000fe20003f06270 */
/*00c0*/ IMAD R11, R15, R10, R3 ; /* 0x0000000a0f0b7224 */
/* 0x004fe200078e0203 */
/*00d0*/ STS [R2.X4], RZ ; /* 0x000000ff02007388 */
/* 0x0001e80000004800 */
/*00e0*/ ISETP.LT.AND P3, PT, R11.reuse, c[0x0][0x178], !P0 ; /* 0x00005e000b007a0c */
/* 0x040fe40004761270 */
/*00f0*/ IADD3 R23, R11, c[0x0][0x0], RZ ; /* 0x000000000b177a10 */
/* 0x000fc80007ffe0ff */
/*0100*/ ISETP.LT.AND P0, PT, R23, c[0x0][0x178], !P0 ; /* 0x00005e0017007a0c */
/* 0x000fce0004701270 */
/*0110*/ @P3 IADD3 R4, R12, c[0x0][0x17c], RZ ; /* 0x00005f000c043a10 */
/* 0x000fe40007ffe0ff */
/*0120*/ @P3 MOV R7, 0x4 ; /* 0x0000000400073802 */
/* 0x000fc60000000f00 */
/*0130*/ @P3 IMAD R18, R4, c[0x0][0x178], R11 ; /* 0x00005e0004123a24 */
/* 0x000fe200078e020b */
/*0140*/ @P0 IADD3 R16, R12, c[0x0][0x17c], RZ ; /* 0x00005f000c100a10 */
/* 0x000fe20007ffe0ff */
/*0150*/ IMAD R4, R15, R0, R14 ; /* 0x000000000f047224 */
/* 0x000fe200078e020e */
/*0160*/ @P0 MOV R9, 0x4 ; /* 0x0000000400090802 */
/* 0x000fe20000000f00 */
/*0170*/ @P3 IMAD.WIDE R18, R18, R7, c[0x0][0x168] ; /* 0x00005a0012123625 */
/* 0x000fc600078e0207 */
/*0180*/ STS [R4.X4], RZ ; /* 0x000000ff04007388 */
/* 0x0001e20000004800 */
/*0190*/ @P0 IMAD R16, R16, c[0x0][0x178], R23 ; /* 0x00005e0010100a24 */
/* 0x000fc600078e0217 */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01b0*/ @P0 IMAD.WIDE R16, R16, R9, c[0x0][0x168] ; /* 0x00005a0010100625 */
/* 0x000fca00078e0209 */
/*01c0*/ @P3 LDG.E R19, [R18.64] ; /* 0x0000000812133981 */
/* 0x000ea8000c1e1900 */
/*01d0*/ @P0 LDG.E R17, [R16.64] ; /* 0x0000000810110981 */
/* 0x000ee2000c1e1900 */
/*01e0*/ HFMA2.MMA R26, -RZ, RZ, 0, 0 ; /* 0x00000000ff1a7435 */
/* 0x000fe200000001ff */
/*01f0*/ @P3 IMAD R6, R12.reuse, c[0x0][0x178], R11 ; /* 0x00005e000c063a24 */
/* 0x040fe200078e020b */
/*0200*/ MOV R5, RZ ; /* 0x000000ff00057202 */
/* 0x000fe20000000f00 */
/*0210*/ @P0 IMAD R8, R12, c[0x0][0x178], R23 ; /* 0x00005e000c080a24 */
/* 0x000fe400078e0217 */
/*0220*/ @P3 IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006063625 */
/* 0x000fc800078e0207 */
/*0230*/ @P0 IMAD.WIDE R8, R8, R9, c[0x0][0x168] ; /* 0x00005a0008080625 */
/* 0x000fe200078e0209 */
/*0240*/ @P3 LDG.E R26, [R6.64] ; /* 0x00000008061a3981 */
/* 0x000168000c1e1900 */
/*0250*/ @P0 LDG.E R5, [R8.64] ; /* 0x0000000808050981 */
/* 0x000162000c1e1900 */
/*0260*/ MOV R22, c[0x0][0x180] ; /* 0x0000600000167a02 */
/* 0x000fc80000000f00 */
/*0270*/ ISETP.GE.AND P1, PT, R22, 0x3, PT ; /* 0x000000031600780c */
/* 0x000fe20003f26270 */
/*0280*/ @P3 STS [R2.X4], R19 ; /* 0x0000001302003388 */
/* 0x0041e80000004800 */
/*0290*/ @P0 STS [R4.X4], R17 ; /* 0x0000001104000388 */
/* 0x0081e80000004800 */
/*02a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02b0*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*02c0*/ UMOV UR6, 0x1 ; /* 0x0000000100067882 */
/* 0x001fe20000000000 */
/*02d0*/ ISETP.GT.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f24270 */
/*02e0*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000a00 */
/*02f0*/ IADD3 R7, R15, -0x1, RZ ; /* 0xffffffff0f077810 */
/* 0x000fe20007ffe0ff */
/*0300*/ UIADD3 UR4, -UR6, UR4, URZ ; /* 0x0000000406047290 */
/* 0x000fe2000fffe13f */
/*0310*/ IADD3 R6, R0, c[0x0][0x17c], RZ ; /* 0x00005f0000067a10 */
/* 0x000fe20007ffe0ff */
/*0320*/ UIADD3 UR5, -UR6, UR5, URZ ; /* 0x0000000506057290 */
/* 0x000fe2000fffe13f */
/*0330*/ MOV R9, c[0x0][0x17c] ; /* 0x00005f0000097a02 */
/* 0x000fc40000000f00 */
/*0340*/ ISETP.NE.AND P4, PT, R14, R7, PT ; /* 0x000000070e00720c */
/* 0x000fe20003f85270 */
/*0350*/ IMAD R14, R21, c[0x0][0x4], R6 ; /* 0x00000100150e7a24 */
/* 0x000fe200078e0206 */
/*0360*/ ISETP.LT.AND P2, PT, R23, UR4, P1 ; /* 0x0000000417007c0c */
/* 0x000fe40008f41270 */
/*0370*/ ISETP.GT.AND P1, PT, R11, RZ, P1 ; /* 0x000000ff0b00720c */
/* 0x000fe40000f24270 */
/*0380*/ SHF.L.U32 R8, R4, 0x2, RZ ; /* 0x0000000204087819 */
/* 0x000fe400000006ff */
/*0390*/ LEA R18, R9, R12, 0x1 ; /* 0x0000000c09127211 */
/* 0x000fe200078e08ff */
/*03a0*/ IMAD R9, R14, c[0x0][0x178], R11.reuse ; /* 0x00005e000e097a24 */
/* 0x100fe200078e020b */
/*03b0*/ ISETP.LT.AND P5, PT, R11, UR4, P1 ; /* 0x000000040b007c0c */
/* 0x000fe20008fa1270 */
/*03c0*/ ULDC UR4, c[0x0][0x4] ; /* 0x0000010000047ab9 */
/* 0x000fe20000000800 */
/*03d0*/ LEA R7, R13, R8, 0x3 ; /* 0x000000080d077211 */
/* 0x000fe200078e18ff */
/*03e0*/ IMAD R8, R18, c[0x0][0x178], R11 ; /* 0x00005e0012087a24 */
/* 0x000fe200078e020b */
/*03f0*/ ISETP.LT.AND P1, PT, R12, UR5, P2 ; /* 0x000000050c007c0c */
/* 0x000fe20009721270 */
/*0400*/ IMAD R17, R18, c[0x0][0x178], R3 ; /* 0x00005e0012117a24 */
/* 0x000fe200078e0203 */
/*0410*/ ISETP.LT.AND P2, PT, R12, UR5, P5 ; /* 0x000000050c007c0c */
/* 0x000fe2000af41270 */
/*0420*/ UIADD3 UR4, -UR6, UR4, URZ ; /* 0x0000000406047290 */
/* 0x000fe2000fffe13f */
/*0430*/ SHF.L.U32 R6, R2, 0x2, RZ ; /* 0x0000000202067819 */
/* 0x000fe200000006ff */
/*0440*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe20000000000 */
/*0450*/ IADD3 R12, R14, -0x1, RZ ; /* 0xffffffff0e0c7810 */
/* 0x000fc40007ffe0ff */
/*0460*/ IADD3 R18, R14.reuse, 0x1, RZ ; /* 0x000000010e127810 */
/* 0x040fe40007ffe0ff */
/*0470*/ LEA R6, R13, R6, 0x3 ; /* 0x000000060d067211 */
/* 0x000fe200078e18ff */
/*0480*/ IMAD R13, R14, c[0x0][0x178], R3.reuse ; /* 0x00005e000e0d7a24 */
/* 0x100fe200078e0203 */
/*0490*/ LEA R16, R10, 0x1, 0x1 ; /* 0x000000010a107811 */
/* 0x000fe200078e08ff */
/*04a0*/ IMAD R19, R12, c[0x0][0x178], R3.reuse ; /* 0x00005e000c137a24 */
/* 0x100fe200078e0203 */
/*04b0*/ IADD3 R22, R22, -0x1, RZ ; /* 0xffffffff16167810 */
/* 0x000fe20007ffe0ff */
/*04c0*/ IMAD R21, R18, c[0x0][0x178], R3 ; /* 0x00005e0012157a24 */
/* 0x000fe200078e0203 */
/*04d0*/ IADD3 R23, -R15.reuse, R2, RZ ; /* 0x000000020f177210 */
/* 0x040fe20007ffe1ff */
/*04e0*/ IMAD R10, R12, c[0x0][0x178], R11.reuse ; /* 0x00005e000c0a7a24 */
/* 0x100fe200078e020b */
/*04f0*/ IADD3 R24, -R15, R4, RZ ; /* 0x000000040f187210 */
/* 0x000fe20007ffe1ff */
/*0500*/ IMAD R11, R18, c[0x0][0x178], R11 ; /* 0x00005e00120b7a24 */
/* 0x000fe200078e020b */
/*0510*/ MOV R25, RZ ; /* 0x000000ff00197202 */
/* 0x000fe20000000f00 */
/*0520*/ IMAD R12, R16.reuse, c[0x0][0x0], R17 ; /* 0x00000000100c7a24 */
/* 0x040fe200078e0211 */
/*0530*/ MOV R27, RZ ; /* 0x000000ff001b7202 */
/* 0x000fe20000000f00 */
/*0540*/ IMAD R13, R16, c[0x0][0x0], R13 ; /* 0x00000000100d7a24 */
/* 0x000fc400078e020d */
/*0550*/ IMAD R20, R16.reuse, c[0x0][0x0], R19 ; /* 0x0000000010147a24 */
/* 0x040fe400078e0213 */
/*0560*/ IMAD R21, R16, c[0x0][0x0], R21 ; /* 0x0000000010157a24 */
/* 0x000fe400078e0215 */
/*0570*/ @P3 MOV R15, 0x4 ; /* 0x00000004000f3802 */
/* 0x000fca0000000f00 */
/*0580*/ @P3 IMAD.WIDE R14, R8, R15, c[0x0][0x168] ; /* 0x00005a00080e3625 */
/* 0x000fca00078e020f */
/*0590*/ @P3 LDG.E R27, [R14.64] ; /* 0x000000080e1b3981 */
/* 0x020162000c1e1900 */
/*05a0*/ BSSY B0, 0x760 ; /* 0x000001b000007945 */
/* 0x000fe20003800000 */
/*05b0*/ @!P2 BRA 0x750 ; /* 0x000001900000a947 */
/* 0x006fea0003800000 */
/*05c0*/ ISETP.NE.AND P5, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003fa5270 */
/*05d0*/ HFMA2.MMA R28, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff1c7435 */
/* 0x000fe200000001ff */
/*05e0*/ LDS R15, [R2.X4+0x4] ; /* 0x00000400020f7984 */
/* 0x001ff60000004800 */
/*05f0*/ @P5 LDS R14, [R2.X4+-0x4] ; /* 0xfffffc00020e5984 */
/* 0x000e220000004800 */
/*0600*/ @!P5 IADD3 R19, R9, -0x1, RZ ; /* 0xffffffff0913d810 */
/* 0x000fca0007ffe0ff */
/*0610*/ @!P5 IMAD.WIDE R18, R19, R28, c[0x0][0x168] ; /* 0x00005a001312d625 */
/* 0x000fca00078e021c */
/*0620*/ @!P5 LDG.E R14, [R18.64] ; /* 0x00000008120ed981 */
/* 0x000e22000c1e1900 */
/*0630*/ ISETP.NE.AND P5, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bfa5270 */
/*0640*/ @P5 LDS R16, [R6] ; /* 0x0000000006105984 */
/* 0x000e620000000800 */
/*0650*/ FADD R17, R15, R14 ; /* 0x0000000e0f117221 */
/* 0x001fe40000000000 */
/*0660*/ @!P5 IMAD.WIDE R14, R11, R28, c[0x0][0x168] ; /* 0x00005a000b0ed625 */
/* 0x000fca00078e021c */
/*0670*/ @!P5 LDG.E R16, [R14.64] ; /* 0x000000080e10d981 */
/* 0x000062000c1e1900 */
/*0680*/ ISETP.NE.AND P5, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc60003fa5270 */
/*0690*/ LDS R15, [R2.X4] ; /* 0x00000000020f7984 */
/* 0x001ff40000004800 */
/*06a0*/ @P5 LDS R29, [R23.X4] ; /* 0x00000000171d5984 */
/* 0x000e220000004800 */
/*06b0*/ FADD R14, R17, R16 ; /* 0x00000010110e7221 */
/* 0x002fc40000000000 */
/*06c0*/ @!P5 IMAD.WIDE R16, R10, R28, c[0x0][0x168] ; /* 0x00005a000a10d625 */
/* 0x000fca00078e021c */
/*06d0*/ @!P5 LDG.E R29, [R16.64] ; /* 0x00000008101dd981 */
/* 0x000e24000c1e1900 */
/*06e0*/ FADD R18, R14, R29 ; /* 0x0000001d0e127221 */
/* 0x001fc80000000000 */
/*06f0*/ FADD R19, R27, R18 ; /* 0x000000121b137221 */
/* 0x020fe40000000000 */
/*0700*/ FMUL R18, R15, c[0x0][0x160] ; /* 0x000058000f127a20 */
/* 0x000fe40000400000 */
/*0710*/ FADD R19, R19, R26 ; /* 0x0000001a13137221 */
/* 0x000fe40000000000 */
/*0720*/ IMAD.WIDE R14, R9, R28, c[0x0][0x170] ; /* 0x00005c00090e7625 */
/* 0x000fc800078e021c */
/*0730*/ FFMA R19, R19, c[0x0][0x164], -R18 ; /* 0x0000590013137a23 */
/* 0x000fca0000000812 */
/*0740*/ STG.E [R14.64], R19 ; /* 0x000000130e007986 */
/* 0x0001e4000c101908 */
/*0750*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0760*/ BSSY B0, 0x7c0 ; /* 0x0000005000007945 */
/* 0x000fe20003800000 */
/*0770*/ @!P0 BRA 0x7b0 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0780*/ MOV R15, 0x4 ; /* 0x00000004000f7802 */
/* 0x001fca0000000f00 */
/*0790*/ IMAD.WIDE R14, R12, R15, c[0x0][0x168] ; /* 0x00005a000c0e7625 */
/* 0x000fca00078e020f */
/*07a0*/ LDG.E R25, [R14.64] ; /* 0x000000080e197981 */
/* 0x000164000c1e1900 */
/*07b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07c0*/ BSSY B0, 0x970 ; /* 0x000001a000007945 */
/* 0x000fe20003800000 */
/*07d0*/ @!P1 BRA 0x960 ; /* 0x0000018000009947 */
/* 0x000fea0003800000 */
/*07e0*/ @P4 LDS R18, [R4.X4+0x4] ; /* 0x0000040004124984 */
/* 0x000fe20000004800 */
/*07f0*/ HFMA2.MMA R26, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff1a7435 */
/* 0x000fe200000001ff */
/*0800*/ @!P4 IADD3 R15, R13, 0x1, RZ ; /* 0x000000010d0fc810 */
/* 0x001fe40007ffe0ff */
/*0810*/ ISETP.NE.AND P6, PT, R0.reuse, UR4, PT ; /* 0x0000000400007c0c */
/* 0x040fe2000bfc5270 */
/*0820*/ LDS R19, [R4.X4+-0x4] ; /* 0xfffffc0004137984 */
/* 0x000e2c0000004800 */
/*0830*/ @!P4 IMAD.WIDE R14, R15, R26, c[0x0][0x168] ; /* 0x00005a000f0ec625 */
/* 0x000fe200078e021a */
/*0840*/ ISETP.NE.AND P5, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fca0003fa5270 */
/*0850*/ @P6 LDS R28, [R7] ; /* 0x00000000071c6984 */
/* 0x000e700000000800 */
/*0860*/ @P5 LDS R29, [R24.X4] ; /* 0x00000000181d5984 */
/* 0x000ea80000004800 */
/*0870*/ @!P4 LDG.E R18, [R14.64] ; /* 0x000000080e12c981 */
/* 0x000622000c1e1900 */
/*0880*/ @!P6 IMAD.WIDE R16, R21, R26, c[0x0][0x168] ; /* 0x00005a001510e625 */
/* 0x000fc600078e021a */
/*0890*/ LDS R14, [R4.X4] ; /* 0x00000000040e7984 */
/* 0x008ee80000004800 */
/*08a0*/ @!P6 LDG.E R28, [R16.64] ; /* 0x00000008101ce981 */
/* 0x000e62000c1e1900 */
/*08b0*/ FADD R15, R19, R18 ; /* 0x00000012130f7221 */
/* 0x001fe40000000000 */
/*08c0*/ @!P5 IMAD.WIDE R18, R20, R26, c[0x0][0x168] ; /* 0x00005a001412d625 */
/* 0x000fca00078e021a */
/*08d0*/ @!P5 LDG.E R29, [R18.64] ; /* 0x00000008121dd981 */
/* 0x000ea2000c1e1900 */
/*08e0*/ FADD R28, R15, R28 ; /* 0x0000001c0f1c7221 */
/* 0x002fc80000000000 */
/*08f0*/ FADD R28, R28, R29 ; /* 0x0000001d1c1c7221 */
/* 0x004fe40000000000 */
/*0900*/ FMUL R29, R14, c[0x0][0x160] ; /* 0x000058000e1d7a20 */
/* 0x008fe40000400000 */
/*0910*/ FADD R28, R25, R28 ; /* 0x0000001c191c7221 */
/* 0x020fe40000000000 */
/*0920*/ IMAD.WIDE R14, R13, R26, c[0x0][0x170] ; /* 0x00005c000d0e7625 */
/* 0x000fc800078e021a */
/*0930*/ FADD R5, R28, R5 ; /* 0x000000051c057221 */
/* 0x000fc80000000000 */
/*0940*/ FFMA R5, R5, c[0x0][0x164], -R29 ; /* 0x0000590005057a23 */
/* 0x000fca000000081d */
/*0950*/ STG.E [R14.64], R5 ; /* 0x000000050e007986 */
/* 0x0001e4000c101908 */
/*0960*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0970*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0980*/ UIADD3 UR5, UR5, 0x1, URZ ; /* 0x0000000105057890 */
/* 0x000fe2000fffe03f */
/*0990*/ MOV R14, c[0x0][0x17c] ; /* 0x00005f00000e7a02 */
/* 0x001fca0000000f00 */
/*09a0*/ ISETP.LE.AND P5, PT, R22, UR5, PT ; /* 0x0000000516007c0c */
/* 0x000fe2000bfa3270 */
/*09b0*/ IMAD R13, R14.reuse, c[0x0][0x178], R13 ; /* 0x00005e000e0d7a24 */
/* 0x040fe400078e020d */
/*09c0*/ IMAD R9, R14.reuse, c[0x0][0x178], R9 ; /* 0x00005e000e097a24 */
/* 0x040fe400078e0209 */
/*09d0*/ IMAD R8, R14.reuse, c[0x0][0x178], R8 ; /* 0x00005e000e087a24 */
/* 0x040fe400078e0208 */
/*09e0*/ IMAD R12, R14.reuse, c[0x0][0x178], R12 ; /* 0x00005e000e0c7a24 */
/* 0x040fe400078e020c */
/*09f0*/ IMAD R10, R14.reuse, c[0x0][0x178], R10 ; /* 0x00005e000e0a7a24 */
/* 0x040fe400078e020a */
/*0a00*/ IMAD R11, R14, c[0x0][0x178], R11 ; /* 0x00005e000e0b7a24 */
/* 0x000fc400078e020b */
/*0a10*/ IMAD R20, R14.reuse, c[0x0][0x178], R20 ; /* 0x00005e000e147a24 */
/* 0x040fe400078e0214 */
/*0a20*/ IMAD R21, R14, c[0x0][0x178], R21 ; /* 0x00005e000e157a24 */
/* 0x000fe200078e0215 */
/*0a30*/ LDS R26, [R2.X4] ; /* 0x00000000021a7984 */
/* 0x0000680000004800 */
/*0a40*/ STS [R2.X4], R27 ; /* 0x0000001b02007388 */
/* 0x0201e80000004800 */
/*0a50*/ LDS R5, [R4.X4] ; /* 0x0000000004057984 */
/* 0x0000a80000004800 */
/*0a60*/ STS [R4.X4], R25 ; /* 0x0000001904007388 */
/* 0x0001e80000004800 */
/*0a70*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0a80*/ @!P5 BRA 0x570 ; /* 0xfffffae00000d947 */
/* 0x001fea000383ffff */
/*0a90*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0aa0*/ BRA 0xaa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /***************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
***************************************************************************/
#include "common.h"
__global__ void block2D_hybrid_coarsen_x(float c0,float c1,float *A0,float *Anext, int nx, int ny, int nz)
{
//thread coarsening along x direction
const int i = blockIdx.x*blockDim.x*2+threadIdx.x;
const int i2= blockIdx.x*blockDim.x*2+threadIdx.x+blockDim.x;
const int j = blockIdx.y*blockDim.y+threadIdx.y;
const int sh_id=threadIdx.x + threadIdx.y*blockDim.x*2;
const int sh_id2=threadIdx.x +blockDim.x+ threadIdx.y*blockDim.x*2;
//shared memeory
extern __shared__ float sh_A0[];
sh_A0[sh_id]=0.0f;
sh_A0[sh_id2]=0.0f;
__syncthreads();
//get available region for load and store
const bool w_region = i>0 && j>0 &&(i<nx-1) &&(j<ny-1) ;
const bool w_region2 = j>0 &&(i2<nx-1) &&(j<ny-1) ;
const bool x_l_bound = (threadIdx.x==0);
const bool x_h_bound = ((threadIdx.x+blockDim.x)==(blockDim.x*2-1));
const bool y_l_bound = (threadIdx.y==0);
const bool y_h_bound = (threadIdx.y==(blockDim.y-1));
//register for bottom and top planes
//because of thread coarsening, we need to doulbe registers
float bottom=0.0f,bottom2=0.0f,top=0.0f,top2=0.0f;
//load data for bottom and current
if((i<nx) &&(j<ny))
{
bottom=A0[Index3D (nx, ny, i, j, 0)];
sh_A0[sh_id]=A0[Index3D (nx, ny, i, j, 1)];
}
if((i2<nx) &&(j<ny))
{
bottom2=A0[Index3D (nx, ny, i2, j, 0)];
sh_A0[sh_id2]=A0[Index3D (nx, ny, i2, j, 1)];
}
__syncthreads();
for(int k=1;k<nz-1;k++)
{
float a_left_right,a_top,a_down;
//load required data on xy planes
//if it on shared memory, load from shared memory
//if not, load from global memory
if((i<nx) &&(j<ny))
top=A0[Index3D (nx, ny, i, j, k+1)];
if(w_region)
{
a_left_right=x_l_bound?A0[Index3D (nx, ny, i-1, j, k )]:sh_A0[sh_id-1];
a_down=y_l_bound?A0[Index3D (nx, ny, i, j-1, k )]:sh_A0[sh_id-2*blockDim.x];
a_top=y_h_bound?A0[Index3D (nx, ny, i, j+1, k )]:sh_A0[sh_id+2*blockDim.x];
Anext[Index3D (nx, ny, i, j, k)] = (a_left_right + sh_A0[sh_id+1] + a_top + a_down
+ top + bottom)*c1 - sh_A0[sh_id]*c0 ;
}
//load another block
if((i2<nx) &&(j<ny))
top2=A0[Index3D (nx, ny, i2, j, k+1)];
if(w_region2)
{
a_left_right=x_h_bound?A0[Index3D (nx, ny, i2+1, j, k )]:sh_A0[sh_id2+1];
a_down=y_l_bound?A0[Index3D (nx, ny, i2, j-1, k )]:sh_A0[sh_id2-2*blockDim.x];
a_top=y_h_bound?A0[Index3D (nx, ny, i2, j+1, k )]:sh_A0[sh_id2+2*blockDim.x];
Anext[Index3D (nx, ny, i2, j, k)] = (a_left_right + sh_A0[sh_id2-1] + a_top + a_down + top2
+bottom2)*c1 - sh_A0[sh_id2]*c0;
}
//swap data
__syncthreads();
bottom=sh_A0[sh_id];
sh_A0[sh_id]=top;
bottom2=sh_A0[sh_id2];
sh_A0[sh_id2]=top2;
__syncthreads();
}
} | .file "tmpxft_000601f4_00000000-6_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z24block2D_hybrid_coarsen_xffPfS_iiiffPfS_iii
.type _Z51__device_stub__Z24block2D_hybrid_coarsen_xffPfS_iiiffPfS_iii, @function
_Z51__device_stub__Z24block2D_hybrid_coarsen_xffPfS_iiiffPfS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movss %xmm0, 44(%rsp)
movss %xmm1, 40(%rsp)
movq %rdi, 32(%rsp)
movq %rsi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z24block2D_hybrid_coarsen_xffPfS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z51__device_stub__Z24block2D_hybrid_coarsen_xffPfS_iiiffPfS_iii, .-_Z51__device_stub__Z24block2D_hybrid_coarsen_xffPfS_iiiffPfS_iii
.globl _Z24block2D_hybrid_coarsen_xffPfS_iii
.type _Z24block2D_hybrid_coarsen_xffPfS_iii, @function
_Z24block2D_hybrid_coarsen_xffPfS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z24block2D_hybrid_coarsen_xffPfS_iiiffPfS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24block2D_hybrid_coarsen_xffPfS_iii, .-_Z24block2D_hybrid_coarsen_xffPfS_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24block2D_hybrid_coarsen_xffPfS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24block2D_hybrid_coarsen_xffPfS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /***************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
***************************************************************************/
#include "common.h"
__global__ void block2D_hybrid_coarsen_x(float c0,float c1,float *A0,float *Anext, int nx, int ny, int nz)
{
//thread coarsening along x direction
const int i = blockIdx.x*blockDim.x*2+threadIdx.x;
const int i2= blockIdx.x*blockDim.x*2+threadIdx.x+blockDim.x;
const int j = blockIdx.y*blockDim.y+threadIdx.y;
const int sh_id=threadIdx.x + threadIdx.y*blockDim.x*2;
const int sh_id2=threadIdx.x +blockDim.x+ threadIdx.y*blockDim.x*2;
//shared memeory
extern __shared__ float sh_A0[];
sh_A0[sh_id]=0.0f;
sh_A0[sh_id2]=0.0f;
__syncthreads();
//get available region for load and store
const bool w_region = i>0 && j>0 &&(i<nx-1) &&(j<ny-1) ;
const bool w_region2 = j>0 &&(i2<nx-1) &&(j<ny-1) ;
const bool x_l_bound = (threadIdx.x==0);
const bool x_h_bound = ((threadIdx.x+blockDim.x)==(blockDim.x*2-1));
const bool y_l_bound = (threadIdx.y==0);
const bool y_h_bound = (threadIdx.y==(blockDim.y-1));
//register for bottom and top planes
//because of thread coarsening, we need to doulbe registers
float bottom=0.0f,bottom2=0.0f,top=0.0f,top2=0.0f;
//load data for bottom and current
if((i<nx) &&(j<ny))
{
bottom=A0[Index3D (nx, ny, i, j, 0)];
sh_A0[sh_id]=A0[Index3D (nx, ny, i, j, 1)];
}
if((i2<nx) &&(j<ny))
{
bottom2=A0[Index3D (nx, ny, i2, j, 0)];
sh_A0[sh_id2]=A0[Index3D (nx, ny, i2, j, 1)];
}
__syncthreads();
for(int k=1;k<nz-1;k++)
{
float a_left_right,a_top,a_down;
//load required data on xy planes
//if it on shared memory, load from shared memory
//if not, load from global memory
if((i<nx) &&(j<ny))
top=A0[Index3D (nx, ny, i, j, k+1)];
if(w_region)
{
a_left_right=x_l_bound?A0[Index3D (nx, ny, i-1, j, k )]:sh_A0[sh_id-1];
a_down=y_l_bound?A0[Index3D (nx, ny, i, j-1, k )]:sh_A0[sh_id-2*blockDim.x];
a_top=y_h_bound?A0[Index3D (nx, ny, i, j+1, k )]:sh_A0[sh_id+2*blockDim.x];
Anext[Index3D (nx, ny, i, j, k)] = (a_left_right + sh_A0[sh_id+1] + a_top + a_down
+ top + bottom)*c1 - sh_A0[sh_id]*c0 ;
}
//load another block
if((i2<nx) &&(j<ny))
top2=A0[Index3D (nx, ny, i2, j, k+1)];
if(w_region2)
{
a_left_right=x_h_bound?A0[Index3D (nx, ny, i2+1, j, k )]:sh_A0[sh_id2+1];
a_down=y_l_bound?A0[Index3D (nx, ny, i2, j-1, k )]:sh_A0[sh_id2-2*blockDim.x];
a_top=y_h_bound?A0[Index3D (nx, ny, i2, j+1, k )]:sh_A0[sh_id2+2*blockDim.x];
Anext[Index3D (nx, ny, i2, j, k)] = (a_left_right + sh_A0[sh_id2-1] + a_top + a_down + top2
+bottom2)*c1 - sh_A0[sh_id2]*c0;
}
//swap data
__syncthreads();
bottom=sh_A0[sh_id];
sh_A0[sh_id]=top;
bottom2=sh_A0[sh_id2];
sh_A0[sh_id2]=top2;
__syncthreads();
}
} | /***************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
***************************************************************************/
#include <hip/hip_runtime.h>
#include "common.h"
__global__ void block2D_hybrid_coarsen_x(float c0,float c1,float *A0,float *Anext, int nx, int ny, int nz)
{
//thread coarsening along x direction
const int i = blockIdx.x*blockDim.x*2+threadIdx.x;
const int i2= blockIdx.x*blockDim.x*2+threadIdx.x+blockDim.x;
const int j = blockIdx.y*blockDim.y+threadIdx.y;
const int sh_id=threadIdx.x + threadIdx.y*blockDim.x*2;
const int sh_id2=threadIdx.x +blockDim.x+ threadIdx.y*blockDim.x*2;
//shared memeory
extern __shared__ float sh_A0[];
sh_A0[sh_id]=0.0f;
sh_A0[sh_id2]=0.0f;
__syncthreads();
//get available region for load and store
const bool w_region = i>0 && j>0 &&(i<nx-1) &&(j<ny-1) ;
const bool w_region2 = j>0 &&(i2<nx-1) &&(j<ny-1) ;
const bool x_l_bound = (threadIdx.x==0);
const bool x_h_bound = ((threadIdx.x+blockDim.x)==(blockDim.x*2-1));
const bool y_l_bound = (threadIdx.y==0);
const bool y_h_bound = (threadIdx.y==(blockDim.y-1));
//register for bottom and top planes
//because of thread coarsening, we need to doulbe registers
float bottom=0.0f,bottom2=0.0f,top=0.0f,top2=0.0f;
//load data for bottom and current
if((i<nx) &&(j<ny))
{
bottom=A0[Index3D (nx, ny, i, j, 0)];
sh_A0[sh_id]=A0[Index3D (nx, ny, i, j, 1)];
}
if((i2<nx) &&(j<ny))
{
bottom2=A0[Index3D (nx, ny, i2, j, 0)];
sh_A0[sh_id2]=A0[Index3D (nx, ny, i2, j, 1)];
}
__syncthreads();
for(int k=1;k<nz-1;k++)
{
float a_left_right,a_top,a_down;
//load required data on xy planes
//if it on shared memory, load from shared memory
//if not, load from global memory
if((i<nx) &&(j<ny))
top=A0[Index3D (nx, ny, i, j, k+1)];
if(w_region)
{
a_left_right=x_l_bound?A0[Index3D (nx, ny, i-1, j, k )]:sh_A0[sh_id-1];
a_down=y_l_bound?A0[Index3D (nx, ny, i, j-1, k )]:sh_A0[sh_id-2*blockDim.x];
a_top=y_h_bound?A0[Index3D (nx, ny, i, j+1, k )]:sh_A0[sh_id+2*blockDim.x];
Anext[Index3D (nx, ny, i, j, k)] = (a_left_right + sh_A0[sh_id+1] + a_top + a_down
+ top + bottom)*c1 - sh_A0[sh_id]*c0 ;
}
//load another block
if((i2<nx) &&(j<ny))
top2=A0[Index3D (nx, ny, i2, j, k+1)];
if(w_region2)
{
a_left_right=x_h_bound?A0[Index3D (nx, ny, i2+1, j, k )]:sh_A0[sh_id2+1];
a_down=y_l_bound?A0[Index3D (nx, ny, i2, j-1, k )]:sh_A0[sh_id2-2*blockDim.x];
a_top=y_h_bound?A0[Index3D (nx, ny, i2, j+1, k )]:sh_A0[sh_id2+2*blockDim.x];
Anext[Index3D (nx, ny, i2, j, k)] = (a_left_right + sh_A0[sh_id2-1] + a_top + a_down + top2
+bottom2)*c1 - sh_A0[sh_id2]*c0;
}
//swap data
__syncthreads();
bottom=sh_A0[sh_id];
sh_A0[sh_id]=top;
bottom2=sh_A0[sh_id2];
sh_A0[sh_id2]=top2;
__syncthreads();
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /***************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
***************************************************************************/
#include <hip/hip_runtime.h>
#include "common.h"
__global__ void block2D_hybrid_coarsen_x(float c0,float c1,float *A0,float *Anext, int nx, int ny, int nz)
{
//thread coarsening along x direction
const int i = blockIdx.x*blockDim.x*2+threadIdx.x;
const int i2= blockIdx.x*blockDim.x*2+threadIdx.x+blockDim.x;
const int j = blockIdx.y*blockDim.y+threadIdx.y;
const int sh_id=threadIdx.x + threadIdx.y*blockDim.x*2;
const int sh_id2=threadIdx.x +blockDim.x+ threadIdx.y*blockDim.x*2;
//shared memeory
extern __shared__ float sh_A0[];
sh_A0[sh_id]=0.0f;
sh_A0[sh_id2]=0.0f;
__syncthreads();
//get available region for load and store
const bool w_region = i>0 && j>0 &&(i<nx-1) &&(j<ny-1) ;
const bool w_region2 = j>0 &&(i2<nx-1) &&(j<ny-1) ;
const bool x_l_bound = (threadIdx.x==0);
const bool x_h_bound = ((threadIdx.x+blockDim.x)==(blockDim.x*2-1));
const bool y_l_bound = (threadIdx.y==0);
const bool y_h_bound = (threadIdx.y==(blockDim.y-1));
//register for bottom and top planes
//because of thread coarsening, we need to doulbe registers
float bottom=0.0f,bottom2=0.0f,top=0.0f,top2=0.0f;
//load data for bottom and current
if((i<nx) &&(j<ny))
{
bottom=A0[Index3D (nx, ny, i, j, 0)];
sh_A0[sh_id]=A0[Index3D (nx, ny, i, j, 1)];
}
if((i2<nx) &&(j<ny))
{
bottom2=A0[Index3D (nx, ny, i2, j, 0)];
sh_A0[sh_id2]=A0[Index3D (nx, ny, i2, j, 1)];
}
__syncthreads();
for(int k=1;k<nz-1;k++)
{
float a_left_right,a_top,a_down;
//load required data on xy planes
//if it on shared memory, load from shared memory
//if not, load from global memory
if((i<nx) &&(j<ny))
top=A0[Index3D (nx, ny, i, j, k+1)];
if(w_region)
{
a_left_right=x_l_bound?A0[Index3D (nx, ny, i-1, j, k )]:sh_A0[sh_id-1];
a_down=y_l_bound?A0[Index3D (nx, ny, i, j-1, k )]:sh_A0[sh_id-2*blockDim.x];
a_top=y_h_bound?A0[Index3D (nx, ny, i, j+1, k )]:sh_A0[sh_id+2*blockDim.x];
Anext[Index3D (nx, ny, i, j, k)] = (a_left_right + sh_A0[sh_id+1] + a_top + a_down
+ top + bottom)*c1 - sh_A0[sh_id]*c0 ;
}
//load another block
if((i2<nx) &&(j<ny))
top2=A0[Index3D (nx, ny, i2, j, k+1)];
if(w_region2)
{
a_left_right=x_h_bound?A0[Index3D (nx, ny, i2+1, j, k )]:sh_A0[sh_id2+1];
a_down=y_l_bound?A0[Index3D (nx, ny, i2, j-1, k )]:sh_A0[sh_id2-2*blockDim.x];
a_top=y_h_bound?A0[Index3D (nx, ny, i2, j+1, k )]:sh_A0[sh_id2+2*blockDim.x];
Anext[Index3D (nx, ny, i2, j, k)] = (a_left_right + sh_A0[sh_id2-1] + a_top + a_down + top2
+bottom2)*c1 - sh_A0[sh_id2]*c0;
}
//swap data
__syncthreads();
bottom=sh_A0[sh_id];
sh_A0[sh_id]=top;
bottom2=sh_A0[sh_id2];
sh_A0[sh_id2]=top2;
__syncthreads();
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24block2D_hybrid_coarsen_xffPfS_iii
.globl _Z24block2D_hybrid_coarsen_xffPfS_iii
.p2align 8
.type _Z24block2D_hybrid_coarsen_xffPfS_iii,@function
_Z24block2D_hybrid_coarsen_xffPfS_iii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[12:13], s[0:1], 0x18
v_bfe_u32 v10, v0, 10, 10
v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v14, 0x3ff, v0
s_lshl_b32 s19, s14, 1
s_mov_b32 s5, 0
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b32_e32 v5, 1, v10
s_mov_b32 s14, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s18, s2, 0xffff
s_lshr_b32 s4, s2, 16
s_mul_i32 s17, s19, s18
s_mul_i32 s20, s15, s4
v_add_nc_u32_e32 v3, s18, v14
v_add_nc_u32_e32 v0, s17, v14
v_add_nc_u32_e32 v4, s20, v10
v_mad_u32_u24 v2, v5, s18, v14
s_add_i32 s6, s12, -1
v_mad_u32_u24 v7, v5, s18, v3
v_cmp_lt_i32_e64 s2, 0, v0
v_cmp_lt_i32_e32 vcc_lo, 0, v4
v_cmp_gt_i32_e64 s3, s6, v0
v_lshl_add_u32 v15, v2, 2, 0
v_lshl_add_u32 v16, v7, 2, 0
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
ds_store_b32 v15, v1
ds_store_b32 v16, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s3, s2
s_add_i32 s2, s13, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s2, v4
s_and_b32 s14, s2, exec_lo
s_or_b32 exec_lo, exec_lo, s3
v_add_nc_u32_e32 v1, s18, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s6, v1
s_and_b32 s3, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s3
s_add_i32 s3, s13, -1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v4
s_and_b32 s5, vcc_lo, exec_lo
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[6:7], s[0:1], 0x8
v_cmp_gt_i32_e64 s2, s12, v0
v_cmp_gt_i32_e32 vcc_lo, s13, v4
v_mov_b32_e32 v17, 0
v_add_nc_u32_e32 v5, s13, v4
v_mov_b32_e32 v19, 0
s_and_b32 s15, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s15
s_cbranch_execz .LBB0_6
v_mad_u64_u32 v[8:9], null, v5, s12, v[0:1]
v_mad_u64_u32 v[11:12], null, v4, s12, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v9, 31, v8
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v8, s2, s6, v8
v_add_co_ci_u32_e64 v9, s2, s7, v9, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v11, s2, s6, v11
v_add_co_ci_u32_e64 v12, s2, s7, v12, s2
s_clause 0x1
global_load_b32 v0, v[8:9], off
global_load_b32 v19, v[11:12], off
s_waitcnt vmcnt(1)
ds_store_b32 v15, v0
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s3
v_cmp_gt_i32_e64 s2, s12, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s16, s2, vcc_lo
s_and_saveexec_b32 s2, s16
s_cbranch_execz .LBB0_8
v_mad_u64_u32 v[8:9], null, v5, s12, v[1:2]
v_mad_u64_u32 v[5:6], null, v4, s12, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v9, 31, v8
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[8:9]
v_lshlrev_b64 v[4:5], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
s_clause 0x1
global_load_b32 v0, v[0:1], off
global_load_b32 v17, v[4:5], off
s_waitcnt vmcnt(1)
ds_store_b32 v16, v0
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s2
s_load_b32 s21, s[0:1], 0x20
s_waitcnt vmcnt(0) lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cmp_lt_i32 s21, 3
s_cbranch_scc1 .LBB0_31
v_lshl_add_u32 v6, v2, 2, 0
s_lshl_b32 s24, s18, 1
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x0
s_load_b64 s[10:11], s[0:1], 0x10
v_subrev_nc_u32_e32 v1, s24, v2
s_add_i32 s2, s24, -1
v_dual_mov_b32 v29, 0 :: v_dual_add_nc_u32 v0, -4, v6
v_cmp_eq_u32_e64 s2, s2, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshl_add_u32 v3, v1, 2, 0
v_lshl_add_u32 v12, v7, 2, 0
v_cmp_ne_u32_e64 s0, -1, v0
s_mov_b64 s[22:23], src_shared_base
v_add_nc_u32_e32 v2, s24, v2
v_subrev_nc_u32_e32 v5, s24, v7
v_add_nc_u32_e32 v8, 4, v12
v_cndmask_b32_e64 v0, 0, v0, s0
v_cndmask_b32_e64 v1, 0, s23, s0
v_cmp_ne_u32_e64 s0, -1, v3
v_lshl_add_u32 v4, v2, 2, 0
v_add3_u32 v13, s20, s13, v10
v_add_nc_u32_e32 v18, 4, v6
v_dual_mov_b32 v30, 0 :: v_dual_add_nc_u32 v11, s24, v7
v_cndmask_b32_e64 v2, 0, v3, s0
v_cndmask_b32_e64 v3, 0, s23, s0
v_cmp_ne_u32_e64 s0, -1, v8
v_cmp_ne_u32_e64 s1, -1, v4
v_lshl_add_u32 v9, v5, 2, 0
v_mul_lo_u32 v25, s12, v13
v_add_nc_u32_e32 v13, -1, v13
v_cndmask_b32_e64 v6, 0, v8, s0
v_cndmask_b32_e64 v7, 0, s23, s0
s_lshl_b32 s0, s13, 1
v_lshl_add_u32 v11, v11, 2, 0
v_add3_u32 v20, s0, s20, v10
v_cndmask_b32_e64 v4, 0, v4, s1
v_cndmask_b32_e64 v5, 0, s23, s1
v_cmp_ne_u32_e64 s1, -1, v9
v_mul_lo_u32 v13, s12, v13
v_mul_lo_u32 v28, s12, v20
v_cmp_ne_u32_e64 s0, -1, v11
v_add_nc_u32_e32 v26, s12, v25
v_cndmask_b32_e64 v8, 0, v9, s1
v_cndmask_b32_e64 v9, 0, s23, s1
s_add_i32 s1, s19, 1
s_add_i32 s4, s4, -1
s_mul_i32 s1, s1, s18
v_cmp_eq_u32_e32 vcc_lo, 0, v14
v_cmp_eq_u32_e64 s3, 0, v10
v_cmp_eq_u32_e64 s4, s4, v10
v_cndmask_b32_e64 v10, 0, v11, s0
v_cndmask_b32_e64 v11, 0, s23, s0
v_add_nc_u32_e32 v20, -4, v12
v_add_nc_u32_e32 v21, s1, v25
v_add_nc_u32_e32 v22, s1, v26
v_add_nc_u32_e32 v23, s1, v13
v_add_nc_u32_e32 v24, s1, v28
v_add_nc_u32_e32 v25, s17, v25
v_add_nc_u32_e32 v26, s17, v26
v_add_nc_u32_e32 v27, s17, v13
v_add_nc_u32_e32 v28, s17, v28
s_add_i32 s1, s21, -2
s_mul_i32 s12, s13, s12
s_branch .LBB0_12
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s17
flat_load_b32 v12, v[12:13]
ds_load_b32 v13, v20
ds_load_b32 v32, v16
s_waitcnt vmcnt(2) lgkmcnt(0)
v_add_f32_e32 v13, v19, v13
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v12, v12, v13
v_add_f32_e32 v13, v31, v12
v_dual_mul_f32 v31, s8, v32 :: v_dual_add_nc_u32 v12, v21, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v19, v29, v13
v_ashrrev_i32_e32 v13, 31, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v17, v17, v19
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v17, v17, s9, -v31
v_add_co_u32 v12, s0, s10, v12
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v13, s0, s11, v13, s0
global_store_b32 v[12:13], v17, off
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s13
s_waitcnt vmcnt(0) lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
ds_load_b32 v19, v15
ds_store_b32 v15, v30
ds_load_b32 v17, v16
v_add_nc_u32_e32 v14, s12, v14
s_add_i32 s1, s1, -1
ds_store_b32 v16, v29
s_cmp_eq_u32 s1, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_31
.LBB0_12:
s_and_saveexec_b32 s13, s15
s_cbranch_execz .LBB0_14
v_add_nc_u32_e32 v12, v28, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v12, s0, s6, v12
v_add_co_ci_u32_e64 v13, s0, s7, v13, s0
global_load_b32 v30, v[12:13], off
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s13
s_and_saveexec_b32 s13, s14
s_cbranch_execz .LBB0_22
v_dual_mov_b32 v13, v1 :: v_dual_mov_b32 v12, v0
s_and_saveexec_b32 s17, vcc_lo
v_add3_u32 v12, v25, v14, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v12, s0, s6, v12
v_add_co_ci_u32_e64 v13, s0, s7, v13, s0
s_or_b32 exec_lo, exec_lo, s17
flat_load_b32 v31, v[12:13]
v_dual_mov_b32 v13, v3 :: v_dual_mov_b32 v12, v2
s_and_saveexec_b32 s17, s3
v_add_nc_u32_e32 v12, v27, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v12, s0, s6, v12
v_add_co_ci_u32_e64 v13, s0, s7, v13, s0
s_or_b32 exec_lo, exec_lo, s17
flat_load_b32 v32, v[12:13]
v_dual_mov_b32 v13, v5 :: v_dual_mov_b32 v12, v4
s_and_saveexec_b32 s17, s4
v_add_nc_u32_e32 v12, v26, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v12, s0, s6, v12
v_add_co_ci_u32_e64 v13, s0, s7, v13, s0
s_or_b32 exec_lo, exec_lo, s17
flat_load_b32 v12, v[12:13]
ds_load_b32 v13, v18
ds_load_b32 v33, v15
s_waitcnt vmcnt(2) lgkmcnt(0)
v_add_f32_e32 v13, v31, v13
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v12, v12, v13
v_dual_add_f32 v13, v32, v12 :: v_dual_mul_f32 v32, s8, v33
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v31, v30, v13 :: v_dual_add_nc_u32 v12, v25, v14
v_ashrrev_i32_e32 v13, 31, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v19, v19, v31
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v19, v19, s9, -v32
v_add_co_u32 v12, s0, s10, v12
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v13, s0, s11, v13, s0
global_store_b32 v[12:13], v19, off
.LBB0_22:
s_or_b32 exec_lo, exec_lo, s13
s_and_saveexec_b32 s13, s16
s_cbranch_execz .LBB0_24
v_add_nc_u32_e32 v12, v24, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v12, s0, s6, v12
v_add_co_ci_u32_e64 v13, s0, s7, v13, s0
global_load_b32 v29, v[12:13], off
.LBB0_24:
s_or_b32 exec_lo, exec_lo, s13
s_and_saveexec_b32 s13, s5
s_cbranch_execz .LBB0_11
v_dual_mov_b32 v13, v7 :: v_dual_mov_b32 v12, v6
s_and_saveexec_b32 s17, s2
v_add3_u32 v12, v21, v14, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v12, s0, s6, v12
v_add_co_ci_u32_e64 v13, s0, s7, v13, s0
s_or_b32 exec_lo, exec_lo, s17
flat_load_b32 v19, v[12:13]
v_dual_mov_b32 v13, v9 :: v_dual_mov_b32 v12, v8
s_and_saveexec_b32 s17, s3
v_add_nc_u32_e32 v12, v23, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v12, s0, s6, v12
v_add_co_ci_u32_e64 v13, s0, s7, v13, s0
s_or_b32 exec_lo, exec_lo, s17
flat_load_b32 v31, v[12:13]
v_dual_mov_b32 v13, v11 :: v_dual_mov_b32 v12, v10
s_and_saveexec_b32 s17, s4
s_cbranch_execz .LBB0_10
v_add_nc_u32_e32 v12, v22, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v12, s0, s6, v12
v_add_co_ci_u32_e64 v13, s0, s7, v13, s0
s_branch .LBB0_10
.LBB0_31:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24block2D_hybrid_coarsen_xffPfS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 34
.amdhsa_next_free_sgpr 25
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24block2D_hybrid_coarsen_xffPfS_iii, .Lfunc_end0-_Z24block2D_hybrid_coarsen_xffPfS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
- .offset: 160
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24block2D_hybrid_coarsen_xffPfS_iii
.private_segment_fixed_size: 0
.sgpr_count: 27
.sgpr_spill_count: 0
.symbol: _Z24block2D_hybrid_coarsen_xffPfS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 34
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /***************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
***************************************************************************/
#include <hip/hip_runtime.h>
#include "common.h"
__global__ void block2D_hybrid_coarsen_x(float c0,float c1,float *A0,float *Anext, int nx, int ny, int nz)
{
//thread coarsening along x direction
const int i = blockIdx.x*blockDim.x*2+threadIdx.x;
const int i2= blockIdx.x*blockDim.x*2+threadIdx.x+blockDim.x;
const int j = blockIdx.y*blockDim.y+threadIdx.y;
const int sh_id=threadIdx.x + threadIdx.y*blockDim.x*2;
const int sh_id2=threadIdx.x +blockDim.x+ threadIdx.y*blockDim.x*2;
//shared memeory
extern __shared__ float sh_A0[];
sh_A0[sh_id]=0.0f;
sh_A0[sh_id2]=0.0f;
__syncthreads();
//get available region for load and store
const bool w_region = i>0 && j>0 &&(i<nx-1) &&(j<ny-1) ;
const bool w_region2 = j>0 &&(i2<nx-1) &&(j<ny-1) ;
const bool x_l_bound = (threadIdx.x==0);
const bool x_h_bound = ((threadIdx.x+blockDim.x)==(blockDim.x*2-1));
const bool y_l_bound = (threadIdx.y==0);
const bool y_h_bound = (threadIdx.y==(blockDim.y-1));
//register for bottom and top planes
//because of thread coarsening, we need to doulbe registers
float bottom=0.0f,bottom2=0.0f,top=0.0f,top2=0.0f;
//load data for bottom and current
if((i<nx) &&(j<ny))
{
bottom=A0[Index3D (nx, ny, i, j, 0)];
sh_A0[sh_id]=A0[Index3D (nx, ny, i, j, 1)];
}
if((i2<nx) &&(j<ny))
{
bottom2=A0[Index3D (nx, ny, i2, j, 0)];
sh_A0[sh_id2]=A0[Index3D (nx, ny, i2, j, 1)];
}
__syncthreads();
for(int k=1;k<nz-1;k++)
{
float a_left_right,a_top,a_down;
//load required data on xy planes
//if it on shared memory, load from shared memory
//if not, load from global memory
if((i<nx) &&(j<ny))
top=A0[Index3D (nx, ny, i, j, k+1)];
if(w_region)
{
a_left_right=x_l_bound?A0[Index3D (nx, ny, i-1, j, k )]:sh_A0[sh_id-1];
a_down=y_l_bound?A0[Index3D (nx, ny, i, j-1, k )]:sh_A0[sh_id-2*blockDim.x];
a_top=y_h_bound?A0[Index3D (nx, ny, i, j+1, k )]:sh_A0[sh_id+2*blockDim.x];
Anext[Index3D (nx, ny, i, j, k)] = (a_left_right + sh_A0[sh_id+1] + a_top + a_down
+ top + bottom)*c1 - sh_A0[sh_id]*c0 ;
}
//load another block
if((i2<nx) &&(j<ny))
top2=A0[Index3D (nx, ny, i2, j, k+1)];
if(w_region2)
{
a_left_right=x_h_bound?A0[Index3D (nx, ny, i2+1, j, k )]:sh_A0[sh_id2+1];
a_down=y_l_bound?A0[Index3D (nx, ny, i2, j-1, k )]:sh_A0[sh_id2-2*blockDim.x];
a_top=y_h_bound?A0[Index3D (nx, ny, i2, j+1, k )]:sh_A0[sh_id2+2*blockDim.x];
Anext[Index3D (nx, ny, i2, j, k)] = (a_left_right + sh_A0[sh_id2-1] + a_top + a_down + top2
+bottom2)*c1 - sh_A0[sh_id2]*c0;
}
//swap data
__syncthreads();
bottom=sh_A0[sh_id];
sh_A0[sh_id]=top;
bottom2=sh_A0[sh_id2];
sh_A0[sh_id2]=top2;
__syncthreads();
}
} | .text
.file "kernels.hip"
.globl _Z39__device_stub__block2D_hybrid_coarsen_xffPfS_iii # -- Begin function _Z39__device_stub__block2D_hybrid_coarsen_xffPfS_iii
.p2align 4, 0x90
.type _Z39__device_stub__block2D_hybrid_coarsen_xffPfS_iii,@function
_Z39__device_stub__block2D_hybrid_coarsen_xffPfS_iii: # @_Z39__device_stub__block2D_hybrid_coarsen_xffPfS_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z24block2D_hybrid_coarsen_xffPfS_iii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z39__device_stub__block2D_hybrid_coarsen_xffPfS_iii, .Lfunc_end0-_Z39__device_stub__block2D_hybrid_coarsen_xffPfS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24block2D_hybrid_coarsen_xffPfS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24block2D_hybrid_coarsen_xffPfS_iii,@object # @_Z24block2D_hybrid_coarsen_xffPfS_iii
.section .rodata,"a",@progbits
.globl _Z24block2D_hybrid_coarsen_xffPfS_iii
.p2align 3, 0x0
_Z24block2D_hybrid_coarsen_xffPfS_iii:
.quad _Z39__device_stub__block2D_hybrid_coarsen_xffPfS_iii
.size _Z24block2D_hybrid_coarsen_xffPfS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24block2D_hybrid_coarsen_xffPfS_iii"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__block2D_hybrid_coarsen_xffPfS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24block2D_hybrid_coarsen_xffPfS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z24block2D_hybrid_coarsen_xffPfS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0020*/ MOV R13, c[0x0][0x0] ; /* 0x00000000000d7a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R21, SR_CTAID.Y ; /* 0x0000000000157919 */
/* 0x000e220000002600 */
/*0050*/ SHF.L.U32 R15, R13, 0x1, RZ ; /* 0x000000010d0f7819 */
/* 0x000fc600000006ff */
/*0060*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e680000002100 */
/*0070*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */
/* 0x000ea20000002500 */
/*0080*/ IMAD R12, R21, c[0x0][0x4], R0 ; /* 0x00000100150c7a24 */
/* 0x001fe200078e0200 */
/*0090*/ IADD3 R14, R3, c[0x0][0x0], RZ ; /* 0x00000000030e7a10 */
/* 0x002fe20007ffe0ff */
/*00a0*/ IMAD R2, R15, R0, R3 ; /* 0x000000000f027224 */
/* 0x000fc600078e0203 */
/*00b0*/ ISETP.GE.AND P0, PT, R12, c[0x0][0x17c], PT ; /* 0x00005f000c007a0c */
/* 0x000fe20003f06270 */
/*00c0*/ IMAD R11, R15, R10, R3 ; /* 0x0000000a0f0b7224 */
/* 0x004fe200078e0203 */
/*00d0*/ STS [R2.X4], RZ ; /* 0x000000ff02007388 */
/* 0x0001e80000004800 */
/*00e0*/ ISETP.LT.AND P3, PT, R11.reuse, c[0x0][0x178], !P0 ; /* 0x00005e000b007a0c */
/* 0x040fe40004761270 */
/*00f0*/ IADD3 R23, R11, c[0x0][0x0], RZ ; /* 0x000000000b177a10 */
/* 0x000fc80007ffe0ff */
/*0100*/ ISETP.LT.AND P0, PT, R23, c[0x0][0x178], !P0 ; /* 0x00005e0017007a0c */
/* 0x000fce0004701270 */
/*0110*/ @P3 IADD3 R4, R12, c[0x0][0x17c], RZ ; /* 0x00005f000c043a10 */
/* 0x000fe40007ffe0ff */
/*0120*/ @P3 MOV R7, 0x4 ; /* 0x0000000400073802 */
/* 0x000fc60000000f00 */
/*0130*/ @P3 IMAD R18, R4, c[0x0][0x178], R11 ; /* 0x00005e0004123a24 */
/* 0x000fe200078e020b */
/*0140*/ @P0 IADD3 R16, R12, c[0x0][0x17c], RZ ; /* 0x00005f000c100a10 */
/* 0x000fe20007ffe0ff */
/*0150*/ IMAD R4, R15, R0, R14 ; /* 0x000000000f047224 */
/* 0x000fe200078e020e */
/*0160*/ @P0 MOV R9, 0x4 ; /* 0x0000000400090802 */
/* 0x000fe20000000f00 */
/*0170*/ @P3 IMAD.WIDE R18, R18, R7, c[0x0][0x168] ; /* 0x00005a0012123625 */
/* 0x000fc600078e0207 */
/*0180*/ STS [R4.X4], RZ ; /* 0x000000ff04007388 */
/* 0x0001e20000004800 */
/*0190*/ @P0 IMAD R16, R16, c[0x0][0x178], R23 ; /* 0x00005e0010100a24 */
/* 0x000fc600078e0217 */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01b0*/ @P0 IMAD.WIDE R16, R16, R9, c[0x0][0x168] ; /* 0x00005a0010100625 */
/* 0x000fca00078e0209 */
/*01c0*/ @P3 LDG.E R19, [R18.64] ; /* 0x0000000812133981 */
/* 0x000ea8000c1e1900 */
/*01d0*/ @P0 LDG.E R17, [R16.64] ; /* 0x0000000810110981 */
/* 0x000ee2000c1e1900 */
/*01e0*/ HFMA2.MMA R26, -RZ, RZ, 0, 0 ; /* 0x00000000ff1a7435 */
/* 0x000fe200000001ff */
/*01f0*/ @P3 IMAD R6, R12.reuse, c[0x0][0x178], R11 ; /* 0x00005e000c063a24 */
/* 0x040fe200078e020b */
/*0200*/ MOV R5, RZ ; /* 0x000000ff00057202 */
/* 0x000fe20000000f00 */
/*0210*/ @P0 IMAD R8, R12, c[0x0][0x178], R23 ; /* 0x00005e000c080a24 */
/* 0x000fe400078e0217 */
/*0220*/ @P3 IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006063625 */
/* 0x000fc800078e0207 */
/*0230*/ @P0 IMAD.WIDE R8, R8, R9, c[0x0][0x168] ; /* 0x00005a0008080625 */
/* 0x000fe200078e0209 */
/*0240*/ @P3 LDG.E R26, [R6.64] ; /* 0x00000008061a3981 */
/* 0x000168000c1e1900 */
/*0250*/ @P0 LDG.E R5, [R8.64] ; /* 0x0000000808050981 */
/* 0x000162000c1e1900 */
/*0260*/ MOV R22, c[0x0][0x180] ; /* 0x0000600000167a02 */
/* 0x000fc80000000f00 */
/*0270*/ ISETP.GE.AND P1, PT, R22, 0x3, PT ; /* 0x000000031600780c */
/* 0x000fe20003f26270 */
/*0280*/ @P3 STS [R2.X4], R19 ; /* 0x0000001302003388 */
/* 0x0041e80000004800 */
/*0290*/ @P0 STS [R4.X4], R17 ; /* 0x0000001104000388 */
/* 0x0081e80000004800 */
/*02a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02b0*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*02c0*/ UMOV UR6, 0x1 ; /* 0x0000000100067882 */
/* 0x001fe20000000000 */
/*02d0*/ ISETP.GT.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f24270 */
/*02e0*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000a00 */
/*02f0*/ IADD3 R7, R15, -0x1, RZ ; /* 0xffffffff0f077810 */
/* 0x000fe20007ffe0ff */
/*0300*/ UIADD3 UR4, -UR6, UR4, URZ ; /* 0x0000000406047290 */
/* 0x000fe2000fffe13f */
/*0310*/ IADD3 R6, R0, c[0x0][0x17c], RZ ; /* 0x00005f0000067a10 */
/* 0x000fe20007ffe0ff */
/*0320*/ UIADD3 UR5, -UR6, UR5, URZ ; /* 0x0000000506057290 */
/* 0x000fe2000fffe13f */
/*0330*/ MOV R9, c[0x0][0x17c] ; /* 0x00005f0000097a02 */
/* 0x000fc40000000f00 */
/*0340*/ ISETP.NE.AND P4, PT, R14, R7, PT ; /* 0x000000070e00720c */
/* 0x000fe20003f85270 */
/*0350*/ IMAD R14, R21, c[0x0][0x4], R6 ; /* 0x00000100150e7a24 */
/* 0x000fe200078e0206 */
/*0360*/ ISETP.LT.AND P2, PT, R23, UR4, P1 ; /* 0x0000000417007c0c */
/* 0x000fe40008f41270 */
/*0370*/ ISETP.GT.AND P1, PT, R11, RZ, P1 ; /* 0x000000ff0b00720c */
/* 0x000fe40000f24270 */
/*0380*/ SHF.L.U32 R8, R4, 0x2, RZ ; /* 0x0000000204087819 */
/* 0x000fe400000006ff */
/*0390*/ LEA R18, R9, R12, 0x1 ; /* 0x0000000c09127211 */
/* 0x000fe200078e08ff */
/*03a0*/ IMAD R9, R14, c[0x0][0x178], R11.reuse ; /* 0x00005e000e097a24 */
/* 0x100fe200078e020b */
/*03b0*/ ISETP.LT.AND P5, PT, R11, UR4, P1 ; /* 0x000000040b007c0c */
/* 0x000fe20008fa1270 */
/*03c0*/ ULDC UR4, c[0x0][0x4] ; /* 0x0000010000047ab9 */
/* 0x000fe20000000800 */
/*03d0*/ LEA R7, R13, R8, 0x3 ; /* 0x000000080d077211 */
/* 0x000fe200078e18ff */
/*03e0*/ IMAD R8, R18, c[0x0][0x178], R11 ; /* 0x00005e0012087a24 */
/* 0x000fe200078e020b */
/*03f0*/ ISETP.LT.AND P1, PT, R12, UR5, P2 ; /* 0x000000050c007c0c */
/* 0x000fe20009721270 */
/*0400*/ IMAD R17, R18, c[0x0][0x178], R3 ; /* 0x00005e0012117a24 */
/* 0x000fe200078e0203 */
/*0410*/ ISETP.LT.AND P2, PT, R12, UR5, P5 ; /* 0x000000050c007c0c */
/* 0x000fe2000af41270 */
/*0420*/ UIADD3 UR4, -UR6, UR4, URZ ; /* 0x0000000406047290 */
/* 0x000fe2000fffe13f */
/*0430*/ SHF.L.U32 R6, R2, 0x2, RZ ; /* 0x0000000202067819 */
/* 0x000fe200000006ff */
/*0440*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe20000000000 */
/*0450*/ IADD3 R12, R14, -0x1, RZ ; /* 0xffffffff0e0c7810 */
/* 0x000fc40007ffe0ff */
/*0460*/ IADD3 R18, R14.reuse, 0x1, RZ ; /* 0x000000010e127810 */
/* 0x040fe40007ffe0ff */
/*0470*/ LEA R6, R13, R6, 0x3 ; /* 0x000000060d067211 */
/* 0x000fe200078e18ff */
/*0480*/ IMAD R13, R14, c[0x0][0x178], R3.reuse ; /* 0x00005e000e0d7a24 */
/* 0x100fe200078e0203 */
/*0490*/ LEA R16, R10, 0x1, 0x1 ; /* 0x000000010a107811 */
/* 0x000fe200078e08ff */
/*04a0*/ IMAD R19, R12, c[0x0][0x178], R3.reuse ; /* 0x00005e000c137a24 */
/* 0x100fe200078e0203 */
/*04b0*/ IADD3 R22, R22, -0x1, RZ ; /* 0xffffffff16167810 */
/* 0x000fe20007ffe0ff */
/*04c0*/ IMAD R21, R18, c[0x0][0x178], R3 ; /* 0x00005e0012157a24 */
/* 0x000fe200078e0203 */
/*04d0*/ IADD3 R23, -R15.reuse, R2, RZ ; /* 0x000000020f177210 */
/* 0x040fe20007ffe1ff */
/*04e0*/ IMAD R10, R12, c[0x0][0x178], R11.reuse ; /* 0x00005e000c0a7a24 */
/* 0x100fe200078e020b */
/*04f0*/ IADD3 R24, -R15, R4, RZ ; /* 0x000000040f187210 */
/* 0x000fe20007ffe1ff */
/*0500*/ IMAD R11, R18, c[0x0][0x178], R11 ; /* 0x00005e00120b7a24 */
/* 0x000fe200078e020b */
/*0510*/ MOV R25, RZ ; /* 0x000000ff00197202 */
/* 0x000fe20000000f00 */
/*0520*/ IMAD R12, R16.reuse, c[0x0][0x0], R17 ; /* 0x00000000100c7a24 */
/* 0x040fe200078e0211 */
/*0530*/ MOV R27, RZ ; /* 0x000000ff001b7202 */
/* 0x000fe20000000f00 */
/*0540*/ IMAD R13, R16, c[0x0][0x0], R13 ; /* 0x00000000100d7a24 */
/* 0x000fc400078e020d */
/*0550*/ IMAD R20, R16.reuse, c[0x0][0x0], R19 ; /* 0x0000000010147a24 */
/* 0x040fe400078e0213 */
/*0560*/ IMAD R21, R16, c[0x0][0x0], R21 ; /* 0x0000000010157a24 */
/* 0x000fe400078e0215 */
/*0570*/ @P3 MOV R15, 0x4 ; /* 0x00000004000f3802 */
/* 0x000fca0000000f00 */
/*0580*/ @P3 IMAD.WIDE R14, R8, R15, c[0x0][0x168] ; /* 0x00005a00080e3625 */
/* 0x000fca00078e020f */
/*0590*/ @P3 LDG.E R27, [R14.64] ; /* 0x000000080e1b3981 */
/* 0x020162000c1e1900 */
/*05a0*/ BSSY B0, 0x760 ; /* 0x000001b000007945 */
/* 0x000fe20003800000 */
/*05b0*/ @!P2 BRA 0x750 ; /* 0x000001900000a947 */
/* 0x006fea0003800000 */
/*05c0*/ ISETP.NE.AND P5, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003fa5270 */
/*05d0*/ HFMA2.MMA R28, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff1c7435 */
/* 0x000fe200000001ff */
/*05e0*/ LDS R15, [R2.X4+0x4] ; /* 0x00000400020f7984 */
/* 0x001ff60000004800 */
/*05f0*/ @P5 LDS R14, [R2.X4+-0x4] ; /* 0xfffffc00020e5984 */
/* 0x000e220000004800 */
/*0600*/ @!P5 IADD3 R19, R9, -0x1, RZ ; /* 0xffffffff0913d810 */
/* 0x000fca0007ffe0ff */
/*0610*/ @!P5 IMAD.WIDE R18, R19, R28, c[0x0][0x168] ; /* 0x00005a001312d625 */
/* 0x000fca00078e021c */
/*0620*/ @!P5 LDG.E R14, [R18.64] ; /* 0x00000008120ed981 */
/* 0x000e22000c1e1900 */
/*0630*/ ISETP.NE.AND P5, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bfa5270 */
/*0640*/ @P5 LDS R16, [R6] ; /* 0x0000000006105984 */
/* 0x000e620000000800 */
/*0650*/ FADD R17, R15, R14 ; /* 0x0000000e0f117221 */
/* 0x001fe40000000000 */
/*0660*/ @!P5 IMAD.WIDE R14, R11, R28, c[0x0][0x168] ; /* 0x00005a000b0ed625 */
/* 0x000fca00078e021c */
/*0670*/ @!P5 LDG.E R16, [R14.64] ; /* 0x000000080e10d981 */
/* 0x000062000c1e1900 */
/*0680*/ ISETP.NE.AND P5, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc60003fa5270 */
/*0690*/ LDS R15, [R2.X4] ; /* 0x00000000020f7984 */
/* 0x001ff40000004800 */
/*06a0*/ @P5 LDS R29, [R23.X4] ; /* 0x00000000171d5984 */
/* 0x000e220000004800 */
/*06b0*/ FADD R14, R17, R16 ; /* 0x00000010110e7221 */
/* 0x002fc40000000000 */
/*06c0*/ @!P5 IMAD.WIDE R16, R10, R28, c[0x0][0x168] ; /* 0x00005a000a10d625 */
/* 0x000fca00078e021c */
/*06d0*/ @!P5 LDG.E R29, [R16.64] ; /* 0x00000008101dd981 */
/* 0x000e24000c1e1900 */
/*06e0*/ FADD R18, R14, R29 ; /* 0x0000001d0e127221 */
/* 0x001fc80000000000 */
/*06f0*/ FADD R19, R27, R18 ; /* 0x000000121b137221 */
/* 0x020fe40000000000 */
/*0700*/ FMUL R18, R15, c[0x0][0x160] ; /* 0x000058000f127a20 */
/* 0x000fe40000400000 */
/*0710*/ FADD R19, R19, R26 ; /* 0x0000001a13137221 */
/* 0x000fe40000000000 */
/*0720*/ IMAD.WIDE R14, R9, R28, c[0x0][0x170] ; /* 0x00005c00090e7625 */
/* 0x000fc800078e021c */
/*0730*/ FFMA R19, R19, c[0x0][0x164], -R18 ; /* 0x0000590013137a23 */
/* 0x000fca0000000812 */
/*0740*/ STG.E [R14.64], R19 ; /* 0x000000130e007986 */
/* 0x0001e4000c101908 */
/*0750*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0760*/ BSSY B0, 0x7c0 ; /* 0x0000005000007945 */
/* 0x000fe20003800000 */
/*0770*/ @!P0 BRA 0x7b0 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0780*/ MOV R15, 0x4 ; /* 0x00000004000f7802 */
/* 0x001fca0000000f00 */
/*0790*/ IMAD.WIDE R14, R12, R15, c[0x0][0x168] ; /* 0x00005a000c0e7625 */
/* 0x000fca00078e020f */
/*07a0*/ LDG.E R25, [R14.64] ; /* 0x000000080e197981 */
/* 0x000164000c1e1900 */
/*07b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07c0*/ BSSY B0, 0x970 ; /* 0x000001a000007945 */
/* 0x000fe20003800000 */
/*07d0*/ @!P1 BRA 0x960 ; /* 0x0000018000009947 */
/* 0x000fea0003800000 */
/*07e0*/ @P4 LDS R18, [R4.X4+0x4] ; /* 0x0000040004124984 */
/* 0x000fe20000004800 */
/*07f0*/ HFMA2.MMA R26, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff1a7435 */
/* 0x000fe200000001ff */
/*0800*/ @!P4 IADD3 R15, R13, 0x1, RZ ; /* 0x000000010d0fc810 */
/* 0x001fe40007ffe0ff */
/*0810*/ ISETP.NE.AND P6, PT, R0.reuse, UR4, PT ; /* 0x0000000400007c0c */
/* 0x040fe2000bfc5270 */
/*0820*/ LDS R19, [R4.X4+-0x4] ; /* 0xfffffc0004137984 */
/* 0x000e2c0000004800 */
/*0830*/ @!P4 IMAD.WIDE R14, R15, R26, c[0x0][0x168] ; /* 0x00005a000f0ec625 */
/* 0x000fe200078e021a */
/*0840*/ ISETP.NE.AND P5, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fca0003fa5270 */
/*0850*/ @P6 LDS R28, [R7] ; /* 0x00000000071c6984 */
/* 0x000e700000000800 */
/*0860*/ @P5 LDS R29, [R24.X4] ; /* 0x00000000181d5984 */
/* 0x000ea80000004800 */
/*0870*/ @!P4 LDG.E R18, [R14.64] ; /* 0x000000080e12c981 */
/* 0x000622000c1e1900 */
/*0880*/ @!P6 IMAD.WIDE R16, R21, R26, c[0x0][0x168] ; /* 0x00005a001510e625 */
/* 0x000fc600078e021a */
/*0890*/ LDS R14, [R4.X4] ; /* 0x00000000040e7984 */
/* 0x008ee80000004800 */
/*08a0*/ @!P6 LDG.E R28, [R16.64] ; /* 0x00000008101ce981 */
/* 0x000e62000c1e1900 */
/*08b0*/ FADD R15, R19, R18 ; /* 0x00000012130f7221 */
/* 0x001fe40000000000 */
/*08c0*/ @!P5 IMAD.WIDE R18, R20, R26, c[0x0][0x168] ; /* 0x00005a001412d625 */
/* 0x000fca00078e021a */
/*08d0*/ @!P5 LDG.E R29, [R18.64] ; /* 0x00000008121dd981 */
/* 0x000ea2000c1e1900 */
/*08e0*/ FADD R28, R15, R28 ; /* 0x0000001c0f1c7221 */
/* 0x002fc80000000000 */
/*08f0*/ FADD R28, R28, R29 ; /* 0x0000001d1c1c7221 */
/* 0x004fe40000000000 */
/*0900*/ FMUL R29, R14, c[0x0][0x160] ; /* 0x000058000e1d7a20 */
/* 0x008fe40000400000 */
/*0910*/ FADD R28, R25, R28 ; /* 0x0000001c191c7221 */
/* 0x020fe40000000000 */
/*0920*/ IMAD.WIDE R14, R13, R26, c[0x0][0x170] ; /* 0x00005c000d0e7625 */
/* 0x000fc800078e021a */
/*0930*/ FADD R5, R28, R5 ; /* 0x000000051c057221 */
/* 0x000fc80000000000 */
/*0940*/ FFMA R5, R5, c[0x0][0x164], -R29 ; /* 0x0000590005057a23 */
/* 0x000fca000000081d */
/*0950*/ STG.E [R14.64], R5 ; /* 0x000000050e007986 */
/* 0x0001e4000c101908 */
/*0960*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0970*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0980*/ UIADD3 UR5, UR5, 0x1, URZ ; /* 0x0000000105057890 */
/* 0x000fe2000fffe03f */
/*0990*/ MOV R14, c[0x0][0x17c] ; /* 0x00005f00000e7a02 */
/* 0x001fca0000000f00 */
/*09a0*/ ISETP.LE.AND P5, PT, R22, UR5, PT ; /* 0x0000000516007c0c */
/* 0x000fe2000bfa3270 */
/*09b0*/ IMAD R13, R14.reuse, c[0x0][0x178], R13 ; /* 0x00005e000e0d7a24 */
/* 0x040fe400078e020d */
/*09c0*/ IMAD R9, R14.reuse, c[0x0][0x178], R9 ; /* 0x00005e000e097a24 */
/* 0x040fe400078e0209 */
/*09d0*/ IMAD R8, R14.reuse, c[0x0][0x178], R8 ; /* 0x00005e000e087a24 */
/* 0x040fe400078e0208 */
/*09e0*/ IMAD R12, R14.reuse, c[0x0][0x178], R12 ; /* 0x00005e000e0c7a24 */
/* 0x040fe400078e020c */
/*09f0*/ IMAD R10, R14.reuse, c[0x0][0x178], R10 ; /* 0x00005e000e0a7a24 */
/* 0x040fe400078e020a */
/*0a00*/ IMAD R11, R14, c[0x0][0x178], R11 ; /* 0x00005e000e0b7a24 */
/* 0x000fc400078e020b */
/*0a10*/ IMAD R20, R14.reuse, c[0x0][0x178], R20 ; /* 0x00005e000e147a24 */
/* 0x040fe400078e0214 */
/*0a20*/ IMAD R21, R14, c[0x0][0x178], R21 ; /* 0x00005e000e157a24 */
/* 0x000fe200078e0215 */
/*0a30*/ LDS R26, [R2.X4] ; /* 0x00000000021a7984 */
/* 0x0000680000004800 */
/*0a40*/ STS [R2.X4], R27 ; /* 0x0000001b02007388 */
/* 0x0201e80000004800 */
/*0a50*/ LDS R5, [R4.X4] ; /* 0x0000000004057984 */
/* 0x0000a80000004800 */
/*0a60*/ STS [R4.X4], R25 ; /* 0x0000001904007388 */
/* 0x0001e80000004800 */
/*0a70*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0a80*/ @!P5 BRA 0x570 ; /* 0xfffffae00000d947 */
/* 0x001fea000383ffff */
/*0a90*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0aa0*/ BRA 0xaa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24block2D_hybrid_coarsen_xffPfS_iii
.globl _Z24block2D_hybrid_coarsen_xffPfS_iii
.p2align 8
.type _Z24block2D_hybrid_coarsen_xffPfS_iii,@function
_Z24block2D_hybrid_coarsen_xffPfS_iii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[12:13], s[0:1], 0x18
v_bfe_u32 v10, v0, 10, 10
v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v14, 0x3ff, v0
s_lshl_b32 s19, s14, 1
s_mov_b32 s5, 0
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b32_e32 v5, 1, v10
s_mov_b32 s14, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s18, s2, 0xffff
s_lshr_b32 s4, s2, 16
s_mul_i32 s17, s19, s18
s_mul_i32 s20, s15, s4
v_add_nc_u32_e32 v3, s18, v14
v_add_nc_u32_e32 v0, s17, v14
v_add_nc_u32_e32 v4, s20, v10
v_mad_u32_u24 v2, v5, s18, v14
s_add_i32 s6, s12, -1
v_mad_u32_u24 v7, v5, s18, v3
v_cmp_lt_i32_e64 s2, 0, v0
v_cmp_lt_i32_e32 vcc_lo, 0, v4
v_cmp_gt_i32_e64 s3, s6, v0
v_lshl_add_u32 v15, v2, 2, 0
v_lshl_add_u32 v16, v7, 2, 0
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
ds_store_b32 v15, v1
ds_store_b32 v16, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s3, s2
s_add_i32 s2, s13, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s2, v4
s_and_b32 s14, s2, exec_lo
s_or_b32 exec_lo, exec_lo, s3
v_add_nc_u32_e32 v1, s18, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s6, v1
s_and_b32 s3, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s3
s_add_i32 s3, s13, -1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v4
s_and_b32 s5, vcc_lo, exec_lo
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[6:7], s[0:1], 0x8
v_cmp_gt_i32_e64 s2, s12, v0
v_cmp_gt_i32_e32 vcc_lo, s13, v4
v_mov_b32_e32 v17, 0
v_add_nc_u32_e32 v5, s13, v4
v_mov_b32_e32 v19, 0
s_and_b32 s15, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s15
s_cbranch_execz .LBB0_6
v_mad_u64_u32 v[8:9], null, v5, s12, v[0:1]
v_mad_u64_u32 v[11:12], null, v4, s12, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v9, 31, v8
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v8, s2, s6, v8
v_add_co_ci_u32_e64 v9, s2, s7, v9, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v11, s2, s6, v11
v_add_co_ci_u32_e64 v12, s2, s7, v12, s2
s_clause 0x1
global_load_b32 v0, v[8:9], off
global_load_b32 v19, v[11:12], off
s_waitcnt vmcnt(1)
ds_store_b32 v15, v0
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s3
v_cmp_gt_i32_e64 s2, s12, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s16, s2, vcc_lo
s_and_saveexec_b32 s2, s16
s_cbranch_execz .LBB0_8
v_mad_u64_u32 v[8:9], null, v5, s12, v[1:2]
v_mad_u64_u32 v[5:6], null, v4, s12, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v9, 31, v8
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[8:9]
v_lshlrev_b64 v[4:5], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
s_clause 0x1
global_load_b32 v0, v[0:1], off
global_load_b32 v17, v[4:5], off
s_waitcnt vmcnt(1)
ds_store_b32 v16, v0
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s2
s_load_b32 s21, s[0:1], 0x20
s_waitcnt vmcnt(0) lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cmp_lt_i32 s21, 3
s_cbranch_scc1 .LBB0_31
v_lshl_add_u32 v6, v2, 2, 0
s_lshl_b32 s24, s18, 1
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x0
s_load_b64 s[10:11], s[0:1], 0x10
v_subrev_nc_u32_e32 v1, s24, v2
s_add_i32 s2, s24, -1
v_dual_mov_b32 v29, 0 :: v_dual_add_nc_u32 v0, -4, v6
v_cmp_eq_u32_e64 s2, s2, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshl_add_u32 v3, v1, 2, 0
v_lshl_add_u32 v12, v7, 2, 0
v_cmp_ne_u32_e64 s0, -1, v0
s_mov_b64 s[22:23], src_shared_base
v_add_nc_u32_e32 v2, s24, v2
v_subrev_nc_u32_e32 v5, s24, v7
v_add_nc_u32_e32 v8, 4, v12
v_cndmask_b32_e64 v0, 0, v0, s0
v_cndmask_b32_e64 v1, 0, s23, s0
v_cmp_ne_u32_e64 s0, -1, v3
v_lshl_add_u32 v4, v2, 2, 0
v_add3_u32 v13, s20, s13, v10
v_add_nc_u32_e32 v18, 4, v6
v_dual_mov_b32 v30, 0 :: v_dual_add_nc_u32 v11, s24, v7
v_cndmask_b32_e64 v2, 0, v3, s0
v_cndmask_b32_e64 v3, 0, s23, s0
v_cmp_ne_u32_e64 s0, -1, v8
v_cmp_ne_u32_e64 s1, -1, v4
v_lshl_add_u32 v9, v5, 2, 0
v_mul_lo_u32 v25, s12, v13
v_add_nc_u32_e32 v13, -1, v13
v_cndmask_b32_e64 v6, 0, v8, s0
v_cndmask_b32_e64 v7, 0, s23, s0
s_lshl_b32 s0, s13, 1
v_lshl_add_u32 v11, v11, 2, 0
v_add3_u32 v20, s0, s20, v10
v_cndmask_b32_e64 v4, 0, v4, s1
v_cndmask_b32_e64 v5, 0, s23, s1
v_cmp_ne_u32_e64 s1, -1, v9
v_mul_lo_u32 v13, s12, v13
v_mul_lo_u32 v28, s12, v20
v_cmp_ne_u32_e64 s0, -1, v11
v_add_nc_u32_e32 v26, s12, v25
v_cndmask_b32_e64 v8, 0, v9, s1
v_cndmask_b32_e64 v9, 0, s23, s1
s_add_i32 s1, s19, 1
s_add_i32 s4, s4, -1
s_mul_i32 s1, s1, s18
v_cmp_eq_u32_e32 vcc_lo, 0, v14
v_cmp_eq_u32_e64 s3, 0, v10
v_cmp_eq_u32_e64 s4, s4, v10
v_cndmask_b32_e64 v10, 0, v11, s0
v_cndmask_b32_e64 v11, 0, s23, s0
v_add_nc_u32_e32 v20, -4, v12
v_add_nc_u32_e32 v21, s1, v25
v_add_nc_u32_e32 v22, s1, v26
v_add_nc_u32_e32 v23, s1, v13
v_add_nc_u32_e32 v24, s1, v28
v_add_nc_u32_e32 v25, s17, v25
v_add_nc_u32_e32 v26, s17, v26
v_add_nc_u32_e32 v27, s17, v13
v_add_nc_u32_e32 v28, s17, v28
s_add_i32 s1, s21, -2
s_mul_i32 s12, s13, s12
s_branch .LBB0_12
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s17
flat_load_b32 v12, v[12:13]
ds_load_b32 v13, v20
ds_load_b32 v32, v16
s_waitcnt vmcnt(2) lgkmcnt(0)
v_add_f32_e32 v13, v19, v13
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v12, v12, v13
v_add_f32_e32 v13, v31, v12
v_dual_mul_f32 v31, s8, v32 :: v_dual_add_nc_u32 v12, v21, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v19, v29, v13
v_ashrrev_i32_e32 v13, 31, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v17, v17, v19
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v17, v17, s9, -v31
v_add_co_u32 v12, s0, s10, v12
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v13, s0, s11, v13, s0
global_store_b32 v[12:13], v17, off
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s13
s_waitcnt vmcnt(0) lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
ds_load_b32 v19, v15
ds_store_b32 v15, v30
ds_load_b32 v17, v16
v_add_nc_u32_e32 v14, s12, v14
s_add_i32 s1, s1, -1
ds_store_b32 v16, v29
s_cmp_eq_u32 s1, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_31
.LBB0_12:
s_and_saveexec_b32 s13, s15
s_cbranch_execz .LBB0_14
v_add_nc_u32_e32 v12, v28, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v12, s0, s6, v12
v_add_co_ci_u32_e64 v13, s0, s7, v13, s0
global_load_b32 v30, v[12:13], off
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s13
s_and_saveexec_b32 s13, s14
s_cbranch_execz .LBB0_22
v_dual_mov_b32 v13, v1 :: v_dual_mov_b32 v12, v0
s_and_saveexec_b32 s17, vcc_lo
v_add3_u32 v12, v25, v14, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v12, s0, s6, v12
v_add_co_ci_u32_e64 v13, s0, s7, v13, s0
s_or_b32 exec_lo, exec_lo, s17
flat_load_b32 v31, v[12:13]
v_dual_mov_b32 v13, v3 :: v_dual_mov_b32 v12, v2
s_and_saveexec_b32 s17, s3
v_add_nc_u32_e32 v12, v27, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v12, s0, s6, v12
v_add_co_ci_u32_e64 v13, s0, s7, v13, s0
s_or_b32 exec_lo, exec_lo, s17
flat_load_b32 v32, v[12:13]
v_dual_mov_b32 v13, v5 :: v_dual_mov_b32 v12, v4
s_and_saveexec_b32 s17, s4
v_add_nc_u32_e32 v12, v26, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v12, s0, s6, v12
v_add_co_ci_u32_e64 v13, s0, s7, v13, s0
s_or_b32 exec_lo, exec_lo, s17
flat_load_b32 v12, v[12:13]
ds_load_b32 v13, v18
ds_load_b32 v33, v15
s_waitcnt vmcnt(2) lgkmcnt(0)
v_add_f32_e32 v13, v31, v13
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v12, v12, v13
v_dual_add_f32 v13, v32, v12 :: v_dual_mul_f32 v32, s8, v33
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v31, v30, v13 :: v_dual_add_nc_u32 v12, v25, v14
v_ashrrev_i32_e32 v13, 31, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v19, v19, v31
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v19, v19, s9, -v32
v_add_co_u32 v12, s0, s10, v12
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v13, s0, s11, v13, s0
global_store_b32 v[12:13], v19, off
.LBB0_22:
s_or_b32 exec_lo, exec_lo, s13
s_and_saveexec_b32 s13, s16
s_cbranch_execz .LBB0_24
v_add_nc_u32_e32 v12, v24, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v12, s0, s6, v12
v_add_co_ci_u32_e64 v13, s0, s7, v13, s0
global_load_b32 v29, v[12:13], off
.LBB0_24:
s_or_b32 exec_lo, exec_lo, s13
s_and_saveexec_b32 s13, s5
s_cbranch_execz .LBB0_11
v_dual_mov_b32 v13, v7 :: v_dual_mov_b32 v12, v6
s_and_saveexec_b32 s17, s2
v_add3_u32 v12, v21, v14, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v12, s0, s6, v12
v_add_co_ci_u32_e64 v13, s0, s7, v13, s0
s_or_b32 exec_lo, exec_lo, s17
flat_load_b32 v19, v[12:13]
v_dual_mov_b32 v13, v9 :: v_dual_mov_b32 v12, v8
s_and_saveexec_b32 s17, s3
v_add_nc_u32_e32 v12, v23, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v12, s0, s6, v12
v_add_co_ci_u32_e64 v13, s0, s7, v13, s0
s_or_b32 exec_lo, exec_lo, s17
flat_load_b32 v31, v[12:13]
v_dual_mov_b32 v13, v11 :: v_dual_mov_b32 v12, v10
s_and_saveexec_b32 s17, s4
s_cbranch_execz .LBB0_10
v_add_nc_u32_e32 v12, v22, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v12, s0, s6, v12
v_add_co_ci_u32_e64 v13, s0, s7, v13, s0
s_branch .LBB0_10
.LBB0_31:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24block2D_hybrid_coarsen_xffPfS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 34
.amdhsa_next_free_sgpr 25
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24block2D_hybrid_coarsen_xffPfS_iii, .Lfunc_end0-_Z24block2D_hybrid_coarsen_xffPfS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
- .offset: 160
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24block2D_hybrid_coarsen_xffPfS_iii
.private_segment_fixed_size: 0
.sgpr_count: 27
.sgpr_spill_count: 0
.symbol: _Z24block2D_hybrid_coarsen_xffPfS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 34
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000601f4_00000000-6_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z24block2D_hybrid_coarsen_xffPfS_iiiffPfS_iii
.type _Z51__device_stub__Z24block2D_hybrid_coarsen_xffPfS_iiiffPfS_iii, @function
_Z51__device_stub__Z24block2D_hybrid_coarsen_xffPfS_iiiffPfS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movss %xmm0, 44(%rsp)
movss %xmm1, 40(%rsp)
movq %rdi, 32(%rsp)
movq %rsi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z24block2D_hybrid_coarsen_xffPfS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z51__device_stub__Z24block2D_hybrid_coarsen_xffPfS_iiiffPfS_iii, .-_Z51__device_stub__Z24block2D_hybrid_coarsen_xffPfS_iiiffPfS_iii
.globl _Z24block2D_hybrid_coarsen_xffPfS_iii
.type _Z24block2D_hybrid_coarsen_xffPfS_iii, @function
_Z24block2D_hybrid_coarsen_xffPfS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z24block2D_hybrid_coarsen_xffPfS_iiiffPfS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24block2D_hybrid_coarsen_xffPfS_iii, .-_Z24block2D_hybrid_coarsen_xffPfS_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24block2D_hybrid_coarsen_xffPfS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24block2D_hybrid_coarsen_xffPfS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernels.hip"
.globl _Z39__device_stub__block2D_hybrid_coarsen_xffPfS_iii # -- Begin function _Z39__device_stub__block2D_hybrid_coarsen_xffPfS_iii
.p2align 4, 0x90
.type _Z39__device_stub__block2D_hybrid_coarsen_xffPfS_iii,@function
_Z39__device_stub__block2D_hybrid_coarsen_xffPfS_iii: # @_Z39__device_stub__block2D_hybrid_coarsen_xffPfS_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z24block2D_hybrid_coarsen_xffPfS_iii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z39__device_stub__block2D_hybrid_coarsen_xffPfS_iii, .Lfunc_end0-_Z39__device_stub__block2D_hybrid_coarsen_xffPfS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24block2D_hybrid_coarsen_xffPfS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24block2D_hybrid_coarsen_xffPfS_iii,@object # @_Z24block2D_hybrid_coarsen_xffPfS_iii
.section .rodata,"a",@progbits
.globl _Z24block2D_hybrid_coarsen_xffPfS_iii
.p2align 3, 0x0
_Z24block2D_hybrid_coarsen_xffPfS_iii:
.quad _Z39__device_stub__block2D_hybrid_coarsen_xffPfS_iii
.size _Z24block2D_hybrid_coarsen_xffPfS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24block2D_hybrid_coarsen_xffPfS_iii"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__block2D_hybrid_coarsen_xffPfS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24block2D_hybrid_coarsen_xffPfS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
__global__
void saxpy(int n, float a, float *x, float *y)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < n; i += blockDim.x * gridDim.x)
{
y[i] = a * x[i] + y[i];
__syncthreads();
}
}
int main(void)
{
int N = 1<<25;
printf("%d\n", N);
float *x, *y, *d_x, *d_y;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
x = (float*)malloc(N*sizeof(float));
y = (float*)malloc(N*sizeof(float));
cudaMalloc(&d_x, N*sizeof(float));
cudaMalloc(&d_y, N*sizeof(float));
for (int n = 0; n < N; n++) {
x[n] = 1.0f;
y[n] = 2.0f;
}
cudaMemcpy(d_x, x, N*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_y, y, N*sizeof(float), cudaMemcpyHostToDevice);
int numSMs;
cudaDeviceGetAttribute(&numSMs, cudaDevAttrMultiProcessorCount, 0);
printf("Blocks Threads Max error Elapsed time Eff. Memory Throughput "
"Peak Memory Throughput Eff. Computational Throughput\n");
for(int j =1; j < 10; j++){
for(int i = 1; i < 10; i++){
int numThreads = i*32, numBlocks = j *32;
printf("%d ", numBlocks);
printf("%d ", numThreads);
cudaEventRecord(start);
saxpy<<<numBlocks, numThreads>>>(N, 2.0f, d_x, d_y);
cudaEventRecord(stop);
cudaMemcpy(y, d_y, N*sizeof(float), cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
float maxError = 0.0f;
for (int k = 0; k < N; k++)
maxError = fmaxf(maxError, fabsf(y[k]-4.0f));
printf("%f ", maxError);
printf("%f ", milliseconds);
// for Memory Throughput Benchmarking:
printf("%f GB/s ", 4.0*N*3.0/milliseconds/1.0e6);
int clockRate;
int busWidth;
cudaDeviceGetAttribute(&clockRate, cudaDevAttrMemoryClockRate, 0);
cudaDeviceGetAttribute(&busWidth, cudaDevAttrGlobalMemoryBusWidth, 0);
printf("%f GB/s ", 2.0*clockRate*(busWidth/8.0)/1.0e6);
// for Computational Throughput Benchmarking:
// (1* multiply + 1*add) times the amount of vector entries
printf("%f GFLOP/s \n",(2*N/milliseconds)/1.0e6);
}
}
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaFree(d_x);
cudaFree(d_y);
free(x);
free(y);
} | code for sm_80
Function : _Z5saxpyifPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R0, R5, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fe400078e0205 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ MOV R9, c[0x0][0x0] ; /* 0x0000000000097a02 */
/* 0x000fe20000000f00 */
/*00d0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe80003800000 */
/*00e0*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fe20003f06270 */
/*0100*/ FFMA R7, R2, c[0x0][0x164], R7 ; /* 0x0000590002077a23 */
/* 0x004fca0000000007 */
/*0110*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e8000c101904 */
/*0120*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0130*/ @!P0 BRA 0x70 ; /* 0xffffff3000008947 */
/* 0x000fea000383ffff */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
__global__
void saxpy(int n, float a, float *x, float *y)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < n; i += blockDim.x * gridDim.x)
{
y[i] = a * x[i] + y[i];
__syncthreads();
}
}
int main(void)
{
int N = 1<<25;
printf("%d\n", N);
float *x, *y, *d_x, *d_y;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
x = (float*)malloc(N*sizeof(float));
y = (float*)malloc(N*sizeof(float));
cudaMalloc(&d_x, N*sizeof(float));
cudaMalloc(&d_y, N*sizeof(float));
for (int n = 0; n < N; n++) {
x[n] = 1.0f;
y[n] = 2.0f;
}
cudaMemcpy(d_x, x, N*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_y, y, N*sizeof(float), cudaMemcpyHostToDevice);
int numSMs;
cudaDeviceGetAttribute(&numSMs, cudaDevAttrMultiProcessorCount, 0);
printf("Blocks Threads Max error Elapsed time Eff. Memory Throughput "
"Peak Memory Throughput Eff. Computational Throughput\n");
for(int j =1; j < 10; j++){
for(int i = 1; i < 10; i++){
int numThreads = i*32, numBlocks = j *32;
printf("%d ", numBlocks);
printf("%d ", numThreads);
cudaEventRecord(start);
saxpy<<<numBlocks, numThreads>>>(N, 2.0f, d_x, d_y);
cudaEventRecord(stop);
cudaMemcpy(y, d_y, N*sizeof(float), cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
float maxError = 0.0f;
for (int k = 0; k < N; k++)
maxError = fmaxf(maxError, fabsf(y[k]-4.0f));
printf("%f ", maxError);
printf("%f ", milliseconds);
// for Memory Throughput Benchmarking:
printf("%f GB/s ", 4.0*N*3.0/milliseconds/1.0e6);
int clockRate;
int busWidth;
cudaDeviceGetAttribute(&clockRate, cudaDevAttrMemoryClockRate, 0);
cudaDeviceGetAttribute(&busWidth, cudaDevAttrGlobalMemoryBusWidth, 0);
printf("%f GB/s ", 2.0*clockRate*(busWidth/8.0)/1.0e6);
// for Computational Throughput Benchmarking:
// (1* multiply + 1*add) times the amount of vector entries
printf("%f GFLOP/s \n",(2*N/milliseconds)/1.0e6);
}
}
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaFree(d_x);
cudaFree(d_y);
free(x);
free(y);
} | .file "tmpxft_000e3121_00000000-6_SaxpyCudaBenchmarking.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z5saxpyifPfS_ifPfS_
.type _Z28__device_stub__Z5saxpyifPfS_ifPfS_, @function
_Z28__device_stub__Z5saxpyifPfS_ifPfS_:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5saxpyifPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z5saxpyifPfS_ifPfS_, .-_Z28__device_stub__Z5saxpyifPfS_ifPfS_
.globl _Z5saxpyifPfS_
.type _Z5saxpyifPfS_, @function
_Z5saxpyifPfS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z5saxpyifPfS_ifPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5saxpyifPfS_, .-_Z5saxpyifPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Blocks\tThreads\tMax error\tElapsed time \tEff. Memory Throughput\tPeak Memory Throughput\tEff. Computational Throughput\n"
.section .rodata.str1.1
.LC5:
.string "%d\t"
.LC8:
.string "%f\t"
.LC11:
.string "%f GB/s\t\t"
.LC14:
.string "%f GFLOP/s\t\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $33554432, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $134217728, %edi
call malloc@PLT
movq %rax, %r14
movl $134217728, %edi
call malloc@PLT
movq %rax, %r13
leaq 32(%rsp), %rdi
movl $134217728, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $134217728, %esi
call cudaMalloc@PLT
movl $0, %eax
movss .LC2(%rip), %xmm1
movss .LC3(%rip), %xmm0
.L12:
movss %xmm1, (%r14,%rax)
movss %xmm0, 0(%r13,%rax)
addq $4, %rax
cmpq $134217728, %rax
jne .L12
movl $1, %ecx
movl $134217728, %edx
movq %r14, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $134217728, %edx
movq %r13, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movl $0, %edx
movl $16, %esi
call cudaDeviceGetAttribute@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $32, %r15d
jmp .L13
.L14:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $134217728, %edx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 28(%rsp)
leaq 28(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq %r13, %rbx
leaq 134217728(%r13), %rbp
pxor %xmm1, %xmm1
.L15:
movss (%rbx), %xmm2
subss .LC6(%rip), %xmm2
andps .LC7(%rip), %xmm2
movaps %xmm2, %xmm0
call fmaxf@PLT
movaps %xmm0, %xmm1
addq $4, %rbx
cmpq %rbp, %rbx
jne .L15
cvtss2sd %xmm0, %xmm0
leaq .LC8(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 28(%rsp), %xmm0
movq %rbx, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm1, %xmm1
cvtss2sd 28(%rsp), %xmm1
movsd .LC9(%rip), %xmm0
divsd %xmm1, %xmm0
divsd .LC10(%rip), %xmm0
leaq .LC11(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 64(%rsp), %rdi
movl $0, %edx
movl $36, %esi
call cudaDeviceGetAttribute@PLT
leaq 76(%rsp), %rdi
movl $0, %edx
movl $37, %esi
call cudaDeviceGetAttribute@PLT
pxor %xmm0, %xmm0
cvtsi2sdl 64(%rsp), %xmm0
addsd %xmm0, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl 76(%rsp), %xmm1
mulsd .LC12(%rip), %xmm1
mulsd %xmm1, %xmm0
divsd .LC10(%rip), %xmm0
movq %rbx, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss .LC13(%rip), %xmm0
divss 28(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LC10(%rip), %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $32, %r12d
cmpl $320, %r12d
je .L23
.L16:
movl 12(%rsp), %edx
leaq .LC5(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl %r12d, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl %r15d, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L14
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movss .LC3(%rip), %xmm0
movl $33554432, %edi
call _Z28__device_stub__Z5saxpyifPfS_ifPfS_
jmp .L14
.L23:
addl $32, %r15d
cmpl $320, %r15d
je .L17
.L13:
movl %r15d, 12(%rsp)
movl $32, %r12d
jmp .L16
.L17:
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC15:
.string "_Z5saxpyifPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z5saxpyifPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1065353216
.align 4
.LC3:
.long 1073741824
.align 4
.LC6:
.long 1082130432
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC7:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC9:
.long 0
.long 1102577664
.align 8
.LC10:
.long 0
.long 1093567616
.align 8
.LC12:
.long 0
.long 1069547520
.section .rodata.cst4
.align 4
.LC13:
.long 1283457024
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
__global__
void saxpy(int n, float a, float *x, float *y)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < n; i += blockDim.x * gridDim.x)
{
y[i] = a * x[i] + y[i];
__syncthreads();
}
}
int main(void)
{
int N = 1<<25;
printf("%d\n", N);
float *x, *y, *d_x, *d_y;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
x = (float*)malloc(N*sizeof(float));
y = (float*)malloc(N*sizeof(float));
cudaMalloc(&d_x, N*sizeof(float));
cudaMalloc(&d_y, N*sizeof(float));
for (int n = 0; n < N; n++) {
x[n] = 1.0f;
y[n] = 2.0f;
}
cudaMemcpy(d_x, x, N*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_y, y, N*sizeof(float), cudaMemcpyHostToDevice);
int numSMs;
cudaDeviceGetAttribute(&numSMs, cudaDevAttrMultiProcessorCount, 0);
printf("Blocks Threads Max error Elapsed time Eff. Memory Throughput "
"Peak Memory Throughput Eff. Computational Throughput\n");
for(int j =1; j < 10; j++){
for(int i = 1; i < 10; i++){
int numThreads = i*32, numBlocks = j *32;
printf("%d ", numBlocks);
printf("%d ", numThreads);
cudaEventRecord(start);
saxpy<<<numBlocks, numThreads>>>(N, 2.0f, d_x, d_y);
cudaEventRecord(stop);
cudaMemcpy(y, d_y, N*sizeof(float), cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
float maxError = 0.0f;
for (int k = 0; k < N; k++)
maxError = fmaxf(maxError, fabsf(y[k]-4.0f));
printf("%f ", maxError);
printf("%f ", milliseconds);
// for Memory Throughput Benchmarking:
printf("%f GB/s ", 4.0*N*3.0/milliseconds/1.0e6);
int clockRate;
int busWidth;
cudaDeviceGetAttribute(&clockRate, cudaDevAttrMemoryClockRate, 0);
cudaDeviceGetAttribute(&busWidth, cudaDevAttrGlobalMemoryBusWidth, 0);
printf("%f GB/s ", 2.0*clockRate*(busWidth/8.0)/1.0e6);
// for Computational Throughput Benchmarking:
// (1* multiply + 1*add) times the amount of vector entries
printf("%f GFLOP/s \n",(2*N/milliseconds)/1.0e6);
}
}
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaFree(d_x);
cudaFree(d_y);
free(x);
free(y);
} | #include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
__global__
void saxpy(int n, float a, float *x, float *y)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < n; i += blockDim.x * gridDim.x)
{
y[i] = a * x[i] + y[i];
__syncthreads();
}
}
int main(void)
{
int N = 1<<25;
printf("%d\n", N);
float *x, *y, *d_x, *d_y;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
x = (float*)malloc(N*sizeof(float));
y = (float*)malloc(N*sizeof(float));
hipMalloc(&d_x, N*sizeof(float));
hipMalloc(&d_y, N*sizeof(float));
for (int n = 0; n < N; n++) {
x[n] = 1.0f;
y[n] = 2.0f;
}
hipMemcpy(d_x, x, N*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_y, y, N*sizeof(float), hipMemcpyHostToDevice);
int numSMs;
hipDeviceGetAttribute(&numSMs, hipDeviceAttributeMultiprocessorCount, 0);
printf("Blocks Threads Max error Elapsed time Eff. Memory Throughput "
"Peak Memory Throughput Eff. Computational Throughput\n");
for(int j =1; j < 10; j++){
for(int i = 1; i < 10; i++){
int numThreads = i*32, numBlocks = j *32;
printf("%d ", numBlocks);
printf("%d ", numThreads);
hipEventRecord(start);
saxpy<<<numBlocks, numThreads>>>(N, 2.0f, d_x, d_y);
hipEventRecord(stop);
hipMemcpy(y, d_y, N*sizeof(float), hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
float maxError = 0.0f;
for (int k = 0; k < N; k++)
maxError = fmaxf(maxError, fabsf(y[k]-4.0f));
printf("%f ", maxError);
printf("%f ", milliseconds);
// for Memory Throughput Benchmarking:
printf("%f GB/s ", 4.0*N*3.0/milliseconds/1.0e6);
int clockRate;
int busWidth;
hipDeviceGetAttribute(&clockRate, hipDeviceAttributeMemoryClockRate, 0);
hipDeviceGetAttribute(&busWidth, hipDeviceAttributeMemoryBusWidth, 0);
printf("%f GB/s ", 2.0*clockRate*(busWidth/8.0)/1.0e6);
// for Computational Throughput Benchmarking:
// (1* multiply + 1*add) times the amount of vector entries
printf("%f GFLOP/s \n",(2*N/milliseconds)/1.0e6);
}
}
hipEventDestroy(start);
hipEventDestroy(stop);
hipFree(d_x);
hipFree(d_y);
free(x);
free(y);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
__global__
void saxpy(int n, float a, float *x, float *y)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < n; i += blockDim.x * gridDim.x)
{
y[i] = a * x[i] + y[i];
__syncthreads();
}
}
int main(void)
{
int N = 1<<25;
printf("%d\n", N);
float *x, *y, *d_x, *d_y;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
x = (float*)malloc(N*sizeof(float));
y = (float*)malloc(N*sizeof(float));
hipMalloc(&d_x, N*sizeof(float));
hipMalloc(&d_y, N*sizeof(float));
for (int n = 0; n < N; n++) {
x[n] = 1.0f;
y[n] = 2.0f;
}
hipMemcpy(d_x, x, N*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_y, y, N*sizeof(float), hipMemcpyHostToDevice);
int numSMs;
hipDeviceGetAttribute(&numSMs, hipDeviceAttributeMultiprocessorCount, 0);
printf("Blocks Threads Max error Elapsed time Eff. Memory Throughput "
"Peak Memory Throughput Eff. Computational Throughput\n");
for(int j =1; j < 10; j++){
for(int i = 1; i < 10; i++){
int numThreads = i*32, numBlocks = j *32;
printf("%d ", numBlocks);
printf("%d ", numThreads);
hipEventRecord(start);
saxpy<<<numBlocks, numThreads>>>(N, 2.0f, d_x, d_y);
hipEventRecord(stop);
hipMemcpy(y, d_y, N*sizeof(float), hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
float maxError = 0.0f;
for (int k = 0; k < N; k++)
maxError = fmaxf(maxError, fabsf(y[k]-4.0f));
printf("%f ", maxError);
printf("%f ", milliseconds);
// for Memory Throughput Benchmarking:
printf("%f GB/s ", 4.0*N*3.0/milliseconds/1.0e6);
int clockRate;
int busWidth;
hipDeviceGetAttribute(&clockRate, hipDeviceAttributeMemoryClockRate, 0);
hipDeviceGetAttribute(&busWidth, hipDeviceAttributeMemoryBusWidth, 0);
printf("%f GB/s ", 2.0*clockRate*(busWidth/8.0)/1.0e6);
// for Computational Throughput Benchmarking:
// (1* multiply + 1*add) times the amount of vector entries
printf("%f GFLOP/s \n",(2*N/milliseconds)/1.0e6);
}
}
hipEventDestroy(start);
hipEventDestroy(stop);
hipFree(d_x);
hipFree(d_y);
free(x);
free(y);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5saxpyifPfS_
.globl _Z5saxpyifPfS_
.p2align 8
.type _Z5saxpyifPfS_,@function
_Z5saxpyifPfS_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s5, 0xffff
s_mov_b32 s5, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_3
s_load_b32 s7, s[2:3], 0x0
s_clause 0x1
s_load_b32 s5, s[0:1], 0x4
s_load_b128 s[0:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_mul_i32 s6, s7, s6
s_mov_b32 s7, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_dual_fmac_f32 v4, s5, v0 :: v_dual_add_nc_u32 v1, s6, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_le_i32_e32 vcc_lo, s4, v1
global_store_b32 v[2:3], v4, off
s_or_b32 s7, vcc_lo, s7
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5saxpyifPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5saxpyifPfS_, .Lfunc_end0-_Z5saxpyifPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5saxpyifPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5saxpyifPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
__global__
void saxpy(int n, float a, float *x, float *y)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < n; i += blockDim.x * gridDim.x)
{
y[i] = a * x[i] + y[i];
__syncthreads();
}
}
int main(void)
{
int N = 1<<25;
printf("%d\n", N);
float *x, *y, *d_x, *d_y;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
x = (float*)malloc(N*sizeof(float));
y = (float*)malloc(N*sizeof(float));
hipMalloc(&d_x, N*sizeof(float));
hipMalloc(&d_y, N*sizeof(float));
for (int n = 0; n < N; n++) {
x[n] = 1.0f;
y[n] = 2.0f;
}
hipMemcpy(d_x, x, N*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_y, y, N*sizeof(float), hipMemcpyHostToDevice);
int numSMs;
hipDeviceGetAttribute(&numSMs, hipDeviceAttributeMultiprocessorCount, 0);
printf("Blocks Threads Max error Elapsed time Eff. Memory Throughput "
"Peak Memory Throughput Eff. Computational Throughput\n");
for(int j =1; j < 10; j++){
for(int i = 1; i < 10; i++){
int numThreads = i*32, numBlocks = j *32;
printf("%d ", numBlocks);
printf("%d ", numThreads);
hipEventRecord(start);
saxpy<<<numBlocks, numThreads>>>(N, 2.0f, d_x, d_y);
hipEventRecord(stop);
hipMemcpy(y, d_y, N*sizeof(float), hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
float maxError = 0.0f;
for (int k = 0; k < N; k++)
maxError = fmaxf(maxError, fabsf(y[k]-4.0f));
printf("%f ", maxError);
printf("%f ", milliseconds);
// for Memory Throughput Benchmarking:
printf("%f GB/s ", 4.0*N*3.0/milliseconds/1.0e6);
int clockRate;
int busWidth;
hipDeviceGetAttribute(&clockRate, hipDeviceAttributeMemoryClockRate, 0);
hipDeviceGetAttribute(&busWidth, hipDeviceAttributeMemoryBusWidth, 0);
printf("%f GB/s ", 2.0*clockRate*(busWidth/8.0)/1.0e6);
// for Computational Throughput Benchmarking:
// (1* multiply + 1*add) times the amount of vector entries
printf("%f GFLOP/s \n",(2*N/milliseconds)/1.0e6);
}
}
hipEventDestroy(start);
hipEventDestroy(stop);
hipFree(d_x);
hipFree(d_y);
free(x);
free(y);
} | .text
.file "SaxpyCudaBenchmarking.hip"
.globl _Z20__device_stub__saxpyifPfS_ # -- Begin function _Z20__device_stub__saxpyifPfS_
.p2align 4, 0x90
.type _Z20__device_stub__saxpyifPfS_,@function
_Z20__device_stub__saxpyifPfS_: # @_Z20__device_stub__saxpyifPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5saxpyifPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__saxpyifPfS_, .Lfunc_end0-_Z20__device_stub__saxpyifPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0xc0800000 # float -4
.LCPI1_5:
.long 0x4c800000 # float 67108864
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_2:
.quad 0x41b8000000000000 # double 402653184
.LCPI1_3:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI1_4:
.quad 0x3fc0000000000000 # double 0.125
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %ebx, %ebx
movl $.L.str, %edi
movl $33554432, %esi # imm = 0x2000000
xorl %eax, %eax
callq printf
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movl $134217728, %edi # imm = 0x8000000
callq malloc
movq %rax, %r15
movl $134217728, %edi # imm = 0x8000000
callq malloc
movq %rax, %r14
leaq 32(%rsp), %rdi
movl $134217728, %esi # imm = 0x8000000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $134217728, %esi # imm = 0x8000000
callq hipMalloc
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%r15,%rbx,4) # imm = 0x3F800000
movl $1073741824, (%r14,%rbx,4) # imm = 0x40000000
incq %rbx
cmpq $33554432, %rbx # imm = 0x2000000
jne .LBB1_1
# %bb.2:
movq 32(%rsp), %rdi
movl $134217728, %edx # imm = 0x8000000
movq %r15, 112(%rsp) # 8-byte Spill
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $134217728, %edx # imm = 0x8000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 164(%rsp), %rdi
movl $63, %esi
xorl %edx, %edx
callq hipDeviceGetAttribute
movl $.Lstr, %edi
callq puts@PLT
movl $1, %r13d
leaq 80(%rsp), %rbx
.p2align 4, 0x90
.LBB1_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
# Child Loop BB1_7 Depth 3
movq %r13, 120(%rsp) # 8-byte Spill
shlq $5, %r13
movq %r13, %rbp
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rbp
movl $1, %r12d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_3 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_7 Depth 3
movq %r12, %r15
shlq $5, %r15
movl $.L.str.2, %edi
movl %r13d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r15
movq %rbp, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5: # in Loop: Header=BB1_4 Depth=2
movq 32(%rsp), %rax
movq 16(%rsp), %rcx
movl $33554432, 44(%rsp) # imm = 0x2000000
movl $1073741824, 40(%rsp) # imm = 0x40000000
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
leaq 44(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rax
movq %rax, 88(%rsp)
leaq 152(%rsp), %rax
movq %rax, 96(%rsp)
leaq 144(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 136(%rsp), %rdx
leaq 128(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z5saxpyifPfS_, %edi
movq %rbx, %r9
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6: # in Loop: Header=BB1_4 Depth=2
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rsi
movl $134217728, %edx # imm = 0x8000000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipEventSynchronize
movl $0, 80(%rsp)
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
movq %rbx, %rdi
callq hipEventElapsedTime
xorps %xmm1, %xmm1
xorl %eax, %eax
movaps %xmm1, %xmm0
movss .LCPI1_0(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
movaps .LCPI1_1(%rip), %xmm5 # xmm5 = [NaN,NaN,NaN,NaN]
.p2align 4, 0x90
.LBB1_7: # Parent Loop BB1_3 Depth=1
# Parent Loop BB1_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r14,%rax,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm4, %xmm2
andps %xmm5, %xmm2
cmpunordss %xmm0, %xmm0
movaps %xmm0, %xmm3
andps %xmm2, %xmm3
maxss %xmm1, %xmm2
andnps %xmm2, %xmm0
orps %xmm3, %xmm0
incq %rax
movaps %xmm0, %xmm1
cmpq $33554432, %rax # imm = 0x2000000
jne .LBB1_7
# %bb.8: # in Loop: Header=BB1_4 Depth=2
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movss 80(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movss 80(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorps %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
movsd .LCPI1_2(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movsd .LCPI1_3(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
leaq 64(%rsp), %rdi
movl $60, %esi
xorl %edx, %edx
callq hipDeviceGetAttribute
leaq 48(%rsp), %rdi
movl $59, %esi
xorl %edx, %edx
callq hipDeviceGetAttribute
xorps %xmm1, %xmm1
cvtsi2sdl 64(%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdl 48(%rsp), %xmm0
addsd %xmm1, %xmm1
mulsd .LCPI1_4(%rip), %xmm0
mulsd %xmm1, %xmm0
divsd .LCPI1_3(%rip), %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movss .LCPI1_5(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss 80(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LCPI1_3(%rip), %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
incq %r12
cmpq $10, %r12
jne .LBB1_4
# %bb.9: # in Loop: Header=BB1_3 Depth=1
movq 120(%rsp), %r13 # 8-byte Reload
incq %r13
cmpq $10, %r13
jne .LBB1_3
# %bb.10:
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 112(%rsp), %rdi # 8-byte Reload
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5saxpyifPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5saxpyifPfS_,@object # @_Z5saxpyifPfS_
.section .rodata,"a",@progbits
.globl _Z5saxpyifPfS_
.p2align 3, 0x0
_Z5saxpyifPfS_:
.quad _Z20__device_stub__saxpyifPfS_
.size _Z5saxpyifPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\n"
.size .L.str, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d\t"
.size .L.str.2, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%f\t"
.size .L.str.3, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%f GB/s\t\t"
.size .L.str.4, 10
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%f GFLOP/s\t\n"
.size .L.str.5, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5saxpyifPfS_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Blocks\tThreads\tMax error\tElapsed time \tEff. Memory Throughput\tPeak Memory Throughput\tEff. Computational Throughput"
.size .Lstr, 115
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__saxpyifPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5saxpyifPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5saxpyifPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R0, R5, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fe400078e0205 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ MOV R9, c[0x0][0x0] ; /* 0x0000000000097a02 */
/* 0x000fe20000000f00 */
/*00d0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe80003800000 */
/*00e0*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fe20003f06270 */
/*0100*/ FFMA R7, R2, c[0x0][0x164], R7 ; /* 0x0000590002077a23 */
/* 0x004fca0000000007 */
/*0110*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e8000c101904 */
/*0120*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0130*/ @!P0 BRA 0x70 ; /* 0xffffff3000008947 */
/* 0x000fea000383ffff */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5saxpyifPfS_
.globl _Z5saxpyifPfS_
.p2align 8
.type _Z5saxpyifPfS_,@function
_Z5saxpyifPfS_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s5, 0xffff
s_mov_b32 s5, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_3
s_load_b32 s7, s[2:3], 0x0
s_clause 0x1
s_load_b32 s5, s[0:1], 0x4
s_load_b128 s[0:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_mul_i32 s6, s7, s6
s_mov_b32 s7, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_dual_fmac_f32 v4, s5, v0 :: v_dual_add_nc_u32 v1, s6, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_le_i32_e32 vcc_lo, s4, v1
global_store_b32 v[2:3], v4, off
s_or_b32 s7, vcc_lo, s7
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5saxpyifPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5saxpyifPfS_, .Lfunc_end0-_Z5saxpyifPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5saxpyifPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5saxpyifPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e3121_00000000-6_SaxpyCudaBenchmarking.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z5saxpyifPfS_ifPfS_
.type _Z28__device_stub__Z5saxpyifPfS_ifPfS_, @function
_Z28__device_stub__Z5saxpyifPfS_ifPfS_:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5saxpyifPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z5saxpyifPfS_ifPfS_, .-_Z28__device_stub__Z5saxpyifPfS_ifPfS_
.globl _Z5saxpyifPfS_
.type _Z5saxpyifPfS_, @function
_Z5saxpyifPfS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z5saxpyifPfS_ifPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5saxpyifPfS_, .-_Z5saxpyifPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Blocks\tThreads\tMax error\tElapsed time \tEff. Memory Throughput\tPeak Memory Throughput\tEff. Computational Throughput\n"
.section .rodata.str1.1
.LC5:
.string "%d\t"
.LC8:
.string "%f\t"
.LC11:
.string "%f GB/s\t\t"
.LC14:
.string "%f GFLOP/s\t\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $33554432, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $134217728, %edi
call malloc@PLT
movq %rax, %r14
movl $134217728, %edi
call malloc@PLT
movq %rax, %r13
leaq 32(%rsp), %rdi
movl $134217728, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $134217728, %esi
call cudaMalloc@PLT
movl $0, %eax
movss .LC2(%rip), %xmm1
movss .LC3(%rip), %xmm0
.L12:
movss %xmm1, (%r14,%rax)
movss %xmm0, 0(%r13,%rax)
addq $4, %rax
cmpq $134217728, %rax
jne .L12
movl $1, %ecx
movl $134217728, %edx
movq %r14, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $134217728, %edx
movq %r13, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movl $0, %edx
movl $16, %esi
call cudaDeviceGetAttribute@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $32, %r15d
jmp .L13
.L14:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $134217728, %edx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 28(%rsp)
leaq 28(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq %r13, %rbx
leaq 134217728(%r13), %rbp
pxor %xmm1, %xmm1
.L15:
movss (%rbx), %xmm2
subss .LC6(%rip), %xmm2
andps .LC7(%rip), %xmm2
movaps %xmm2, %xmm0
call fmaxf@PLT
movaps %xmm0, %xmm1
addq $4, %rbx
cmpq %rbp, %rbx
jne .L15
cvtss2sd %xmm0, %xmm0
leaq .LC8(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 28(%rsp), %xmm0
movq %rbx, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm1, %xmm1
cvtss2sd 28(%rsp), %xmm1
movsd .LC9(%rip), %xmm0
divsd %xmm1, %xmm0
divsd .LC10(%rip), %xmm0
leaq .LC11(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 64(%rsp), %rdi
movl $0, %edx
movl $36, %esi
call cudaDeviceGetAttribute@PLT
leaq 76(%rsp), %rdi
movl $0, %edx
movl $37, %esi
call cudaDeviceGetAttribute@PLT
pxor %xmm0, %xmm0
cvtsi2sdl 64(%rsp), %xmm0
addsd %xmm0, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl 76(%rsp), %xmm1
mulsd .LC12(%rip), %xmm1
mulsd %xmm1, %xmm0
divsd .LC10(%rip), %xmm0
movq %rbx, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss .LC13(%rip), %xmm0
divss 28(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LC10(%rip), %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $32, %r12d
cmpl $320, %r12d
je .L23
.L16:
movl 12(%rsp), %edx
leaq .LC5(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl %r12d, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl %r15d, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L14
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movss .LC3(%rip), %xmm0
movl $33554432, %edi
call _Z28__device_stub__Z5saxpyifPfS_ifPfS_
jmp .L14
.L23:
addl $32, %r15d
cmpl $320, %r15d
je .L17
.L13:
movl %r15d, 12(%rsp)
movl $32, %r12d
jmp .L16
.L17:
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC15:
.string "_Z5saxpyifPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z5saxpyifPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1065353216
.align 4
.LC3:
.long 1073741824
.align 4
.LC6:
.long 1082130432
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC7:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC9:
.long 0
.long 1102577664
.align 8
.LC10:
.long 0
.long 1093567616
.align 8
.LC12:
.long 0
.long 1069547520
.section .rodata.cst4
.align 4
.LC13:
.long 1283457024
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "SaxpyCudaBenchmarking.hip"
.globl _Z20__device_stub__saxpyifPfS_ # -- Begin function _Z20__device_stub__saxpyifPfS_
.p2align 4, 0x90
.type _Z20__device_stub__saxpyifPfS_,@function
_Z20__device_stub__saxpyifPfS_: # @_Z20__device_stub__saxpyifPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5saxpyifPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__saxpyifPfS_, .Lfunc_end0-_Z20__device_stub__saxpyifPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0xc0800000 # float -4
.LCPI1_5:
.long 0x4c800000 # float 67108864
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_2:
.quad 0x41b8000000000000 # double 402653184
.LCPI1_3:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI1_4:
.quad 0x3fc0000000000000 # double 0.125
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %ebx, %ebx
movl $.L.str, %edi
movl $33554432, %esi # imm = 0x2000000
xorl %eax, %eax
callq printf
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movl $134217728, %edi # imm = 0x8000000
callq malloc
movq %rax, %r15
movl $134217728, %edi # imm = 0x8000000
callq malloc
movq %rax, %r14
leaq 32(%rsp), %rdi
movl $134217728, %esi # imm = 0x8000000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $134217728, %esi # imm = 0x8000000
callq hipMalloc
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%r15,%rbx,4) # imm = 0x3F800000
movl $1073741824, (%r14,%rbx,4) # imm = 0x40000000
incq %rbx
cmpq $33554432, %rbx # imm = 0x2000000
jne .LBB1_1
# %bb.2:
movq 32(%rsp), %rdi
movl $134217728, %edx # imm = 0x8000000
movq %r15, 112(%rsp) # 8-byte Spill
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $134217728, %edx # imm = 0x8000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 164(%rsp), %rdi
movl $63, %esi
xorl %edx, %edx
callq hipDeviceGetAttribute
movl $.Lstr, %edi
callq puts@PLT
movl $1, %r13d
leaq 80(%rsp), %rbx
.p2align 4, 0x90
.LBB1_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
# Child Loop BB1_7 Depth 3
movq %r13, 120(%rsp) # 8-byte Spill
shlq $5, %r13
movq %r13, %rbp
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rbp
movl $1, %r12d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_3 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_7 Depth 3
movq %r12, %r15
shlq $5, %r15
movl $.L.str.2, %edi
movl %r13d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r15
movq %rbp, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5: # in Loop: Header=BB1_4 Depth=2
movq 32(%rsp), %rax
movq 16(%rsp), %rcx
movl $33554432, 44(%rsp) # imm = 0x2000000
movl $1073741824, 40(%rsp) # imm = 0x40000000
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
leaq 44(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rax
movq %rax, 88(%rsp)
leaq 152(%rsp), %rax
movq %rax, 96(%rsp)
leaq 144(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 136(%rsp), %rdx
leaq 128(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z5saxpyifPfS_, %edi
movq %rbx, %r9
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6: # in Loop: Header=BB1_4 Depth=2
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rsi
movl $134217728, %edx # imm = 0x8000000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipEventSynchronize
movl $0, 80(%rsp)
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
movq %rbx, %rdi
callq hipEventElapsedTime
xorps %xmm1, %xmm1
xorl %eax, %eax
movaps %xmm1, %xmm0
movss .LCPI1_0(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
movaps .LCPI1_1(%rip), %xmm5 # xmm5 = [NaN,NaN,NaN,NaN]
.p2align 4, 0x90
.LBB1_7: # Parent Loop BB1_3 Depth=1
# Parent Loop BB1_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r14,%rax,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm4, %xmm2
andps %xmm5, %xmm2
cmpunordss %xmm0, %xmm0
movaps %xmm0, %xmm3
andps %xmm2, %xmm3
maxss %xmm1, %xmm2
andnps %xmm2, %xmm0
orps %xmm3, %xmm0
incq %rax
movaps %xmm0, %xmm1
cmpq $33554432, %rax # imm = 0x2000000
jne .LBB1_7
# %bb.8: # in Loop: Header=BB1_4 Depth=2
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movss 80(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movss 80(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorps %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
movsd .LCPI1_2(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movsd .LCPI1_3(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
leaq 64(%rsp), %rdi
movl $60, %esi
xorl %edx, %edx
callq hipDeviceGetAttribute
leaq 48(%rsp), %rdi
movl $59, %esi
xorl %edx, %edx
callq hipDeviceGetAttribute
xorps %xmm1, %xmm1
cvtsi2sdl 64(%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdl 48(%rsp), %xmm0
addsd %xmm1, %xmm1
mulsd .LCPI1_4(%rip), %xmm0
mulsd %xmm1, %xmm0
divsd .LCPI1_3(%rip), %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movss .LCPI1_5(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss 80(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LCPI1_3(%rip), %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
incq %r12
cmpq $10, %r12
jne .LBB1_4
# %bb.9: # in Loop: Header=BB1_3 Depth=1
movq 120(%rsp), %r13 # 8-byte Reload
incq %r13
cmpq $10, %r13
jne .LBB1_3
# %bb.10:
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 112(%rsp), %rdi # 8-byte Reload
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5saxpyifPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5saxpyifPfS_,@object # @_Z5saxpyifPfS_
.section .rodata,"a",@progbits
.globl _Z5saxpyifPfS_
.p2align 3, 0x0
_Z5saxpyifPfS_:
.quad _Z20__device_stub__saxpyifPfS_
.size _Z5saxpyifPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\n"
.size .L.str, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d\t"
.size .L.str.2, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%f\t"
.size .L.str.3, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%f GB/s\t\t"
.size .L.str.4, 10
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%f GFLOP/s\t\n"
.size .L.str.5, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5saxpyifPfS_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Blocks\tThreads\tMax error\tElapsed time \tEff. Memory Throughput\tPeak Memory Throughput\tEff. Computational Throughput"
.size .Lstr, 115
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__saxpyifPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5saxpyifPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void colorToGray(unsigned char *input, unsigned char *output, int height, int width)
{
int col= blockDim.x * blockIdx.x + threadIdx.x;
int row = blockDim.y * blockIdx.y + threadIdx.y;
float scale[3] = {0.299, 0.587, 0.114};
if (row < height && col < width)
{
int pixelIndex = row * width + col;
int rgbIndex = pixelIndex * 3;
unsigned char r = input[rgbIndex]; // rgb rgb rgb rgb rgb
unsigned char g = input[rgbIndex + 1];
unsigned char b = input[rgbIndex + 2];
output[pixelIndex] = r* scale[0] + g * scale[1] + b*scale[2];
}
} | code for sm_80
Function : _Z11colorToGrayPhS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x170], P0 ; /* 0x00005c0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R0, R3, c[0x0][0x174], R0 ; /* 0x00005d0003007a24 */
/* 0x000fe200078e0200 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00c0*/ IMAD R3, R0, 0x3, RZ ; /* 0x0000000300037824 */
/* 0x000fca00078e02ff */
/*00d0*/ IADD3 R2, P0, R3, c[0x0][0x160], RZ ; /* 0x0000580003027a10 */
/* 0x000fc80007f1e0ff */
/*00e0*/ LEA.HI.X.SX32 R3, R3, c[0x0][0x164], 0x1, P0 ; /* 0x0000590003037a11 */
/* 0x000fca00000f0eff */
/*00f0*/ LDG.E.U8 R7, [R2.64+0x1] ; /* 0x0000010402077981 */
/* 0x000ea8000c1e1100 */
/*0100*/ LDG.E.U8 R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ee8000c1e1100 */
/*0110*/ LDG.E.U8 R8, [R2.64+0x2] ; /* 0x0000020402087981 */
/* 0x000f22000c1e1100 */
/*0120*/ IADD3 R4, P0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000047a10 */
/* 0x000fe20007f1e0ff */
/*0130*/ I2F.U16 R7, R7 ; /* 0x0000000700077306 */
/* 0x004e300000101000 */
/*0140*/ I2F.U16 R6, R6 ; /* 0x0000000600067306 */
/* 0x008e700000101000 */
/*0150*/ I2F.U16 R8, R8 ; /* 0x0000000800087306 */
/* 0x010ea20000101000 */
/*0160*/ FMUL R5, R7, 0.58700001239776611328 ; /* 0x3f1645a207057820 */
/* 0x001fc80000400000 */
/*0170*/ FFMA R5, R6, 0.29899999499320983887, R5 ; /* 0x3e99168706057823 */
/* 0x002fc80000000005 */
/*0180*/ FFMA R9, R8, 0.11400000005960464478, R5 ; /* 0x3de978d508097823 */
/* 0x004fe20000000005 */
/*0190*/ LEA.HI.X.SX32 R5, R0, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0000057a11 */
/* 0x000fca00000f0eff */
/*01a0*/ F2I.U32.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e24000020f000 */
/*01b0*/ STG.E.U8 [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x001fe2000c101104 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void colorToGray(unsigned char *input, unsigned char *output, int height, int width)
{
int col= blockDim.x * blockIdx.x + threadIdx.x;
int row = blockDim.y * blockIdx.y + threadIdx.y;
float scale[3] = {0.299, 0.587, 0.114};
if (row < height && col < width)
{
int pixelIndex = row * width + col;
int rgbIndex = pixelIndex * 3;
unsigned char r = input[rgbIndex]; // rgb rgb rgb rgb rgb
unsigned char g = input[rgbIndex + 1];
unsigned char b = input[rgbIndex + 2];
output[pixelIndex] = r* scale[0] + g * scale[1] + b*scale[2];
}
} | .file "tmpxft_00013430_00000000-6_colorToGray.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z11colorToGrayPhS_iiPhS_ii
.type _Z35__device_stub__Z11colorToGrayPhS_iiPhS_ii, @function
_Z35__device_stub__Z11colorToGrayPhS_iiPhS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11colorToGrayPhS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z11colorToGrayPhS_iiPhS_ii, .-_Z35__device_stub__Z11colorToGrayPhS_iiPhS_ii
.globl _Z11colorToGrayPhS_ii
.type _Z11colorToGrayPhS_ii, @function
_Z11colorToGrayPhS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11colorToGrayPhS_iiPhS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11colorToGrayPhS_ii, .-_Z11colorToGrayPhS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11colorToGrayPhS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11colorToGrayPhS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void colorToGray(unsigned char *input, unsigned char *output, int height, int width)
{
int col= blockDim.x * blockIdx.x + threadIdx.x;
int row = blockDim.y * blockIdx.y + threadIdx.y;
float scale[3] = {0.299, 0.587, 0.114};
if (row < height && col < width)
{
int pixelIndex = row * width + col;
int rgbIndex = pixelIndex * 3;
unsigned char r = input[rgbIndex]; // rgb rgb rgb rgb rgb
unsigned char g = input[rgbIndex + 1];
unsigned char b = input[rgbIndex + 2];
output[pixelIndex] = r* scale[0] + g * scale[1] + b*scale[2];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void colorToGray(unsigned char *input, unsigned char *output, int height, int width)
{
int col= blockDim.x * blockIdx.x + threadIdx.x;
int row = blockDim.y * blockIdx.y + threadIdx.y;
float scale[3] = {0.299, 0.587, 0.114};
if (row < height && col < width)
{
int pixelIndex = row * width + col;
int rgbIndex = pixelIndex * 3;
unsigned char r = input[rgbIndex]; // rgb rgb rgb rgb rgb
unsigned char g = input[rgbIndex + 1];
unsigned char b = input[rgbIndex + 2];
output[pixelIndex] = r* scale[0] + g * scale[1] + b*scale[2];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void colorToGray(unsigned char *input, unsigned char *output, int height, int width)
{
int col= blockDim.x * blockIdx.x + threadIdx.x;
int row = blockDim.y * blockIdx.y + threadIdx.y;
float scale[3] = {0.299, 0.587, 0.114};
if (row < height && col < width)
{
int pixelIndex = row * width + col;
int rgbIndex = pixelIndex * 3;
unsigned char r = input[rgbIndex]; // rgb rgb rgb rgb rgb
unsigned char g = input[rgbIndex + 1];
unsigned char b = input[rgbIndex + 2];
output[pixelIndex] = r* scale[0] + g * scale[1] + b*scale[2];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11colorToGrayPhS_ii
.globl _Z11colorToGrayPhS_ii
.p2align 8
.type _Z11colorToGrayPhS_ii,@function
_Z11colorToGrayPhS_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s5, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
v_cmp_gt_i32_e64 s2, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
v_lshl_add_u32 v0, v2, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_clause 0x2
global_load_u8 v3, v[0:1], off offset:1
global_load_u8 v4, v[0:1], off
global_load_u8 v0, v[0:1], off offset:2
s_waitcnt vmcnt(2)
v_cvt_f32_ubyte0_e32 v1, v3
s_waitcnt vmcnt(1)
v_cvt_f32_ubyte0_e32 v3, v4
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v0, v0
v_mul_f32_e32 v1, 0x3f1645a2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v1, v3, 0x3e991687, v1
v_fmamk_f32 v0, v0, 0x3de978d5, v1
v_ashrrev_i32_e32 v1, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cvt_i32_f32_e32 v3, v0
v_add_co_u32 v0, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_store_b8 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11colorToGrayPhS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11colorToGrayPhS_ii, .Lfunc_end0-_Z11colorToGrayPhS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11colorToGrayPhS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11colorToGrayPhS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void colorToGray(unsigned char *input, unsigned char *output, int height, int width)
{
int col= blockDim.x * blockIdx.x + threadIdx.x;
int row = blockDim.y * blockIdx.y + threadIdx.y;
float scale[3] = {0.299, 0.587, 0.114};
if (row < height && col < width)
{
int pixelIndex = row * width + col;
int rgbIndex = pixelIndex * 3;
unsigned char r = input[rgbIndex]; // rgb rgb rgb rgb rgb
unsigned char g = input[rgbIndex + 1];
unsigned char b = input[rgbIndex + 2];
output[pixelIndex] = r* scale[0] + g * scale[1] + b*scale[2];
}
} | .text
.file "colorToGray.hip"
.globl _Z26__device_stub__colorToGrayPhS_ii # -- Begin function _Z26__device_stub__colorToGrayPhS_ii
.p2align 4, 0x90
.type _Z26__device_stub__colorToGrayPhS_ii,@function
_Z26__device_stub__colorToGrayPhS_ii: # @_Z26__device_stub__colorToGrayPhS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11colorToGrayPhS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__colorToGrayPhS_ii, .Lfunc_end0-_Z26__device_stub__colorToGrayPhS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11colorToGrayPhS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11colorToGrayPhS_ii,@object # @_Z11colorToGrayPhS_ii
.section .rodata,"a",@progbits
.globl _Z11colorToGrayPhS_ii
.p2align 3, 0x0
_Z11colorToGrayPhS_ii:
.quad _Z26__device_stub__colorToGrayPhS_ii
.size _Z11colorToGrayPhS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11colorToGrayPhS_ii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__colorToGrayPhS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11colorToGrayPhS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11colorToGrayPhS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x170], P0 ; /* 0x00005c0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R0, R3, c[0x0][0x174], R0 ; /* 0x00005d0003007a24 */
/* 0x000fe200078e0200 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00c0*/ IMAD R3, R0, 0x3, RZ ; /* 0x0000000300037824 */
/* 0x000fca00078e02ff */
/*00d0*/ IADD3 R2, P0, R3, c[0x0][0x160], RZ ; /* 0x0000580003027a10 */
/* 0x000fc80007f1e0ff */
/*00e0*/ LEA.HI.X.SX32 R3, R3, c[0x0][0x164], 0x1, P0 ; /* 0x0000590003037a11 */
/* 0x000fca00000f0eff */
/*00f0*/ LDG.E.U8 R7, [R2.64+0x1] ; /* 0x0000010402077981 */
/* 0x000ea8000c1e1100 */
/*0100*/ LDG.E.U8 R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ee8000c1e1100 */
/*0110*/ LDG.E.U8 R8, [R2.64+0x2] ; /* 0x0000020402087981 */
/* 0x000f22000c1e1100 */
/*0120*/ IADD3 R4, P0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000047a10 */
/* 0x000fe20007f1e0ff */
/*0130*/ I2F.U16 R7, R7 ; /* 0x0000000700077306 */
/* 0x004e300000101000 */
/*0140*/ I2F.U16 R6, R6 ; /* 0x0000000600067306 */
/* 0x008e700000101000 */
/*0150*/ I2F.U16 R8, R8 ; /* 0x0000000800087306 */
/* 0x010ea20000101000 */
/*0160*/ FMUL R5, R7, 0.58700001239776611328 ; /* 0x3f1645a207057820 */
/* 0x001fc80000400000 */
/*0170*/ FFMA R5, R6, 0.29899999499320983887, R5 ; /* 0x3e99168706057823 */
/* 0x002fc80000000005 */
/*0180*/ FFMA R9, R8, 0.11400000005960464478, R5 ; /* 0x3de978d508097823 */
/* 0x004fe20000000005 */
/*0190*/ LEA.HI.X.SX32 R5, R0, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0000057a11 */
/* 0x000fca00000f0eff */
/*01a0*/ F2I.U32.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e24000020f000 */
/*01b0*/ STG.E.U8 [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x001fe2000c101104 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11colorToGrayPhS_ii
.globl _Z11colorToGrayPhS_ii
.p2align 8
.type _Z11colorToGrayPhS_ii,@function
_Z11colorToGrayPhS_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s5, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
v_cmp_gt_i32_e64 s2, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
v_lshl_add_u32 v0, v2, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_clause 0x2
global_load_u8 v3, v[0:1], off offset:1
global_load_u8 v4, v[0:1], off
global_load_u8 v0, v[0:1], off offset:2
s_waitcnt vmcnt(2)
v_cvt_f32_ubyte0_e32 v1, v3
s_waitcnt vmcnt(1)
v_cvt_f32_ubyte0_e32 v3, v4
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v0, v0
v_mul_f32_e32 v1, 0x3f1645a2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v1, v3, 0x3e991687, v1
v_fmamk_f32 v0, v0, 0x3de978d5, v1
v_ashrrev_i32_e32 v1, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cvt_i32_f32_e32 v3, v0
v_add_co_u32 v0, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_store_b8 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11colorToGrayPhS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11colorToGrayPhS_ii, .Lfunc_end0-_Z11colorToGrayPhS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11colorToGrayPhS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11colorToGrayPhS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00013430_00000000-6_colorToGray.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z11colorToGrayPhS_iiPhS_ii
.type _Z35__device_stub__Z11colorToGrayPhS_iiPhS_ii, @function
_Z35__device_stub__Z11colorToGrayPhS_iiPhS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11colorToGrayPhS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z11colorToGrayPhS_iiPhS_ii, .-_Z35__device_stub__Z11colorToGrayPhS_iiPhS_ii
.globl _Z11colorToGrayPhS_ii
.type _Z11colorToGrayPhS_ii, @function
_Z11colorToGrayPhS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11colorToGrayPhS_iiPhS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11colorToGrayPhS_ii, .-_Z11colorToGrayPhS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11colorToGrayPhS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11colorToGrayPhS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "colorToGray.hip"
.globl _Z26__device_stub__colorToGrayPhS_ii # -- Begin function _Z26__device_stub__colorToGrayPhS_ii
.p2align 4, 0x90
.type _Z26__device_stub__colorToGrayPhS_ii,@function
_Z26__device_stub__colorToGrayPhS_ii: # @_Z26__device_stub__colorToGrayPhS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11colorToGrayPhS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__colorToGrayPhS_ii, .Lfunc_end0-_Z26__device_stub__colorToGrayPhS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11colorToGrayPhS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11colorToGrayPhS_ii,@object # @_Z11colorToGrayPhS_ii
.section .rodata,"a",@progbits
.globl _Z11colorToGrayPhS_ii
.p2align 3, 0x0
_Z11colorToGrayPhS_ii:
.quad _Z26__device_stub__colorToGrayPhS_ii
.size _Z11colorToGrayPhS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11colorToGrayPhS_ii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__colorToGrayPhS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11colorToGrayPhS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define LOG_INPUT if(0)
#define LOG_OUTPUT if(1)
#define LOG if(0)
__global__ void hadamard(float *A, float *B, float *C, int M, int N)
{
// Complete the kernel code snippet
int i = threadIdx.x + blockDim.x * blockIdx.x;
if(i < M*N)
C[i] = A[i]*B[i];
}
/**
* Host main routine
*/
void print_matrix(float *A,int m,int n)
{
for(int i =0;i<m;i++)
{
for(int j=0;j<n;j++)
printf("%.2f ",A[i*n+j]);
printf("\n");
}
}
int main(void)
{
// Error code to check return values for CUDA calls
cudaError_t err = cudaSuccess;
// Print the vector length to be used, and compute its size
int t; //number of test cases
scanf("%d",&t);
while(t--)
{
int m,n;
scanf("%d %d",&m,&n);
size_t size = m*n * sizeof(float);
LOG printf("[Hadamard product of two matrices ]\n");
// Allocate the host input vector A
float *h_A = (float*)malloc(size);
// Allocate the host input vector B
float *h_B = (float*)malloc(size);
// Allocate the host output vector C
float *h_C = (float*)malloc(size);
// Verify that allocations succeeded
if (h_A == NULL || h_B == NULL || h_C == NULL)
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
// Initialize the host input vectors
for (int i = 0; i < n*m; ++i)
{
scanf("%f",&h_A[i]);
scanf("%f",&h_B[i]);
}
float *d_A = NULL, *d_B = NULL, *d_C = NULL;
// Allocate the device input vector A
cudaMalloc((void**)&d_A, size);
// Allocate the device input vector B
cudaMalloc((void**)&d_B, size);
// Allocate the device output vector C
cudaMalloc((void**)&d_C, size);
// Copy the host input vectors A and B in host memory to the device input vectors in
// device memory
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_C, h_C, size, cudaMemcpyHostToDevice);
// initialize blocksPerGrid and threads Per Block
int threadsPerBlock = 256;
int blocksPerGrid = ((m*n)+threadsPerBlock-1)/threadsPerBlock;
hadamard<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C, m, n);
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch vectorAdd kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Copy the device result vector in device memory to the host result vector
// in host memory.
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
// Verify that the result vector is correct
for (int i = 0; i < n*m; ++i)
{
if (fabs(h_A[i] * h_B[i] - h_C[i]) > 1e-5)
{
fprintf(stderr, "Result verification failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
LOG printf("Test PASSED\n");
// Free device global memory
// Free host memory
err = cudaDeviceReset();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to deinitialize the device! error=%s\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
print_matrix(h_C,m,n);
LOG printf("Done\n");
}
return 0;
} | code for sm_80
Function : _Z8hadamardPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0060*/ ISETP.GE.AND P0, PT, R6, UR4, PT ; /* 0x0000000406007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00c0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00f0*/ FMUL R9, R4, R3 ; /* 0x0000000304097220 */
/* 0x004fca0000400000 */
/*0100*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define LOG_INPUT if(0)
#define LOG_OUTPUT if(1)
#define LOG if(0)
__global__ void hadamard(float *A, float *B, float *C, int M, int N)
{
// Complete the kernel code snippet
int i = threadIdx.x + blockDim.x * blockIdx.x;
if(i < M*N)
C[i] = A[i]*B[i];
}
/**
* Host main routine
*/
void print_matrix(float *A,int m,int n)
{
for(int i =0;i<m;i++)
{
for(int j=0;j<n;j++)
printf("%.2f ",A[i*n+j]);
printf("\n");
}
}
int main(void)
{
// Error code to check return values for CUDA calls
cudaError_t err = cudaSuccess;
// Print the vector length to be used, and compute its size
int t; //number of test cases
scanf("%d",&t);
while(t--)
{
int m,n;
scanf("%d %d",&m,&n);
size_t size = m*n * sizeof(float);
LOG printf("[Hadamard product of two matrices ]\n");
// Allocate the host input vector A
float *h_A = (float*)malloc(size);
// Allocate the host input vector B
float *h_B = (float*)malloc(size);
// Allocate the host output vector C
float *h_C = (float*)malloc(size);
// Verify that allocations succeeded
if (h_A == NULL || h_B == NULL || h_C == NULL)
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
// Initialize the host input vectors
for (int i = 0; i < n*m; ++i)
{
scanf("%f",&h_A[i]);
scanf("%f",&h_B[i]);
}
float *d_A = NULL, *d_B = NULL, *d_C = NULL;
// Allocate the device input vector A
cudaMalloc((void**)&d_A, size);
// Allocate the device input vector B
cudaMalloc((void**)&d_B, size);
// Allocate the device output vector C
cudaMalloc((void**)&d_C, size);
// Copy the host input vectors A and B in host memory to the device input vectors in
// device memory
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_C, h_C, size, cudaMemcpyHostToDevice);
// initialize blocksPerGrid and threads Per Block
int threadsPerBlock = 256;
int blocksPerGrid = ((m*n)+threadsPerBlock-1)/threadsPerBlock;
hadamard<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C, m, n);
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch vectorAdd kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Copy the device result vector in device memory to the host result vector
// in host memory.
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
// Verify that the result vector is correct
for (int i = 0; i < n*m; ++i)
{
if (fabs(h_A[i] * h_B[i] - h_C[i]) > 1e-5)
{
fprintf(stderr, "Result verification failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
LOG printf("Test PASSED\n");
// Free device global memory
// Free host memory
err = cudaDeviceReset();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to deinitialize the device! error=%s\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
print_matrix(h_C,m,n);
LOG printf("Done\n");
}
return 0;
} | .file "tmpxft_001525a2_00000000-6_hadamard_product.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%.2f "
.LC1:
.string "\n"
.text
.globl _Z12print_matrixPfii
.type _Z12print_matrixPfii, @function
_Z12print_matrixPfii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L3
movl %edx, %r15d
movl $0, %r14d
movl $0, %r13d
movslq %edx, %rax
movq %rax, 24(%rsp)
leaq .LC0(%rip), %r12
jmp .L5
.L7:
movslq %r14d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rdx
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L6:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
.L8:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, 12(%rsp)
je .L3
.L5:
testl %r15d, %r15d
jg .L7
jmp .L8
.L3:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z12print_matrixPfii, .-_Z12print_matrixPfii
.globl _Z33__device_stub__Z8hadamardPfS_S_iiPfS_S_ii
.type _Z33__device_stub__Z8hadamardPfS_S_iiPfS_S_ii, @function
_Z33__device_stub__Z8hadamardPfS_S_iiPfS_S_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8hadamardPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z33__device_stub__Z8hadamardPfS_S_iiPfS_S_ii, .-_Z33__device_stub__Z8hadamardPfS_S_iiPfS_S_ii
.globl _Z8hadamardPfS_S_ii
.type _Z8hadamardPfS_S_ii, @function
_Z8hadamardPfS_S_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z8hadamardPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z8hadamardPfS_S_ii, .-_Z8hadamardPfS_S_ii
.section .rodata.str1.1
.LC2:
.string "%d"
.LC3:
.string "%d %d"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Failed to allocate host vectors!\n"
.section .rodata.str1.1
.LC5:
.string "%f"
.section .rodata.str1.8
.align 8
.LC6:
.string "Failed to launch vectorAdd kernel (error code %s)!\n"
.align 8
.LC9:
.string "Result verification failed at element %d!\n"
.align 8
.LC10:
.string "Failed to deinitialize the device! error=%s\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rsi
leaq .LC2(%rip), %rdi
call __isoc23_scanf@PLT
movl 28(%rsp), %eax
leal -1(%rax), %edx
movl %edx, 28(%rsp)
testl %eax, %eax
jne .L32
.L20:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L25:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L42
movl $2, %ecx
movq (%rsp), %rdx
movq 56(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl 36(%rsp), %edx
imull 32(%rsp), %edx
testl %edx, %edx
jle .L27
movslq %edx, %rdx
movl $0, %eax
.L30:
movss (%r14,%rax,4), %xmm0
mulss (%r15,%rax,4), %xmm0
subss 0(%r13,%rax,4), %xmm0
andps .LC7(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
comisd .LC8(%rip), %xmm0
ja .L43
addq $1, %rax
cmpq %rdx, %rax
jne .L30
.L27:
call cudaDeviceReset@PLT
testl %eax, %eax
jne .L44
movl 36(%rsp), %edx
movl 32(%rsp), %esi
movq %r13, %rdi
call _Z12print_matrixPfii
movl 28(%rsp), %eax
leal -1(%rax), %edx
movl %edx, 28(%rsp)
testl %eax, %eax
je .L20
.L32:
leaq 36(%rsp), %rdx
leaq 32(%rsp), %rsi
leaq .LC3(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 32(%rsp), %eax
imull 36(%rsp), %eax
movl %eax, 12(%rsp)
cltq
leaq 0(,%rax,4), %rbx
movq %rbx, (%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r15
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
testq %r14, %r14
sete %al
testq %r15, %r15
sete %dl
orb %dl, %al
jne .L21
testq %r13, %r13
je .L21
movq %r14, %r12
movq %r15, %rbp
movl $0, %ebx
cmpl $0, 12(%rsp)
jle .L23
.L24:
movq %r12, %rsi
leaq .LC5(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movq %rbp, %rsi
leaq .LC5(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
addq $4, %r12
addq $4, %rbp
movl 36(%rsp), %eax
imull 32(%rsp), %eax
cmpl %ebx, %eax
jg .L24
.L23:
movq $0, 40(%rsp)
movq $0, 48(%rsp)
movq $0, 56(%rsp)
leaq 40(%rsp), %rdi
movq (%rsp), %rbx
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl 32(%rsp), %eax
imull 36(%rsp), %eax
leal 510(%rax), %edx
addl $255, %eax
cmovs %edx, %eax
sarl $8, %eax
movl $256, 76(%rsp)
movl $1, 80(%rsp)
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L25
movl 36(%rsp), %r8d
movl 32(%rsp), %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z33__device_stub__Z8hadamardPfS_S_iiPfS_S_ii
jmp .L25
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L43:
movl %eax, %ecx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L44:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z8hadamardPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z8hadamardPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC7:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC8:
.long -1998362383
.long 1055193269
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define LOG_INPUT if(0)
#define LOG_OUTPUT if(1)
#define LOG if(0)
__global__ void hadamard(float *A, float *B, float *C, int M, int N)
{
// Complete the kernel code snippet
int i = threadIdx.x + blockDim.x * blockIdx.x;
if(i < M*N)
C[i] = A[i]*B[i];
}
/**
* Host main routine
*/
void print_matrix(float *A,int m,int n)
{
for(int i =0;i<m;i++)
{
for(int j=0;j<n;j++)
printf("%.2f ",A[i*n+j]);
printf("\n");
}
}
int main(void)
{
// Error code to check return values for CUDA calls
cudaError_t err = cudaSuccess;
// Print the vector length to be used, and compute its size
int t; //number of test cases
scanf("%d",&t);
while(t--)
{
int m,n;
scanf("%d %d",&m,&n);
size_t size = m*n * sizeof(float);
LOG printf("[Hadamard product of two matrices ]\n");
// Allocate the host input vector A
float *h_A = (float*)malloc(size);
// Allocate the host input vector B
float *h_B = (float*)malloc(size);
// Allocate the host output vector C
float *h_C = (float*)malloc(size);
// Verify that allocations succeeded
if (h_A == NULL || h_B == NULL || h_C == NULL)
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
// Initialize the host input vectors
for (int i = 0; i < n*m; ++i)
{
scanf("%f",&h_A[i]);
scanf("%f",&h_B[i]);
}
float *d_A = NULL, *d_B = NULL, *d_C = NULL;
// Allocate the device input vector A
cudaMalloc((void**)&d_A, size);
// Allocate the device input vector B
cudaMalloc((void**)&d_B, size);
// Allocate the device output vector C
cudaMalloc((void**)&d_C, size);
// Copy the host input vectors A and B in host memory to the device input vectors in
// device memory
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_C, h_C, size, cudaMemcpyHostToDevice);
// initialize blocksPerGrid and threads Per Block
int threadsPerBlock = 256;
int blocksPerGrid = ((m*n)+threadsPerBlock-1)/threadsPerBlock;
hadamard<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C, m, n);
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch vectorAdd kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Copy the device result vector in device memory to the host result vector
// in host memory.
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
// Verify that the result vector is correct
for (int i = 0; i < n*m; ++i)
{
if (fabs(h_A[i] * h_B[i] - h_C[i]) > 1e-5)
{
fprintf(stderr, "Result verification failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
LOG printf("Test PASSED\n");
// Free device global memory
// Free host memory
err = cudaDeviceReset();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to deinitialize the device! error=%s\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
print_matrix(h_C,m,n);
LOG printf("Done\n");
}
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#define LOG_INPUT if(0)
#define LOG_OUTPUT if(1)
#define LOG if(0)
__global__ void hadamard(float *A, float *B, float *C, int M, int N)
{
// Complete the kernel code snippet
int i = threadIdx.x + blockDim.x * blockIdx.x;
if(i < M*N)
C[i] = A[i]*B[i];
}
/**
* Host main routine
*/
void print_matrix(float *A,int m,int n)
{
for(int i =0;i<m;i++)
{
for(int j=0;j<n;j++)
printf("%.2f ",A[i*n+j]);
printf("\n");
}
}
int main(void)
{
// Error code to check return values for CUDA calls
hipError_t err = hipSuccess;
// Print the vector length to be used, and compute its size
int t; //number of test cases
scanf("%d",&t);
while(t--)
{
int m,n;
scanf("%d %d",&m,&n);
size_t size = m*n * sizeof(float);
LOG printf("[Hadamard product of two matrices ]\n");
// Allocate the host input vector A
float *h_A = (float*)malloc(size);
// Allocate the host input vector B
float *h_B = (float*)malloc(size);
// Allocate the host output vector C
float *h_C = (float*)malloc(size);
// Verify that allocations succeeded
if (h_A == NULL || h_B == NULL || h_C == NULL)
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
// Initialize the host input vectors
for (int i = 0; i < n*m; ++i)
{
scanf("%f",&h_A[i]);
scanf("%f",&h_B[i]);
}
float *d_A = NULL, *d_B = NULL, *d_C = NULL;
// Allocate the device input vector A
hipMalloc((void**)&d_A, size);
// Allocate the device input vector B
hipMalloc((void**)&d_B, size);
// Allocate the device output vector C
hipMalloc((void**)&d_C, size);
// Copy the host input vectors A and B in host memory to the device input vectors in
// device memory
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
hipMemcpy(d_C, h_C, size, hipMemcpyHostToDevice);
// initialize blocksPerGrid and threads Per Block
int threadsPerBlock = 256;
int blocksPerGrid = ((m*n)+threadsPerBlock-1)/threadsPerBlock;
hadamard<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C, m, n);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch vectorAdd kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Copy the device result vector in device memory to the host result vector
// in host memory.
hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
// Verify that the result vector is correct
for (int i = 0; i < n*m; ++i)
{
if (fabs(h_A[i] * h_B[i] - h_C[i]) > 1e-5)
{
fprintf(stderr, "Result verification failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
LOG printf("Test PASSED\n");
// Free device global memory
// Free host memory
err = hipDeviceReset();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to deinitialize the device! error=%s\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
print_matrix(h_C,m,n);
LOG printf("Done\n");
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#define LOG_INPUT if(0)
#define LOG_OUTPUT if(1)
#define LOG if(0)
__global__ void hadamard(float *A, float *B, float *C, int M, int N)
{
// Complete the kernel code snippet
int i = threadIdx.x + blockDim.x * blockIdx.x;
if(i < M*N)
C[i] = A[i]*B[i];
}
/**
* Host main routine
*/
void print_matrix(float *A,int m,int n)
{
for(int i =0;i<m;i++)
{
for(int j=0;j<n;j++)
printf("%.2f ",A[i*n+j]);
printf("\n");
}
}
int main(void)
{
// Error code to check return values for CUDA calls
hipError_t err = hipSuccess;
// Print the vector length to be used, and compute its size
int t; //number of test cases
scanf("%d",&t);
while(t--)
{
int m,n;
scanf("%d %d",&m,&n);
size_t size = m*n * sizeof(float);
LOG printf("[Hadamard product of two matrices ]\n");
// Allocate the host input vector A
float *h_A = (float*)malloc(size);
// Allocate the host input vector B
float *h_B = (float*)malloc(size);
// Allocate the host output vector C
float *h_C = (float*)malloc(size);
// Verify that allocations succeeded
if (h_A == NULL || h_B == NULL || h_C == NULL)
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
// Initialize the host input vectors
for (int i = 0; i < n*m; ++i)
{
scanf("%f",&h_A[i]);
scanf("%f",&h_B[i]);
}
float *d_A = NULL, *d_B = NULL, *d_C = NULL;
// Allocate the device input vector A
hipMalloc((void**)&d_A, size);
// Allocate the device input vector B
hipMalloc((void**)&d_B, size);
// Allocate the device output vector C
hipMalloc((void**)&d_C, size);
// Copy the host input vectors A and B in host memory to the device input vectors in
// device memory
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
hipMemcpy(d_C, h_C, size, hipMemcpyHostToDevice);
// initialize blocksPerGrid and threads Per Block
int threadsPerBlock = 256;
int blocksPerGrid = ((m*n)+threadsPerBlock-1)/threadsPerBlock;
hadamard<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C, m, n);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch vectorAdd kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Copy the device result vector in device memory to the host result vector
// in host memory.
hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
// Verify that the result vector is correct
for (int i = 0; i < n*m; ++i)
{
if (fabs(h_A[i] * h_B[i] - h_C[i]) > 1e-5)
{
fprintf(stderr, "Result verification failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
LOG printf("Test PASSED\n");
// Free device global memory
// Free host memory
err = hipDeviceReset();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to deinitialize the device! error=%s\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
print_matrix(h_C,m,n);
LOG printf("Done\n");
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8hadamardPfS_S_ii
.globl _Z8hadamardPfS_S_ii
.p2align 8
.type _Z8hadamardPfS_S_ii,@function
_Z8hadamardPfS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_mul_i32 s2, s3, s2
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8hadamardPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8hadamardPfS_S_ii, .Lfunc_end0-_Z8hadamardPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8hadamardPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8hadamardPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#define LOG_INPUT if(0)
#define LOG_OUTPUT if(1)
#define LOG if(0)
__global__ void hadamard(float *A, float *B, float *C, int M, int N)
{
// Complete the kernel code snippet
int i = threadIdx.x + blockDim.x * blockIdx.x;
if(i < M*N)
C[i] = A[i]*B[i];
}
/**
* Host main routine
*/
void print_matrix(float *A,int m,int n)
{
for(int i =0;i<m;i++)
{
for(int j=0;j<n;j++)
printf("%.2f ",A[i*n+j]);
printf("\n");
}
}
int main(void)
{
// Error code to check return values for CUDA calls
hipError_t err = hipSuccess;
// Print the vector length to be used, and compute its size
int t; //number of test cases
scanf("%d",&t);
while(t--)
{
int m,n;
scanf("%d %d",&m,&n);
size_t size = m*n * sizeof(float);
LOG printf("[Hadamard product of two matrices ]\n");
// Allocate the host input vector A
float *h_A = (float*)malloc(size);
// Allocate the host input vector B
float *h_B = (float*)malloc(size);
// Allocate the host output vector C
float *h_C = (float*)malloc(size);
// Verify that allocations succeeded
if (h_A == NULL || h_B == NULL || h_C == NULL)
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
// Initialize the host input vectors
for (int i = 0; i < n*m; ++i)
{
scanf("%f",&h_A[i]);
scanf("%f",&h_B[i]);
}
float *d_A = NULL, *d_B = NULL, *d_C = NULL;
// Allocate the device input vector A
hipMalloc((void**)&d_A, size);
// Allocate the device input vector B
hipMalloc((void**)&d_B, size);
// Allocate the device output vector C
hipMalloc((void**)&d_C, size);
// Copy the host input vectors A and B in host memory to the device input vectors in
// device memory
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
hipMemcpy(d_C, h_C, size, hipMemcpyHostToDevice);
// initialize blocksPerGrid and threads Per Block
int threadsPerBlock = 256;
int blocksPerGrid = ((m*n)+threadsPerBlock-1)/threadsPerBlock;
hadamard<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C, m, n);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch vectorAdd kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Copy the device result vector in device memory to the host result vector
// in host memory.
hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
// Verify that the result vector is correct
for (int i = 0; i < n*m; ++i)
{
if (fabs(h_A[i] * h_B[i] - h_C[i]) > 1e-5)
{
fprintf(stderr, "Result verification failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
LOG printf("Test PASSED\n");
// Free device global memory
// Free host memory
err = hipDeviceReset();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to deinitialize the device! error=%s\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
print_matrix(h_C,m,n);
LOG printf("Done\n");
}
return 0;
} | .text
.file "hadamard_product.hip"
.globl _Z23__device_stub__hadamardPfS_S_ii # -- Begin function _Z23__device_stub__hadamardPfS_S_ii
.p2align 4, 0x90
.type _Z23__device_stub__hadamardPfS_S_ii,@function
_Z23__device_stub__hadamardPfS_S_ii: # @_Z23__device_stub__hadamardPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8hadamardPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__hadamardPfS_S_ii, .Lfunc_end0-_Z23__device_stub__hadamardPfS_S_ii
.cfi_endproc
# -- End function
.globl _Z12print_matrixPfii # -- Begin function _Z12print_matrixPfii
.p2align 4, 0x90
.type _Z12print_matrixPfii,@function
_Z12print_matrixPfii: # @_Z12print_matrixPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 8(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB1_6
# %bb.1: # %.preheader.lr.ph
movl %edx, %ebx
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %edx, %r12d
xorl %r13d, %r13d
xorl %ebp, %ebp
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %rbp
addl %ebx, %r13d
cmpq 16(%rsp), %rbp # 8-byte Folded Reload
je .LBB1_6
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
testl %ebx, %ebx
jle .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %r13d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB1_4
jmp .LBB1_5
.LBB1_6: # %._crit_edge13
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z12print_matrixPfii, .Lfunc_end1-_Z12print_matrixPfii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_1:
.quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 20(%rsp), %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq __isoc23_scanf
subl $1, 20(%rsp)
jae .LBB2_1
.LBB2_26: # %._crit_edge69
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_1: # %.lr.ph68
.cfi_def_cfa_offset 240
movabsq $4294967296, %rax # imm = 0x100000000
addq $256, %rax # imm = 0x100
movq %rax, 64(%rsp) # 8-byte Spill
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_25: # %_Z12print_matrixPfii.exit
# in Loop: Header=BB2_2 Depth=1
subl $1, 20(%rsp)
jb .LBB2_26
.LBB2_2: # =>This Loop Header: Depth=1
# Child Loop BB2_7 Depth 2
# Child Loop BB2_15 Depth 2
# Child Loop BB2_21 Depth 2
# Child Loop BB2_23 Depth 3
movl $.L.str.3, %edi
leaq 16(%rsp), %rsi
leaq 12(%rsp), %rdx
xorl %eax, %eax
callq __isoc23_scanf
movslq 16(%rsp), %rax
movslq 12(%rsp), %r12
imulq %rax, %r12
shlq $2, %r12
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, %rbp
movq %r12, %rdi
callq malloc
movq %r14, 24(%rsp) # 8-byte Spill
testq %r14, %r14
je .LBB2_28
# %bb.3: # in Loop: Header=BB2_2 Depth=1
testq %rbp, %rbp
je .LBB2_28
# %bb.4: # in Loop: Header=BB2_2 Depth=1
movq %rax, %rbx
testq %rax, %rax
je .LBB2_28
# %bb.5: # %.preheader
# in Loop: Header=BB2_2 Depth=1
movl 16(%rsp), %eax
imull 12(%rsp), %eax
testl %eax, %eax
jle .LBB2_8
# %bb.6: # %.lr.ph.preheader
# in Loop: Header=BB2_2 Depth=1
movq 24(%rsp), %r14 # 8-byte Reload
movq %rbp, %r15
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_7: # %.lr.ph
# Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str.5, %edi
movq %r14, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.5, %edi
movq %r15, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r13
movslq 12(%rsp), %rax
movslq 16(%rsp), %rcx
imulq %rax, %rcx
addq $4, %r15
addq $4, %r14
cmpq %rcx, %r13
jl .LBB2_7
.LBB2_8: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movq $0, 48(%rsp)
movq $0, 40(%rsp)
movq $0, 32(%rsp)
leaq 48(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 48(%rsp), %rdi
movq 24(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq %rbp, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl 12(%rsp), %edi
imull 16(%rsp), %edi
leal 255(%rdi), %eax
addl $510, %edi # imm = 0x1FE
testl %eax, %eax
cmovnsl %eax, %edi
sarl $8, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl $1, %esi
movq 64(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9: # in Loop: Header=BB2_2 Depth=1
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movl 16(%rsp), %esi
movl 12(%rsp), %edi
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl %esi, 60(%rsp)
movl %edi, 56(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 60(%rsp), %rax
movq %rax, 168(%rsp)
leaq 56(%rsp), %rax
movq %rax, 176(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
movl $_Z8hadamardPfS_S_ii, %edi
leaq 144(%rsp), %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_10: # in Loop: Header=BB2_2 Depth=1
callq hipGetLastError
testl %eax, %eax
jne .LBB2_11
# %bb.13: # in Loop: Header=BB2_2 Depth=1
movq 32(%rsp), %rsi
movq %rbx, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movl 16(%rsp), %eax
imull 12(%rsp), %eax
testl %eax, %eax
movaps .LCPI2_0(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movsd .LCPI2_1(%rip), %xmm2 # xmm2 = mem[0],zero
jle .LBB2_17
# %bb.14: # %.lr.ph64.preheader
# in Loop: Header=BB2_2 Depth=1
movl %eax, %eax
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_15: # %.lr.ph64
# Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%rdx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%rbp,%rdx,4), %xmm0
subss (%rbx,%rdx,4), %xmm0
andps %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
ucomisd %xmm2, %xmm0
ja .LBB2_27
# %bb.16: # in Loop: Header=BB2_15 Depth=2
incq %rdx
cmpq %rdx, %rax
jne .LBB2_15
.LBB2_17: # %._crit_edge65
# in Loop: Header=BB2_2 Depth=1
movq %rbx, 24(%rsp) # 8-byte Spill
callq hipDeviceReset
testl %eax, %eax
jne .LBB2_18
# %bb.19: # in Loop: Header=BB2_2 Depth=1
movl 16(%rsp), %r14d
testl %r14d, %r14d
jle .LBB2_25
# %bb.20: # %.preheader.lr.ph.i
# in Loop: Header=BB2_2 Depth=1
movl 12(%rsp), %r15d
xorl %r12d, %r12d
xorl %r13d, %r13d
jmp .LBB2_21
.p2align 4, 0x90
.LBB2_24: # %._crit_edge.i
# in Loop: Header=BB2_21 Depth=2
movl $10, %edi
callq putchar@PLT
incq %r13
addl %r15d, %r12d
cmpq %r14, %r13
je .LBB2_25
.LBB2_21: # %.preheader.i
# Parent Loop BB2_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_23 Depth 3
testl %r15d, %r15d
jle .LBB2_24
# %bb.22: # %.lr.ph.i
# in Loop: Header=BB2_21 Depth=2
movl %r12d, %eax
movq 24(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_23: # Parent Loop BB2_2 Depth=1
# Parent Loop BB2_21 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rbp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %rbx
cmpq %rbx, %r15
jne .LBB2_23
jmp .LBB2_24
.LBB2_27:
movq stderr(%rip), %rdi
movl $.L.str.7, %esi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB2_28:
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
movl $33, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.LBB2_11:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
jmp .LBB2_12
.LBB2_18:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
.LBB2_12:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8hadamardPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8hadamardPfS_S_ii,@object # @_Z8hadamardPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z8hadamardPfS_S_ii
.p2align 3, 0x0
_Z8hadamardPfS_S_ii:
.quad _Z23__device_stub__hadamardPfS_S_ii
.size _Z8hadamardPfS_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%.2f "
.size .L.str, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d %d"
.size .L.str.3, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to allocate host vectors!\n"
.size .L.str.4, 34
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%f"
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Failed to launch vectorAdd kernel (error code %s)!\n"
.size .L.str.6, 52
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Result verification failed at element %d!\n"
.size .L.str.7, 43
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Failed to deinitialize the device! error=%s\n"
.size .L.str.8, 45
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8hadamardPfS_S_ii"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__hadamardPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8hadamardPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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