system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* Autor: Grupo GRID
* Fecha: Julio 2016
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#define N 4
__global__
void MultiplocarMatrices(int *d_a, int *d_b, int *d_c, int n )
{
int id, i, j;
id = blockIdx.x * blockDim.x + threadIdx.x;
if ( id < n )
{
for( i = 0 ; i < n ; i++ )
{
d_c[ id * n + i ] = 0;
for ( j = 0 ; j < n ; j++)
{
d_c[ id * n + i ] += ( d_a[ id * n + j ] * d_b[ j * n + id ] );
}
}
}
}
int main( int argc, char** argv)
{
int *h_a, *h_b, *h_c;
int *d_a, *d_b, *d_c;
char validacion[10];
int n = N; // Valor por defecto
if ( argc > 1 )
{
n = atoi (argv[1]);
if ( n > 1024 )
{
n = 1024;
}
}
size_t memSize = n * n * sizeof( int );
h_a = (int *) malloc( memSize );
h_b = (int *) malloc( memSize );
h_c = (int *) malloc( memSize );
if ( h_a == NULL || h_b == NULL || h_c == NULL )
{
perror("Memoria insuficiente\n");
exit(-1);
}
cudaMalloc( (void**) &d_a, memSize );
cudaMalloc( (void**) &d_b, memSize );
cudaMalloc( (void**) &d_c, memSize );
if ( d_a == NULL || d_b == NULL || d_c == NULL )
{
perror("Memoria insuficiente en la GPU\n");
exit(-1);
}
for( int i = 0 ; i < n ; i++ )
{
for( int j = 0 ; j < n ; j++ )
{
h_a[ n * i + j] = 1;
h_b[ n * i + j] = 1;
h_c[ n * i + j] = 0;
}
}
cudaMemcpy( d_a, h_a , memSize, cudaMemcpyHostToDevice );
cudaMemcpy( d_b, h_b , memSize, cudaMemcpyHostToDevice );
MultiplocarMatrices<<< 1 , n >>> (d_a, d_b, d_c, n );
cudaMemcpy( h_c, d_c, memSize, cudaMemcpyDeviceToHost );
// Validación de la multiplicación
// El producto de dos matrices de NxN de unos produce una matriz donde todos los elementos son N
strcpy(validacion, "Ok");
for( int i = 0 ; i < n ; i++ )
{
for( int j = 0 ; j < n ; j++ )
{
if ( h_c[ n * i + j ] != n )
{
strcpy(validacion, "Error");
}
}
}
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
free(h_a);
free(h_b);
free(h_c);
printf ( "\t %10d \t\t %s \t ", n, validacion );
return 0;
} | /**
* Autor: Grupo GRID
* Fecha: Julio 2016
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#define N 4
__global__
void MultiplocarMatrices(int *d_a, int *d_b, int *d_c, int n )
{
int id, i, j;
id = blockIdx.x * blockDim.x + threadIdx.x;
if ( id < n )
{
for( i = 0 ; i < n ; i++ )
{
d_c[ id * n + i ] = 0;
for ( j = 0 ; j < n ; j++)
{
d_c[ id * n + i ] += ( d_a[ id * n + j ] * d_b[ j * n + id ] );
}
}
}
}
int main( int argc, char** argv)
{
int *h_a, *h_b, *h_c;
int *d_a, *d_b, *d_c;
char validacion[10];
int n = N; // Valor por defecto
if ( argc > 1 )
{
n = atoi (argv[1]);
if ( n > 1024 )
{
n = 1024;
}
}
size_t memSize = n * n * sizeof( int );
h_a = (int *) malloc( memSize );
h_b = (int *) malloc( memSize );
h_c = (int *) malloc( memSize );
if ( h_a == NULL || h_b == NULL || h_c == NULL )
{
perror("Memoria insuficiente\n");
exit(-1);
}
hipMalloc( (void**) &d_a, memSize );
hipMalloc( (void**) &d_b, memSize );
hipMalloc( (void**) &d_c, memSize );
if ( d_a == NULL || d_b == NULL || d_c == NULL )
{
perror("Memoria insuficiente en la GPU\n");
exit(-1);
}
for( int i = 0 ; i < n ; i++ )
{
for( int j = 0 ; j < n ; j++ )
{
h_a[ n * i + j] = 1;
h_b[ n * i + j] = 1;
h_c[ n * i + j] = 0;
}
}
hipMemcpy( d_a, h_a , memSize, hipMemcpyHostToDevice );
hipMemcpy( d_b, h_b , memSize, hipMemcpyHostToDevice );
MultiplocarMatrices<<< 1 , n >>> (d_a, d_b, d_c, n );
hipMemcpy( h_c, d_c, memSize, hipMemcpyDeviceToHost );
// Validación de la multiplicación
// El producto de dos matrices de NxN de unos produce una matriz donde todos los elementos son N
strcpy(validacion, "Ok");
for( int i = 0 ; i < n ; i++ )
{
for( int j = 0 ; j < n ; j++ )
{
if ( h_c[ n * i + j ] != n )
{
strcpy(validacion, "Error");
}
}
}
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
free(h_a);
free(h_b);
free(h_c);
printf ( "\t %10d \t\t %s \t ", n, validacion );
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
* Autor: Grupo GRID
* Fecha: Julio 2016
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#define N 4
__global__
void MultiplocarMatrices(int *d_a, int *d_b, int *d_c, int n )
{
int id, i, j;
id = blockIdx.x * blockDim.x + threadIdx.x;
if ( id < n )
{
for( i = 0 ; i < n ; i++ )
{
d_c[ id * n + i ] = 0;
for ( j = 0 ; j < n ; j++)
{
d_c[ id * n + i ] += ( d_a[ id * n + j ] * d_b[ j * n + id ] );
}
}
}
}
int main( int argc, char** argv)
{
int *h_a, *h_b, *h_c;
int *d_a, *d_b, *d_c;
char validacion[10];
int n = N; // Valor por defecto
if ( argc > 1 )
{
n = atoi (argv[1]);
if ( n > 1024 )
{
n = 1024;
}
}
size_t memSize = n * n * sizeof( int );
h_a = (int *) malloc( memSize );
h_b = (int *) malloc( memSize );
h_c = (int *) malloc( memSize );
if ( h_a == NULL || h_b == NULL || h_c == NULL )
{
perror("Memoria insuficiente\n");
exit(-1);
}
hipMalloc( (void**) &d_a, memSize );
hipMalloc( (void**) &d_b, memSize );
hipMalloc( (void**) &d_c, memSize );
if ( d_a == NULL || d_b == NULL || d_c == NULL )
{
perror("Memoria insuficiente en la GPU\n");
exit(-1);
}
for( int i = 0 ; i < n ; i++ )
{
for( int j = 0 ; j < n ; j++ )
{
h_a[ n * i + j] = 1;
h_b[ n * i + j] = 1;
h_c[ n * i + j] = 0;
}
}
hipMemcpy( d_a, h_a , memSize, hipMemcpyHostToDevice );
hipMemcpy( d_b, h_b , memSize, hipMemcpyHostToDevice );
MultiplocarMatrices<<< 1 , n >>> (d_a, d_b, d_c, n );
hipMemcpy( h_c, d_c, memSize, hipMemcpyDeviceToHost );
// Validación de la multiplicación
// El producto de dos matrices de NxN de unos produce una matriz donde todos los elementos son N
strcpy(validacion, "Ok");
for( int i = 0 ; i < n ; i++ )
{
for( int j = 0 ; j < n ; j++ )
{
if ( h_c[ n * i + j ] != n )
{
strcpy(validacion, "Error");
}
}
}
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
free(h_a);
free(h_b);
free(h_c);
printf ( "\t %10d \t\t %s \t ", n, validacion );
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19MultiplocarMatricesPiS_S_i
.globl _Z19MultiplocarMatricesPiS_S_i
.p2align 8
.type _Z19MultiplocarMatricesPiS_S_i,@function
_Z19MultiplocarMatricesPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, 0
v_max_i32_e32 v0, 0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s2
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v11, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_dual_mov_b32 v0, 0 :: v_dual_add_nc_u32 v5, s3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_mov_b32 v8, v4 :: v_dual_mov_b32 v7, v3
v_mov_b32_e32 v9, v1
v_ashrrev_i32_e32 v6, 31, v5
s_mov_b32 s4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, vcc_lo, s0, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
global_store_b32 v[5:6], v11, off
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v10, 31, v9
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s2, s4
v_lshlrev_b64 v[12:13], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v12, vcc_lo, s6, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
global_load_b32 v10, v[7:8], off
global_load_b32 v14, v[12:13], off
v_add_co_u32 v7, vcc_lo, v7, 4
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[12:13], null, v14, v10, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v0, v12 :: v_dual_add_nc_u32 v9, s2, v9
global_store_b32 v[5:6], v12, off
s_cbranch_scc1 .LBB0_3
s_add_i32 s3, s3, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s3, s2
s_cbranch_scc1 .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19MultiplocarMatricesPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19MultiplocarMatricesPiS_S_i, .Lfunc_end0-_Z19MultiplocarMatricesPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19MultiplocarMatricesPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19MultiplocarMatricesPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
* Autor: Grupo GRID
* Fecha: Julio 2016
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#define N 4
__global__
void MultiplocarMatrices(int *d_a, int *d_b, int *d_c, int n )
{
int id, i, j;
id = blockIdx.x * blockDim.x + threadIdx.x;
if ( id < n )
{
for( i = 0 ; i < n ; i++ )
{
d_c[ id * n + i ] = 0;
for ( j = 0 ; j < n ; j++)
{
d_c[ id * n + i ] += ( d_a[ id * n + j ] * d_b[ j * n + id ] );
}
}
}
}
int main( int argc, char** argv)
{
int *h_a, *h_b, *h_c;
int *d_a, *d_b, *d_c;
char validacion[10];
int n = N; // Valor por defecto
if ( argc > 1 )
{
n = atoi (argv[1]);
if ( n > 1024 )
{
n = 1024;
}
}
size_t memSize = n * n * sizeof( int );
h_a = (int *) malloc( memSize );
h_b = (int *) malloc( memSize );
h_c = (int *) malloc( memSize );
if ( h_a == NULL || h_b == NULL || h_c == NULL )
{
perror("Memoria insuficiente\n");
exit(-1);
}
hipMalloc( (void**) &d_a, memSize );
hipMalloc( (void**) &d_b, memSize );
hipMalloc( (void**) &d_c, memSize );
if ( d_a == NULL || d_b == NULL || d_c == NULL )
{
perror("Memoria insuficiente en la GPU\n");
exit(-1);
}
for( int i = 0 ; i < n ; i++ )
{
for( int j = 0 ; j < n ; j++ )
{
h_a[ n * i + j] = 1;
h_b[ n * i + j] = 1;
h_c[ n * i + j] = 0;
}
}
hipMemcpy( d_a, h_a , memSize, hipMemcpyHostToDevice );
hipMemcpy( d_b, h_b , memSize, hipMemcpyHostToDevice );
MultiplocarMatrices<<< 1 , n >>> (d_a, d_b, d_c, n );
hipMemcpy( h_c, d_c, memSize, hipMemcpyDeviceToHost );
// Validación de la multiplicación
// El producto de dos matrices de NxN de unos produce una matriz donde todos los elementos son N
strcpy(validacion, "Ok");
for( int i = 0 ; i < n ; i++ )
{
for( int j = 0 ; j < n ; j++ )
{
if ( h_c[ n * i + j ] != n )
{
strcpy(validacion, "Error");
}
}
}
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
free(h_a);
free(h_b);
free(h_c);
printf ( "\t %10d \t\t %s \t ", n, validacion );
return 0;
} | .text
.file "mm.hip"
.globl _Z34__device_stub__MultiplocarMatricesPiS_S_i # -- Begin function _Z34__device_stub__MultiplocarMatricesPiS_S_i
.p2align 4, 0x90
.type _Z34__device_stub__MultiplocarMatricesPiS_S_i,@function
_Z34__device_stub__MultiplocarMatricesPiS_S_i: # @_Z34__device_stub__MultiplocarMatricesPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19MultiplocarMatricesPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z34__device_stub__MultiplocarMatricesPiS_S_i, .Lfunc_end0-_Z34__device_stub__MultiplocarMatricesPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4, %ebx
cmpl $2, %edi
jl .LBB1_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
cmpl $1024, %eax # imm = 0x400
movl $1024, %ebx # imm = 0x400
cmovll %eax, %ebx
.LBB1_2:
movl %ebx, %r15d
imull %r15d, %r15d
shlq $2, %r15
movq %r15, %rdi
callq malloc
movq %rax, %r14
movq %r15, %rdi
callq malloc
movq %rax, 8(%rsp) # 8-byte Spill
movq %r15, %rdi
callq malloc
movq %r14, 32(%rsp) # 8-byte Spill
testq %r14, %r14
je .LBB1_5
# %bb.3:
cmpq $0, 8(%rsp) # 8-byte Folded Reload
je .LBB1_5
# %bb.4:
testq %rax, %rax
je .LBB1_5
# %bb.7:
movq %rax, 56(%rsp) # 8-byte Spill
leaq 40(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r15, 112(%rsp) # 8-byte Spill
movq %r15, %rsi
callq hipMalloc
movq 40(%rsp), %rax
movq %rax, 104(%rsp) # 8-byte Spill
testq %rax, %rax
je .LBB1_25
# %bb.8:
cmpq $0, 24(%rsp)
je .LBB1_25
# %bb.9:
cmpq $0, 16(%rsp)
je .LBB1_25
# %bb.10: # %.preheader76
movl %ebx, %r13d
testl %ebx, %ebx
jle .LBB1_15
# %bb.11: # %.preheader75.lr.ph
leaq (,%r13,4), %rax
movq %rax, 120(%rsp) # 8-byte Spill
xorl %r14d, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_12: # %.preheader75
# =>This Loop Header: Depth=1
# Child Loop BB1_13 Depth 2
movl %r14d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r12
movq 32(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
movl %ebx, %eax
imull %r15d, %eax
movq 56(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rdi
xorl %esi, %esi
movq 120(%rsp), %rdx # 8-byte Reload
callq memset@PLT
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_13: # Parent Loop BB1_12 Depth=1
# => This Inner Loop Header: Depth=2
movl $1, (%rbp,%rax,4)
movl $1, (%r12,%rax,4)
incq %rax
cmpq %rax, %r13
jne .LBB1_13
# %bb.14: # %._crit_edge
# in Loop: Header=BB1_12 Depth=1
incq %r15
addl %ebx, %r14d
cmpq %r13, %r15
jne .LBB1_12
.LBB1_15: # %._crit_edge79
movq 104(%rsp), %rdi # 8-byte Reload
movq 32(%rsp), %rsi # 8-byte Reload
movq 112(%rsp), %r15 # 8-byte Reload
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq 8(%rsp), %rsi # 8-byte Reload
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967296, %rdi # imm = 0x100000000
leaq (%rdi,%r13), %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_17
# %bb.16:
movq 40(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 192(%rsp)
movq %rcx, 184(%rsp)
movq %rdx, 176(%rsp)
movl %ebx, 52(%rsp)
leaq 192(%rsp), %rax
movq %rax, 64(%rsp)
leaq 184(%rsp), %rax
movq %rax, 72(%rsp)
leaq 176(%rsp), %rax
movq %rax, 80(%rsp)
leaq 52(%rsp), %rax
movq %rax, 88(%rsp)
leaq 160(%rsp), %rdi
leaq 144(%rsp), %rsi
leaq 136(%rsp), %rdx
leaq 128(%rsp), %rcx
callq __hipPopCallConfiguration
movq 160(%rsp), %rsi
movl 168(%rsp), %edx
movq 144(%rsp), %rcx
movl 152(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z19MultiplocarMatricesPiS_S_i, %edi
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_17:
movq 16(%rsp), %rsi
movq 56(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movw $27471, 64(%rsp) # imm = 0x6B4F
movb $0, 66(%rsp)
testl %ebx, %ebx
jle .LBB1_24
# %bb.18: # %.preheader.lr.ph
xorl %eax, %eax
xorl %ecx, %ecx
jmp .LBB1_19
.p2align 4, 0x90
.LBB1_23: # %._crit_edge82
# in Loop: Header=BB1_19 Depth=1
incq %rcx
addl %ebx, %eax
cmpq %r13, %rcx
je .LBB1_24
.LBB1_19: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_20 Depth 2
movl %eax, %edx
leaq (%r14,%rdx,4), %rdx
xorl %esi, %esi
jmp .LBB1_20
.p2align 4, 0x90
.LBB1_22: # in Loop: Header=BB1_20 Depth=2
incq %rsi
cmpq %rsi, %r13
je .LBB1_23
.LBB1_20: # Parent Loop BB1_19 Depth=1
# => This Inner Loop Header: Depth=2
cmpl %ebx, (%rdx,%rsi,4)
je .LBB1_22
# %bb.21: # in Loop: Header=BB1_20 Depth=2
movw $114, 68(%rsp)
movl $1869771333, 64(%rsp) # imm = 0x6F727245
jmp .LBB1_22
.LBB1_24: # %._crit_edge84
movq 40(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi # 8-byte Reload
callq free
movq 8(%rsp), %rdi # 8-byte Reload
callq free
movq %r14, %rdi
callq free
leaq 64(%rsp), %rdx
movl $.L.str.4, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_5:
.cfi_def_cfa_offset 256
movl $.L.str, %edi
jmp .LBB1_6
.LBB1_25:
movl $.L.str.1, %edi
.LBB1_6:
callq perror
movl $-1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19MultiplocarMatricesPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19MultiplocarMatricesPiS_S_i,@object # @_Z19MultiplocarMatricesPiS_S_i
.section .rodata,"a",@progbits
.globl _Z19MultiplocarMatricesPiS_S_i
.p2align 3, 0x0
_Z19MultiplocarMatricesPiS_S_i:
.quad _Z34__device_stub__MultiplocarMatricesPiS_S_i
.size _Z19MultiplocarMatricesPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Memoria insuficiente\n"
.size .L.str, 22
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Memoria insuficiente en la GPU\n"
.size .L.str.1, 32
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Ok"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Error"
.size .L.str.3, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\t %10d \t\t %s \t "
.size .L.str.4, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19MultiplocarMatricesPiS_S_i"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__MultiplocarMatricesPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19MultiplocarMatricesPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19MultiplocarMatricesPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R24, SR_CTAID.X ; /* 0x0000000000187919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff097624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fe20003f06270 */
/*0050*/ IMAD R24, R24, c[0x0][0x0], R3 ; /* 0x0000000018187a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.OR P0, PT, R24, c[0x0][0x178], !P0 ; /* 0x00005e0018007a0c */
/* 0x000fda0004706670 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*0090*/ SHF.R.S32.HI R8, RZ, 0x1f, R9 ; /* 0x0000001fff087819 */
/* 0x000fe20000011409 */
/*00a0*/ IMAD R20, R24, c[0x0][0x178], RZ ; /* 0x00005e0018147a24 */
/* 0x000fe200078e02ff */
/*00b0*/ LOP3.LUT R21, R9.reuse, 0x3, RZ, 0xc0, !PT ; /* 0x0000000309157812 */
/* 0x040fe200078ec0ff */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*00d0*/ IADD3 R22, R9.reuse, -0x1, RZ ; /* 0xffffffff09167810 */
/* 0x040fe20007ffe0ff */
/*00e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00f0*/ SHF.L.U64.HI R8, R9.reuse, 0x2, R8 ; /* 0x0000000209087819 */
/* 0x040fe20000010208 */
/*0100*/ IMAD.SHL.U32 R9, R9, 0x4, RZ ; /* 0x0000000409097824 */
/* 0x000fe200078e00ff */
/*0110*/ IADD3 R6, -R21, c[0x0][0x178], RZ ; /* 0x00005e0015067a10 */
/* 0x000fe20007ffe1ff */
/*0120*/ IMAD.WIDE R10, R20, R13, c[0x0][0x160] ; /* 0x00005800140a7625 */
/* 0x000fc800078e020d */
/*0130*/ IMAD.WIDE R12, R24, R13, c[0x0][0x168] ; /* 0x00005a00180c7625 */
/* 0x000fc800078e020d */
/*0140*/ ISETP.GE.U32.AND P0, PT, R22, 0x3, PT ; /* 0x000000031600780c */
/* 0x000fe20003f06070 */
/*0150*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0160*/ IADD3 R14, R20, R7, RZ ; /* 0x00000007140e7210 */
/* 0x00ffe20007ffe0ff */
/*0170*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0180*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe40007ffe0ff */
/*0190*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fe20000000f00 */
/*01a0*/ IMAD.WIDE R14, R14, R5, c[0x0][0x170] ; /* 0x00005c000e0e7625 */
/* 0x000fe200078e0205 */
/*01b0*/ ISETP.GE.AND P1, PT, R7, c[0x0][0x178], PT ; /* 0x00005e0007007a0c */
/* 0x000fc80003f26270 */
/*01c0*/ STG.E [R14.64], RZ ; /* 0x000000ff0e007986 */
/* 0x0001e2000c101904 */
/*01d0*/ @!P0 BRA 0xef0 ; /* 0x00000d1000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f04270 */
/*01f0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0200*/ MOV R2, R6 ; /* 0x0000000600027202 */
/* 0x000fe20000000f00 */
/*0210*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*0220*/ MOV R16, R10 ; /* 0x0000000a00107202 */
/* 0x000fe20000000f00 */
/*0230*/ IMAD.MOV.U32 R0, RZ, RZ, R12 ; /* 0x000000ffff007224 */
/* 0x000fe400078e000c */
/*0240*/ IMAD.MOV.U32 R19, RZ, RZ, R13 ; /* 0x000000ffff137224 */
/* 0x000fe400078e000d */
/*0250*/ IMAD.MOV.U32 R17, RZ, RZ, R11 ; /* 0x000000ffff117224 */
/* 0x000fc800078e000b */
/*0260*/ @!P0 BRA 0xce0 ; /* 0x00000a7000008947 */
/* 0x000fea0003800000 */
/*0270*/ ISETP.GT.AND P2, PT, R2, 0xc, PT ; /* 0x0000000c0200780c */
/* 0x000fe40003f44270 */
/*0280*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0290*/ @!P2 BRA 0x930 ; /* 0x000006900000a947 */
/* 0x000fea0003800000 */
/*02a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*02b0*/ IMAD.MOV.U32 R18, RZ, RZ, R0 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0000 */
/*02c0*/ LDG.E R25, [R16.64] ; /* 0x0000000410197981 */
/* 0x004ea8000c1e1900 */
/*02d0*/ LDG.E R23, [R18.64] ; /* 0x0000000412177981 */
/* 0x000ea2000c1e1900 */
/*02e0*/ IADD3 R26, P2, R0, R9, RZ ; /* 0x00000009001a7210 */
/* 0x000fc80007f5e0ff */
/*02f0*/ IADD3.X R27, R19, R8, RZ, P2, !PT ; /* 0x00000008131b7210 */
/* 0x000fe200017fe4ff */
/*0300*/ IMAD R23, R23, R25, R4 ; /* 0x0000001917177224 */
/* 0x004fca00078e0204 */
/*0310*/ STG.E [R14.64], R23 ; /* 0x000000170e007986 */
/* 0x0003e8000c101904 */
/*0320*/ LDG.E R0, [R26.64] ; /* 0x000000041a007981 */
/* 0x0004e8000c1e1900 */
/*0330*/ LDG.E R4, [R16.64+0x4] ; /* 0x0000040410047981 */
/* 0x000ee2000c1e1900 */
/*0340*/ IADD3 R26, P2, R26, R9, RZ ; /* 0x000000091a1a7210 */
/* 0x004fca0007f5e0ff */
/*0350*/ IMAD.X R27, R27, 0x1, R8, P2 ; /* 0x000000011b1b7824 */
/* 0x000fe400010e0608 */
/*0360*/ IMAD R25, R0, R4, R23 ; /* 0x0000000400197224 */
/* 0x008fca00078e0217 */
/*0370*/ STG.E [R14.64], R25 ; /* 0x000000190e007986 */
/* 0x0005e8000c101904 */
/*0380*/ LDG.E R0, [R26.64] ; /* 0x000000041a007981 */
/* 0x000e68000c1e1900 */
/*0390*/ LDG.E R4, [R16.64+0x8] ; /* 0x0000080410047981 */
/* 0x000e62000c1e1900 */
/*03a0*/ IADD3 R18, P2, R26, R9, RZ ; /* 0x000000091a127210 */
/* 0x000fca0007f5e0ff */
/*03b0*/ IMAD.X R19, R27, 0x1, R8, P2 ; /* 0x000000011b137824 */
/* 0x000fe400010e0608 */
/*03c0*/ IMAD R23, R0, R4, R25 ; /* 0x0000000400177224 */
/* 0x002fca00078e0219 */
/*03d0*/ STG.E [R14.64], R23 ; /* 0x000000170e007986 */
/* 0x0003e8000c101904 */
/*03e0*/ LDG.E R0, [R18.64] ; /* 0x0000000412007981 */
/* 0x000ea8000c1e1900 */
/*03f0*/ LDG.E R4, [R16.64+0xc] ; /* 0x00000c0410047981 */
/* 0x000ea2000c1e1900 */
/*0400*/ IADD3 R28, P2, R18, R9, RZ ; /* 0x00000009121c7210 */
/* 0x000fc80007f5e0ff */
/*0410*/ IADD3.X R29, R19, R8, RZ, P2, !PT ; /* 0x00000008131d7210 */
/* 0x000fe200017fe4ff */
/*0420*/ IMAD R25, R0, R4, R23 ; /* 0x0000000400197224 */
/* 0x004fca00078e0217 */
/*0430*/ STG.E [R14.64], R25 ; /* 0x000000190e007986 */
/* 0x0005e8000c101904 */
/*0440*/ LDG.E R0, [R28.64] ; /* 0x000000041c007981 */
/* 0x000e68000c1e1900 */
/*0450*/ LDG.E R4, [R16.64+0x10] ; /* 0x0000100410047981 */
/* 0x000e62000c1e1900 */
/*0460*/ IADD3 R18, P2, R28, R9, RZ ; /* 0x000000091c127210 */
/* 0x000fca0007f5e0ff */
/*0470*/ IMAD.X R19, R29, 0x1, R8, P2 ; /* 0x000000011d137824 */
/* 0x000fe400010e0608 */
/*0480*/ IMAD R23, R0, R4, R25 ; /* 0x0000000400177224 */
/* 0x002fca00078e0219 */
/*0490*/ STG.E [R14.64], R23 ; /* 0x000000170e007986 */
/* 0x0003e8000c101904 */
/*04a0*/ LDG.E R0, [R18.64] ; /* 0x0000000412007981 */
/* 0x000ea8000c1e1900 */
/*04b0*/ LDG.E R4, [R16.64+0x14] ; /* 0x0000140410047981 */
/* 0x000ea2000c1e1900 */
/*04c0*/ IADD3 R26, P2, R18, R9, RZ ; /* 0x00000009121a7210 */
/* 0x000fca0007f5e0ff */
/*04d0*/ IMAD.X R27, R19, 0x1, R8, P2 ; /* 0x00000001131b7824 */
/* 0x000fe400010e0608 */
/*04e0*/ IMAD R25, R0, R4, R23 ; /* 0x0000000400197224 */
/* 0x004fca00078e0217 */
/*04f0*/ STG.E [R14.64], R25 ; /* 0x000000190e007986 */
/* 0x0005e8000c101904 */
/*0500*/ LDG.E R0, [R26.64] ; /* 0x000000041a007981 */
/* 0x000e68000c1e1900 */
/*0510*/ LDG.E R4, [R16.64+0x18] ; /* 0x0000180410047981 */
/* 0x000e62000c1e1900 */
/*0520*/ IADD3 R28, P2, R26, R9, RZ ; /* 0x000000091a1c7210 */
/* 0x000fc80007f5e0ff */
/*0530*/ IADD3.X R29, R27, R8, RZ, P2, !PT ; /* 0x000000081b1d7210 */
/* 0x000fe200017fe4ff */
/*0540*/ IMAD R23, R0, R4, R25 ; /* 0x0000000400177224 */
/* 0x002fca00078e0219 */
/*0550*/ STG.E [R14.64], R23 ; /* 0x000000170e007986 */
/* 0x0003e8000c101904 */
/*0560*/ LDG.E R0, [R28.64] ; /* 0x000000041c007981 */
/* 0x000ea8000c1e1900 */
/*0570*/ LDG.E R4, [R16.64+0x1c] ; /* 0x00001c0410047981 */
/* 0x000ea2000c1e1900 */
/*0580*/ IADD3 R18, P2, R28, R9, RZ ; /* 0x000000091c127210 */
/* 0x000fca0007f5e0ff */
/*0590*/ IMAD.X R19, R29, 0x1, R8, P2 ; /* 0x000000011d137824 */
/* 0x000fe400010e0608 */
/*05a0*/ IMAD R25, R0, R4, R23 ; /* 0x0000000400197224 */
/* 0x004fca00078e0217 */
/*05b0*/ STG.E [R14.64], R25 ; /* 0x000000190e007986 */
/* 0x0005e8000c101904 */
/*05c0*/ LDG.E R0, [R18.64] ; /* 0x0000000412007981 */
/* 0x000e68000c1e1900 */
/*05d0*/ LDG.E R4, [R16.64+0x20] ; /* 0x0000200410047981 */
/* 0x000e62000c1e1900 */
/*05e0*/ IADD3 R26, P2, R18, R9, RZ ; /* 0x00000009121a7210 */
/* 0x000fca0007f5e0ff */
/*05f0*/ IMAD.X R27, R19, 0x1, R8, P2 ; /* 0x00000001131b7824 */
/* 0x000fe400010e0608 */
/*0600*/ IMAD R23, R0, R4, R25 ; /* 0x0000000400177224 */
/* 0x002fca00078e0219 */
/*0610*/ STG.E [R14.64], R23 ; /* 0x000000170e007986 */
/* 0x0003e8000c101904 */
/*0620*/ LDG.E R0, [R26.64] ; /* 0x000000041a007981 */
/* 0x000ea8000c1e1900 */
/*0630*/ LDG.E R4, [R16.64+0x24] ; /* 0x0000240410047981 */
/* 0x000ea2000c1e1900 */
/*0640*/ IADD3 R28, P2, R26, R9, RZ ; /* 0x000000091a1c7210 */
/* 0x000fc80007f5e0ff */
/*0650*/ IADD3.X R29, R27, R8, RZ, P2, !PT ; /* 0x000000081b1d7210 */
/* 0x000fe200017fe4ff */
/*0660*/ IMAD R25, R0, R4, R23 ; /* 0x0000000400197224 */
/* 0x004fca00078e0217 */
/*0670*/ STG.E [R14.64], R25 ; /* 0x000000190e007986 */
/* 0x0005e8000c101904 */
/*0680*/ LDG.E R0, [R28.64] ; /* 0x000000041c007981 */
/* 0x000e68000c1e1900 */
/*0690*/ LDG.E R4, [R16.64+0x28] ; /* 0x0000280410047981 */
/* 0x000e62000c1e1900 */
/*06a0*/ IADD3 R18, P2, R28, R9, RZ ; /* 0x000000091c127210 */
/* 0x000fca0007f5e0ff */
/*06b0*/ IMAD.X R19, R29, 0x1, R8, P2 ; /* 0x000000011d137824 */
/* 0x000fe400010e0608 */
/*06c0*/ IMAD R23, R0, R4, R25 ; /* 0x0000000400177224 */
/* 0x002fca00078e0219 */
/*06d0*/ STG.E [R14.64], R23 ; /* 0x000000170e007986 */
/* 0x0003e8000c101904 */
/*06e0*/ LDG.E R0, [R18.64] ; /* 0x0000000412007981 */
/* 0x000ea8000c1e1900 */
/*06f0*/ LDG.E R4, [R16.64+0x2c] ; /* 0x00002c0410047981 */
/* 0x000ea2000c1e1900 */
/*0700*/ IADD3 R26, P2, R18, R9, RZ ; /* 0x00000009121a7210 */
/* 0x000fca0007f5e0ff */
/*0710*/ IMAD.X R27, R19, 0x1, R8, P2 ; /* 0x00000001131b7824 */
/* 0x000fe400010e0608 */
/*0720*/ IMAD R25, R0, R4, R23 ; /* 0x0000000400197224 */
/* 0x004fca00078e0217 */
/*0730*/ STG.E [R14.64], R25 ; /* 0x000000190e007986 */
/* 0x0005e8000c101904 */
/*0740*/ LDG.E R0, [R26.64] ; /* 0x000000041a007981 */
/* 0x000e68000c1e1900 */
/*0750*/ LDG.E R4, [R16.64+0x30] ; /* 0x0000300410047981 */
/* 0x000e62000c1e1900 */
/*0760*/ IADD3 R28, P2, R26, R9, RZ ; /* 0x000000091a1c7210 */
/* 0x000fc80007f5e0ff */
/*0770*/ IADD3.X R29, R27, R8, RZ, P2, !PT ; /* 0x000000081b1d7210 */
/* 0x000fe200017fe4ff */
/*0780*/ IMAD R23, R0, R4, R25 ; /* 0x0000000400177224 */
/* 0x002fca00078e0219 */
/*0790*/ STG.E [R14.64], R23 ; /* 0x000000170e007986 */
/* 0x0003e8000c101904 */
/*07a0*/ LDG.E R0, [R28.64] ; /* 0x000000041c007981 */
/* 0x000ea8000c1e1900 */
/*07b0*/ LDG.E R4, [R16.64+0x34] ; /* 0x0000340410047981 */
/* 0x000ea2000c1e1900 */
/*07c0*/ IADD3 R18, P2, R28, R9, RZ ; /* 0x000000091c127210 */
/* 0x000fca0007f5e0ff */
/*07d0*/ IMAD.X R19, R29, 0x1, R8, P2 ; /* 0x000000011d137824 */
/* 0x000fe400010e0608 */
/*07e0*/ IMAD R25, R0, R4, R23 ; /* 0x0000000400197224 */
/* 0x004fca00078e0217 */
/*07f0*/ STG.E [R14.64], R25 ; /* 0x000000190e007986 */
/* 0x0005e8000c101904 */
/*0800*/ LDG.E R0, [R18.64] ; /* 0x0000000412007981 */
/* 0x000e68000c1e1900 */
/*0810*/ LDG.E R4, [R16.64+0x38] ; /* 0x0000380410047981 */
/* 0x000e62000c1e1900 */
/*0820*/ IADD3 R26, P2, R18, R9, RZ ; /* 0x00000009121a7210 */
/* 0x000fca0007f5e0ff */
/*0830*/ IMAD.X R27, R19, 0x1, R8, P2 ; /* 0x00000001131b7824 */
/* 0x000fe400010e0608 */
/*0840*/ IMAD R23, R0, R4, R25 ; /* 0x0000000400177224 */
/* 0x002fca00078e0219 */
/*0850*/ STG.E [R14.64], R23 ; /* 0x000000170e007986 */
/* 0x0005e8000c101904 */
/*0860*/ LDG.E R4, [R26.64] ; /* 0x000000041a047981 */
/* 0x000ee8000c1e1900 */
/*0870*/ LDG.E R0, [R16.64+0x3c] ; /* 0x00003c0410007981 */
/* 0x0002e2000c1e1900 */
/*0880*/ IADD3 R2, R2, -0x10, RZ ; /* 0xfffffff002027810 */
/* 0x000fc80007ffe0ff */
/*0890*/ ISETP.GT.AND P2, PT, R2, 0xc, PT ; /* 0x0000000c0200780c */
/* 0x000fe40003f44270 */
/*08a0*/ IADD3 R18, P4, R16, 0x40, RZ ; /* 0x0000004010127810 */
/* 0x000fe40007f9e0ff */
/*08b0*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fe40007ffe0ff */
/*08c0*/ IADD3.X R17, RZ, R17, RZ, P4, !PT ; /* 0x00000011ff117210 */
/* 0x002fe200027fe4ff */
/*08d0*/ IMAD.MOV.U32 R16, RZ, RZ, R18 ; /* 0x000000ffff107224 */
/* 0x000fe400078e0012 */
/*08e0*/ IMAD R4, R4, R0, R23 ; /* 0x0000000004047224 */
/* 0x008fe200078e0217 */
/*08f0*/ IADD3 R0, P3, R26, R9, RZ ; /* 0x000000091a007210 */
/* 0x000fc80007f7e0ff */
/*0900*/ STG.E [R14.64], R4 ; /* 0x000000040e007986 */
/* 0x0005e2000c101904 */
/*0910*/ IMAD.X R19, R27, 0x1, R8, P3 ; /* 0x000000011b137824 */
/* 0x000fe200018e0608 */
/*0920*/ @P2 BRA 0x2b0 ; /* 0xfffff98000002947 */
/* 0x000fea000383ffff */
/*0930*/ ISETP.GT.AND P2, PT, R2, 0x4, PT ; /* 0x000000040200780c */
/* 0x000fda0003f44270 */
/*0940*/ @!P2 BRA 0xcc0 ; /* 0x000003700000a947 */
/* 0x000fea0003800000 */
/*0950*/ MOV R18, R0 ; /* 0x0000000000127202 */
/* 0x000fe20000000f00 */
/*0960*/ LDG.E R25, [R16.64] ; /* 0x0000000410197981 */
/* 0x004ea8000c1e1900 */
/*0970*/ LDG.E R23, [R18.64] ; /* 0x0000000412177981 */
/* 0x000ea2000c1e1900 */
/*0980*/ IADD3 R26, P0, R0, R9, RZ ; /* 0x00000009001a7210 */
/* 0x000fca0007f1e0ff */
/*0990*/ IMAD.X R27, R19, 0x1, R8, P0 ; /* 0x00000001131b7824 */
/* 0x000fe400000e0608 */
/*09a0*/ IMAD R23, R23, R25, R4 ; /* 0x0000001917177224 */
/* 0x004fca00078e0204 */
/*09b0*/ STG.E [R14.64], R23 ; /* 0x000000170e007986 */
/* 0x0003e8000c101904 */
/*09c0*/ LDG.E R0, [R26.64] ; /* 0x000000041a007981 */
/* 0x000ea8000c1e1900 */
/*09d0*/ LDG.E R4, [R16.64+0x4] ; /* 0x0000040410047981 */
/* 0x000ea2000c1e1900 */
/*09e0*/ IADD3 R28, P0, R26, R9, RZ ; /* 0x000000091a1c7210 */
/* 0x000fca0007f1e0ff */
/*09f0*/ IMAD.X R29, R27, 0x1, R8, P0 ; /* 0x000000011b1d7824 */
/* 0x000fe400000e0608 */
/*0a00*/ IMAD R25, R0, R4, R23 ; /* 0x0000000400197224 */
/* 0x004fca00078e0217 */
/*0a10*/ STG.E [R14.64], R25 ; /* 0x000000190e007986 */
/* 0x0005e8000c101904 */
/*0a20*/ LDG.E R0, [R28.64] ; /* 0x000000041c007981 */
/* 0x000e68000c1e1900 */
/*0a30*/ LDG.E R4, [R16.64+0x8] ; /* 0x0000080410047981 */
/* 0x000e62000c1e1900 */
/*0a40*/ IADD3 R18, P0, R28, R9, RZ ; /* 0x000000091c127210 */
/* 0x000fc80007f1e0ff */
/*0a50*/ IADD3.X R19, R29, R8, RZ, P0, !PT ; /* 0x000000081d137210 */
/* 0x000fe200007fe4ff */
/*0a60*/ IMAD R23, R0, R4, R25 ; /* 0x0000000400177224 */
/* 0x002fca00078e0219 */
/*0a70*/ STG.E [R14.64], R23 ; /* 0x000000170e007986 */
/* 0x0003e8000c101904 */
/*0a80*/ LDG.E R0, [R18.64] ; /* 0x0000000412007981 */
/* 0x000ea8000c1e1900 */
/*0a90*/ LDG.E R4, [R16.64+0xc] ; /* 0x00000c0410047981 */
/* 0x000ea2000c1e1900 */
/*0aa0*/ IADD3 R26, P0, R18, R9, RZ ; /* 0x00000009121a7210 */
/* 0x000fca0007f1e0ff */
/*0ab0*/ IMAD.X R27, R19, 0x1, R8, P0 ; /* 0x00000001131b7824 */
/* 0x000fe400000e0608 */
/*0ac0*/ IMAD R25, R0, R4, R23 ; /* 0x0000000400197224 */
/* 0x004fca00078e0217 */
/*0ad0*/ STG.E [R14.64], R25 ; /* 0x000000190e007986 */
/* 0x0005e8000c101904 */
/*0ae0*/ LDG.E R0, [R26.64] ; /* 0x000000041a007981 */
/* 0x000e68000c1e1900 */
/*0af0*/ LDG.E R4, [R16.64+0x10] ; /* 0x0000100410047981 */
/* 0x000e62000c1e1900 */
/*0b00*/ IADD3 R28, P0, R26, R9, RZ ; /* 0x000000091a1c7210 */
/* 0x000fca0007f1e0ff */
/*0b10*/ IMAD.X R29, R27, 0x1, R8, P0 ; /* 0x000000011b1d7824 */
/* 0x000fe400000e0608 */
/*0b20*/ IMAD R23, R0, R4, R25 ; /* 0x0000000400177224 */
/* 0x002fca00078e0219 */
/*0b30*/ STG.E [R14.64], R23 ; /* 0x000000170e007986 */
/* 0x0003e8000c101904 */
/*0b40*/ LDG.E R0, [R28.64] ; /* 0x000000041c007981 */
/* 0x000ea8000c1e1900 */
/*0b50*/ LDG.E R4, [R16.64+0x14] ; /* 0x0000140410047981 */
/* 0x000ea2000c1e1900 */
/*0b60*/ IADD3 R18, P0, R28, R9, RZ ; /* 0x000000091c127210 */
/* 0x000fc80007f1e0ff */
/*0b70*/ IADD3.X R19, R29, R8, RZ, P0, !PT ; /* 0x000000081d137210 */
/* 0x000fe200007fe4ff */
/*0b80*/ IMAD R25, R0, R4, R23 ; /* 0x0000000400197224 */
/* 0x004fca00078e0217 */
/*0b90*/ STG.E [R14.64], R25 ; /* 0x000000190e007986 */
/* 0x0005e8000c101904 */
/*0ba0*/ LDG.E R0, [R18.64] ; /* 0x0000000412007981 */
/* 0x000e68000c1e1900 */
/*0bb0*/ LDG.E R4, [R16.64+0x18] ; /* 0x0000180410047981 */
/* 0x000e62000c1e1900 */
/*0bc0*/ IADD3 R26, P0, R18, R9, RZ ; /* 0x00000009121a7210 */
/* 0x000fca0007f1e0ff */
/*0bd0*/ IMAD.X R27, R19, 0x1, R8, P0 ; /* 0x00000001131b7824 */
/* 0x000fe400000e0608 */
/*0be0*/ IMAD R23, R0, R4, R25 ; /* 0x0000000400177224 */
/* 0x002fca00078e0219 */
/*0bf0*/ STG.E [R14.64], R23 ; /* 0x000000170e007986 */
/* 0x0005e8000c101904 */
/*0c00*/ LDG.E R4, [R26.64] ; /* 0x000000041a047981 */
/* 0x000ee8000c1e1900 */
/*0c10*/ LDG.E R0, [R16.64+0x1c] ; /* 0x00001c0410007981 */
/* 0x0002e2000c1e1900 */
/*0c20*/ IADD3 R18, P3, R16, 0x20, RZ ; /* 0x0000002010127810 */
/* 0x000fe40007f7e0ff */
/*0c30*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0c40*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*0c50*/ IADD3 R2, R2, -0x8, RZ ; /* 0xfffffff802027810 */
/* 0x000fe20007ffe0ff */
/*0c60*/ IMAD.X R17, RZ, RZ, R17, P3 ; /* 0x000000ffff117224 */
/* 0x002fe400018e0611 */
/*0c70*/ IMAD.MOV.U32 R16, RZ, RZ, R18 ; /* 0x000000ffff107224 */
/* 0x000fe400078e0012 */
/*0c80*/ IMAD R4, R4, R0, R23 ; /* 0x0000000004047224 */
/* 0x008fca00078e0217 */
/*0c90*/ STG.E [R14.64], R4 ; /* 0x000000040e007986 */
/* 0x0005e2000c101904 */
/*0ca0*/ IADD3 R0, P2, R26, R9, RZ ; /* 0x000000091a007210 */
/* 0x000fc80007f5e0ff */
/*0cb0*/ IADD3.X R19, R27, R8, RZ, P2, !PT ; /* 0x000000081b137210 */
/* 0x000fe400017fe4ff */
/*0cc0*/ ISETP.NE.OR P0, PT, R2, RZ, P0 ; /* 0x000000ff0200720c */
/* 0x000fda0000705670 */
/*0cd0*/ @!P0 BRA 0xef0 ; /* 0x0000021000008947 */
/* 0x000fea0003800000 */
/*0ce0*/ IMAD.MOV.U32 R18, RZ, RZ, R0 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0000 */
/*0cf0*/ LDG.E R25, [R16.64] ; /* 0x0000000410197981 */
/* 0x004ea8000c1e1900 */
/*0d00*/ LDG.E R23, [R18.64] ; /* 0x0000000412177981 */
/* 0x000ea2000c1e1900 */
/*0d10*/ IADD3 R26, P0, R0, R9, RZ ; /* 0x00000009001a7210 */
/* 0x000fc80007f1e0ff */
/*0d20*/ IADD3.X R27, R19, R8, RZ, P0, !PT ; /* 0x00000008131b7210 */
/* 0x000fe200007fe4ff */
/*0d30*/ IMAD R23, R23, R25, R4 ; /* 0x0000001917177224 */
/* 0x004fca00078e0204 */
/*0d40*/ STG.E [R14.64], R23 ; /* 0x000000170e007986 */
/* 0x0003e8000c101904 */
/*0d50*/ LDG.E R0, [R26.64] ; /* 0x000000041a007981 */
/* 0x000ea8000c1e1900 */
/*0d60*/ LDG.E R4, [R16.64+0x4] ; /* 0x0000040410047981 */
/* 0x000ea2000c1e1900 */
/*0d70*/ IADD3 R28, P0, R26, R9, RZ ; /* 0x000000091a1c7210 */
/* 0x000fca0007f1e0ff */
/*0d80*/ IMAD.X R29, R27, 0x1, R8, P0 ; /* 0x000000011b1d7824 */
/* 0x000fe400000e0608 */
/*0d90*/ IMAD R25, R0, R4, R23 ; /* 0x0000000400197224 */
/* 0x004fca00078e0217 */
/*0da0*/ STG.E [R14.64], R25 ; /* 0x000000190e007986 */
/* 0x0005e8000c101904 */
/*0db0*/ LDG.E R0, [R28.64] ; /* 0x000000041c007981 */
/* 0x000e68000c1e1900 */
/*0dc0*/ LDG.E R4, [R16.64+0x8] ; /* 0x0000080410047981 */
/* 0x000e62000c1e1900 */
/*0dd0*/ IADD3 R18, P0, R28, R9, RZ ; /* 0x000000091c127210 */
/* 0x000fca0007f1e0ff */
/*0de0*/ IMAD.X R19, R29, 0x1, R8, P0 ; /* 0x000000011d137824 */
/* 0x000fe400000e0608 */
/*0df0*/ IMAD R23, R0, R4, R25 ; /* 0x0000000400177224 */
/* 0x002fca00078e0219 */
/*0e00*/ STG.E [R14.64], R23 ; /* 0x000000170e007986 */
/* 0x0003e8000c101904 */
/*0e10*/ LDG.E R4, [R18.64] ; /* 0x0000000412047981 */
/* 0x000ee8000c1e1900 */
/*0e20*/ LDG.E R0, [R16.64+0xc] ; /* 0x00000c0410007981 */
/* 0x0008e2000c1e1900 */
/*0e30*/ IADD3 R2, R2, -0x4, RZ ; /* 0xfffffffc02027810 */
/* 0x000fc80007ffe0ff */
/*0e40*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f05270 */
/*0e50*/ IADD3 R25, P2, R16, 0x10, RZ ; /* 0x0000001010197810 */
/* 0x004fc80007f5e0ff */
/*0e60*/ IADD3.X R26, RZ, R17, RZ, P2, !PT ; /* 0x00000011ff1a7210 */
/* 0x000fe400017fe4ff */
/*0e70*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fe40007ffe0ff */
/*0e80*/ MOV R16, R25 ; /* 0x0000001900107202 */
/* 0x010fe20000000f00 */
/*0e90*/ IMAD.MOV.U32 R17, RZ, RZ, R26 ; /* 0x000000ffff117224 */
/* 0x000fe400078e001a */
/*0ea0*/ IMAD R4, R4, R0, R23 ; /* 0x0000000004047224 */
/* 0x008fe200078e0217 */
/*0eb0*/ IADD3 R0, P3, R18, R9, RZ ; /* 0x0000000912007210 */
/* 0x000fc80007f7e0ff */
/*0ec0*/ STG.E [R14.64], R4 ; /* 0x000000040e007986 */
/* 0x0003e2000c101904 */
/*0ed0*/ IMAD.X R19, R19, 0x1, R8, P3 ; /* 0x0000000113137824 */
/* 0x000fe200018e0608 */
/*0ee0*/ @P0 BRA 0xce0 ; /* 0xfffffdf000000947 */
/* 0x003fea000383ffff */
/*0ef0*/ ISETP.NE.AND P0, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fda0003f05270 */
/*0f00*/ @!P0 BRA 0x1090 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0f10*/ IADD3 R2, R20, R3, RZ ; /* 0x0000000314027210 */
/* 0x000fe20007ffe0ff */
/*0f20*/ IMAD R18, R3, c[0x0][0x178], R24 ; /* 0x00005e0003127a24 */
/* 0x000fc800078e0218 */
/*0f30*/ IMAD.WIDE R16, R18, R5, c[0x0][0x168] ; /* 0x00005a0012107625 */
/* 0x000fc800078e0205 */
/*0f40*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe400078e0205 */
/*0f50*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee8000c1e1900 */
/*0f60*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ee2000c1e1900 */
/*0f70*/ ISETP.NE.AND P0, PT, R21, 0x1, PT ; /* 0x000000011500780c */
/* 0x000fe20003f05270 */
/*0f80*/ IMAD R23, R17, R0, R4 ; /* 0x0000000011177224 */
/* 0x00cfca00078e0204 */
/*0f90*/ STG.E [R14.64], R23 ; /* 0x000000170e007986 */
/* 0x0003ee000c101904 */
/*0fa0*/ @!P0 BRA 0x1090 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0fb0*/ IADD3 R4, R18, c[0x0][0x178], RZ ; /* 0x00005e0012047a10 */
/* 0x000fe20007ffe0ff */
/*0fc0*/ LDG.E R19, [R2.64+0x4] ; /* 0x0000040402137981 */
/* 0x000ea8000c1e1900 */
/*0fd0*/ IMAD.WIDE R16, R4, R5, c[0x0][0x168] ; /* 0x00005a0004107625 */
/* 0x000fcc00078e0205 */
/*0fe0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea2000c1e1900 */
/*0ff0*/ ISETP.NE.AND P0, PT, R21, 0x2, PT ; /* 0x000000021500780c */
/* 0x000fe20003f05270 */
/*1000*/ IMAD R19, R16, R19, R23 ; /* 0x0000001310137224 */
/* 0x004fca00078e0217 */
/*1010*/ STG.E [R14.64], R19 ; /* 0x000000130e007986 */
/* 0x0005ee000c101904 */
/*1020*/ @!P0 BRA 0x1090 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*1030*/ IADD3 R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a10 */
/* 0x000fe20007ffe0ff */
/*1040*/ LDG.E R3, [R2.64+0x8] ; /* 0x0000080402037981 */
/* 0x000ee8000c1e1900 */
/*1050*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fcc00078e0205 */
/*1060*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee4000c1e1900 */
/*1070*/ IMAD R17, R4, R3, R19 ; /* 0x0000000304117224 */
/* 0x008fca00078e0213 */
/*1080*/ STG.E [R14.64], R17 ; /* 0x000000110e007986 */
/* 0x0007e4000c101904 */
/*1090*/ @P1 CALL.REL.NOINC 0x10b0 ; /* 0x0000001000001944 */
/* 0x000fe20003c00000 */
/*10a0*/ BRA 0x140 ; /* 0xfffff09000007947 */
/* 0x000fea000383ffff */
/*10b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*10c0*/ BRA 0x10c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19MultiplocarMatricesPiS_S_i
.globl _Z19MultiplocarMatricesPiS_S_i
.p2align 8
.type _Z19MultiplocarMatricesPiS_S_i,@function
_Z19MultiplocarMatricesPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, 0
v_max_i32_e32 v0, 0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s2
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v11, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_dual_mov_b32 v0, 0 :: v_dual_add_nc_u32 v5, s3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_mov_b32 v8, v4 :: v_dual_mov_b32 v7, v3
v_mov_b32_e32 v9, v1
v_ashrrev_i32_e32 v6, 31, v5
s_mov_b32 s4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, vcc_lo, s0, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
global_store_b32 v[5:6], v11, off
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v10, 31, v9
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s2, s4
v_lshlrev_b64 v[12:13], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v12, vcc_lo, s6, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
global_load_b32 v10, v[7:8], off
global_load_b32 v14, v[12:13], off
v_add_co_u32 v7, vcc_lo, v7, 4
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[12:13], null, v14, v10, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v0, v12 :: v_dual_add_nc_u32 v9, s2, v9
global_store_b32 v[5:6], v12, off
s_cbranch_scc1 .LBB0_3
s_add_i32 s3, s3, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s3, s2
s_cbranch_scc1 .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19MultiplocarMatricesPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19MultiplocarMatricesPiS_S_i, .Lfunc_end0-_Z19MultiplocarMatricesPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19MultiplocarMatricesPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19MultiplocarMatricesPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f1d1e_00000000-6_mm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z19MultiplocarMatricesPiS_S_iPiS_S_i
.type _Z44__device_stub__Z19MultiplocarMatricesPiS_S_iPiS_S_i, @function
_Z44__device_stub__Z19MultiplocarMatricesPiS_S_iPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19MultiplocarMatricesPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z44__device_stub__Z19MultiplocarMatricesPiS_S_iPiS_S_i, .-_Z44__device_stub__Z19MultiplocarMatricesPiS_S_iPiS_S_i
.globl _Z19MultiplocarMatricesPiS_S_i
.type _Z19MultiplocarMatricesPiS_S_i, @function
_Z19MultiplocarMatricesPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z19MultiplocarMatricesPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z19MultiplocarMatricesPiS_S_i, .-_Z19MultiplocarMatricesPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Memoria insuficiente\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Memoria insuficiente en la GPU\n"
.section .rodata.str1.1
.LC2:
.string "\t %10d \t\t %s \t "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $4, %ebx
cmpl $1, %edi
jg .L30
.L12:
movl %ebx, %r14d
imull %ebx, %r14d
movslq %r14d, %r14
salq $2, %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %r13
movq %r14, %rdi
call malloc@PLT
movq %rax, %r12
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
testq %r13, %r13
sete %al
testq %r12, %r12
sete %dl
orb %dl, %al
jne .L26
testq %rbp, %rbp
je .L26
leaq 8(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movq 8(%rsp), %rdi
testq %rdi, %rdi
je .L15
cmpq $0, 16(%rsp)
je .L15
cmpq $0, 24(%rsp)
je .L15
testl %ebx, %ebx
jle .L16
movslq %ebx, %rsi
leaq 0(,%rsi,4), %r8
negq %rsi
salq $2, %rsi
movq %r8, %rdx
movl $0, %ecx
.L17:
leaq (%rdx,%rsi), %rax
.L18:
movl $1, 0(%r13,%rax)
movl $1, (%r12,%rax)
movl $0, 0(%rbp,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L18
addl $1, %ecx
addq %r8, %rdx
cmpl %ecx, %ebx
jne .L17
.L16:
movl $1, %ecx
movq %r14, %rdx
movq %r13, %rsi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebx, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L19:
movl $2, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movw $27471, 62(%rsp)
movb $0, 64(%rsp)
testl %ebx, %ebx
jle .L20
movslq %ebx, %rsi
leaq 0(,%rsi,4), %rdi
leaq 0(%rbp,%rdi), %rdx
negq %rsi
salq $2, %rsi
movl $0, %ecx
jmp .L21
.L30:
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl $1024, %eax
cmpl %eax, %ebx
cmovg %eax, %ebx
jmp .L12
.L26:
leaq .LC0(%rip), %rdi
call perror@PLT
movl $-1, %edi
call exit@PLT
.L15:
leaq .LC1(%rip), %rdi
call perror@PLT
movl $-1, %edi
call exit@PLT
.L31:
movl %ebx, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z44__device_stub__Z19MultiplocarMatricesPiS_S_iPiS_S_i
jmp .L19
.L22:
addq $4, %rax
cmpq %rdx, %rax
je .L32
.L23:
cmpl %ebx, (%rax)
je .L22
movl $1869771333, 62(%rsp)
movw $114, 66(%rsp)
jmp .L22
.L32:
addl $1, %ecx
addq %rdi, %rdx
cmpl %ecx, %ebx
je .L20
.L21:
leaq (%rdx,%rsi), %rax
jmp .L23
.L20:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
leaq 62(%rsp), %rcx
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L33
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC3:
.string "_Z19MultiplocarMatricesPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z19MultiplocarMatricesPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mm.hip"
.globl _Z34__device_stub__MultiplocarMatricesPiS_S_i # -- Begin function _Z34__device_stub__MultiplocarMatricesPiS_S_i
.p2align 4, 0x90
.type _Z34__device_stub__MultiplocarMatricesPiS_S_i,@function
_Z34__device_stub__MultiplocarMatricesPiS_S_i: # @_Z34__device_stub__MultiplocarMatricesPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19MultiplocarMatricesPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z34__device_stub__MultiplocarMatricesPiS_S_i, .Lfunc_end0-_Z34__device_stub__MultiplocarMatricesPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4, %ebx
cmpl $2, %edi
jl .LBB1_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
cmpl $1024, %eax # imm = 0x400
movl $1024, %ebx # imm = 0x400
cmovll %eax, %ebx
.LBB1_2:
movl %ebx, %r15d
imull %r15d, %r15d
shlq $2, %r15
movq %r15, %rdi
callq malloc
movq %rax, %r14
movq %r15, %rdi
callq malloc
movq %rax, 8(%rsp) # 8-byte Spill
movq %r15, %rdi
callq malloc
movq %r14, 32(%rsp) # 8-byte Spill
testq %r14, %r14
je .LBB1_5
# %bb.3:
cmpq $0, 8(%rsp) # 8-byte Folded Reload
je .LBB1_5
# %bb.4:
testq %rax, %rax
je .LBB1_5
# %bb.7:
movq %rax, 56(%rsp) # 8-byte Spill
leaq 40(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r15, 112(%rsp) # 8-byte Spill
movq %r15, %rsi
callq hipMalloc
movq 40(%rsp), %rax
movq %rax, 104(%rsp) # 8-byte Spill
testq %rax, %rax
je .LBB1_25
# %bb.8:
cmpq $0, 24(%rsp)
je .LBB1_25
# %bb.9:
cmpq $0, 16(%rsp)
je .LBB1_25
# %bb.10: # %.preheader76
movl %ebx, %r13d
testl %ebx, %ebx
jle .LBB1_15
# %bb.11: # %.preheader75.lr.ph
leaq (,%r13,4), %rax
movq %rax, 120(%rsp) # 8-byte Spill
xorl %r14d, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_12: # %.preheader75
# =>This Loop Header: Depth=1
# Child Loop BB1_13 Depth 2
movl %r14d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r12
movq 32(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
movl %ebx, %eax
imull %r15d, %eax
movq 56(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rdi
xorl %esi, %esi
movq 120(%rsp), %rdx # 8-byte Reload
callq memset@PLT
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_13: # Parent Loop BB1_12 Depth=1
# => This Inner Loop Header: Depth=2
movl $1, (%rbp,%rax,4)
movl $1, (%r12,%rax,4)
incq %rax
cmpq %rax, %r13
jne .LBB1_13
# %bb.14: # %._crit_edge
# in Loop: Header=BB1_12 Depth=1
incq %r15
addl %ebx, %r14d
cmpq %r13, %r15
jne .LBB1_12
.LBB1_15: # %._crit_edge79
movq 104(%rsp), %rdi # 8-byte Reload
movq 32(%rsp), %rsi # 8-byte Reload
movq 112(%rsp), %r15 # 8-byte Reload
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq 8(%rsp), %rsi # 8-byte Reload
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967296, %rdi # imm = 0x100000000
leaq (%rdi,%r13), %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_17
# %bb.16:
movq 40(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 192(%rsp)
movq %rcx, 184(%rsp)
movq %rdx, 176(%rsp)
movl %ebx, 52(%rsp)
leaq 192(%rsp), %rax
movq %rax, 64(%rsp)
leaq 184(%rsp), %rax
movq %rax, 72(%rsp)
leaq 176(%rsp), %rax
movq %rax, 80(%rsp)
leaq 52(%rsp), %rax
movq %rax, 88(%rsp)
leaq 160(%rsp), %rdi
leaq 144(%rsp), %rsi
leaq 136(%rsp), %rdx
leaq 128(%rsp), %rcx
callq __hipPopCallConfiguration
movq 160(%rsp), %rsi
movl 168(%rsp), %edx
movq 144(%rsp), %rcx
movl 152(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z19MultiplocarMatricesPiS_S_i, %edi
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_17:
movq 16(%rsp), %rsi
movq 56(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movw $27471, 64(%rsp) # imm = 0x6B4F
movb $0, 66(%rsp)
testl %ebx, %ebx
jle .LBB1_24
# %bb.18: # %.preheader.lr.ph
xorl %eax, %eax
xorl %ecx, %ecx
jmp .LBB1_19
.p2align 4, 0x90
.LBB1_23: # %._crit_edge82
# in Loop: Header=BB1_19 Depth=1
incq %rcx
addl %ebx, %eax
cmpq %r13, %rcx
je .LBB1_24
.LBB1_19: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_20 Depth 2
movl %eax, %edx
leaq (%r14,%rdx,4), %rdx
xorl %esi, %esi
jmp .LBB1_20
.p2align 4, 0x90
.LBB1_22: # in Loop: Header=BB1_20 Depth=2
incq %rsi
cmpq %rsi, %r13
je .LBB1_23
.LBB1_20: # Parent Loop BB1_19 Depth=1
# => This Inner Loop Header: Depth=2
cmpl %ebx, (%rdx,%rsi,4)
je .LBB1_22
# %bb.21: # in Loop: Header=BB1_20 Depth=2
movw $114, 68(%rsp)
movl $1869771333, 64(%rsp) # imm = 0x6F727245
jmp .LBB1_22
.LBB1_24: # %._crit_edge84
movq 40(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi # 8-byte Reload
callq free
movq 8(%rsp), %rdi # 8-byte Reload
callq free
movq %r14, %rdi
callq free
leaq 64(%rsp), %rdx
movl $.L.str.4, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_5:
.cfi_def_cfa_offset 256
movl $.L.str, %edi
jmp .LBB1_6
.LBB1_25:
movl $.L.str.1, %edi
.LBB1_6:
callq perror
movl $-1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19MultiplocarMatricesPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19MultiplocarMatricesPiS_S_i,@object # @_Z19MultiplocarMatricesPiS_S_i
.section .rodata,"a",@progbits
.globl _Z19MultiplocarMatricesPiS_S_i
.p2align 3, 0x0
_Z19MultiplocarMatricesPiS_S_i:
.quad _Z34__device_stub__MultiplocarMatricesPiS_S_i
.size _Z19MultiplocarMatricesPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Memoria insuficiente\n"
.size .L.str, 22
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Memoria insuficiente en la GPU\n"
.size .L.str.1, 32
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Ok"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Error"
.size .L.str.3, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\t %10d \t\t %s \t "
.size .L.str.4, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19MultiplocarMatricesPiS_S_i"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__MultiplocarMatricesPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19MultiplocarMatricesPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | char *title = "Erosion and Dilation filter";
char *description = "Erosion and Dilation filter";
/*
Фильтр «минимум» – также известный как фильтр эрозии, заменяет значение минимальным в окрестности.
Фильтр «максимум» – также известный как фильтр расширения, заменяет значение максимальным в окрестности.
*/
#include <iostream>
#include <cstdio>
#include <cstdlib>
#include <assert.h>
#include <time.h>
#include <cuda.h>
#include <cuda_runtime.h>
#ifndef max
#define max( a, b ) ( ((a) > (b)) ? (a) : (b) )
#endif
#ifndef min
#define min( a, b ) ( ((a) < (b)) ? (a) : (b) )
#endif
#ifndef uint8_t
typedef unsigned char uint8_t;
#endif
#ifndef uint16_t
typedef unsigned short uint16_t;
#endif
#ifndef uint32_t
typedef unsigned int uint32_t;
#endif
// http://en.wikipedia.org/wiki/BMP_file_format
#define BMPMAGIC 0x00
#define BMPFILESIZE 0x02
#define BMPOFFSET 0x0A
#define BMPDIBSISE 0x0E
#define BMPWIDTH 0x12
#define BMPHEIGHT 0x16
#define BMPBITSPERPIXEL 0x1C
typedef struct {
uint8_t magic[2]; /* the magic number used to identify the BMP file:
0x42 0x4D (Hex code points for B and M).
The following entries are possible:
BM - Windows 3.1x, 95, NT, ... etc
BA - OS/2 Bitmap Array
CI - OS/2 Color Icon
CP - OS/2 Color Pointer
IC - OS/2 Icon
PT - OS/2 Pointer. */
uint32_t filesz; /* the size of the BMP file in bytes */
uint16_t creator1; /* reserved. */
uint16_t creator2; /* reserved. */
uint32_t offset; /* the offset, i.e. starting address,
of the byte where the bitmap data can be found. */
} bmp_header_t;
typedef struct {
uint32_t header_sz; /* the size of this header (40 bytes) */
uint32_t width; /* the bitmap width in pixels */
uint32_t height; /* the bitmap height in pixels */
uint16_t nplanes; /* the number of color planes being used.
Must be set to 1. */
uint16_t depth; /* the number of bits per pixel,
which is the color depth of the image.
Typical values are 1, 4, 8, 16, 24 and 32. */
uint32_t compress_type; /* the compression method being used.
See also bmp_compression_method_t. */
uint32_t bmp_bytesz; /* the image size. This is the size of the raw bitmap
data (see below), and should not be confused
with the file size. */
uint32_t hres; /* the horizontal resolution of the image.
(pixel per meter) */
uint32_t vres; /* the vertical resolution of the image.
(pixel per meter) */
uint32_t ncolors; /* the number of colors in the color palette,
or 0 to default to 2<sup><i>n</i></sup>. */
uint32_t nimpcolors; /* the number of important colors used,
or 0 when every color is important;
generally ignored. */
} bmp_dib_v3_header_t;
__global__ void global_set2grayscale(
float *grayscale,
unsigned int *input,
float weight,
int width,
int height)
{
for (int id = blockDim.x*blockIdx.x + threadIdx.x;
id < width*height;
id += blockDim.x*gridDim.x) {
grayscale[id] += weight*(float)(input[id]&0xFF);
}
}
__global__ void global_add2grayscale(
float *grayscale,
unsigned int *input,
float weight,
int width,
int height)
{
for (int id = blockDim.x*blockIdx.x + threadIdx.x;
id < width*height;
id += blockDim.x*gridDim.x) {
grayscale[id] += weight*(float)(input[id]&0xFF);
}
}
// Поиск индекса элемента с наилучшим значением интенсивности
__global__ void global_find2grayscale(
float *grayscale,
unsigned int *index,
int width,
int height,
float radius2,
int mode)
{
int radius = 1;
while((float)radius*radius<radius2) radius++; // поскольку числа маленькие, то быстрее перебором
if(mode>0){ // если расширение
for (int id = blockDim.x*blockIdx.x + threadIdx.x;
id < width*height;
id += blockDim.x*gridDim.x) {
int x=id%width;
int y=id/width;
int currentId = id;
// перебираем пиксели в окружности
for(int i=max(0,x-radius);i<=min(width,x+radius);i++){
for(int j=max(0,y-radius);j<=min(height,y+radius);j++){
if((float)((i-x)*(i-x)+(j-y)*(j-y))<=radius2) {
int itemId = j*width+i;
if(grayscale[itemId]>grayscale[currentId]) currentId=itemId;
}
}
}
index[id] = currentId;
}
} else if(mode<0){ // если эрозия
for (int id = blockDim.x*blockIdx.x + threadIdx.x;
id < width*height;
id += blockDim.x*gridDim.x) {
int x=id%width;
int y=id/width;
int currentId = id;
// перебираем пиксели в окружности
for(int i=max(0,x-radius);i<=min(width,x+radius);i++){
for(int j=max(0,y-radius);j<=min(height,y+radius);j++){
if((float)((i-x)*(i-x)+(j-y)*(j-y))<=radius2) {
int itemId = j*width+i;
if(grayscale[itemId]<grayscale[currentId]) currentId=itemId;
}
}
}
index[id] = currentId;
}
}else {
for (int id = blockDim.x*blockIdx.x + threadIdx.x;
id < width*height;
id += blockDim.x*gridDim.x) {
index[id] = id;
}
}
}
// Получение цвета из таблицы по индексу
__global__ void global_indexcolor(
unsigned int *input,
unsigned int *output,
unsigned int *index,
int width,
int height)
{
for (int id = blockDim.x*blockIdx.x + threadIdx.x;
id < width*height;
id += blockDim.x*gridDim.x) {
output[id] = input[index[id]];
}
}
__host__ void host_erosiondilationfilter(
int gridSize,
int blockSize,
unsigned int *r,
unsigned int *g,
unsigned int *b,
int width,
int height,
float radius2,
int mode)
{
// формула для конвертации RGB в интенсивность
// http://en.wikipedia.org/wiki/Grayscale
// Y = 0.2126 * R + 0.7152 * G + 0.0722 * B
unsigned int *channel[3] = { r,g,b };
float weight[3] = {0.2126f, 0.7152f, 0.0722f};
// channel - массив данных
// width - ширина
// height - высота
cudaError_t err;
float *device_grayscale;
unsigned int *device_input;
unsigned int *device_output;
unsigned int *device_index;
err = cudaMalloc((void**)&device_input, width*height*sizeof(unsigned int));
err = cudaMalloc((void**)&device_grayscale, width*height*sizeof(float));
int blocks = (gridSize > 0)? gridSize : min(15, (int)sqrt(width*height));
int threads = (blockSize > 0)? blockSize : min(15, (int)sqrt(width*height));
// Шаг 1. Рассчитываем монохромное изображение
cudaMemcpy(device_input, channel[0], width*height*sizeof(unsigned int), cudaMemcpyHostToDevice);
global_set2grayscale <<< blocks, threads >>>(device_grayscale, device_input, weight[0], width, height);
for(int j=1;j<3;j++){
cudaMemcpy(device_input, channel[j], width*height*sizeof(unsigned int), cudaMemcpyHostToDevice);
global_add2grayscale <<< blocks, threads >>>(device_grayscale, device_input, weight[j], width, height);
}
err = cudaMalloc((void**)&device_index, width*height*sizeof(unsigned int));
// Шаг 2. Находим индексы (то есть находим требуемую замену пикселей)
global_find2grayscale <<< blocks, threads >>>(device_grayscale, device_index, width, height, radius2, mode);
cudaFree((void*)device_grayscale);
err = cudaMalloc((void**)&device_output, width*height*sizeof(unsigned int));
// Шаг 3. Заменяем пиксели согласно ранее полученной подстановке
for(int j=3;j-->0;){
// Перевый раз копировать в видео память не надо, поскольку уже копировали при подсчёте монохромного изображения
if(j<2) cudaMemcpy(device_input, channel[j], width*height*sizeof(unsigned int), cudaMemcpyHostToDevice);
global_indexcolor <<< blocks, threads >>>(device_input, device_output, device_index, width, height);
cudaMemcpy(channel[j], device_output, width*height*sizeof(unsigned int), cudaMemcpyDeviceToHost);
}
cudaFree((void*)device_index);
cudaFree((void*)device_input);
cudaFree((void*)device_output);
err = err;
}
int main(int argc, char* argv[])
{
int i, j;
std::cout << title << std::endl;
// Find/set the device.
int device_count = 0;
cudaGetDeviceCount(&device_count);
for (i = 0; i < device_count; ++i)
{
cudaDeviceProp properties;
cudaGetDeviceProperties(&properties, i);
std::cout << "Running on GPU " << i << " (" << properties.name << ")" << std::endl;
}
if (argc < 5){
printf("Usage :\t%s filter radius2 inputfilename.bmp ouputfilename.bmp\n", argv[0]);
exit(-1);
}
// Получаем параметры - имена файлов
char *filter = argv[1];
float radius2 = atof(argv[2]);
char *inputFileName = argv[3];
char *outputFileName = argv[4];
int gridSize = (argc>5)?atoi(argv[5]):0;
int blockSize = (argc>6)?atoi(argv[6]):0;
int mode = (strcmp(filter,"dilation")==0)?1:-1;
printf("Title :\t%s\n", title);
printf("Description :\t%s\n", description);
printf("Filter :\t%s\n", filter);
printf("Radius2 :\t%d\n", radius2);
printf("Input file name :\t%s\n", inputFileName);
printf("Output file name :\t%s\n", outputFileName);
FILE *file = fopen(inputFileName, "rb");
if (!file) {
fprintf(stderr, "Open file error (%s)\n", inputFileName);
fflush(stderr);
exit(-1);
}
fseek(file, 0L, SEEK_END);
long size = ftell(file);
unsigned char *buffer = (unsigned char *)malloc((size_t)size);
fseek(file, 0L, SEEK_SET);
fread((void*)buffer, (size_t)1, (size_t)size, file);
fclose(file);
uint32_t width = *(uint32_t *)&buffer[BMPWIDTH];
uint32_t height = *(uint32_t *)&buffer[BMPHEIGHT];
uint32_t file_size = *(uint32_t *)&buffer[BMPFILESIZE];
uint32_t offset = *(uint32_t *)&buffer[BMPOFFSET];
uint16_t bits_per_pixel = *(uint16_t *)&buffer[BMPBITSPERPIXEL];
uint16_t bytes_per_pixel = ((int)((bits_per_pixel+7)/8));
uint32_t bytes_per_line = ((int)((bits_per_pixel * width+31)/32))*4; // http://en.wikipedia.org/wiki/BMP_file_format
printf("BMP image size :\t%ld x %ld\n", width, height);
printf("BMP file size :\t%ld\n", file_size);
printf("BMP pixels offset :\t%ld\n", offset);
printf("BMP bits per pixel :\t%d\n", bits_per_pixel);
printf("BMP bytes per pixel :\t%d\n", bytes_per_pixel);
printf("BMP bytes per line :\t%d\n", bytes_per_line);
uint8_t *pixels =(uint8_t *)&buffer[offset];
uint8_t *pixel;
uint32_t x, y;
/* выделение памяти под байтовые цветовые каналы */
int count = width*height;
unsigned int* channel[3];
for (j = 0; j < 3; j++)
channel[j] = (unsigned int*)malloc(count*sizeof(unsigned int));
int pos = 0;
for (y = 0; y < height; y++) {
for (x = 0; x < width; x++) {
pixel = &pixels[y*bytes_per_line+x*bytes_per_pixel];
channel[0][pos] = (unsigned int)pixel[0];
channel[1][pos] = (unsigned int)pixel[1];
channel[2][pos] = (unsigned int)pixel[2];
pos++;
}
}
clock_t t1, t2;
t1 = clock();
host_erosiondilationfilter(gridSize, blockSize,
channel[0], channel[1], channel[2],
(int)width, (int)height,
radius2, mode);
t2 = clock();
double seconds = ((double)(t2-t1))/CLOCKS_PER_SEC;
printf("Execution time :\t%le\n", seconds);
pos = 0;
for (y = 0; y < height; y++) {
for (x = 0; x < width; x++) {
pixel = &pixels[y*bytes_per_line+x*bytes_per_pixel];
pixel[0] = (uint8_t)channel[0][pos];
pixel[1] = (uint8_t)channel[1][pos];
pixel[2] = (uint8_t)channel[2][pos];
pos++;
}
}
/* высвобождаем массивы */
for (j = 0; j < 3; j++)
free(channel[j]);
/* выводим результаты */
file = fopen(outputFileName, "wb");
if (!file) {
fprintf(stderr, "Open file error (%s)\n", outputFileName);
fflush(stderr);
exit(-1);
}
fwrite((void*)buffer, (size_t)1, (size_t)size, file);
printf("Output file size :\t%ld\n", size);
free(buffer);
fclose(file);
cudaDeviceReset();
exit(0);
} | .file "tmpxft_0016de85_00000000-6_cudaerosiondilationfilter.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z20global_set2grayscalePfPjfiiPfPjfii
.type _Z45__device_stub__Z20global_set2grayscalePfPjfiiPfPjfii, @function
_Z45__device_stub__Z20global_set2grayscalePfPjfiiPfPjfii:
.LFB3695:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20global_set2grayscalePfPjfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z45__device_stub__Z20global_set2grayscalePfPjfiiPfPjfii, .-_Z45__device_stub__Z20global_set2grayscalePfPjfiiPfPjfii
.globl _Z20global_set2grayscalePfPjfii
.type _Z20global_set2grayscalePfPjfii, @function
_Z20global_set2grayscalePfPjfii:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z20global_set2grayscalePfPjfiiPfPjfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z20global_set2grayscalePfPjfii, .-_Z20global_set2grayscalePfPjfii
.globl _Z45__device_stub__Z20global_add2grayscalePfPjfiiPfPjfii
.type _Z45__device_stub__Z20global_add2grayscalePfPjfiiPfPjfii, @function
_Z45__device_stub__Z20global_add2grayscalePfPjfiiPfPjfii:
.LFB3697:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20global_add2grayscalePfPjfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z45__device_stub__Z20global_add2grayscalePfPjfiiPfPjfii, .-_Z45__device_stub__Z20global_add2grayscalePfPjfiiPfPjfii
.globl _Z20global_add2grayscalePfPjfii
.type _Z20global_add2grayscalePfPjfii, @function
_Z20global_add2grayscalePfPjfii:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z20global_add2grayscalePfPjfiiPfPjfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z20global_add2grayscalePfPjfii, .-_Z20global_add2grayscalePfPjfii
.globl _Z47__device_stub__Z21global_find2grayscalePfPjiifiPfPjiifi
.type _Z47__device_stub__Z21global_find2grayscalePfPjiifiPfPjiifi, @function
_Z47__device_stub__Z21global_find2grayscalePfPjiifiPfPjiifi:
.LFB3699:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21global_find2grayscalePfPjiifi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _Z47__device_stub__Z21global_find2grayscalePfPjiifiPfPjiifi, .-_Z47__device_stub__Z21global_find2grayscalePfPjiifiPfPjiifi
.globl _Z21global_find2grayscalePfPjiifi
.type _Z21global_find2grayscalePfPjiifi, @function
_Z21global_find2grayscalePfPjiifi:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z21global_find2grayscalePfPjiifiPfPjiifi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _Z21global_find2grayscalePfPjiifi, .-_Z21global_find2grayscalePfPjiifi
.globl _Z43__device_stub__Z17global_indexcolorPjS_S_iiPjS_S_ii
.type _Z43__device_stub__Z17global_indexcolorPjS_S_iiPjS_S_ii, @function
_Z43__device_stub__Z17global_indexcolorPjS_S_iiPjS_S_ii:
.LFB3701:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17global_indexcolorPjS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3701:
.size _Z43__device_stub__Z17global_indexcolorPjS_S_iiPjS_S_ii, .-_Z43__device_stub__Z17global_indexcolorPjS_S_iiPjS_S_ii
.globl _Z17global_indexcolorPjS_S_ii
.type _Z17global_indexcolorPjS_S_ii, @function
_Z17global_indexcolorPjS_S_ii:
.LFB3702:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z17global_indexcolorPjS_S_iiPjS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _Z17global_indexcolorPjS_S_ii, .-_Z17global_indexcolorPjS_S_ii
.globl _Z26host_erosiondilationfilteriiPjS_S_iifi
.type _Z26host_erosiondilationfilteriiPjS_S_iifi, @function
_Z26host_erosiondilationfilteriiPjS_S_iifi:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movl %edi, %r12d
movl %esi, %r13d
movq %rdx, 8(%rsp)
movl %r9d, %ebp
movl 208(%rsp), %r14d
movss %xmm0, 20(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movq %rdx, 112(%rsp)
movq %rcx, 120(%rsp)
movq %r8, 128(%rsp)
movl $0x3e59b3d0, 100(%rsp)
movl $0x3f371759, 104(%rsp)
movl $0x3d93dd98, 108(%rsp)
movl %r9d, %r15d
imull %r14d, %r15d
movslq %r15d, %rbx
salq $2, %rbx
leaq 48(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %r12d, %r12d
jle .L67
.L36:
testl %r13d, %r13d
jle .L68
.L43:
movl $1, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %r13d, %r15d
movl %r13d, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl %r12d, %r13d
movl %r12d, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 88(%rsp), %rdx
movl $1, %ecx
movq 76(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L69
.L48:
movl $1, %r12d
.L50:
movq 112(%rsp,%r12,8), %rsi
movl $1, %ecx
movq %rbx, %rdx
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %r15d, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl %r13d, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 88(%rsp), %rdx
movl $1, %ecx
movq 76(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L70
.L49:
addq $1, %r12
cmpq $3, %r12
jne .L50
leaq 64(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %r15d, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl %r13d, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 88(%rsp), %rdx
movl $1, %ecx
movq 76(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L71
.L51:
movq 40(%rsp), %rdi
call cudaFree@PLT
leaq 56(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $2, %r12d
jmp .L54
.L67:
pxor %xmm1, %xmm1
cvtsi2sdl %r15d, %xmm1
movsd %xmm1, 24(%rsp)
pxor %xmm0, %xmm0
ucomisd %xmm1, %xmm0
ja .L62
movapd %xmm1, %xmm0
sqrtsd %xmm0, %xmm0
cvttsd2sil %xmm0, %eax
cmpl $15, %eax
jle .L39
movl $15, %r12d
testl %r13d, %r13d
jg .L43
pxor %xmm3, %xmm3
cvtsi2sdl %r15d, %xmm3
movsd %xmm3, 24(%rsp)
movl $15, %r12d
jmp .L55
.L62:
movsd 24(%rsp), %xmm0
call sqrt@PLT
cvttsd2sil %xmm0, %eax
cmpl $15, %eax
jle .L72
testl %r13d, %r13d
jle .L57
movl $15, %r12d
jmp .L43
.L68:
pxor %xmm2, %xmm2
cvtsi2sdl %r15d, %xmm2
movsd %xmm2, 24(%rsp)
pxor %xmm0, %xmm0
ucomisd %xmm2, %xmm0
ja .L44
.L55:
movsd 24(%rsp), %xmm0
sqrtsd %xmm0, %xmm0
cvttsd2sil %xmm0, %eax
movl $15, %r13d
cmpl $15, %eax
jg .L43
.L46:
cvttsd2sil %xmm0, %r13d
jmp .L43
.L69:
movl %r14d, %ecx
movl %ebp, %edx
movss .LC0(%rip), %xmm0
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z45__device_stub__Z20global_set2grayscalePfPjfiiPfPjfii
jmp .L48
.L70:
movss 100(%rsp,%r12,4), %xmm0
movl %r14d, %ecx
movl %ebp, %edx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z45__device_stub__Z20global_add2grayscalePfPjfiiPfPjfii
jmp .L49
.L71:
movl 216(%rsp), %r8d
movss 20(%rsp), %xmm0
movl %r14d, %ecx
movl %ebp, %edx
movq 64(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z47__device_stub__Z21global_find2grayscalePfPjiifiPfPjiifi
jmp .L51
.L53:
movq 112(%rsp,%r12,8), %rdi
movl $2, %ecx
movq %rbx, %rdx
movq 56(%rsp), %rsi
call cudaMemcpy@PLT
subq $1, %r12
cmpq $-1, %r12
je .L73
.L54:
cmpl $1, %r12d
jg .L52
movq 112(%rsp,%r12,8), %rsi
movl $1, %ecx
movq %rbx, %rdx
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
.L52:
movl %r15d, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl %r13d, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 88(%rsp), %rdx
movl $1, %ecx
movq 76(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L53
movl %r14d, %r8d
movl %ebp, %ecx
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z43__device_stub__Z17global_indexcolorPjS_S_iiPjS_S_ii
jmp .L53
.L73:
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L74
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
movsd 24(%rsp), %xmm0
call sqrt@PLT
jmp .L46
.L72:
movsd 24(%rsp), %xmm0
call sqrt@PLT
.L39:
cvttsd2sil %xmm0, %r12d
jmp .L36
.L57:
pxor %xmm4, %xmm4
cvtsi2sdl %r15d, %xmm4
movsd %xmm4, 24(%rsp)
movl $15, %r12d
.L44:
movsd 24(%rsp), %xmm0
call sqrt@PLT
cvttsd2sil %xmm0, %eax
cmpl $15, %eax
jle .L47
movl $15, %r13d
jmp .L43
.L74:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z26host_erosiondilationfilteriiPjS_S_iifi, .-_Z26host_erosiondilationfilteriiPjS_S_iifi
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "Running on GPU "
.LC5:
.string " ("
.LC6:
.string ")"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "Usage :\t%s filter radius2 inputfilename.bmp ouputfilename.bmp\n"
.section .rodata.str1.1
.LC8:
.string "dilation"
.LC9:
.string "Title :\t%s\n"
.LC10:
.string "Description :\t%s\n"
.LC11:
.string "Filter :\t%s\n"
.LC12:
.string "Radius2 :\t%d\n"
.LC13:
.string "Input file name :\t%s\n"
.LC14:
.string "Output file name :\t%s\n"
.LC15:
.string "rb"
.LC16:
.string "Open file error (%s)\n"
.LC17:
.string "BMP image size :\t%ld x %ld\n"
.LC18:
.string "BMP file size :\t%ld\n"
.LC19:
.string "BMP pixels offset :\t%ld\n"
.LC20:
.string "BMP bits per pixel :\t%d\n"
.LC21:
.string "BMP bytes per pixel :\t%d\n"
.LC22:
.string "BMP bytes per line :\t%d\n"
.LC24:
.string "Execution time :\t%le\n"
.LC25:
.string "wb"
.LC26:
.string "Output file size :\t%ld\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1128, %rsp
.cfi_def_cfa_offset 1184
movl %edi, 16(%rsp)
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 1112(%rsp)
xorl %eax, %eax
movq title(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, 76(%rsp)
leaq 76(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 76(%rsp)
jle .L76
movl $0, %ebp
leaq .LC4(%rip), %r15
leaq _ZSt4cout(%rip), %r13
leaq .LC5(%rip), %r14
movq %r12, 8(%rsp)
jmp .L81
.L113:
movq 1112(%rsp), %rax
subq %fs:40, %rax
jne .L111
call _ZSt16__throw_bad_castv@PLT
.L111:
call __stack_chk_fail@PLT
.L79:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L80:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %ebp
cmpl %ebp, 76(%rsp)
jle .L112
.L81:
leaq 80(%rsp), %r12
movl %ebp, %esi
movq %r12, %rdi
call cudaGetDeviceProperties_v2@PLT
movl $15, %edx
movq %r15, %rsi
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $2, %edx
movq %r14, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %r12, %rdi
call strlen@PLT
movq %rax, %rdx
movq %r12, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $1, %edx
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L113
cmpb $0, 56(%r12)
je .L79
movzbl 67(%r12), %esi
jmp .L80
.L112:
movq 8(%rsp), %r12
.L76:
cmpl $4, 16(%rsp)
jg .L82
movq (%r12), %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L82:
movq 8(%r12), %rbx
movq 16(%r12), %rdi
movl $0, %esi
call strtod@PLT
pxor %xmm1, %xmm1
cvtsd2ss %xmm0, %xmm1
movss %xmm1, 32(%rsp)
movq 24(%r12), %rbp
movq 32(%r12), %rax
movq %rax, 24(%rsp)
cmpl $5, 16(%rsp)
jg .L114
movl $0, 40(%rsp)
movl $0, 36(%rsp)
.L83:
leaq .LC8(%rip), %rsi
movq %rbx, %rdi
call strcmp@PLT
negl %eax
sbbl %eax, %eax
orl $1, %eax
movl %eax, 44(%rsp)
movq title(%rip), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq description(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 32(%rsp), %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rdx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC15(%rip), %rsi
movq %rbp, %rdi
call fopen@PLT
movq %rax, %rbx
testq %rax, %rax
je .L115
movl $2, %edx
movl $0, %esi
movq %rax, %rdi
call fseek@PLT
movq %rbx, %rdi
call ftell@PLT
movq %rax, %r14
movq %rax, 48(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %r13
movq %rax, 56(%rsp)
movl $0, %edx
movl $0, %esi
movq %rbx, %rdi
call fseek@PLT
movq %rbx, %r8
movq %r14, %rcx
movl $1, %edx
movq %r14, %rsi
movq %r13, %rdi
call __fread_chk@PLT
movq %rbx, %rdi
call fclose@PLT
movl 18(%r13), %r15d
movl 22(%r13), %edi
movl 2(%r13), %ebp
movl 10(%r13), %r12d
movzwl 28(%r13), %ebx
leal 7(%rbx), %eax
movl $8, %ecx
cltd
idivl %ecx
movl %eax, %r14d
movl %ebx, %eax
imull %r15d, %eax
addl $31, %eax
shrl $5, %eax
sall $2, %eax
movl %eax, 20(%rsp)
movl %edi, 16(%rsp)
movl %edi, %ecx
movl %r15d, %edx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %edx
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edx
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r14d, %edx
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 20(%rsp), %edx
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %ebx
addq %r13, %rbx
movl 16(%rsp), %r13d
imull %r15d, %r13d
movslq %r13d, %r13
salq $2, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r13, %rdi
call malloc@PLT
movq %rax, %r12
movq %r13, %rdi
call malloc@PLT
movq %rax, %r13
cmpl $0, 16(%rsp)
je .L116
movl $0, %r8d
movl $0, %r9d
movl $0, %edi
movl %r15d, %r10d
movl 20(%rsp), %edx
jmp .L86
.L114:
movq 40(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 40(%rsp)
movl $0, 36(%rsp)
cmpl $6, 16(%rsp)
jle .L83
movq 48(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 36(%rsp)
jmp .L83
.L115:
movq %rbp, %rcx
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq stderr(%rip), %rdi
call fflush@PLT
movl $-1, %edi
call exit@PLT
.L91:
addl $1, %edi
addl %edx, %r8d
cmpl %edi, 16(%rsp)
je .L117
.L86:
movslq %r9d, %rax
leaq (%r10,%rax), %r11
movl %r8d, %ecx
testl %r15d, %r15d
je .L91
movl %r15d, 8(%rsp)
.L88:
movl %ecx, %esi
addq %rbx, %rsi
movzbl (%rsi), %r15d
movl %r15d, 0(%rbp,%rax,4)
movzbl 1(%rsi), %r15d
movl %r15d, (%r12,%rax,4)
movzbl 2(%rsi), %esi
movl %esi, 0(%r13,%rax,4)
addq $1, %rax
addl %r14d, %ecx
cmpq %rax, %r11
jne .L88
movl 8(%rsp), %r15d
addl %r15d, %r9d
jmp .L91
.L117:
call clock@PLT
movq %rax, 8(%rsp)
movl 44(%rsp), %ecx
pushq %rcx
.cfi_def_cfa_offset 1192
movl 24(%rsp), %ecx
pushq %rcx
.cfi_def_cfa_offset 1200
movss 48(%rsp), %xmm0
movl %r15d, %r9d
movq %r13, %r8
movq %r12, %rcx
movq %rbp, %rdx
movl 52(%rsp), %esi
movl 56(%rsp), %edi
call _Z26host_erosiondilationfilteriiPjS_S_iifi
call clock@PLT
addq $16, %rsp
.cfi_def_cfa_offset 1184
movq 8(%rsp), %rcx
subq %rcx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC23(%rip), %xmm0
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %r9d
movl $0, %r10d
movl $0, %r8d
movl %r15d, %r11d
movl 20(%rsp), %edi
jmp .L92
.L96:
addl $1, %r8d
addl %edi, %r9d
cmpl %r8d, 16(%rsp)
je .L94
.L92:
movslq %r10d, %rax
leaq (%r11,%rax), %rsi
movl %r9d, %ecx
testl %r15d, %r15d
je .L96
movl %edi, 8(%rsp)
.L93:
movl %ecx, %edx
addq %rbx, %rdx
movzbl 0(%rbp,%rax,4), %edi
movb %dil, (%rdx)
movzbl (%r12,%rax,4), %edi
movb %dil, 1(%rdx)
movzbl 0(%r13,%rax,4), %edi
movb %dil, 2(%rdx)
addq $1, %rax
addl %r14d, %ecx
cmpq %rsi, %rax
jne .L93
movl 8(%rsp), %edi
addl %r15d, %r10d
jmp .L96
.L118:
movq 24(%rsp), %rcx
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq stderr(%rip), %rdi
call fflush@PLT
movl $-1, %edi
call exit@PLT
.L116:
call clock@PLT
movq %rax, %rbx
movl 44(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 1192
pushq $0
.cfi_def_cfa_offset 1200
movss 48(%rsp), %xmm0
movl %r15d, %r9d
movq %r13, %r8
movq %r12, %rcx
movq %rbp, %rdx
movl 52(%rsp), %esi
movl 56(%rsp), %edi
call _Z26host_erosiondilationfilteriiPjS_S_iifi
call clock@PLT
addq $16, %rsp
.cfi_def_cfa_offset 1184
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC23(%rip), %xmm0
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.L94:
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
leaq .LC25(%rip), %rsi
movq 24(%rsp), %rdi
call fopen@PLT
movq %rax, %rbx
testq %rax, %rax
je .L118
movq %rax, %rcx
movq 48(%rsp), %r15
movq %r15, %rdx
movl $1, %esi
movq 56(%rsp), %r14
movq %r14, %rdi
call fwrite@PLT
movq %r15, %rdx
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r14, %rdi
call free@PLT
movq %rbx, %rdi
call fclose@PLT
call cudaDeviceReset@PLT
movl $0, %edi
call exit@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC27:
.string "_Z17global_indexcolorPjS_S_ii"
.section .rodata.str1.8
.align 8
.LC28:
.string "_Z21global_find2grayscalePfPjiifi"
.align 8
.LC29:
.string "_Z20global_add2grayscalePfPjfii"
.align 8
.LC30:
.string "_Z20global_set2grayscalePfPjfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3704:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC27(%rip), %rdx
movq %rdx, %rcx
leaq _Z17global_indexcolorPjS_S_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC28(%rip), %rdx
movq %rdx, %rcx
leaq _Z21global_find2grayscalePfPjiifi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC29(%rip), %rdx
movq %rdx, %rcx
leaq _Z20global_add2grayscalePfPjfii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC30(%rip), %rdx
movq %rdx, %rcx
leaq _Z20global_set2grayscalePfPjfii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3704:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl description
.section .rodata.str1.1
.LC31:
.string "Erosion and Dilation filter"
.section .data.rel.local,"aw"
.align 8
.type description, @object
.size description, 8
description:
.quad .LC31
.globl title
.align 8
.type title, @object
.size title, 8
title:
.quad .LC31
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1046066128
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC23:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | char *title = "Erosion and Dilation filter";
char *description = "Erosion and Dilation filter";
/*
Фильтр «минимум» – также известный как фильтр эрозии, заменяет значение минимальным в окрестности.
Фильтр «максимум» – также известный как фильтр расширения, заменяет значение максимальным в окрестности.
*/
#include <iostream>
#include <cstdio>
#include <cstdlib>
#include <assert.h>
#include <time.h>
#include <cuda.h>
#include <cuda_runtime.h>
#ifndef max
#define max( a, b ) ( ((a) > (b)) ? (a) : (b) )
#endif
#ifndef min
#define min( a, b ) ( ((a) < (b)) ? (a) : (b) )
#endif
#ifndef uint8_t
typedef unsigned char uint8_t;
#endif
#ifndef uint16_t
typedef unsigned short uint16_t;
#endif
#ifndef uint32_t
typedef unsigned int uint32_t;
#endif
// http://en.wikipedia.org/wiki/BMP_file_format
#define BMPMAGIC 0x00
#define BMPFILESIZE 0x02
#define BMPOFFSET 0x0A
#define BMPDIBSISE 0x0E
#define BMPWIDTH 0x12
#define BMPHEIGHT 0x16
#define BMPBITSPERPIXEL 0x1C
typedef struct {
uint8_t magic[2]; /* the magic number used to identify the BMP file:
0x42 0x4D (Hex code points for B and M).
The following entries are possible:
BM - Windows 3.1x, 95, NT, ... etc
BA - OS/2 Bitmap Array
CI - OS/2 Color Icon
CP - OS/2 Color Pointer
IC - OS/2 Icon
PT - OS/2 Pointer. */
uint32_t filesz; /* the size of the BMP file in bytes */
uint16_t creator1; /* reserved. */
uint16_t creator2; /* reserved. */
uint32_t offset; /* the offset, i.e. starting address,
of the byte where the bitmap data can be found. */
} bmp_header_t;
typedef struct {
uint32_t header_sz; /* the size of this header (40 bytes) */
uint32_t width; /* the bitmap width in pixels */
uint32_t height; /* the bitmap height in pixels */
uint16_t nplanes; /* the number of color planes being used.
Must be set to 1. */
uint16_t depth; /* the number of bits per pixel,
which is the color depth of the image.
Typical values are 1, 4, 8, 16, 24 and 32. */
uint32_t compress_type; /* the compression method being used.
See also bmp_compression_method_t. */
uint32_t bmp_bytesz; /* the image size. This is the size of the raw bitmap
data (see below), and should not be confused
with the file size. */
uint32_t hres; /* the horizontal resolution of the image.
(pixel per meter) */
uint32_t vres; /* the vertical resolution of the image.
(pixel per meter) */
uint32_t ncolors; /* the number of colors in the color palette,
or 0 to default to 2<sup><i>n</i></sup>. */
uint32_t nimpcolors; /* the number of important colors used,
or 0 when every color is important;
generally ignored. */
} bmp_dib_v3_header_t;
__global__ void global_set2grayscale(
float *grayscale,
unsigned int *input,
float weight,
int width,
int height)
{
for (int id = blockDim.x*blockIdx.x + threadIdx.x;
id < width*height;
id += blockDim.x*gridDim.x) {
grayscale[id] += weight*(float)(input[id]&0xFF);
}
}
__global__ void global_add2grayscale(
float *grayscale,
unsigned int *input,
float weight,
int width,
int height)
{
for (int id = blockDim.x*blockIdx.x + threadIdx.x;
id < width*height;
id += blockDim.x*gridDim.x) {
grayscale[id] += weight*(float)(input[id]&0xFF);
}
}
// Поиск индекса элемента с наилучшим значением интенсивности
__global__ void global_find2grayscale(
float *grayscale,
unsigned int *index,
int width,
int height,
float radius2,
int mode)
{
int radius = 1;
while((float)radius*radius<radius2) radius++; // поскольку числа маленькие, то быстрее перебором
if(mode>0){ // если расширение
for (int id = blockDim.x*blockIdx.x + threadIdx.x;
id < width*height;
id += blockDim.x*gridDim.x) {
int x=id%width;
int y=id/width;
int currentId = id;
// перебираем пиксели в окружности
for(int i=max(0,x-radius);i<=min(width,x+radius);i++){
for(int j=max(0,y-radius);j<=min(height,y+radius);j++){
if((float)((i-x)*(i-x)+(j-y)*(j-y))<=radius2) {
int itemId = j*width+i;
if(grayscale[itemId]>grayscale[currentId]) currentId=itemId;
}
}
}
index[id] = currentId;
}
} else if(mode<0){ // если эрозия
for (int id = blockDim.x*blockIdx.x + threadIdx.x;
id < width*height;
id += blockDim.x*gridDim.x) {
int x=id%width;
int y=id/width;
int currentId = id;
// перебираем пиксели в окружности
for(int i=max(0,x-radius);i<=min(width,x+radius);i++){
for(int j=max(0,y-radius);j<=min(height,y+radius);j++){
if((float)((i-x)*(i-x)+(j-y)*(j-y))<=radius2) {
int itemId = j*width+i;
if(grayscale[itemId]<grayscale[currentId]) currentId=itemId;
}
}
}
index[id] = currentId;
}
}else {
for (int id = blockDim.x*blockIdx.x + threadIdx.x;
id < width*height;
id += blockDim.x*gridDim.x) {
index[id] = id;
}
}
}
// Получение цвета из таблицы по индексу
__global__ void global_indexcolor(
unsigned int *input,
unsigned int *output,
unsigned int *index,
int width,
int height)
{
for (int id = blockDim.x*blockIdx.x + threadIdx.x;
id < width*height;
id += blockDim.x*gridDim.x) {
output[id] = input[index[id]];
}
}
__host__ void host_erosiondilationfilter(
int gridSize,
int blockSize,
unsigned int *r,
unsigned int *g,
unsigned int *b,
int width,
int height,
float radius2,
int mode)
{
// формула для конвертации RGB в интенсивность
// http://en.wikipedia.org/wiki/Grayscale
// Y = 0.2126 * R + 0.7152 * G + 0.0722 * B
unsigned int *channel[3] = { r,g,b };
float weight[3] = {0.2126f, 0.7152f, 0.0722f};
// channel - массив данных
// width - ширина
// height - высота
cudaError_t err;
float *device_grayscale;
unsigned int *device_input;
unsigned int *device_output;
unsigned int *device_index;
err = cudaMalloc((void**)&device_input, width*height*sizeof(unsigned int));
err = cudaMalloc((void**)&device_grayscale, width*height*sizeof(float));
int blocks = (gridSize > 0)? gridSize : min(15, (int)sqrt(width*height));
int threads = (blockSize > 0)? blockSize : min(15, (int)sqrt(width*height));
// Шаг 1. Рассчитываем монохромное изображение
cudaMemcpy(device_input, channel[0], width*height*sizeof(unsigned int), cudaMemcpyHostToDevice);
global_set2grayscale <<< blocks, threads >>>(device_grayscale, device_input, weight[0], width, height);
for(int j=1;j<3;j++){
cudaMemcpy(device_input, channel[j], width*height*sizeof(unsigned int), cudaMemcpyHostToDevice);
global_add2grayscale <<< blocks, threads >>>(device_grayscale, device_input, weight[j], width, height);
}
err = cudaMalloc((void**)&device_index, width*height*sizeof(unsigned int));
// Шаг 2. Находим индексы (то есть находим требуемую замену пикселей)
global_find2grayscale <<< blocks, threads >>>(device_grayscale, device_index, width, height, radius2, mode);
cudaFree((void*)device_grayscale);
err = cudaMalloc((void**)&device_output, width*height*sizeof(unsigned int));
// Шаг 3. Заменяем пиксели согласно ранее полученной подстановке
for(int j=3;j-->0;){
// Перевый раз копировать в видео память не надо, поскольку уже копировали при подсчёте монохромного изображения
if(j<2) cudaMemcpy(device_input, channel[j], width*height*sizeof(unsigned int), cudaMemcpyHostToDevice);
global_indexcolor <<< blocks, threads >>>(device_input, device_output, device_index, width, height);
cudaMemcpy(channel[j], device_output, width*height*sizeof(unsigned int), cudaMemcpyDeviceToHost);
}
cudaFree((void*)device_index);
cudaFree((void*)device_input);
cudaFree((void*)device_output);
err = err;
}
int main(int argc, char* argv[])
{
int i, j;
std::cout << title << std::endl;
// Find/set the device.
int device_count = 0;
cudaGetDeviceCount(&device_count);
for (i = 0; i < device_count; ++i)
{
cudaDeviceProp properties;
cudaGetDeviceProperties(&properties, i);
std::cout << "Running on GPU " << i << " (" << properties.name << ")" << std::endl;
}
if (argc < 5){
printf("Usage :\t%s filter radius2 inputfilename.bmp ouputfilename.bmp\n", argv[0]);
exit(-1);
}
// Получаем параметры - имена файлов
char *filter = argv[1];
float radius2 = atof(argv[2]);
char *inputFileName = argv[3];
char *outputFileName = argv[4];
int gridSize = (argc>5)?atoi(argv[5]):0;
int blockSize = (argc>6)?atoi(argv[6]):0;
int mode = (strcmp(filter,"dilation")==0)?1:-1;
printf("Title :\t%s\n", title);
printf("Description :\t%s\n", description);
printf("Filter :\t%s\n", filter);
printf("Radius2 :\t%d\n", radius2);
printf("Input file name :\t%s\n", inputFileName);
printf("Output file name :\t%s\n", outputFileName);
FILE *file = fopen(inputFileName, "rb");
if (!file) {
fprintf(stderr, "Open file error (%s)\n", inputFileName);
fflush(stderr);
exit(-1);
}
fseek(file, 0L, SEEK_END);
long size = ftell(file);
unsigned char *buffer = (unsigned char *)malloc((size_t)size);
fseek(file, 0L, SEEK_SET);
fread((void*)buffer, (size_t)1, (size_t)size, file);
fclose(file);
uint32_t width = *(uint32_t *)&buffer[BMPWIDTH];
uint32_t height = *(uint32_t *)&buffer[BMPHEIGHT];
uint32_t file_size = *(uint32_t *)&buffer[BMPFILESIZE];
uint32_t offset = *(uint32_t *)&buffer[BMPOFFSET];
uint16_t bits_per_pixel = *(uint16_t *)&buffer[BMPBITSPERPIXEL];
uint16_t bytes_per_pixel = ((int)((bits_per_pixel+7)/8));
uint32_t bytes_per_line = ((int)((bits_per_pixel * width+31)/32))*4; // http://en.wikipedia.org/wiki/BMP_file_format
printf("BMP image size :\t%ld x %ld\n", width, height);
printf("BMP file size :\t%ld\n", file_size);
printf("BMP pixels offset :\t%ld\n", offset);
printf("BMP bits per pixel :\t%d\n", bits_per_pixel);
printf("BMP bytes per pixel :\t%d\n", bytes_per_pixel);
printf("BMP bytes per line :\t%d\n", bytes_per_line);
uint8_t *pixels =(uint8_t *)&buffer[offset];
uint8_t *pixel;
uint32_t x, y;
/* выделение памяти под байтовые цветовые каналы */
int count = width*height;
unsigned int* channel[3];
for (j = 0; j < 3; j++)
channel[j] = (unsigned int*)malloc(count*sizeof(unsigned int));
int pos = 0;
for (y = 0; y < height; y++) {
for (x = 0; x < width; x++) {
pixel = &pixels[y*bytes_per_line+x*bytes_per_pixel];
channel[0][pos] = (unsigned int)pixel[0];
channel[1][pos] = (unsigned int)pixel[1];
channel[2][pos] = (unsigned int)pixel[2];
pos++;
}
}
clock_t t1, t2;
t1 = clock();
host_erosiondilationfilter(gridSize, blockSize,
channel[0], channel[1], channel[2],
(int)width, (int)height,
radius2, mode);
t2 = clock();
double seconds = ((double)(t2-t1))/CLOCKS_PER_SEC;
printf("Execution time :\t%le\n", seconds);
pos = 0;
for (y = 0; y < height; y++) {
for (x = 0; x < width; x++) {
pixel = &pixels[y*bytes_per_line+x*bytes_per_pixel];
pixel[0] = (uint8_t)channel[0][pos];
pixel[1] = (uint8_t)channel[1][pos];
pixel[2] = (uint8_t)channel[2][pos];
pos++;
}
}
/* высвобождаем массивы */
for (j = 0; j < 3; j++)
free(channel[j]);
/* выводим результаты */
file = fopen(outputFileName, "wb");
if (!file) {
fprintf(stderr, "Open file error (%s)\n", outputFileName);
fflush(stderr);
exit(-1);
}
fwrite((void*)buffer, (size_t)1, (size_t)size, file);
printf("Output file size :\t%ld\n", size);
free(buffer);
fclose(file);
cudaDeviceReset();
exit(0);
} | char *title = "Erosion and Dilation filter";
char *description = "Erosion and Dilation filter";
/*
Фильтр «минимум» – также известный как фильтр эрозии, заменяет значение минимальным в окрестности.
Фильтр «максимум» – также известный как фильтр расширения, заменяет значение максимальным в окрестности.
*/
#include <iostream>
#include <cstdio>
#include <cstdlib>
#include <assert.h>
#include <time.h>
#include <hip/hip_runtime.h>
#ifndef max
#define max( a, b ) ( ((a) > (b)) ? (a) : (b) )
#endif
#ifndef min
#define min( a, b ) ( ((a) < (b)) ? (a) : (b) )
#endif
#ifndef uint8_t
typedef unsigned char uint8_t;
#endif
#ifndef uint16_t
typedef unsigned short uint16_t;
#endif
#ifndef uint32_t
typedef unsigned int uint32_t;
#endif
// http://en.wikipedia.org/wiki/BMP_file_format
#define BMPMAGIC 0x00
#define BMPFILESIZE 0x02
#define BMPOFFSET 0x0A
#define BMPDIBSISE 0x0E
#define BMPWIDTH 0x12
#define BMPHEIGHT 0x16
#define BMPBITSPERPIXEL 0x1C
typedef struct {
uint8_t magic[2]; /* the magic number used to identify the BMP file:
0x42 0x4D (Hex code points for B and M).
The following entries are possible:
BM - Windows 3.1x, 95, NT, ... etc
BA - OS/2 Bitmap Array
CI - OS/2 Color Icon
CP - OS/2 Color Pointer
IC - OS/2 Icon
PT - OS/2 Pointer. */
uint32_t filesz; /* the size of the BMP file in bytes */
uint16_t creator1; /* reserved. */
uint16_t creator2; /* reserved. */
uint32_t offset; /* the offset, i.e. starting address,
of the byte where the bitmap data can be found. */
} bmp_header_t;
typedef struct {
uint32_t header_sz; /* the size of this header (40 bytes) */
uint32_t width; /* the bitmap width in pixels */
uint32_t height; /* the bitmap height in pixels */
uint16_t nplanes; /* the number of color planes being used.
Must be set to 1. */
uint16_t depth; /* the number of bits per pixel,
which is the color depth of the image.
Typical values are 1, 4, 8, 16, 24 and 32. */
uint32_t compress_type; /* the compression method being used.
See also bmp_compression_method_t. */
uint32_t bmp_bytesz; /* the image size. This is the size of the raw bitmap
data (see below), and should not be confused
with the file size. */
uint32_t hres; /* the horizontal resolution of the image.
(pixel per meter) */
uint32_t vres; /* the vertical resolution of the image.
(pixel per meter) */
uint32_t ncolors; /* the number of colors in the color palette,
or 0 to default to 2<sup><i>n</i></sup>. */
uint32_t nimpcolors; /* the number of important colors used,
or 0 when every color is important;
generally ignored. */
} bmp_dib_v3_header_t;
__global__ void global_set2grayscale(
float *grayscale,
unsigned int *input,
float weight,
int width,
int height)
{
for (int id = blockDim.x*blockIdx.x + threadIdx.x;
id < width*height;
id += blockDim.x*gridDim.x) {
grayscale[id] += weight*(float)(input[id]&0xFF);
}
}
__global__ void global_add2grayscale(
float *grayscale,
unsigned int *input,
float weight,
int width,
int height)
{
for (int id = blockDim.x*blockIdx.x + threadIdx.x;
id < width*height;
id += blockDim.x*gridDim.x) {
grayscale[id] += weight*(float)(input[id]&0xFF);
}
}
// Поиск индекса элемента с наилучшим значением интенсивности
__global__ void global_find2grayscale(
float *grayscale,
unsigned int *index,
int width,
int height,
float radius2,
int mode)
{
int radius = 1;
while((float)radius*radius<radius2) radius++; // поскольку числа маленькие, то быстрее перебором
if(mode>0){ // если расширение
for (int id = blockDim.x*blockIdx.x + threadIdx.x;
id < width*height;
id += blockDim.x*gridDim.x) {
int x=id%width;
int y=id/width;
int currentId = id;
// перебираем пиксели в окружности
for(int i=max(0,x-radius);i<=min(width,x+radius);i++){
for(int j=max(0,y-radius);j<=min(height,y+radius);j++){
if((float)((i-x)*(i-x)+(j-y)*(j-y))<=radius2) {
int itemId = j*width+i;
if(grayscale[itemId]>grayscale[currentId]) currentId=itemId;
}
}
}
index[id] = currentId;
}
} else if(mode<0){ // если эрозия
for (int id = blockDim.x*blockIdx.x + threadIdx.x;
id < width*height;
id += blockDim.x*gridDim.x) {
int x=id%width;
int y=id/width;
int currentId = id;
// перебираем пиксели в окружности
for(int i=max(0,x-radius);i<=min(width,x+radius);i++){
for(int j=max(0,y-radius);j<=min(height,y+radius);j++){
if((float)((i-x)*(i-x)+(j-y)*(j-y))<=radius2) {
int itemId = j*width+i;
if(grayscale[itemId]<grayscale[currentId]) currentId=itemId;
}
}
}
index[id] = currentId;
}
}else {
for (int id = blockDim.x*blockIdx.x + threadIdx.x;
id < width*height;
id += blockDim.x*gridDim.x) {
index[id] = id;
}
}
}
// Получение цвета из таблицы по индексу
__global__ void global_indexcolor(
unsigned int *input,
unsigned int *output,
unsigned int *index,
int width,
int height)
{
for (int id = blockDim.x*blockIdx.x + threadIdx.x;
id < width*height;
id += blockDim.x*gridDim.x) {
output[id] = input[index[id]];
}
}
__host__ void host_erosiondilationfilter(
int gridSize,
int blockSize,
unsigned int *r,
unsigned int *g,
unsigned int *b,
int width,
int height,
float radius2,
int mode)
{
// формула для конвертации RGB в интенсивность
// http://en.wikipedia.org/wiki/Grayscale
// Y = 0.2126 * R + 0.7152 * G + 0.0722 * B
unsigned int *channel[3] = { r,g,b };
float weight[3] = {0.2126f, 0.7152f, 0.0722f};
// channel - массив данных
// width - ширина
// height - высота
hipError_t err;
float *device_grayscale;
unsigned int *device_input;
unsigned int *device_output;
unsigned int *device_index;
err = hipMalloc((void**)&device_input, width*height*sizeof(unsigned int));
err = hipMalloc((void**)&device_grayscale, width*height*sizeof(float));
int blocks = (gridSize > 0)? gridSize : min(15, (int)sqrt(width*height));
int threads = (blockSize > 0)? blockSize : min(15, (int)sqrt(width*height));
// Шаг 1. Рассчитываем монохромное изображение
hipMemcpy(device_input, channel[0], width*height*sizeof(unsigned int), hipMemcpyHostToDevice);
global_set2grayscale <<< blocks, threads >>>(device_grayscale, device_input, weight[0], width, height);
for(int j=1;j<3;j++){
hipMemcpy(device_input, channel[j], width*height*sizeof(unsigned int), hipMemcpyHostToDevice);
global_add2grayscale <<< blocks, threads >>>(device_grayscale, device_input, weight[j], width, height);
}
err = hipMalloc((void**)&device_index, width*height*sizeof(unsigned int));
// Шаг 2. Находим индексы (то есть находим требуемую замену пикселей)
global_find2grayscale <<< blocks, threads >>>(device_grayscale, device_index, width, height, radius2, mode);
hipFree((void*)device_grayscale);
err = hipMalloc((void**)&device_output, width*height*sizeof(unsigned int));
// Шаг 3. Заменяем пиксели согласно ранее полученной подстановке
for(int j=3;j-->0;){
// Перевый раз копировать в видео память не надо, поскольку уже копировали при подсчёте монохромного изображения
if(j<2) hipMemcpy(device_input, channel[j], width*height*sizeof(unsigned int), hipMemcpyHostToDevice);
global_indexcolor <<< blocks, threads >>>(device_input, device_output, device_index, width, height);
hipMemcpy(channel[j], device_output, width*height*sizeof(unsigned int), hipMemcpyDeviceToHost);
}
hipFree((void*)device_index);
hipFree((void*)device_input);
hipFree((void*)device_output);
err = err;
}
int main(int argc, char* argv[])
{
int i, j;
std::cout << title << std::endl;
// Find/set the device.
int device_count = 0;
hipGetDeviceCount(&device_count);
for (i = 0; i < device_count; ++i)
{
hipDeviceProp_t properties;
hipGetDeviceProperties(&properties, i);
std::cout << "Running on GPU " << i << " (" << properties.name << ")" << std::endl;
}
if (argc < 5){
printf("Usage :\t%s filter radius2 inputfilename.bmp ouputfilename.bmp\n", argv[0]);
exit(-1);
}
// Получаем параметры - имена файлов
char *filter = argv[1];
float radius2 = atof(argv[2]);
char *inputFileName = argv[3];
char *outputFileName = argv[4];
int gridSize = (argc>5)?atoi(argv[5]):0;
int blockSize = (argc>6)?atoi(argv[6]):0;
int mode = (strcmp(filter,"dilation")==0)?1:-1;
printf("Title :\t%s\n", title);
printf("Description :\t%s\n", description);
printf("Filter :\t%s\n", filter);
printf("Radius2 :\t%d\n", radius2);
printf("Input file name :\t%s\n", inputFileName);
printf("Output file name :\t%s\n", outputFileName);
FILE *file = fopen(inputFileName, "rb");
if (!file) {
fprintf(stderr, "Open file error (%s)\n", inputFileName);
fflush(stderr);
exit(-1);
}
fseek(file, 0L, SEEK_END);
long size = ftell(file);
unsigned char *buffer = (unsigned char *)malloc((size_t)size);
fseek(file, 0L, SEEK_SET);
fread((void*)buffer, (size_t)1, (size_t)size, file);
fclose(file);
uint32_t width = *(uint32_t *)&buffer[BMPWIDTH];
uint32_t height = *(uint32_t *)&buffer[BMPHEIGHT];
uint32_t file_size = *(uint32_t *)&buffer[BMPFILESIZE];
uint32_t offset = *(uint32_t *)&buffer[BMPOFFSET];
uint16_t bits_per_pixel = *(uint16_t *)&buffer[BMPBITSPERPIXEL];
uint16_t bytes_per_pixel = ((int)((bits_per_pixel+7)/8));
uint32_t bytes_per_line = ((int)((bits_per_pixel * width+31)/32))*4; // http://en.wikipedia.org/wiki/BMP_file_format
printf("BMP image size :\t%ld x %ld\n", width, height);
printf("BMP file size :\t%ld\n", file_size);
printf("BMP pixels offset :\t%ld\n", offset);
printf("BMP bits per pixel :\t%d\n", bits_per_pixel);
printf("BMP bytes per pixel :\t%d\n", bytes_per_pixel);
printf("BMP bytes per line :\t%d\n", bytes_per_line);
uint8_t *pixels =(uint8_t *)&buffer[offset];
uint8_t *pixel;
uint32_t x, y;
/* выделение памяти под байтовые цветовые каналы */
int count = width*height;
unsigned int* channel[3];
for (j = 0; j < 3; j++)
channel[j] = (unsigned int*)malloc(count*sizeof(unsigned int));
int pos = 0;
for (y = 0; y < height; y++) {
for (x = 0; x < width; x++) {
pixel = &pixels[y*bytes_per_line+x*bytes_per_pixel];
channel[0][pos] = (unsigned int)pixel[0];
channel[1][pos] = (unsigned int)pixel[1];
channel[2][pos] = (unsigned int)pixel[2];
pos++;
}
}
clock_t t1, t2;
t1 = clock();
host_erosiondilationfilter(gridSize, blockSize,
channel[0], channel[1], channel[2],
(int)width, (int)height,
radius2, mode);
t2 = clock();
double seconds = ((double)(t2-t1))/CLOCKS_PER_SEC;
printf("Execution time :\t%le\n", seconds);
pos = 0;
for (y = 0; y < height; y++) {
for (x = 0; x < width; x++) {
pixel = &pixels[y*bytes_per_line+x*bytes_per_pixel];
pixel[0] = (uint8_t)channel[0][pos];
pixel[1] = (uint8_t)channel[1][pos];
pixel[2] = (uint8_t)channel[2][pos];
pos++;
}
}
/* высвобождаем массивы */
for (j = 0; j < 3; j++)
free(channel[j]);
/* выводим результаты */
file = fopen(outputFileName, "wb");
if (!file) {
fprintf(stderr, "Open file error (%s)\n", outputFileName);
fflush(stderr);
exit(-1);
}
fwrite((void*)buffer, (size_t)1, (size_t)size, file);
printf("Output file size :\t%ld\n", size);
free(buffer);
fclose(file);
hipDeviceReset();
exit(0);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | char *title = "Erosion and Dilation filter";
char *description = "Erosion and Dilation filter";
/*
Фильтр «минимум» – также известный как фильтр эрозии, заменяет значение минимальным в окрестности.
Фильтр «максимум» – также известный как фильтр расширения, заменяет значение максимальным в окрестности.
*/
#include <iostream>
#include <cstdio>
#include <cstdlib>
#include <assert.h>
#include <time.h>
#include <hip/hip_runtime.h>
#ifndef max
#define max( a, b ) ( ((a) > (b)) ? (a) : (b) )
#endif
#ifndef min
#define min( a, b ) ( ((a) < (b)) ? (a) : (b) )
#endif
#ifndef uint8_t
typedef unsigned char uint8_t;
#endif
#ifndef uint16_t
typedef unsigned short uint16_t;
#endif
#ifndef uint32_t
typedef unsigned int uint32_t;
#endif
// http://en.wikipedia.org/wiki/BMP_file_format
#define BMPMAGIC 0x00
#define BMPFILESIZE 0x02
#define BMPOFFSET 0x0A
#define BMPDIBSISE 0x0E
#define BMPWIDTH 0x12
#define BMPHEIGHT 0x16
#define BMPBITSPERPIXEL 0x1C
typedef struct {
uint8_t magic[2]; /* the magic number used to identify the BMP file:
0x42 0x4D (Hex code points for B and M).
The following entries are possible:
BM - Windows 3.1x, 95, NT, ... etc
BA - OS/2 Bitmap Array
CI - OS/2 Color Icon
CP - OS/2 Color Pointer
IC - OS/2 Icon
PT - OS/2 Pointer. */
uint32_t filesz; /* the size of the BMP file in bytes */
uint16_t creator1; /* reserved. */
uint16_t creator2; /* reserved. */
uint32_t offset; /* the offset, i.e. starting address,
of the byte where the bitmap data can be found. */
} bmp_header_t;
typedef struct {
uint32_t header_sz; /* the size of this header (40 bytes) */
uint32_t width; /* the bitmap width in pixels */
uint32_t height; /* the bitmap height in pixels */
uint16_t nplanes; /* the number of color planes being used.
Must be set to 1. */
uint16_t depth; /* the number of bits per pixel,
which is the color depth of the image.
Typical values are 1, 4, 8, 16, 24 and 32. */
uint32_t compress_type; /* the compression method being used.
See also bmp_compression_method_t. */
uint32_t bmp_bytesz; /* the image size. This is the size of the raw bitmap
data (see below), and should not be confused
with the file size. */
uint32_t hres; /* the horizontal resolution of the image.
(pixel per meter) */
uint32_t vres; /* the vertical resolution of the image.
(pixel per meter) */
uint32_t ncolors; /* the number of colors in the color palette,
or 0 to default to 2<sup><i>n</i></sup>. */
uint32_t nimpcolors; /* the number of important colors used,
or 0 when every color is important;
generally ignored. */
} bmp_dib_v3_header_t;
__global__ void global_set2grayscale(
float *grayscale,
unsigned int *input,
float weight,
int width,
int height)
{
for (int id = blockDim.x*blockIdx.x + threadIdx.x;
id < width*height;
id += blockDim.x*gridDim.x) {
grayscale[id] += weight*(float)(input[id]&0xFF);
}
}
__global__ void global_add2grayscale(
float *grayscale,
unsigned int *input,
float weight,
int width,
int height)
{
for (int id = blockDim.x*blockIdx.x + threadIdx.x;
id < width*height;
id += blockDim.x*gridDim.x) {
grayscale[id] += weight*(float)(input[id]&0xFF);
}
}
// Поиск индекса элемента с наилучшим значением интенсивности
__global__ void global_find2grayscale(
float *grayscale,
unsigned int *index,
int width,
int height,
float radius2,
int mode)
{
int radius = 1;
while((float)radius*radius<radius2) radius++; // поскольку числа маленькие, то быстрее перебором
if(mode>0){ // если расширение
for (int id = blockDim.x*blockIdx.x + threadIdx.x;
id < width*height;
id += blockDim.x*gridDim.x) {
int x=id%width;
int y=id/width;
int currentId = id;
// перебираем пиксели в окружности
for(int i=max(0,x-radius);i<=min(width,x+radius);i++){
for(int j=max(0,y-radius);j<=min(height,y+radius);j++){
if((float)((i-x)*(i-x)+(j-y)*(j-y))<=radius2) {
int itemId = j*width+i;
if(grayscale[itemId]>grayscale[currentId]) currentId=itemId;
}
}
}
index[id] = currentId;
}
} else if(mode<0){ // если эрозия
for (int id = blockDim.x*blockIdx.x + threadIdx.x;
id < width*height;
id += blockDim.x*gridDim.x) {
int x=id%width;
int y=id/width;
int currentId = id;
// перебираем пиксели в окружности
for(int i=max(0,x-radius);i<=min(width,x+radius);i++){
for(int j=max(0,y-radius);j<=min(height,y+radius);j++){
if((float)((i-x)*(i-x)+(j-y)*(j-y))<=radius2) {
int itemId = j*width+i;
if(grayscale[itemId]<grayscale[currentId]) currentId=itemId;
}
}
}
index[id] = currentId;
}
}else {
for (int id = blockDim.x*blockIdx.x + threadIdx.x;
id < width*height;
id += blockDim.x*gridDim.x) {
index[id] = id;
}
}
}
// Получение цвета из таблицы по индексу
__global__ void global_indexcolor(
unsigned int *input,
unsigned int *output,
unsigned int *index,
int width,
int height)
{
for (int id = blockDim.x*blockIdx.x + threadIdx.x;
id < width*height;
id += blockDim.x*gridDim.x) {
output[id] = input[index[id]];
}
}
__host__ void host_erosiondilationfilter(
int gridSize,
int blockSize,
unsigned int *r,
unsigned int *g,
unsigned int *b,
int width,
int height,
float radius2,
int mode)
{
// формула для конвертации RGB в интенсивность
// http://en.wikipedia.org/wiki/Grayscale
// Y = 0.2126 * R + 0.7152 * G + 0.0722 * B
unsigned int *channel[3] = { r,g,b };
float weight[3] = {0.2126f, 0.7152f, 0.0722f};
// channel - массив данных
// width - ширина
// height - высота
hipError_t err;
float *device_grayscale;
unsigned int *device_input;
unsigned int *device_output;
unsigned int *device_index;
err = hipMalloc((void**)&device_input, width*height*sizeof(unsigned int));
err = hipMalloc((void**)&device_grayscale, width*height*sizeof(float));
int blocks = (gridSize > 0)? gridSize : min(15, (int)sqrt(width*height));
int threads = (blockSize > 0)? blockSize : min(15, (int)sqrt(width*height));
// Шаг 1. Рассчитываем монохромное изображение
hipMemcpy(device_input, channel[0], width*height*sizeof(unsigned int), hipMemcpyHostToDevice);
global_set2grayscale <<< blocks, threads >>>(device_grayscale, device_input, weight[0], width, height);
for(int j=1;j<3;j++){
hipMemcpy(device_input, channel[j], width*height*sizeof(unsigned int), hipMemcpyHostToDevice);
global_add2grayscale <<< blocks, threads >>>(device_grayscale, device_input, weight[j], width, height);
}
err = hipMalloc((void**)&device_index, width*height*sizeof(unsigned int));
// Шаг 2. Находим индексы (то есть находим требуемую замену пикселей)
global_find2grayscale <<< blocks, threads >>>(device_grayscale, device_index, width, height, radius2, mode);
hipFree((void*)device_grayscale);
err = hipMalloc((void**)&device_output, width*height*sizeof(unsigned int));
// Шаг 3. Заменяем пиксели согласно ранее полученной подстановке
for(int j=3;j-->0;){
// Перевый раз копировать в видео память не надо, поскольку уже копировали при подсчёте монохромного изображения
if(j<2) hipMemcpy(device_input, channel[j], width*height*sizeof(unsigned int), hipMemcpyHostToDevice);
global_indexcolor <<< blocks, threads >>>(device_input, device_output, device_index, width, height);
hipMemcpy(channel[j], device_output, width*height*sizeof(unsigned int), hipMemcpyDeviceToHost);
}
hipFree((void*)device_index);
hipFree((void*)device_input);
hipFree((void*)device_output);
err = err;
}
int main(int argc, char* argv[])
{
int i, j;
std::cout << title << std::endl;
// Find/set the device.
int device_count = 0;
hipGetDeviceCount(&device_count);
for (i = 0; i < device_count; ++i)
{
hipDeviceProp_t properties;
hipGetDeviceProperties(&properties, i);
std::cout << "Running on GPU " << i << " (" << properties.name << ")" << std::endl;
}
if (argc < 5){
printf("Usage :\t%s filter radius2 inputfilename.bmp ouputfilename.bmp\n", argv[0]);
exit(-1);
}
// Получаем параметры - имена файлов
char *filter = argv[1];
float radius2 = atof(argv[2]);
char *inputFileName = argv[3];
char *outputFileName = argv[4];
int gridSize = (argc>5)?atoi(argv[5]):0;
int blockSize = (argc>6)?atoi(argv[6]):0;
int mode = (strcmp(filter,"dilation")==0)?1:-1;
printf("Title :\t%s\n", title);
printf("Description :\t%s\n", description);
printf("Filter :\t%s\n", filter);
printf("Radius2 :\t%d\n", radius2);
printf("Input file name :\t%s\n", inputFileName);
printf("Output file name :\t%s\n", outputFileName);
FILE *file = fopen(inputFileName, "rb");
if (!file) {
fprintf(stderr, "Open file error (%s)\n", inputFileName);
fflush(stderr);
exit(-1);
}
fseek(file, 0L, SEEK_END);
long size = ftell(file);
unsigned char *buffer = (unsigned char *)malloc((size_t)size);
fseek(file, 0L, SEEK_SET);
fread((void*)buffer, (size_t)1, (size_t)size, file);
fclose(file);
uint32_t width = *(uint32_t *)&buffer[BMPWIDTH];
uint32_t height = *(uint32_t *)&buffer[BMPHEIGHT];
uint32_t file_size = *(uint32_t *)&buffer[BMPFILESIZE];
uint32_t offset = *(uint32_t *)&buffer[BMPOFFSET];
uint16_t bits_per_pixel = *(uint16_t *)&buffer[BMPBITSPERPIXEL];
uint16_t bytes_per_pixel = ((int)((bits_per_pixel+7)/8));
uint32_t bytes_per_line = ((int)((bits_per_pixel * width+31)/32))*4; // http://en.wikipedia.org/wiki/BMP_file_format
printf("BMP image size :\t%ld x %ld\n", width, height);
printf("BMP file size :\t%ld\n", file_size);
printf("BMP pixels offset :\t%ld\n", offset);
printf("BMP bits per pixel :\t%d\n", bits_per_pixel);
printf("BMP bytes per pixel :\t%d\n", bytes_per_pixel);
printf("BMP bytes per line :\t%d\n", bytes_per_line);
uint8_t *pixels =(uint8_t *)&buffer[offset];
uint8_t *pixel;
uint32_t x, y;
/* выделение памяти под байтовые цветовые каналы */
int count = width*height;
unsigned int* channel[3];
for (j = 0; j < 3; j++)
channel[j] = (unsigned int*)malloc(count*sizeof(unsigned int));
int pos = 0;
for (y = 0; y < height; y++) {
for (x = 0; x < width; x++) {
pixel = &pixels[y*bytes_per_line+x*bytes_per_pixel];
channel[0][pos] = (unsigned int)pixel[0];
channel[1][pos] = (unsigned int)pixel[1];
channel[2][pos] = (unsigned int)pixel[2];
pos++;
}
}
clock_t t1, t2;
t1 = clock();
host_erosiondilationfilter(gridSize, blockSize,
channel[0], channel[1], channel[2],
(int)width, (int)height,
radius2, mode);
t2 = clock();
double seconds = ((double)(t2-t1))/CLOCKS_PER_SEC;
printf("Execution time :\t%le\n", seconds);
pos = 0;
for (y = 0; y < height; y++) {
for (x = 0; x < width; x++) {
pixel = &pixels[y*bytes_per_line+x*bytes_per_pixel];
pixel[0] = (uint8_t)channel[0][pos];
pixel[1] = (uint8_t)channel[1][pos];
pixel[2] = (uint8_t)channel[2][pos];
pos++;
}
}
/* высвобождаем массивы */
for (j = 0; j < 3; j++)
free(channel[j]);
/* выводим результаты */
file = fopen(outputFileName, "wb");
if (!file) {
fprintf(stderr, "Open file error (%s)\n", outputFileName);
fflush(stderr);
exit(-1);
}
fwrite((void*)buffer, (size_t)1, (size_t)size, file);
printf("Output file size :\t%ld\n", size);
free(buffer);
fclose(file);
hipDeviceReset();
exit(0);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20global_set2grayscalePfPjfii
.globl _Z20global_set2grayscalePfPjfii
.p2align 8
.type _Z20global_set2grayscalePfPjfii,@function
_Z20global_set2grayscalePfPjfii:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x14
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s6, 0xffff
s_mul_i32 s8, s5, s4
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s2, s9
s_mov_b32 s2, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(1)
v_cvt_f32_ubyte0_e32 v0, v0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmac_f32 v4, s0, v0 :: v_dual_add_nc_u32 v1, s1, v1
v_cmp_le_i32_e32 vcc_lo, s8, v1
global_store_b32 v[2:3], v4, off
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20global_set2grayscalePfPjfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20global_set2grayscalePfPjfii, .Lfunc_end0-_Z20global_set2grayscalePfPjfii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z20global_add2grayscalePfPjfii
.globl _Z20global_add2grayscalePfPjfii
.p2align 8
.type _Z20global_add2grayscalePfPjfii,@function
_Z20global_add2grayscalePfPjfii:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x14
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s6, 0xffff
s_mul_i32 s8, s5, s4
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB1_3
s_load_b32 s2, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s2, s9
s_mov_b32 s2, 0
.p2align 6
.LBB1_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(1)
v_cvt_f32_ubyte0_e32 v0, v0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmac_f32 v4, s0, v0 :: v_dual_add_nc_u32 v1, s1, v1
v_cmp_le_i32_e32 vcc_lo, s8, v1
global_store_b32 v[2:3], v4, off
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20global_add2grayscalePfPjfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z20global_add2grayscalePfPjfii, .Lfunc_end1-_Z20global_add2grayscalePfPjfii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z21global_find2grayscalePfPjiifi
.globl _Z21global_find2grayscalePfPjiifi
.p2align 8
.type _Z21global_find2grayscalePfPjiifi,@function
_Z21global_find2grayscalePfPjiifi:
s_load_b32 s3, s[0:1], 0x18
s_mov_b32 s12, 0
.LBB2_1:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s12, s12, 1
v_cvt_f32_i32_e32 v1, s12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v1, v1, v1
s_waitcnt lgkmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, s3, v1
s_cbranch_vccnz .LBB2_1
s_clause 0x2
s_load_b32 s14, s[0:1], 0x1c
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, -1
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s14, 1
s_mul_i32 s13, s9, s8
s_cbranch_scc0 .LBB2_24
s_load_b32 s2, s[0:1], 0x2c
s_add_u32 s10, s0, 32
s_addc_u32 s11, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s18, s2, 0xffff
s_cmp_gt_i32 s14, -1
v_mad_u64_u32 v[1:2], null, s15, s18, v[0:1]
s_mov_b32 s14, -1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s13, v1
s_cbranch_scc0 .LBB2_8
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s14, s2
s_cbranch_execz .LBB2_7
s_load_b32 s16, s[10:11], 0x0
v_mov_b32_e32 v2, v1
s_mov_b32 s17, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s16, s16, s18
.LBB2_6:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_store_b32 v[3:4], v2, off
v_add_nc_u32_e32 v2, s16, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s13, v2
s_or_b32 s17, vcc_lo, s17
s_and_not1_b32 exec_lo, exec_lo, s17
s_cbranch_execnz .LBB2_6
.LBB2_7:
s_or_b32 exec_lo, exec_lo, s14
s_mov_b32 s14, 0
.LBB2_8:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s14
s_cbranch_vccnz .LBB2_23
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s14, s2
s_cbranch_execz .LBB2_22
s_ashr_i32 s16, s8, 31
s_load_b32 s10, s[10:11], 0x0
s_add_i32 s2, s8, s16
s_mov_b32 s11, 0
s_xor_b32 s17, s2, s16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v2, s17
s_sub_i32 s2, 0, s17
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt lgkmcnt(0)
s_mul_i32 s10, s10, s18
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
s_sub_i32 s18, 0, s12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v2, v2
v_mul_lo_u32 v3, s2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v2, v3
v_add_nc_u32_e32 v8, v2, v3
s_branch .LBB2_13
.LBB2_11:
s_or_b32 exec_lo, exec_lo, s20
.LBB2_12:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s19
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, s10, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_i32_e32 vcc_lo, s13, v1
v_add_co_u32 v4, s2, s6, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s2, s7, v5, s2
s_or_b32 s11, vcc_lo, s11
global_store_b32 v[4:5], v3, off
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execz .LBB2_22
.LBB2_13:
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s19, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v1, v2
v_xor_b32_e32 v3, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v3, v8
v_mul_lo_u32 v5, v4, s17
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v3, v5
v_add_nc_u32_e32 v5, 1, v4
v_subrev_nc_u32_e32 v6, s17, v3
v_cmp_le_u32_e32 vcc_lo, s17, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v5, v4, v5, vcc_lo
v_cndmask_b32_e32 v3, v3, v6, vcc_lo
v_xor_b32_e32 v4, s16, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v6, 1, v5
v_cmp_le_u32_e32 vcc_lo, s17, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v5, v6, vcc_lo
v_xor_b32_e32 v5, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v6, v5, v4
v_mul_lo_u32 v2, v6, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v9, v1, v2
v_add_nc_u32_e32 v3, s12, v9
v_add_nc_u32_e32 v2, s18, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_min_i32_e32 v10, s8, v3
v_mov_b32_e32 v3, v1
v_max_i32_e32 v11, 0, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_le_i32_e64 v11, v10
s_cbranch_execz .LBB2_12
v_add_nc_u32_e32 v3, s18, v6
v_add_nc_u32_e32 v7, s12, v6
v_max_i32_e32 v6, 0, v2
v_sub_nc_u32_e32 v14, v4, v5
s_mov_b32 s20, 0
v_max_i32_e32 v12, 0, v3
v_min_i32_e32 v13, s9, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s8, v12, v[6:7]
v_cmp_le_i32_e32 vcc_lo, v12, v13
v_mov_b32_e32 v3, v1
s_branch .LBB2_17
.LBB2_15:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s22
.LBB2_16:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s21
v_add_nc_u32_e32 v4, 1, v11
v_cmp_ge_i32_e64 s2, v11, v10
v_dual_mov_b32 v11, v4 :: v_dual_add_nc_u32 v2, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s20, s2, s20
s_and_not1_b32 exec_lo, exec_lo, s20
s_cbranch_execz .LBB2_11
.LBB2_17:
s_and_saveexec_b32 s21, vcc_lo
s_cbranch_execz .LBB2_16
v_sub_nc_u32_e32 v4, v11, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v15, v12
s_mov_b32 s22, 0
v_mul_lo_u32 v5, v4, v4
s_set_inst_prefetch_distance 0x1
s_branch .LBB2_20
.p2align 6
.LBB2_19:
s_or_b32 exec_lo, exec_lo, s23
v_add_nc_u32_e32 v4, 1, v15
v_cmp_ge_i32_e64 s2, v15, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v15, v4 :: v_dual_add_nc_u32 v6, s8, v6
s_or_b32 s22, s2, s22
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s22
s_cbranch_execz .LBB2_15
.LBB2_20:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v14, v15
s_mov_b32 s23, exec_lo
v_mad_u64_u32 v[16:17], null, v4, v4, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v4, v16
v_cmpx_ge_f32_e32 s3, v4
s_cbranch_execz .LBB2_19
v_ashrrev_i32_e32 v7, 31, v6
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[16:17], 2, v[6:7]
v_lshlrev_b64 v[18:19], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v16, s2, s4, v16
v_add_co_ci_u32_e64 v17, s2, s5, v17, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v18, s2, s4, v18
v_add_co_ci_u32_e64 v19, s2, s5, v19, s2
s_clause 0x1
global_load_b32 v4, v[16:17], off
global_load_b32 v7, v[18:19], off
s_waitcnt vmcnt(0)
v_cmp_lt_f32_e64 s2, v4, v7
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v3, v3, v6, s2
s_branch .LBB2_19
.LBB2_22:
s_or_b32 exec_lo, exec_lo, s14
.LBB2_23:
s_mov_b32 s2, 0
.LBB2_24:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB2_38
s_load_b32 s2, s[0:1], 0x2c
s_add_u32 s0, s0, 32
s_addc_u32 s1, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s11, s2, 0xffff
s_mov_b32 s2, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s11, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s13, v1
s_cbranch_execz .LBB2_38
s_ashr_i32 s2, s8, 31
s_load_b32 s1, s[0:1], 0x0
s_add_i32 s10, s8, s2
s_sub_i32 s14, 0, s12
s_xor_b32 s10, s10, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v0, s10
s_sub_i32 s0, 0, s10
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s1, s11
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_mov_b32 s11, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v7, v0, v2
s_branch .LBB2_29
.LBB2_27:
s_or_b32 exec_lo, exec_lo, s16
.LBB2_28:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s15
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_i32_e32 vcc_lo, s13, v1
v_add_co_u32 v4, s0, s6, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s0, s7, v5, s0
s_or_b32 s11, vcc_lo, s11
global_store_b32 v[4:5], v3, off
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execz .LBB2_38
.LBB2_29:
v_ashrrev_i32_e32 v0, 31, v1
s_mov_b32 s15, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v1, v0
v_xor_b32_e32 v2, v2, v0
v_xor_b32_e32 v0, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v2, v7
v_mul_lo_u32 v4, v3, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v2, v4
v_add_nc_u32_e32 v4, 1, v3
v_subrev_nc_u32_e32 v5, s10, v2
v_cmp_le_u32_e32 vcc_lo, s10, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v3, v3, v4 :: v_dual_cndmask_b32 v2, v2, v5
v_add_nc_u32_e32 v4, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s10, v2
v_cndmask_b32_e32 v2, v3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v4, v2, v0
v_sub_nc_u32_e32 v5, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v5, s8
v_sub_nc_u32_e32 v8, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, s14, v8
v_add_nc_u32_e32 v3, s12, v8
v_max_i32_e32 v10, 0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_min_i32_e32 v9, s8, v3
v_mov_b32_e32 v3, v1
v_cmpx_le_i32_e64 v10, v9
s_cbranch_execz .LBB2_28
v_add_nc_u32_e32 v3, s14, v5
v_add_nc_u32_e32 v6, s12, v5
v_max_i32_e32 v5, 0, v2
v_sub_nc_u32_e32 v13, v0, v4
s_mov_b32 s16, 0
v_max_i32_e32 v11, 0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s8, v11, v[5:6]
v_mov_b32_e32 v3, v1
v_min_i32_e32 v12, s9, v6
v_cmp_le_i32_e32 vcc_lo, v11, v12
s_branch .LBB2_33
.LBB2_31:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s18
.LBB2_32:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
s_or_b32 exec_lo, exec_lo, s17
v_add_nc_u32_e32 v0, 1, v10
v_cmp_ge_i32_e64 s0, v10, v9
v_add_nc_u32_e32 v2, 1, v2
v_mov_b32_e32 v10, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s16, s0, s16
s_and_not1_b32 exec_lo, exec_lo, s16
s_cbranch_execz .LBB2_27
.LBB2_33:
s_and_saveexec_b32 s17, vcc_lo
s_cbranch_execz .LBB2_32
v_sub_nc_u32_e32 v0, v10, v8
v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v14, v11
s_mov_b32 s18, 0
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v0, v0, v0
s_set_inst_prefetch_distance 0x1
s_branch .LBB2_36
.p2align 6
.LBB2_35:
s_or_b32 exec_lo, exec_lo, s19
v_add_nc_u32_e32 v4, 1, v14
v_cmp_ge_i32_e64 s0, v14, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v14, v4 :: v_dual_add_nc_u32 v5, s8, v5
s_or_b32 s18, s0, s18
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s18
s_cbranch_execz .LBB2_31
.LBB2_36:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v13, v14
s_mov_b32 s19, exec_lo
v_mad_u64_u32 v[15:16], null, v4, v4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v4, v15
v_cmpx_ge_f32_e32 s3, v4
s_cbranch_execz .LBB2_35
v_ashrrev_i32_e32 v6, 31, v5
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[15:16], 2, v[5:6]
v_lshlrev_b64 v[17:18], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v15, s0, s4, v15
v_add_co_ci_u32_e64 v16, s0, s5, v16, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v17, s0, s4, v17
v_add_co_ci_u32_e64 v18, s0, s5, v18, s0
s_clause 0x1
global_load_b32 v4, v[15:16], off
global_load_b32 v6, v[17:18], off
s_waitcnt vmcnt(0)
v_cmp_gt_f32_e64 s0, v4, v6
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v3, v3, v5, s0
s_branch .LBB2_35
.LBB2_38:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21global_find2grayscalePfPjiifi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 20
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z21global_find2grayscalePfPjiifi, .Lfunc_end2-_Z21global_find2grayscalePfPjiifi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z17global_indexcolorPjS_S_ii
.globl _Z17global_indexcolorPjS_S_ii
.p2align 8
.type _Z17global_indexcolorPjS_S_ii,@function
_Z17global_indexcolorPjS_S_ii:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s6, 0xffff
s_mul_i32 s8, s5, s4
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB3_3
s_load_b32 s10, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s10, s9
s_mov_b32 s9, 0
.p2align 6
.LBB3_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v6, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v5, vcc_lo
v_add_co_u32 v4, s0, s6, v4
v_add_co_ci_u32_e64 v5, s0, s7, v5, s0
global_load_b32 v2, v[6:7], off
s_waitcnt vmcnt(0)
v_lshlrev_b64 v[6:7], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s8, v1
global_load_b32 v0, v[6:7], off
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v0, off
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB3_2
.LBB3_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17global_indexcolorPjS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z17global_indexcolorPjS_S_ii, .Lfunc_end3-_Z17global_indexcolorPjS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20global_set2grayscalePfPjfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20global_set2grayscalePfPjfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20global_add2grayscalePfPjfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20global_add2grayscalePfPjfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21global_find2grayscalePfPjiifi
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z21global_find2grayscalePfPjiifi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 20
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17global_indexcolorPjS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17global_indexcolorPjS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | char *title = "Erosion and Dilation filter";
char *description = "Erosion and Dilation filter";
/*
Фильтр «минимум» – также известный как фильтр эрозии, заменяет значение минимальным в окрестности.
Фильтр «максимум» – также известный как фильтр расширения, заменяет значение максимальным в окрестности.
*/
#include <iostream>
#include <cstdio>
#include <cstdlib>
#include <assert.h>
#include <time.h>
#include <hip/hip_runtime.h>
#ifndef max
#define max( a, b ) ( ((a) > (b)) ? (a) : (b) )
#endif
#ifndef min
#define min( a, b ) ( ((a) < (b)) ? (a) : (b) )
#endif
#ifndef uint8_t
typedef unsigned char uint8_t;
#endif
#ifndef uint16_t
typedef unsigned short uint16_t;
#endif
#ifndef uint32_t
typedef unsigned int uint32_t;
#endif
// http://en.wikipedia.org/wiki/BMP_file_format
#define BMPMAGIC 0x00
#define BMPFILESIZE 0x02
#define BMPOFFSET 0x0A
#define BMPDIBSISE 0x0E
#define BMPWIDTH 0x12
#define BMPHEIGHT 0x16
#define BMPBITSPERPIXEL 0x1C
typedef struct {
uint8_t magic[2]; /* the magic number used to identify the BMP file:
0x42 0x4D (Hex code points for B and M).
The following entries are possible:
BM - Windows 3.1x, 95, NT, ... etc
BA - OS/2 Bitmap Array
CI - OS/2 Color Icon
CP - OS/2 Color Pointer
IC - OS/2 Icon
PT - OS/2 Pointer. */
uint32_t filesz; /* the size of the BMP file in bytes */
uint16_t creator1; /* reserved. */
uint16_t creator2; /* reserved. */
uint32_t offset; /* the offset, i.e. starting address,
of the byte where the bitmap data can be found. */
} bmp_header_t;
typedef struct {
uint32_t header_sz; /* the size of this header (40 bytes) */
uint32_t width; /* the bitmap width in pixels */
uint32_t height; /* the bitmap height in pixels */
uint16_t nplanes; /* the number of color planes being used.
Must be set to 1. */
uint16_t depth; /* the number of bits per pixel,
which is the color depth of the image.
Typical values are 1, 4, 8, 16, 24 and 32. */
uint32_t compress_type; /* the compression method being used.
See also bmp_compression_method_t. */
uint32_t bmp_bytesz; /* the image size. This is the size of the raw bitmap
data (see below), and should not be confused
with the file size. */
uint32_t hres; /* the horizontal resolution of the image.
(pixel per meter) */
uint32_t vres; /* the vertical resolution of the image.
(pixel per meter) */
uint32_t ncolors; /* the number of colors in the color palette,
or 0 to default to 2<sup><i>n</i></sup>. */
uint32_t nimpcolors; /* the number of important colors used,
or 0 when every color is important;
generally ignored. */
} bmp_dib_v3_header_t;
__global__ void global_set2grayscale(
float *grayscale,
unsigned int *input,
float weight,
int width,
int height)
{
for (int id = blockDim.x*blockIdx.x + threadIdx.x;
id < width*height;
id += blockDim.x*gridDim.x) {
grayscale[id] += weight*(float)(input[id]&0xFF);
}
}
__global__ void global_add2grayscale(
float *grayscale,
unsigned int *input,
float weight,
int width,
int height)
{
for (int id = blockDim.x*blockIdx.x + threadIdx.x;
id < width*height;
id += blockDim.x*gridDim.x) {
grayscale[id] += weight*(float)(input[id]&0xFF);
}
}
// Поиск индекса элемента с наилучшим значением интенсивности
__global__ void global_find2grayscale(
float *grayscale,
unsigned int *index,
int width,
int height,
float radius2,
int mode)
{
int radius = 1;
while((float)radius*radius<radius2) radius++; // поскольку числа маленькие, то быстрее перебором
if(mode>0){ // если расширение
for (int id = blockDim.x*blockIdx.x + threadIdx.x;
id < width*height;
id += blockDim.x*gridDim.x) {
int x=id%width;
int y=id/width;
int currentId = id;
// перебираем пиксели в окружности
for(int i=max(0,x-radius);i<=min(width,x+radius);i++){
for(int j=max(0,y-radius);j<=min(height,y+radius);j++){
if((float)((i-x)*(i-x)+(j-y)*(j-y))<=radius2) {
int itemId = j*width+i;
if(grayscale[itemId]>grayscale[currentId]) currentId=itemId;
}
}
}
index[id] = currentId;
}
} else if(mode<0){ // если эрозия
for (int id = blockDim.x*blockIdx.x + threadIdx.x;
id < width*height;
id += blockDim.x*gridDim.x) {
int x=id%width;
int y=id/width;
int currentId = id;
// перебираем пиксели в окружности
for(int i=max(0,x-radius);i<=min(width,x+radius);i++){
for(int j=max(0,y-radius);j<=min(height,y+radius);j++){
if((float)((i-x)*(i-x)+(j-y)*(j-y))<=radius2) {
int itemId = j*width+i;
if(grayscale[itemId]<grayscale[currentId]) currentId=itemId;
}
}
}
index[id] = currentId;
}
}else {
for (int id = blockDim.x*blockIdx.x + threadIdx.x;
id < width*height;
id += blockDim.x*gridDim.x) {
index[id] = id;
}
}
}
// Получение цвета из таблицы по индексу
__global__ void global_indexcolor(
unsigned int *input,
unsigned int *output,
unsigned int *index,
int width,
int height)
{
for (int id = blockDim.x*blockIdx.x + threadIdx.x;
id < width*height;
id += blockDim.x*gridDim.x) {
output[id] = input[index[id]];
}
}
__host__ void host_erosiondilationfilter(
int gridSize,
int blockSize,
unsigned int *r,
unsigned int *g,
unsigned int *b,
int width,
int height,
float radius2,
int mode)
{
// формула для конвертации RGB в интенсивность
// http://en.wikipedia.org/wiki/Grayscale
// Y = 0.2126 * R + 0.7152 * G + 0.0722 * B
unsigned int *channel[3] = { r,g,b };
float weight[3] = {0.2126f, 0.7152f, 0.0722f};
// channel - массив данных
// width - ширина
// height - высота
hipError_t err;
float *device_grayscale;
unsigned int *device_input;
unsigned int *device_output;
unsigned int *device_index;
err = hipMalloc((void**)&device_input, width*height*sizeof(unsigned int));
err = hipMalloc((void**)&device_grayscale, width*height*sizeof(float));
int blocks = (gridSize > 0)? gridSize : min(15, (int)sqrt(width*height));
int threads = (blockSize > 0)? blockSize : min(15, (int)sqrt(width*height));
// Шаг 1. Рассчитываем монохромное изображение
hipMemcpy(device_input, channel[0], width*height*sizeof(unsigned int), hipMemcpyHostToDevice);
global_set2grayscale <<< blocks, threads >>>(device_grayscale, device_input, weight[0], width, height);
for(int j=1;j<3;j++){
hipMemcpy(device_input, channel[j], width*height*sizeof(unsigned int), hipMemcpyHostToDevice);
global_add2grayscale <<< blocks, threads >>>(device_grayscale, device_input, weight[j], width, height);
}
err = hipMalloc((void**)&device_index, width*height*sizeof(unsigned int));
// Шаг 2. Находим индексы (то есть находим требуемую замену пикселей)
global_find2grayscale <<< blocks, threads >>>(device_grayscale, device_index, width, height, radius2, mode);
hipFree((void*)device_grayscale);
err = hipMalloc((void**)&device_output, width*height*sizeof(unsigned int));
// Шаг 3. Заменяем пиксели согласно ранее полученной подстановке
for(int j=3;j-->0;){
// Перевый раз копировать в видео память не надо, поскольку уже копировали при подсчёте монохромного изображения
if(j<2) hipMemcpy(device_input, channel[j], width*height*sizeof(unsigned int), hipMemcpyHostToDevice);
global_indexcolor <<< blocks, threads >>>(device_input, device_output, device_index, width, height);
hipMemcpy(channel[j], device_output, width*height*sizeof(unsigned int), hipMemcpyDeviceToHost);
}
hipFree((void*)device_index);
hipFree((void*)device_input);
hipFree((void*)device_output);
err = err;
}
int main(int argc, char* argv[])
{
int i, j;
std::cout << title << std::endl;
// Find/set the device.
int device_count = 0;
hipGetDeviceCount(&device_count);
for (i = 0; i < device_count; ++i)
{
hipDeviceProp_t properties;
hipGetDeviceProperties(&properties, i);
std::cout << "Running on GPU " << i << " (" << properties.name << ")" << std::endl;
}
if (argc < 5){
printf("Usage :\t%s filter radius2 inputfilename.bmp ouputfilename.bmp\n", argv[0]);
exit(-1);
}
// Получаем параметры - имена файлов
char *filter = argv[1];
float radius2 = atof(argv[2]);
char *inputFileName = argv[3];
char *outputFileName = argv[4];
int gridSize = (argc>5)?atoi(argv[5]):0;
int blockSize = (argc>6)?atoi(argv[6]):0;
int mode = (strcmp(filter,"dilation")==0)?1:-1;
printf("Title :\t%s\n", title);
printf("Description :\t%s\n", description);
printf("Filter :\t%s\n", filter);
printf("Radius2 :\t%d\n", radius2);
printf("Input file name :\t%s\n", inputFileName);
printf("Output file name :\t%s\n", outputFileName);
FILE *file = fopen(inputFileName, "rb");
if (!file) {
fprintf(stderr, "Open file error (%s)\n", inputFileName);
fflush(stderr);
exit(-1);
}
fseek(file, 0L, SEEK_END);
long size = ftell(file);
unsigned char *buffer = (unsigned char *)malloc((size_t)size);
fseek(file, 0L, SEEK_SET);
fread((void*)buffer, (size_t)1, (size_t)size, file);
fclose(file);
uint32_t width = *(uint32_t *)&buffer[BMPWIDTH];
uint32_t height = *(uint32_t *)&buffer[BMPHEIGHT];
uint32_t file_size = *(uint32_t *)&buffer[BMPFILESIZE];
uint32_t offset = *(uint32_t *)&buffer[BMPOFFSET];
uint16_t bits_per_pixel = *(uint16_t *)&buffer[BMPBITSPERPIXEL];
uint16_t bytes_per_pixel = ((int)((bits_per_pixel+7)/8));
uint32_t bytes_per_line = ((int)((bits_per_pixel * width+31)/32))*4; // http://en.wikipedia.org/wiki/BMP_file_format
printf("BMP image size :\t%ld x %ld\n", width, height);
printf("BMP file size :\t%ld\n", file_size);
printf("BMP pixels offset :\t%ld\n", offset);
printf("BMP bits per pixel :\t%d\n", bits_per_pixel);
printf("BMP bytes per pixel :\t%d\n", bytes_per_pixel);
printf("BMP bytes per line :\t%d\n", bytes_per_line);
uint8_t *pixels =(uint8_t *)&buffer[offset];
uint8_t *pixel;
uint32_t x, y;
/* выделение памяти под байтовые цветовые каналы */
int count = width*height;
unsigned int* channel[3];
for (j = 0; j < 3; j++)
channel[j] = (unsigned int*)malloc(count*sizeof(unsigned int));
int pos = 0;
for (y = 0; y < height; y++) {
for (x = 0; x < width; x++) {
pixel = &pixels[y*bytes_per_line+x*bytes_per_pixel];
channel[0][pos] = (unsigned int)pixel[0];
channel[1][pos] = (unsigned int)pixel[1];
channel[2][pos] = (unsigned int)pixel[2];
pos++;
}
}
clock_t t1, t2;
t1 = clock();
host_erosiondilationfilter(gridSize, blockSize,
channel[0], channel[1], channel[2],
(int)width, (int)height,
radius2, mode);
t2 = clock();
double seconds = ((double)(t2-t1))/CLOCKS_PER_SEC;
printf("Execution time :\t%le\n", seconds);
pos = 0;
for (y = 0; y < height; y++) {
for (x = 0; x < width; x++) {
pixel = &pixels[y*bytes_per_line+x*bytes_per_pixel];
pixel[0] = (uint8_t)channel[0][pos];
pixel[1] = (uint8_t)channel[1][pos];
pixel[2] = (uint8_t)channel[2][pos];
pos++;
}
}
/* высвобождаем массивы */
for (j = 0; j < 3; j++)
free(channel[j]);
/* выводим результаты */
file = fopen(outputFileName, "wb");
if (!file) {
fprintf(stderr, "Open file error (%s)\n", outputFileName);
fflush(stderr);
exit(-1);
}
fwrite((void*)buffer, (size_t)1, (size_t)size, file);
printf("Output file size :\t%ld\n", size);
free(buffer);
fclose(file);
hipDeviceReset();
exit(0);
} | .text
.file "cudaerosiondilationfilter.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z35__device_stub__global_set2grayscalePfPjfii # -- Begin function _Z35__device_stub__global_set2grayscalePfPjfii
.p2align 4, 0x90
.type _Z35__device_stub__global_set2grayscalePfPjfii,@function
_Z35__device_stub__global_set2grayscalePfPjfii: # @_Z35__device_stub__global_set2grayscalePfPjfii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20global_set2grayscalePfPjfii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z35__device_stub__global_set2grayscalePfPjfii, .Lfunc_end0-_Z35__device_stub__global_set2grayscalePfPjfii
.cfi_endproc
# -- End function
.globl _Z35__device_stub__global_add2grayscalePfPjfii # -- Begin function _Z35__device_stub__global_add2grayscalePfPjfii
.p2align 4, 0x90
.type _Z35__device_stub__global_add2grayscalePfPjfii,@function
_Z35__device_stub__global_add2grayscalePfPjfii: # @_Z35__device_stub__global_add2grayscalePfPjfii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20global_add2grayscalePfPjfii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z35__device_stub__global_add2grayscalePfPjfii, .Lfunc_end1-_Z35__device_stub__global_add2grayscalePfPjfii
.cfi_endproc
# -- End function
.globl _Z36__device_stub__global_find2grayscalePfPjiifi # -- Begin function _Z36__device_stub__global_find2grayscalePfPjiifi
.p2align 4, 0x90
.type _Z36__device_stub__global_find2grayscalePfPjiifi,@function
_Z36__device_stub__global_find2grayscalePfPjiifi: # @_Z36__device_stub__global_find2grayscalePfPjiifi
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21global_find2grayscalePfPjiifi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end2:
.size _Z36__device_stub__global_find2grayscalePfPjiifi, .Lfunc_end2-_Z36__device_stub__global_find2grayscalePfPjiifi
.cfi_endproc
# -- End function
.globl _Z32__device_stub__global_indexcolorPjS_S_ii # -- Begin function _Z32__device_stub__global_indexcolorPjS_S_ii
.p2align 4, 0x90
.type _Z32__device_stub__global_indexcolorPjS_S_ii,@function
_Z32__device_stub__global_indexcolorPjS_S_ii: # @_Z32__device_stub__global_indexcolorPjS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17global_indexcolorPjS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z32__device_stub__global_indexcolorPjS_S_ii, .Lfunc_end3-_Z32__device_stub__global_indexcolorPjS_S_ii
.cfi_endproc
# -- End function
.globl _Z26host_erosiondilationfilteriiPjS_S_iifi # -- Begin function _Z26host_erosiondilationfilteriiPjS_S_iifi
.p2align 4, 0x90
.type _Z26host_erosiondilationfilteriiPjS_S_iifi,@function
_Z26host_erosiondilationfilteriiPjS_S_iifi: # @_Z26host_erosiondilationfilteriiPjS_S_iifi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movss %xmm0, 188(%rsp) # 4-byte Spill
movq %rdx, %r15
movl %esi, %ebp
movl %edi, %r12d
movl 288(%rsp), %ebx
movq %rdx, 192(%rsp)
movq %rcx, 200(%rsp)
movq %r8, 208(%rsp)
movabsq $4555135220174140368, %rax # imm = 0x3F3717593E59B3D0
movq %rax, 220(%rsp)
movl $1033100696, 228(%rsp) # imm = 0x3D93DD98
movl %r9d, 20(%rsp) # 4-byte Spill
imull %r9d, %ebx
movslq %ebx, %r14
shlq $2, %r14
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 120(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %r12d, %r12d
jg .LBB4_9
# %bb.1:
cvtsi2sd %ebx, %xmm1
xorpd %xmm0, %xmm0
ucomisd %xmm0, %xmm1
jb .LBB4_3
# %bb.2:
xorps %xmm0, %xmm0
sqrtsd %xmm1, %xmm0
jmp .LBB4_4
.LBB4_3: # %call.sqrt
movapd %xmm1, %xmm0
movsd %xmm1, 176(%rsp) # 8-byte Spill
callq sqrt
movsd 176(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
.LBB4_4: # %.split
cvttsd2si %xmm0, %eax
movl $15, %r12d
cmpl $15, %eax
jg .LBB4_9
# %bb.5:
xorpd %xmm0, %xmm0
ucomisd %xmm0, %xmm1
jb .LBB4_7
# %bb.6:
xorps %xmm0, %xmm0
sqrtsd %xmm1, %xmm0
jmp .LBB4_8
.LBB4_7: # %call.sqrt130
movapd %xmm1, %xmm0
callq sqrt
.LBB4_8: # %.split129
cvttsd2si %xmm0, %r12d
.LBB4_9:
testl %ebp, %ebp
jg .LBB4_18
# %bb.10:
xorps %xmm1, %xmm1
cvtsi2sd %ebx, %xmm1
xorpd %xmm0, %xmm0
ucomisd %xmm0, %xmm1
jb .LBB4_12
# %bb.11:
xorps %xmm0, %xmm0
sqrtsd %xmm1, %xmm0
jmp .LBB4_13
.LBB4_12: # %call.sqrt132
movapd %xmm1, %xmm0
movsd %xmm1, 176(%rsp) # 8-byte Spill
callq sqrt
movsd 176(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
.LBB4_13: # %.split131
cvttsd2si %xmm0, %eax
movl $15, %ebp
cmpl $15, %eax
jg .LBB4_18
# %bb.14:
xorpd %xmm0, %xmm0
ucomisd %xmm0, %xmm1
jb .LBB4_16
# %bb.15:
xorps %xmm0, %xmm0
sqrtsd %xmm1, %xmm0
jmp .LBB4_17
.LBB4_16: # %call.sqrt134
movapd %xmm1, %xmm0
callq sqrt
.LBB4_17: # %.split133
cvttsd2si %xmm0, %ebp
.LBB4_18:
movq 32(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r12d, %r15d
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r15
movl %ebp, %r12d
orq %rax, %r12
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_20
# %bb.19:
movq 120(%rsp), %rax
movq 32(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl $1046066128, 40(%rsp) # imm = 0x3E59B3D0
movl 20(%rsp), %eax # 4-byte Reload
movl %eax, 8(%rsp)
movl 288(%rsp), %eax
movl %eax, 24(%rsp)
leaq 104(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z20global_set2grayscalePfPjfii, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_20:
movl $1, %r13d
leaq 48(%rsp), %rbp
leaq 128(%rsp), %rbx
jmp .LBB4_21
.p2align 4, 0x90
.LBB4_23: # in Loop: Header=BB4_21 Depth=1
incq %r13
cmpq $3, %r13
je .LBB4_24
.LBB4_21: # =>This Inner Loop Header: Depth=1
movq 32(%rsp), %rdi
movq 192(%rsp,%r13,8), %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_23
# %bb.22: # in Loop: Header=BB4_21 Depth=1
movq 120(%rsp), %rax
movq 32(%rsp), %rcx
movss 220(%rsp,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movss %xmm0, 40(%rsp)
movl 20(%rsp), %eax # 4-byte Reload
movl %eax, 8(%rsp)
movl 288(%rsp), %eax
movl %eax, 24(%rsp)
leaq 104(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 88(%rsp), %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z20global_add2grayscalePfPjfii, %edi
movq %rbx, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB4_23
.LBB4_24:
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_26
# %bb.25:
movq 120(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl 20(%rsp), %eax # 4-byte Reload
movl %eax, 40(%rsp)
movl 288(%rsp), %eax
movl %eax, 8(%rsp)
movss 188(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 116(%rsp)
movl 296(%rsp), %eax
movl %eax, 112(%rsp)
leaq 104(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 116(%rsp), %rax
movq %rax, 160(%rsp)
leaq 112(%rsp), %rax
movq %rax, 168(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z21global_find2grayscalePfPjiifi, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_26:
movq 120(%rsp), %rdi
callq hipFree
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movl $3, %ebx
leaq 40(%rsp), %rbp
leaq 128(%rsp), %r13
jmp .LBB4_27
.p2align 4, 0x90
.LBB4_29: # in Loop: Header=BB4_27 Depth=1
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB4_30
.LBB4_31: # in Loop: Header=BB4_27 Depth=1
movq 184(%rsp,%rbx,8), %rdi
movq 8(%rsp), %rsi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
decq %rbx
je .LBB4_32
.LBB4_27: # =>This Inner Loop Header: Depth=1
cmpl $2, %ebx
ja .LBB4_29
# %bb.28: # in Loop: Header=BB4_27 Depth=1
movq 32(%rsp), %rdi
movq 184(%rsp,%rbx,8), %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
jmp .LBB4_29
.p2align 4, 0x90
.LBB4_30: # in Loop: Header=BB4_27 Depth=1
movq 32(%rsp), %rax
movq 8(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl 20(%rsp), %eax # 4-byte Reload
movl %eax, 116(%rsp)
movl 288(%rsp), %eax
movl %eax, 112(%rsp)
leaq 104(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 88(%rsp), %rax
movq %rax, 144(%rsp)
leaq 116(%rsp), %rax
movq %rax, 152(%rsp)
leaq 112(%rsp), %rax
movq %rax, 160(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z17global_indexcolorPjS_S_ii, %edi
movq %r13, %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB4_31
.LBB4_32:
movq 24(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z26host_erosiondilationfilteriiPjS_S_iifi, .Lfunc_end4-_Z26host_erosiondilationfilteriiPjS_S_iifi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI5_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1592, %rsp # imm = 0x638
.cfi_def_cfa_offset 1648
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
movq title(%rip), %r14
testq %r14, %r14
jne .LBB5_2
# %bb.1:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
jmp .LBB5_3
.LBB5_2:
movq %r14, %rdi
callq strlen
movl $_ZSt4cout, %edi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB5_3: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
jne .LBB5_4
.LBB5_43:
callq _ZSt16__throw_bad_castv
.LBB5_4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
jne .LBB5_5
# %bb.6:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
jmp .LBB5_7
.LBB5_5:
movzbl 67(%r14), %eax
.LBB5_7: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $0, 12(%rsp)
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 12(%rsp)
jle .LBB5_14
# %bb.8: # %.lr.ph.preheader
xorl %r14d, %r14d
leaq 112(%rsp), %r15
jmp .LBB5_9
.p2align 4, 0x90
.LBB5_11: # in Loop: Header=BB5_9 Depth=1
movzbl 67(%r13), %eax
.LBB5_13: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit127
# in Loop: Header=BB5_9 Depth=1
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incl %r14d
cmpl 12(%rsp), %r14d
jge .LBB5_14
.LBB5_9: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl %r14d, %esi
callq hipGetDevicePropertiesR0600
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %r12
movl $.L.str.2, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r15, %rdi
callq strlen
movq %r12, %rdi
movq %r15, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $.L.str.3, %esi
movl $1, %edx
movq %r12, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB5_43
# %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i124
# in Loop: Header=BB5_9 Depth=1
cmpb $0, 56(%r13)
jne .LBB5_11
# %bb.12: # in Loop: Header=BB5_9 Depth=1
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
jmp .LBB5_13
.LBB5_14: # %._crit_edge
cmpl $4, %ebp
jg .LBB5_15
# %bb.44:
movq (%rbx), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.LBB5_15:
movq 8(%rbx), %r15
movq 16(%rbx), %rdi
xorl %r13d, %r13d
xorl %esi, %esi
callq strtod
movq 24(%rbx), %r14
movq 32(%rbx), %r12
movl $0, %eax
cmpl $5, %ebp
je .LBB5_17
# %bb.16:
movq 40(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
movsd %xmm0, 24(%rsp) # 8-byte Spill
callq __isoc23_strtol
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
.LBB5_17:
movq %rax, 104(%rsp) # 8-byte Spill
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 36(%rsp) # 4-byte Spill
cmpl $7, %ebp
jl .LBB5_19
# %bb.18:
movq 48(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
.LBB5_19:
movl $.L.str.5, %esi
movq %r15, %rdi
callq strcmp
negl %eax
movl $0, %ebp
sbbl %ebp, %ebp
movq title(%rip), %rsi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movq description(%rip), %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl $.L.str.8, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
movss 36(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.9, %edi
movb $1, %al
callq printf
movl $.L.str.10, %edi
movq %r14, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.11, %edi
movq %r12, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.12, %esi
movq %r14, %rdi
callq fopen
testq %rax, %rax
jne .LBB5_40
# %bb.20:
movq stderr(%rip), %rdi
movl $.L.str.13, %esi
movq %r14, %rdx
jmp .LBB5_21
.LBB5_40:
movq %rax, %rbx
movq %r13, 88(%rsp) # 8-byte Spill
movq %r12, 96(%rsp) # 8-byte Spill
orl $1, %ebp
movq %rbp, 80(%rsp) # 8-byte Spill
xorl %r14d, %r14d
movq %rax, %rdi
xorl %esi, %esi
movl $2, %edx
callq fseek
movq %rbx, %rdi
callq ftell
movq %rax, %r15
movq %rax, %rdi
callq malloc
movq %rax, %rbp
movq %rax, 48(%rsp) # 8-byte Spill
movq %rbx, %rdi
xorl %esi, %esi
xorl %edx, %edx
callq fseek
movl $1, %esi
movq %rbp, %rdi
movq %r15, 56(%rsp) # 8-byte Spill
movq %r15, %rdx
movq %rbx, %rcx
callq fread
movq %rbx, %rdi
callq fclose
movl 18(%rbp), %r15d
movl 22(%rbp), %edx
movq %rdx, 72(%rsp) # 8-byte Spill
movl 2(%rbp), %eax
movl %eax, 24(%rsp) # 4-byte Spill
movl 10(%rbp), %eax
movq %rax, 16(%rsp) # 8-byte Spill
movzwl 28(%rbp), %r13d
leal 7(%r13), %ebx
shrl $3, %ebx
movl %r15d, %r12d
imull %r13d, %r12d
addl $31, %r12d
shrl $3, %r12d
andl $-4, %r12d
movl $.L.str.14, %edi
movl %r15d, %esi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
movl $.L.str.15, %edi
movl 24(%rsp), %esi # 4-byte Reload
xorl %eax, %eax
callq printf
movl $.L.str.16, %edi
movq 16(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
movl $.L.str.17, %edi
movl %r13d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.18, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movl $.L.str.19, %edi
movl %r12d, 24(%rsp) # 4-byte Spill
movl %r12d, %esi
xorl %eax, %eax
callq printf
movl %r15d, %eax
movq 72(%rsp), %rcx # 8-byte Reload
movq %rcx, %r12
imull %ecx, %eax
movslq %eax, %r13
shlq $2, %r13
.p2align 4, 0x90
.LBB5_41: # =>This Inner Loop Header: Depth=1
movq %r13, %rdi
callq malloc
movq %rax, 112(%rsp,%r14,8)
incq %r14
cmpq $3, %r14
jne .LBB5_41
# %bb.22: # %.preheader130
addq 16(%rsp), %rbp # 8-byte Folded Reload
testl %r12d, %r12d
jne .LBB5_23
.LBB5_29: # %._crit_edge139
callq clock
movq %rax, 64(%rsp) # 8-byte Spill
movq 112(%rsp), %rdx
movq 120(%rsp), %rcx
movq 128(%rsp), %r8
movq 104(%rsp), %rdi # 8-byte Reload
# kill: def $edi killed $edi killed $rdi
movq 88(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
movq %rdx, 16(%rsp) # 8-byte Spill
movq %rcx, 40(%rsp) # 8-byte Spill
movq %r8, %r13
movl %r15d, %r9d
movss 36(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
pushq 80(%rsp) # 8-byte Folded Reload
.cfi_adjust_cfa_offset 8
movq %r12, %r14
pushq %r12
.cfi_adjust_cfa_offset 8
callq _Z26host_erosiondilationfilteriiPjS_S_iifi
addq $16, %rsp
.cfi_adjust_cfa_offset -16
callq clock
subq 64(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI5_0(%rip), %xmm0
movl $.L.str.20, %edi
movb $1, %al
callq printf
testl %r14d, %r14d
jne .LBB5_30
.LBB5_36: # %.preheader.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB5_37: # %.preheader
# =>This Inner Loop Header: Depth=1
movq 112(%rsp,%rbx,8), %rdi
callq free
incq %rbx
cmpq $3, %rbx
jne .LBB5_37
# %bb.38:
movl $.L.str.21, %esi
movq 96(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
callq fopen
testq %rax, %rax
jne .LBB5_42
# %bb.39:
movq stderr(%rip), %rdi
movl $.L.str.13, %esi
movq %rbx, %rdx
.LBB5_21:
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rdi
callq fflush
movl $-1, %edi
callq exit
.LBB5_23: # %.preheader129.lr.ph
movq 112(%rsp), %rax
movq %rax, 16(%rsp) # 8-byte Spill
movq 120(%rsp), %rax
movq %rax, 40(%rsp) # 8-byte Spill
xorl %edx, %edx
movq 128(%rsp), %rsi
xorl %edi, %edi
xorl %r8d, %r8d
jmp .LBB5_24
.p2align 4, 0x90
.LBB5_27: # %._crit_edge136.loopexit
# in Loop: Header=BB5_24 Depth=1
addl %r11d, %edi
.LBB5_28: # %._crit_edge136
# in Loop: Header=BB5_24 Depth=1
incl %r8d
addl 24(%rsp), %edx # 4-byte Folded Reload
cmpl %r12d, %r8d
je .LBB5_29
.LBB5_24: # %.preheader129
# =>This Loop Header: Depth=1
# Child Loop BB5_26 Depth 2
testq %r15, %r15
je .LBB5_28
# %bb.25: # %.lr.ph135
# in Loop: Header=BB5_24 Depth=1
movslq %edi, %r11
movq 16(%rsp), %rax # 8-byte Reload
leaq (%rax,%r11,4), %r9
movq 40(%rsp), %rax # 8-byte Reload
leaq (%rax,%r11,4), %r10
leaq (%rsi,%r11,4), %r14
movl %edx, %r13d
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB5_26: # Parent Loop BB5_24 Depth=1
# => This Inner Loop Header: Depth=2
movl %r13d, %eax
movzbl (%rbp,%rax), %ecx
movl %ecx, (%r9,%r11,4)
movzbl 1(%rbp,%rax), %ecx
movl %ecx, (%r10,%r11,4)
movzbl 2(%rbp,%rax), %eax
movl %eax, (%r14,%r11,4)
incq %r11
addl %ebx, %r13d
cmpq %r11, %r15
jne .LBB5_26
jmp .LBB5_27
.LBB5_30: # %.preheader128.lr.ph
xorl %eax, %eax
xorl %ecx, %ecx
xorl %edx, %edx
jmp .LBB5_31
.p2align 4, 0x90
.LBB5_34: # %._crit_edge143.loopexit
# in Loop: Header=BB5_31 Depth=1
addl %r8d, %ecx
.LBB5_35: # %._crit_edge143
# in Loop: Header=BB5_31 Depth=1
incl %edx
addl 24(%rsp), %eax # 4-byte Folded Reload
cmpl %r12d, %edx
je .LBB5_36
.LBB5_31: # %.preheader128
# =>This Loop Header: Depth=1
# Child Loop BB5_33 Depth 2
testq %r15, %r15
je .LBB5_35
# %bb.32: # %.lr.ph142
# in Loop: Header=BB5_31 Depth=1
movslq %ecx, %r8
movq 16(%rsp), %rsi # 8-byte Reload
leaq (%rsi,%r8,4), %rsi
movq 40(%rsp), %rdi # 8-byte Reload
leaq (%rdi,%r8,4), %rdi
leaq (,%r8,4), %r9
addq %r13, %r9
movl %eax, %r10d
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB5_33: # Parent Loop BB5_31 Depth=1
# => This Inner Loop Header: Depth=2
movl %r10d, %r11d
movzbl (%rsi,%r8,4), %r14d
movb %r14b, (%rbp,%r11)
movzbl (%rdi,%r8,4), %r14d
movb %r14b, 1(%rbp,%r11)
movzbl (%r9,%r8,4), %r14d
movb %r14b, 2(%rbp,%r11)
incq %r8
addl %ebx, %r10d
cmpq %r8, %r15
jne .LBB5_33
jmp .LBB5_34
.LBB5_42:
movl $1, %esi
movq 48(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movq 56(%rsp), %r14 # 8-byte Reload
movq %r14, %rdx
movq %rax, %rcx
movq %rax, %rbx
callq fwrite
movl $.L.str.22, %edi
movq %r14, %rsi
xorl %eax, %eax
callq printf
movq %r15, %rdi
callq free
movq %rbx, %rdi
callq fclose
callq hipDeviceReset
xorl %edi, %edi
callq exit
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20global_set2grayscalePfPjfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20global_add2grayscalePfPjfii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21global_find2grayscalePfPjiifi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17global_indexcolorPjS_S_ii, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Erosion and Dilation filter"
.size .L.str, 28
.type title,@object # @title
.data
.globl title
.p2align 3, 0x0
title:
.quad .L.str
.size title, 8
.type description,@object # @description
.globl description
.p2align 3, 0x0
description:
.quad .L.str
.size description, 8
.type _Z20global_set2grayscalePfPjfii,@object # @_Z20global_set2grayscalePfPjfii
.section .rodata,"a",@progbits
.globl _Z20global_set2grayscalePfPjfii
.p2align 3, 0x0
_Z20global_set2grayscalePfPjfii:
.quad _Z35__device_stub__global_set2grayscalePfPjfii
.size _Z20global_set2grayscalePfPjfii, 8
.type _Z20global_add2grayscalePfPjfii,@object # @_Z20global_add2grayscalePfPjfii
.globl _Z20global_add2grayscalePfPjfii
.p2align 3, 0x0
_Z20global_add2grayscalePfPjfii:
.quad _Z35__device_stub__global_add2grayscalePfPjfii
.size _Z20global_add2grayscalePfPjfii, 8
.type _Z21global_find2grayscalePfPjiifi,@object # @_Z21global_find2grayscalePfPjiifi
.globl _Z21global_find2grayscalePfPjiifi
.p2align 3, 0x0
_Z21global_find2grayscalePfPjiifi:
.quad _Z36__device_stub__global_find2grayscalePfPjiifi
.size _Z21global_find2grayscalePfPjiifi, 8
.type _Z17global_indexcolorPjS_S_ii,@object # @_Z17global_indexcolorPjS_S_ii
.globl _Z17global_indexcolorPjS_S_ii
.p2align 3, 0x0
_Z17global_indexcolorPjS_S_ii:
.quad _Z32__device_stub__global_indexcolorPjS_S_ii
.size _Z17global_indexcolorPjS_S_ii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Running on GPU "
.size .L.str.1, 16
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " ("
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz ")"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Usage :\t%s filter radius2 inputfilename.bmp ouputfilename.bmp\n"
.size .L.str.4, 63
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "dilation"
.size .L.str.5, 9
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Title :\t%s\n"
.size .L.str.6, 12
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Description :\t%s\n"
.size .L.str.7, 18
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Filter :\t%s\n"
.size .L.str.8, 13
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Radius2 :\t%d\n"
.size .L.str.9, 14
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Input file name :\t%s\n"
.size .L.str.10, 22
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Output file name :\t%s\n"
.size .L.str.11, 23
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "rb"
.size .L.str.12, 3
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Open file error (%s)\n"
.size .L.str.13, 22
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "BMP image size :\t%ld x %ld\n"
.size .L.str.14, 28
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "BMP file size :\t%ld\n"
.size .L.str.15, 21
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "BMP pixels offset :\t%ld\n"
.size .L.str.16, 25
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "BMP bits per pixel :\t%d\n"
.size .L.str.17, 25
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "BMP bytes per pixel :\t%d\n"
.size .L.str.18, 26
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "BMP bytes per line :\t%d\n"
.size .L.str.19, 25
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "Execution time :\t%le\n"
.size .L.str.20, 22
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "wb"
.size .L.str.21, 3
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "Output file size :\t%ld\n"
.size .L.str.22, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20global_set2grayscalePfPjfii"
.size .L__unnamed_1, 32
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z20global_add2grayscalePfPjfii"
.size .L__unnamed_2, 32
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z21global_find2grayscalePfPjiifi"
.size .L__unnamed_3, 34
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z17global_indexcolorPjS_S_ii"
.size .L__unnamed_4, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__global_set2grayscalePfPjfii
.addrsig_sym _Z35__device_stub__global_add2grayscalePfPjfii
.addrsig_sym _Z36__device_stub__global_find2grayscalePfPjiifi
.addrsig_sym _Z32__device_stub__global_indexcolorPjS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20global_set2grayscalePfPjfii
.addrsig_sym _Z20global_add2grayscalePfPjfii
.addrsig_sym _Z21global_find2grayscalePfPjiifi
.addrsig_sym _Z17global_indexcolorPjS_S_ii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <algorithm>
#include <cmath>
#include <cstdio>
#include <fstream>
#include <iostream>
#include <sstream>
#include <string>
#include <vector>
#include <sys/time.h>
#include <chrono>
#include <dirent.h>
using namespace std::chrono;
using namespace std;
vector<int> G_timestamps;
int getCurrentTime () {
return duration_cast<milliseconds>(system_clock::now().time_since_epoch()).count();
}
void F_TIME_START () {
G_timestamps.push_back(getCurrentTime());
}
void F_TIME_END (string measuredName) {
int start = G_timestamps.back();
int end = getCurrentTime();
float diff = (end - start) / 1000.0;
G_timestamps.pop_back();
cout << endl << "## [" << measuredName << "]: " << diff << "s" << endl << endl;
}
void coutGPUStatus () {
size_t freem, totalm;
float free_m, total_m, used_m;
cudaMemGetInfo((size_t*)&freem, (size_t*)&totalm);
free_m = (size_t) freem / 1048576.0;
total_m = (size_t) totalm / 1048576.0;
used_m = total_m - free_m;
printf ( "## Total: %f MB. Used %f MB. Free: %f MB. \n", total_m, used_m, free_m);
}
void coutResult(int& generation, int& max_fitness_value) {
cout << "Generation " << generation << ", currently best individual can activate " << max_fitness_value << " others" << endl;
}
void coutPopulation (vector <vector<int>>& population) {
cout << "Population:";
for (int i=0; i<population.size(); i++) {
cout << "\nIndiv: " << i << ": ";
for (int j=0; j<population[i].size(); j++) {
if (population[i][j] < 10) {
cout << population[i][j] << ", ";
}
else if (population[i][j] < 100) {
cout << population[i][j] << ", ";
}
else if (population[i][j] < 1000) {
cout << population[i][j] << ", ";
}
else if (population[i][j] < 10000) {
cout << population[i][j] << ", ";
}
else {
cout << population[i][j] << ",";
}
}
}
cout << "\n\n";
}
void coutIndividual (vector <vector<int>>& population, int i) {
cout << "Individual " << i << ":";
for (int j=0; j<population[i].size(); j++) {
if (population[i][j] < 10) {
cout << population[i][j] << ", ";
}
else if (population[i][j] < 100) {
cout << population[i][j] << ", ";
}
else if (population[i][j] < 1000) {
cout << population[i][j] << ", ";
}
else if (population[i][j] < 10000) {
cout << population[i][j] << ", ";
}
else {
cout << population[i][j] << ",";
}
}
cout << "\n\n";
}
float getInfluenceValue (int N, int inf_values_size, vector<float>& inf_values, vector<float>& inf_col_ind, vector<float>& inf_row_ptr, int x, int y) {
float infValue = 0;
int min = inf_row_ptr[x];
int max = x == N-1 ? inf_values_size-1 : inf_row_ptr[x+1]; //inf_values_size-1
for (int i=min; i<max; i++) {
if (inf_col_ind[i] == y) {
infValue = inf_values[i];
break;
}
}
return infValue;
}
void InfluenceSpreadPopulationStep (bool *dyn_activeNodesPerIndividual, vector<float>& inf_values, vector<float>& inf_col_ind, vector<float>& inf_row_ptr, int N, int nrOfChangedIndividuals, int inf_values_size, float INFLUENCE_THRESHOLD, vector<int>& changedIndividuals) {
for (int indiv_id = 0; indiv_id < nrOfChangedIndividuals; indiv_id++) {
for (int node_id = 0; node_id < N; node_id++) {
int indiv_index = changedIndividuals[indiv_id];
float infValue = 0; // total value of influence on the node
for (int i=0; i<N; i++) {
if (dyn_activeNodesPerIndividual[indiv_index * N + i] && node_id != i) { // if i-th element is active and is not the node
float result = getInfluenceValue(N, inf_values_size, inf_values, inf_col_ind, inf_row_ptr, i, node_id);
infValue += result; // add i-th element influence on the node
//printf("Influence %d on %d is: %f\n", i, node_id, result);
//printf("\ninfValue: %f, id: %d", infValue, id);
}
}
//printf("\ninfValue: %f, id: %d", infValue, id);
if (infValue >= INFLUENCE_THRESHOLD) { // if total influence on the node is greater than or equal to the INFLUENCE_THRESHOLD value
dyn_activeNodesPerIndividual[indiv_index * N + node_id] = true; // activate the node
}
}
}
}
vector <vector<float>> readData (string dataset_name, int N, string _EXPERIMENT_ID) {
vector <vector<float>> influence;
// initialization of the influence vector
for (int i=0; i<N; i++) {
cout << endl << i << " out of " << N << endl;
vector<float> row(N, 0);
influence.push_back(row);
if ((i + 1) * N % (N * N / 10) == 0) {
cout << "[Initialization of the influence matrix]: " << float((i + 1) * N) / (N * N) * 100 << "%" << endl;
}
}
// total number of interactions received by every node
vector<float> received(N, 0);
ifstream infile("./experiments_" + _EXPERIMENT_ID + "/" + dataset_name);
string line;
int _csv_id_hack = -1;
if (dataset_name.find(".csv") != std::string::npos) {
_csv_id_hack = 0;
}
if (infile.good()) {
int line_nr = 0;
while (getline(infile, line)) {
cout << "Reading raw data file, line nr: " << line_nr << endl;
//cout << line << endl;
istringstream iss(line);
int a, b;
if (!(iss >> a >> b)) { cout << "ERROR" << endl; break; } // error
if (a != b && a + _csv_id_hack < N && b + _csv_id_hack < N) {
influence[a + _csv_id_hack][b + _csv_id_hack] += 1; // temp inf_values, calculating the total number of iteractions from "i" to "j"
received [b + _csv_id_hack] += 1;
//cout << "message from " << a + _csv_id_hack << " to " << b + _csv_id_hack << endl;
}
line_nr++;
}
infile.close();
cout << "File reading finished successfully." << endl;
ofstream outfile ("./experiments-counted/" + dataset_name + "_influenceCounted_" + to_string(N));
if (outfile.good()) {
// Influence value calculated as the ratio of iteractions from "i" node to "j" node, to the total number of iteractions to the "j" node.
for (int i=0; i<N; i++) {
for (int j=0; j<N; j++) {
//cout << "Influence values calculations, step: " << i*N+(j+1) << "/" << N*N << endl;
if (i == j) {
outfile << i << " " << j << " " << -1 << "\n";
influence[i][j] = -1;
} else if (influence[i][j] > 0) {
if (received[j] != 0) {
influence[i][j] = influence[i][j] / received[j];
} else if (influence[i][j] != 0) {
cout << "Received array error";
}
/*cout << i << "'s influence on " << j << " equals: " << influence[i][j] << endl;*/
outfile << i << " " << j << " " << influence[i][j] << "\n";
} else {
influence[i][j] = 0;
}
}
}
cout << "Compressed file saved successfully." << endl;
outfile.close();
} else {
throw std::invalid_argument("readData - File " + dataset_name + " not saved.");
}
} else {
throw std::invalid_argument("readData - File " + dataset_name + " not found.");
}
return influence;
}
void defineInfluenceArrayAndVectors (string dataset_name, int N, vector<float>& inf_values, vector<float>& inf_col_ind, vector<float>& inf_row_ptr, string _EXPERIMENT_ID) {
//cout << "File reading started." << endl;
ifstream infile("./experiments-counted/" + dataset_name + "_influenceCounted_" + to_string(N));
if (infile.good()) { // reading the already calculated influence values
int line_nr = 0;
string line;
float last_a = -1;
while (getline(infile, line)) {
cout << "Reading influence file, line nr: " << line_nr << endl;
istringstream iss(line);
float a, b, c;
if (!(iss >> a >> b >> c)) { break; } // error
if (c != 0) {
if (a != last_a) {
inf_row_ptr.push_back(inf_values.size());
//cout << "add row ptr: " << inf_values.size() << endl;
last_a = a;
}
inf_values.push_back(c);
//cout << "add value: " << c << endl;
inf_col_ind.push_back(b);
//cout << "add col ind: " << b << endl;
}
line_nr++;
}
infile.close();
} else { // calculating influnce values
infile.close();
vector <vector<float>> influence = readData(dataset_name, N, _EXPERIMENT_ID);
// inf_values, inf_col_ind, inf_row_ptr creation, based on the influence array
for (int i=0; i<N; i++) {
bool added = false;
for (int j=0; j<N; j++) {
//cout << "Influence of " << i << " on " << j << " is equal to: " << influence[i][j] << endl;
if (influence[i][j] != 0) {
if (!added) {
inf_row_ptr.push_back(inf_values.size());
//cout << "add row ptr: " << inf_values.size() << endl;
added = true;
}
inf_values.push_back(influence[i][j]);
//cout << "add value: " << influence[i][j] << endl;
inf_col_ind.push_back(j);
//cout << "add col ind: " << j << endl;
}
}
if (!added) {
//inf_row_ptr.push_back(-1);
}
}
/*cout << "\n\n size of influence array: " << sizeof(influence) + sizeof(float) * influence.capacity() * influence.capacity();
cout << "\n\n Total size of vectors: "
<< sizeof(inf_values) + sizeof(float) * inf_values.capacity()
+ sizeof(inf_col_ind) + sizeof(float) * inf_col_ind.capacity()
+ sizeof(inf_row_ptr) + sizeof(float) * inf_row_ptr.capacity() << "\n\n";*/
}
}
void createPopulation (int nrOfIndividuals, int N, int toFind, vector <vector<int>>& population) {
// creating random individuals within population
for (int i = 0; i<nrOfIndividuals; i++) {
vector<int> row;
population.push_back(row);
cout << "Creating individual " << i << " of " << nrOfIndividuals << endl;
for (int j = 0; j<toFind; j++) {
int rand_id = rand() % N;
bool alreadyAdded = true;
while (alreadyAdded) {
alreadyAdded = false;
for (int k=0; k<population[i].size(); k++) {
if (population[i][k] == rand_id) {
alreadyAdded = true;
rand_id = rand() % N;
}
}
}
//cout << "pushing: " << rand_id << endl;
population[i].push_back(rand_id);
}
}
}
void createPopulationSample (int nrOfIndividuals, int N, int toFind, vector <vector<int>>& population) {
// creating one individual - used as a sample e.g. for GPU vs CPU tests
vector<int> row;
population.push_back(row);
for (int x = 0; x<toFind; x++) {
population[0].push_back(x);
}
}
void setPopulationFitness (vector<vector<int>>& population, int nrOfIndividuals, int N, int inf_values_size, float& INFLUENCE_THRESHOLD, int STEPS_MAX, vector<float>& inf_values, vector<float>& inf_col_ind, vector<float>& inf_row_ptr, int toFind, vector<int>& fitness, int THREADS_PER_BLOCK) {
//bool activeNodesPerIndividual[nrOfIndividuals][N];
bool *dyn_activeNodesPerIndividual = new bool[nrOfIndividuals*N];
for (int i=0; i<nrOfIndividuals; i++) {
for (int j=0; j<N; j++) {
int index = N * i + j;
dyn_activeNodesPerIndividual[index] = false;
}
for (int j=0; j<toFind; j++) {
int index = N * i + population[i][j];
dyn_activeNodesPerIndividual[index] = true;
}
}
int active [nrOfIndividuals];
vector<int> changedIndividuals;
for (int i=0; i<nrOfIndividuals; i++) {
active[i] = toFind;
changedIndividuals.push_back(i);
}
int step_counter = 0;
while (step_counter < STEPS_MAX && changedIndividuals.size() > 0) {
//cout << "Step: " << step_counter << " / " << STEPS_MAX << endl;
int nrOfChangedIndividuals = changedIndividuals.size();
cout << "nrOfChangedIndividuals " << nrOfChangedIndividuals << endl;
F_TIME_START();
InfluenceSpreadPopulationStep (dyn_activeNodesPerIndividual, inf_values, inf_col_ind, inf_row_ptr, N, nrOfChangedIndividuals, inf_values_size, INFLUENCE_THRESHOLD, changedIndividuals);
F_TIME_END("host functions");
changedIndividuals.clear();
int curr_active;
for (int i=0; i<nrOfIndividuals; i++) {
curr_active = 0;
for (int j=0; j<N; j++) {
int index = N * i + j;
if (dyn_activeNodesPerIndividual[index]) {
curr_active++;
}
}
if (curr_active != active[i]) {
changedIndividuals.push_back(i);
}
active[i] = curr_active;
}
step_counter++;
}
for (int i = 0; i < nrOfIndividuals; i++) {
int individualFitness = 0;
for (int j = 0; j < N; j++) {
int index = N * i + j;
if (dyn_activeNodesPerIndividual[index]) {
individualFitness++;
//cout << "Activated " << j << endl;
}
}
//cout << "individualFitness: " << individualFitness << endl;
//cout << "toFind: " << toFind << endl;
// acceptable `error`
/*if (individualFitness-toFind < 0) {
cout << "# Crossover/mutation overlapping" << endl; // can happen because of random crossover and mutation
//coutIndividual(population, i);
}*/
//cout << "fitness Indiv: " << i << ": " << individualFitness-toFind << endl;
fitness.push_back(individualFitness-toFind);
}
}
void performPopulationSelection (vector<vector<int>>& population, int& nrOfIndividuals, int N, int inf_values_size, float& INFLUENCE_THRESHOLD, int& groupSize, int& STEPS_MAX, vector<float>& inf_values, vector<float>& inf_col_ind, vector<float>& inf_row_ptr, int& toFind, int& max_fitness_value, vector<int>& max_fitness_individual, int THREADS_PER_BLOCK) {
vector<int> fitness;
F_TIME_START();
setPopulationFitness(population, nrOfIndividuals, N, inf_values_size, INFLUENCE_THRESHOLD, STEPS_MAX, inf_values, inf_col_ind, inf_row_ptr, toFind, fitness, THREADS_PER_BLOCK);
F_TIME_END("selection - fitness count");
F_TIME_START();
vector<vector<int>> newPopulation;
while (newPopulation.size() != population.size()) {
vector<int> newGroup;
bool alreadyAdded[nrOfIndividuals];
for (int i=0; i<nrOfIndividuals; i++) {
alreadyAdded[i] = false;
}
for (int j=0; j<groupSize; j++) {
int randIndiv = rand() % nrOfIndividuals;
while (alreadyAdded[randIndiv]) {
randIndiv = rand() % nrOfIndividuals;
}
newGroup.push_back(randIndiv);
}
int curr_best_fitness = -1;
int curr_best_id = -1;
int currentFitness = -1;
for (int j=0; j<newGroup.size(); j++) {
currentFitness = fitness[newGroup[j]];
if (currentFitness > curr_best_fitness) {
curr_best_fitness = currentFitness;
curr_best_id = j;
}
}
newPopulation.push_back(population[newGroup[curr_best_id]]);
if (curr_best_fitness > max_fitness_value) {
max_fitness_individual = population[newGroup[curr_best_id]];
max_fitness_value = curr_best_fitness;
}
}
population = newPopulation;
F_TIME_END("selection - population swapping");
}
// TODO performCrossover on DEVICE (nrOfIndividuals/2 threads (from 0 to nr/2 - 1), ids: id*2, id*2+1
void performCrossover (vector<vector<int>>& population, int& nrOfIndividuals, float& crossover_ratio, int& toFind) {
float split_ratio = 0.5;
float split_point = split_ratio*toFind;
int id_first = -1;
int id_second = -1;
for (int i=0; i<nrOfIndividuals; i++) {
int cross = rand() % 100;
if (cross < crossover_ratio * 100) {
if (id_first == -1) {
id_first = i;
} else {
id_second = i;
}
}
if (id_second != -1) {
for (int j=0; j<split_point; j++) {
float temp = population[id_first][j];
population[id_first][j] = population[id_second][j];
population[id_second][j] = temp;
}
id_first = -1;
id_second = -1;
}
} // allows to node doubling (fitness = -1 can happen)
}
// TODO performMutation on DEVICE
void performMutation (vector<vector<int>>& population, int& nrOfIndividuals, float& mutation_ratio, float& mutation_potency, int& toFind, int N) {
for (int i=0; i<nrOfIndividuals; i++) {
int mutation = rand() % 100;
if (mutation < mutation_ratio * 100) {
for (int j=0; j<mutation_potency*toFind; j++) {
population[i][rand() % toFind] = rand() % N;
}
}
} // allows to node doubling (fitness = -1 can happen)
}
bool anyLimitReached(int resultBufferSize, float resultMinDiff, vector<int> &resultsBuffer, int generation, int generationsLimit, float timeLimit, int COMPUTATION_START_TIME, int result, int resultLimit) {
int now = duration_cast<milliseconds>(system_clock::now().time_since_epoch()).count();
float diff = (now - COMPUTATION_START_TIME) / 1000.0;
bool anyLimit =
(resultMinDiff > 0 && generation > resultBufferSize && result < resultsBuffer[0] * (1 + resultMinDiff))
|| (generationsLimit > 0 && generation >= generationsLimit)
|| (resultLimit > 0 && result >= resultLimit)
|| (timeLimit > 0 && diff >= timeLimit);
if (generation > 0) {
resultsBuffer.push_back(result);
}
if (generation > resultBufferSize) {
resultsBuffer.erase(resultsBuffer.begin());
//cout << endl << "Current resultsBuffer[0]: " << resultsBuffer[0] << endl;
}
return anyLimit;
}
vector<string> getFileNames (string path) {
DIR *pDIR;
struct dirent *entry;
vector<string> fileNames;
if (pDIR=opendir(path.c_str())) {
while (entry = readdir(pDIR)) {
if (strcmp(entry->d_name, ".") != 0 && strcmp(entry->d_name, "..") != 0) {
fileNames.push_back(entry->d_name);
}
}
closedir(pDIR);
}
return fileNames;
}
/* pearson, spearman */
float mean (vector<float> values) {
float sum = 0;
int size = values.size();
for (int i = 0; i < size; i++) {
sum += values[i];
}
return sum / size;
}
float pearson_numerator (vector<float> A, vector<float> B, float meanA, float meanB) {
float numerator = 0;
for (int i = 0; i < A.size(); i++) {
numerator += (A[i] - meanA) * (B[i] - meanB);
}
return numerator;
}
float pearson_denominator (vector<float> A, vector<float> B, float meanA, float meanB) {
float denominator1;
float denominator1_sum = 0;
float denominator2;
float denominator2_sum = 0;
for (int i = 0; i < A.size(); i++) {
denominator1_sum += pow(A[i] - meanA, 2);
}
for (int i = 0; i < B.size(); i++) {
denominator2_sum += pow(B[i] - meanB, 2);
}
denominator1 = pow(denominator1_sum, 0.5);
denominator2 = pow(denominator2_sum, 0.5);
if (denominator1 == 0 || denominator2 == 0)
cout << endl << endl << "##### ERROR: Denominator equal to 0 - probable cause: all result values are equal" << endl << endl;
return denominator1 * denominator2;
}
float pearson (vector<float> A, vector<float> B) {
if (A.size() != B.size()) {
cout << "ERROR - wrong vector lengths" << endl;
return -1;
}
float meanA = mean(A);
float meanB = mean(B);
float numerator = pearson_numerator(A, B, meanA, meanB);
float denominator = pearson_denominator(A, B, meanA, meanB);
return numerator / denominator;
}
vector<float> toRank (vector<float> A) {
vector<float> sorted = A;
sort(sorted.begin(), sorted.end());
vector<float> rank;
for (int i = 0; i < A.size(); i++) {
vector<int> positions;
for (int j = 0; j < A.size(); j++) {
if (sorted[j] == A[i]) {
positions.push_back(j);
}
}
float sum = 0;
float avg;
for (int j = 0; j < positions.size(); j++) {
sum += positions[j] + 1;
}
avg = sum / positions.size();
rank.push_back(avg);
//rank.push_back(positions[positions.size()-1] + 1); //libreoffice calc rank
}
/*
cout << "Ranking: " << endl;
for (int i = 0; i < rank.size(); i++) {
cout << rank[i] << ", ";
}
cout << endl << endl;
*/
return rank;
}
float spearman (vector<float> A, vector<float> B) {
vector<float> A_ranked = toRank(A);
vector<float> B_ranked = toRank(B);
return pearson(A_ranked, B_ranked);
}
int main (int argc, char* argv[]) {
srand (time(NULL));
coutGPUStatus();
string _EXPERIMENT_ID = argv[1];
int tests = 100;
float timeLimit = 6; //seconds
int generationsLimit = 0; //5;
int resultLimit = 0; //32;
int resultBufferSize = 10;
float resultMinDiff = 0; //0.01;
bool saveResults = true;
bool saveResultsCorrelation = true;
float INFLUENCE_THRESHOLD = 0.5;
int N_MAX = 1000;
int STEPS_MAX = 10000;
int TO_FIND_PERCENTAGE = 5;
int THREADS_PER_BLOCK = 1024;
/* Parameters */
//int groupSize = 20; // 10, 20, 30 // 2, 5, 10, 20, 50
//int nrOfIndividuals = (int)ceil(N/10.0); // N/20, N/10, N/5 // 100, 500 1k, 2k, 10k
//float crossover_ratio = 0.7; // 0.5, 0.7, 0.9 // 0.1, 0.3, 0.5, 0.7, 0.9
//float mutation_potency = 0.01; // 0.001, 0.01, 0.1 // 0.01, 0.02, 0.05, 0.1, 0.2
//float mutation_ratio = 0.9; // 0.75, 0.9, 0.95, // 0.1, 0.3, 0.5, 0.7, 0.9
vector<int> a_groupSize {10, 20, 30}; // 10, 20, 30
vector<int> a_nrOfIndividuals {12, 10, 8}; // N/12, N/10, N/8
vector<float> a_crossover_ratio {0.6, 0.7, 0.8}; // 0.6, 0.7, 0.8
vector<float> a_mutation_potency {0.001, 0.01, 0.1}; // 0.001, 0.01, 0.1
vector<float> a_mutation_ratio {0.7, 0.8, 0.9}; // 0.7, 0.8, 0.9
int parameters_sets = a_groupSize.size() * a_nrOfIndividuals.size() * a_crossover_ratio.size() * a_mutation_potency.size() * a_mutation_ratio.size();
vector<string> datasets = getFileNames("./experiments_" + _EXPERIMENT_ID);
/* DEBUG */
int debug_nrOfIndividuals;
bool debug = true;
if (debug) {
tests = 10;
N_MAX = 1000;
THREADS_PER_BLOCK = 1024;
debug_nrOfIndividuals = -1; // -1 - the same as if it wasn't a debug mode (so devides N by a_nrOfIndividuals to get indivnr)
// tests: 10, debug_nrOfIndividuals: -1, generationsLimit: 1, THREADS_PER_BLOCK: 1024, default parameters, facebook
/* 100: 7 in 1ms, 500: 46 in 10ms, 1000: 88 in 53ms */
timeLimit = 0;
generationsLimit = 5; // 5 - 80s
resultLimit = 0;
resultMinDiff = 0;
saveResults = true;//false;
saveResultsCorrelation = true;//false;
a_groupSize = {20};
a_nrOfIndividuals = {8};
a_crossover_ratio = {0.7};
a_mutation_potency = {0.01};
a_mutation_ratio = {0.9};
parameters_sets = a_groupSize.size() * a_nrOfIndividuals.size() * a_crossover_ratio.size() * a_mutation_potency.size() * a_mutation_ratio.size();
//datasets = {"facebook-46952"};
//datasets = {"BA-1000-1-3.csv"};
datasets = {"ER-1000-0.05-10.csv"};
//datasets = getFileNames("./experiments_" + _EXPERIMENT_ID);
}
/*
N = 1000
INDIVIDUALS = 1000
THREADS_PER_BLOCK = 192
1 individuals - 0.056s
10 individuals - 0.081s
100 individuals - 0.265s
1000 individuals - 2.483s
THREADS_PER_BLOCK = 512
1000 individuals - 2.423s
THREADS_PER_BLOCK = 1024
1000 individuals - 2.481s
N = max (~47k for facebook)
THREADS_PER_BLOCK = 512
100 individuals - 5.08s
*/
vector<vector<float>> results;
for (int i=0; i<datasets.size(); i++) {
vector<float> row(parameters_sets, -1);
results.push_back(row);
}
for (int file_id=0; file_id<datasets.size(); file_id++) {
int dataset_id = file_id; //TODO to refactor
string dataset_name = datasets[file_id];
stringstream ssname(dataset_name);
string token;
getline(ssname, token, '-');
getline(ssname, token, '-');
int maxSize = stoi(token);
int N = min(N_MAX, maxSize);
int toFind = (int)ceil(float(TO_FIND_PERCENTAGE * N) / 100.0);
// using ofstream constructors.
std::ofstream outfile("results_" + dataset_name + "_" + _EXPERIMENT_ID + "_" + ".xls");
if (saveResults) {
outfile << "<?xml version='1.0'?>" << std::endl;
outfile << "<Workbook xmlns='urn:schemas-microsoft-com:office:spreadsheet'" << std::endl;
outfile << " xmlns:o='urn:schemas-microsoft-com:office:office'" << std::endl;
outfile << " xmlns:x='urn:schemas-microsoft-com:office:excel'" << std::endl;
outfile << " xmlns:ss='urn:schemas-microsoft-com:office:spreadsheet'" << std::endl;
outfile << " xmlns:html='http://www.w3.org/TR/REC-html40'>" << std::endl;
outfile << " <Worksheet ss:Name='Sheet1'>" << std::endl;
outfile << " <Table>" << std::endl;
outfile << " <Row>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>Dataset</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>Test nr</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>groupSize</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>nrOfIndividuals</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>crossover_ratio</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>mutation_potency</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>mutation_ratio</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>Generations</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>Result</Data></Cell>" << std::endl;
outfile << " </Row>" << std::endl;
}
vector <float> inf_col_ind;
vector <float> inf_row_ptr;
vector <float> inf_values;
defineInfluenceArrayAndVectors(dataset_name, N, inf_values, inf_col_ind, inf_row_ptr, _EXPERIMENT_ID);
int inf_values_size = inf_values.size();
int parameters_set = 1;
for_each(a_groupSize.begin(), a_groupSize.end(), [&] (int groupSize) {
for_each(a_nrOfIndividuals.begin(), a_nrOfIndividuals.end(), [&] (int nrOfIndividualsRaw) {
int nrOfIndividuals = (int)ceil(N/nrOfIndividualsRaw);
if (debug && debug_nrOfIndividuals != -1) {
nrOfIndividuals = debug_nrOfIndividuals;
}
for_each(a_crossover_ratio.begin(), a_crossover_ratio.end(), [&] (float crossover_ratio) {
for_each(a_mutation_potency.begin(), a_mutation_potency.end(), [&] (float mutation_potency) {
for_each(a_mutation_ratio.begin(), a_mutation_ratio.end(), [&] (float mutation_ratio) {
float testsResultsSum = 0;
float testsGenerationsSum = 0;
float testsTimeSum = 0;
for (int test = 0; test < tests; test++) {
vector <int> max_fitness_individual;
vector <vector<int>> population;
int max_fitness_value = -1;
int progressBarLength = 10;
int generation = 0;
vector<int> resultsBuffer;
createPopulation(nrOfIndividuals, N, toFind, population);
//createPopulationSample(nrOfIndividuals, N, toFind, population);
//coutPopulation(population);
int COMPUTATION_START_TIME = duration_cast<milliseconds>(system_clock::now().time_since_epoch()).count();
while (!anyLimitReached(resultBufferSize, resultMinDiff, resultsBuffer, generation, generationsLimit, timeLimit, COMPUTATION_START_TIME, max_fitness_value, resultLimit)) {
//coutGPUStatus();
F_TIME_START();
performPopulationSelection(population, nrOfIndividuals, N, inf_values_size, INFLUENCE_THRESHOLD, groupSize, STEPS_MAX, inf_values, inf_col_ind, inf_row_ptr, toFind, max_fitness_value, max_fitness_individual, THREADS_PER_BLOCK);
F_TIME_END("selection");
F_TIME_START();
performCrossover(population, nrOfIndividuals, crossover_ratio, toFind);
F_TIME_END("crossover");
F_TIME_START();
performMutation(population, nrOfIndividuals, mutation_ratio, mutation_potency, toFind, N);
F_TIME_END("mutation");
//coutResult(generation, max_fitness_value);
generation++;
}
int COMPUTATION_END_TIME = duration_cast<milliseconds>(system_clock::now().time_since_epoch()).count();
int COMPUTATION_DURATION = COMPUTATION_END_TIME - COMPUTATION_START_TIME;
cout << endl << "[FINISHED] test: " << test+1 << "/" << tests
<< " for parameters set nr: " << parameters_set << "/" << parameters_sets
<< " for dataset_id: " << dataset_id+1 << "/" << datasets.size()
<< " in: " << COMPUTATION_DURATION / 1000.0 << "s";
cout << endl;
coutGPUStatus();
cout << endl;
if (saveResults) {
outfile << " <Row>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(parameters_set) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(test+1) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(groupSize) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(nrOfIndividuals) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(crossover_ratio) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(mutation_potency) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(mutation_ratio) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(generation) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(max_fitness_value) + "</Data></Cell>" << std::endl;
outfile << " </Row>" << std::endl;
}
//cout << endl << "result " << test+1 << ": " << max_fitness_value << endl;
testsResultsSum += max_fitness_value;
testsGenerationsSum += generation;
testsTimeSum += COMPUTATION_DURATION;
/*cout << "Best individual found: " << endl;
for (int i=0; i<max_fitness_individual.size(); i++) {
cout << max_fitness_individual[i] << ", ";
}*/
//cout << endl << endl << "This group can activate " << max_fitness_value << " others";
//cout << endl << "Time elapsed: " << (time2 - COMPUTATION_START_TIME) / 1000.0 << "s" << endl;
} // TEST
float finalResult = std::round(testsResultsSum / tests);
float finalGenerations = std::round(testsGenerationsSum / tests);
float finalTime = std::round(testsTimeSum / tests);
cout << endl << "Final result avg: " << finalResult << " in avg " << finalTime / 1000.0 << "s" << endl;
results[file_id][parameters_set-1] = finalResult;
if (saveResults) {
outfile << " <Row>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(parameters_set) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>AVG </Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(groupSize) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(nrOfIndividuals) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(crossover_ratio) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(mutation_potency) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(mutation_ratio) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(finalGenerations) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(finalResult) + "</Data></Cell>" << std::endl;
outfile << " </Row>" << std::endl;
}
parameters_set++;
});
});
});
});
});
if (saveResults) {
outfile << " </Table>" << std::endl;
outfile << " </Worksheet>" << std::endl;
outfile << "</Workbook>" << std::endl;
}
outfile.close();
}
cout << endl << endl << "*** RESULTS ***" << endl;
for (int i=0; i<datasets.size(); i++) {
for (int j=0; j<parameters_sets; j++) {
cout << results[i][j] << ", ";
}
cout << endl;
}
if (saveResultsCorrelation) {
// using ofstream constructors.
std::ofstream outfile("results_correlation_" + _EXPERIMENT_ID + "_.xls");
outfile << "<?xml version='1.0'?>" << std::endl;
outfile << "<Workbook xmlns='urn:schemas-microsoft-com:office:spreadsheet'" << std::endl;
outfile << " xmlns:o='urn:schemas-microsoft-com:office:office'" << std::endl;
outfile << " xmlns:x='urn:schemas-microsoft-com:office:excel'" << std::endl;
outfile << " xmlns:ss='urn:schemas-microsoft-com:office:spreadsheet'" << std::endl;
outfile << " xmlns:html='http://www.w3.org/TR/REC-html40'>" << std::endl;
outfile << " <Worksheet ss:Name='Sheet1'>" << std::endl;
outfile << " <Table>" << std::endl;
outfile << " <Row>" << std::endl;
outfile << " <Cell></Cell>" << std::endl;
for (int i=0; i<datasets.size(); i++) {
outfile << " <Cell><Data ss:Type='String'>" + datasets[i] + "</Data></Cell>" << std::endl;
}
outfile << " </Row>" << std::endl;
for (int i=0; i<datasets.size(); i++) {
outfile << " <Row>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>" + datasets[i] + "</Data></Cell>" << std::endl;
for (int j=0; j<datasets.size(); j++) {
if (j > i) {
outfile << " <Cell><Data ss:Type='Number'>" + to_string(pearson(results[i], results[j])) + "</Data></Cell>" << std::endl;
} else {
outfile << " <Cell></Cell>" << std::endl;
}
}
outfile << " </Row>" << std::endl;
}
outfile << " <Row></Row>" << std::endl;
outfile << " <Row></Row>" << std::endl;
outfile << " <Row></Row>" << std::endl;
outfile << " <Row>" << std::endl;
outfile << " <Cell></Cell>" << std::endl;
for (int i=0; i<datasets.size(); i++) {
outfile << " <Cell><Data ss:Type='String'>" + datasets[i] + "</Data></Cell>" << std::endl;
}
outfile << " </Row>" << std::endl;
for (int i=0; i<datasets.size(); i++) {
outfile << " <Row>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>" + datasets[i] + "</Data></Cell>" << std::endl;
for (int j=0; j<datasets.size(); j++) {
if (j > i) {
outfile << " <Cell><Data ss:Type='Number'>" + to_string(spearman(results[i], results[j])) + "</Data></Cell>" << std::endl;
} else {
outfile << " <Cell></Cell>" << std::endl;
}
}
outfile << " </Row>" << std::endl;
}
outfile << " </Table>" << std::endl;
outfile << " </Worksheet>" << std::endl;
outfile << "</Workbook>" << std::endl;
outfile.close();
}
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <algorithm>
#include <cmath>
#include <cstdio>
#include <fstream>
#include <iostream>
#include <sstream>
#include <string>
#include <vector>
#include <sys/time.h>
#include <chrono>
#include <dirent.h>
using namespace std::chrono;
using namespace std;
vector<int> G_timestamps;
int getCurrentTime () {
return duration_cast<milliseconds>(system_clock::now().time_since_epoch()).count();
}
void F_TIME_START () {
G_timestamps.push_back(getCurrentTime());
}
void F_TIME_END (string measuredName) {
int start = G_timestamps.back();
int end = getCurrentTime();
float diff = (end - start) / 1000.0;
G_timestamps.pop_back();
cout << endl << "## [" << measuredName << "]: " << diff << "s" << endl << endl;
}
void coutGPUStatus () {
size_t freem, totalm;
float free_m, total_m, used_m;
cudaMemGetInfo((size_t*)&freem, (size_t*)&totalm);
free_m = (size_t) freem / 1048576.0;
total_m = (size_t) totalm / 1048576.0;
used_m = total_m - free_m;
printf ( "## Total: %f MB. Used %f MB. Free: %f MB. \n", total_m, used_m, free_m);
}
void coutResult(int& generation, int& max_fitness_value) {
cout << "Generation " << generation << ", currently best individual can activate " << max_fitness_value << " others" << endl;
}
void coutPopulation (vector <vector<int>>& population) {
cout << "Population:";
for (int i=0; i<population.size(); i++) {
cout << "\nIndiv: " << i << ": ";
for (int j=0; j<population[i].size(); j++) {
if (population[i][j] < 10) {
cout << population[i][j] << ", ";
}
else if (population[i][j] < 100) {
cout << population[i][j] << ", ";
}
else if (population[i][j] < 1000) {
cout << population[i][j] << ", ";
}
else if (population[i][j] < 10000) {
cout << population[i][j] << ", ";
}
else {
cout << population[i][j] << ",";
}
}
}
cout << "\n\n";
}
void coutIndividual (vector <vector<int>>& population, int i) {
cout << "Individual " << i << ":";
for (int j=0; j<population[i].size(); j++) {
if (population[i][j] < 10) {
cout << population[i][j] << ", ";
}
else if (population[i][j] < 100) {
cout << population[i][j] << ", ";
}
else if (population[i][j] < 1000) {
cout << population[i][j] << ", ";
}
else if (population[i][j] < 10000) {
cout << population[i][j] << ", ";
}
else {
cout << population[i][j] << ",";
}
}
cout << "\n\n";
}
float getInfluenceValue (int N, int inf_values_size, vector<float>& inf_values, vector<float>& inf_col_ind, vector<float>& inf_row_ptr, int x, int y) {
float infValue = 0;
int min = inf_row_ptr[x];
int max = x == N-1 ? inf_values_size-1 : inf_row_ptr[x+1]; //inf_values_size-1
for (int i=min; i<max; i++) {
if (inf_col_ind[i] == y) {
infValue = inf_values[i];
break;
}
}
return infValue;
}
void InfluenceSpreadPopulationStep (bool *dyn_activeNodesPerIndividual, vector<float>& inf_values, vector<float>& inf_col_ind, vector<float>& inf_row_ptr, int N, int nrOfChangedIndividuals, int inf_values_size, float INFLUENCE_THRESHOLD, vector<int>& changedIndividuals) {
for (int indiv_id = 0; indiv_id < nrOfChangedIndividuals; indiv_id++) {
for (int node_id = 0; node_id < N; node_id++) {
int indiv_index = changedIndividuals[indiv_id];
float infValue = 0; // total value of influence on the node
for (int i=0; i<N; i++) {
if (dyn_activeNodesPerIndividual[indiv_index * N + i] && node_id != i) { // if i-th element is active and is not the node
float result = getInfluenceValue(N, inf_values_size, inf_values, inf_col_ind, inf_row_ptr, i, node_id);
infValue += result; // add i-th element influence on the node
//printf("Influence %d on %d is: %f\n", i, node_id, result);
//printf("\ninfValue: %f, id: %d", infValue, id);
}
}
//printf("\ninfValue: %f, id: %d", infValue, id);
if (infValue >= INFLUENCE_THRESHOLD) { // if total influence on the node is greater than or equal to the INFLUENCE_THRESHOLD value
dyn_activeNodesPerIndividual[indiv_index * N + node_id] = true; // activate the node
}
}
}
}
vector <vector<float>> readData (string dataset_name, int N, string _EXPERIMENT_ID) {
vector <vector<float>> influence;
// initialization of the influence vector
for (int i=0; i<N; i++) {
cout << endl << i << " out of " << N << endl;
vector<float> row(N, 0);
influence.push_back(row);
if ((i + 1) * N % (N * N / 10) == 0) {
cout << "[Initialization of the influence matrix]: " << float((i + 1) * N) / (N * N) * 100 << "%" << endl;
}
}
// total number of interactions received by every node
vector<float> received(N, 0);
ifstream infile("./experiments_" + _EXPERIMENT_ID + "/" + dataset_name);
string line;
int _csv_id_hack = -1;
if (dataset_name.find(".csv") != std::string::npos) {
_csv_id_hack = 0;
}
if (infile.good()) {
int line_nr = 0;
while (getline(infile, line)) {
cout << "Reading raw data file, line nr: " << line_nr << endl;
//cout << line << endl;
istringstream iss(line);
int a, b;
if (!(iss >> a >> b)) { cout << "ERROR" << endl; break; } // error
if (a != b && a + _csv_id_hack < N && b + _csv_id_hack < N) {
influence[a + _csv_id_hack][b + _csv_id_hack] += 1; // temp inf_values, calculating the total number of iteractions from "i" to "j"
received [b + _csv_id_hack] += 1;
//cout << "message from " << a + _csv_id_hack << " to " << b + _csv_id_hack << endl;
}
line_nr++;
}
infile.close();
cout << "File reading finished successfully." << endl;
ofstream outfile ("./experiments-counted/" + dataset_name + "_influenceCounted_" + to_string(N));
if (outfile.good()) {
// Influence value calculated as the ratio of iteractions from "i" node to "j" node, to the total number of iteractions to the "j" node.
for (int i=0; i<N; i++) {
for (int j=0; j<N; j++) {
//cout << "Influence values calculations, step: " << i*N+(j+1) << "/" << N*N << endl;
if (i == j) {
outfile << i << " " << j << " " << -1 << "\n";
influence[i][j] = -1;
} else if (influence[i][j] > 0) {
if (received[j] != 0) {
influence[i][j] = influence[i][j] / received[j];
} else if (influence[i][j] != 0) {
cout << "Received array error";
}
/*cout << i << "'s influence on " << j << " equals: " << influence[i][j] << endl;*/
outfile << i << " " << j << " " << influence[i][j] << "\n";
} else {
influence[i][j] = 0;
}
}
}
cout << "Compressed file saved successfully." << endl;
outfile.close();
} else {
throw std::invalid_argument("readData - File " + dataset_name + " not saved.");
}
} else {
throw std::invalid_argument("readData - File " + dataset_name + " not found.");
}
return influence;
}
void defineInfluenceArrayAndVectors (string dataset_name, int N, vector<float>& inf_values, vector<float>& inf_col_ind, vector<float>& inf_row_ptr, string _EXPERIMENT_ID) {
//cout << "File reading started." << endl;
ifstream infile("./experiments-counted/" + dataset_name + "_influenceCounted_" + to_string(N));
if (infile.good()) { // reading the already calculated influence values
int line_nr = 0;
string line;
float last_a = -1;
while (getline(infile, line)) {
cout << "Reading influence file, line nr: " << line_nr << endl;
istringstream iss(line);
float a, b, c;
if (!(iss >> a >> b >> c)) { break; } // error
if (c != 0) {
if (a != last_a) {
inf_row_ptr.push_back(inf_values.size());
//cout << "add row ptr: " << inf_values.size() << endl;
last_a = a;
}
inf_values.push_back(c);
//cout << "add value: " << c << endl;
inf_col_ind.push_back(b);
//cout << "add col ind: " << b << endl;
}
line_nr++;
}
infile.close();
} else { // calculating influnce values
infile.close();
vector <vector<float>> influence = readData(dataset_name, N, _EXPERIMENT_ID);
// inf_values, inf_col_ind, inf_row_ptr creation, based on the influence array
for (int i=0; i<N; i++) {
bool added = false;
for (int j=0; j<N; j++) {
//cout << "Influence of " << i << " on " << j << " is equal to: " << influence[i][j] << endl;
if (influence[i][j] != 0) {
if (!added) {
inf_row_ptr.push_back(inf_values.size());
//cout << "add row ptr: " << inf_values.size() << endl;
added = true;
}
inf_values.push_back(influence[i][j]);
//cout << "add value: " << influence[i][j] << endl;
inf_col_ind.push_back(j);
//cout << "add col ind: " << j << endl;
}
}
if (!added) {
//inf_row_ptr.push_back(-1);
}
}
/*cout << "\n\n size of influence array: " << sizeof(influence) + sizeof(float) * influence.capacity() * influence.capacity();
cout << "\n\n Total size of vectors: "
<< sizeof(inf_values) + sizeof(float) * inf_values.capacity()
+ sizeof(inf_col_ind) + sizeof(float) * inf_col_ind.capacity()
+ sizeof(inf_row_ptr) + sizeof(float) * inf_row_ptr.capacity() << "\n\n";*/
}
}
void createPopulation (int nrOfIndividuals, int N, int toFind, vector <vector<int>>& population) {
// creating random individuals within population
for (int i = 0; i<nrOfIndividuals; i++) {
vector<int> row;
population.push_back(row);
cout << "Creating individual " << i << " of " << nrOfIndividuals << endl;
for (int j = 0; j<toFind; j++) {
int rand_id = rand() % N;
bool alreadyAdded = true;
while (alreadyAdded) {
alreadyAdded = false;
for (int k=0; k<population[i].size(); k++) {
if (population[i][k] == rand_id) {
alreadyAdded = true;
rand_id = rand() % N;
}
}
}
//cout << "pushing: " << rand_id << endl;
population[i].push_back(rand_id);
}
}
}
void createPopulationSample (int nrOfIndividuals, int N, int toFind, vector <vector<int>>& population) {
// creating one individual - used as a sample e.g. for GPU vs CPU tests
vector<int> row;
population.push_back(row);
for (int x = 0; x<toFind; x++) {
population[0].push_back(x);
}
}
void setPopulationFitness (vector<vector<int>>& population, int nrOfIndividuals, int N, int inf_values_size, float& INFLUENCE_THRESHOLD, int STEPS_MAX, vector<float>& inf_values, vector<float>& inf_col_ind, vector<float>& inf_row_ptr, int toFind, vector<int>& fitness, int THREADS_PER_BLOCK) {
//bool activeNodesPerIndividual[nrOfIndividuals][N];
bool *dyn_activeNodesPerIndividual = new bool[nrOfIndividuals*N];
for (int i=0; i<nrOfIndividuals; i++) {
for (int j=0; j<N; j++) {
int index = N * i + j;
dyn_activeNodesPerIndividual[index] = false;
}
for (int j=0; j<toFind; j++) {
int index = N * i + population[i][j];
dyn_activeNodesPerIndividual[index] = true;
}
}
int active [nrOfIndividuals];
vector<int> changedIndividuals;
for (int i=0; i<nrOfIndividuals; i++) {
active[i] = toFind;
changedIndividuals.push_back(i);
}
int step_counter = 0;
while (step_counter < STEPS_MAX && changedIndividuals.size() > 0) {
//cout << "Step: " << step_counter << " / " << STEPS_MAX << endl;
int nrOfChangedIndividuals = changedIndividuals.size();
cout << "nrOfChangedIndividuals " << nrOfChangedIndividuals << endl;
F_TIME_START();
InfluenceSpreadPopulationStep (dyn_activeNodesPerIndividual, inf_values, inf_col_ind, inf_row_ptr, N, nrOfChangedIndividuals, inf_values_size, INFLUENCE_THRESHOLD, changedIndividuals);
F_TIME_END("host functions");
changedIndividuals.clear();
int curr_active;
for (int i=0; i<nrOfIndividuals; i++) {
curr_active = 0;
for (int j=0; j<N; j++) {
int index = N * i + j;
if (dyn_activeNodesPerIndividual[index]) {
curr_active++;
}
}
if (curr_active != active[i]) {
changedIndividuals.push_back(i);
}
active[i] = curr_active;
}
step_counter++;
}
for (int i = 0; i < nrOfIndividuals; i++) {
int individualFitness = 0;
for (int j = 0; j < N; j++) {
int index = N * i + j;
if (dyn_activeNodesPerIndividual[index]) {
individualFitness++;
//cout << "Activated " << j << endl;
}
}
//cout << "individualFitness: " << individualFitness << endl;
//cout << "toFind: " << toFind << endl;
// acceptable `error`
/*if (individualFitness-toFind < 0) {
cout << "# Crossover/mutation overlapping" << endl; // can happen because of random crossover and mutation
//coutIndividual(population, i);
}*/
//cout << "fitness Indiv: " << i << ": " << individualFitness-toFind << endl;
fitness.push_back(individualFitness-toFind);
}
}
void performPopulationSelection (vector<vector<int>>& population, int& nrOfIndividuals, int N, int inf_values_size, float& INFLUENCE_THRESHOLD, int& groupSize, int& STEPS_MAX, vector<float>& inf_values, vector<float>& inf_col_ind, vector<float>& inf_row_ptr, int& toFind, int& max_fitness_value, vector<int>& max_fitness_individual, int THREADS_PER_BLOCK) {
vector<int> fitness;
F_TIME_START();
setPopulationFitness(population, nrOfIndividuals, N, inf_values_size, INFLUENCE_THRESHOLD, STEPS_MAX, inf_values, inf_col_ind, inf_row_ptr, toFind, fitness, THREADS_PER_BLOCK);
F_TIME_END("selection - fitness count");
F_TIME_START();
vector<vector<int>> newPopulation;
while (newPopulation.size() != population.size()) {
vector<int> newGroup;
bool alreadyAdded[nrOfIndividuals];
for (int i=0; i<nrOfIndividuals; i++) {
alreadyAdded[i] = false;
}
for (int j=0; j<groupSize; j++) {
int randIndiv = rand() % nrOfIndividuals;
while (alreadyAdded[randIndiv]) {
randIndiv = rand() % nrOfIndividuals;
}
newGroup.push_back(randIndiv);
}
int curr_best_fitness = -1;
int curr_best_id = -1;
int currentFitness = -1;
for (int j=0; j<newGroup.size(); j++) {
currentFitness = fitness[newGroup[j]];
if (currentFitness > curr_best_fitness) {
curr_best_fitness = currentFitness;
curr_best_id = j;
}
}
newPopulation.push_back(population[newGroup[curr_best_id]]);
if (curr_best_fitness > max_fitness_value) {
max_fitness_individual = population[newGroup[curr_best_id]];
max_fitness_value = curr_best_fitness;
}
}
population = newPopulation;
F_TIME_END("selection - population swapping");
}
// TODO performCrossover on DEVICE (nrOfIndividuals/2 threads (from 0 to nr/2 - 1), ids: id*2, id*2+1
void performCrossover (vector<vector<int>>& population, int& nrOfIndividuals, float& crossover_ratio, int& toFind) {
float split_ratio = 0.5;
float split_point = split_ratio*toFind;
int id_first = -1;
int id_second = -1;
for (int i=0; i<nrOfIndividuals; i++) {
int cross = rand() % 100;
if (cross < crossover_ratio * 100) {
if (id_first == -1) {
id_first = i;
} else {
id_second = i;
}
}
if (id_second != -1) {
for (int j=0; j<split_point; j++) {
float temp = population[id_first][j];
population[id_first][j] = population[id_second][j];
population[id_second][j] = temp;
}
id_first = -1;
id_second = -1;
}
} // allows to node doubling (fitness = -1 can happen)
}
// TODO performMutation on DEVICE
void performMutation (vector<vector<int>>& population, int& nrOfIndividuals, float& mutation_ratio, float& mutation_potency, int& toFind, int N) {
for (int i=0; i<nrOfIndividuals; i++) {
int mutation = rand() % 100;
if (mutation < mutation_ratio * 100) {
for (int j=0; j<mutation_potency*toFind; j++) {
population[i][rand() % toFind] = rand() % N;
}
}
} // allows to node doubling (fitness = -1 can happen)
}
bool anyLimitReached(int resultBufferSize, float resultMinDiff, vector<int> &resultsBuffer, int generation, int generationsLimit, float timeLimit, int COMPUTATION_START_TIME, int result, int resultLimit) {
int now = duration_cast<milliseconds>(system_clock::now().time_since_epoch()).count();
float diff = (now - COMPUTATION_START_TIME) / 1000.0;
bool anyLimit =
(resultMinDiff > 0 && generation > resultBufferSize && result < resultsBuffer[0] * (1 + resultMinDiff))
|| (generationsLimit > 0 && generation >= generationsLimit)
|| (resultLimit > 0 && result >= resultLimit)
|| (timeLimit > 0 && diff >= timeLimit);
if (generation > 0) {
resultsBuffer.push_back(result);
}
if (generation > resultBufferSize) {
resultsBuffer.erase(resultsBuffer.begin());
//cout << endl << "Current resultsBuffer[0]: " << resultsBuffer[0] << endl;
}
return anyLimit;
}
vector<string> getFileNames (string path) {
DIR *pDIR;
struct dirent *entry;
vector<string> fileNames;
if (pDIR=opendir(path.c_str())) {
while (entry = readdir(pDIR)) {
if (strcmp(entry->d_name, ".") != 0 && strcmp(entry->d_name, "..") != 0) {
fileNames.push_back(entry->d_name);
}
}
closedir(pDIR);
}
return fileNames;
}
/* pearson, spearman */
float mean (vector<float> values) {
float sum = 0;
int size = values.size();
for (int i = 0; i < size; i++) {
sum += values[i];
}
return sum / size;
}
float pearson_numerator (vector<float> A, vector<float> B, float meanA, float meanB) {
float numerator = 0;
for (int i = 0; i < A.size(); i++) {
numerator += (A[i] - meanA) * (B[i] - meanB);
}
return numerator;
}
float pearson_denominator (vector<float> A, vector<float> B, float meanA, float meanB) {
float denominator1;
float denominator1_sum = 0;
float denominator2;
float denominator2_sum = 0;
for (int i = 0; i < A.size(); i++) {
denominator1_sum += pow(A[i] - meanA, 2);
}
for (int i = 0; i < B.size(); i++) {
denominator2_sum += pow(B[i] - meanB, 2);
}
denominator1 = pow(denominator1_sum, 0.5);
denominator2 = pow(denominator2_sum, 0.5);
if (denominator1 == 0 || denominator2 == 0)
cout << endl << endl << "##### ERROR: Denominator equal to 0 - probable cause: all result values are equal" << endl << endl;
return denominator1 * denominator2;
}
float pearson (vector<float> A, vector<float> B) {
if (A.size() != B.size()) {
cout << "ERROR - wrong vector lengths" << endl;
return -1;
}
float meanA = mean(A);
float meanB = mean(B);
float numerator = pearson_numerator(A, B, meanA, meanB);
float denominator = pearson_denominator(A, B, meanA, meanB);
return numerator / denominator;
}
vector<float> toRank (vector<float> A) {
vector<float> sorted = A;
sort(sorted.begin(), sorted.end());
vector<float> rank;
for (int i = 0; i < A.size(); i++) {
vector<int> positions;
for (int j = 0; j < A.size(); j++) {
if (sorted[j] == A[i]) {
positions.push_back(j);
}
}
float sum = 0;
float avg;
for (int j = 0; j < positions.size(); j++) {
sum += positions[j] + 1;
}
avg = sum / positions.size();
rank.push_back(avg);
//rank.push_back(positions[positions.size()-1] + 1); //libreoffice calc rank
}
/*
cout << "Ranking: " << endl;
for (int i = 0; i < rank.size(); i++) {
cout << rank[i] << ", ";
}
cout << endl << endl;
*/
return rank;
}
float spearman (vector<float> A, vector<float> B) {
vector<float> A_ranked = toRank(A);
vector<float> B_ranked = toRank(B);
return pearson(A_ranked, B_ranked);
}
int main (int argc, char* argv[]) {
srand (time(NULL));
coutGPUStatus();
string _EXPERIMENT_ID = argv[1];
int tests = 100;
float timeLimit = 6; //seconds
int generationsLimit = 0; //5;
int resultLimit = 0; //32;
int resultBufferSize = 10;
float resultMinDiff = 0; //0.01;
bool saveResults = true;
bool saveResultsCorrelation = true;
float INFLUENCE_THRESHOLD = 0.5;
int N_MAX = 1000;
int STEPS_MAX = 10000;
int TO_FIND_PERCENTAGE = 5;
int THREADS_PER_BLOCK = 1024;
/* Parameters */
//int groupSize = 20; // 10, 20, 30 // 2, 5, 10, 20, 50
//int nrOfIndividuals = (int)ceil(N/10.0); // N/20, N/10, N/5 // 100, 500 1k, 2k, 10k
//float crossover_ratio = 0.7; // 0.5, 0.7, 0.9 // 0.1, 0.3, 0.5, 0.7, 0.9
//float mutation_potency = 0.01; // 0.001, 0.01, 0.1 // 0.01, 0.02, 0.05, 0.1, 0.2
//float mutation_ratio = 0.9; // 0.75, 0.9, 0.95, // 0.1, 0.3, 0.5, 0.7, 0.9
vector<int> a_groupSize {10, 20, 30}; // 10, 20, 30
vector<int> a_nrOfIndividuals {12, 10, 8}; // N/12, N/10, N/8
vector<float> a_crossover_ratio {0.6, 0.7, 0.8}; // 0.6, 0.7, 0.8
vector<float> a_mutation_potency {0.001, 0.01, 0.1}; // 0.001, 0.01, 0.1
vector<float> a_mutation_ratio {0.7, 0.8, 0.9}; // 0.7, 0.8, 0.9
int parameters_sets = a_groupSize.size() * a_nrOfIndividuals.size() * a_crossover_ratio.size() * a_mutation_potency.size() * a_mutation_ratio.size();
vector<string> datasets = getFileNames("./experiments_" + _EXPERIMENT_ID);
/* DEBUG */
int debug_nrOfIndividuals;
bool debug = true;
if (debug) {
tests = 10;
N_MAX = 1000;
THREADS_PER_BLOCK = 1024;
debug_nrOfIndividuals = -1; // -1 - the same as if it wasn't a debug mode (so devides N by a_nrOfIndividuals to get indivnr)
// tests: 10, debug_nrOfIndividuals: -1, generationsLimit: 1, THREADS_PER_BLOCK: 1024, default parameters, facebook
/* 100: 7 in 1ms, 500: 46 in 10ms, 1000: 88 in 53ms */
timeLimit = 0;
generationsLimit = 5; // 5 - 80s
resultLimit = 0;
resultMinDiff = 0;
saveResults = true;//false;
saveResultsCorrelation = true;//false;
a_groupSize = {20};
a_nrOfIndividuals = {8};
a_crossover_ratio = {0.7};
a_mutation_potency = {0.01};
a_mutation_ratio = {0.9};
parameters_sets = a_groupSize.size() * a_nrOfIndividuals.size() * a_crossover_ratio.size() * a_mutation_potency.size() * a_mutation_ratio.size();
//datasets = {"facebook-46952"};
//datasets = {"BA-1000-1-3.csv"};
datasets = {"ER-1000-0.05-10.csv"};
//datasets = getFileNames("./experiments_" + _EXPERIMENT_ID);
}
/*
N = 1000
INDIVIDUALS = 1000
THREADS_PER_BLOCK = 192
1 individuals - 0.056s
10 individuals - 0.081s
100 individuals - 0.265s
1000 individuals - 2.483s
THREADS_PER_BLOCK = 512
1000 individuals - 2.423s
THREADS_PER_BLOCK = 1024
1000 individuals - 2.481s
N = max (~47k for facebook)
THREADS_PER_BLOCK = 512
100 individuals - 5.08s
*/
vector<vector<float>> results;
for (int i=0; i<datasets.size(); i++) {
vector<float> row(parameters_sets, -1);
results.push_back(row);
}
for (int file_id=0; file_id<datasets.size(); file_id++) {
int dataset_id = file_id; //TODO to refactor
string dataset_name = datasets[file_id];
stringstream ssname(dataset_name);
string token;
getline(ssname, token, '-');
getline(ssname, token, '-');
int maxSize = stoi(token);
int N = min(N_MAX, maxSize);
int toFind = (int)ceil(float(TO_FIND_PERCENTAGE * N) / 100.0);
// using ofstream constructors.
std::ofstream outfile("results_" + dataset_name + "_" + _EXPERIMENT_ID + "_" + ".xls");
if (saveResults) {
outfile << "<?xml version='1.0'?>" << std::endl;
outfile << "<Workbook xmlns='urn:schemas-microsoft-com:office:spreadsheet'" << std::endl;
outfile << " xmlns:o='urn:schemas-microsoft-com:office:office'" << std::endl;
outfile << " xmlns:x='urn:schemas-microsoft-com:office:excel'" << std::endl;
outfile << " xmlns:ss='urn:schemas-microsoft-com:office:spreadsheet'" << std::endl;
outfile << " xmlns:html='http://www.w3.org/TR/REC-html40'>" << std::endl;
outfile << " <Worksheet ss:Name='Sheet1'>" << std::endl;
outfile << " <Table>" << std::endl;
outfile << " <Row>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>Dataset</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>Test nr</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>groupSize</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>nrOfIndividuals</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>crossover_ratio</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>mutation_potency</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>mutation_ratio</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>Generations</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>Result</Data></Cell>" << std::endl;
outfile << " </Row>" << std::endl;
}
vector <float> inf_col_ind;
vector <float> inf_row_ptr;
vector <float> inf_values;
defineInfluenceArrayAndVectors(dataset_name, N, inf_values, inf_col_ind, inf_row_ptr, _EXPERIMENT_ID);
int inf_values_size = inf_values.size();
int parameters_set = 1;
for_each(a_groupSize.begin(), a_groupSize.end(), [&] (int groupSize) {
for_each(a_nrOfIndividuals.begin(), a_nrOfIndividuals.end(), [&] (int nrOfIndividualsRaw) {
int nrOfIndividuals = (int)ceil(N/nrOfIndividualsRaw);
if (debug && debug_nrOfIndividuals != -1) {
nrOfIndividuals = debug_nrOfIndividuals;
}
for_each(a_crossover_ratio.begin(), a_crossover_ratio.end(), [&] (float crossover_ratio) {
for_each(a_mutation_potency.begin(), a_mutation_potency.end(), [&] (float mutation_potency) {
for_each(a_mutation_ratio.begin(), a_mutation_ratio.end(), [&] (float mutation_ratio) {
float testsResultsSum = 0;
float testsGenerationsSum = 0;
float testsTimeSum = 0;
for (int test = 0; test < tests; test++) {
vector <int> max_fitness_individual;
vector <vector<int>> population;
int max_fitness_value = -1;
int progressBarLength = 10;
int generation = 0;
vector<int> resultsBuffer;
createPopulation(nrOfIndividuals, N, toFind, population);
//createPopulationSample(nrOfIndividuals, N, toFind, population);
//coutPopulation(population);
int COMPUTATION_START_TIME = duration_cast<milliseconds>(system_clock::now().time_since_epoch()).count();
while (!anyLimitReached(resultBufferSize, resultMinDiff, resultsBuffer, generation, generationsLimit, timeLimit, COMPUTATION_START_TIME, max_fitness_value, resultLimit)) {
//coutGPUStatus();
F_TIME_START();
performPopulationSelection(population, nrOfIndividuals, N, inf_values_size, INFLUENCE_THRESHOLD, groupSize, STEPS_MAX, inf_values, inf_col_ind, inf_row_ptr, toFind, max_fitness_value, max_fitness_individual, THREADS_PER_BLOCK);
F_TIME_END("selection");
F_TIME_START();
performCrossover(population, nrOfIndividuals, crossover_ratio, toFind);
F_TIME_END("crossover");
F_TIME_START();
performMutation(population, nrOfIndividuals, mutation_ratio, mutation_potency, toFind, N);
F_TIME_END("mutation");
//coutResult(generation, max_fitness_value);
generation++;
}
int COMPUTATION_END_TIME = duration_cast<milliseconds>(system_clock::now().time_since_epoch()).count();
int COMPUTATION_DURATION = COMPUTATION_END_TIME - COMPUTATION_START_TIME;
cout << endl << "[FINISHED] test: " << test+1 << "/" << tests
<< " for parameters set nr: " << parameters_set << "/" << parameters_sets
<< " for dataset_id: " << dataset_id+1 << "/" << datasets.size()
<< " in: " << COMPUTATION_DURATION / 1000.0 << "s";
cout << endl;
coutGPUStatus();
cout << endl;
if (saveResults) {
outfile << " <Row>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(parameters_set) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(test+1) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(groupSize) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(nrOfIndividuals) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(crossover_ratio) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(mutation_potency) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(mutation_ratio) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(generation) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(max_fitness_value) + "</Data></Cell>" << std::endl;
outfile << " </Row>" << std::endl;
}
//cout << endl << "result " << test+1 << ": " << max_fitness_value << endl;
testsResultsSum += max_fitness_value;
testsGenerationsSum += generation;
testsTimeSum += COMPUTATION_DURATION;
/*cout << "Best individual found: " << endl;
for (int i=0; i<max_fitness_individual.size(); i++) {
cout << max_fitness_individual[i] << ", ";
}*/
//cout << endl << endl << "This group can activate " << max_fitness_value << " others";
//cout << endl << "Time elapsed: " << (time2 - COMPUTATION_START_TIME) / 1000.0 << "s" << endl;
} // TEST
float finalResult = std::round(testsResultsSum / tests);
float finalGenerations = std::round(testsGenerationsSum / tests);
float finalTime = std::round(testsTimeSum / tests);
cout << endl << "Final result avg: " << finalResult << " in avg " << finalTime / 1000.0 << "s" << endl;
results[file_id][parameters_set-1] = finalResult;
if (saveResults) {
outfile << " <Row>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(parameters_set) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>AVG </Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(groupSize) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(nrOfIndividuals) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(crossover_ratio) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(mutation_potency) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(mutation_ratio) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(finalGenerations) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(finalResult) + "</Data></Cell>" << std::endl;
outfile << " </Row>" << std::endl;
}
parameters_set++;
});
});
});
});
});
if (saveResults) {
outfile << " </Table>" << std::endl;
outfile << " </Worksheet>" << std::endl;
outfile << "</Workbook>" << std::endl;
}
outfile.close();
}
cout << endl << endl << "*** RESULTS ***" << endl;
for (int i=0; i<datasets.size(); i++) {
for (int j=0; j<parameters_sets; j++) {
cout << results[i][j] << ", ";
}
cout << endl;
}
if (saveResultsCorrelation) {
// using ofstream constructors.
std::ofstream outfile("results_correlation_" + _EXPERIMENT_ID + "_.xls");
outfile << "<?xml version='1.0'?>" << std::endl;
outfile << "<Workbook xmlns='urn:schemas-microsoft-com:office:spreadsheet'" << std::endl;
outfile << " xmlns:o='urn:schemas-microsoft-com:office:office'" << std::endl;
outfile << " xmlns:x='urn:schemas-microsoft-com:office:excel'" << std::endl;
outfile << " xmlns:ss='urn:schemas-microsoft-com:office:spreadsheet'" << std::endl;
outfile << " xmlns:html='http://www.w3.org/TR/REC-html40'>" << std::endl;
outfile << " <Worksheet ss:Name='Sheet1'>" << std::endl;
outfile << " <Table>" << std::endl;
outfile << " <Row>" << std::endl;
outfile << " <Cell></Cell>" << std::endl;
for (int i=0; i<datasets.size(); i++) {
outfile << " <Cell><Data ss:Type='String'>" + datasets[i] + "</Data></Cell>" << std::endl;
}
outfile << " </Row>" << std::endl;
for (int i=0; i<datasets.size(); i++) {
outfile << " <Row>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>" + datasets[i] + "</Data></Cell>" << std::endl;
for (int j=0; j<datasets.size(); j++) {
if (j > i) {
outfile << " <Cell><Data ss:Type='Number'>" + to_string(pearson(results[i], results[j])) + "</Data></Cell>" << std::endl;
} else {
outfile << " <Cell></Cell>" << std::endl;
}
}
outfile << " </Row>" << std::endl;
}
outfile << " <Row></Row>" << std::endl;
outfile << " <Row></Row>" << std::endl;
outfile << " <Row></Row>" << std::endl;
outfile << " <Row>" << std::endl;
outfile << " <Cell></Cell>" << std::endl;
for (int i=0; i<datasets.size(); i++) {
outfile << " <Cell><Data ss:Type='String'>" + datasets[i] + "</Data></Cell>" << std::endl;
}
outfile << " </Row>" << std::endl;
for (int i=0; i<datasets.size(); i++) {
outfile << " <Row>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>" + datasets[i] + "</Data></Cell>" << std::endl;
for (int j=0; j<datasets.size(); j++) {
if (j > i) {
outfile << " <Cell><Data ss:Type='Number'>" + to_string(spearman(results[i], results[j])) + "</Data></Cell>" << std::endl;
} else {
outfile << " <Cell></Cell>" << std::endl;
}
}
outfile << " </Row>" << std::endl;
}
outfile << " </Table>" << std::endl;
outfile << " </Worksheet>" << std::endl;
outfile << "</Workbook>" << std::endl;
outfile.close();
}
return 0;
} | #include <hip/hip_runtime.h>
#include <algorithm>
#include <cmath>
#include <cstdio>
#include <fstream>
#include <iostream>
#include <sstream>
#include <string>
#include <vector>
#include <sys/time.h>
#include <chrono>
#include <dirent.h>
using namespace std::chrono;
using namespace std;
vector<int> G_timestamps;
int getCurrentTime () {
return duration_cast<milliseconds>(system_clock::now().time_since_epoch()).count();
}
void F_TIME_START () {
G_timestamps.push_back(getCurrentTime());
}
void F_TIME_END (string measuredName) {
int start = G_timestamps.back();
int end = getCurrentTime();
float diff = (end - start) / 1000.0;
G_timestamps.pop_back();
cout << endl << "## [" << measuredName << "]: " << diff << "s" << endl << endl;
}
void coutGPUStatus () {
size_t freem, totalm;
float free_m, total_m, used_m;
hipMemGetInfo((size_t*)&freem, (size_t*)&totalm);
free_m = (size_t) freem / 1048576.0;
total_m = (size_t) totalm / 1048576.0;
used_m = total_m - free_m;
printf ( "## Total: %f MB. Used %f MB. Free: %f MB. \n", total_m, used_m, free_m);
}
void coutResult(int& generation, int& max_fitness_value) {
cout << "Generation " << generation << ", currently best individual can activate " << max_fitness_value << " others" << endl;
}
void coutPopulation (vector <vector<int>>& population) {
cout << "Population:";
for (int i=0; i<population.size(); i++) {
cout << "\nIndiv: " << i << ": ";
for (int j=0; j<population[i].size(); j++) {
if (population[i][j] < 10) {
cout << population[i][j] << ", ";
}
else if (population[i][j] < 100) {
cout << population[i][j] << ", ";
}
else if (population[i][j] < 1000) {
cout << population[i][j] << ", ";
}
else if (population[i][j] < 10000) {
cout << population[i][j] << ", ";
}
else {
cout << population[i][j] << ",";
}
}
}
cout << "\n\n";
}
void coutIndividual (vector <vector<int>>& population, int i) {
cout << "Individual " << i << ":";
for (int j=0; j<population[i].size(); j++) {
if (population[i][j] < 10) {
cout << population[i][j] << ", ";
}
else if (population[i][j] < 100) {
cout << population[i][j] << ", ";
}
else if (population[i][j] < 1000) {
cout << population[i][j] << ", ";
}
else if (population[i][j] < 10000) {
cout << population[i][j] << ", ";
}
else {
cout << population[i][j] << ",";
}
}
cout << "\n\n";
}
float getInfluenceValue (int N, int inf_values_size, vector<float>& inf_values, vector<float>& inf_col_ind, vector<float>& inf_row_ptr, int x, int y) {
float infValue = 0;
int min = inf_row_ptr[x];
int max = x == N-1 ? inf_values_size-1 : inf_row_ptr[x+1]; //inf_values_size-1
for (int i=min; i<max; i++) {
if (inf_col_ind[i] == y) {
infValue = inf_values[i];
break;
}
}
return infValue;
}
void InfluenceSpreadPopulationStep (bool *dyn_activeNodesPerIndividual, vector<float>& inf_values, vector<float>& inf_col_ind, vector<float>& inf_row_ptr, int N, int nrOfChangedIndividuals, int inf_values_size, float INFLUENCE_THRESHOLD, vector<int>& changedIndividuals) {
for (int indiv_id = 0; indiv_id < nrOfChangedIndividuals; indiv_id++) {
for (int node_id = 0; node_id < N; node_id++) {
int indiv_index = changedIndividuals[indiv_id];
float infValue = 0; // total value of influence on the node
for (int i=0; i<N; i++) {
if (dyn_activeNodesPerIndividual[indiv_index * N + i] && node_id != i) { // if i-th element is active and is not the node
float result = getInfluenceValue(N, inf_values_size, inf_values, inf_col_ind, inf_row_ptr, i, node_id);
infValue += result; // add i-th element influence on the node
//printf("Influence %d on %d is: %f\n", i, node_id, result);
//printf("\ninfValue: %f, id: %d", infValue, id);
}
}
//printf("\ninfValue: %f, id: %d", infValue, id);
if (infValue >= INFLUENCE_THRESHOLD) { // if total influence on the node is greater than or equal to the INFLUENCE_THRESHOLD value
dyn_activeNodesPerIndividual[indiv_index * N + node_id] = true; // activate the node
}
}
}
}
vector <vector<float>> readData (string dataset_name, int N, string _EXPERIMENT_ID) {
vector <vector<float>> influence;
// initialization of the influence vector
for (int i=0; i<N; i++) {
cout << endl << i << " out of " << N << endl;
vector<float> row(N, 0);
influence.push_back(row);
if ((i + 1) * N % (N * N / 10) == 0) {
cout << "[Initialization of the influence matrix]: " << float((i + 1) * N) / (N * N) * 100 << "%" << endl;
}
}
// total number of interactions received by every node
vector<float> received(N, 0);
ifstream infile("./experiments_" + _EXPERIMENT_ID + "/" + dataset_name);
string line;
int _csv_id_hack = -1;
if (dataset_name.find(".csv") != std::string::npos) {
_csv_id_hack = 0;
}
if (infile.good()) {
int line_nr = 0;
while (getline(infile, line)) {
cout << "Reading raw data file, line nr: " << line_nr << endl;
//cout << line << endl;
istringstream iss(line);
int a, b;
if (!(iss >> a >> b)) { cout << "ERROR" << endl; break; } // error
if (a != b && a + _csv_id_hack < N && b + _csv_id_hack < N) {
influence[a + _csv_id_hack][b + _csv_id_hack] += 1; // temp inf_values, calculating the total number of iteractions from "i" to "j"
received [b + _csv_id_hack] += 1;
//cout << "message from " << a + _csv_id_hack << " to " << b + _csv_id_hack << endl;
}
line_nr++;
}
infile.close();
cout << "File reading finished successfully." << endl;
ofstream outfile ("./experiments-counted/" + dataset_name + "_influenceCounted_" + to_string(N));
if (outfile.good()) {
// Influence value calculated as the ratio of iteractions from "i" node to "j" node, to the total number of iteractions to the "j" node.
for (int i=0; i<N; i++) {
for (int j=0; j<N; j++) {
//cout << "Influence values calculations, step: " << i*N+(j+1) << "/" << N*N << endl;
if (i == j) {
outfile << i << " " << j << " " << -1 << "\n";
influence[i][j] = -1;
} else if (influence[i][j] > 0) {
if (received[j] != 0) {
influence[i][j] = influence[i][j] / received[j];
} else if (influence[i][j] != 0) {
cout << "Received array error";
}
/*cout << i << "'s influence on " << j << " equals: " << influence[i][j] << endl;*/
outfile << i << " " << j << " " << influence[i][j] << "\n";
} else {
influence[i][j] = 0;
}
}
}
cout << "Compressed file saved successfully." << endl;
outfile.close();
} else {
throw std::invalid_argument("readData - File " + dataset_name + " not saved.");
}
} else {
throw std::invalid_argument("readData - File " + dataset_name + " not found.");
}
return influence;
}
void defineInfluenceArrayAndVectors (string dataset_name, int N, vector<float>& inf_values, vector<float>& inf_col_ind, vector<float>& inf_row_ptr, string _EXPERIMENT_ID) {
//cout << "File reading started." << endl;
ifstream infile("./experiments-counted/" + dataset_name + "_influenceCounted_" + to_string(N));
if (infile.good()) { // reading the already calculated influence values
int line_nr = 0;
string line;
float last_a = -1;
while (getline(infile, line)) {
cout << "Reading influence file, line nr: " << line_nr << endl;
istringstream iss(line);
float a, b, c;
if (!(iss >> a >> b >> c)) { break; } // error
if (c != 0) {
if (a != last_a) {
inf_row_ptr.push_back(inf_values.size());
//cout << "add row ptr: " << inf_values.size() << endl;
last_a = a;
}
inf_values.push_back(c);
//cout << "add value: " << c << endl;
inf_col_ind.push_back(b);
//cout << "add col ind: " << b << endl;
}
line_nr++;
}
infile.close();
} else { // calculating influnce values
infile.close();
vector <vector<float>> influence = readData(dataset_name, N, _EXPERIMENT_ID);
// inf_values, inf_col_ind, inf_row_ptr creation, based on the influence array
for (int i=0; i<N; i++) {
bool added = false;
for (int j=0; j<N; j++) {
//cout << "Influence of " << i << " on " << j << " is equal to: " << influence[i][j] << endl;
if (influence[i][j] != 0) {
if (!added) {
inf_row_ptr.push_back(inf_values.size());
//cout << "add row ptr: " << inf_values.size() << endl;
added = true;
}
inf_values.push_back(influence[i][j]);
//cout << "add value: " << influence[i][j] << endl;
inf_col_ind.push_back(j);
//cout << "add col ind: " << j << endl;
}
}
if (!added) {
//inf_row_ptr.push_back(-1);
}
}
/*cout << "\n\n size of influence array: " << sizeof(influence) + sizeof(float) * influence.capacity() * influence.capacity();
cout << "\n\n Total size of vectors: "
<< sizeof(inf_values) + sizeof(float) * inf_values.capacity()
+ sizeof(inf_col_ind) + sizeof(float) * inf_col_ind.capacity()
+ sizeof(inf_row_ptr) + sizeof(float) * inf_row_ptr.capacity() << "\n\n";*/
}
}
void createPopulation (int nrOfIndividuals, int N, int toFind, vector <vector<int>>& population) {
// creating random individuals within population
for (int i = 0; i<nrOfIndividuals; i++) {
vector<int> row;
population.push_back(row);
cout << "Creating individual " << i << " of " << nrOfIndividuals << endl;
for (int j = 0; j<toFind; j++) {
int rand_id = rand() % N;
bool alreadyAdded = true;
while (alreadyAdded) {
alreadyAdded = false;
for (int k=0; k<population[i].size(); k++) {
if (population[i][k] == rand_id) {
alreadyAdded = true;
rand_id = rand() % N;
}
}
}
//cout << "pushing: " << rand_id << endl;
population[i].push_back(rand_id);
}
}
}
void createPopulationSample (int nrOfIndividuals, int N, int toFind, vector <vector<int>>& population) {
// creating one individual - used as a sample e.g. for GPU vs CPU tests
vector<int> row;
population.push_back(row);
for (int x = 0; x<toFind; x++) {
population[0].push_back(x);
}
}
void setPopulationFitness (vector<vector<int>>& population, int nrOfIndividuals, int N, int inf_values_size, float& INFLUENCE_THRESHOLD, int STEPS_MAX, vector<float>& inf_values, vector<float>& inf_col_ind, vector<float>& inf_row_ptr, int toFind, vector<int>& fitness, int THREADS_PER_BLOCK) {
//bool activeNodesPerIndividual[nrOfIndividuals][N];
bool *dyn_activeNodesPerIndividual = new bool[nrOfIndividuals*N];
for (int i=0; i<nrOfIndividuals; i++) {
for (int j=0; j<N; j++) {
int index = N * i + j;
dyn_activeNodesPerIndividual[index] = false;
}
for (int j=0; j<toFind; j++) {
int index = N * i + population[i][j];
dyn_activeNodesPerIndividual[index] = true;
}
}
int active [nrOfIndividuals];
vector<int> changedIndividuals;
for (int i=0; i<nrOfIndividuals; i++) {
active[i] = toFind;
changedIndividuals.push_back(i);
}
int step_counter = 0;
while (step_counter < STEPS_MAX && changedIndividuals.size() > 0) {
//cout << "Step: " << step_counter << " / " << STEPS_MAX << endl;
int nrOfChangedIndividuals = changedIndividuals.size();
cout << "nrOfChangedIndividuals " << nrOfChangedIndividuals << endl;
F_TIME_START();
InfluenceSpreadPopulationStep (dyn_activeNodesPerIndividual, inf_values, inf_col_ind, inf_row_ptr, N, nrOfChangedIndividuals, inf_values_size, INFLUENCE_THRESHOLD, changedIndividuals);
F_TIME_END("host functions");
changedIndividuals.clear();
int curr_active;
for (int i=0; i<nrOfIndividuals; i++) {
curr_active = 0;
for (int j=0; j<N; j++) {
int index = N * i + j;
if (dyn_activeNodesPerIndividual[index]) {
curr_active++;
}
}
if (curr_active != active[i]) {
changedIndividuals.push_back(i);
}
active[i] = curr_active;
}
step_counter++;
}
for (int i = 0; i < nrOfIndividuals; i++) {
int individualFitness = 0;
for (int j = 0; j < N; j++) {
int index = N * i + j;
if (dyn_activeNodesPerIndividual[index]) {
individualFitness++;
//cout << "Activated " << j << endl;
}
}
//cout << "individualFitness: " << individualFitness << endl;
//cout << "toFind: " << toFind << endl;
// acceptable `error`
/*if (individualFitness-toFind < 0) {
cout << "# Crossover/mutation overlapping" << endl; // can happen because of random crossover and mutation
//coutIndividual(population, i);
}*/
//cout << "fitness Indiv: " << i << ": " << individualFitness-toFind << endl;
fitness.push_back(individualFitness-toFind);
}
}
void performPopulationSelection (vector<vector<int>>& population, int& nrOfIndividuals, int N, int inf_values_size, float& INFLUENCE_THRESHOLD, int& groupSize, int& STEPS_MAX, vector<float>& inf_values, vector<float>& inf_col_ind, vector<float>& inf_row_ptr, int& toFind, int& max_fitness_value, vector<int>& max_fitness_individual, int THREADS_PER_BLOCK) {
vector<int> fitness;
F_TIME_START();
setPopulationFitness(population, nrOfIndividuals, N, inf_values_size, INFLUENCE_THRESHOLD, STEPS_MAX, inf_values, inf_col_ind, inf_row_ptr, toFind, fitness, THREADS_PER_BLOCK);
F_TIME_END("selection - fitness count");
F_TIME_START();
vector<vector<int>> newPopulation;
while (newPopulation.size() != population.size()) {
vector<int> newGroup;
bool alreadyAdded[nrOfIndividuals];
for (int i=0; i<nrOfIndividuals; i++) {
alreadyAdded[i] = false;
}
for (int j=0; j<groupSize; j++) {
int randIndiv = rand() % nrOfIndividuals;
while (alreadyAdded[randIndiv]) {
randIndiv = rand() % nrOfIndividuals;
}
newGroup.push_back(randIndiv);
}
int curr_best_fitness = -1;
int curr_best_id = -1;
int currentFitness = -1;
for (int j=0; j<newGroup.size(); j++) {
currentFitness = fitness[newGroup[j]];
if (currentFitness > curr_best_fitness) {
curr_best_fitness = currentFitness;
curr_best_id = j;
}
}
newPopulation.push_back(population[newGroup[curr_best_id]]);
if (curr_best_fitness > max_fitness_value) {
max_fitness_individual = population[newGroup[curr_best_id]];
max_fitness_value = curr_best_fitness;
}
}
population = newPopulation;
F_TIME_END("selection - population swapping");
}
// TODO performCrossover on DEVICE (nrOfIndividuals/2 threads (from 0 to nr/2 - 1), ids: id*2, id*2+1
void performCrossover (vector<vector<int>>& population, int& nrOfIndividuals, float& crossover_ratio, int& toFind) {
float split_ratio = 0.5;
float split_point = split_ratio*toFind;
int id_first = -1;
int id_second = -1;
for (int i=0; i<nrOfIndividuals; i++) {
int cross = rand() % 100;
if (cross < crossover_ratio * 100) {
if (id_first == -1) {
id_first = i;
} else {
id_second = i;
}
}
if (id_second != -1) {
for (int j=0; j<split_point; j++) {
float temp = population[id_first][j];
population[id_first][j] = population[id_second][j];
population[id_second][j] = temp;
}
id_first = -1;
id_second = -1;
}
} // allows to node doubling (fitness = -1 can happen)
}
// TODO performMutation on DEVICE
void performMutation (vector<vector<int>>& population, int& nrOfIndividuals, float& mutation_ratio, float& mutation_potency, int& toFind, int N) {
for (int i=0; i<nrOfIndividuals; i++) {
int mutation = rand() % 100;
if (mutation < mutation_ratio * 100) {
for (int j=0; j<mutation_potency*toFind; j++) {
population[i][rand() % toFind] = rand() % N;
}
}
} // allows to node doubling (fitness = -1 can happen)
}
bool anyLimitReached(int resultBufferSize, float resultMinDiff, vector<int> &resultsBuffer, int generation, int generationsLimit, float timeLimit, int COMPUTATION_START_TIME, int result, int resultLimit) {
int now = duration_cast<milliseconds>(system_clock::now().time_since_epoch()).count();
float diff = (now - COMPUTATION_START_TIME) / 1000.0;
bool anyLimit =
(resultMinDiff > 0 && generation > resultBufferSize && result < resultsBuffer[0] * (1 + resultMinDiff))
|| (generationsLimit > 0 && generation >= generationsLimit)
|| (resultLimit > 0 && result >= resultLimit)
|| (timeLimit > 0 && diff >= timeLimit);
if (generation > 0) {
resultsBuffer.push_back(result);
}
if (generation > resultBufferSize) {
resultsBuffer.erase(resultsBuffer.begin());
//cout << endl << "Current resultsBuffer[0]: " << resultsBuffer[0] << endl;
}
return anyLimit;
}
vector<string> getFileNames (string path) {
DIR *pDIR;
struct dirent *entry;
vector<string> fileNames;
if (pDIR=opendir(path.c_str())) {
while (entry = readdir(pDIR)) {
if (strcmp(entry->d_name, ".") != 0 && strcmp(entry->d_name, "..") != 0) {
fileNames.push_back(entry->d_name);
}
}
closedir(pDIR);
}
return fileNames;
}
/* pearson, spearman */
float mean (vector<float> values) {
float sum = 0;
int size = values.size();
for (int i = 0; i < size; i++) {
sum += values[i];
}
return sum / size;
}
float pearson_numerator (vector<float> A, vector<float> B, float meanA, float meanB) {
float numerator = 0;
for (int i = 0; i < A.size(); i++) {
numerator += (A[i] - meanA) * (B[i] - meanB);
}
return numerator;
}
float pearson_denominator (vector<float> A, vector<float> B, float meanA, float meanB) {
float denominator1;
float denominator1_sum = 0;
float denominator2;
float denominator2_sum = 0;
for (int i = 0; i < A.size(); i++) {
denominator1_sum += pow(A[i] - meanA, 2);
}
for (int i = 0; i < B.size(); i++) {
denominator2_sum += pow(B[i] - meanB, 2);
}
denominator1 = pow(denominator1_sum, 0.5);
denominator2 = pow(denominator2_sum, 0.5);
if (denominator1 == 0 || denominator2 == 0)
cout << endl << endl << "##### ERROR: Denominator equal to 0 - probable cause: all result values are equal" << endl << endl;
return denominator1 * denominator2;
}
float pearson (vector<float> A, vector<float> B) {
if (A.size() != B.size()) {
cout << "ERROR - wrong vector lengths" << endl;
return -1;
}
float meanA = mean(A);
float meanB = mean(B);
float numerator = pearson_numerator(A, B, meanA, meanB);
float denominator = pearson_denominator(A, B, meanA, meanB);
return numerator / denominator;
}
vector<float> toRank (vector<float> A) {
vector<float> sorted = A;
sort(sorted.begin(), sorted.end());
vector<float> rank;
for (int i = 0; i < A.size(); i++) {
vector<int> positions;
for (int j = 0; j < A.size(); j++) {
if (sorted[j] == A[i]) {
positions.push_back(j);
}
}
float sum = 0;
float avg;
for (int j = 0; j < positions.size(); j++) {
sum += positions[j] + 1;
}
avg = sum / positions.size();
rank.push_back(avg);
//rank.push_back(positions[positions.size()-1] + 1); //libreoffice calc rank
}
/*
cout << "Ranking: " << endl;
for (int i = 0; i < rank.size(); i++) {
cout << rank[i] << ", ";
}
cout << endl << endl;
*/
return rank;
}
float spearman (vector<float> A, vector<float> B) {
vector<float> A_ranked = toRank(A);
vector<float> B_ranked = toRank(B);
return pearson(A_ranked, B_ranked);
}
int main (int argc, char* argv[]) {
srand (time(NULL));
coutGPUStatus();
string _EXPERIMENT_ID = argv[1];
int tests = 100;
float timeLimit = 6; //seconds
int generationsLimit = 0; //5;
int resultLimit = 0; //32;
int resultBufferSize = 10;
float resultMinDiff = 0; //0.01;
bool saveResults = true;
bool saveResultsCorrelation = true;
float INFLUENCE_THRESHOLD = 0.5;
int N_MAX = 1000;
int STEPS_MAX = 10000;
int TO_FIND_PERCENTAGE = 5;
int THREADS_PER_BLOCK = 1024;
/* Parameters */
//int groupSize = 20; // 10, 20, 30 // 2, 5, 10, 20, 50
//int nrOfIndividuals = (int)ceil(N/10.0); // N/20, N/10, N/5 // 100, 500 1k, 2k, 10k
//float crossover_ratio = 0.7; // 0.5, 0.7, 0.9 // 0.1, 0.3, 0.5, 0.7, 0.9
//float mutation_potency = 0.01; // 0.001, 0.01, 0.1 // 0.01, 0.02, 0.05, 0.1, 0.2
//float mutation_ratio = 0.9; // 0.75, 0.9, 0.95, // 0.1, 0.3, 0.5, 0.7, 0.9
vector<int> a_groupSize {10, 20, 30}; // 10, 20, 30
vector<int> a_nrOfIndividuals {12, 10, 8}; // N/12, N/10, N/8
vector<float> a_crossover_ratio {0.6, 0.7, 0.8}; // 0.6, 0.7, 0.8
vector<float> a_mutation_potency {0.001, 0.01, 0.1}; // 0.001, 0.01, 0.1
vector<float> a_mutation_ratio {0.7, 0.8, 0.9}; // 0.7, 0.8, 0.9
int parameters_sets = a_groupSize.size() * a_nrOfIndividuals.size() * a_crossover_ratio.size() * a_mutation_potency.size() * a_mutation_ratio.size();
vector<string> datasets = getFileNames("./experiments_" + _EXPERIMENT_ID);
/* DEBUG */
int debug_nrOfIndividuals;
bool debug = true;
if (debug) {
tests = 10;
N_MAX = 1000;
THREADS_PER_BLOCK = 1024;
debug_nrOfIndividuals = -1; // -1 - the same as if it wasn't a debug mode (so devides N by a_nrOfIndividuals to get indivnr)
// tests: 10, debug_nrOfIndividuals: -1, generationsLimit: 1, THREADS_PER_BLOCK: 1024, default parameters, facebook
/* 100: 7 in 1ms, 500: 46 in 10ms, 1000: 88 in 53ms */
timeLimit = 0;
generationsLimit = 5; // 5 - 80s
resultLimit = 0;
resultMinDiff = 0;
saveResults = true;//false;
saveResultsCorrelation = true;//false;
a_groupSize = {20};
a_nrOfIndividuals = {8};
a_crossover_ratio = {0.7};
a_mutation_potency = {0.01};
a_mutation_ratio = {0.9};
parameters_sets = a_groupSize.size() * a_nrOfIndividuals.size() * a_crossover_ratio.size() * a_mutation_potency.size() * a_mutation_ratio.size();
//datasets = {"facebook-46952"};
//datasets = {"BA-1000-1-3.csv"};
datasets = {"ER-1000-0.05-10.csv"};
//datasets = getFileNames("./experiments_" + _EXPERIMENT_ID);
}
/*
N = 1000
INDIVIDUALS = 1000
THREADS_PER_BLOCK = 192
1 individuals - 0.056s
10 individuals - 0.081s
100 individuals - 0.265s
1000 individuals - 2.483s
THREADS_PER_BLOCK = 512
1000 individuals - 2.423s
THREADS_PER_BLOCK = 1024
1000 individuals - 2.481s
N = max (~47k for facebook)
THREADS_PER_BLOCK = 512
100 individuals - 5.08s
*/
vector<vector<float>> results;
for (int i=0; i<datasets.size(); i++) {
vector<float> row(parameters_sets, -1);
results.push_back(row);
}
for (int file_id=0; file_id<datasets.size(); file_id++) {
int dataset_id = file_id; //TODO to refactor
string dataset_name = datasets[file_id];
stringstream ssname(dataset_name);
string token;
getline(ssname, token, '-');
getline(ssname, token, '-');
int maxSize = stoi(token);
int N = min(N_MAX, maxSize);
int toFind = (int)ceil(float(TO_FIND_PERCENTAGE * N) / 100.0);
// using ofstream constructors.
std::ofstream outfile("results_" + dataset_name + "_" + _EXPERIMENT_ID + "_" + ".xls");
if (saveResults) {
outfile << "<?xml version='1.0'?>" << std::endl;
outfile << "<Workbook xmlns='urn:schemas-microsoft-com:office:spreadsheet'" << std::endl;
outfile << " xmlns:o='urn:schemas-microsoft-com:office:office'" << std::endl;
outfile << " xmlns:x='urn:schemas-microsoft-com:office:excel'" << std::endl;
outfile << " xmlns:ss='urn:schemas-microsoft-com:office:spreadsheet'" << std::endl;
outfile << " xmlns:html='http://www.w3.org/TR/REC-html40'>" << std::endl;
outfile << " <Worksheet ss:Name='Sheet1'>" << std::endl;
outfile << " <Table>" << std::endl;
outfile << " <Row>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>Dataset</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>Test nr</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>groupSize</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>nrOfIndividuals</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>crossover_ratio</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>mutation_potency</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>mutation_ratio</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>Generations</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>Result</Data></Cell>" << std::endl;
outfile << " </Row>" << std::endl;
}
vector <float> inf_col_ind;
vector <float> inf_row_ptr;
vector <float> inf_values;
defineInfluenceArrayAndVectors(dataset_name, N, inf_values, inf_col_ind, inf_row_ptr, _EXPERIMENT_ID);
int inf_values_size = inf_values.size();
int parameters_set = 1;
for_each(a_groupSize.begin(), a_groupSize.end(), [&] (int groupSize) {
for_each(a_nrOfIndividuals.begin(), a_nrOfIndividuals.end(), [&] (int nrOfIndividualsRaw) {
int nrOfIndividuals = (int)ceil(N/nrOfIndividualsRaw);
if (debug && debug_nrOfIndividuals != -1) {
nrOfIndividuals = debug_nrOfIndividuals;
}
for_each(a_crossover_ratio.begin(), a_crossover_ratio.end(), [&] (float crossover_ratio) {
for_each(a_mutation_potency.begin(), a_mutation_potency.end(), [&] (float mutation_potency) {
for_each(a_mutation_ratio.begin(), a_mutation_ratio.end(), [&] (float mutation_ratio) {
float testsResultsSum = 0;
float testsGenerationsSum = 0;
float testsTimeSum = 0;
for (int test = 0; test < tests; test++) {
vector <int> max_fitness_individual;
vector <vector<int>> population;
int max_fitness_value = -1;
int progressBarLength = 10;
int generation = 0;
vector<int> resultsBuffer;
createPopulation(nrOfIndividuals, N, toFind, population);
//createPopulationSample(nrOfIndividuals, N, toFind, population);
//coutPopulation(population);
int COMPUTATION_START_TIME = duration_cast<milliseconds>(system_clock::now().time_since_epoch()).count();
while (!anyLimitReached(resultBufferSize, resultMinDiff, resultsBuffer, generation, generationsLimit, timeLimit, COMPUTATION_START_TIME, max_fitness_value, resultLimit)) {
//coutGPUStatus();
F_TIME_START();
performPopulationSelection(population, nrOfIndividuals, N, inf_values_size, INFLUENCE_THRESHOLD, groupSize, STEPS_MAX, inf_values, inf_col_ind, inf_row_ptr, toFind, max_fitness_value, max_fitness_individual, THREADS_PER_BLOCK);
F_TIME_END("selection");
F_TIME_START();
performCrossover(population, nrOfIndividuals, crossover_ratio, toFind);
F_TIME_END("crossover");
F_TIME_START();
performMutation(population, nrOfIndividuals, mutation_ratio, mutation_potency, toFind, N);
F_TIME_END("mutation");
//coutResult(generation, max_fitness_value);
generation++;
}
int COMPUTATION_END_TIME = duration_cast<milliseconds>(system_clock::now().time_since_epoch()).count();
int COMPUTATION_DURATION = COMPUTATION_END_TIME - COMPUTATION_START_TIME;
cout << endl << "[FINISHED] test: " << test+1 << "/" << tests
<< " for parameters set nr: " << parameters_set << "/" << parameters_sets
<< " for dataset_id: " << dataset_id+1 << "/" << datasets.size()
<< " in: " << COMPUTATION_DURATION / 1000.0 << "s";
cout << endl;
coutGPUStatus();
cout << endl;
if (saveResults) {
outfile << " <Row>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(parameters_set) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(test+1) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(groupSize) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(nrOfIndividuals) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(crossover_ratio) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(mutation_potency) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(mutation_ratio) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(generation) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(max_fitness_value) + "</Data></Cell>" << std::endl;
outfile << " </Row>" << std::endl;
}
//cout << endl << "result " << test+1 << ": " << max_fitness_value << endl;
testsResultsSum += max_fitness_value;
testsGenerationsSum += generation;
testsTimeSum += COMPUTATION_DURATION;
/*cout << "Best individual found: " << endl;
for (int i=0; i<max_fitness_individual.size(); i++) {
cout << max_fitness_individual[i] << ", ";
}*/
//cout << endl << endl << "This group can activate " << max_fitness_value << " others";
//cout << endl << "Time elapsed: " << (time2 - COMPUTATION_START_TIME) / 1000.0 << "s" << endl;
} // TEST
float finalResult = std::round(testsResultsSum / tests);
float finalGenerations = std::round(testsGenerationsSum / tests);
float finalTime = std::round(testsTimeSum / tests);
cout << endl << "Final result avg: " << finalResult << " in avg " << finalTime / 1000.0 << "s" << endl;
results[file_id][parameters_set-1] = finalResult;
if (saveResults) {
outfile << " <Row>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(parameters_set) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>AVG </Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(groupSize) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(nrOfIndividuals) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(crossover_ratio) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(mutation_potency) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(mutation_ratio) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(finalGenerations) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(finalResult) + "</Data></Cell>" << std::endl;
outfile << " </Row>" << std::endl;
}
parameters_set++;
});
});
});
});
});
if (saveResults) {
outfile << " </Table>" << std::endl;
outfile << " </Worksheet>" << std::endl;
outfile << "</Workbook>" << std::endl;
}
outfile.close();
}
cout << endl << endl << "*** RESULTS ***" << endl;
for (int i=0; i<datasets.size(); i++) {
for (int j=0; j<parameters_sets; j++) {
cout << results[i][j] << ", ";
}
cout << endl;
}
if (saveResultsCorrelation) {
// using ofstream constructors.
std::ofstream outfile("results_correlation_" + _EXPERIMENT_ID + "_.xls");
outfile << "<?xml version='1.0'?>" << std::endl;
outfile << "<Workbook xmlns='urn:schemas-microsoft-com:office:spreadsheet'" << std::endl;
outfile << " xmlns:o='urn:schemas-microsoft-com:office:office'" << std::endl;
outfile << " xmlns:x='urn:schemas-microsoft-com:office:excel'" << std::endl;
outfile << " xmlns:ss='urn:schemas-microsoft-com:office:spreadsheet'" << std::endl;
outfile << " xmlns:html='http://www.w3.org/TR/REC-html40'>" << std::endl;
outfile << " <Worksheet ss:Name='Sheet1'>" << std::endl;
outfile << " <Table>" << std::endl;
outfile << " <Row>" << std::endl;
outfile << " <Cell></Cell>" << std::endl;
for (int i=0; i<datasets.size(); i++) {
outfile << " <Cell><Data ss:Type='String'>" + datasets[i] + "</Data></Cell>" << std::endl;
}
outfile << " </Row>" << std::endl;
for (int i=0; i<datasets.size(); i++) {
outfile << " <Row>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>" + datasets[i] + "</Data></Cell>" << std::endl;
for (int j=0; j<datasets.size(); j++) {
if (j > i) {
outfile << " <Cell><Data ss:Type='Number'>" + to_string(pearson(results[i], results[j])) + "</Data></Cell>" << std::endl;
} else {
outfile << " <Cell></Cell>" << std::endl;
}
}
outfile << " </Row>" << std::endl;
}
outfile << " <Row></Row>" << std::endl;
outfile << " <Row></Row>" << std::endl;
outfile << " <Row></Row>" << std::endl;
outfile << " <Row>" << std::endl;
outfile << " <Cell></Cell>" << std::endl;
for (int i=0; i<datasets.size(); i++) {
outfile << " <Cell><Data ss:Type='String'>" + datasets[i] + "</Data></Cell>" << std::endl;
}
outfile << " </Row>" << std::endl;
for (int i=0; i<datasets.size(); i++) {
outfile << " <Row>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>" + datasets[i] + "</Data></Cell>" << std::endl;
for (int j=0; j<datasets.size(); j++) {
if (j > i) {
outfile << " <Cell><Data ss:Type='Number'>" + to_string(spearman(results[i], results[j])) + "</Data></Cell>" << std::endl;
} else {
outfile << " <Cell></Cell>" << std::endl;
}
}
outfile << " </Row>" << std::endl;
}
outfile << " </Table>" << std::endl;
outfile << " </Worksheet>" << std::endl;
outfile << "</Workbook>" << std::endl;
outfile.close();
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <algorithm>
#include <cmath>
#include <cstdio>
#include <fstream>
#include <iostream>
#include <sstream>
#include <string>
#include <vector>
#include <sys/time.h>
#include <chrono>
#include <dirent.h>
using namespace std::chrono;
using namespace std;
vector<int> G_timestamps;
int getCurrentTime () {
return duration_cast<milliseconds>(system_clock::now().time_since_epoch()).count();
}
void F_TIME_START () {
G_timestamps.push_back(getCurrentTime());
}
void F_TIME_END (string measuredName) {
int start = G_timestamps.back();
int end = getCurrentTime();
float diff = (end - start) / 1000.0;
G_timestamps.pop_back();
cout << endl << "## [" << measuredName << "]: " << diff << "s" << endl << endl;
}
void coutGPUStatus () {
size_t freem, totalm;
float free_m, total_m, used_m;
hipMemGetInfo((size_t*)&freem, (size_t*)&totalm);
free_m = (size_t) freem / 1048576.0;
total_m = (size_t) totalm / 1048576.0;
used_m = total_m - free_m;
printf ( "## Total: %f MB. Used %f MB. Free: %f MB. \n", total_m, used_m, free_m);
}
void coutResult(int& generation, int& max_fitness_value) {
cout << "Generation " << generation << ", currently best individual can activate " << max_fitness_value << " others" << endl;
}
void coutPopulation (vector <vector<int>>& population) {
cout << "Population:";
for (int i=0; i<population.size(); i++) {
cout << "\nIndiv: " << i << ": ";
for (int j=0; j<population[i].size(); j++) {
if (population[i][j] < 10) {
cout << population[i][j] << ", ";
}
else if (population[i][j] < 100) {
cout << population[i][j] << ", ";
}
else if (population[i][j] < 1000) {
cout << population[i][j] << ", ";
}
else if (population[i][j] < 10000) {
cout << population[i][j] << ", ";
}
else {
cout << population[i][j] << ",";
}
}
}
cout << "\n\n";
}
void coutIndividual (vector <vector<int>>& population, int i) {
cout << "Individual " << i << ":";
for (int j=0; j<population[i].size(); j++) {
if (population[i][j] < 10) {
cout << population[i][j] << ", ";
}
else if (population[i][j] < 100) {
cout << population[i][j] << ", ";
}
else if (population[i][j] < 1000) {
cout << population[i][j] << ", ";
}
else if (population[i][j] < 10000) {
cout << population[i][j] << ", ";
}
else {
cout << population[i][j] << ",";
}
}
cout << "\n\n";
}
float getInfluenceValue (int N, int inf_values_size, vector<float>& inf_values, vector<float>& inf_col_ind, vector<float>& inf_row_ptr, int x, int y) {
float infValue = 0;
int min = inf_row_ptr[x];
int max = x == N-1 ? inf_values_size-1 : inf_row_ptr[x+1]; //inf_values_size-1
for (int i=min; i<max; i++) {
if (inf_col_ind[i] == y) {
infValue = inf_values[i];
break;
}
}
return infValue;
}
void InfluenceSpreadPopulationStep (bool *dyn_activeNodesPerIndividual, vector<float>& inf_values, vector<float>& inf_col_ind, vector<float>& inf_row_ptr, int N, int nrOfChangedIndividuals, int inf_values_size, float INFLUENCE_THRESHOLD, vector<int>& changedIndividuals) {
for (int indiv_id = 0; indiv_id < nrOfChangedIndividuals; indiv_id++) {
for (int node_id = 0; node_id < N; node_id++) {
int indiv_index = changedIndividuals[indiv_id];
float infValue = 0; // total value of influence on the node
for (int i=0; i<N; i++) {
if (dyn_activeNodesPerIndividual[indiv_index * N + i] && node_id != i) { // if i-th element is active and is not the node
float result = getInfluenceValue(N, inf_values_size, inf_values, inf_col_ind, inf_row_ptr, i, node_id);
infValue += result; // add i-th element influence on the node
//printf("Influence %d on %d is: %f\n", i, node_id, result);
//printf("\ninfValue: %f, id: %d", infValue, id);
}
}
//printf("\ninfValue: %f, id: %d", infValue, id);
if (infValue >= INFLUENCE_THRESHOLD) { // if total influence on the node is greater than or equal to the INFLUENCE_THRESHOLD value
dyn_activeNodesPerIndividual[indiv_index * N + node_id] = true; // activate the node
}
}
}
}
vector <vector<float>> readData (string dataset_name, int N, string _EXPERIMENT_ID) {
vector <vector<float>> influence;
// initialization of the influence vector
for (int i=0; i<N; i++) {
cout << endl << i << " out of " << N << endl;
vector<float> row(N, 0);
influence.push_back(row);
if ((i + 1) * N % (N * N / 10) == 0) {
cout << "[Initialization of the influence matrix]: " << float((i + 1) * N) / (N * N) * 100 << "%" << endl;
}
}
// total number of interactions received by every node
vector<float> received(N, 0);
ifstream infile("./experiments_" + _EXPERIMENT_ID + "/" + dataset_name);
string line;
int _csv_id_hack = -1;
if (dataset_name.find(".csv") != std::string::npos) {
_csv_id_hack = 0;
}
if (infile.good()) {
int line_nr = 0;
while (getline(infile, line)) {
cout << "Reading raw data file, line nr: " << line_nr << endl;
//cout << line << endl;
istringstream iss(line);
int a, b;
if (!(iss >> a >> b)) { cout << "ERROR" << endl; break; } // error
if (a != b && a + _csv_id_hack < N && b + _csv_id_hack < N) {
influence[a + _csv_id_hack][b + _csv_id_hack] += 1; // temp inf_values, calculating the total number of iteractions from "i" to "j"
received [b + _csv_id_hack] += 1;
//cout << "message from " << a + _csv_id_hack << " to " << b + _csv_id_hack << endl;
}
line_nr++;
}
infile.close();
cout << "File reading finished successfully." << endl;
ofstream outfile ("./experiments-counted/" + dataset_name + "_influenceCounted_" + to_string(N));
if (outfile.good()) {
// Influence value calculated as the ratio of iteractions from "i" node to "j" node, to the total number of iteractions to the "j" node.
for (int i=0; i<N; i++) {
for (int j=0; j<N; j++) {
//cout << "Influence values calculations, step: " << i*N+(j+1) << "/" << N*N << endl;
if (i == j) {
outfile << i << " " << j << " " << -1 << "\n";
influence[i][j] = -1;
} else if (influence[i][j] > 0) {
if (received[j] != 0) {
influence[i][j] = influence[i][j] / received[j];
} else if (influence[i][j] != 0) {
cout << "Received array error";
}
/*cout << i << "'s influence on " << j << " equals: " << influence[i][j] << endl;*/
outfile << i << " " << j << " " << influence[i][j] << "\n";
} else {
influence[i][j] = 0;
}
}
}
cout << "Compressed file saved successfully." << endl;
outfile.close();
} else {
throw std::invalid_argument("readData - File " + dataset_name + " not saved.");
}
} else {
throw std::invalid_argument("readData - File " + dataset_name + " not found.");
}
return influence;
}
void defineInfluenceArrayAndVectors (string dataset_name, int N, vector<float>& inf_values, vector<float>& inf_col_ind, vector<float>& inf_row_ptr, string _EXPERIMENT_ID) {
//cout << "File reading started." << endl;
ifstream infile("./experiments-counted/" + dataset_name + "_influenceCounted_" + to_string(N));
if (infile.good()) { // reading the already calculated influence values
int line_nr = 0;
string line;
float last_a = -1;
while (getline(infile, line)) {
cout << "Reading influence file, line nr: " << line_nr << endl;
istringstream iss(line);
float a, b, c;
if (!(iss >> a >> b >> c)) { break; } // error
if (c != 0) {
if (a != last_a) {
inf_row_ptr.push_back(inf_values.size());
//cout << "add row ptr: " << inf_values.size() << endl;
last_a = a;
}
inf_values.push_back(c);
//cout << "add value: " << c << endl;
inf_col_ind.push_back(b);
//cout << "add col ind: " << b << endl;
}
line_nr++;
}
infile.close();
} else { // calculating influnce values
infile.close();
vector <vector<float>> influence = readData(dataset_name, N, _EXPERIMENT_ID);
// inf_values, inf_col_ind, inf_row_ptr creation, based on the influence array
for (int i=0; i<N; i++) {
bool added = false;
for (int j=0; j<N; j++) {
//cout << "Influence of " << i << " on " << j << " is equal to: " << influence[i][j] << endl;
if (influence[i][j] != 0) {
if (!added) {
inf_row_ptr.push_back(inf_values.size());
//cout << "add row ptr: " << inf_values.size() << endl;
added = true;
}
inf_values.push_back(influence[i][j]);
//cout << "add value: " << influence[i][j] << endl;
inf_col_ind.push_back(j);
//cout << "add col ind: " << j << endl;
}
}
if (!added) {
//inf_row_ptr.push_back(-1);
}
}
/*cout << "\n\n size of influence array: " << sizeof(influence) + sizeof(float) * influence.capacity() * influence.capacity();
cout << "\n\n Total size of vectors: "
<< sizeof(inf_values) + sizeof(float) * inf_values.capacity()
+ sizeof(inf_col_ind) + sizeof(float) * inf_col_ind.capacity()
+ sizeof(inf_row_ptr) + sizeof(float) * inf_row_ptr.capacity() << "\n\n";*/
}
}
void createPopulation (int nrOfIndividuals, int N, int toFind, vector <vector<int>>& population) {
// creating random individuals within population
for (int i = 0; i<nrOfIndividuals; i++) {
vector<int> row;
population.push_back(row);
cout << "Creating individual " << i << " of " << nrOfIndividuals << endl;
for (int j = 0; j<toFind; j++) {
int rand_id = rand() % N;
bool alreadyAdded = true;
while (alreadyAdded) {
alreadyAdded = false;
for (int k=0; k<population[i].size(); k++) {
if (population[i][k] == rand_id) {
alreadyAdded = true;
rand_id = rand() % N;
}
}
}
//cout << "pushing: " << rand_id << endl;
population[i].push_back(rand_id);
}
}
}
void createPopulationSample (int nrOfIndividuals, int N, int toFind, vector <vector<int>>& population) {
// creating one individual - used as a sample e.g. for GPU vs CPU tests
vector<int> row;
population.push_back(row);
for (int x = 0; x<toFind; x++) {
population[0].push_back(x);
}
}
void setPopulationFitness (vector<vector<int>>& population, int nrOfIndividuals, int N, int inf_values_size, float& INFLUENCE_THRESHOLD, int STEPS_MAX, vector<float>& inf_values, vector<float>& inf_col_ind, vector<float>& inf_row_ptr, int toFind, vector<int>& fitness, int THREADS_PER_BLOCK) {
//bool activeNodesPerIndividual[nrOfIndividuals][N];
bool *dyn_activeNodesPerIndividual = new bool[nrOfIndividuals*N];
for (int i=0; i<nrOfIndividuals; i++) {
for (int j=0; j<N; j++) {
int index = N * i + j;
dyn_activeNodesPerIndividual[index] = false;
}
for (int j=0; j<toFind; j++) {
int index = N * i + population[i][j];
dyn_activeNodesPerIndividual[index] = true;
}
}
int active [nrOfIndividuals];
vector<int> changedIndividuals;
for (int i=0; i<nrOfIndividuals; i++) {
active[i] = toFind;
changedIndividuals.push_back(i);
}
int step_counter = 0;
while (step_counter < STEPS_MAX && changedIndividuals.size() > 0) {
//cout << "Step: " << step_counter << " / " << STEPS_MAX << endl;
int nrOfChangedIndividuals = changedIndividuals.size();
cout << "nrOfChangedIndividuals " << nrOfChangedIndividuals << endl;
F_TIME_START();
InfluenceSpreadPopulationStep (dyn_activeNodesPerIndividual, inf_values, inf_col_ind, inf_row_ptr, N, nrOfChangedIndividuals, inf_values_size, INFLUENCE_THRESHOLD, changedIndividuals);
F_TIME_END("host functions");
changedIndividuals.clear();
int curr_active;
for (int i=0; i<nrOfIndividuals; i++) {
curr_active = 0;
for (int j=0; j<N; j++) {
int index = N * i + j;
if (dyn_activeNodesPerIndividual[index]) {
curr_active++;
}
}
if (curr_active != active[i]) {
changedIndividuals.push_back(i);
}
active[i] = curr_active;
}
step_counter++;
}
for (int i = 0; i < nrOfIndividuals; i++) {
int individualFitness = 0;
for (int j = 0; j < N; j++) {
int index = N * i + j;
if (dyn_activeNodesPerIndividual[index]) {
individualFitness++;
//cout << "Activated " << j << endl;
}
}
//cout << "individualFitness: " << individualFitness << endl;
//cout << "toFind: " << toFind << endl;
// acceptable `error`
/*if (individualFitness-toFind < 0) {
cout << "# Crossover/mutation overlapping" << endl; // can happen because of random crossover and mutation
//coutIndividual(population, i);
}*/
//cout << "fitness Indiv: " << i << ": " << individualFitness-toFind << endl;
fitness.push_back(individualFitness-toFind);
}
}
void performPopulationSelection (vector<vector<int>>& population, int& nrOfIndividuals, int N, int inf_values_size, float& INFLUENCE_THRESHOLD, int& groupSize, int& STEPS_MAX, vector<float>& inf_values, vector<float>& inf_col_ind, vector<float>& inf_row_ptr, int& toFind, int& max_fitness_value, vector<int>& max_fitness_individual, int THREADS_PER_BLOCK) {
vector<int> fitness;
F_TIME_START();
setPopulationFitness(population, nrOfIndividuals, N, inf_values_size, INFLUENCE_THRESHOLD, STEPS_MAX, inf_values, inf_col_ind, inf_row_ptr, toFind, fitness, THREADS_PER_BLOCK);
F_TIME_END("selection - fitness count");
F_TIME_START();
vector<vector<int>> newPopulation;
while (newPopulation.size() != population.size()) {
vector<int> newGroup;
bool alreadyAdded[nrOfIndividuals];
for (int i=0; i<nrOfIndividuals; i++) {
alreadyAdded[i] = false;
}
for (int j=0; j<groupSize; j++) {
int randIndiv = rand() % nrOfIndividuals;
while (alreadyAdded[randIndiv]) {
randIndiv = rand() % nrOfIndividuals;
}
newGroup.push_back(randIndiv);
}
int curr_best_fitness = -1;
int curr_best_id = -1;
int currentFitness = -1;
for (int j=0; j<newGroup.size(); j++) {
currentFitness = fitness[newGroup[j]];
if (currentFitness > curr_best_fitness) {
curr_best_fitness = currentFitness;
curr_best_id = j;
}
}
newPopulation.push_back(population[newGroup[curr_best_id]]);
if (curr_best_fitness > max_fitness_value) {
max_fitness_individual = population[newGroup[curr_best_id]];
max_fitness_value = curr_best_fitness;
}
}
population = newPopulation;
F_TIME_END("selection - population swapping");
}
// TODO performCrossover on DEVICE (nrOfIndividuals/2 threads (from 0 to nr/2 - 1), ids: id*2, id*2+1
void performCrossover (vector<vector<int>>& population, int& nrOfIndividuals, float& crossover_ratio, int& toFind) {
float split_ratio = 0.5;
float split_point = split_ratio*toFind;
int id_first = -1;
int id_second = -1;
for (int i=0; i<nrOfIndividuals; i++) {
int cross = rand() % 100;
if (cross < crossover_ratio * 100) {
if (id_first == -1) {
id_first = i;
} else {
id_second = i;
}
}
if (id_second != -1) {
for (int j=0; j<split_point; j++) {
float temp = population[id_first][j];
population[id_first][j] = population[id_second][j];
population[id_second][j] = temp;
}
id_first = -1;
id_second = -1;
}
} // allows to node doubling (fitness = -1 can happen)
}
// TODO performMutation on DEVICE
void performMutation (vector<vector<int>>& population, int& nrOfIndividuals, float& mutation_ratio, float& mutation_potency, int& toFind, int N) {
for (int i=0; i<nrOfIndividuals; i++) {
int mutation = rand() % 100;
if (mutation < mutation_ratio * 100) {
for (int j=0; j<mutation_potency*toFind; j++) {
population[i][rand() % toFind] = rand() % N;
}
}
} // allows to node doubling (fitness = -1 can happen)
}
bool anyLimitReached(int resultBufferSize, float resultMinDiff, vector<int> &resultsBuffer, int generation, int generationsLimit, float timeLimit, int COMPUTATION_START_TIME, int result, int resultLimit) {
int now = duration_cast<milliseconds>(system_clock::now().time_since_epoch()).count();
float diff = (now - COMPUTATION_START_TIME) / 1000.0;
bool anyLimit =
(resultMinDiff > 0 && generation > resultBufferSize && result < resultsBuffer[0] * (1 + resultMinDiff))
|| (generationsLimit > 0 && generation >= generationsLimit)
|| (resultLimit > 0 && result >= resultLimit)
|| (timeLimit > 0 && diff >= timeLimit);
if (generation > 0) {
resultsBuffer.push_back(result);
}
if (generation > resultBufferSize) {
resultsBuffer.erase(resultsBuffer.begin());
//cout << endl << "Current resultsBuffer[0]: " << resultsBuffer[0] << endl;
}
return anyLimit;
}
vector<string> getFileNames (string path) {
DIR *pDIR;
struct dirent *entry;
vector<string> fileNames;
if (pDIR=opendir(path.c_str())) {
while (entry = readdir(pDIR)) {
if (strcmp(entry->d_name, ".") != 0 && strcmp(entry->d_name, "..") != 0) {
fileNames.push_back(entry->d_name);
}
}
closedir(pDIR);
}
return fileNames;
}
/* pearson, spearman */
float mean (vector<float> values) {
float sum = 0;
int size = values.size();
for (int i = 0; i < size; i++) {
sum += values[i];
}
return sum / size;
}
float pearson_numerator (vector<float> A, vector<float> B, float meanA, float meanB) {
float numerator = 0;
for (int i = 0; i < A.size(); i++) {
numerator += (A[i] - meanA) * (B[i] - meanB);
}
return numerator;
}
float pearson_denominator (vector<float> A, vector<float> B, float meanA, float meanB) {
float denominator1;
float denominator1_sum = 0;
float denominator2;
float denominator2_sum = 0;
for (int i = 0; i < A.size(); i++) {
denominator1_sum += pow(A[i] - meanA, 2);
}
for (int i = 0; i < B.size(); i++) {
denominator2_sum += pow(B[i] - meanB, 2);
}
denominator1 = pow(denominator1_sum, 0.5);
denominator2 = pow(denominator2_sum, 0.5);
if (denominator1 == 0 || denominator2 == 0)
cout << endl << endl << "##### ERROR: Denominator equal to 0 - probable cause: all result values are equal" << endl << endl;
return denominator1 * denominator2;
}
float pearson (vector<float> A, vector<float> B) {
if (A.size() != B.size()) {
cout << "ERROR - wrong vector lengths" << endl;
return -1;
}
float meanA = mean(A);
float meanB = mean(B);
float numerator = pearson_numerator(A, B, meanA, meanB);
float denominator = pearson_denominator(A, B, meanA, meanB);
return numerator / denominator;
}
vector<float> toRank (vector<float> A) {
vector<float> sorted = A;
sort(sorted.begin(), sorted.end());
vector<float> rank;
for (int i = 0; i < A.size(); i++) {
vector<int> positions;
for (int j = 0; j < A.size(); j++) {
if (sorted[j] == A[i]) {
positions.push_back(j);
}
}
float sum = 0;
float avg;
for (int j = 0; j < positions.size(); j++) {
sum += positions[j] + 1;
}
avg = sum / positions.size();
rank.push_back(avg);
//rank.push_back(positions[positions.size()-1] + 1); //libreoffice calc rank
}
/*
cout << "Ranking: " << endl;
for (int i = 0; i < rank.size(); i++) {
cout << rank[i] << ", ";
}
cout << endl << endl;
*/
return rank;
}
float spearman (vector<float> A, vector<float> B) {
vector<float> A_ranked = toRank(A);
vector<float> B_ranked = toRank(B);
return pearson(A_ranked, B_ranked);
}
int main (int argc, char* argv[]) {
srand (time(NULL));
coutGPUStatus();
string _EXPERIMENT_ID = argv[1];
int tests = 100;
float timeLimit = 6; //seconds
int generationsLimit = 0; //5;
int resultLimit = 0; //32;
int resultBufferSize = 10;
float resultMinDiff = 0; //0.01;
bool saveResults = true;
bool saveResultsCorrelation = true;
float INFLUENCE_THRESHOLD = 0.5;
int N_MAX = 1000;
int STEPS_MAX = 10000;
int TO_FIND_PERCENTAGE = 5;
int THREADS_PER_BLOCK = 1024;
/* Parameters */
//int groupSize = 20; // 10, 20, 30 // 2, 5, 10, 20, 50
//int nrOfIndividuals = (int)ceil(N/10.0); // N/20, N/10, N/5 // 100, 500 1k, 2k, 10k
//float crossover_ratio = 0.7; // 0.5, 0.7, 0.9 // 0.1, 0.3, 0.5, 0.7, 0.9
//float mutation_potency = 0.01; // 0.001, 0.01, 0.1 // 0.01, 0.02, 0.05, 0.1, 0.2
//float mutation_ratio = 0.9; // 0.75, 0.9, 0.95, // 0.1, 0.3, 0.5, 0.7, 0.9
vector<int> a_groupSize {10, 20, 30}; // 10, 20, 30
vector<int> a_nrOfIndividuals {12, 10, 8}; // N/12, N/10, N/8
vector<float> a_crossover_ratio {0.6, 0.7, 0.8}; // 0.6, 0.7, 0.8
vector<float> a_mutation_potency {0.001, 0.01, 0.1}; // 0.001, 0.01, 0.1
vector<float> a_mutation_ratio {0.7, 0.8, 0.9}; // 0.7, 0.8, 0.9
int parameters_sets = a_groupSize.size() * a_nrOfIndividuals.size() * a_crossover_ratio.size() * a_mutation_potency.size() * a_mutation_ratio.size();
vector<string> datasets = getFileNames("./experiments_" + _EXPERIMENT_ID);
/* DEBUG */
int debug_nrOfIndividuals;
bool debug = true;
if (debug) {
tests = 10;
N_MAX = 1000;
THREADS_PER_BLOCK = 1024;
debug_nrOfIndividuals = -1; // -1 - the same as if it wasn't a debug mode (so devides N by a_nrOfIndividuals to get indivnr)
// tests: 10, debug_nrOfIndividuals: -1, generationsLimit: 1, THREADS_PER_BLOCK: 1024, default parameters, facebook
/* 100: 7 in 1ms, 500: 46 in 10ms, 1000: 88 in 53ms */
timeLimit = 0;
generationsLimit = 5; // 5 - 80s
resultLimit = 0;
resultMinDiff = 0;
saveResults = true;//false;
saveResultsCorrelation = true;//false;
a_groupSize = {20};
a_nrOfIndividuals = {8};
a_crossover_ratio = {0.7};
a_mutation_potency = {0.01};
a_mutation_ratio = {0.9};
parameters_sets = a_groupSize.size() * a_nrOfIndividuals.size() * a_crossover_ratio.size() * a_mutation_potency.size() * a_mutation_ratio.size();
//datasets = {"facebook-46952"};
//datasets = {"BA-1000-1-3.csv"};
datasets = {"ER-1000-0.05-10.csv"};
//datasets = getFileNames("./experiments_" + _EXPERIMENT_ID);
}
/*
N = 1000
INDIVIDUALS = 1000
THREADS_PER_BLOCK = 192
1 individuals - 0.056s
10 individuals - 0.081s
100 individuals - 0.265s
1000 individuals - 2.483s
THREADS_PER_BLOCK = 512
1000 individuals - 2.423s
THREADS_PER_BLOCK = 1024
1000 individuals - 2.481s
N = max (~47k for facebook)
THREADS_PER_BLOCK = 512
100 individuals - 5.08s
*/
vector<vector<float>> results;
for (int i=0; i<datasets.size(); i++) {
vector<float> row(parameters_sets, -1);
results.push_back(row);
}
for (int file_id=0; file_id<datasets.size(); file_id++) {
int dataset_id = file_id; //TODO to refactor
string dataset_name = datasets[file_id];
stringstream ssname(dataset_name);
string token;
getline(ssname, token, '-');
getline(ssname, token, '-');
int maxSize = stoi(token);
int N = min(N_MAX, maxSize);
int toFind = (int)ceil(float(TO_FIND_PERCENTAGE * N) / 100.0);
// using ofstream constructors.
std::ofstream outfile("results_" + dataset_name + "_" + _EXPERIMENT_ID + "_" + ".xls");
if (saveResults) {
outfile << "<?xml version='1.0'?>" << std::endl;
outfile << "<Workbook xmlns='urn:schemas-microsoft-com:office:spreadsheet'" << std::endl;
outfile << " xmlns:o='urn:schemas-microsoft-com:office:office'" << std::endl;
outfile << " xmlns:x='urn:schemas-microsoft-com:office:excel'" << std::endl;
outfile << " xmlns:ss='urn:schemas-microsoft-com:office:spreadsheet'" << std::endl;
outfile << " xmlns:html='http://www.w3.org/TR/REC-html40'>" << std::endl;
outfile << " <Worksheet ss:Name='Sheet1'>" << std::endl;
outfile << " <Table>" << std::endl;
outfile << " <Row>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>Dataset</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>Test nr</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>groupSize</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>nrOfIndividuals</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>crossover_ratio</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>mutation_potency</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>mutation_ratio</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>Generations</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>Result</Data></Cell>" << std::endl;
outfile << " </Row>" << std::endl;
}
vector <float> inf_col_ind;
vector <float> inf_row_ptr;
vector <float> inf_values;
defineInfluenceArrayAndVectors(dataset_name, N, inf_values, inf_col_ind, inf_row_ptr, _EXPERIMENT_ID);
int inf_values_size = inf_values.size();
int parameters_set = 1;
for_each(a_groupSize.begin(), a_groupSize.end(), [&] (int groupSize) {
for_each(a_nrOfIndividuals.begin(), a_nrOfIndividuals.end(), [&] (int nrOfIndividualsRaw) {
int nrOfIndividuals = (int)ceil(N/nrOfIndividualsRaw);
if (debug && debug_nrOfIndividuals != -1) {
nrOfIndividuals = debug_nrOfIndividuals;
}
for_each(a_crossover_ratio.begin(), a_crossover_ratio.end(), [&] (float crossover_ratio) {
for_each(a_mutation_potency.begin(), a_mutation_potency.end(), [&] (float mutation_potency) {
for_each(a_mutation_ratio.begin(), a_mutation_ratio.end(), [&] (float mutation_ratio) {
float testsResultsSum = 0;
float testsGenerationsSum = 0;
float testsTimeSum = 0;
for (int test = 0; test < tests; test++) {
vector <int> max_fitness_individual;
vector <vector<int>> population;
int max_fitness_value = -1;
int progressBarLength = 10;
int generation = 0;
vector<int> resultsBuffer;
createPopulation(nrOfIndividuals, N, toFind, population);
//createPopulationSample(nrOfIndividuals, N, toFind, population);
//coutPopulation(population);
int COMPUTATION_START_TIME = duration_cast<milliseconds>(system_clock::now().time_since_epoch()).count();
while (!anyLimitReached(resultBufferSize, resultMinDiff, resultsBuffer, generation, generationsLimit, timeLimit, COMPUTATION_START_TIME, max_fitness_value, resultLimit)) {
//coutGPUStatus();
F_TIME_START();
performPopulationSelection(population, nrOfIndividuals, N, inf_values_size, INFLUENCE_THRESHOLD, groupSize, STEPS_MAX, inf_values, inf_col_ind, inf_row_ptr, toFind, max_fitness_value, max_fitness_individual, THREADS_PER_BLOCK);
F_TIME_END("selection");
F_TIME_START();
performCrossover(population, nrOfIndividuals, crossover_ratio, toFind);
F_TIME_END("crossover");
F_TIME_START();
performMutation(population, nrOfIndividuals, mutation_ratio, mutation_potency, toFind, N);
F_TIME_END("mutation");
//coutResult(generation, max_fitness_value);
generation++;
}
int COMPUTATION_END_TIME = duration_cast<milliseconds>(system_clock::now().time_since_epoch()).count();
int COMPUTATION_DURATION = COMPUTATION_END_TIME - COMPUTATION_START_TIME;
cout << endl << "[FINISHED] test: " << test+1 << "/" << tests
<< " for parameters set nr: " << parameters_set << "/" << parameters_sets
<< " for dataset_id: " << dataset_id+1 << "/" << datasets.size()
<< " in: " << COMPUTATION_DURATION / 1000.0 << "s";
cout << endl;
coutGPUStatus();
cout << endl;
if (saveResults) {
outfile << " <Row>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(parameters_set) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(test+1) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(groupSize) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(nrOfIndividuals) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(crossover_ratio) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(mutation_potency) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(mutation_ratio) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(generation) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(max_fitness_value) + "</Data></Cell>" << std::endl;
outfile << " </Row>" << std::endl;
}
//cout << endl << "result " << test+1 << ": " << max_fitness_value << endl;
testsResultsSum += max_fitness_value;
testsGenerationsSum += generation;
testsTimeSum += COMPUTATION_DURATION;
/*cout << "Best individual found: " << endl;
for (int i=0; i<max_fitness_individual.size(); i++) {
cout << max_fitness_individual[i] << ", ";
}*/
//cout << endl << endl << "This group can activate " << max_fitness_value << " others";
//cout << endl << "Time elapsed: " << (time2 - COMPUTATION_START_TIME) / 1000.0 << "s" << endl;
} // TEST
float finalResult = std::round(testsResultsSum / tests);
float finalGenerations = std::round(testsGenerationsSum / tests);
float finalTime = std::round(testsTimeSum / tests);
cout << endl << "Final result avg: " << finalResult << " in avg " << finalTime / 1000.0 << "s" << endl;
results[file_id][parameters_set-1] = finalResult;
if (saveResults) {
outfile << " <Row>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(parameters_set) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>AVG </Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(groupSize) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(nrOfIndividuals) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(crossover_ratio) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(mutation_potency) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(mutation_ratio) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(finalGenerations) + "</Data></Cell>" << std::endl;
outfile << " <Cell><Data ss:Type='Number'>" + to_string(finalResult) + "</Data></Cell>" << std::endl;
outfile << " </Row>" << std::endl;
}
parameters_set++;
});
});
});
});
});
if (saveResults) {
outfile << " </Table>" << std::endl;
outfile << " </Worksheet>" << std::endl;
outfile << "</Workbook>" << std::endl;
}
outfile.close();
}
cout << endl << endl << "*** RESULTS ***" << endl;
for (int i=0; i<datasets.size(); i++) {
for (int j=0; j<parameters_sets; j++) {
cout << results[i][j] << ", ";
}
cout << endl;
}
if (saveResultsCorrelation) {
// using ofstream constructors.
std::ofstream outfile("results_correlation_" + _EXPERIMENT_ID + "_.xls");
outfile << "<?xml version='1.0'?>" << std::endl;
outfile << "<Workbook xmlns='urn:schemas-microsoft-com:office:spreadsheet'" << std::endl;
outfile << " xmlns:o='urn:schemas-microsoft-com:office:office'" << std::endl;
outfile << " xmlns:x='urn:schemas-microsoft-com:office:excel'" << std::endl;
outfile << " xmlns:ss='urn:schemas-microsoft-com:office:spreadsheet'" << std::endl;
outfile << " xmlns:html='http://www.w3.org/TR/REC-html40'>" << std::endl;
outfile << " <Worksheet ss:Name='Sheet1'>" << std::endl;
outfile << " <Table>" << std::endl;
outfile << " <Row>" << std::endl;
outfile << " <Cell></Cell>" << std::endl;
for (int i=0; i<datasets.size(); i++) {
outfile << " <Cell><Data ss:Type='String'>" + datasets[i] + "</Data></Cell>" << std::endl;
}
outfile << " </Row>" << std::endl;
for (int i=0; i<datasets.size(); i++) {
outfile << " <Row>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>" + datasets[i] + "</Data></Cell>" << std::endl;
for (int j=0; j<datasets.size(); j++) {
if (j > i) {
outfile << " <Cell><Data ss:Type='Number'>" + to_string(pearson(results[i], results[j])) + "</Data></Cell>" << std::endl;
} else {
outfile << " <Cell></Cell>" << std::endl;
}
}
outfile << " </Row>" << std::endl;
}
outfile << " <Row></Row>" << std::endl;
outfile << " <Row></Row>" << std::endl;
outfile << " <Row></Row>" << std::endl;
outfile << " <Row>" << std::endl;
outfile << " <Cell></Cell>" << std::endl;
for (int i=0; i<datasets.size(); i++) {
outfile << " <Cell><Data ss:Type='String'>" + datasets[i] + "</Data></Cell>" << std::endl;
}
outfile << " </Row>" << std::endl;
for (int i=0; i<datasets.size(); i++) {
outfile << " <Row>" << std::endl;
outfile << " <Cell><Data ss:Type='String'>" + datasets[i] + "</Data></Cell>" << std::endl;
for (int j=0; j<datasets.size(); j++) {
if (j > i) {
outfile << " <Cell><Data ss:Type='Number'>" + to_string(spearman(results[i], results[j])) + "</Data></Cell>" << std::endl;
} else {
outfile << " <Cell></Cell>" << std::endl;
}
}
outfile << " </Row>" << std::endl;
}
outfile << " </Table>" << std::endl;
outfile << " </Worksheet>" << std::endl;
outfile << "</Workbook>" << std::endl;
outfile.close();
}
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void fill( float4 *localbuf, float val, float4* ptr, int offset, int N ) {
int idx= blockDim.x * blockIdx.x + threadIdx.x;
if( idx < N ) {
float4 t = localbuf[ idx ];
t.x += val;
t.y += val;
t.z += val;
t.w += val;
ptr[ offset + idx ] = t;
}
} | code for sm_80
Function : _Z4fillP6float4fS0_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0205 */
/*0090*/ LDG.E.128 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea2000c1e1d00 */
/*00a0*/ IADD3 R4, R0, c[0x0][0x178], RZ ; /* 0x00005e0000047a10 */
/* 0x000fca0007ffe0ff */
/*00b0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fc800078e0205 */
/*00c0*/ FADD R11, R11, c[0x0][0x168] ; /* 0x00005a000b0b7621 */
/* 0x004fe40000000000 */
/*00d0*/ FADD R10, R10, c[0x0][0x168] ; /* 0x00005a000a0a7621 */
/* 0x000fe40000000000 */
/*00e0*/ FADD R9, R9, c[0x0][0x168] ; /* 0x00005a0009097621 */
/* 0x000fe40000000000 */
/*00f0*/ FADD R8, R8, c[0x0][0x168] ; /* 0x00005a0008087621 */
/* 0x000fca0000000000 */
/*0100*/ STG.E.128 [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x000fe2000c101d04 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void fill( float4 *localbuf, float val, float4* ptr, int offset, int N ) {
int idx= blockDim.x * blockIdx.x + threadIdx.x;
if( idx < N ) {
float4 t = localbuf[ idx ];
t.x += val;
t.y += val;
t.z += val;
t.w += val;
ptr[ offset + idx ] = t;
}
} | .file "tmpxft_001156ec_00000000-6_fill.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z4fillP6float4fS0_iiP6float4fS0_ii
.type _Z35__device_stub__Z4fillP6float4fS0_iiP6float4fS0_ii, @function
_Z35__device_stub__Z4fillP6float4fS0_iiP6float4fS0_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movss %xmm0, 20(%rsp)
movq %rsi, 8(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4fillP6float4fS0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z4fillP6float4fS0_iiP6float4fS0_ii, .-_Z35__device_stub__Z4fillP6float4fS0_iiP6float4fS0_ii
.globl _Z4fillP6float4fS0_ii
.type _Z4fillP6float4fS0_ii, @function
_Z4fillP6float4fS0_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z4fillP6float4fS0_iiP6float4fS0_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4fillP6float4fS0_ii, .-_Z4fillP6float4fS0_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4fillP6float4fS0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4fillP6float4fS0_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void fill( float4 *localbuf, float val, float4* ptr, int offset, int N ) {
int idx= blockDim.x * blockIdx.x + threadIdx.x;
if( idx < N ) {
float4 t = localbuf[ idx ];
t.x += val;
t.y += val;
t.z += val;
t.w += val;
ptr[ offset + idx ] = t;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void fill( float4 *localbuf, float val, float4* ptr, int offset, int N ) {
int idx= blockDim.x * blockIdx.x + threadIdx.x;
if( idx < N ) {
float4 t = localbuf[ idx ];
t.x += val;
t.y += val;
t.z += val;
t.w += val;
ptr[ offset + idx ] = t;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void fill( float4 *localbuf, float val, float4* ptr, int offset, int N ) {
int idx= blockDim.x * blockIdx.x + threadIdx.x;
if( idx < N ) {
float4 t = localbuf[ idx ];
t.x += val;
t.y += val;
t.z += val;
t.w += val;
ptr[ offset + idx ] = t;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4fillP15HIP_vector_typeIfLj4EEfS1_ii
.globl _Z4fillP15HIP_vector_typeIfLj4EEfS1_ii
.p2align 8
.type _Z4fillP15HIP_vector_typeIfLj4EEfS1_ii,@function
_Z4fillP15HIP_vector_typeIfLj4EEfS1_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_clause 0x2
s_load_b32 s6, s[0:1], 0x8
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b32 s0, s[0:1], 0x18
v_lshlrev_b64 v[2:3], 4, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b128 v[2:5], v[2:3], off
v_add_nc_u32_e32 v0, s0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[6:7], 4, v[0:1]
s_waitcnt vmcnt(0)
v_dual_add_f32 v1, s6, v3 :: v_dual_add_f32 v0, s6, v2
v_dual_add_f32 v3, s6, v5 :: v_dual_add_f32 v2, s6, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v7, vcc_lo
global_store_b128 v[4:5], v[0:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4fillP15HIP_vector_typeIfLj4EEfS1_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4fillP15HIP_vector_typeIfLj4EEfS1_ii, .Lfunc_end0-_Z4fillP15HIP_vector_typeIfLj4EEfS1_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4fillP15HIP_vector_typeIfLj4EEfS1_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4fillP15HIP_vector_typeIfLj4EEfS1_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void fill( float4 *localbuf, float val, float4* ptr, int offset, int N ) {
int idx= blockDim.x * blockIdx.x + threadIdx.x;
if( idx < N ) {
float4 t = localbuf[ idx ];
t.x += val;
t.y += val;
t.z += val;
t.w += val;
ptr[ offset + idx ] = t;
}
} | .text
.file "fill.hip"
.globl _Z19__device_stub__fillP15HIP_vector_typeIfLj4EEfS1_ii # -- Begin function _Z19__device_stub__fillP15HIP_vector_typeIfLj4EEfS1_ii
.p2align 4, 0x90
.type _Z19__device_stub__fillP15HIP_vector_typeIfLj4EEfS1_ii,@function
_Z19__device_stub__fillP15HIP_vector_typeIfLj4EEfS1_ii: # @_Z19__device_stub__fillP15HIP_vector_typeIfLj4EEfS1_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movss %xmm0, 12(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4fillP15HIP_vector_typeIfLj4EEfS1_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__fillP15HIP_vector_typeIfLj4EEfS1_ii, .Lfunc_end0-_Z19__device_stub__fillP15HIP_vector_typeIfLj4EEfS1_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4fillP15HIP_vector_typeIfLj4EEfS1_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4fillP15HIP_vector_typeIfLj4EEfS1_ii,@object # @_Z4fillP15HIP_vector_typeIfLj4EEfS1_ii
.section .rodata,"a",@progbits
.globl _Z4fillP15HIP_vector_typeIfLj4EEfS1_ii
.p2align 3, 0x0
_Z4fillP15HIP_vector_typeIfLj4EEfS1_ii:
.quad _Z19__device_stub__fillP15HIP_vector_typeIfLj4EEfS1_ii
.size _Z4fillP15HIP_vector_typeIfLj4EEfS1_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4fillP15HIP_vector_typeIfLj4EEfS1_ii"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__fillP15HIP_vector_typeIfLj4EEfS1_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4fillP15HIP_vector_typeIfLj4EEfS1_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4fillP6float4fS0_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0205 */
/*0090*/ LDG.E.128 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea2000c1e1d00 */
/*00a0*/ IADD3 R4, R0, c[0x0][0x178], RZ ; /* 0x00005e0000047a10 */
/* 0x000fca0007ffe0ff */
/*00b0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fc800078e0205 */
/*00c0*/ FADD R11, R11, c[0x0][0x168] ; /* 0x00005a000b0b7621 */
/* 0x004fe40000000000 */
/*00d0*/ FADD R10, R10, c[0x0][0x168] ; /* 0x00005a000a0a7621 */
/* 0x000fe40000000000 */
/*00e0*/ FADD R9, R9, c[0x0][0x168] ; /* 0x00005a0009097621 */
/* 0x000fe40000000000 */
/*00f0*/ FADD R8, R8, c[0x0][0x168] ; /* 0x00005a0008087621 */
/* 0x000fca0000000000 */
/*0100*/ STG.E.128 [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x000fe2000c101d04 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4fillP15HIP_vector_typeIfLj4EEfS1_ii
.globl _Z4fillP15HIP_vector_typeIfLj4EEfS1_ii
.p2align 8
.type _Z4fillP15HIP_vector_typeIfLj4EEfS1_ii,@function
_Z4fillP15HIP_vector_typeIfLj4EEfS1_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_clause 0x2
s_load_b32 s6, s[0:1], 0x8
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b32 s0, s[0:1], 0x18
v_lshlrev_b64 v[2:3], 4, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b128 v[2:5], v[2:3], off
v_add_nc_u32_e32 v0, s0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[6:7], 4, v[0:1]
s_waitcnt vmcnt(0)
v_dual_add_f32 v1, s6, v3 :: v_dual_add_f32 v0, s6, v2
v_dual_add_f32 v3, s6, v5 :: v_dual_add_f32 v2, s6, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v7, vcc_lo
global_store_b128 v[4:5], v[0:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4fillP15HIP_vector_typeIfLj4EEfS1_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4fillP15HIP_vector_typeIfLj4EEfS1_ii, .Lfunc_end0-_Z4fillP15HIP_vector_typeIfLj4EEfS1_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4fillP15HIP_vector_typeIfLj4EEfS1_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4fillP15HIP_vector_typeIfLj4EEfS1_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001156ec_00000000-6_fill.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z4fillP6float4fS0_iiP6float4fS0_ii
.type _Z35__device_stub__Z4fillP6float4fS0_iiP6float4fS0_ii, @function
_Z35__device_stub__Z4fillP6float4fS0_iiP6float4fS0_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movss %xmm0, 20(%rsp)
movq %rsi, 8(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4fillP6float4fS0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z4fillP6float4fS0_iiP6float4fS0_ii, .-_Z35__device_stub__Z4fillP6float4fS0_iiP6float4fS0_ii
.globl _Z4fillP6float4fS0_ii
.type _Z4fillP6float4fS0_ii, @function
_Z4fillP6float4fS0_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z4fillP6float4fS0_iiP6float4fS0_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4fillP6float4fS0_ii, .-_Z4fillP6float4fS0_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4fillP6float4fS0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4fillP6float4fS0_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "fill.hip"
.globl _Z19__device_stub__fillP15HIP_vector_typeIfLj4EEfS1_ii # -- Begin function _Z19__device_stub__fillP15HIP_vector_typeIfLj4EEfS1_ii
.p2align 4, 0x90
.type _Z19__device_stub__fillP15HIP_vector_typeIfLj4EEfS1_ii,@function
_Z19__device_stub__fillP15HIP_vector_typeIfLj4EEfS1_ii: # @_Z19__device_stub__fillP15HIP_vector_typeIfLj4EEfS1_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movss %xmm0, 12(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4fillP15HIP_vector_typeIfLj4EEfS1_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__fillP15HIP_vector_typeIfLj4EEfS1_ii, .Lfunc_end0-_Z19__device_stub__fillP15HIP_vector_typeIfLj4EEfS1_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4fillP15HIP_vector_typeIfLj4EEfS1_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4fillP15HIP_vector_typeIfLj4EEfS1_ii,@object # @_Z4fillP15HIP_vector_typeIfLj4EEfS1_ii
.section .rodata,"a",@progbits
.globl _Z4fillP15HIP_vector_typeIfLj4EEfS1_ii
.p2align 3, 0x0
_Z4fillP15HIP_vector_typeIfLj4EEfS1_ii:
.quad _Z19__device_stub__fillP15HIP_vector_typeIfLj4EEfS1_ii
.size _Z4fillP15HIP_vector_typeIfLj4EEfS1_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4fillP15HIP_vector_typeIfLj4EEfS1_ii"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__fillP15HIP_vector_typeIfLj4EEfS1_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4fillP15HIP_vector_typeIfLj4EEfS1_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // input: iou_matrix, [n, n], points_sampling, [n, npoint], merge function, 0:union, 1: intersection
// min_keep_num
// output: keep_inds [n, n], 0/1
// nmsed_points_sample: [n, npoint], 0/1
#include <stdio.h>
#include <iostream>
#include <vector>
#include <time.h>
#define CUDA_CHECK(condition) \
/* Code block avoids redefinition of cudaError_t error */ \
do { \
cudaError_t error = condition; \
if (error != cudaSuccess) { \
std::cout << cudaGetErrorString(error) << std::endl; \
} \
} while (0)
const int block_num = 512;
#define DIVUP(m,n) ((m) / (n) + ((m) % (n) > 0))
const int threadsPerBlock = sizeof(unsigned long long) * 8;
__global__ void points_inside_boxes(const int n, const int npoint, const float *points, const float* anchors, int* points_sample_mask){
// n: boxes_num, npoint: points_num, points: points_num x 3, anchors: boxes_num, 6
// return: points_sample_mask: boxes_num x npoint
for (int batch_idx=blockIdx.x; batch_idx < n; batch_idx += gridDim.x){
// xmin, ymin, zmin, xmax, ymax, zmax
const float* cur_anchors = anchors + batch_idx * 6;
int *cur_points_sample_mask = points_sample_mask + batch_idx * npoint;
int x_index = threadIdx.x;
int x_stride = blockDim.x;
const float cur_anchors_xmin = cur_anchors[0] - cur_anchors[3] / 2.;
const float cur_anchors_ymin = cur_anchors[1] - cur_anchors[4];
const float cur_anchors_zmin = cur_anchors[2] - cur_anchors[5] / 2.;
const float cur_anchors_xmax = cur_anchors[0] + cur_anchors[3] / 2.;
const float cur_anchors_ymax = cur_anchors[1];
const float cur_anchors_zmax = cur_anchors[2] + cur_anchors[5] / 2.;
for (int points_idx = x_index; points_idx < npoint; points_idx += x_stride){
const float* cur_points = points + points_idx * 3;
const float cur_points_x = cur_points[0];
const float cur_points_y = cur_points[1];
const float cur_points_z = cur_points[2];
int _x = (cur_points_x >= cur_anchors_xmin) * (cur_points_x <= cur_anchors_xmax);
int _y = (cur_points_y >= cur_anchors_ymin) * (cur_points_y <= cur_anchors_ymax);
int _z = (cur_points_z >= cur_anchors_zmin) * (cur_points_z <= cur_anchors_zmax);
cur_points_sample_mask[points_idx] = _x * _y * _z;
}
}
}
__global__ void points_iou_kernel(const int n, const int npoint, const int* points_sample_mask, float* iou_matrix){
// points_sample_mask, [n, npoint], 0/1
// iou_matrix, [n, n]
for (int x_num_idx=blockIdx.x; x_num_idx<n; x_num_idx+=gridDim.x){
for(int y_num_idx=blockIdx.y; y_num_idx<n; y_num_idx+=gridDim.y){
const int* x_points_sample_mask = points_sample_mask + x_num_idx * npoint;
const int* y_points_sample_mask = points_sample_mask + y_num_idx * npoint;
int x_index = threadIdx.x;
int x_stride = blockDim.x;
__shared__ float intersect_list[threadsPerBlock];
__shared__ float union_list[threadsPerBlock];
// first initialize intersect_list and union_list by zero
intersect_list[x_index] = 0;
union_list[x_index] = 0;
__syncthreads();
for(int i_x=x_index; i_x<npoint; i_x+= x_stride){
intersect_list[x_index] = intersect_list[x_index] + float(x_points_sample_mask[i_x] && y_points_sample_mask[i_x]);
union_list[x_index] = union_list[x_index] + float(x_points_sample_mask[i_x] || y_points_sample_mask[i_x]);
}
__syncthreads();
// after calc the intersect
// then get the sum
__shared__ float intersect_sum;
__shared__ float union_sum;
intersect_sum = 0;
union_sum = 0;
__syncthreads();
atomicAdd(&intersect_sum, intersect_list[x_index]);
atomicAdd(&union_sum, union_list[x_index]);
__syncthreads();
float iou = intersect_sum / max(union_sum, 1.);
iou_matrix[x_num_idx * n + y_num_idx] = iou;
}
}
}
__device__ inline float devIou(const int *a, const int *b, int npoint) {
// a:[npoint], b[npoint], then calc the iou
float intersect = 0;
float union_sect = 0;
for (int i = 0; i < npoint; i ++){
intersect += a[i] && b[i];
union_sect += a[i] || b[i];
}
return intersect / union_sect;
}
__global__ void points_nms_block_kernel(const int n, const int npoint, const int merge_function, const float iou_thresh, const int*points_sample, unsigned long long *keep_inds, int *nmsed_points_sample){
const int row_start = blockIdx.y;
const int col_start = blockIdx.x;
const int row_size = min(n - row_start * threadsPerBlock, threadsPerBlock);
const int col_size = min(n - col_start * threadsPerBlock, threadsPerBlock);
const int* col_points_sample = points_sample + (threadsPerBlock * col_start) * npoint;
if (threadIdx.x < row_size){
const int cur_box_idx = threadsPerBlock * row_start + threadIdx.x;
const int *cur_points_sample = points_sample + cur_box_idx * npoint;
int *cur_nmsed_points_sample = nmsed_points_sample + cur_box_idx * npoint;
int i = 0;
unsigned long long t = 0;
int start = 0;
if (row_start == col_start){
start = threadIdx.x + 1;
}
for (i = start; i < col_size; i ++){
if (devIou(cur_points_sample, col_points_sample + i * npoint, npoint) > iou_thresh) {
// merge the nmsed_points_sample
const int *merged_col_points_sample = col_points_sample + i * npoint;
if (merge_function == 0){
for (int j = 0; j < npoint; j++){
atomicOr(&cur_nmsed_points_sample[j], merged_col_points_sample[j]);
}
}
else if (merge_function == 1){
for (int j = 0; j < npoint; j++){
atomicAnd(&cur_nmsed_points_sample[j], merged_col_points_sample[j]);
}
}
t |= 1ULL << i;
}
}
const int col_blocks = DIVUP(n, threadsPerBlock);
// keep_inds, [col_blocks, threadsPerBlock]
keep_inds[cur_box_idx * col_blocks + col_start] = t;
}
}
__global__ void points_nms_kernel(const int n, const int npoint, const int merge_function, float iou_thresh, const float *iou_matrix, const int *points_sample, int *keep_inds, int *nmsed_points_sample) {
// nmsed_points_sample [n, npoint]
for (int x_num_idx=blockIdx.x; x_num_idx<n; x_num_idx+=gridDim.x){
for(int y_num_idx=blockIdx.y; y_num_idx<n; y_num_idx+=gridDim.y){
if (x_num_idx == y_num_idx)
continue;
// const int* x_points_sample = points_sample + x_num_idx * npoint;
const int* y_points_sample = points_sample + y_num_idx * npoint;
const float* x_iou_matrix = iou_matrix + x_num_idx * n;
int *x_keep_inds = keep_inds + x_num_idx * n;
int* x_nmsed_points_sample = nmsed_points_sample + x_num_idx * npoint;
int index = threadIdx.x;
int stride = blockDim.x;
float cur_iou = x_iou_matrix[y_num_idx];
if (cur_iou > iou_thresh){
// merge them togethor
x_keep_inds[y_num_idx] = 1;
for (int i=index;i<npoint;i+=stride){
// merge the result
if (merge_function == 0){
// union the two vector
atomicOr(&x_nmsed_points_sample[i], y_points_sample[i]);
}
else if(merge_function == 1){
atomicAnd(&x_nmsed_points_sample[i], y_points_sample[i]);
}
else{
continue;
}
}
}
}
}
}
__global__ void points_nms_sample(const int n, const int npoint, int merge_function, int* nmsed_points_sample_media, int* nmsed_points_sample){
for (int num_idx=blockIdx.x; num_idx<n; num_idx+=gridDim.x){
int *batch_nmsed_points_sample_media = nmsed_points_sample_media + num_idx * n *npoint;
int *batch_nmsed_points_sample = nmsed_points_sample + num_idx * npoint;
int index = threadIdx.x;
int stride = blockDim.x;
for (int i=index; i<n; i+=stride){
for(int j=0; j < npoint; j++){
if (merge_function == 0 || merge_function == 2){
// union or keep the origin
atomicOr(&batch_nmsed_points_sample[j], batch_nmsed_points_sample_media[i * npoint + j]);
// batch_nmsed_points_sample[j] = batch_nmsed_points_sample[j] + batch_nmsed_points_sample_media[i * npoint + j];
}
else if (merge_function == 1){
atomicAnd(&batch_nmsed_points_sample[j], batch_nmsed_points_sample_media[i * npoint + j]);
// batch_nmsed_points_sample[j] = batch_nmsed_points_sample[j] && batch_nmsed_points_sample_media[i * npoint + j];
}
}
}
}
}
void points_iou_gpu(const int n, const int npoint, const int* points_sample_mask, float* iou_matrix){
dim3 blocks(512, 512);
points_iou_kernel<<<blocks, threadsPerBlock>>>(n, npoint, points_sample_mask, iou_matrix);
// std::cout << "Iou Caluculating Done!!" << std::endl;
}
void points_inside_boxes_gpu(const int n, const int npoint, const float *points, const float* anchors, int* points_sample_mask){
CUDA_CHECK(cudaMemset(points_sample_mask, 1, n * npoint * sizeof(int)));
points_inside_boxes<<<512, threadsPerBlock>>>(n, npoint, points, anchors, points_sample_mask);
}
void points_nms_block_gpu(const int n, const int npoint, const int merge_function, const float iou_thresh, const int num_to_keep, const int *points_sample, int *keep_inds, int *nmsed_points_sample){
unsigned long long* mask_dev = NULL;
const int col_blocks = DIVUP(n, threadsPerBlock);
CUDA_CHECK(cudaMalloc(&mask_dev, n * col_blocks * sizeof(unsigned long long)));
CUDA_CHECK(cudaMemcpy(nmsed_points_sample, points_sample, sizeof(int) * n * npoint, cudaMemcpyDeviceToDevice));
time_t c_start, c_end;
c_start = clock();
cudaEvent_t start, stop; // variables that holds 2 events
float time; // Variable that will hold the time
cudaEventCreate(&start); // creating the event 1
cudaEventCreate(&stop); // creating the event 2
cudaEventRecord(start, 0); // start measuring the time
dim3 blocks(DIVUP(n, threadsPerBlock),
DIVUP(n, threadsPerBlock));
dim3 threads(threadsPerBlock);
points_nms_block_kernel<<<blocks, threads>>>(n, npoint, merge_function, iou_thresh, points_sample, mask_dev, nmsed_points_sample);
c_end = clock();
cudaEventRecord(stop, 0); // Stop time measuring
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
std::cout << difftime(c_end,c_start) << std::endl;
std::cout << time << std::endl;
std::cout << "Finished main working !!!" << std::endl;
c_start = clock();
std::vector<unsigned long long> mask_host(n * col_blocks);
cudaMemcpy(&mask_host[0],
mask_dev,
sizeof(unsigned long long) * n * col_blocks,
cudaMemcpyDeviceToHost);
c_end = clock();
std::cout << difftime(c_end,c_start) << std::endl;
std::cout << "Finished copying" << std::endl;
c_start = clock();
std::vector<unsigned long long> remv(col_blocks);
memset(&remv[0], 0, sizeof(unsigned long long) * col_blocks);
std::vector<int> cpu_keep_inds(n);
memset(&cpu_keep_inds[0], -1, sizeof(int) * num_to_keep);
std::cout << "setting the output to -1" << std::endl;
int keeping_num = 0;
for (int i=0; i < n; i ++){
int nblock = i / threadsPerBlock;
int inblock = i % threadsPerBlock;
if (!(remv[nblock] & (1ULL << inblock))){
cpu_keep_inds[keeping_num++] = i;
if (keeping_num >= num_to_keep)
break;
unsigned long long *p = &mask_host[0] + i * col_blocks;
for (int j = nblock; j < col_blocks; j ++){
remv[j] |= p[j];
}
}
}
c_end = clock();
std::cout << difftime(c_end,c_start) << std::endl;
CUDA_CHECK(cudaFree(mask_dev));
CUDA_CHECK(cudaMemcpy(keep_inds, &cpu_keep_inds[0], sizeof(int) * num_to_keep, cudaMemcpyHostToDevice));
std::cout << "Finished!!!" << std::endl;
}
void points_nms_gpu(const int n, const int npoint, const int merge_function, float iou_thresh, const float *iou_matrix, const int *points_sample, int *keep_inds, int *nmsed_points_sample) {
// std::cout << "Beginning points nms !!!" << std::endl;
int *remove_inds = NULL;
CUDA_CHECK(cudaMalloc(&remove_inds, n * n * sizeof(int)));
CUDA_CHECK(cudaMemset(remove_inds, 0, n * n * sizeof(int)));
std::vector<int> cpu_keep_inds(n, 1);
// First initialize the nmsed_points_sample by the points_sample
CUDA_CHECK(cudaMemcpy(nmsed_points_sample, points_sample, sizeof(int) * n * npoint, cudaMemcpyDeviceToDevice));
dim3 blocks(block_num, block_num);
points_nms_kernel<<<blocks, threadsPerBlock>>>(n, npoint, merge_function, iou_thresh, iou_matrix, points_sample, remove_inds, nmsed_points_sample);
// Using for Debug
// std::vector<int> debug(n * npoint);
// CUDA_CHECK(cudaMemcpy(&debug[0], media_nmsed_points_sample, sizeof(int) * n * npoint, cudaMemcpyDeviceToHost));
// for (int i=0; i<n; i++){
// for (int j=0; j< npoint; j++)
// std::cout << debug[i * npoint + j] << " ";
// std::cout << std::endl;
// }
// std::cout << std::endl;
std::vector<int> cpu_remove_inds(n * n);
CUDA_CHECK(cudaMemcpy(&cpu_remove_inds[0], remove_inds, sizeof(int) * n * n, cudaMemcpyDeviceToHost));
// std::cout << "points nms_remove inds Done !!!" << std::endl;
// finally get the keep_inds
for (int i=0; i<n; i++){
// std::cout << 1 << std::endl;
if (cpu_keep_inds[i] == 0){
continue;
}
for(int j=i+1; j<n; j++){
if (cpu_remove_inds[i * n + j] == 1){
// remove this point
cpu_keep_inds[j] = 0;
}
}
}
// at last, make it back
CUDA_CHECK(cudaMemcpy(keep_inds, &cpu_keep_inds[0], sizeof(int) * n, cudaMemcpyHostToDevice));
CUDA_CHECK(cudaFree(remove_inds));
// std::cout << "points nms Done !!!" << std::endl;
} | // input: iou_matrix, [n, n], points_sampling, [n, npoint], merge function, 0:union, 1: intersection
// min_keep_num
// output: keep_inds [n, n], 0/1
// nmsed_points_sample: [n, npoint], 0/1
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <vector>
#include <time.h>
#define CUDA_CHECK(condition) \
/* Code block avoids redefinition of cudaError_t error */ \
do { \
hipError_t error = condition; \
if (error != hipSuccess) { \
std::cout << hipGetErrorString(error) << std::endl; \
} \
} while (0)
const int block_num = 512;
#define DIVUP(m,n) ((m) / (n) + ((m) % (n) > 0))
const int threadsPerBlock = sizeof(unsigned long long) * 8;
__global__ void points_inside_boxes(const int n, const int npoint, const float *points, const float* anchors, int* points_sample_mask){
// n: boxes_num, npoint: points_num, points: points_num x 3, anchors: boxes_num, 6
// return: points_sample_mask: boxes_num x npoint
for (int batch_idx=blockIdx.x; batch_idx < n; batch_idx += gridDim.x){
// xmin, ymin, zmin, xmax, ymax, zmax
const float* cur_anchors = anchors + batch_idx * 6;
int *cur_points_sample_mask = points_sample_mask + batch_idx * npoint;
int x_index = threadIdx.x;
int x_stride = blockDim.x;
const float cur_anchors_xmin = cur_anchors[0] - cur_anchors[3] / 2.;
const float cur_anchors_ymin = cur_anchors[1] - cur_anchors[4];
const float cur_anchors_zmin = cur_anchors[2] - cur_anchors[5] / 2.;
const float cur_anchors_xmax = cur_anchors[0] + cur_anchors[3] / 2.;
const float cur_anchors_ymax = cur_anchors[1];
const float cur_anchors_zmax = cur_anchors[2] + cur_anchors[5] / 2.;
for (int points_idx = x_index; points_idx < npoint; points_idx += x_stride){
const float* cur_points = points + points_idx * 3;
const float cur_points_x = cur_points[0];
const float cur_points_y = cur_points[1];
const float cur_points_z = cur_points[2];
int _x = (cur_points_x >= cur_anchors_xmin) * (cur_points_x <= cur_anchors_xmax);
int _y = (cur_points_y >= cur_anchors_ymin) * (cur_points_y <= cur_anchors_ymax);
int _z = (cur_points_z >= cur_anchors_zmin) * (cur_points_z <= cur_anchors_zmax);
cur_points_sample_mask[points_idx] = _x * _y * _z;
}
}
}
__global__ void points_iou_kernel(const int n, const int npoint, const int* points_sample_mask, float* iou_matrix){
// points_sample_mask, [n, npoint], 0/1
// iou_matrix, [n, n]
for (int x_num_idx=blockIdx.x; x_num_idx<n; x_num_idx+=gridDim.x){
for(int y_num_idx=blockIdx.y; y_num_idx<n; y_num_idx+=gridDim.y){
const int* x_points_sample_mask = points_sample_mask + x_num_idx * npoint;
const int* y_points_sample_mask = points_sample_mask + y_num_idx * npoint;
int x_index = threadIdx.x;
int x_stride = blockDim.x;
__shared__ float intersect_list[threadsPerBlock];
__shared__ float union_list[threadsPerBlock];
// first initialize intersect_list and union_list by zero
intersect_list[x_index] = 0;
union_list[x_index] = 0;
__syncthreads();
for(int i_x=x_index; i_x<npoint; i_x+= x_stride){
intersect_list[x_index] = intersect_list[x_index] + float(x_points_sample_mask[i_x] && y_points_sample_mask[i_x]);
union_list[x_index] = union_list[x_index] + float(x_points_sample_mask[i_x] || y_points_sample_mask[i_x]);
}
__syncthreads();
// after calc the intersect
// then get the sum
__shared__ float intersect_sum;
__shared__ float union_sum;
intersect_sum = 0;
union_sum = 0;
__syncthreads();
atomicAdd(&intersect_sum, intersect_list[x_index]);
atomicAdd(&union_sum, union_list[x_index]);
__syncthreads();
float iou = intersect_sum / max(union_sum, 1.);
iou_matrix[x_num_idx * n + y_num_idx] = iou;
}
}
}
__device__ inline float devIou(const int *a, const int *b, int npoint) {
// a:[npoint], b[npoint], then calc the iou
float intersect = 0;
float union_sect = 0;
for (int i = 0; i < npoint; i ++){
intersect += a[i] && b[i];
union_sect += a[i] || b[i];
}
return intersect / union_sect;
}
__global__ void points_nms_block_kernel(const int n, const int npoint, const int merge_function, const float iou_thresh, const int*points_sample, unsigned long long *keep_inds, int *nmsed_points_sample){
const int row_start = blockIdx.y;
const int col_start = blockIdx.x;
const int row_size = min(n - row_start * threadsPerBlock, threadsPerBlock);
const int col_size = min(n - col_start * threadsPerBlock, threadsPerBlock);
const int* col_points_sample = points_sample + (threadsPerBlock * col_start) * npoint;
if (threadIdx.x < row_size){
const int cur_box_idx = threadsPerBlock * row_start + threadIdx.x;
const int *cur_points_sample = points_sample + cur_box_idx * npoint;
int *cur_nmsed_points_sample = nmsed_points_sample + cur_box_idx * npoint;
int i = 0;
unsigned long long t = 0;
int start = 0;
if (row_start == col_start){
start = threadIdx.x + 1;
}
for (i = start; i < col_size; i ++){
if (devIou(cur_points_sample, col_points_sample + i * npoint, npoint) > iou_thresh) {
// merge the nmsed_points_sample
const int *merged_col_points_sample = col_points_sample + i * npoint;
if (merge_function == 0){
for (int j = 0; j < npoint; j++){
atomicOr(&cur_nmsed_points_sample[j], merged_col_points_sample[j]);
}
}
else if (merge_function == 1){
for (int j = 0; j < npoint; j++){
atomicAnd(&cur_nmsed_points_sample[j], merged_col_points_sample[j]);
}
}
t |= 1ULL << i;
}
}
const int col_blocks = DIVUP(n, threadsPerBlock);
// keep_inds, [col_blocks, threadsPerBlock]
keep_inds[cur_box_idx * col_blocks + col_start] = t;
}
}
__global__ void points_nms_kernel(const int n, const int npoint, const int merge_function, float iou_thresh, const float *iou_matrix, const int *points_sample, int *keep_inds, int *nmsed_points_sample) {
// nmsed_points_sample [n, npoint]
for (int x_num_idx=blockIdx.x; x_num_idx<n; x_num_idx+=gridDim.x){
for(int y_num_idx=blockIdx.y; y_num_idx<n; y_num_idx+=gridDim.y){
if (x_num_idx == y_num_idx)
continue;
// const int* x_points_sample = points_sample + x_num_idx * npoint;
const int* y_points_sample = points_sample + y_num_idx * npoint;
const float* x_iou_matrix = iou_matrix + x_num_idx * n;
int *x_keep_inds = keep_inds + x_num_idx * n;
int* x_nmsed_points_sample = nmsed_points_sample + x_num_idx * npoint;
int index = threadIdx.x;
int stride = blockDim.x;
float cur_iou = x_iou_matrix[y_num_idx];
if (cur_iou > iou_thresh){
// merge them togethor
x_keep_inds[y_num_idx] = 1;
for (int i=index;i<npoint;i+=stride){
// merge the result
if (merge_function == 0){
// union the two vector
atomicOr(&x_nmsed_points_sample[i], y_points_sample[i]);
}
else if(merge_function == 1){
atomicAnd(&x_nmsed_points_sample[i], y_points_sample[i]);
}
else{
continue;
}
}
}
}
}
}
__global__ void points_nms_sample(const int n, const int npoint, int merge_function, int* nmsed_points_sample_media, int* nmsed_points_sample){
for (int num_idx=blockIdx.x; num_idx<n; num_idx+=gridDim.x){
int *batch_nmsed_points_sample_media = nmsed_points_sample_media + num_idx * n *npoint;
int *batch_nmsed_points_sample = nmsed_points_sample + num_idx * npoint;
int index = threadIdx.x;
int stride = blockDim.x;
for (int i=index; i<n; i+=stride){
for(int j=0; j < npoint; j++){
if (merge_function == 0 || merge_function == 2){
// union or keep the origin
atomicOr(&batch_nmsed_points_sample[j], batch_nmsed_points_sample_media[i * npoint + j]);
// batch_nmsed_points_sample[j] = batch_nmsed_points_sample[j] + batch_nmsed_points_sample_media[i * npoint + j];
}
else if (merge_function == 1){
atomicAnd(&batch_nmsed_points_sample[j], batch_nmsed_points_sample_media[i * npoint + j]);
// batch_nmsed_points_sample[j] = batch_nmsed_points_sample[j] && batch_nmsed_points_sample_media[i * npoint + j];
}
}
}
}
}
void points_iou_gpu(const int n, const int npoint, const int* points_sample_mask, float* iou_matrix){
dim3 blocks(512, 512);
points_iou_kernel<<<blocks, threadsPerBlock>>>(n, npoint, points_sample_mask, iou_matrix);
// std::cout << "Iou Caluculating Done!!" << std::endl;
}
void points_inside_boxes_gpu(const int n, const int npoint, const float *points, const float* anchors, int* points_sample_mask){
CUDA_CHECK(hipMemset(points_sample_mask, 1, n * npoint * sizeof(int)));
points_inside_boxes<<<512, threadsPerBlock>>>(n, npoint, points, anchors, points_sample_mask);
}
void points_nms_block_gpu(const int n, const int npoint, const int merge_function, const float iou_thresh, const int num_to_keep, const int *points_sample, int *keep_inds, int *nmsed_points_sample){
unsigned long long* mask_dev = NULL;
const int col_blocks = DIVUP(n, threadsPerBlock);
CUDA_CHECK(hipMalloc(&mask_dev, n * col_blocks * sizeof(unsigned long long)));
CUDA_CHECK(hipMemcpy(nmsed_points_sample, points_sample, sizeof(int) * n * npoint, hipMemcpyDeviceToDevice));
time_t c_start, c_end;
c_start = clock();
hipEvent_t start, stop; // variables that holds 2 events
float time; // Variable that will hold the time
hipEventCreate(&start); // creating the event 1
hipEventCreate(&stop); // creating the event 2
hipEventRecord(start, 0); // start measuring the time
dim3 blocks(DIVUP(n, threadsPerBlock),
DIVUP(n, threadsPerBlock));
dim3 threads(threadsPerBlock);
points_nms_block_kernel<<<blocks, threads>>>(n, npoint, merge_function, iou_thresh, points_sample, mask_dev, nmsed_points_sample);
c_end = clock();
hipEventRecord(stop, 0); // Stop time measuring
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
std::cout << difftime(c_end,c_start) << std::endl;
std::cout << time << std::endl;
std::cout << "Finished main working !!!" << std::endl;
c_start = clock();
std::vector<unsigned long long> mask_host(n * col_blocks);
hipMemcpy(&mask_host[0],
mask_dev,
sizeof(unsigned long long) * n * col_blocks,
hipMemcpyDeviceToHost);
c_end = clock();
std::cout << difftime(c_end,c_start) << std::endl;
std::cout << "Finished copying" << std::endl;
c_start = clock();
std::vector<unsigned long long> remv(col_blocks);
memset(&remv[0], 0, sizeof(unsigned long long) * col_blocks);
std::vector<int> cpu_keep_inds(n);
memset(&cpu_keep_inds[0], -1, sizeof(int) * num_to_keep);
std::cout << "setting the output to -1" << std::endl;
int keeping_num = 0;
for (int i=0; i < n; i ++){
int nblock = i / threadsPerBlock;
int inblock = i % threadsPerBlock;
if (!(remv[nblock] & (1ULL << inblock))){
cpu_keep_inds[keeping_num++] = i;
if (keeping_num >= num_to_keep)
break;
unsigned long long *p = &mask_host[0] + i * col_blocks;
for (int j = nblock; j < col_blocks; j ++){
remv[j] |= p[j];
}
}
}
c_end = clock();
std::cout << difftime(c_end,c_start) << std::endl;
CUDA_CHECK(hipFree(mask_dev));
CUDA_CHECK(hipMemcpy(keep_inds, &cpu_keep_inds[0], sizeof(int) * num_to_keep, hipMemcpyHostToDevice));
std::cout << "Finished!!!" << std::endl;
}
void points_nms_gpu(const int n, const int npoint, const int merge_function, float iou_thresh, const float *iou_matrix, const int *points_sample, int *keep_inds, int *nmsed_points_sample) {
// std::cout << "Beginning points nms !!!" << std::endl;
int *remove_inds = NULL;
CUDA_CHECK(hipMalloc(&remove_inds, n * n * sizeof(int)));
CUDA_CHECK(hipMemset(remove_inds, 0, n * n * sizeof(int)));
std::vector<int> cpu_keep_inds(n, 1);
// First initialize the nmsed_points_sample by the points_sample
CUDA_CHECK(hipMemcpy(nmsed_points_sample, points_sample, sizeof(int) * n * npoint, hipMemcpyDeviceToDevice));
dim3 blocks(block_num, block_num);
points_nms_kernel<<<blocks, threadsPerBlock>>>(n, npoint, merge_function, iou_thresh, iou_matrix, points_sample, remove_inds, nmsed_points_sample);
// Using for Debug
// std::vector<int> debug(n * npoint);
// CUDA_CHECK(cudaMemcpy(&debug[0], media_nmsed_points_sample, sizeof(int) * n * npoint, cudaMemcpyDeviceToHost));
// for (int i=0; i<n; i++){
// for (int j=0; j< npoint; j++)
// std::cout << debug[i * npoint + j] << " ";
// std::cout << std::endl;
// }
// std::cout << std::endl;
std::vector<int> cpu_remove_inds(n * n);
CUDA_CHECK(hipMemcpy(&cpu_remove_inds[0], remove_inds, sizeof(int) * n * n, hipMemcpyDeviceToHost));
// std::cout << "points nms_remove inds Done !!!" << std::endl;
// finally get the keep_inds
for (int i=0; i<n; i++){
// std::cout << 1 << std::endl;
if (cpu_keep_inds[i] == 0){
continue;
}
for(int j=i+1; j<n; j++){
if (cpu_remove_inds[i * n + j] == 1){
// remove this point
cpu_keep_inds[j] = 0;
}
}
}
// at last, make it back
CUDA_CHECK(hipMemcpy(keep_inds, &cpu_keep_inds[0], sizeof(int) * n, hipMemcpyHostToDevice));
CUDA_CHECK(hipFree(remove_inds));
// std::cout << "points nms Done !!!" << std::endl;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
#include <stdio.h>
__global__ void func(void)
{
printf("hello world from GPU\n");
}
int main(void)
{
printf("hello world from CPU\n");
func <<<1, 10>>>();
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z4funcv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include <stdio.h>
__global__ void func(void)
{
printf("hello world from GPU\n");
}
int main(void)
{
printf("hello world from CPU\n");
func <<<1, 10>>>();
cudaDeviceReset();
return 0;
} | .file "tmpxft_0004d306_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z4funcvv
.type _Z22__device_stub__Z4funcvv, @function
_Z22__device_stub__Z4funcvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z4funcv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z22__device_stub__Z4funcvv, .-_Z22__device_stub__Z4funcvv
.globl _Z4funcv
.type _Z4funcv, @function
_Z4funcv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z4funcvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4funcv, .-_Z4funcv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "hello world from CPU\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z22__device_stub__Z4funcvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z4funcv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z4funcv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <stdio.h>
__global__ void func(void)
{
printf("hello world from GPU\n");
}
int main(void)
{
printf("hello world from CPU\n");
func <<<1, 10>>>();
cudaDeviceReset();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void func(void)
{
printf("hello world from GPU\n");
}
int main(void)
{
printf("hello world from CPU\n");
func <<<1, 10>>>();
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void func(void)
{
printf("hello world from GPU\n");
}
int main(void)
{
printf("hello world from CPU\n");
func <<<1, 10>>>();
hipDeviceReset();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4funcv
.globl _Z4funcv
.p2align 8
.type _Z4funcv,@function
_Z4funcv:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 22
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4funcv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4funcv, .Lfunc_end0-_Z4funcv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "hello world from GPU\n"
.size .str, 22
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4funcv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z4funcv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void func(void)
{
printf("hello world from GPU\n");
}
int main(void)
{
printf("hello world from CPU\n");
func <<<1, 10>>>();
hipDeviceReset();
return 0;
} | .text
.file "main.hip"
.globl _Z19__device_stub__funcv # -- Begin function _Z19__device_stub__funcv
.p2align 4, 0x90
.type _Z19__device_stub__funcv,@function
_Z19__device_stub__funcv: # @_Z19__device_stub__funcv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4funcv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z19__device_stub__funcv, .Lfunc_end0-_Z19__device_stub__funcv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4funcv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4funcv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4funcv,@object # @_Z4funcv
.section .rodata,"a",@progbits
.globl _Z4funcv
.p2align 3, 0x0
_Z4funcv:
.quad _Z19__device_stub__funcv
.size _Z4funcv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4funcv"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "hello world from CPU"
.size .Lstr, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__funcv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4funcv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4funcv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4funcv
.globl _Z4funcv
.p2align 8
.type _Z4funcv,@function
_Z4funcv:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 22
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4funcv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4funcv, .Lfunc_end0-_Z4funcv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "hello world from GPU\n"
.size .str, 22
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4funcv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z4funcv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004d306_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z4funcvv
.type _Z22__device_stub__Z4funcvv, @function
_Z22__device_stub__Z4funcvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z4funcv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z22__device_stub__Z4funcvv, .-_Z22__device_stub__Z4funcvv
.globl _Z4funcv
.type _Z4funcv, @function
_Z4funcv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z4funcvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4funcv, .-_Z4funcv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "hello world from CPU\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z22__device_stub__Z4funcvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z4funcv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z4funcv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z19__device_stub__funcv # -- Begin function _Z19__device_stub__funcv
.p2align 4, 0x90
.type _Z19__device_stub__funcv,@function
_Z19__device_stub__funcv: # @_Z19__device_stub__funcv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4funcv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z19__device_stub__funcv, .Lfunc_end0-_Z19__device_stub__funcv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4funcv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4funcv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4funcv,@object # @_Z4funcv
.section .rodata,"a",@progbits
.globl _Z4funcv
.p2align 3, 0x0
_Z4funcv:
.quad _Z19__device_stub__funcv
.size _Z4funcv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4funcv"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "hello world from CPU"
.size .Lstr, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__funcv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4funcv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#define RADIUS 3
#define BLOCK_SIZE 1024
__global__ void stencil_1d(int *in, int *out, int n) {
__shared__ int temp[BLOCK_SIZE + 2 * RADIUS];
int gindex = threadIdx.x + blockIdx.x * blockDim.x;
int lindex = threadIdx.x + RADIUS;
// check boundary
if (gindex >= n) {
return;
}
// read
temp[lindex] = in[gindex];
if(threadIdx.x < RADIUS) {
temp[lindex - RADIUS] = in[gindex - RADIUS];
temp[lindex + BLOCK_SIZE] = in[gindex + BLOCK_SIZE];
}
// sync
__syncthreads();
int result = 0;
for(int offset = -RADIUS ; offset <= RADIUS; offset++) {
result += temp[lindex + offset];
}
out[gindex] = result;
}
void random_ints(int* a, int N)
{
int i;
for (i = 0; i < N; ++i)
a[i] = rand() % 30;
}
#define N (2048 * 2048 * 100)
int main(void) {
int *a, *b;
int *d_a, *d_b;
int size = N * sizeof(int);
cudaMalloc((void **)&d_a, size);
cudaMalloc((void **)&d_b, size);
a = (int *)malloc(size);
random_ints(a, N);
b = (int *)malloc(size);
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
int M = BLOCK_SIZE;
stencil_1d<<<(N + M - 1) / M,M>>>(d_a, d_b, N);
cudaMemcpy(b, d_b, size, cudaMemcpyDeviceToHost);
/*
for (int i = RADIUS; i < N - RADIUS; i++) {
for (int offset = -RADIUS; offset < RADIUS; offset++) {
int num = a[i + offset];
std::cout << num << " + ";
}
int num = a[i + RADIUS];
std::cout << num << " = " << b[i] << std::endl;
}
*/
} | code for sm_80
Function : _Z10stencil_1dPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R15, SR_TID.X ; /* 0x00000000000f7919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R15 ; /* 0x0000000000007a24 */
/* 0x001fca00078e020f */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R15, 0x3, PT ; /* 0x000000030f00780c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00a0*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x0000a8000c1e1900 */
/*00b0*/ @!P0 LDG.E R5, [R2.64+-0xc] ; /* 0xfffff40402058981 */
/* 0x0000e8000c1e1900 */
/*00c0*/ @!P0 LDG.E R6, [R2.64+0x1000] ; /* 0x0010000402068981 */
/* 0x000124000c1e1900 */
/*00d0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x001fc40000011400 */
/*00e0*/ STS [R15.X4+0xc], R4 ; /* 0x00000c040f007388 */
/* 0x004fe80000004800 */
/*00f0*/ @!P0 STS [R15.X4], R5 ; /* 0x000000050f008388 */
/* 0x008fe80000004800 */
/*0100*/ @!P0 STS [R15.X4+0x100c], R6 ; /* 0x00100c060f008388 */
/* 0x010fe80000004800 */
/*0110*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0120*/ LEA R2, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fc800078010ff */
/*0130*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b0000037a11 */
/* 0x000fe200000f1403 */
/*0140*/ LDS R7, [R15.X4+0x4] ; /* 0x000004000f077984 */
/* 0x000fe80000004800 */
/*0150*/ LDS R8, [R15.X4] ; /* 0x000000000f087984 */
/* 0x000fe80000004800 */
/*0160*/ LDS R9, [R15.X4+0x8] ; /* 0x000008000f097984 */
/* 0x000e280000004800 */
/*0170*/ LDS R10, [R15.X4+0xc] ; /* 0x00000c000f0a7984 */
/* 0x000fe80000004800 */
/*0180*/ LDS R11, [R15.X4+0x10] ; /* 0x000010000f0b7984 */
/* 0x000e680000004800 */
/*0190*/ LDS R12, [R15.X4+0x14] ; /* 0x000014000f0c7984 */
/* 0x000fe80000004800 */
/*01a0*/ LDS R13, [R15.X4+0x18] ; /* 0x000018000f0d7984 */
/* 0x000ea20000004800 */
/*01b0*/ IADD3 R7, R9, R7, R8 ; /* 0x0000000709077210 */
/* 0x001fc80007ffe008 */
/*01c0*/ IADD3 R7, R11, R10, R7 ; /* 0x0000000a0b077210 */
/* 0x002fc80007ffe007 */
/*01d0*/ IADD3 R7, R13, R12, R7 ; /* 0x0000000c0d077210 */
/* 0x004fca0007ffe007 */
/*01e0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#define RADIUS 3
#define BLOCK_SIZE 1024
__global__ void stencil_1d(int *in, int *out, int n) {
__shared__ int temp[BLOCK_SIZE + 2 * RADIUS];
int gindex = threadIdx.x + blockIdx.x * blockDim.x;
int lindex = threadIdx.x + RADIUS;
// check boundary
if (gindex >= n) {
return;
}
// read
temp[lindex] = in[gindex];
if(threadIdx.x < RADIUS) {
temp[lindex - RADIUS] = in[gindex - RADIUS];
temp[lindex + BLOCK_SIZE] = in[gindex + BLOCK_SIZE];
}
// sync
__syncthreads();
int result = 0;
for(int offset = -RADIUS ; offset <= RADIUS; offset++) {
result += temp[lindex + offset];
}
out[gindex] = result;
}
void random_ints(int* a, int N)
{
int i;
for (i = 0; i < N; ++i)
a[i] = rand() % 30;
}
#define N (2048 * 2048 * 100)
int main(void) {
int *a, *b;
int *d_a, *d_b;
int size = N * sizeof(int);
cudaMalloc((void **)&d_a, size);
cudaMalloc((void **)&d_b, size);
a = (int *)malloc(size);
random_ints(a, N);
b = (int *)malloc(size);
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
int M = BLOCK_SIZE;
stencil_1d<<<(N + M - 1) / M,M>>>(d_a, d_b, N);
cudaMemcpy(b, d_b, size, cudaMemcpyDeviceToHost);
/*
for (int i = RADIUS; i < N - RADIUS; i++) {
for (int offset = -RADIUS; offset < RADIUS; offset++) {
int num = a[i + offset];
std::cout << num << " + ";
}
int num = a[i + RADIUS];
std::cout << num << " = " << b[i] << std::endl;
}
*/
} | .file "tmpxft_000bc525_00000000-6_stencil.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11random_intsPii
.type _Z11random_intsPii, @function
_Z11random_intsPii:
.LFB3669:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
movslq %eax, %rdx
imulq $-2004318071, %rdx, %rdx
shrq $32, %rdx
addl %eax, %edx
sarl $4, %edx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $30, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE3669:
.size _Z11random_intsPii, .-_Z11random_intsPii
.globl _Z33__device_stub__Z10stencil_1dPiS_iPiS_i
.type _Z33__device_stub__Z10stencil_1dPiS_iPiS_i, @function
_Z33__device_stub__Z10stencil_1dPiS_iPiS_i:
.LFB3695:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10stencil_1dPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z33__device_stub__Z10stencil_1dPiS_iPiS_i, .-_Z33__device_stub__Z10stencil_1dPiS_iPiS_i
.globl _Z10stencil_1dPiS_i
.type _Z10stencil_1dPiS_i, @function
_Z10stencil_1dPiS_i:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10stencil_1dPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z10stencil_1dPiS_i, .-_Z10stencil_1dPiS_i
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1677721600, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $1677721600, %esi
call cudaMalloc@PLT
movl $1677721600, %edi
call malloc@PLT
movq %rax, %rbx
movl $419430400, %esi
movq %rax, %rdi
call _Z11random_intsPii
movl $1677721600, %edi
call malloc@PLT
movq %rax, %rbp
movl $1, %ecx
movl $1677721600, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $409600, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
movl $2, %ecx
movl $1677721600, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl $419430400, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z33__device_stub__Z10stencil_1dPiS_iPiS_i
jmp .L20
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10stencil_1dPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10stencil_1dPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#define RADIUS 3
#define BLOCK_SIZE 1024
__global__ void stencil_1d(int *in, int *out, int n) {
__shared__ int temp[BLOCK_SIZE + 2 * RADIUS];
int gindex = threadIdx.x + blockIdx.x * blockDim.x;
int lindex = threadIdx.x + RADIUS;
// check boundary
if (gindex >= n) {
return;
}
// read
temp[lindex] = in[gindex];
if(threadIdx.x < RADIUS) {
temp[lindex - RADIUS] = in[gindex - RADIUS];
temp[lindex + BLOCK_SIZE] = in[gindex + BLOCK_SIZE];
}
// sync
__syncthreads();
int result = 0;
for(int offset = -RADIUS ; offset <= RADIUS; offset++) {
result += temp[lindex + offset];
}
out[gindex] = result;
}
void random_ints(int* a, int N)
{
int i;
for (i = 0; i < N; ++i)
a[i] = rand() % 30;
}
#define N (2048 * 2048 * 100)
int main(void) {
int *a, *b;
int *d_a, *d_b;
int size = N * sizeof(int);
cudaMalloc((void **)&d_a, size);
cudaMalloc((void **)&d_b, size);
a = (int *)malloc(size);
random_ints(a, N);
b = (int *)malloc(size);
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
int M = BLOCK_SIZE;
stencil_1d<<<(N + M - 1) / M,M>>>(d_a, d_b, N);
cudaMemcpy(b, d_b, size, cudaMemcpyDeviceToHost);
/*
for (int i = RADIUS; i < N - RADIUS; i++) {
for (int offset = -RADIUS; offset < RADIUS; offset++) {
int num = a[i + offset];
std::cout << num << " + ";
}
int num = a[i + RADIUS];
std::cout << num << " = " << b[i] << std::endl;
}
*/
} | #include <hip/hip_runtime.h>
#include <iostream>
#define RADIUS 3
#define BLOCK_SIZE 1024
__global__ void stencil_1d(int *in, int *out, int n) {
__shared__ int temp[BLOCK_SIZE + 2 * RADIUS];
int gindex = threadIdx.x + blockIdx.x * blockDim.x;
int lindex = threadIdx.x + RADIUS;
// check boundary
if (gindex >= n) {
return;
}
// read
temp[lindex] = in[gindex];
if(threadIdx.x < RADIUS) {
temp[lindex - RADIUS] = in[gindex - RADIUS];
temp[lindex + BLOCK_SIZE] = in[gindex + BLOCK_SIZE];
}
// sync
__syncthreads();
int result = 0;
for(int offset = -RADIUS ; offset <= RADIUS; offset++) {
result += temp[lindex + offset];
}
out[gindex] = result;
}
void random_ints(int* a, int N)
{
int i;
for (i = 0; i < N; ++i)
a[i] = rand() % 30;
}
#define N (2048 * 2048 * 100)
int main(void) {
int *a, *b;
int *d_a, *d_b;
int size = N * sizeof(int);
hipMalloc((void **)&d_a, size);
hipMalloc((void **)&d_b, size);
a = (int *)malloc(size);
random_ints(a, N);
b = (int *)malloc(size);
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
int M = BLOCK_SIZE;
stencil_1d<<<(N + M - 1) / M,M>>>(d_a, d_b, N);
hipMemcpy(b, d_b, size, hipMemcpyDeviceToHost);
/*
for (int i = RADIUS; i < N - RADIUS; i++) {
for (int offset = -RADIUS; offset < RADIUS; offset++) {
int num = a[i + offset];
std::cout << num << " + ";
}
int num = a[i + RADIUS];
std::cout << num << " = " << b[i] << std::endl;
}
*/
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#define RADIUS 3
#define BLOCK_SIZE 1024
__global__ void stencil_1d(int *in, int *out, int n) {
__shared__ int temp[BLOCK_SIZE + 2 * RADIUS];
int gindex = threadIdx.x + blockIdx.x * blockDim.x;
int lindex = threadIdx.x + RADIUS;
// check boundary
if (gindex >= n) {
return;
}
// read
temp[lindex] = in[gindex];
if(threadIdx.x < RADIUS) {
temp[lindex - RADIUS] = in[gindex - RADIUS];
temp[lindex + BLOCK_SIZE] = in[gindex + BLOCK_SIZE];
}
// sync
__syncthreads();
int result = 0;
for(int offset = -RADIUS ; offset <= RADIUS; offset++) {
result += temp[lindex + offset];
}
out[gindex] = result;
}
void random_ints(int* a, int N)
{
int i;
for (i = 0; i < N; ++i)
a[i] = rand() % 30;
}
#define N (2048 * 2048 * 100)
int main(void) {
int *a, *b;
int *d_a, *d_b;
int size = N * sizeof(int);
hipMalloc((void **)&d_a, size);
hipMalloc((void **)&d_b, size);
a = (int *)malloc(size);
random_ints(a, N);
b = (int *)malloc(size);
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
int M = BLOCK_SIZE;
stencil_1d<<<(N + M - 1) / M,M>>>(d_a, d_b, N);
hipMemcpy(b, d_b, size, hipMemcpyDeviceToHost);
/*
for (int i = RADIUS; i < N - RADIUS; i++) {
for (int offset = -RADIUS; offset < RADIUS; offset++) {
int num = a[i + offset];
std::cout << num << " + ";
}
int num = a[i + RADIUS];
std::cout << num << " = " << b[i] << std::endl;
}
*/
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10stencil_1dPiS_i
.globl _Z10stencil_1dPiS_i
.p2align 8
.type _Z10stencil_1dPiS_i,@function
_Z10stencil_1dPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_6
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b32_e32 v5, 2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_mov_b32 s2, exec_lo
global_load_b32 v6, v[3:4], off
s_waitcnt vmcnt(0)
ds_store_b32 v5, v6 offset:12
v_cmpx_gt_u32_e32 3, v0
s_cbranch_execz .LBB0_3
v_add_co_u32 v6, vcc_lo, 0x1000, v3
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v4, vcc_lo
s_clause 0x1
global_load_b32 v0, v[3:4], off offset:-12
global_load_b32 v3, v[6:7], off
s_waitcnt vmcnt(1)
ds_store_b32 v5, v0
s_waitcnt vmcnt(0)
ds_store_b32 v5, v3 offset:4108
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
v_mov_b32_e32 v0, 0
s_mov_b32 s2, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_4:
v_add_nc_u32_e32 v3, s2, v5
s_add_i32 s2, s2, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 28
ds_load_b32 v3, v3
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, v3, v0
s_cbranch_scc0 .LBB0_4
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10stencil_1dPiS_i
.amdhsa_group_segment_fixed_size 4120
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10stencil_1dPiS_i, .Lfunc_end0-_Z10stencil_1dPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4120
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10stencil_1dPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10stencil_1dPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#define RADIUS 3
#define BLOCK_SIZE 1024
__global__ void stencil_1d(int *in, int *out, int n) {
__shared__ int temp[BLOCK_SIZE + 2 * RADIUS];
int gindex = threadIdx.x + blockIdx.x * blockDim.x;
int lindex = threadIdx.x + RADIUS;
// check boundary
if (gindex >= n) {
return;
}
// read
temp[lindex] = in[gindex];
if(threadIdx.x < RADIUS) {
temp[lindex - RADIUS] = in[gindex - RADIUS];
temp[lindex + BLOCK_SIZE] = in[gindex + BLOCK_SIZE];
}
// sync
__syncthreads();
int result = 0;
for(int offset = -RADIUS ; offset <= RADIUS; offset++) {
result += temp[lindex + offset];
}
out[gindex] = result;
}
void random_ints(int* a, int N)
{
int i;
for (i = 0; i < N; ++i)
a[i] = rand() % 30;
}
#define N (2048 * 2048 * 100)
int main(void) {
int *a, *b;
int *d_a, *d_b;
int size = N * sizeof(int);
hipMalloc((void **)&d_a, size);
hipMalloc((void **)&d_b, size);
a = (int *)malloc(size);
random_ints(a, N);
b = (int *)malloc(size);
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
int M = BLOCK_SIZE;
stencil_1d<<<(N + M - 1) / M,M>>>(d_a, d_b, N);
hipMemcpy(b, d_b, size, hipMemcpyDeviceToHost);
/*
for (int i = RADIUS; i < N - RADIUS; i++) {
for (int offset = -RADIUS; offset < RADIUS; offset++) {
int num = a[i + offset];
std::cout << num << " + ";
}
int num = a[i + RADIUS];
std::cout << num << " = " << b[i] << std::endl;
}
*/
} | .text
.file "stencil.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z25__device_stub__stencil_1dPiS_i # -- Begin function _Z25__device_stub__stencil_1dPiS_i
.p2align 4, 0x90
.type _Z25__device_stub__stencil_1dPiS_i,@function
_Z25__device_stub__stencil_1dPiS_i: # @_Z25__device_stub__stencil_1dPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10stencil_1dPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__stencil_1dPiS_i, .Lfunc_end0-_Z25__device_stub__stencil_1dPiS_i
.cfi_endproc
# -- End function
.globl _Z11random_intsPii # -- Begin function _Z11random_intsPii
.p2align 4, 0x90
.type _Z11random_intsPii,@function
_Z11random_intsPii: # @_Z11random_intsPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $-2004318071, %rax, %rcx # imm = 0x88888889
shrq $32, %rcx
addl %eax, %ecx
movl %ecx, %edx
shrl $31, %edx
sarl $4, %ecx
addl %edx, %ecx
movl %ecx, %edx
shll $5, %edx
addl %ecx, %ecx
subl %edx, %ecx
addl %eax, %ecx
movl %ecx, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z11random_intsPii, .Lfunc_end1-_Z11random_intsPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $120, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 24(%rsp), %rdi
movl $1677721600, %esi # imm = 0x64000000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $1677721600, %esi # imm = 0x64000000
callq hipMalloc
movl $1677721600, %edi # imm = 0x64000000
callq malloc
movq %rax, %r14
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $-2004318071, %rax, %rcx # imm = 0x88888889
shrq $32, %rcx
addl %eax, %ecx
movl %ecx, %edx
shrl $31, %edx
sarl $4, %ecx
addl %edx, %ecx
movl %ecx, %edx
shll $5, %edx
addl %ecx, %ecx
subl %edx, %ecx
addl %eax, %ecx
movl %ecx, (%r14,%rbx,4)
incq %rbx
cmpq $419430400, %rbx # imm = 0x19000000
jne .LBB2_1
# %bb.2: # %_Z11random_intsPii.exit
movl $1677721600, %edi # imm = 0x64000000
callq malloc
movq %rax, %rbx
movq 24(%rsp), %rdi
movl $1677721600, %edx # imm = 0x64000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294968320, %rdx # imm = 0x100000400
leaq 408576(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $419430400, 12(%rsp) # imm = 0x19000000
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10stencil_1dPiS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq 16(%rsp), %rsi
movl $1677721600, %edx # imm = 0x64000000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10stencil_1dPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10stencil_1dPiS_i,@object # @_Z10stencil_1dPiS_i
.section .rodata,"a",@progbits
.globl _Z10stencil_1dPiS_i
.p2align 3, 0x0
_Z10stencil_1dPiS_i:
.quad _Z25__device_stub__stencil_1dPiS_i
.size _Z10stencil_1dPiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10stencil_1dPiS_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__stencil_1dPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10stencil_1dPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10stencil_1dPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R15, SR_TID.X ; /* 0x00000000000f7919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R15 ; /* 0x0000000000007a24 */
/* 0x001fca00078e020f */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R15, 0x3, PT ; /* 0x000000030f00780c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00a0*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x0000a8000c1e1900 */
/*00b0*/ @!P0 LDG.E R5, [R2.64+-0xc] ; /* 0xfffff40402058981 */
/* 0x0000e8000c1e1900 */
/*00c0*/ @!P0 LDG.E R6, [R2.64+0x1000] ; /* 0x0010000402068981 */
/* 0x000124000c1e1900 */
/*00d0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x001fc40000011400 */
/*00e0*/ STS [R15.X4+0xc], R4 ; /* 0x00000c040f007388 */
/* 0x004fe80000004800 */
/*00f0*/ @!P0 STS [R15.X4], R5 ; /* 0x000000050f008388 */
/* 0x008fe80000004800 */
/*0100*/ @!P0 STS [R15.X4+0x100c], R6 ; /* 0x00100c060f008388 */
/* 0x010fe80000004800 */
/*0110*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0120*/ LEA R2, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fc800078010ff */
/*0130*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b0000037a11 */
/* 0x000fe200000f1403 */
/*0140*/ LDS R7, [R15.X4+0x4] ; /* 0x000004000f077984 */
/* 0x000fe80000004800 */
/*0150*/ LDS R8, [R15.X4] ; /* 0x000000000f087984 */
/* 0x000fe80000004800 */
/*0160*/ LDS R9, [R15.X4+0x8] ; /* 0x000008000f097984 */
/* 0x000e280000004800 */
/*0170*/ LDS R10, [R15.X4+0xc] ; /* 0x00000c000f0a7984 */
/* 0x000fe80000004800 */
/*0180*/ LDS R11, [R15.X4+0x10] ; /* 0x000010000f0b7984 */
/* 0x000e680000004800 */
/*0190*/ LDS R12, [R15.X4+0x14] ; /* 0x000014000f0c7984 */
/* 0x000fe80000004800 */
/*01a0*/ LDS R13, [R15.X4+0x18] ; /* 0x000018000f0d7984 */
/* 0x000ea20000004800 */
/*01b0*/ IADD3 R7, R9, R7, R8 ; /* 0x0000000709077210 */
/* 0x001fc80007ffe008 */
/*01c0*/ IADD3 R7, R11, R10, R7 ; /* 0x0000000a0b077210 */
/* 0x002fc80007ffe007 */
/*01d0*/ IADD3 R7, R13, R12, R7 ; /* 0x0000000c0d077210 */
/* 0x004fca0007ffe007 */
/*01e0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10stencil_1dPiS_i
.globl _Z10stencil_1dPiS_i
.p2align 8
.type _Z10stencil_1dPiS_i,@function
_Z10stencil_1dPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_6
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b32_e32 v5, 2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_mov_b32 s2, exec_lo
global_load_b32 v6, v[3:4], off
s_waitcnt vmcnt(0)
ds_store_b32 v5, v6 offset:12
v_cmpx_gt_u32_e32 3, v0
s_cbranch_execz .LBB0_3
v_add_co_u32 v6, vcc_lo, 0x1000, v3
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v4, vcc_lo
s_clause 0x1
global_load_b32 v0, v[3:4], off offset:-12
global_load_b32 v3, v[6:7], off
s_waitcnt vmcnt(1)
ds_store_b32 v5, v0
s_waitcnt vmcnt(0)
ds_store_b32 v5, v3 offset:4108
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
v_mov_b32_e32 v0, 0
s_mov_b32 s2, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_4:
v_add_nc_u32_e32 v3, s2, v5
s_add_i32 s2, s2, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 28
ds_load_b32 v3, v3
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, v3, v0
s_cbranch_scc0 .LBB0_4
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10stencil_1dPiS_i
.amdhsa_group_segment_fixed_size 4120
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10stencil_1dPiS_i, .Lfunc_end0-_Z10stencil_1dPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4120
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10stencil_1dPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10stencil_1dPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000bc525_00000000-6_stencil.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11random_intsPii
.type _Z11random_intsPii, @function
_Z11random_intsPii:
.LFB3669:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
movslq %eax, %rdx
imulq $-2004318071, %rdx, %rdx
shrq $32, %rdx
addl %eax, %edx
sarl $4, %edx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $30, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE3669:
.size _Z11random_intsPii, .-_Z11random_intsPii
.globl _Z33__device_stub__Z10stencil_1dPiS_iPiS_i
.type _Z33__device_stub__Z10stencil_1dPiS_iPiS_i, @function
_Z33__device_stub__Z10stencil_1dPiS_iPiS_i:
.LFB3695:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10stencil_1dPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z33__device_stub__Z10stencil_1dPiS_iPiS_i, .-_Z33__device_stub__Z10stencil_1dPiS_iPiS_i
.globl _Z10stencil_1dPiS_i
.type _Z10stencil_1dPiS_i, @function
_Z10stencil_1dPiS_i:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10stencil_1dPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z10stencil_1dPiS_i, .-_Z10stencil_1dPiS_i
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1677721600, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $1677721600, %esi
call cudaMalloc@PLT
movl $1677721600, %edi
call malloc@PLT
movq %rax, %rbx
movl $419430400, %esi
movq %rax, %rdi
call _Z11random_intsPii
movl $1677721600, %edi
call malloc@PLT
movq %rax, %rbp
movl $1, %ecx
movl $1677721600, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $409600, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
movl $2, %ecx
movl $1677721600, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl $419430400, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z33__device_stub__Z10stencil_1dPiS_iPiS_i
jmp .L20
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10stencil_1dPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10stencil_1dPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "stencil.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z25__device_stub__stencil_1dPiS_i # -- Begin function _Z25__device_stub__stencil_1dPiS_i
.p2align 4, 0x90
.type _Z25__device_stub__stencil_1dPiS_i,@function
_Z25__device_stub__stencil_1dPiS_i: # @_Z25__device_stub__stencil_1dPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10stencil_1dPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__stencil_1dPiS_i, .Lfunc_end0-_Z25__device_stub__stencil_1dPiS_i
.cfi_endproc
# -- End function
.globl _Z11random_intsPii # -- Begin function _Z11random_intsPii
.p2align 4, 0x90
.type _Z11random_intsPii,@function
_Z11random_intsPii: # @_Z11random_intsPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $-2004318071, %rax, %rcx # imm = 0x88888889
shrq $32, %rcx
addl %eax, %ecx
movl %ecx, %edx
shrl $31, %edx
sarl $4, %ecx
addl %edx, %ecx
movl %ecx, %edx
shll $5, %edx
addl %ecx, %ecx
subl %edx, %ecx
addl %eax, %ecx
movl %ecx, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z11random_intsPii, .Lfunc_end1-_Z11random_intsPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $120, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 24(%rsp), %rdi
movl $1677721600, %esi # imm = 0x64000000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $1677721600, %esi # imm = 0x64000000
callq hipMalloc
movl $1677721600, %edi # imm = 0x64000000
callq malloc
movq %rax, %r14
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $-2004318071, %rax, %rcx # imm = 0x88888889
shrq $32, %rcx
addl %eax, %ecx
movl %ecx, %edx
shrl $31, %edx
sarl $4, %ecx
addl %edx, %ecx
movl %ecx, %edx
shll $5, %edx
addl %ecx, %ecx
subl %edx, %ecx
addl %eax, %ecx
movl %ecx, (%r14,%rbx,4)
incq %rbx
cmpq $419430400, %rbx # imm = 0x19000000
jne .LBB2_1
# %bb.2: # %_Z11random_intsPii.exit
movl $1677721600, %edi # imm = 0x64000000
callq malloc
movq %rax, %rbx
movq 24(%rsp), %rdi
movl $1677721600, %edx # imm = 0x64000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294968320, %rdx # imm = 0x100000400
leaq 408576(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $419430400, 12(%rsp) # imm = 0x19000000
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10stencil_1dPiS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq 16(%rsp), %rsi
movl $1677721600, %edx # imm = 0x64000000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10stencil_1dPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10stencil_1dPiS_i,@object # @_Z10stencil_1dPiS_i
.section .rodata,"a",@progbits
.globl _Z10stencil_1dPiS_i
.p2align 3, 0x0
_Z10stencil_1dPiS_i:
.quad _Z25__device_stub__stencil_1dPiS_i
.size _Z10stencil_1dPiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10stencil_1dPiS_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__stencil_1dPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10stencil_1dPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | typedef struct KernelData
{
float a;
float b;
float result;
} KernelData;
__global__ void vectorAddition(KernelData* data)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
data[index].result = data[index].a + data[index].b;
} | code for sm_80
Function : _Z14vectorAdditionP10KernelData
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 7.152557373046875e-07 ; /* 0x0000000cff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0080*/ LDG.E R5, [R2.64+0x4] ; /* 0x0000040402057981 */
/* 0x000ea4000c1e1900 */
/*0090*/ FADD R5, R0, R5 ; /* 0x0000000500057221 */
/* 0x004fca0000000000 */
/*00a0*/ STG.E [R2.64+0x8], R5 ; /* 0x0000080502007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | typedef struct KernelData
{
float a;
float b;
float result;
} KernelData;
__global__ void vectorAddition(KernelData* data)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
data[index].result = data[index].a + data[index].b;
} | .file "tmpxft_001bdab7_00000000-6_CudaKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z14vectorAdditionP10KernelDataP10KernelData
.type _Z45__device_stub__Z14vectorAdditionP10KernelDataP10KernelData, @function
_Z45__device_stub__Z14vectorAdditionP10KernelDataP10KernelData:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14vectorAdditionP10KernelData(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z14vectorAdditionP10KernelDataP10KernelData, .-_Z45__device_stub__Z14vectorAdditionP10KernelDataP10KernelData
.globl _Z14vectorAdditionP10KernelData
.type _Z14vectorAdditionP10KernelData, @function
_Z14vectorAdditionP10KernelData:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z14vectorAdditionP10KernelDataP10KernelData
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14vectorAdditionP10KernelData, .-_Z14vectorAdditionP10KernelData
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z14vectorAdditionP10KernelData"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14vectorAdditionP10KernelData(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | typedef struct KernelData
{
float a;
float b;
float result;
} KernelData;
__global__ void vectorAddition(KernelData* data)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
data[index].result = data[index].a + data[index].b;
} | #include <hip/hip_runtime.h>
typedef struct KernelData
{
float a;
float b;
float result;
} KernelData;
__global__ void vectorAddition(KernelData* data)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
data[index].result = data[index].a + data[index].b;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
typedef struct KernelData
{
float a;
float b;
float result;
} KernelData;
__global__ void vectorAddition(KernelData* data)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
data[index].result = data[index].a + data[index].b;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14vectorAdditionP10KernelData
.globl _Z14vectorAdditionP10KernelData
.p2align 8
.type _Z14vectorAdditionP10KernelData,@function
_Z14vectorAdditionP10KernelData:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mad_i64_i32 v[2:3], null, v1, 12, s[0:1]
global_load_b64 v[0:1], v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v1
global_store_b32 v[2:3], v0, off offset:8
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14vectorAdditionP10KernelData
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14vectorAdditionP10KernelData, .Lfunc_end0-_Z14vectorAdditionP10KernelData
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14vectorAdditionP10KernelData
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z14vectorAdditionP10KernelData.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
typedef struct KernelData
{
float a;
float b;
float result;
} KernelData;
__global__ void vectorAddition(KernelData* data)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
data[index].result = data[index].a + data[index].b;
} | .text
.file "CudaKernel.hip"
.globl _Z29__device_stub__vectorAdditionP10KernelData # -- Begin function _Z29__device_stub__vectorAdditionP10KernelData
.p2align 4, 0x90
.type _Z29__device_stub__vectorAdditionP10KernelData,@function
_Z29__device_stub__vectorAdditionP10KernelData: # @_Z29__device_stub__vectorAdditionP10KernelData
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z14vectorAdditionP10KernelData, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z29__device_stub__vectorAdditionP10KernelData, .Lfunc_end0-_Z29__device_stub__vectorAdditionP10KernelData
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14vectorAdditionP10KernelData, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14vectorAdditionP10KernelData,@object # @_Z14vectorAdditionP10KernelData
.section .rodata,"a",@progbits
.globl _Z14vectorAdditionP10KernelData
.p2align 3, 0x0
_Z14vectorAdditionP10KernelData:
.quad _Z29__device_stub__vectorAdditionP10KernelData
.size _Z14vectorAdditionP10KernelData, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14vectorAdditionP10KernelData"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__vectorAdditionP10KernelData
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14vectorAdditionP10KernelData
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14vectorAdditionP10KernelData
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 7.152557373046875e-07 ; /* 0x0000000cff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0080*/ LDG.E R5, [R2.64+0x4] ; /* 0x0000040402057981 */
/* 0x000ea4000c1e1900 */
/*0090*/ FADD R5, R0, R5 ; /* 0x0000000500057221 */
/* 0x004fca0000000000 */
/*00a0*/ STG.E [R2.64+0x8], R5 ; /* 0x0000080502007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14vectorAdditionP10KernelData
.globl _Z14vectorAdditionP10KernelData
.p2align 8
.type _Z14vectorAdditionP10KernelData,@function
_Z14vectorAdditionP10KernelData:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mad_i64_i32 v[2:3], null, v1, 12, s[0:1]
global_load_b64 v[0:1], v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v1
global_store_b32 v[2:3], v0, off offset:8
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14vectorAdditionP10KernelData
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14vectorAdditionP10KernelData, .Lfunc_end0-_Z14vectorAdditionP10KernelData
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14vectorAdditionP10KernelData
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z14vectorAdditionP10KernelData.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001bdab7_00000000-6_CudaKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z14vectorAdditionP10KernelDataP10KernelData
.type _Z45__device_stub__Z14vectorAdditionP10KernelDataP10KernelData, @function
_Z45__device_stub__Z14vectorAdditionP10KernelDataP10KernelData:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14vectorAdditionP10KernelData(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z14vectorAdditionP10KernelDataP10KernelData, .-_Z45__device_stub__Z14vectorAdditionP10KernelDataP10KernelData
.globl _Z14vectorAdditionP10KernelData
.type _Z14vectorAdditionP10KernelData, @function
_Z14vectorAdditionP10KernelData:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z14vectorAdditionP10KernelDataP10KernelData
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14vectorAdditionP10KernelData, .-_Z14vectorAdditionP10KernelData
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z14vectorAdditionP10KernelData"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14vectorAdditionP10KernelData(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "CudaKernel.hip"
.globl _Z29__device_stub__vectorAdditionP10KernelData # -- Begin function _Z29__device_stub__vectorAdditionP10KernelData
.p2align 4, 0x90
.type _Z29__device_stub__vectorAdditionP10KernelData,@function
_Z29__device_stub__vectorAdditionP10KernelData: # @_Z29__device_stub__vectorAdditionP10KernelData
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z14vectorAdditionP10KernelData, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z29__device_stub__vectorAdditionP10KernelData, .Lfunc_end0-_Z29__device_stub__vectorAdditionP10KernelData
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14vectorAdditionP10KernelData, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14vectorAdditionP10KernelData,@object # @_Z14vectorAdditionP10KernelData
.section .rodata,"a",@progbits
.globl _Z14vectorAdditionP10KernelData
.p2align 3, 0x0
_Z14vectorAdditionP10KernelData:
.quad _Z29__device_stub__vectorAdditionP10KernelData
.size _Z14vectorAdditionP10KernelData, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14vectorAdditionP10KernelData"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__vectorAdditionP10KernelData
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14vectorAdditionP10KernelData
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void iReduceSum(int *idata, int *odata, unsigned int ncols) {
int i;
unsigned int tid = threadIdx.x;
extern __shared__ int sdata[];
unsigned int startPos = blockDim.x + threadIdx.x;
int colsPerThread = ncols/blockDim.x;
int blockOffset = threadIdx.x *(ncols/blockDim.x);
int myPart = 0;
for(i=0;i<colsPerThread;i++) {
myPart+=idata[blockOffset+startPos+i];
}
sdata[tid]=myPart;
__syncthreads();
unsigned int s;
for(s=1;s<blockDim.x;s*=2){
if(tid%(2*s) == 0){
sdata[tid]+=sdata[tid+s];
}
__syncthreads();
}
if(tid==0)odata[blockIdx.x]=sdata[0];
} | code for sm_80
Function : _Z10iReduceSumPiS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ I2F.U32.RP R4, c[0x0][0x0] ; /* 0x0000000000047b06 */
/* 0x000e220000209000 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0030*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fe20003f45070 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fc800078e00ff */
/*0060*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0070*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0080*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0090*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00a0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x002fc800078e0a03 */
/*00b0*/ IMAD R5, R5, c[0x0][0x0], RZ ; /* 0x0000000005057a24 */
/* 0x000fc800078e02ff */
/*00c0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fe400078e0002 */
/*00d0*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*00e0*/ IMAD.HI.U32 R3, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a27 */
/* 0x000fc800078e00ff */
/*00f0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a03 */
/*0100*/ IMAD R4, R5, R0, c[0x0][0x170] ; /* 0x00005c0005047624 */
/* 0x000fca00078e0200 */
/*0110*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x0], PT ; /* 0x0000000004007a0c */
/* 0x000fda0003f06070 */
/*0120*/ @P0 IADD3 R4, R4, -c[0x0][0x0], RZ ; /* 0x8000000004040a10 */
/* 0x000fe40007ffe0ff */
/*0130*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe40007ffe0ff */
/*0140*/ ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x0], PT ; /* 0x0000000004007a0c */
/* 0x000fda0003f26070 */
/*0150*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*0160*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff03aa12 */
/* 0x000fc800078e33ff */
/*0170*/ ISETP.GE.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fda0003f06270 */
/*0180*/ @!P0 BRA 0xa80 ; /* 0x000008f000008947 */
/* 0x000fea0003800000 */
/*0190*/ IADD3 R4, R3.reuse, -0x1, RZ ; /* 0xffffffff03047810 */
/* 0x041fe20007ffe0ff */
/*01a0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*01b0*/ IADD3 R6, R2, c[0x0][0x0], RZ ; /* 0x0000000002067a10 */
/* 0x000fe20007ffe0ff */
/*01c0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*01d0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*01e0*/ LOP3.LUT R4, R3.reuse, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303047812 */
/* 0x040fe200078ec0ff */
/*01f0*/ IMAD R6, R3, R2, R6 ; /* 0x0000000203067224 */
/* 0x000fd400078e0206 */
/*0200*/ @!P0 BRA 0x9d0 ; /* 0x000007c000008947 */
/* 0x000fea0003800000 */
/*0210*/ IMAD.IADD R3, R3, 0x1, -R4 ; /* 0x0000000103037824 */
/* 0x000fe400078e0a04 */
/*0220*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fc600078e00ff */
/*0230*/ ISETP.GT.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f04270 */
/*0240*/ @!P0 BRA 0x8a0 ; /* 0x0000065000008947 */
/* 0x000fea0003800000 */
/*0250*/ ISETP.GT.AND P1, PT, R3, 0xc, PT ; /* 0x0000000c0300780c */
/* 0x000fe40003f24270 */
/*0260*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0270*/ @!P1 BRA 0x660 ; /* 0x000003e000009947 */
/* 0x000fea0003800000 */
/*0280*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0290*/ IMAD.IADD R23, R6.reuse, 0x1, R5.reuse ; /* 0x0000000106177824 */
/* 0x140fe200078e0205 */
/*02a0*/ IADD3 R27, R6.reuse, 0x4, R5.reuse ; /* 0x00000004061b7810 */
/* 0x140fe20007ffe005 */
/*02b0*/ IMAD.MOV.U32 R24, RZ, RZ, 0x4 ; /* 0x00000004ff187424 */
/* 0x000fe200078e00ff */
/*02c0*/ IADD3 R19, R6.reuse, 0x8, R5.reuse ; /* 0x0000000806137810 */
/* 0x140fe40007ffe005 */
/*02d0*/ IADD3 R13, R23.reuse, 0x1, RZ ; /* 0x00000001170d7810 */
/* 0x040fe20007ffe0ff */
/*02e0*/ IMAD.WIDE.U32 R20, R23.reuse, R24.reuse, c[0x0][0x160] ; /* 0x0000580017147625 */
/* 0x0c0fe200078e0018 */
/*02f0*/ IADD3 R25, R23.reuse, 0x3, RZ ; /* 0x0000000317197810 */
/* 0x040fe40007ffe0ff */
/*0300*/ IADD3 R15, R23, 0x2, RZ ; /* 0x00000002170f7810 */
/* 0x000fe20007ffe0ff */
/*0310*/ IMAD.WIDE.U32 R12, R13, R24.reuse, c[0x0][0x160] ; /* 0x000058000d0c7625 */
/* 0x080fe200078e0018 */
/*0320*/ IADD3 R17, R6, 0xc, R5 ; /* 0x0000000c06117810 */
/* 0x000fe20007ffe005 */
/*0330*/ LDG.E R8, [R20.64] ; /* 0x0000000414087981 */
/* 0x0000a2000c1e1900 */
/*0340*/ IADD3 R29, R23, 0x5, RZ ; /* 0x00000005171d7810 */
/* 0x000fe20007ffe0ff */
/*0350*/ IMAD.WIDE.U32 R26, R27, R24, c[0x0][0x160] ; /* 0x000058001b1a7625 */
/* 0x000fc400078e0018 */
/*0360*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x0002a4000c1e1900 */
/*0370*/ IMAD.WIDE.U32 R18, R19, R24.reuse, c[0x0][0x160] ; /* 0x0000580013127625 */
/* 0x080fe400078e0018 */
/*0380*/ LDG.E R9, [R26.64] ; /* 0x000000041a097981 */
/* 0x000724000c1e1900 */
/*0390*/ IMAD.WIDE.U32 R20, R25, R24.reuse, c[0x0][0x160] ; /* 0x0000580019147625 */
/* 0x081fe200078e0018 */
/*03a0*/ IADD3 R25, R23, 0x6, RZ ; /* 0x0000000617197810 */
/* 0x000fe20007ffe0ff */
/*03b0*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x000164000c1e1900 */
/*03c0*/ IMAD.WIDE.U32 R14, R15, R24, c[0x0][0x160] ; /* 0x000058000f0e7625 */
/* 0x000fc800078e0018 */
/*03d0*/ IMAD.WIDE.U32 R16, R17, R24.reuse, c[0x0][0x160] ; /* 0x0000580011107625 */
/* 0x080fe200078e0018 */
/*03e0*/ IADD3 R27, R23, 0x7, RZ ; /* 0x00000007171b7810 */
/* 0x008fe20007ffe0ff */
/*03f0*/ LDG.E R13, [R14.64] ; /* 0x000000040e0d7981 */
/* 0x0022e4000c1e1900 */
/*0400*/ IMAD.WIDE.U32 R28, R29, R24.reuse, c[0x0][0x160] ; /* 0x000058001d1c7625 */
/* 0x080fe400078e0018 */
/*0410*/ LDG.E R26, [R20.64] ; /* 0x00000004141a7981 */
/* 0x0002e4000c1e1900 */
/*0420*/ IMAD.WIDE.U32 R18, R25, R24, c[0x0][0x160] ; /* 0x0000580019127625 */
/* 0x001fe200078e0018 */
/*0430*/ IADD3 R25, R23.reuse, 0x9, RZ ; /* 0x0000000917197810 */
/* 0x040fe20007ffe0ff */
/*0440*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000122000c1e1900 */
/*0450*/ IADD3 R22, R23, 0xa, RZ ; /* 0x0000000a17167810 */
/* 0x000fc60007ffe0ff */
/*0460*/ LDG.E R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000122000c1e1900 */
/*0470*/ IMAD.WIDE.U32 R14, R25, R24, c[0x0][0x160] ; /* 0x00005800190e7625 */
/* 0x002fe200078e0018 */
/*0480*/ IADD3 R21, R23, 0xb, RZ ; /* 0x0000000b17157810 */
/* 0x000fc60007ffe0ff */
/*0490*/ IMAD.WIDE.U32 R16, R27, R24.reuse, c[0x0][0x160] ; /* 0x000058001b107625 */
/* 0x081fe200078e0018 */
/*04a0*/ IADD3 R25, R23, 0xd, RZ ; /* 0x0000000d17197810 */
/* 0x000fe20007ffe0ff */
/*04b0*/ LDG.E R27, [R18.64] ; /* 0x00000004121b7981 */
/* 0x000168000c1e1900 */
/*04c0*/ LDG.E R29, [R16.64] ; /* 0x00000004101d7981 */
/* 0x000368000c1e1900 */
/*04d0*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000f62000c1e1900 */
/*04e0*/ IMAD.WIDE.U32 R18, R21, R24, c[0x0][0x160] ; /* 0x0000580015127625 */
/* 0x001fc800078e0018 */
/*04f0*/ IMAD.WIDE.U32 R16, R22, R24.reuse, c[0x0][0x160] ; /* 0x0000580016107625 */
/* 0x082fe200078e0018 */
/*0500*/ IADD3 R22, R23, 0xe, RZ ; /* 0x0000000e17167810 */
/* 0x000fe20007ffe0ff */
/*0510*/ LDG.E R19, [R18.64] ; /* 0x0000000412137981 */
/* 0x000f64000c1e1900 */
/*0520*/ IMAD.WIDE.U32 R20, R25, R24.reuse, c[0x0][0x160] ; /* 0x0000580019147625 */
/* 0x080fe200078e0018 */
/*0530*/ IADD3 R25, R23, 0xf, RZ ; /* 0x0000000f17197810 */
/* 0x000fe20007ffe0ff */
/*0540*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f64000c1e1900 */
/*0550*/ IMAD.WIDE.U32 R22, R22, R24.reuse, c[0x0][0x160] ; /* 0x0000580016167625 */
/* 0x080fe400078e0018 */
/*0560*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000f64000c1e1900 */
/*0570*/ IMAD.WIDE.U32 R24, R25, R24, c[0x0][0x160] ; /* 0x0000580019187625 */
/* 0x000fc400078e0018 */
/*0580*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000f68000c1e1900 */
/*0590*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000f62000c1e1900 */
/*05a0*/ IADD3 R3, R3, -0x10, RZ ; /* 0xfffffff003037810 */
/* 0x000fc80007ffe0ff */
/*05b0*/ ISETP.GT.AND P1, PT, R3, 0xc, PT ; /* 0x0000000c0300780c */
/* 0x000fe40003f24270 */
/*05c0*/ IADD3 R5, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x000fe40007ffe0ff */
/*05d0*/ IADD3 R8, R12, R8, R7 ; /* 0x000000080c087210 */
/* 0x004fc80007ffe007 */
/*05e0*/ IADD3 R8, R26, R13, R8 ; /* 0x0000000d1a087210 */
/* 0x008fc80007ffe008 */
/*05f0*/ IADD3 R8, R28, R9, R8 ; /* 0x000000091c087210 */
/* 0x010fc80007ffe008 */
/*0600*/ IADD3 R8, R29, R27, R8 ; /* 0x0000001b1d087210 */
/* 0x020fc80007ffe008 */
/*0610*/ IADD3 R8, R15, R10, R8 ; /* 0x0000000a0f087210 */
/* 0x000fc80007ffe008 */
/*0620*/ IADD3 R8, R19, R16, R8 ; /* 0x0000001013087210 */
/* 0x000fc80007ffe008 */
/*0630*/ IADD3 R8, R20, R11, R8 ; /* 0x0000000b14087210 */
/* 0x000fc80007ffe008 */
/*0640*/ IADD3 R7, R25, R22, R8 ; /* 0x0000001619077210 */
/* 0x000fe20007ffe008 */
/*0650*/ @P1 BRA 0x290 ; /* 0xfffffc3000001947 */
/* 0x000fea000383ffff */
/*0660*/ ISETP.GT.AND P1, PT, R3, 0x4, PT ; /* 0x000000040300780c */
/* 0x000fda0003f24270 */
/*0670*/ @!P1 BRA 0x880 ; /* 0x0000020000009947 */
/* 0x000fea0003800000 */
/*0680*/ IMAD.IADD R9, R6, 0x1, R5 ; /* 0x0000000106097824 */
/* 0x000fe400078e0205 */
/*0690*/ IMAD.MOV.U32 R18, RZ, RZ, 0x4 ; /* 0x00000004ff127424 */
/* 0x000fc600078e00ff */
/*06a0*/ IADD3 R15, R9.reuse, 0x1, RZ ; /* 0x00000001090f7810 */
/* 0x040fe20007ffe0ff */
/*06b0*/ IMAD.WIDE.U32 R22, R9.reuse, R18.reuse, c[0x0][0x160] ; /* 0x0000580009167625 */
/* 0x0c0fe200078e0012 */
/*06c0*/ IADD3 R17, R9.reuse, 0x2, RZ ; /* 0x0000000209117810 */
/* 0x040fe40007ffe0ff */
/*06d0*/ IADD3 R11, R9, 0x3, RZ ; /* 0x00000003090b7810 */
/* 0x000fe20007ffe0ff */
/*06e0*/ IMAD.WIDE.U32 R14, R15, R18.reuse, c[0x0][0x160] ; /* 0x000058000f0e7625 */
/* 0x080fe200078e0012 */
/*06f0*/ IADD3 R13, R6, 0x4, R5 ; /* 0x00000004060d7810 */
/* 0x000fe20007ffe005 */
/*0700*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000ea2000c1e1900 */
/*0710*/ IADD3 R19, R9, 0x5, RZ ; /* 0x0000000509137810 */
/* 0x000fe20007ffe0ff */
/*0720*/ IMAD.WIDE.U32 R16, R17, R18.reuse, c[0x0][0x160] ; /* 0x0000580011107625 */
/* 0x080fe200078e0012 */
/*0730*/ IADD3 R21, R9, 0x6, RZ ; /* 0x0000000609157810 */
/* 0x000fe20007ffe0ff */
/*0740*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea4000c1e1900 */
/*0750*/ IMAD.WIDE.U32 R10, R11, R18.reuse, c[0x0][0x160] ; /* 0x000058000b0a7625 */
/* 0x080fe200078e0012 */
/*0760*/ IADD3 R25, R9, 0x7, RZ ; /* 0x0000000709197810 */
/* 0x000fe20007ffe0ff */
/*0770*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ee4000c1e1900 */
/*0780*/ IMAD.WIDE.U32 R12, R13, R18, c[0x0][0x160] ; /* 0x000058000d0c7625 */
/* 0x000fc400078e0012 */
/*0790*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee4000c1e1900 */
/*07a0*/ IMAD.WIDE.U32 R8, R19, R18.reuse, c[0x0][0x160] ; /* 0x0000580013087625 */
/* 0x080fe400078e0012 */
/*07b0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f24000c1e1900 */
/*07c0*/ IMAD.WIDE.U32 R20, R21, R18.reuse, c[0x0][0x160] ; /* 0x0000580015147625 */
/* 0x080fe400078e0012 */
/*07d0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f24000c1e1900 */
/*07e0*/ IMAD.WIDE.U32 R18, R25, R18, c[0x0][0x160] ; /* 0x0000580019127625 */
/* 0x000fc400078e0012 */
/*07f0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000f68000c1e1900 */
/*0800*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f62000c1e1900 */
/*0810*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0820*/ IADD3 R3, R3, -0x8, RZ ; /* 0xfffffff803037810 */
/* 0x000fe40007ffe0ff */
/*0830*/ IADD3 R5, R5, 0x8, RZ ; /* 0x0000000805057810 */
/* 0x000fe40007ffe0ff */
/*0840*/ IADD3 R7, R14, R22, R7 ; /* 0x000000160e077210 */
/* 0x004fc80007ffe007 */
/*0850*/ IADD3 R7, R10, R16, R7 ; /* 0x000000100a077210 */
/* 0x008fc80007ffe007 */
/*0860*/ IADD3 R7, R8, R12, R7 ; /* 0x0000000c08077210 */
/* 0x010fc80007ffe007 */
/*0870*/ IADD3 R7, R18, R20, R7 ; /* 0x0000001412077210 */
/* 0x020fe40007ffe007 */
/*0880*/ ISETP.NE.OR P0, PT, R3, RZ, P0 ; /* 0x000000ff0300720c */
/* 0x000fda0000705670 */
/*0890*/ @!P0 BRA 0x9d0 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*08a0*/ IMAD.IADD R8, R6, 0x1, R5 ; /* 0x0000000106087824 */
/* 0x000fe400078e0205 */
/*08b0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fc600078e00ff */
/*08c0*/ IADD3 R12, R8.reuse, 0x1, RZ ; /* 0x00000001080c7810 */
/* 0x040fe20007ffe0ff */
/*08d0*/ IMAD.WIDE.U32 R10, R8.reuse, R15.reuse, c[0x0][0x160] ; /* 0x00005800080a7625 */
/* 0x0c0fe200078e000f */
/*08e0*/ IADD3 R14, R8.reuse, 0x2, RZ ; /* 0x00000002080e7810 */
/* 0x040fe40007ffe0ff */
/*08f0*/ IADD3 R16, R8, 0x3, RZ ; /* 0x0000000308107810 */
/* 0x000fe20007ffe0ff */
/*0900*/ IMAD.WIDE.U32 R8, R12, R15.reuse, c[0x0][0x160] ; /* 0x000058000c087625 */
/* 0x080fe400078e000f */
/*0910*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea4000c1e1900 */
/*0920*/ IMAD.WIDE.U32 R12, R14, R15.reuse, c[0x0][0x160] ; /* 0x000058000e0c7625 */
/* 0x080fe400078e000f */
/*0930*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea4000c1e1900 */
/*0940*/ IMAD.WIDE.U32 R14, R16, R15, c[0x0][0x160] ; /* 0x00005800100e7625 */
/* 0x000fc400078e000f */
/*0950*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee8000c1e1900 */
/*0960*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*0970*/ IADD3 R3, R3, -0x4, RZ ; /* 0xfffffffc03037810 */
/* 0x000fc80007ffe0ff */
/*0980*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f05270 */
/*0990*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fe40007ffe0ff */
/*09a0*/ IADD3 R7, R8, R10, R7 ; /* 0x0000000a08077210 */
/* 0x004fc80007ffe007 */
/*09b0*/ IADD3 R7, R14, R12, R7 ; /* 0x0000000c0e077210 */
/* 0x008fca0007ffe007 */
/*09c0*/ @P0 BRA 0x8a0 ; /* 0xfffffed000000947 */
/* 0x000fea000383ffff */
/*09d0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*09e0*/ @!P0 BRA 0xa80 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*09f0*/ IMAD.IADD R8, R6, 0x1, R5 ; /* 0x0000000106087824 */
/* 0x000fe400078e0205 */
/*0a00*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc800078e00ff */
/*0a10*/ IMAD.WIDE.U32 R8, R8, R9, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fcc00078e0009 */
/*0a20*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1900 */
/*0a30*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0a40*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe40007ffe0ff */
/*0a50*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0a60*/ IMAD.IADD R7, R8, 0x1, R7 ; /* 0x0000000108077824 */
/* 0x004fd800078e0207 */
/*0a70*/ @P0 BRA 0x9f0 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0a80*/ ISETP.GE.U32.AND P1, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x001fe20003f26070 */
/*0a90*/ STS [R2.X4], R7 ; /* 0x0000000702007388 */
/* 0x0001e80000004800 */
/*0aa0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0ab0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fce0003f05270 */
/*0ac0*/ @!P1 BRA 0xcb0 ; /* 0x000001e000009947 */
/* 0x000fec0003800000 */
/*0ad0*/ IMAD.SHL.U32 R0, R2, 0x4, RZ ; /* 0x0000000402007824 */
/* 0x001fe400078e00ff */
/*0ae0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x1 ; /* 0x00000001ff037424 */
/* 0x000fc800078e00ff */
/*0af0*/ IMAD.SHL.U32 R8, R3, 0x2, RZ ; /* 0x0000000203087824 */
/* 0x000fc800078e00ff */
/*0b00*/ I2F.U32.RP R6, R8 ; /* 0x0000000800067306 */
/* 0x000e220000209000 */
/*0b10*/ IMAD.MOV R7, RZ, RZ, -R8 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a08 */
/*0b20*/ ISETP.NE.U32.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fcc0003f45070 */
/*0b30*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0b40*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0b50*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0b60*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0b70*/ IMAD R7, R7, R5, RZ ; /* 0x0000000507077224 */
/* 0x002fc800078e02ff */
/*0b80*/ IMAD.HI.U32 R5, R5, R7, R4 ; /* 0x0000000705057227 */
/* 0x000fcc00078e0004 */
/*0b90*/ IMAD.HI.U32 R5, R5, R2, RZ ; /* 0x0000000205057227 */
/* 0x000fc800078e00ff */
/*0ba0*/ IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a05 */
/*0bb0*/ IMAD R5, R8, R5, R2 ; /* 0x0000000508057224 */
/* 0x000fca00078e0202 */
/*0bc0*/ ISETP.GE.U32.AND P1, PT, R5, R8, PT ; /* 0x000000080500720c */
/* 0x000fda0003f26070 */
/*0bd0*/ @P1 IMAD.IADD R5, R5, 0x1, -R8 ; /* 0x0000000105051824 */
/* 0x000fca00078e0a08 */
/*0be0*/ ISETP.GE.U32.AND P1, PT, R5, R8, PT ; /* 0x000000080500720c */
/* 0x000fda0003f26070 */
/*0bf0*/ @P1 IMAD.IADD R5, R5, 0x1, -R8 ; /* 0x0000000105051824 */
/* 0x000fe200078e0a08 */
/*0c00*/ @!P2 LOP3.LUT R5, RZ, R8, RZ, 0x33, !PT ; /* 0x00000008ff05a212 */
/* 0x000fc800078e33ff */
/*0c10*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f25270 */
/*0c20*/ @!P1 IMAD R4, R3, 0x4, R0 ; /* 0x0000000403049824 */
/* 0x000fe400078e0200 */
/*0c30*/ @!P1 LDS R3, [R2.X4] ; /* 0x0000000002039984 */
/* 0x000fe80000004800 */
/*0c40*/ @!P1 LDS R4, [R4] ; /* 0x0000000004049984 */
/* 0x000e240000000800 */
/*0c50*/ @!P1 IMAD.IADD R5, R3, 0x1, R4 ; /* 0x0000000103059824 */
/* 0x001fe400078e0204 */
/*0c60*/ IMAD.MOV.U32 R3, RZ, RZ, R8 ; /* 0x000000ffff037224 */
/* 0x000fc600078e0008 */
/*0c70*/ @!P1 STS [R2.X4], R5 ; /* 0x0000000502009388 */
/* 0x0001e80000004800 */
/*0c80*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0c90*/ ISETP.GE.U32.AND P1, PT, R8, c[0x0][0x0], PT ; /* 0x0000000008007a0c */
/* 0x000fda0003f26070 */
/*0ca0*/ @!P1 BRA 0xaf0 ; /* 0xfffffe4000009947 */
/* 0x001fea000383ffff */
/*0cb0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*0cc0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0cd0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*0ce0*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e640000002500 */
/*0cf0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x002fca00078e0003 */
/*0d00*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0d10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d20*/ BRA 0xd20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void iReduceSum(int *idata, int *odata, unsigned int ncols) {
int i;
unsigned int tid = threadIdx.x;
extern __shared__ int sdata[];
unsigned int startPos = blockDim.x + threadIdx.x;
int colsPerThread = ncols/blockDim.x;
int blockOffset = threadIdx.x *(ncols/blockDim.x);
int myPart = 0;
for(i=0;i<colsPerThread;i++) {
myPart+=idata[blockOffset+startPos+i];
}
sdata[tid]=myPart;
__syncthreads();
unsigned int s;
for(s=1;s<blockDim.x;s*=2){
if(tid%(2*s) == 0){
sdata[tid]+=sdata[tid+s];
}
__syncthreads();
}
if(tid==0)odata[blockIdx.x]=sdata[0];
} | .file "tmpxft_00118056_00000000-6_iReduceSum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z10iReduceSumPiS_jPiS_j
.type _Z33__device_stub__Z10iReduceSumPiS_jPiS_j, @function
_Z33__device_stub__Z10iReduceSumPiS_jPiS_j:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10iReduceSumPiS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z10iReduceSumPiS_jPiS_j, .-_Z33__device_stub__Z10iReduceSumPiS_jPiS_j
.globl _Z10iReduceSumPiS_j
.type _Z10iReduceSumPiS_j, @function
_Z10iReduceSumPiS_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10iReduceSumPiS_jPiS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10iReduceSumPiS_j, .-_Z10iReduceSumPiS_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10iReduceSumPiS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10iReduceSumPiS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void iReduceSum(int *idata, int *odata, unsigned int ncols) {
int i;
unsigned int tid = threadIdx.x;
extern __shared__ int sdata[];
unsigned int startPos = blockDim.x + threadIdx.x;
int colsPerThread = ncols/blockDim.x;
int blockOffset = threadIdx.x *(ncols/blockDim.x);
int myPart = 0;
for(i=0;i<colsPerThread;i++) {
myPart+=idata[blockOffset+startPos+i];
}
sdata[tid]=myPart;
__syncthreads();
unsigned int s;
for(s=1;s<blockDim.x;s*=2){
if(tid%(2*s) == 0){
sdata[tid]+=sdata[tid+s];
}
__syncthreads();
}
if(tid==0)odata[blockIdx.x]=sdata[0];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void iReduceSum(int *idata, int *odata, unsigned int ncols) {
int i;
unsigned int tid = threadIdx.x;
extern __shared__ int sdata[];
unsigned int startPos = blockDim.x + threadIdx.x;
int colsPerThread = ncols/blockDim.x;
int blockOffset = threadIdx.x *(ncols/blockDim.x);
int myPart = 0;
for(i=0;i<colsPerThread;i++) {
myPart+=idata[blockOffset+startPos+i];
}
sdata[tid]=myPart;
__syncthreads();
unsigned int s;
for(s=1;s<blockDim.x;s*=2){
if(tid%(2*s) == 0){
sdata[tid]+=sdata[tid+s];
}
__syncthreads();
}
if(tid==0)odata[blockIdx.x]=sdata[0];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void iReduceSum(int *idata, int *odata, unsigned int ncols) {
int i;
unsigned int tid = threadIdx.x;
extern __shared__ int sdata[];
unsigned int startPos = blockDim.x + threadIdx.x;
int colsPerThread = ncols/blockDim.x;
int blockOffset = threadIdx.x *(ncols/blockDim.x);
int myPart = 0;
for(i=0;i<colsPerThread;i++) {
myPart+=idata[blockOffset+startPos+i];
}
sdata[tid]=myPart;
__syncthreads();
unsigned int s;
for(s=1;s<blockDim.x;s*=2){
if(tid%(2*s) == 0){
sdata[tid]+=sdata[tid+s];
}
__syncthreads();
}
if(tid==0)odata[blockIdx.x]=sdata[0];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10iReduceSumPiS_j
.globl _Z10iReduceSumPiS_j
.p2align 8
.type _Z10iReduceSumPiS_j,@function
_Z10iReduceSumPiS_j:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
v_mov_b32_e32 v3, 0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s3
s_sub_i32 s6, 0, s3
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s6, s5
s_mul_hi_u32 s6, s5, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s5, s6
s_mul_hi_u32 s5, s4, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s5, s3
s_sub_i32 s4, s4, s6
s_add_i32 s6, s5, 1
s_sub_i32 s7, s4, s3
s_cmp_ge_u32 s4, s3
s_cselect_b32 s5, s6, s5
s_cselect_b32 s4, s7, s4
s_add_i32 s6, s5, 1
s_cmp_ge_u32 s4, s3
s_mov_b32 s7, 0
s_cselect_b32 s6, s6, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB0_3
s_load_b64 s[4:5], s[0:1], 0x0
v_mul_lo_u32 v1, v0, s6
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, 0
s_delay_alu instid0(VALU_DEP_2)
v_add3_u32 v4, v1, v0, s3
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v1, s7, v4
s_add_i32 s7, s7, 1
s_cmp_lt_i32 s7, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b32 v1, v[5:6], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v1, v3
s_cbranch_scc1 .LBB0_2
.LBB0_3:
v_lshl_add_u32 v1, v0, 2, 0
s_cmp_lt_u32 s3, 2
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_8
s_mov_b32 s5, 1
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s6
s_cmp_lt_u32 s4, s3
s_mov_b32 s5, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_8
.LBB0_6:
s_lshl_b32 s4, s5, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s4, -1
v_and_b32_e32 v2, s6, v0
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_5
v_add_nc_u32_e32 v2, s5, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB0_5
.LBB0_8:
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_10
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10iReduceSumPiS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10iReduceSumPiS_j, .Lfunc_end0-_Z10iReduceSumPiS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10iReduceSumPiS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10iReduceSumPiS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void iReduceSum(int *idata, int *odata, unsigned int ncols) {
int i;
unsigned int tid = threadIdx.x;
extern __shared__ int sdata[];
unsigned int startPos = blockDim.x + threadIdx.x;
int colsPerThread = ncols/blockDim.x;
int blockOffset = threadIdx.x *(ncols/blockDim.x);
int myPart = 0;
for(i=0;i<colsPerThread;i++) {
myPart+=idata[blockOffset+startPos+i];
}
sdata[tid]=myPart;
__syncthreads();
unsigned int s;
for(s=1;s<blockDim.x;s*=2){
if(tid%(2*s) == 0){
sdata[tid]+=sdata[tid+s];
}
__syncthreads();
}
if(tid==0)odata[blockIdx.x]=sdata[0];
} | .text
.file "iReduceSum.hip"
.globl _Z25__device_stub__iReduceSumPiS_j # -- Begin function _Z25__device_stub__iReduceSumPiS_j
.p2align 4, 0x90
.type _Z25__device_stub__iReduceSumPiS_j,@function
_Z25__device_stub__iReduceSumPiS_j: # @_Z25__device_stub__iReduceSumPiS_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10iReduceSumPiS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__iReduceSumPiS_j, .Lfunc_end0-_Z25__device_stub__iReduceSumPiS_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10iReduceSumPiS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10iReduceSumPiS_j,@object # @_Z10iReduceSumPiS_j
.section .rodata,"a",@progbits
.globl _Z10iReduceSumPiS_j
.p2align 3, 0x0
_Z10iReduceSumPiS_j:
.quad _Z25__device_stub__iReduceSumPiS_j
.size _Z10iReduceSumPiS_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10iReduceSumPiS_j"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__iReduceSumPiS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10iReduceSumPiS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10iReduceSumPiS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ I2F.U32.RP R4, c[0x0][0x0] ; /* 0x0000000000047b06 */
/* 0x000e220000209000 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0030*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fe20003f45070 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fc800078e00ff */
/*0060*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0070*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0080*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0090*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00a0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x002fc800078e0a03 */
/*00b0*/ IMAD R5, R5, c[0x0][0x0], RZ ; /* 0x0000000005057a24 */
/* 0x000fc800078e02ff */
/*00c0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fe400078e0002 */
/*00d0*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*00e0*/ IMAD.HI.U32 R3, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a27 */
/* 0x000fc800078e00ff */
/*00f0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a03 */
/*0100*/ IMAD R4, R5, R0, c[0x0][0x170] ; /* 0x00005c0005047624 */
/* 0x000fca00078e0200 */
/*0110*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x0], PT ; /* 0x0000000004007a0c */
/* 0x000fda0003f06070 */
/*0120*/ @P0 IADD3 R4, R4, -c[0x0][0x0], RZ ; /* 0x8000000004040a10 */
/* 0x000fe40007ffe0ff */
/*0130*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe40007ffe0ff */
/*0140*/ ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x0], PT ; /* 0x0000000004007a0c */
/* 0x000fda0003f26070 */
/*0150*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*0160*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff03aa12 */
/* 0x000fc800078e33ff */
/*0170*/ ISETP.GE.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fda0003f06270 */
/*0180*/ @!P0 BRA 0xa80 ; /* 0x000008f000008947 */
/* 0x000fea0003800000 */
/*0190*/ IADD3 R4, R3.reuse, -0x1, RZ ; /* 0xffffffff03047810 */
/* 0x041fe20007ffe0ff */
/*01a0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*01b0*/ IADD3 R6, R2, c[0x0][0x0], RZ ; /* 0x0000000002067a10 */
/* 0x000fe20007ffe0ff */
/*01c0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*01d0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*01e0*/ LOP3.LUT R4, R3.reuse, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303047812 */
/* 0x040fe200078ec0ff */
/*01f0*/ IMAD R6, R3, R2, R6 ; /* 0x0000000203067224 */
/* 0x000fd400078e0206 */
/*0200*/ @!P0 BRA 0x9d0 ; /* 0x000007c000008947 */
/* 0x000fea0003800000 */
/*0210*/ IMAD.IADD R3, R3, 0x1, -R4 ; /* 0x0000000103037824 */
/* 0x000fe400078e0a04 */
/*0220*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fc600078e00ff */
/*0230*/ ISETP.GT.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f04270 */
/*0240*/ @!P0 BRA 0x8a0 ; /* 0x0000065000008947 */
/* 0x000fea0003800000 */
/*0250*/ ISETP.GT.AND P1, PT, R3, 0xc, PT ; /* 0x0000000c0300780c */
/* 0x000fe40003f24270 */
/*0260*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0270*/ @!P1 BRA 0x660 ; /* 0x000003e000009947 */
/* 0x000fea0003800000 */
/*0280*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0290*/ IMAD.IADD R23, R6.reuse, 0x1, R5.reuse ; /* 0x0000000106177824 */
/* 0x140fe200078e0205 */
/*02a0*/ IADD3 R27, R6.reuse, 0x4, R5.reuse ; /* 0x00000004061b7810 */
/* 0x140fe20007ffe005 */
/*02b0*/ IMAD.MOV.U32 R24, RZ, RZ, 0x4 ; /* 0x00000004ff187424 */
/* 0x000fe200078e00ff */
/*02c0*/ IADD3 R19, R6.reuse, 0x8, R5.reuse ; /* 0x0000000806137810 */
/* 0x140fe40007ffe005 */
/*02d0*/ IADD3 R13, R23.reuse, 0x1, RZ ; /* 0x00000001170d7810 */
/* 0x040fe20007ffe0ff */
/*02e0*/ IMAD.WIDE.U32 R20, R23.reuse, R24.reuse, c[0x0][0x160] ; /* 0x0000580017147625 */
/* 0x0c0fe200078e0018 */
/*02f0*/ IADD3 R25, R23.reuse, 0x3, RZ ; /* 0x0000000317197810 */
/* 0x040fe40007ffe0ff */
/*0300*/ IADD3 R15, R23, 0x2, RZ ; /* 0x00000002170f7810 */
/* 0x000fe20007ffe0ff */
/*0310*/ IMAD.WIDE.U32 R12, R13, R24.reuse, c[0x0][0x160] ; /* 0x000058000d0c7625 */
/* 0x080fe200078e0018 */
/*0320*/ IADD3 R17, R6, 0xc, R5 ; /* 0x0000000c06117810 */
/* 0x000fe20007ffe005 */
/*0330*/ LDG.E R8, [R20.64] ; /* 0x0000000414087981 */
/* 0x0000a2000c1e1900 */
/*0340*/ IADD3 R29, R23, 0x5, RZ ; /* 0x00000005171d7810 */
/* 0x000fe20007ffe0ff */
/*0350*/ IMAD.WIDE.U32 R26, R27, R24, c[0x0][0x160] ; /* 0x000058001b1a7625 */
/* 0x000fc400078e0018 */
/*0360*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x0002a4000c1e1900 */
/*0370*/ IMAD.WIDE.U32 R18, R19, R24.reuse, c[0x0][0x160] ; /* 0x0000580013127625 */
/* 0x080fe400078e0018 */
/*0380*/ LDG.E R9, [R26.64] ; /* 0x000000041a097981 */
/* 0x000724000c1e1900 */
/*0390*/ IMAD.WIDE.U32 R20, R25, R24.reuse, c[0x0][0x160] ; /* 0x0000580019147625 */
/* 0x081fe200078e0018 */
/*03a0*/ IADD3 R25, R23, 0x6, RZ ; /* 0x0000000617197810 */
/* 0x000fe20007ffe0ff */
/*03b0*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x000164000c1e1900 */
/*03c0*/ IMAD.WIDE.U32 R14, R15, R24, c[0x0][0x160] ; /* 0x000058000f0e7625 */
/* 0x000fc800078e0018 */
/*03d0*/ IMAD.WIDE.U32 R16, R17, R24.reuse, c[0x0][0x160] ; /* 0x0000580011107625 */
/* 0x080fe200078e0018 */
/*03e0*/ IADD3 R27, R23, 0x7, RZ ; /* 0x00000007171b7810 */
/* 0x008fe20007ffe0ff */
/*03f0*/ LDG.E R13, [R14.64] ; /* 0x000000040e0d7981 */
/* 0x0022e4000c1e1900 */
/*0400*/ IMAD.WIDE.U32 R28, R29, R24.reuse, c[0x0][0x160] ; /* 0x000058001d1c7625 */
/* 0x080fe400078e0018 */
/*0410*/ LDG.E R26, [R20.64] ; /* 0x00000004141a7981 */
/* 0x0002e4000c1e1900 */
/*0420*/ IMAD.WIDE.U32 R18, R25, R24, c[0x0][0x160] ; /* 0x0000580019127625 */
/* 0x001fe200078e0018 */
/*0430*/ IADD3 R25, R23.reuse, 0x9, RZ ; /* 0x0000000917197810 */
/* 0x040fe20007ffe0ff */
/*0440*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000122000c1e1900 */
/*0450*/ IADD3 R22, R23, 0xa, RZ ; /* 0x0000000a17167810 */
/* 0x000fc60007ffe0ff */
/*0460*/ LDG.E R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000122000c1e1900 */
/*0470*/ IMAD.WIDE.U32 R14, R25, R24, c[0x0][0x160] ; /* 0x00005800190e7625 */
/* 0x002fe200078e0018 */
/*0480*/ IADD3 R21, R23, 0xb, RZ ; /* 0x0000000b17157810 */
/* 0x000fc60007ffe0ff */
/*0490*/ IMAD.WIDE.U32 R16, R27, R24.reuse, c[0x0][0x160] ; /* 0x000058001b107625 */
/* 0x081fe200078e0018 */
/*04a0*/ IADD3 R25, R23, 0xd, RZ ; /* 0x0000000d17197810 */
/* 0x000fe20007ffe0ff */
/*04b0*/ LDG.E R27, [R18.64] ; /* 0x00000004121b7981 */
/* 0x000168000c1e1900 */
/*04c0*/ LDG.E R29, [R16.64] ; /* 0x00000004101d7981 */
/* 0x000368000c1e1900 */
/*04d0*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000f62000c1e1900 */
/*04e0*/ IMAD.WIDE.U32 R18, R21, R24, c[0x0][0x160] ; /* 0x0000580015127625 */
/* 0x001fc800078e0018 */
/*04f0*/ IMAD.WIDE.U32 R16, R22, R24.reuse, c[0x0][0x160] ; /* 0x0000580016107625 */
/* 0x082fe200078e0018 */
/*0500*/ IADD3 R22, R23, 0xe, RZ ; /* 0x0000000e17167810 */
/* 0x000fe20007ffe0ff */
/*0510*/ LDG.E R19, [R18.64] ; /* 0x0000000412137981 */
/* 0x000f64000c1e1900 */
/*0520*/ IMAD.WIDE.U32 R20, R25, R24.reuse, c[0x0][0x160] ; /* 0x0000580019147625 */
/* 0x080fe200078e0018 */
/*0530*/ IADD3 R25, R23, 0xf, RZ ; /* 0x0000000f17197810 */
/* 0x000fe20007ffe0ff */
/*0540*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f64000c1e1900 */
/*0550*/ IMAD.WIDE.U32 R22, R22, R24.reuse, c[0x0][0x160] ; /* 0x0000580016167625 */
/* 0x080fe400078e0018 */
/*0560*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000f64000c1e1900 */
/*0570*/ IMAD.WIDE.U32 R24, R25, R24, c[0x0][0x160] ; /* 0x0000580019187625 */
/* 0x000fc400078e0018 */
/*0580*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000f68000c1e1900 */
/*0590*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000f62000c1e1900 */
/*05a0*/ IADD3 R3, R3, -0x10, RZ ; /* 0xfffffff003037810 */
/* 0x000fc80007ffe0ff */
/*05b0*/ ISETP.GT.AND P1, PT, R3, 0xc, PT ; /* 0x0000000c0300780c */
/* 0x000fe40003f24270 */
/*05c0*/ IADD3 R5, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x000fe40007ffe0ff */
/*05d0*/ IADD3 R8, R12, R8, R7 ; /* 0x000000080c087210 */
/* 0x004fc80007ffe007 */
/*05e0*/ IADD3 R8, R26, R13, R8 ; /* 0x0000000d1a087210 */
/* 0x008fc80007ffe008 */
/*05f0*/ IADD3 R8, R28, R9, R8 ; /* 0x000000091c087210 */
/* 0x010fc80007ffe008 */
/*0600*/ IADD3 R8, R29, R27, R8 ; /* 0x0000001b1d087210 */
/* 0x020fc80007ffe008 */
/*0610*/ IADD3 R8, R15, R10, R8 ; /* 0x0000000a0f087210 */
/* 0x000fc80007ffe008 */
/*0620*/ IADD3 R8, R19, R16, R8 ; /* 0x0000001013087210 */
/* 0x000fc80007ffe008 */
/*0630*/ IADD3 R8, R20, R11, R8 ; /* 0x0000000b14087210 */
/* 0x000fc80007ffe008 */
/*0640*/ IADD3 R7, R25, R22, R8 ; /* 0x0000001619077210 */
/* 0x000fe20007ffe008 */
/*0650*/ @P1 BRA 0x290 ; /* 0xfffffc3000001947 */
/* 0x000fea000383ffff */
/*0660*/ ISETP.GT.AND P1, PT, R3, 0x4, PT ; /* 0x000000040300780c */
/* 0x000fda0003f24270 */
/*0670*/ @!P1 BRA 0x880 ; /* 0x0000020000009947 */
/* 0x000fea0003800000 */
/*0680*/ IMAD.IADD R9, R6, 0x1, R5 ; /* 0x0000000106097824 */
/* 0x000fe400078e0205 */
/*0690*/ IMAD.MOV.U32 R18, RZ, RZ, 0x4 ; /* 0x00000004ff127424 */
/* 0x000fc600078e00ff */
/*06a0*/ IADD3 R15, R9.reuse, 0x1, RZ ; /* 0x00000001090f7810 */
/* 0x040fe20007ffe0ff */
/*06b0*/ IMAD.WIDE.U32 R22, R9.reuse, R18.reuse, c[0x0][0x160] ; /* 0x0000580009167625 */
/* 0x0c0fe200078e0012 */
/*06c0*/ IADD3 R17, R9.reuse, 0x2, RZ ; /* 0x0000000209117810 */
/* 0x040fe40007ffe0ff */
/*06d0*/ IADD3 R11, R9, 0x3, RZ ; /* 0x00000003090b7810 */
/* 0x000fe20007ffe0ff */
/*06e0*/ IMAD.WIDE.U32 R14, R15, R18.reuse, c[0x0][0x160] ; /* 0x000058000f0e7625 */
/* 0x080fe200078e0012 */
/*06f0*/ IADD3 R13, R6, 0x4, R5 ; /* 0x00000004060d7810 */
/* 0x000fe20007ffe005 */
/*0700*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000ea2000c1e1900 */
/*0710*/ IADD3 R19, R9, 0x5, RZ ; /* 0x0000000509137810 */
/* 0x000fe20007ffe0ff */
/*0720*/ IMAD.WIDE.U32 R16, R17, R18.reuse, c[0x0][0x160] ; /* 0x0000580011107625 */
/* 0x080fe200078e0012 */
/*0730*/ IADD3 R21, R9, 0x6, RZ ; /* 0x0000000609157810 */
/* 0x000fe20007ffe0ff */
/*0740*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea4000c1e1900 */
/*0750*/ IMAD.WIDE.U32 R10, R11, R18.reuse, c[0x0][0x160] ; /* 0x000058000b0a7625 */
/* 0x080fe200078e0012 */
/*0760*/ IADD3 R25, R9, 0x7, RZ ; /* 0x0000000709197810 */
/* 0x000fe20007ffe0ff */
/*0770*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ee4000c1e1900 */
/*0780*/ IMAD.WIDE.U32 R12, R13, R18, c[0x0][0x160] ; /* 0x000058000d0c7625 */
/* 0x000fc400078e0012 */
/*0790*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee4000c1e1900 */
/*07a0*/ IMAD.WIDE.U32 R8, R19, R18.reuse, c[0x0][0x160] ; /* 0x0000580013087625 */
/* 0x080fe400078e0012 */
/*07b0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f24000c1e1900 */
/*07c0*/ IMAD.WIDE.U32 R20, R21, R18.reuse, c[0x0][0x160] ; /* 0x0000580015147625 */
/* 0x080fe400078e0012 */
/*07d0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f24000c1e1900 */
/*07e0*/ IMAD.WIDE.U32 R18, R25, R18, c[0x0][0x160] ; /* 0x0000580019127625 */
/* 0x000fc400078e0012 */
/*07f0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000f68000c1e1900 */
/*0800*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f62000c1e1900 */
/*0810*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0820*/ IADD3 R3, R3, -0x8, RZ ; /* 0xfffffff803037810 */
/* 0x000fe40007ffe0ff */
/*0830*/ IADD3 R5, R5, 0x8, RZ ; /* 0x0000000805057810 */
/* 0x000fe40007ffe0ff */
/*0840*/ IADD3 R7, R14, R22, R7 ; /* 0x000000160e077210 */
/* 0x004fc80007ffe007 */
/*0850*/ IADD3 R7, R10, R16, R7 ; /* 0x000000100a077210 */
/* 0x008fc80007ffe007 */
/*0860*/ IADD3 R7, R8, R12, R7 ; /* 0x0000000c08077210 */
/* 0x010fc80007ffe007 */
/*0870*/ IADD3 R7, R18, R20, R7 ; /* 0x0000001412077210 */
/* 0x020fe40007ffe007 */
/*0880*/ ISETP.NE.OR P0, PT, R3, RZ, P0 ; /* 0x000000ff0300720c */
/* 0x000fda0000705670 */
/*0890*/ @!P0 BRA 0x9d0 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*08a0*/ IMAD.IADD R8, R6, 0x1, R5 ; /* 0x0000000106087824 */
/* 0x000fe400078e0205 */
/*08b0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fc600078e00ff */
/*08c0*/ IADD3 R12, R8.reuse, 0x1, RZ ; /* 0x00000001080c7810 */
/* 0x040fe20007ffe0ff */
/*08d0*/ IMAD.WIDE.U32 R10, R8.reuse, R15.reuse, c[0x0][0x160] ; /* 0x00005800080a7625 */
/* 0x0c0fe200078e000f */
/*08e0*/ IADD3 R14, R8.reuse, 0x2, RZ ; /* 0x00000002080e7810 */
/* 0x040fe40007ffe0ff */
/*08f0*/ IADD3 R16, R8, 0x3, RZ ; /* 0x0000000308107810 */
/* 0x000fe20007ffe0ff */
/*0900*/ IMAD.WIDE.U32 R8, R12, R15.reuse, c[0x0][0x160] ; /* 0x000058000c087625 */
/* 0x080fe400078e000f */
/*0910*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea4000c1e1900 */
/*0920*/ IMAD.WIDE.U32 R12, R14, R15.reuse, c[0x0][0x160] ; /* 0x000058000e0c7625 */
/* 0x080fe400078e000f */
/*0930*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea4000c1e1900 */
/*0940*/ IMAD.WIDE.U32 R14, R16, R15, c[0x0][0x160] ; /* 0x00005800100e7625 */
/* 0x000fc400078e000f */
/*0950*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee8000c1e1900 */
/*0960*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*0970*/ IADD3 R3, R3, -0x4, RZ ; /* 0xfffffffc03037810 */
/* 0x000fc80007ffe0ff */
/*0980*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f05270 */
/*0990*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fe40007ffe0ff */
/*09a0*/ IADD3 R7, R8, R10, R7 ; /* 0x0000000a08077210 */
/* 0x004fc80007ffe007 */
/*09b0*/ IADD3 R7, R14, R12, R7 ; /* 0x0000000c0e077210 */
/* 0x008fca0007ffe007 */
/*09c0*/ @P0 BRA 0x8a0 ; /* 0xfffffed000000947 */
/* 0x000fea000383ffff */
/*09d0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*09e0*/ @!P0 BRA 0xa80 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*09f0*/ IMAD.IADD R8, R6, 0x1, R5 ; /* 0x0000000106087824 */
/* 0x000fe400078e0205 */
/*0a00*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc800078e00ff */
/*0a10*/ IMAD.WIDE.U32 R8, R8, R9, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fcc00078e0009 */
/*0a20*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1900 */
/*0a30*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0a40*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe40007ffe0ff */
/*0a50*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0a60*/ IMAD.IADD R7, R8, 0x1, R7 ; /* 0x0000000108077824 */
/* 0x004fd800078e0207 */
/*0a70*/ @P0 BRA 0x9f0 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0a80*/ ISETP.GE.U32.AND P1, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x001fe20003f26070 */
/*0a90*/ STS [R2.X4], R7 ; /* 0x0000000702007388 */
/* 0x0001e80000004800 */
/*0aa0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0ab0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fce0003f05270 */
/*0ac0*/ @!P1 BRA 0xcb0 ; /* 0x000001e000009947 */
/* 0x000fec0003800000 */
/*0ad0*/ IMAD.SHL.U32 R0, R2, 0x4, RZ ; /* 0x0000000402007824 */
/* 0x001fe400078e00ff */
/*0ae0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x1 ; /* 0x00000001ff037424 */
/* 0x000fc800078e00ff */
/*0af0*/ IMAD.SHL.U32 R8, R3, 0x2, RZ ; /* 0x0000000203087824 */
/* 0x000fc800078e00ff */
/*0b00*/ I2F.U32.RP R6, R8 ; /* 0x0000000800067306 */
/* 0x000e220000209000 */
/*0b10*/ IMAD.MOV R7, RZ, RZ, -R8 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a08 */
/*0b20*/ ISETP.NE.U32.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fcc0003f45070 */
/*0b30*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0b40*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0b50*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0b60*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0b70*/ IMAD R7, R7, R5, RZ ; /* 0x0000000507077224 */
/* 0x002fc800078e02ff */
/*0b80*/ IMAD.HI.U32 R5, R5, R7, R4 ; /* 0x0000000705057227 */
/* 0x000fcc00078e0004 */
/*0b90*/ IMAD.HI.U32 R5, R5, R2, RZ ; /* 0x0000000205057227 */
/* 0x000fc800078e00ff */
/*0ba0*/ IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a05 */
/*0bb0*/ IMAD R5, R8, R5, R2 ; /* 0x0000000508057224 */
/* 0x000fca00078e0202 */
/*0bc0*/ ISETP.GE.U32.AND P1, PT, R5, R8, PT ; /* 0x000000080500720c */
/* 0x000fda0003f26070 */
/*0bd0*/ @P1 IMAD.IADD R5, R5, 0x1, -R8 ; /* 0x0000000105051824 */
/* 0x000fca00078e0a08 */
/*0be0*/ ISETP.GE.U32.AND P1, PT, R5, R8, PT ; /* 0x000000080500720c */
/* 0x000fda0003f26070 */
/*0bf0*/ @P1 IMAD.IADD R5, R5, 0x1, -R8 ; /* 0x0000000105051824 */
/* 0x000fe200078e0a08 */
/*0c00*/ @!P2 LOP3.LUT R5, RZ, R8, RZ, 0x33, !PT ; /* 0x00000008ff05a212 */
/* 0x000fc800078e33ff */
/*0c10*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f25270 */
/*0c20*/ @!P1 IMAD R4, R3, 0x4, R0 ; /* 0x0000000403049824 */
/* 0x000fe400078e0200 */
/*0c30*/ @!P1 LDS R3, [R2.X4] ; /* 0x0000000002039984 */
/* 0x000fe80000004800 */
/*0c40*/ @!P1 LDS R4, [R4] ; /* 0x0000000004049984 */
/* 0x000e240000000800 */
/*0c50*/ @!P1 IMAD.IADD R5, R3, 0x1, R4 ; /* 0x0000000103059824 */
/* 0x001fe400078e0204 */
/*0c60*/ IMAD.MOV.U32 R3, RZ, RZ, R8 ; /* 0x000000ffff037224 */
/* 0x000fc600078e0008 */
/*0c70*/ @!P1 STS [R2.X4], R5 ; /* 0x0000000502009388 */
/* 0x0001e80000004800 */
/*0c80*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0c90*/ ISETP.GE.U32.AND P1, PT, R8, c[0x0][0x0], PT ; /* 0x0000000008007a0c */
/* 0x000fda0003f26070 */
/*0ca0*/ @!P1 BRA 0xaf0 ; /* 0xfffffe4000009947 */
/* 0x001fea000383ffff */
/*0cb0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*0cc0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0cd0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*0ce0*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e640000002500 */
/*0cf0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x002fca00078e0003 */
/*0d00*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0d10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d20*/ BRA 0xd20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10iReduceSumPiS_j
.globl _Z10iReduceSumPiS_j
.p2align 8
.type _Z10iReduceSumPiS_j,@function
_Z10iReduceSumPiS_j:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
v_mov_b32_e32 v3, 0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s3
s_sub_i32 s6, 0, s3
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s6, s5
s_mul_hi_u32 s6, s5, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s5, s6
s_mul_hi_u32 s5, s4, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s5, s3
s_sub_i32 s4, s4, s6
s_add_i32 s6, s5, 1
s_sub_i32 s7, s4, s3
s_cmp_ge_u32 s4, s3
s_cselect_b32 s5, s6, s5
s_cselect_b32 s4, s7, s4
s_add_i32 s6, s5, 1
s_cmp_ge_u32 s4, s3
s_mov_b32 s7, 0
s_cselect_b32 s6, s6, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB0_3
s_load_b64 s[4:5], s[0:1], 0x0
v_mul_lo_u32 v1, v0, s6
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, 0
s_delay_alu instid0(VALU_DEP_2)
v_add3_u32 v4, v1, v0, s3
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v1, s7, v4
s_add_i32 s7, s7, 1
s_cmp_lt_i32 s7, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b32 v1, v[5:6], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v1, v3
s_cbranch_scc1 .LBB0_2
.LBB0_3:
v_lshl_add_u32 v1, v0, 2, 0
s_cmp_lt_u32 s3, 2
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_8
s_mov_b32 s5, 1
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s6
s_cmp_lt_u32 s4, s3
s_mov_b32 s5, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_8
.LBB0_6:
s_lshl_b32 s4, s5, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s4, -1
v_and_b32_e32 v2, s6, v0
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_5
v_add_nc_u32_e32 v2, s5, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB0_5
.LBB0_8:
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_10
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10iReduceSumPiS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10iReduceSumPiS_j, .Lfunc_end0-_Z10iReduceSumPiS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10iReduceSumPiS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10iReduceSumPiS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00118056_00000000-6_iReduceSum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z10iReduceSumPiS_jPiS_j
.type _Z33__device_stub__Z10iReduceSumPiS_jPiS_j, @function
_Z33__device_stub__Z10iReduceSumPiS_jPiS_j:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10iReduceSumPiS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z10iReduceSumPiS_jPiS_j, .-_Z33__device_stub__Z10iReduceSumPiS_jPiS_j
.globl _Z10iReduceSumPiS_j
.type _Z10iReduceSumPiS_j, @function
_Z10iReduceSumPiS_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10iReduceSumPiS_jPiS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10iReduceSumPiS_j, .-_Z10iReduceSumPiS_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10iReduceSumPiS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10iReduceSumPiS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "iReduceSum.hip"
.globl _Z25__device_stub__iReduceSumPiS_j # -- Begin function _Z25__device_stub__iReduceSumPiS_j
.p2align 4, 0x90
.type _Z25__device_stub__iReduceSumPiS_j,@function
_Z25__device_stub__iReduceSumPiS_j: # @_Z25__device_stub__iReduceSumPiS_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10iReduceSumPiS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__iReduceSumPiS_j, .Lfunc_end0-_Z25__device_stub__iReduceSumPiS_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10iReduceSumPiS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10iReduceSumPiS_j,@object # @_Z10iReduceSumPiS_j
.section .rodata,"a",@progbits
.globl _Z10iReduceSumPiS_j
.p2align 3, 0x0
_Z10iReduceSumPiS_j:
.quad _Z25__device_stub__iReduceSumPiS_j
.size _Z10iReduceSumPiS_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10iReduceSumPiS_j"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__iReduceSumPiS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10iReduceSumPiS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdio.h>
#define cuda_safe_call(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code,
const char *file,
int line,
bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n",
cudaGetErrorString(code),
file,
line);
if (abort)
exit(code);
}
}
__global__ void kernel_hello()
{
printf("Hello from the device.\n");
}
int main()
{
printf("Hello from the host.\n");
kernel_hello<<<1,1>>>();
cuda_safe_call(cudaDeviceSynchronize());
printf("Success!\n");
return 0;
} | code for sm_80
Function : _Z12kernel_hellov
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdio.h>
#define cuda_safe_call(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code,
const char *file,
int line,
bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n",
cudaGetErrorString(code),
file,
line);
if (abort)
exit(code);
}
}
__global__ void kernel_hello()
{
printf("Hello from the device.\n");
}
int main()
{
printf("Hello from the host.\n");
kernel_hello<<<1,1>>>();
cuda_safe_call(cudaDeviceSynchronize());
printf("Success!\n");
return 0;
} | .file "tmpxft_00155ea2_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z12kernel_hellovv
.type _Z31__device_stub__Z12kernel_hellovv, @function
_Z31__device_stub__Z12kernel_hellovv:
.LFB2083:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12kernel_hellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z31__device_stub__Z12kernel_hellovv, .-_Z31__device_stub__Z12kernel_hellovv
.globl _Z12kernel_hellov
.type _Z12kernel_hellov, @function
_Z12kernel_hellov:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z12kernel_hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z12kernel_hellov, .-_Z12kernel_hellov
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello from the host.\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/Li0nMo0se/cuda-install-ubuntu/main/main.cu"
.section .rodata.str1.1
.LC2:
.string "GPUassert: %s %s %d\n"
.LC3:
.string "Success!\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L16
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call _Z31__device_stub__Z12kernel_hellovv
jmp .L12
.L16:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $31, %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z12kernel_hellov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z12kernel_hellov(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdio.h>
#define cuda_safe_call(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code,
const char *file,
int line,
bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n",
cudaGetErrorString(code),
file,
line);
if (abort)
exit(code);
}
}
__global__ void kernel_hello()
{
printf("Hello from the device.\n");
}
int main()
{
printf("Hello from the host.\n");
kernel_hello<<<1,1>>>();
cuda_safe_call(cudaDeviceSynchronize());
printf("Success!\n");
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define cuda_safe_call(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code,
const char *file,
int line,
bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n",
hipGetErrorString(code),
file,
line);
if (abort)
exit(code);
}
}
__global__ void kernel_hello()
{
printf("Hello from the device.\n");
}
int main()
{
printf("Hello from the host.\n");
kernel_hello<<<1,1>>>();
cuda_safe_call(hipDeviceSynchronize());
printf("Success!\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define cuda_safe_call(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code,
const char *file,
int line,
bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n",
hipGetErrorString(code),
file,
line);
if (abort)
exit(code);
}
}
__global__ void kernel_hello()
{
printf("Hello from the device.\n");
}
int main()
{
printf("Hello from the host.\n");
kernel_hello<<<1,1>>>();
cuda_safe_call(hipDeviceSynchronize());
printf("Success!\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12kernel_hellov
.globl _Z12kernel_hellov
.p2align 8
.type _Z12kernel_hellov,@function
_Z12kernel_hellov:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 24
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12kernel_hellov
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12kernel_hellov, .Lfunc_end0-_Z12kernel_hellov
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello from the device.\n"
.size .str, 24
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12kernel_hellov
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z12kernel_hellov.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define cuda_safe_call(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code,
const char *file,
int line,
bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n",
hipGetErrorString(code),
file,
line);
if (abort)
exit(code);
}
}
__global__ void kernel_hello()
{
printf("Hello from the device.\n");
}
int main()
{
printf("Hello from the host.\n");
kernel_hello<<<1,1>>>();
cuda_safe_call(hipDeviceSynchronize());
printf("Success!\n");
return 0;
} | .text
.file "main.hip"
.globl _Z27__device_stub__kernel_hellov # -- Begin function _Z27__device_stub__kernel_hellov
.p2align 4, 0x90
.type _Z27__device_stub__kernel_hellov,@function
_Z27__device_stub__kernel_hellov: # @_Z27__device_stub__kernel_hellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12kernel_hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z27__device_stub__kernel_hellov, .Lfunc_end0-_Z27__device_stub__kernel_hellov
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $56, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12kernel_hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_4
# %bb.3: # %_Z9gpuAssert10hipError_tPKcib.exit
movl $.Lstr.1, %edi
callq puts@PLT
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_4:
.cfi_def_cfa_offset 80
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $31, %r8d
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12kernel_hellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12kernel_hellov,@object # @_Z12kernel_hellov
.section .rodata,"a",@progbits
.globl _Z12kernel_hellov
.p2align 3, 0x0
_Z12kernel_hellov:
.quad _Z27__device_stub__kernel_hellov
.size _Z12kernel_hellov, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/Li0nMo0se/cuda-install-ubuntu/main/main.hip"
.size .L.str.1, 101
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.3, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12kernel_hellov"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello from the host."
.size .Lstr, 21
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Success!"
.size .Lstr.1, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__kernel_hellov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12kernel_hellov
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12kernel_hellov
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12kernel_hellov
.globl _Z12kernel_hellov
.p2align 8
.type _Z12kernel_hellov,@function
_Z12kernel_hellov:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 24
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12kernel_hellov
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12kernel_hellov, .Lfunc_end0-_Z12kernel_hellov
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello from the device.\n"
.size .str, 24
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12kernel_hellov
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z12kernel_hellov.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00155ea2_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z12kernel_hellovv
.type _Z31__device_stub__Z12kernel_hellovv, @function
_Z31__device_stub__Z12kernel_hellovv:
.LFB2083:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12kernel_hellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z31__device_stub__Z12kernel_hellovv, .-_Z31__device_stub__Z12kernel_hellovv
.globl _Z12kernel_hellov
.type _Z12kernel_hellov, @function
_Z12kernel_hellov:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z12kernel_hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z12kernel_hellov, .-_Z12kernel_hellov
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello from the host.\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/Li0nMo0se/cuda-install-ubuntu/main/main.cu"
.section .rodata.str1.1
.LC2:
.string "GPUassert: %s %s %d\n"
.LC3:
.string "Success!\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L16
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call _Z31__device_stub__Z12kernel_hellovv
jmp .L12
.L16:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $31, %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z12kernel_hellov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z12kernel_hellov(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z27__device_stub__kernel_hellov # -- Begin function _Z27__device_stub__kernel_hellov
.p2align 4, 0x90
.type _Z27__device_stub__kernel_hellov,@function
_Z27__device_stub__kernel_hellov: # @_Z27__device_stub__kernel_hellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12kernel_hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z27__device_stub__kernel_hellov, .Lfunc_end0-_Z27__device_stub__kernel_hellov
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $56, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12kernel_hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_4
# %bb.3: # %_Z9gpuAssert10hipError_tPKcib.exit
movl $.Lstr.1, %edi
callq puts@PLT
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_4:
.cfi_def_cfa_offset 80
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $31, %r8d
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12kernel_hellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12kernel_hellov,@object # @_Z12kernel_hellov
.section .rodata,"a",@progbits
.globl _Z12kernel_hellov
.p2align 3, 0x0
_Z12kernel_hellov:
.quad _Z27__device_stub__kernel_hellov
.size _Z12kernel_hellov, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/Li0nMo0se/cuda-install-ubuntu/main/main.hip"
.size .L.str.1, 101
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.3, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12kernel_hellov"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello from the host."
.size .Lstr, 21
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Success!"
.size .Lstr.1, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__kernel_hellov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12kernel_hellov
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <math.h>
void generateRuns(int *** inputRuns,int * length,int N){
// GetGPUProperties
cudaDeviceProp props;
cudaGetDeviceProperties(&props,0);
// Get maximum threads, blocks and grids
printf("Generating test runs using N= %d:\n",N);
printf("GPU Info\n");
printf("Name: %s\n",props.name);
printf("Max Threads Per Block %d\n",props.maxThreadsPerBlock);
printf("Max Threads Size %d %d %d\n",
props.maxThreadsDim[0],
props.maxThreadsDim[1],
props.maxThreadsDim[2]);
printf("Max Grid Size %d %d %d\n",
props.maxGridSize[0],
props.maxGridSize[1],
props.maxGridSize[2]);
printf("Compute Capability %d\n",props.major);
/* Get total number of tests- from linear to squared,
from threads to blocks */
int t;
if(N*N<props.maxThreadsPerBlock)
t = N*N;
else
t= props.maxThreadsPerBlock;
int b = N*N/t+1;
int threadsToBlocksTests = log2(t/32.0) + 1;
int linearToSquareTests = log2(t/1.0) + 1;
printf("%d %d\n",threadsToBlocksTests,linearToSquareTests);
*length = threadsToBlocksTests + linearToSquareTests;
// Allocate runs
int ** runs = (int**)malloc((*length)*sizeof(int*));
for(int i=0;i<*length;i++){
runs[i] = (int*)malloc(6*sizeof(int));
}
// Generate the block, grid, threads
// From linear to squared
int j = 0;
int i;
for(i=1;j<threadsToBlocksTests;i*=2){
runs[j][0]= t/i;
runs[j][1]= 1;
runs[j][2]= 1;
runs[j][3]= b*i;
runs[j][4]= 1;
runs[j][5]= 1;
j++;
}
// From threads to blocks
for(i=1;j<*length;i*=2){
runs[j][0]= t/i;
runs[j][1]= i;
runs[j][2]= 1;
runs[j][3]= b;
runs[j][4]= 1;
runs[j][5]= 1;
j++;
}
*inputRuns = runs;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <math.h>
void generateRuns(int *** inputRuns,int * length,int N){
// GetGPUProperties
cudaDeviceProp props;
cudaGetDeviceProperties(&props,0);
// Get maximum threads, blocks and grids
printf("Generating test runs using N= %d:\n",N);
printf("GPU Info\n");
printf("Name: %s\n",props.name);
printf("Max Threads Per Block %d\n",props.maxThreadsPerBlock);
printf("Max Threads Size %d %d %d\n",
props.maxThreadsDim[0],
props.maxThreadsDim[1],
props.maxThreadsDim[2]);
printf("Max Grid Size %d %d %d\n",
props.maxGridSize[0],
props.maxGridSize[1],
props.maxGridSize[2]);
printf("Compute Capability %d\n",props.major);
/* Get total number of tests- from linear to squared,
from threads to blocks */
int t;
if(N*N<props.maxThreadsPerBlock)
t = N*N;
else
t= props.maxThreadsPerBlock;
int b = N*N/t+1;
int threadsToBlocksTests = log2(t/32.0) + 1;
int linearToSquareTests = log2(t/1.0) + 1;
printf("%d %d\n",threadsToBlocksTests,linearToSquareTests);
*length = threadsToBlocksTests + linearToSquareTests;
// Allocate runs
int ** runs = (int**)malloc((*length)*sizeof(int*));
for(int i=0;i<*length;i++){
runs[i] = (int*)malloc(6*sizeof(int));
}
// Generate the block, grid, threads
// From linear to squared
int j = 0;
int i;
for(i=1;j<threadsToBlocksTests;i*=2){
runs[j][0]= t/i;
runs[j][1]= 1;
runs[j][2]= 1;
runs[j][3]= b*i;
runs[j][4]= 1;
runs[j][5]= 1;
j++;
}
// From threads to blocks
for(i=1;j<*length;i*=2){
runs[j][0]= t/i;
runs[j][1]= i;
runs[j][2]= 1;
runs[j][3]= b;
runs[j][4]= 1;
runs[j][5]= 1;
j++;
}
*inputRuns = runs;
} | .file "tmpxft_0000c666_00000000-6_generateRuns.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Generating test runs using N= %d:\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "GPU Info\n"
.LC2:
.string "Name: %s\n"
.LC3:
.string "Max Threads Per Block %d\n"
.LC4:
.string "Max Threads Size %d %d %d\n"
.LC5:
.string "Max Grid Size %d %d %d\n"
.LC6:
.string "Compute Capability %d\n"
.LC9:
.string "%d %d\n"
.text
.globl _Z12generateRunsPPPiS_i
.type _Z12generateRunsPPPiS_i, @function
_Z12generateRunsPPPiS_i:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %rdi, 8(%rsp)
movq %rsi, %r14
movl %edx, %r13d
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rbx
movl $0, %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movl %r13d, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 376(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %eax
imull %r13d, %eax
movl 336(%rsp), %ebx
cmpl %ebx, %eax
cmovle %eax, %ebx
cltd
idivl %ebx
leal 1(%rax), %r13d
pxor %xmm1, %xmm1
cvtsi2sdl %ebx, %xmm1
movq %xmm1, %rbp
movapd %xmm1, %xmm0
mulsd .LC7(%rip), %xmm0
call log2@PLT
addsd .LC8(%rip), %xmm0
cvttsd2sil %xmm0, %r12d
movq %rbp, %xmm0
call log2@PLT
addsd .LC8(%rip), %xmm0
cvttsd2sil %xmm0, %ebp
movl %ebp, %ecx
movl %r12d, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl %r12d, %ebp
movl %ebp, (%r14)
movslq %ebp, %rbp
leaq 0(,%rbp,8), %rdi
call malloc@PLT
movq %rax, %r15
cmpl $0, (%r14)
jle .L4
movl $0, %ebp
.L5:
movl $24, %edi
call malloc@PLT
movq %rax, (%r15,%rbp,8)
addq $1, %rbp
cmpl %ebp, (%r14)
jg .L5
testl %r12d, %r12d
jle .L12
.L10:
movq %r15, %rcx
movslq %r12d, %rax
leaq (%r15,%rax,8), %rdi
movl $1, %esi
.L7:
movq (%rcx), %r8
movl %ebx, %eax
cltd
idivl %esi
movl %eax, (%r8)
movq (%rcx), %rax
movl $1, 4(%rax)
movq (%rcx), %rax
movl $1, 8(%rax)
movq (%rcx), %rax
movl %r13d, %edx
imull %esi, %edx
movl %edx, 12(%rax)
movq (%rcx), %rax
movl $1, 16(%rax)
movq (%rcx), %rax
movl $1, 20(%rax)
addl %esi, %esi
addq $8, %rcx
cmpq %rdi, %rcx
jne .L7
.L6:
cmpl %r12d, (%r14)
jle .L8
movslq %r12d, %rax
leaq (%r15,%rax,8), %rcx
movl $1, %esi
.L9:
movq (%rcx), %rdi
movl %ebx, %eax
cltd
idivl %esi
movl %eax, (%rdi)
movq (%rcx), %rax
movl %esi, 4(%rax)
movq (%rcx), %rax
movl $1, 8(%rax)
movq (%rcx), %rax
movl %r13d, 12(%rax)
movq (%rcx), %rax
movl $1, 16(%rax)
movq (%rcx), %rax
movl $1, 20(%rax)
addl $1, %r12d
addl %esi, %esi
addq $8, %rcx
cmpl %r12d, (%r14)
jg .L9
.L8:
movq 8(%rsp), %rax
movq %r15, (%rax)
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movl $0, %r12d
jmp .L6
.L4:
testl %r12d, %r12d
jg .L10
jmp .L8
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z12generateRunsPPPiS_i, .-_Z12generateRunsPPPiS_i
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC7:
.long 0
.long 1067450368
.align 8
.LC8:
.long 0
.long 1072693248
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <math.h>
void generateRuns(int *** inputRuns,int * length,int N){
// GetGPUProperties
cudaDeviceProp props;
cudaGetDeviceProperties(&props,0);
// Get maximum threads, blocks and grids
printf("Generating test runs using N= %d:\n",N);
printf("GPU Info\n");
printf("Name: %s\n",props.name);
printf("Max Threads Per Block %d\n",props.maxThreadsPerBlock);
printf("Max Threads Size %d %d %d\n",
props.maxThreadsDim[0],
props.maxThreadsDim[1],
props.maxThreadsDim[2]);
printf("Max Grid Size %d %d %d\n",
props.maxGridSize[0],
props.maxGridSize[1],
props.maxGridSize[2]);
printf("Compute Capability %d\n",props.major);
/* Get total number of tests- from linear to squared,
from threads to blocks */
int t;
if(N*N<props.maxThreadsPerBlock)
t = N*N;
else
t= props.maxThreadsPerBlock;
int b = N*N/t+1;
int threadsToBlocksTests = log2(t/32.0) + 1;
int linearToSquareTests = log2(t/1.0) + 1;
printf("%d %d\n",threadsToBlocksTests,linearToSquareTests);
*length = threadsToBlocksTests + linearToSquareTests;
// Allocate runs
int ** runs = (int**)malloc((*length)*sizeof(int*));
for(int i=0;i<*length;i++){
runs[i] = (int*)malloc(6*sizeof(int));
}
// Generate the block, grid, threads
// From linear to squared
int j = 0;
int i;
for(i=1;j<threadsToBlocksTests;i*=2){
runs[j][0]= t/i;
runs[j][1]= 1;
runs[j][2]= 1;
runs[j][3]= b*i;
runs[j][4]= 1;
runs[j][5]= 1;
j++;
}
// From threads to blocks
for(i=1;j<*length;i*=2){
runs[j][0]= t/i;
runs[j][1]= i;
runs[j][2]= 1;
runs[j][3]= b;
runs[j][4]= 1;
runs[j][5]= 1;
j++;
}
*inputRuns = runs;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
void generateRuns(int *** inputRuns,int * length,int N){
// GetGPUProperties
hipDeviceProp_t props;
hipGetDeviceProperties(&props,0);
// Get maximum threads, blocks and grids
printf("Generating test runs using N= %d:\n",N);
printf("GPU Info\n");
printf("Name: %s\n",props.name);
printf("Max Threads Per Block %d\n",props.maxThreadsPerBlock);
printf("Max Threads Size %d %d %d\n",
props.maxThreadsDim[0],
props.maxThreadsDim[1],
props.maxThreadsDim[2]);
printf("Max Grid Size %d %d %d\n",
props.maxGridSize[0],
props.maxGridSize[1],
props.maxGridSize[2]);
printf("Compute Capability %d\n",props.major);
/* Get total number of tests- from linear to squared,
from threads to blocks */
int t;
if(N*N<props.maxThreadsPerBlock)
t = N*N;
else
t= props.maxThreadsPerBlock;
int b = N*N/t+1;
int threadsToBlocksTests = log2(t/32.0) + 1;
int linearToSquareTests = log2(t/1.0) + 1;
printf("%d %d\n",threadsToBlocksTests,linearToSquareTests);
*length = threadsToBlocksTests + linearToSquareTests;
// Allocate runs
int ** runs = (int**)malloc((*length)*sizeof(int*));
for(int i=0;i<*length;i++){
runs[i] = (int*)malloc(6*sizeof(int));
}
// Generate the block, grid, threads
// From linear to squared
int j = 0;
int i;
for(i=1;j<threadsToBlocksTests;i*=2){
runs[j][0]= t/i;
runs[j][1]= 1;
runs[j][2]= 1;
runs[j][3]= b*i;
runs[j][4]= 1;
runs[j][5]= 1;
j++;
}
// From threads to blocks
for(i=1;j<*length;i*=2){
runs[j][0]= t/i;
runs[j][1]= i;
runs[j][2]= 1;
runs[j][3]= b;
runs[j][4]= 1;
runs[j][5]= 1;
j++;
}
*inputRuns = runs;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
void generateRuns(int *** inputRuns,int * length,int N){
// GetGPUProperties
hipDeviceProp_t props;
hipGetDeviceProperties(&props,0);
// Get maximum threads, blocks and grids
printf("Generating test runs using N= %d:\n",N);
printf("GPU Info\n");
printf("Name: %s\n",props.name);
printf("Max Threads Per Block %d\n",props.maxThreadsPerBlock);
printf("Max Threads Size %d %d %d\n",
props.maxThreadsDim[0],
props.maxThreadsDim[1],
props.maxThreadsDim[2]);
printf("Max Grid Size %d %d %d\n",
props.maxGridSize[0],
props.maxGridSize[1],
props.maxGridSize[2]);
printf("Compute Capability %d\n",props.major);
/* Get total number of tests- from linear to squared,
from threads to blocks */
int t;
if(N*N<props.maxThreadsPerBlock)
t = N*N;
else
t= props.maxThreadsPerBlock;
int b = N*N/t+1;
int threadsToBlocksTests = log2(t/32.0) + 1;
int linearToSquareTests = log2(t/1.0) + 1;
printf("%d %d\n",threadsToBlocksTests,linearToSquareTests);
*length = threadsToBlocksTests + linearToSquareTests;
// Allocate runs
int ** runs = (int**)malloc((*length)*sizeof(int*));
for(int i=0;i<*length;i++){
runs[i] = (int*)malloc(6*sizeof(int));
}
// Generate the block, grid, threads
// From linear to squared
int j = 0;
int i;
for(i=1;j<threadsToBlocksTests;i*=2){
runs[j][0]= t/i;
runs[j][1]= 1;
runs[j][2]= 1;
runs[j][3]= b*i;
runs[j][4]= 1;
runs[j][5]= 1;
j++;
}
// From threads to blocks
for(i=1;j<*length;i*=2){
runs[j][0]= t/i;
runs[j][1]= i;
runs[j][2]= 1;
runs[j][3]= b;
runs[j][4]= 1;
runs[j][5]= 1;
j++;
}
*inputRuns = runs;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
void generateRuns(int *** inputRuns,int * length,int N){
// GetGPUProperties
hipDeviceProp_t props;
hipGetDeviceProperties(&props,0);
// Get maximum threads, blocks and grids
printf("Generating test runs using N= %d:\n",N);
printf("GPU Info\n");
printf("Name: %s\n",props.name);
printf("Max Threads Per Block %d\n",props.maxThreadsPerBlock);
printf("Max Threads Size %d %d %d\n",
props.maxThreadsDim[0],
props.maxThreadsDim[1],
props.maxThreadsDim[2]);
printf("Max Grid Size %d %d %d\n",
props.maxGridSize[0],
props.maxGridSize[1],
props.maxGridSize[2]);
printf("Compute Capability %d\n",props.major);
/* Get total number of tests- from linear to squared,
from threads to blocks */
int t;
if(N*N<props.maxThreadsPerBlock)
t = N*N;
else
t= props.maxThreadsPerBlock;
int b = N*N/t+1;
int threadsToBlocksTests = log2(t/32.0) + 1;
int linearToSquareTests = log2(t/1.0) + 1;
printf("%d %d\n",threadsToBlocksTests,linearToSquareTests);
*length = threadsToBlocksTests + linearToSquareTests;
// Allocate runs
int ** runs = (int**)malloc((*length)*sizeof(int*));
for(int i=0;i<*length;i++){
runs[i] = (int*)malloc(6*sizeof(int));
}
// Generate the block, grid, threads
// From linear to squared
int j = 0;
int i;
for(i=1;j<threadsToBlocksTests;i*=2){
runs[j][0]= t/i;
runs[j][1]= 1;
runs[j][2]= 1;
runs[j][3]= b*i;
runs[j][4]= 1;
runs[j][5]= 1;
j++;
}
// From threads to blocks
for(i=1;j<*length;i*=2){
runs[j][0]= t/i;
runs[j][1]= i;
runs[j][2]= 1;
runs[j][3]= b;
runs[j][4]= 1;
runs[j][5]= 1;
j++;
}
*inputRuns = runs;
} | .text
.file "generateRuns.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z12generateRunsPPPiS_i
.LCPI0_0:
.quad 0x3fa0000000000000 # double 0.03125
.LCPI0_1:
.quad 0x3ff0000000000000 # double 1
.text
.globl _Z12generateRunsPPPiS_i
.p2align 4, 0x90
.type _Z12generateRunsPPPiS_i,@function
_Z12generateRunsPPPiS_i: # @_Z12generateRunsPPPiS_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1496, %rsp # imm = 0x5D8
.cfi_def_cfa_offset 1552
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r15d
movq %rsi, %r14
movq %rdi, 16(%rsp) # 8-byte Spill
leaq 24(%rsp), %rbx
xorl %r13d, %r13d
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 344(%rsp), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl 348(%rsp), %esi
movl 352(%rsp), %edx
movl 356(%rsp), %ecx
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl 360(%rsp), %esi
movl 364(%rsp), %edx
movl 368(%rsp), %ecx
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 384(%rsp), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
imull %r15d, %r15d
movl 344(%rsp), %ebp
cmpl %ebp, %r15d
cmovll %r15d, %ebp
cvtsi2sd %ebp, %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
movl %r15d, %eax
xorl %edx, %edx
idivl %ebp
movl %eax, %r15d
movsd .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero
mulsd %xmm1, %xmm0
callq log2
addsd .LCPI0_1(%rip), %xmm0
cvttsd2si %xmm0, %r12d
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq log2
addsd .LCPI0_1(%rip), %xmm0
cvttsd2si %xmm0, %ebx
movl $.L.str.7, %edi
movl %r12d, %esi
movl %ebx, %edx
xorl %eax, %eax
callq printf
movl %r12d, 12(%rsp) # 4-byte Spill
addl %r12d, %ebx
movq %r14, (%rsp) # 8-byte Spill
movl %ebx, (%r14)
movslq %ebx, %r14
leaq (,%r14,8), %rdi
callq malloc
movq %rax, %r12
testl %r14d, %r14d
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %ebx, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $24, %edi
callq malloc
movq %rax, (%r12,%r14,8)
incq %r14
cmpq %r14, %rbx
jne .LBB0_2
.LBB0_3: # %.preheader68
incl %r15d
movabsq $4294967297, %rcx # imm = 0x100000001
movl 12(%rsp), %eax # 4-byte Reload
testl %eax, %eax
movq (%rsp), %r8 # 8-byte Reload
jle .LBB0_6
# %bb.4: # %.lr.ph72.preheader
movl %eax, %esi
movl $1, %edi
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_5: # %.lr.ph72
# =>This Inner Loop Header: Depth=1
movl %ebp, %eax
cltd
idivl %edi
movq (%r12,%r13,8), %rdx
movl %eax, (%rdx)
movq %rcx, 4(%rdx)
movl %edi, %eax
imull %r15d, %eax
movl %eax, 12(%rdx)
movq %rcx, 16(%rdx)
incq %r13
addl %edi, %edi
cmpq %r13, %rsi
jne .LBB0_5
.LBB0_6: # %.preheader
cmpl (%r8), %r13d
jge .LBB0_9
# %bb.7: # %.lr.ph75.preheader
movl %r13d, %esi
movl $1, %edi
.p2align 4, 0x90
.LBB0_8: # %.lr.ph75
# =>This Inner Loop Header: Depth=1
movl %ebp, %eax
cltd
idivl %edi
movq (%r12,%rsi,8), %rdx
movl %eax, (%rdx)
movl %edi, 4(%rdx)
movl $1, 8(%rdx)
movl %r15d, 12(%rdx)
movq %rcx, 16(%rdx)
incq %rsi
addl %edi, %edi
cmpl %esi, (%r8)
jg .LBB0_8
.LBB0_9: # %._crit_edge
movq 16(%rsp), %rax # 8-byte Reload
movq %r12, (%rax)
addq $1496, %rsp # imm = 0x5D8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z12generateRunsPPPiS_i, .Lfunc_end0-_Z12generateRunsPPPiS_i
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Generating test runs using N= %d:\n"
.size .L.str, 35
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Name: %s\n"
.size .L.str.2, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Max Threads Per Block %d\n"
.size .L.str.3, 27
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Max Threads Size %d %d %d\n"
.size .L.str.4, 28
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Max Grid Size %d %d %d\n"
.size .L.str.5, 24
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Compute Capability %d\n"
.size .L.str.6, 23
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%d %d\n"
.size .L.str.7, 7
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "GPU Info"
.size .Lstr, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000c666_00000000-6_generateRuns.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Generating test runs using N= %d:\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "GPU Info\n"
.LC2:
.string "Name: %s\n"
.LC3:
.string "Max Threads Per Block %d\n"
.LC4:
.string "Max Threads Size %d %d %d\n"
.LC5:
.string "Max Grid Size %d %d %d\n"
.LC6:
.string "Compute Capability %d\n"
.LC9:
.string "%d %d\n"
.text
.globl _Z12generateRunsPPPiS_i
.type _Z12generateRunsPPPiS_i, @function
_Z12generateRunsPPPiS_i:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %rdi, 8(%rsp)
movq %rsi, %r14
movl %edx, %r13d
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rbx
movl $0, %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movl %r13d, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 376(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %eax
imull %r13d, %eax
movl 336(%rsp), %ebx
cmpl %ebx, %eax
cmovle %eax, %ebx
cltd
idivl %ebx
leal 1(%rax), %r13d
pxor %xmm1, %xmm1
cvtsi2sdl %ebx, %xmm1
movq %xmm1, %rbp
movapd %xmm1, %xmm0
mulsd .LC7(%rip), %xmm0
call log2@PLT
addsd .LC8(%rip), %xmm0
cvttsd2sil %xmm0, %r12d
movq %rbp, %xmm0
call log2@PLT
addsd .LC8(%rip), %xmm0
cvttsd2sil %xmm0, %ebp
movl %ebp, %ecx
movl %r12d, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl %r12d, %ebp
movl %ebp, (%r14)
movslq %ebp, %rbp
leaq 0(,%rbp,8), %rdi
call malloc@PLT
movq %rax, %r15
cmpl $0, (%r14)
jle .L4
movl $0, %ebp
.L5:
movl $24, %edi
call malloc@PLT
movq %rax, (%r15,%rbp,8)
addq $1, %rbp
cmpl %ebp, (%r14)
jg .L5
testl %r12d, %r12d
jle .L12
.L10:
movq %r15, %rcx
movslq %r12d, %rax
leaq (%r15,%rax,8), %rdi
movl $1, %esi
.L7:
movq (%rcx), %r8
movl %ebx, %eax
cltd
idivl %esi
movl %eax, (%r8)
movq (%rcx), %rax
movl $1, 4(%rax)
movq (%rcx), %rax
movl $1, 8(%rax)
movq (%rcx), %rax
movl %r13d, %edx
imull %esi, %edx
movl %edx, 12(%rax)
movq (%rcx), %rax
movl $1, 16(%rax)
movq (%rcx), %rax
movl $1, 20(%rax)
addl %esi, %esi
addq $8, %rcx
cmpq %rdi, %rcx
jne .L7
.L6:
cmpl %r12d, (%r14)
jle .L8
movslq %r12d, %rax
leaq (%r15,%rax,8), %rcx
movl $1, %esi
.L9:
movq (%rcx), %rdi
movl %ebx, %eax
cltd
idivl %esi
movl %eax, (%rdi)
movq (%rcx), %rax
movl %esi, 4(%rax)
movq (%rcx), %rax
movl $1, 8(%rax)
movq (%rcx), %rax
movl %r13d, 12(%rax)
movq (%rcx), %rax
movl $1, 16(%rax)
movq (%rcx), %rax
movl $1, 20(%rax)
addl $1, %r12d
addl %esi, %esi
addq $8, %rcx
cmpl %r12d, (%r14)
jg .L9
.L8:
movq 8(%rsp), %rax
movq %r15, (%rax)
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movl $0, %r12d
jmp .L6
.L4:
testl %r12d, %r12d
jg .L10
jmp .L8
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z12generateRunsPPPiS_i, .-_Z12generateRunsPPPiS_i
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC7:
.long 0
.long 1067450368
.align 8
.LC8:
.long 0
.long 1072693248
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "generateRuns.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z12generateRunsPPPiS_i
.LCPI0_0:
.quad 0x3fa0000000000000 # double 0.03125
.LCPI0_1:
.quad 0x3ff0000000000000 # double 1
.text
.globl _Z12generateRunsPPPiS_i
.p2align 4, 0x90
.type _Z12generateRunsPPPiS_i,@function
_Z12generateRunsPPPiS_i: # @_Z12generateRunsPPPiS_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1496, %rsp # imm = 0x5D8
.cfi_def_cfa_offset 1552
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r15d
movq %rsi, %r14
movq %rdi, 16(%rsp) # 8-byte Spill
leaq 24(%rsp), %rbx
xorl %r13d, %r13d
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 344(%rsp), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl 348(%rsp), %esi
movl 352(%rsp), %edx
movl 356(%rsp), %ecx
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl 360(%rsp), %esi
movl 364(%rsp), %edx
movl 368(%rsp), %ecx
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 384(%rsp), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
imull %r15d, %r15d
movl 344(%rsp), %ebp
cmpl %ebp, %r15d
cmovll %r15d, %ebp
cvtsi2sd %ebp, %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
movl %r15d, %eax
xorl %edx, %edx
idivl %ebp
movl %eax, %r15d
movsd .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero
mulsd %xmm1, %xmm0
callq log2
addsd .LCPI0_1(%rip), %xmm0
cvttsd2si %xmm0, %r12d
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq log2
addsd .LCPI0_1(%rip), %xmm0
cvttsd2si %xmm0, %ebx
movl $.L.str.7, %edi
movl %r12d, %esi
movl %ebx, %edx
xorl %eax, %eax
callq printf
movl %r12d, 12(%rsp) # 4-byte Spill
addl %r12d, %ebx
movq %r14, (%rsp) # 8-byte Spill
movl %ebx, (%r14)
movslq %ebx, %r14
leaq (,%r14,8), %rdi
callq malloc
movq %rax, %r12
testl %r14d, %r14d
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %ebx, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $24, %edi
callq malloc
movq %rax, (%r12,%r14,8)
incq %r14
cmpq %r14, %rbx
jne .LBB0_2
.LBB0_3: # %.preheader68
incl %r15d
movabsq $4294967297, %rcx # imm = 0x100000001
movl 12(%rsp), %eax # 4-byte Reload
testl %eax, %eax
movq (%rsp), %r8 # 8-byte Reload
jle .LBB0_6
# %bb.4: # %.lr.ph72.preheader
movl %eax, %esi
movl $1, %edi
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_5: # %.lr.ph72
# =>This Inner Loop Header: Depth=1
movl %ebp, %eax
cltd
idivl %edi
movq (%r12,%r13,8), %rdx
movl %eax, (%rdx)
movq %rcx, 4(%rdx)
movl %edi, %eax
imull %r15d, %eax
movl %eax, 12(%rdx)
movq %rcx, 16(%rdx)
incq %r13
addl %edi, %edi
cmpq %r13, %rsi
jne .LBB0_5
.LBB0_6: # %.preheader
cmpl (%r8), %r13d
jge .LBB0_9
# %bb.7: # %.lr.ph75.preheader
movl %r13d, %esi
movl $1, %edi
.p2align 4, 0x90
.LBB0_8: # %.lr.ph75
# =>This Inner Loop Header: Depth=1
movl %ebp, %eax
cltd
idivl %edi
movq (%r12,%rsi,8), %rdx
movl %eax, (%rdx)
movl %edi, 4(%rdx)
movl $1, 8(%rdx)
movl %r15d, 12(%rdx)
movq %rcx, 16(%rdx)
incq %rsi
addl %edi, %edi
cmpl %esi, (%r8)
jg .LBB0_8
.LBB0_9: # %._crit_edge
movq 16(%rsp), %rax # 8-byte Reload
movq %r12, (%rax)
addq $1496, %rsp # imm = 0x5D8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z12generateRunsPPPiS_i, .Lfunc_end0-_Z12generateRunsPPPiS_i
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Generating test runs using N= %d:\n"
.size .L.str, 35
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Name: %s\n"
.size .L.str.2, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Max Threads Per Block %d\n"
.size .L.str.3, 27
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Max Threads Size %d %d %d\n"
.size .L.str.4, 28
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Max Grid Size %d %d %d\n"
.size .L.str.5, 24
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Compute Capability %d\n"
.size .L.str.6, 23
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%d %d\n"
.size .L.str.7, 7
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "GPU Info"
.size .Lstr, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C" __global__ __launch_bounds__(32) void sconv_bprop_C1_N64(
float *param_test,
float *param_I,
const float *param_E,
const float *param_F,
float param_alpha,
float param_N,
float param_K,
float param_D,
float param_H,
float param_W,
float param_WN,
float param_HWN,
float param_DHWN,
float param_C,
float param_CRST,
float param_RST,
float param_magic_RST,
float param_shift_RST,
float param_RS,
float param_magic_RS,
float param_shift_RS,
float param_S,
float param_magic_S,
float param_shift_S,
float param_pad_d,
float param_pad_h,
float param_pad_w,
float param_str_d,
float param_str_h,
float param_str_w,
float param_Q,
float param_PQ,
float param_QN,
float param_PQN,
float param_MPQN,
float param_magic_Q,
float param_shift_Q,
float param_magic_PQ,
float param_shift_PQ,
float param_CRST8,
float param_MPQN8) {
__shared__ float share[64 * 8 * 2 + 32 * 8 * 2 + 8];
int tid = threadIdx.x;
share[tid] = 1;
} | code for sm_80
Function : sconv_bprop_C1_N64
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C" __global__ __launch_bounds__(32) void sconv_bprop_C1_N64(
float *param_test,
float *param_I,
const float *param_E,
const float *param_F,
float param_alpha,
float param_N,
float param_K,
float param_D,
float param_H,
float param_W,
float param_WN,
float param_HWN,
float param_DHWN,
float param_C,
float param_CRST,
float param_RST,
float param_magic_RST,
float param_shift_RST,
float param_RS,
float param_magic_RS,
float param_shift_RS,
float param_S,
float param_magic_S,
float param_shift_S,
float param_pad_d,
float param_pad_h,
float param_pad_w,
float param_str_d,
float param_str_h,
float param_str_w,
float param_Q,
float param_PQ,
float param_QN,
float param_PQN,
float param_MPQN,
float param_magic_Q,
float param_shift_Q,
float param_magic_PQ,
float param_shift_PQ,
float param_CRST8,
float param_MPQN8) {
__shared__ float share[64 * 8 * 2 + 32 * 8 * 2 + 8];
int tid = threadIdx.x;
share[tid] = 1;
} | .file "tmpxft_0018c1c1_00000000-6_sconv_bprop_C1_N64.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z83__device_stub__Z18sconv_bprop_C1_N64PfS_PKfS1_fffffffffffffffffffffffffffffffffffffPfS_PKfS1_fffffffffffffffffffffffffffffffffffff
.type _Z83__device_stub__Z18sconv_bprop_C1_N64PfS_PKfS1_fffffffffffffffffffffffffffffffffffffPfS_PKfS1_fffffffffffffffffffffffffffffffffffff, @function
_Z83__device_stub__Z18sconv_bprop_C1_N64PfS_PKfS1_fffffffffffffffffffffffffffffffffffffPfS_PKfS1_fffffffffffffffffffffffffffffffffffff:
.LFB2051:
.cfi_startproc
endbr64
subq $472, %rsp
.cfi_def_cfa_offset 480
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 16(%rsp)
movss %xmm4, 12(%rsp)
movss %xmm5, 8(%rsp)
movss %xmm6, 4(%rsp)
movss %xmm7, (%rsp)
movq %fs:40, %rax
movq %rax, 456(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 28(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 20(%rsp), %rax
movq %rax, 176(%rsp)
leaq 16(%rsp), %rax
movq %rax, 184(%rsp)
leaq 12(%rsp), %rax
movq %rax, 192(%rsp)
leaq 8(%rsp), %rax
movq %rax, 200(%rsp)
leaq 4(%rsp), %rax
movq %rax, 208(%rsp)
movq %rsp, %rax
movq %rax, 216(%rsp)
leaq 480(%rsp), %rax
movq %rax, 224(%rsp)
leaq 488(%rsp), %rax
movq %rax, 232(%rsp)
leaq 496(%rsp), %rax
movq %rax, 240(%rsp)
leaq 504(%rsp), %rax
movq %rax, 248(%rsp)
leaq 512(%rsp), %rax
movq %rax, 256(%rsp)
leaq 520(%rsp), %rax
movq %rax, 264(%rsp)
leaq 528(%rsp), %rax
movq %rax, 272(%rsp)
leaq 536(%rsp), %rax
movq %rax, 280(%rsp)
leaq 544(%rsp), %rax
movq %rax, 288(%rsp)
leaq 552(%rsp), %rax
movq %rax, 296(%rsp)
leaq 560(%rsp), %rax
movq %rax, 304(%rsp)
leaq 568(%rsp), %rax
movq %rax, 312(%rsp)
leaq 576(%rsp), %rax
movq %rax, 320(%rsp)
leaq 584(%rsp), %rax
movq %rax, 328(%rsp)
leaq 592(%rsp), %rax
movq %rax, 336(%rsp)
leaq 600(%rsp), %rax
movq %rax, 344(%rsp)
leaq 608(%rsp), %rax
movq %rax, 352(%rsp)
leaq 616(%rsp), %rax
movq %rax, 360(%rsp)
leaq 624(%rsp), %rax
movq %rax, 368(%rsp)
leaq 632(%rsp), %rax
movq %rax, 376(%rsp)
leaq 640(%rsp), %rax
movq %rax, 384(%rsp)
leaq 648(%rsp), %rax
movq %rax, 392(%rsp)
leaq 656(%rsp), %rax
movq %rax, 400(%rsp)
leaq 664(%rsp), %rax
movq %rax, 408(%rsp)
leaq 672(%rsp), %rax
movq %rax, 416(%rsp)
leaq 680(%rsp), %rax
movq %rax, 424(%rsp)
leaq 688(%rsp), %rax
movq %rax, 432(%rsp)
leaq 696(%rsp), %rax
movq %rax, 440(%rsp)
leaq 704(%rsp), %rax
movq %rax, 448(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 456(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $472, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 488
pushq 72(%rsp)
.cfi_def_cfa_offset 496
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq sconv_bprop_C1_N64(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 480
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z83__device_stub__Z18sconv_bprop_C1_N64PfS_PKfS1_fffffffffffffffffffffffffffffffffffffPfS_PKfS1_fffffffffffffffffffffffffffffffffffff, .-_Z83__device_stub__Z18sconv_bprop_C1_N64PfS_PKfS1_fffffffffffffffffffffffffffffffffffffPfS_PKfS1_fffffffffffffffffffffffffffffffffffff
.globl sconv_bprop_C1_N64
.type sconv_bprop_C1_N64, @function
sconv_bprop_C1_N64:
.LFB2052:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movss 480(%rsp), %xmm8
movss %xmm8, 224(%rsp)
movss 472(%rsp), %xmm8
movss %xmm8, 216(%rsp)
movss 464(%rsp), %xmm8
movss %xmm8, 208(%rsp)
movss 456(%rsp), %xmm8
movss %xmm8, 200(%rsp)
movss 448(%rsp), %xmm8
movss %xmm8, 192(%rsp)
movss 440(%rsp), %xmm8
movss %xmm8, 184(%rsp)
movss 432(%rsp), %xmm8
movss %xmm8, 176(%rsp)
movss 424(%rsp), %xmm8
movss %xmm8, 168(%rsp)
movss 416(%rsp), %xmm8
movss %xmm8, 160(%rsp)
movss 408(%rsp), %xmm8
movss %xmm8, 152(%rsp)
movss 400(%rsp), %xmm8
movss %xmm8, 144(%rsp)
movss 392(%rsp), %xmm8
movss %xmm8, 136(%rsp)
movss 384(%rsp), %xmm8
movss %xmm8, 128(%rsp)
movss 376(%rsp), %xmm8
movss %xmm8, 120(%rsp)
movss 368(%rsp), %xmm8
movss %xmm8, 112(%rsp)
movss 360(%rsp), %xmm8
movss %xmm8, 104(%rsp)
movss 352(%rsp), %xmm8
movss %xmm8, 96(%rsp)
movss 344(%rsp), %xmm8
movss %xmm8, 88(%rsp)
movss 336(%rsp), %xmm8
movss %xmm8, 80(%rsp)
movss 328(%rsp), %xmm8
movss %xmm8, 72(%rsp)
movss 320(%rsp), %xmm8
movss %xmm8, 64(%rsp)
movss 312(%rsp), %xmm8
movss %xmm8, 56(%rsp)
movss 304(%rsp), %xmm8
movss %xmm8, 48(%rsp)
movss 296(%rsp), %xmm8
movss %xmm8, 40(%rsp)
movss 288(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 280(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 272(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 264(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 256(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z83__device_stub__Z18sconv_bprop_C1_N64PfS_PKfS1_fffffffffffffffffffffffffffffffffffffPfS_PKfS1_fffffffffffffffffffffffffffffffffffff
addq $248, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size sconv_bprop_C1_N64, .-sconv_bprop_C1_N64
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "sconv_bprop_C1_N64"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq sconv_bprop_C1_N64(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C" __global__ __launch_bounds__(32) void sconv_bprop_C1_N64(
float *param_test,
float *param_I,
const float *param_E,
const float *param_F,
float param_alpha,
float param_N,
float param_K,
float param_D,
float param_H,
float param_W,
float param_WN,
float param_HWN,
float param_DHWN,
float param_C,
float param_CRST,
float param_RST,
float param_magic_RST,
float param_shift_RST,
float param_RS,
float param_magic_RS,
float param_shift_RS,
float param_S,
float param_magic_S,
float param_shift_S,
float param_pad_d,
float param_pad_h,
float param_pad_w,
float param_str_d,
float param_str_h,
float param_str_w,
float param_Q,
float param_PQ,
float param_QN,
float param_PQN,
float param_MPQN,
float param_magic_Q,
float param_shift_Q,
float param_magic_PQ,
float param_shift_PQ,
float param_CRST8,
float param_MPQN8) {
__shared__ float share[64 * 8 * 2 + 32 * 8 * 2 + 8];
int tid = threadIdx.x;
share[tid] = 1;
} | #include <hip/hip_runtime.h>
extern "C" __global__ __launch_bounds__(32) void sconv_bprop_C1_N64(
float *param_test,
float *param_I,
const float *param_E,
const float *param_F,
float param_alpha,
float param_N,
float param_K,
float param_D,
float param_H,
float param_W,
float param_WN,
float param_HWN,
float param_DHWN,
float param_C,
float param_CRST,
float param_RST,
float param_magic_RST,
float param_shift_RST,
float param_RS,
float param_magic_RS,
float param_shift_RS,
float param_S,
float param_magic_S,
float param_shift_S,
float param_pad_d,
float param_pad_h,
float param_pad_w,
float param_str_d,
float param_str_h,
float param_str_w,
float param_Q,
float param_PQ,
float param_QN,
float param_PQN,
float param_MPQN,
float param_magic_Q,
float param_shift_Q,
float param_magic_PQ,
float param_shift_PQ,
float param_CRST8,
float param_MPQN8) {
__shared__ float share[64 * 8 * 2 + 32 * 8 * 2 + 8];
int tid = threadIdx.x;
share[tid] = 1;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C" __global__ __launch_bounds__(32) void sconv_bprop_C1_N64(
float *param_test,
float *param_I,
const float *param_E,
const float *param_F,
float param_alpha,
float param_N,
float param_K,
float param_D,
float param_H,
float param_W,
float param_WN,
float param_HWN,
float param_DHWN,
float param_C,
float param_CRST,
float param_RST,
float param_magic_RST,
float param_shift_RST,
float param_RS,
float param_magic_RS,
float param_shift_RS,
float param_S,
float param_magic_S,
float param_shift_S,
float param_pad_d,
float param_pad_h,
float param_pad_w,
float param_str_d,
float param_str_h,
float param_str_w,
float param_Q,
float param_PQ,
float param_QN,
float param_PQN,
float param_MPQN,
float param_magic_Q,
float param_shift_Q,
float param_magic_PQ,
float param_shift_PQ,
float param_CRST8,
float param_MPQN8) {
__shared__ float share[64 * 8 * 2 + 32 * 8 * 2 + 8];
int tid = threadIdx.x;
share[tid] = 1;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected sconv_bprop_C1_N64
.globl sconv_bprop_C1_N64
.p2align 8
.type sconv_bprop_C1_N64,@function
sconv_bprop_C1_N64:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel sconv_bprop_C1_N64
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 180
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size sconv_bprop_C1_N64, .Lfunc_end0-sconv_bprop_C1_N64
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 60
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: by_value
- .offset: 68
.size: 4
.value_kind: by_value
- .offset: 72
.size: 4
.value_kind: by_value
- .offset: 76
.size: 4
.value_kind: by_value
- .offset: 80
.size: 4
.value_kind: by_value
- .offset: 84
.size: 4
.value_kind: by_value
- .offset: 88
.size: 4
.value_kind: by_value
- .offset: 92
.size: 4
.value_kind: by_value
- .offset: 96
.size: 4
.value_kind: by_value
- .offset: 100
.size: 4
.value_kind: by_value
- .offset: 104
.size: 4
.value_kind: by_value
- .offset: 108
.size: 4
.value_kind: by_value
- .offset: 112
.size: 4
.value_kind: by_value
- .offset: 116
.size: 4
.value_kind: by_value
- .offset: 120
.size: 4
.value_kind: by_value
- .offset: 124
.size: 4
.value_kind: by_value
- .offset: 128
.size: 4
.value_kind: by_value
- .offset: 132
.size: 4
.value_kind: by_value
- .offset: 136
.size: 4
.value_kind: by_value
- .offset: 140
.size: 4
.value_kind: by_value
- .offset: 144
.size: 4
.value_kind: by_value
- .offset: 148
.size: 4
.value_kind: by_value
- .offset: 152
.size: 4
.value_kind: by_value
- .offset: 156
.size: 4
.value_kind: by_value
- .offset: 160
.size: 4
.value_kind: by_value
- .offset: 164
.size: 4
.value_kind: by_value
- .offset: 168
.size: 4
.value_kind: by_value
- .offset: 172
.size: 4
.value_kind: by_value
- .offset: 176
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 180
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 32
.name: sconv_bprop_C1_N64
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: sconv_bprop_C1_N64.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C" __global__ __launch_bounds__(32) void sconv_bprop_C1_N64(
float *param_test,
float *param_I,
const float *param_E,
const float *param_F,
float param_alpha,
float param_N,
float param_K,
float param_D,
float param_H,
float param_W,
float param_WN,
float param_HWN,
float param_DHWN,
float param_C,
float param_CRST,
float param_RST,
float param_magic_RST,
float param_shift_RST,
float param_RS,
float param_magic_RS,
float param_shift_RS,
float param_S,
float param_magic_S,
float param_shift_S,
float param_pad_d,
float param_pad_h,
float param_pad_w,
float param_str_d,
float param_str_h,
float param_str_w,
float param_Q,
float param_PQ,
float param_QN,
float param_PQN,
float param_MPQN,
float param_magic_Q,
float param_shift_Q,
float param_magic_PQ,
float param_shift_PQ,
float param_CRST8,
float param_MPQN8) {
__shared__ float share[64 * 8 * 2 + 32 * 8 * 2 + 8];
int tid = threadIdx.x;
share[tid] = 1;
} | .text
.file "sconv_bprop_C1_N64.hip"
.globl __device_stub__sconv_bprop_C1_N64 # -- Begin function __device_stub__sconv_bprop_C1_N64
.p2align 4, 0x90
.type __device_stub__sconv_bprop_C1_N64,@function
__device_stub__sconv_bprop_C1_N64: # @__device_stub__sconv_bprop_C1_N64
.cfi_startproc
# %bb.0:
subq $440, %rsp # imm = 0x1B8
.cfi_def_cfa_offset 448
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 16(%rsp)
movss %xmm4, 12(%rsp)
movss %xmm5, 8(%rsp)
movss %xmm6, 4(%rsp)
movss %xmm7, (%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
leaq 4(%rsp), %rax
movq %rax, 192(%rsp)
movq %rsp, %rax
movq %rax, 200(%rsp)
leaq 448(%rsp), %rax
movq %rax, 208(%rsp)
leaq 456(%rsp), %rax
movq %rax, 216(%rsp)
leaq 464(%rsp), %rax
movq %rax, 224(%rsp)
leaq 472(%rsp), %rax
movq %rax, 232(%rsp)
leaq 480(%rsp), %rax
movq %rax, 240(%rsp)
leaq 488(%rsp), %rax
movq %rax, 248(%rsp)
leaq 496(%rsp), %rax
movq %rax, 256(%rsp)
leaq 504(%rsp), %rax
movq %rax, 264(%rsp)
leaq 512(%rsp), %rax
movq %rax, 272(%rsp)
leaq 520(%rsp), %rax
movq %rax, 280(%rsp)
leaq 528(%rsp), %rax
movq %rax, 288(%rsp)
leaq 536(%rsp), %rax
movq %rax, 296(%rsp)
leaq 544(%rsp), %rax
movq %rax, 304(%rsp)
leaq 552(%rsp), %rax
movq %rax, 312(%rsp)
leaq 560(%rsp), %rax
movq %rax, 320(%rsp)
leaq 568(%rsp), %rax
movq %rax, 328(%rsp)
leaq 576(%rsp), %rax
movq %rax, 336(%rsp)
leaq 584(%rsp), %rax
movq %rax, 344(%rsp)
leaq 592(%rsp), %rax
movq %rax, 352(%rsp)
leaq 600(%rsp), %rax
movq %rax, 360(%rsp)
leaq 608(%rsp), %rax
movq %rax, 368(%rsp)
leaq 616(%rsp), %rax
movq %rax, 376(%rsp)
leaq 624(%rsp), %rax
movq %rax, 384(%rsp)
leaq 632(%rsp), %rax
movq %rax, 392(%rsp)
leaq 640(%rsp), %rax
movq %rax, 400(%rsp)
leaq 648(%rsp), %rax
movq %rax, 408(%rsp)
leaq 656(%rsp), %rax
movq %rax, 416(%rsp)
leaq 664(%rsp), %rax
movq %rax, 424(%rsp)
leaq 672(%rsp), %rax
movq %rax, 432(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $sconv_bprop_C1_N64, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $456, %rsp # imm = 0x1C8
.cfi_adjust_cfa_offset -456
retq
.Lfunc_end0:
.size __device_stub__sconv_bprop_C1_N64, .Lfunc_end0-__device_stub__sconv_bprop_C1_N64
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $sconv_bprop_C1_N64, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type sconv_bprop_C1_N64,@object # @sconv_bprop_C1_N64
.section .rodata,"a",@progbits
.globl sconv_bprop_C1_N64
.p2align 3, 0x0
sconv_bprop_C1_N64:
.quad __device_stub__sconv_bprop_C1_N64
.size sconv_bprop_C1_N64, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "sconv_bprop_C1_N64"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__sconv_bprop_C1_N64
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym sconv_bprop_C1_N64
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : sconv_bprop_C1_N64
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected sconv_bprop_C1_N64
.globl sconv_bprop_C1_N64
.p2align 8
.type sconv_bprop_C1_N64,@function
sconv_bprop_C1_N64:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel sconv_bprop_C1_N64
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 180
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size sconv_bprop_C1_N64, .Lfunc_end0-sconv_bprop_C1_N64
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 60
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: by_value
- .offset: 68
.size: 4
.value_kind: by_value
- .offset: 72
.size: 4
.value_kind: by_value
- .offset: 76
.size: 4
.value_kind: by_value
- .offset: 80
.size: 4
.value_kind: by_value
- .offset: 84
.size: 4
.value_kind: by_value
- .offset: 88
.size: 4
.value_kind: by_value
- .offset: 92
.size: 4
.value_kind: by_value
- .offset: 96
.size: 4
.value_kind: by_value
- .offset: 100
.size: 4
.value_kind: by_value
- .offset: 104
.size: 4
.value_kind: by_value
- .offset: 108
.size: 4
.value_kind: by_value
- .offset: 112
.size: 4
.value_kind: by_value
- .offset: 116
.size: 4
.value_kind: by_value
- .offset: 120
.size: 4
.value_kind: by_value
- .offset: 124
.size: 4
.value_kind: by_value
- .offset: 128
.size: 4
.value_kind: by_value
- .offset: 132
.size: 4
.value_kind: by_value
- .offset: 136
.size: 4
.value_kind: by_value
- .offset: 140
.size: 4
.value_kind: by_value
- .offset: 144
.size: 4
.value_kind: by_value
- .offset: 148
.size: 4
.value_kind: by_value
- .offset: 152
.size: 4
.value_kind: by_value
- .offset: 156
.size: 4
.value_kind: by_value
- .offset: 160
.size: 4
.value_kind: by_value
- .offset: 164
.size: 4
.value_kind: by_value
- .offset: 168
.size: 4
.value_kind: by_value
- .offset: 172
.size: 4
.value_kind: by_value
- .offset: 176
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 180
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 32
.name: sconv_bprop_C1_N64
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: sconv_bprop_C1_N64.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018c1c1_00000000-6_sconv_bprop_C1_N64.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z83__device_stub__Z18sconv_bprop_C1_N64PfS_PKfS1_fffffffffffffffffffffffffffffffffffffPfS_PKfS1_fffffffffffffffffffffffffffffffffffff
.type _Z83__device_stub__Z18sconv_bprop_C1_N64PfS_PKfS1_fffffffffffffffffffffffffffffffffffffPfS_PKfS1_fffffffffffffffffffffffffffffffffffff, @function
_Z83__device_stub__Z18sconv_bprop_C1_N64PfS_PKfS1_fffffffffffffffffffffffffffffffffffffPfS_PKfS1_fffffffffffffffffffffffffffffffffffff:
.LFB2051:
.cfi_startproc
endbr64
subq $472, %rsp
.cfi_def_cfa_offset 480
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 16(%rsp)
movss %xmm4, 12(%rsp)
movss %xmm5, 8(%rsp)
movss %xmm6, 4(%rsp)
movss %xmm7, (%rsp)
movq %fs:40, %rax
movq %rax, 456(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 28(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 20(%rsp), %rax
movq %rax, 176(%rsp)
leaq 16(%rsp), %rax
movq %rax, 184(%rsp)
leaq 12(%rsp), %rax
movq %rax, 192(%rsp)
leaq 8(%rsp), %rax
movq %rax, 200(%rsp)
leaq 4(%rsp), %rax
movq %rax, 208(%rsp)
movq %rsp, %rax
movq %rax, 216(%rsp)
leaq 480(%rsp), %rax
movq %rax, 224(%rsp)
leaq 488(%rsp), %rax
movq %rax, 232(%rsp)
leaq 496(%rsp), %rax
movq %rax, 240(%rsp)
leaq 504(%rsp), %rax
movq %rax, 248(%rsp)
leaq 512(%rsp), %rax
movq %rax, 256(%rsp)
leaq 520(%rsp), %rax
movq %rax, 264(%rsp)
leaq 528(%rsp), %rax
movq %rax, 272(%rsp)
leaq 536(%rsp), %rax
movq %rax, 280(%rsp)
leaq 544(%rsp), %rax
movq %rax, 288(%rsp)
leaq 552(%rsp), %rax
movq %rax, 296(%rsp)
leaq 560(%rsp), %rax
movq %rax, 304(%rsp)
leaq 568(%rsp), %rax
movq %rax, 312(%rsp)
leaq 576(%rsp), %rax
movq %rax, 320(%rsp)
leaq 584(%rsp), %rax
movq %rax, 328(%rsp)
leaq 592(%rsp), %rax
movq %rax, 336(%rsp)
leaq 600(%rsp), %rax
movq %rax, 344(%rsp)
leaq 608(%rsp), %rax
movq %rax, 352(%rsp)
leaq 616(%rsp), %rax
movq %rax, 360(%rsp)
leaq 624(%rsp), %rax
movq %rax, 368(%rsp)
leaq 632(%rsp), %rax
movq %rax, 376(%rsp)
leaq 640(%rsp), %rax
movq %rax, 384(%rsp)
leaq 648(%rsp), %rax
movq %rax, 392(%rsp)
leaq 656(%rsp), %rax
movq %rax, 400(%rsp)
leaq 664(%rsp), %rax
movq %rax, 408(%rsp)
leaq 672(%rsp), %rax
movq %rax, 416(%rsp)
leaq 680(%rsp), %rax
movq %rax, 424(%rsp)
leaq 688(%rsp), %rax
movq %rax, 432(%rsp)
leaq 696(%rsp), %rax
movq %rax, 440(%rsp)
leaq 704(%rsp), %rax
movq %rax, 448(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 456(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $472, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 488
pushq 72(%rsp)
.cfi_def_cfa_offset 496
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq sconv_bprop_C1_N64(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 480
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z83__device_stub__Z18sconv_bprop_C1_N64PfS_PKfS1_fffffffffffffffffffffffffffffffffffffPfS_PKfS1_fffffffffffffffffffffffffffffffffffff, .-_Z83__device_stub__Z18sconv_bprop_C1_N64PfS_PKfS1_fffffffffffffffffffffffffffffffffffffPfS_PKfS1_fffffffffffffffffffffffffffffffffffff
.globl sconv_bprop_C1_N64
.type sconv_bprop_C1_N64, @function
sconv_bprop_C1_N64:
.LFB2052:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movss 480(%rsp), %xmm8
movss %xmm8, 224(%rsp)
movss 472(%rsp), %xmm8
movss %xmm8, 216(%rsp)
movss 464(%rsp), %xmm8
movss %xmm8, 208(%rsp)
movss 456(%rsp), %xmm8
movss %xmm8, 200(%rsp)
movss 448(%rsp), %xmm8
movss %xmm8, 192(%rsp)
movss 440(%rsp), %xmm8
movss %xmm8, 184(%rsp)
movss 432(%rsp), %xmm8
movss %xmm8, 176(%rsp)
movss 424(%rsp), %xmm8
movss %xmm8, 168(%rsp)
movss 416(%rsp), %xmm8
movss %xmm8, 160(%rsp)
movss 408(%rsp), %xmm8
movss %xmm8, 152(%rsp)
movss 400(%rsp), %xmm8
movss %xmm8, 144(%rsp)
movss 392(%rsp), %xmm8
movss %xmm8, 136(%rsp)
movss 384(%rsp), %xmm8
movss %xmm8, 128(%rsp)
movss 376(%rsp), %xmm8
movss %xmm8, 120(%rsp)
movss 368(%rsp), %xmm8
movss %xmm8, 112(%rsp)
movss 360(%rsp), %xmm8
movss %xmm8, 104(%rsp)
movss 352(%rsp), %xmm8
movss %xmm8, 96(%rsp)
movss 344(%rsp), %xmm8
movss %xmm8, 88(%rsp)
movss 336(%rsp), %xmm8
movss %xmm8, 80(%rsp)
movss 328(%rsp), %xmm8
movss %xmm8, 72(%rsp)
movss 320(%rsp), %xmm8
movss %xmm8, 64(%rsp)
movss 312(%rsp), %xmm8
movss %xmm8, 56(%rsp)
movss 304(%rsp), %xmm8
movss %xmm8, 48(%rsp)
movss 296(%rsp), %xmm8
movss %xmm8, 40(%rsp)
movss 288(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 280(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 272(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 264(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 256(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z83__device_stub__Z18sconv_bprop_C1_N64PfS_PKfS1_fffffffffffffffffffffffffffffffffffffPfS_PKfS1_fffffffffffffffffffffffffffffffffffff
addq $248, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size sconv_bprop_C1_N64, .-sconv_bprop_C1_N64
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "sconv_bprop_C1_N64"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq sconv_bprop_C1_N64(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sconv_bprop_C1_N64.hip"
.globl __device_stub__sconv_bprop_C1_N64 # -- Begin function __device_stub__sconv_bprop_C1_N64
.p2align 4, 0x90
.type __device_stub__sconv_bprop_C1_N64,@function
__device_stub__sconv_bprop_C1_N64: # @__device_stub__sconv_bprop_C1_N64
.cfi_startproc
# %bb.0:
subq $440, %rsp # imm = 0x1B8
.cfi_def_cfa_offset 448
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 16(%rsp)
movss %xmm4, 12(%rsp)
movss %xmm5, 8(%rsp)
movss %xmm6, 4(%rsp)
movss %xmm7, (%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
leaq 4(%rsp), %rax
movq %rax, 192(%rsp)
movq %rsp, %rax
movq %rax, 200(%rsp)
leaq 448(%rsp), %rax
movq %rax, 208(%rsp)
leaq 456(%rsp), %rax
movq %rax, 216(%rsp)
leaq 464(%rsp), %rax
movq %rax, 224(%rsp)
leaq 472(%rsp), %rax
movq %rax, 232(%rsp)
leaq 480(%rsp), %rax
movq %rax, 240(%rsp)
leaq 488(%rsp), %rax
movq %rax, 248(%rsp)
leaq 496(%rsp), %rax
movq %rax, 256(%rsp)
leaq 504(%rsp), %rax
movq %rax, 264(%rsp)
leaq 512(%rsp), %rax
movq %rax, 272(%rsp)
leaq 520(%rsp), %rax
movq %rax, 280(%rsp)
leaq 528(%rsp), %rax
movq %rax, 288(%rsp)
leaq 536(%rsp), %rax
movq %rax, 296(%rsp)
leaq 544(%rsp), %rax
movq %rax, 304(%rsp)
leaq 552(%rsp), %rax
movq %rax, 312(%rsp)
leaq 560(%rsp), %rax
movq %rax, 320(%rsp)
leaq 568(%rsp), %rax
movq %rax, 328(%rsp)
leaq 576(%rsp), %rax
movq %rax, 336(%rsp)
leaq 584(%rsp), %rax
movq %rax, 344(%rsp)
leaq 592(%rsp), %rax
movq %rax, 352(%rsp)
leaq 600(%rsp), %rax
movq %rax, 360(%rsp)
leaq 608(%rsp), %rax
movq %rax, 368(%rsp)
leaq 616(%rsp), %rax
movq %rax, 376(%rsp)
leaq 624(%rsp), %rax
movq %rax, 384(%rsp)
leaq 632(%rsp), %rax
movq %rax, 392(%rsp)
leaq 640(%rsp), %rax
movq %rax, 400(%rsp)
leaq 648(%rsp), %rax
movq %rax, 408(%rsp)
leaq 656(%rsp), %rax
movq %rax, 416(%rsp)
leaq 664(%rsp), %rax
movq %rax, 424(%rsp)
leaq 672(%rsp), %rax
movq %rax, 432(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $sconv_bprop_C1_N64, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $456, %rsp # imm = 0x1C8
.cfi_adjust_cfa_offset -456
retq
.Lfunc_end0:
.size __device_stub__sconv_bprop_C1_N64, .Lfunc_end0-__device_stub__sconv_bprop_C1_N64
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $sconv_bprop_C1_N64, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type sconv_bprop_C1_N64,@object # @sconv_bprop_C1_N64
.section .rodata,"a",@progbits
.globl sconv_bprop_C1_N64
.p2align 3, 0x0
sconv_bprop_C1_N64:
.quad __device_stub__sconv_bprop_C1_N64
.size sconv_bprop_C1_N64, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "sconv_bprop_C1_N64"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__sconv_bprop_C1_N64
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym sconv_bprop_C1_N64
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
static const int NTHREADS = 32;
__global__ void cunn_ClassNLLCriterion_updateGradInput_kernel1( float* gradInput, float* weights, float* target, float* total_weight, int size_average, int n_classes)
{
if (*total_weight <= 0) {
return;
}
float norm = size_average ? (1.0f / *total_weight) : 1.0f;
int t = (int)*target - 1;
if (t >= 0 && t < n_classes) {
gradInput[t] = -(weights ? weights[t] : 1.0f) * norm;
}
} | code for sm_80
Function : _Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff037624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*0050*/ FSETP.GTU.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x004fda0003f0c000 */
/*0060*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0070*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fe20003f05270 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff007424 */
/* 0x000fd800078e00ff */
/*0090*/ @!P0 BRA 0x160 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R0, R2, 0x1800000, RZ ; /* 0x0180000002007810 */
/* 0x000fc80007ffe0ff */
/*00b0*/ LOP3.LUT R0, R0, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000000007812 */
/* 0x000fc800078ec0ff */
/*00c0*/ ISETP.GT.U32.AND P0, PT, R0, 0x1ffffff, PT ; /* 0x01ffffff0000780c */
/* 0x000fda0003f04070 */
/*00d0*/ @P0 BRA 0x120 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*00e0*/ MOV R0, 0x100 ; /* 0x0000010000007802 */
/* 0x000fe40000000f00 */
/*00f0*/ CALL.REL.NOINC 0x2b0 ; /* 0x000001b000007944 */
/* 0x000fea0003c00000 */
/*0100*/ IMAD.MOV.U32 R0, RZ, RZ, R4 ; /* 0x000000ffff007224 */
/* 0x000fe200078e0004 */
/*0110*/ BRA 0x160 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0120*/ MUFU.RCP R3, R2 ; /* 0x0000000200037308 */
/* 0x000e240000001000 */
/*0130*/ FFMA R0, R2, R3, -1 ; /* 0xbf80000002007423 */
/* 0x001fc80000000003 */
/*0140*/ FADD.FTZ R0, -R0, -RZ ; /* 0x800000ff00007221 */
/* 0x000fc80000010100 */
/*0150*/ FFMA R0, R3, R0, R3 ; /* 0x0000000003007223 */
/* 0x000fe40000000003 */
/*0160*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe400078e00ff */
/*0170*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fca00078e00ff */
/*0180*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*0190*/ F2I.TRUNC.NTZ R4, R2 ; /* 0x0000000200047305 */
/* 0x004e24000020f100 */
/*01a0*/ ISETP.GT.AND P0, PT, R4, c[0x0][0x184], PT ; /* 0x0000610004007a0c */
/* 0x001fc80003f04270 */
/*01b0*/ ISETP.LT.OR P0, PT, R4, 0x1, P0 ; /* 0x000000010400780c */
/* 0x000fda0000701670 */
/*01c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe40003f05070 */
/*01e0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x16c], PT, P0 ; /* 0x00005b00ff007a0c */
/* 0x000fda0003f05300 */
/*0200*/ @!P0 BRA 0x250 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0210*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0220*/ IMAD.WIDE R2, R4, R3, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0203 */
/*0230*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000162000c1e1900 */
/*0240*/ BRA 0x260 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0250*/ IMAD.MOV.U32 R3, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff037424 */
/* 0x000fe400078e00ff */
/*0260*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe400078e00ff */
/*0270*/ FFMA R5, -R3, R0, -RZ ; /* 0x0000000003057223 */
/* 0x020fe400000009ff */
/*0280*/ IMAD.WIDE R2, R4, R7, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x001fca00078e0207 */
/*0290*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*02a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02b0*/ IMAD.SHL.U32 R3, R2, 0x2, RZ ; /* 0x0000000202037824 */
/* 0x000fca00078e00ff */
/*02c0*/ SHF.R.U32.HI R3, RZ, 0x18, R3 ; /* 0x00000018ff037819 */
/* 0x000fc80000011603 */
/*02d0*/ ISETP.NE.U32.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05070 */
/*02e0*/ @P0 BRA 0x3a0 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*02f0*/ IMAD.SHL.U32 R3, R2, 0x2, RZ ; /* 0x0000000202037824 */
/* 0x000fca00078e00ff */
/*0300*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0310*/ @!P0 MUFU.RCP R3, R2 ; /* 0x0000000200038308 */
/* 0x0000620000001000 */
/*0320*/ @!P0 BRA 0x5c0 ; /* 0x0000029000008947 */
/* 0x000fea0003800000 */
/*0330*/ FFMA R2, R2, 1.84467440737095516160e+19, RZ ; /* 0x5f80000002027823 */
/* 0x001fc800000000ff */
/*0340*/ MUFU.RCP R3, R2 ; /* 0x0000000200037308 */
/* 0x002e240000001000 */
/*0350*/ FFMA R4, R2, R3, -1 ; /* 0xbf80000002047423 */
/* 0x001fc80000000003 */
/*0360*/ FADD.FTZ R4, -R4, -RZ ; /* 0x800000ff04047221 */
/* 0x000fc80000010100 */
/*0370*/ FFMA R3, R3, R4, R3 ; /* 0x0000000403037223 */
/* 0x000fc80000000003 */
/*0380*/ FFMA R3, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003037823 */
/* 0x000fe200000000ff */
/*0390*/ BRA 0x5c0 ; /* 0x0000022000007947 */
/* 0x000fea0003800000 */
/*03a0*/ IADD3 R4, R3, -0xfd, RZ ; /* 0xffffff0303047810 */
/* 0x000fc80007ffe0ff */
/*03b0*/ ISETP.GT.U32.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f04070 */
/*03c0*/ @P0 BRA 0x5b0 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*03d0*/ LOP3.LUT R5, R2, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff02057812 */
/* 0x000fe200078ec0ff */
/*03e0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3 ; /* 0x00000003ff097424 */
/* 0x000fc600078e00ff */
/*03f0*/ LOP3.LUT R5, R5, 0x3f800000, RZ, 0xfc, !PT ; /* 0x3f80000005057812 */
/* 0x000fe400078efcff */
/*0400*/ SHF.L.U32 R10, R9, R4, RZ ; /* 0x00000004090a7219 */
/* 0x000fe400000006ff */
/*0410*/ MUFU.RCP R6, R5 ; /* 0x0000000500067308 */
/* 0x000e240000001000 */
/*0420*/ FFMA R7, R5, R6, -1 ; /* 0xbf80000005077423 */
/* 0x001fc80000000006 */
/*0430*/ FADD.FTZ R7, -R7, -RZ ; /* 0x800000ff07077221 */
/* 0x000fc80000010100 */
/*0440*/ FFMA.RM R8, R6.reuse, R7.reuse, R6.reuse ; /* 0x0000000706087223 */
/* 0x1c0fe40000004006 */
/*0450*/ FFMA.RP R7, R6, R7, R6 ; /* 0x0000000706077223 */
/* 0x000fc60000008006 */
/*0460*/ LOP3.LUT R6, R8.reuse, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff08067812 */
/* 0x040fe400078ec0ff */
/*0470*/ FSETP.NEU.FTZ.AND P0, PT, R8, R7, PT ; /* 0x000000070800720b */
/* 0x000fe40003f1d000 */
/*0480*/ LOP3.LUT R7, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006077812 */
/* 0x000fe400078efcff */
/*0490*/ SEL R6, RZ, 0xffffffff, !P0 ; /* 0xffffffffff067807 */
/* 0x000fe40004000000 */
/*04a0*/ LOP3.LUT R5, R10, R7, RZ, 0xc0, !PT ; /* 0x000000070a057212 */
/* 0x000fc600078ec0ff */
/*04b0*/ IMAD.MOV R6, RZ, RZ, -R6 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0a06 */
/*04c0*/ SHF.R.U32.HI R5, RZ, R4, R5 ; /* 0x00000004ff057219 */
/* 0x000fc80000011605 */
/*04d0*/ LOP3.LUT P1, RZ, R6, R4, R7, 0xf8, !PT ; /* 0x0000000406ff7212 */
/* 0x000fe4000782f807 */
/*04e0*/ LOP3.LUT P0, RZ, R5.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000105ff7812 */
/* 0x040fe4000780c0ff */
/*04f0*/ LOP3.LUT P2, RZ, R5, 0x2, RZ, 0xc0, !PT ; /* 0x0000000205ff7812 */
/* 0x000fc8000784c0ff */
/*0500*/ PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703c20 */
/*0510*/ LOP3.LUT P1, RZ, R2, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff02ff7812 */
/* 0x000fe4000782c0ff */
/*0520*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fca0004000000 */
/*0530*/ IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff047224 */
/* 0x000fca00078e0a04 */
/*0540*/ ISETP.GE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f06270 */
/*0550*/ IADD3 R4, R3, -0xfc, RZ ; /* 0xffffff0403047810 */
/* 0x000fc80007ffe0ff */
/*0560*/ SHF.R.U32.HI R3, RZ, R4, R7 ; /* 0x00000004ff037219 */
/* 0x000fce0000011607 */
/*0570*/ @!P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103038810 */
/* 0x000fca0007ffe0ff */
/*0580*/ @!P1 IMAD.SHL.U32 R3, R3, 0x2, RZ ; /* 0x0000000203039824 */
/* 0x000fca00078e00ff */
/*0590*/ LOP3.LUT R3, R3, 0x80000000, R2, 0xf8, !PT ; /* 0x8000000003037812 */
/* 0x000fe200078ef802 */
/*05a0*/ BRA 0x5c0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*05b0*/ MUFU.RCP R3, R2 ; /* 0x0000000200037308 */
/* 0x0000640000001000 */
/*05c0*/ IMAD.MOV.U32 R4, RZ, RZ, R3 ; /* 0x000000ffff047224 */
/* 0x002fe400078e0003 */
/*05d0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0000 */
/*05e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*05f0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffffa0002007950 */
/* 0x000fea0003c3ffff */
/*0600*/ BRA 0x600; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
static const int NTHREADS = 32;
__global__ void cunn_ClassNLLCriterion_updateGradInput_kernel1( float* gradInput, float* weights, float* target, float* total_weight, int size_average, int n_classes)
{
if (*total_weight <= 0) {
return;
}
float norm = size_average ? (1.0f / *total_weight) : 1.0f;
int t = (int)*target - 1;
if (t >= 0 && t < n_classes) {
gradInput[t] = -(weights ? weights[t] : 1.0f) * norm;
}
} | .file "tmpxft_001465e2_00000000-6_cunn_ClassNLLCriterion_updateGradInput_kernel1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z74__device_stub__Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_iiPfS_S_S_ii
.type _Z74__device_stub__Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_iiPfS_S_S_ii, @function
_Z74__device_stub__Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_iiPfS_S_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z74__device_stub__Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_iiPfS_S_S_ii, .-_Z74__device_stub__Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_iiPfS_S_S_ii
.globl _Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii
.type _Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii, @function
_Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z74__device_stub__Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_iiPfS_S_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii, .-_Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
static const int NTHREADS = 32;
__global__ void cunn_ClassNLLCriterion_updateGradInput_kernel1( float* gradInput, float* weights, float* target, float* total_weight, int size_average, int n_classes)
{
if (*total_weight <= 0) {
return;
}
float norm = size_average ? (1.0f / *total_weight) : 1.0f;
int t = (int)*target - 1;
if (t >= 0 && t < n_classes) {
gradInput[t] = -(weights ? weights[t] : 1.0f) * norm;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
static const int NTHREADS = 32;
__global__ void cunn_ClassNLLCriterion_updateGradInput_kernel1( float* gradInput, float* weights, float* target, float* total_weight, int size_average, int n_classes)
{
if (*total_weight <= 0) {
return;
}
float norm = size_average ? (1.0f / *total_weight) : 1.0f;
int t = (int)*target - 1;
if (t >= 0 && t < n_classes) {
gradInput[t] = -(weights ? weights[t] : 1.0f) * norm;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
static const int NTHREADS = 32;
__global__ void cunn_ClassNLLCriterion_updateGradInput_kernel1( float* gradInput, float* weights, float* target, float* total_weight, int size_average, int n_classes)
{
if (*total_weight <= 0) {
return;
}
float norm = size_average ? (1.0f / *total_weight) : 1.0f;
int t = (int)*target - 1;
if (t >= 0 && t < n_classes) {
gradInput[t] = -(weights ? weights[t] : 1.0f) * norm;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii
.globl _Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii
.p2align 8
.type _Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii,@function
_Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii:
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_load_b32 s6, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_le_f32_e64 s2, s6, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_5
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s4, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_cvt_i32_f32_e32 v0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, 1, v0
v_cmp_lt_i32_e64 s2, s4, v0
s_or_b32 s3, vcc_lo, s2
v_readfirstlane_b32 s2, v0
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB0_5
s_load_b64 s[4:5], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1)
s_add_i32 s2, s2, -1
s_mov_b32 s7, 1.0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u64 s[4:5], 0
s_cbranch_scc1 .LBB0_4
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 2
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_load_b32 s7, s[4:5], 0x0
.LBB0_4:
v_div_scale_f32 v0, null, s6, s6, 1.0
v_div_scale_f32 v3, vcc_lo, 1.0, s6, 1.0
s_load_b32 s3, s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v1, v0
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt_depctr 0xfff
v_fma_f32 v2, -v0, v1, 1.0
v_fmac_f32_e32 v1, v2, v1
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v2, v3, v1
s_mov_b32 s3, 0
v_fma_f32 v4, -v0, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, v4, v1
v_fma_f32 v0, -v0, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_div_fmas_f32 v0, v0, v1, v2
v_mov_b32_e32 v1, 0
s_cselect_b32 vcc_lo, -1, 0
s_lshl_b64 s[2:3], s[2:3], 2
s_add_u32 s0, s0, s2
v_div_fixup_f32 v0, v0, s6, 1.0
s_addc_u32 s1, s1, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, 1.0, v0, vcc_lo
v_mul_f32_e64 v0, v0, -s7
global_store_b32 v1, v0, s[0:1]
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii, .Lfunc_end0-_Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
static const int NTHREADS = 32;
__global__ void cunn_ClassNLLCriterion_updateGradInput_kernel1( float* gradInput, float* weights, float* target, float* total_weight, int size_average, int n_classes)
{
if (*total_weight <= 0) {
return;
}
float norm = size_average ? (1.0f / *total_weight) : 1.0f;
int t = (int)*target - 1;
if (t >= 0 && t < n_classes) {
gradInput[t] = -(weights ? weights[t] : 1.0f) * norm;
}
} | .text
.file "cunn_ClassNLLCriterion_updateGradInput_kernel1.hip"
.globl _Z61__device_stub__cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii # -- Begin function _Z61__device_stub__cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii
.p2align 4, 0x90
.type _Z61__device_stub__cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii,@function
_Z61__device_stub__cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii: # @_Z61__device_stub__cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z61__device_stub__cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii, .Lfunc_end0-_Z61__device_stub__cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii,@object # @_Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii
.section .rodata,"a",@progbits
.globl _Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii
.p2align 3, 0x0
_Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii:
.quad _Z61__device_stub__cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii
.size _Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii"
.size .L__unnamed_1, 61
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z61__device_stub__cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff037624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*0050*/ FSETP.GTU.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x004fda0003f0c000 */
/*0060*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0070*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fe20003f05270 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff007424 */
/* 0x000fd800078e00ff */
/*0090*/ @!P0 BRA 0x160 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R0, R2, 0x1800000, RZ ; /* 0x0180000002007810 */
/* 0x000fc80007ffe0ff */
/*00b0*/ LOP3.LUT R0, R0, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000000007812 */
/* 0x000fc800078ec0ff */
/*00c0*/ ISETP.GT.U32.AND P0, PT, R0, 0x1ffffff, PT ; /* 0x01ffffff0000780c */
/* 0x000fda0003f04070 */
/*00d0*/ @P0 BRA 0x120 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*00e0*/ MOV R0, 0x100 ; /* 0x0000010000007802 */
/* 0x000fe40000000f00 */
/*00f0*/ CALL.REL.NOINC 0x2b0 ; /* 0x000001b000007944 */
/* 0x000fea0003c00000 */
/*0100*/ IMAD.MOV.U32 R0, RZ, RZ, R4 ; /* 0x000000ffff007224 */
/* 0x000fe200078e0004 */
/*0110*/ BRA 0x160 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0120*/ MUFU.RCP R3, R2 ; /* 0x0000000200037308 */
/* 0x000e240000001000 */
/*0130*/ FFMA R0, R2, R3, -1 ; /* 0xbf80000002007423 */
/* 0x001fc80000000003 */
/*0140*/ FADD.FTZ R0, -R0, -RZ ; /* 0x800000ff00007221 */
/* 0x000fc80000010100 */
/*0150*/ FFMA R0, R3, R0, R3 ; /* 0x0000000003007223 */
/* 0x000fe40000000003 */
/*0160*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe400078e00ff */
/*0170*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fca00078e00ff */
/*0180*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*0190*/ F2I.TRUNC.NTZ R4, R2 ; /* 0x0000000200047305 */
/* 0x004e24000020f100 */
/*01a0*/ ISETP.GT.AND P0, PT, R4, c[0x0][0x184], PT ; /* 0x0000610004007a0c */
/* 0x001fc80003f04270 */
/*01b0*/ ISETP.LT.OR P0, PT, R4, 0x1, P0 ; /* 0x000000010400780c */
/* 0x000fda0000701670 */
/*01c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe40003f05070 */
/*01e0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x16c], PT, P0 ; /* 0x00005b00ff007a0c */
/* 0x000fda0003f05300 */
/*0200*/ @!P0 BRA 0x250 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0210*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0220*/ IMAD.WIDE R2, R4, R3, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0203 */
/*0230*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000162000c1e1900 */
/*0240*/ BRA 0x260 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0250*/ IMAD.MOV.U32 R3, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff037424 */
/* 0x000fe400078e00ff */
/*0260*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe400078e00ff */
/*0270*/ FFMA R5, -R3, R0, -RZ ; /* 0x0000000003057223 */
/* 0x020fe400000009ff */
/*0280*/ IMAD.WIDE R2, R4, R7, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x001fca00078e0207 */
/*0290*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*02a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02b0*/ IMAD.SHL.U32 R3, R2, 0x2, RZ ; /* 0x0000000202037824 */
/* 0x000fca00078e00ff */
/*02c0*/ SHF.R.U32.HI R3, RZ, 0x18, R3 ; /* 0x00000018ff037819 */
/* 0x000fc80000011603 */
/*02d0*/ ISETP.NE.U32.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05070 */
/*02e0*/ @P0 BRA 0x3a0 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*02f0*/ IMAD.SHL.U32 R3, R2, 0x2, RZ ; /* 0x0000000202037824 */
/* 0x000fca00078e00ff */
/*0300*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0310*/ @!P0 MUFU.RCP R3, R2 ; /* 0x0000000200038308 */
/* 0x0000620000001000 */
/*0320*/ @!P0 BRA 0x5c0 ; /* 0x0000029000008947 */
/* 0x000fea0003800000 */
/*0330*/ FFMA R2, R2, 1.84467440737095516160e+19, RZ ; /* 0x5f80000002027823 */
/* 0x001fc800000000ff */
/*0340*/ MUFU.RCP R3, R2 ; /* 0x0000000200037308 */
/* 0x002e240000001000 */
/*0350*/ FFMA R4, R2, R3, -1 ; /* 0xbf80000002047423 */
/* 0x001fc80000000003 */
/*0360*/ FADD.FTZ R4, -R4, -RZ ; /* 0x800000ff04047221 */
/* 0x000fc80000010100 */
/*0370*/ FFMA R3, R3, R4, R3 ; /* 0x0000000403037223 */
/* 0x000fc80000000003 */
/*0380*/ FFMA R3, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003037823 */
/* 0x000fe200000000ff */
/*0390*/ BRA 0x5c0 ; /* 0x0000022000007947 */
/* 0x000fea0003800000 */
/*03a0*/ IADD3 R4, R3, -0xfd, RZ ; /* 0xffffff0303047810 */
/* 0x000fc80007ffe0ff */
/*03b0*/ ISETP.GT.U32.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f04070 */
/*03c0*/ @P0 BRA 0x5b0 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*03d0*/ LOP3.LUT R5, R2, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff02057812 */
/* 0x000fe200078ec0ff */
/*03e0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3 ; /* 0x00000003ff097424 */
/* 0x000fc600078e00ff */
/*03f0*/ LOP3.LUT R5, R5, 0x3f800000, RZ, 0xfc, !PT ; /* 0x3f80000005057812 */
/* 0x000fe400078efcff */
/*0400*/ SHF.L.U32 R10, R9, R4, RZ ; /* 0x00000004090a7219 */
/* 0x000fe400000006ff */
/*0410*/ MUFU.RCP R6, R5 ; /* 0x0000000500067308 */
/* 0x000e240000001000 */
/*0420*/ FFMA R7, R5, R6, -1 ; /* 0xbf80000005077423 */
/* 0x001fc80000000006 */
/*0430*/ FADD.FTZ R7, -R7, -RZ ; /* 0x800000ff07077221 */
/* 0x000fc80000010100 */
/*0440*/ FFMA.RM R8, R6.reuse, R7.reuse, R6.reuse ; /* 0x0000000706087223 */
/* 0x1c0fe40000004006 */
/*0450*/ FFMA.RP R7, R6, R7, R6 ; /* 0x0000000706077223 */
/* 0x000fc60000008006 */
/*0460*/ LOP3.LUT R6, R8.reuse, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff08067812 */
/* 0x040fe400078ec0ff */
/*0470*/ FSETP.NEU.FTZ.AND P0, PT, R8, R7, PT ; /* 0x000000070800720b */
/* 0x000fe40003f1d000 */
/*0480*/ LOP3.LUT R7, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006077812 */
/* 0x000fe400078efcff */
/*0490*/ SEL R6, RZ, 0xffffffff, !P0 ; /* 0xffffffffff067807 */
/* 0x000fe40004000000 */
/*04a0*/ LOP3.LUT R5, R10, R7, RZ, 0xc0, !PT ; /* 0x000000070a057212 */
/* 0x000fc600078ec0ff */
/*04b0*/ IMAD.MOV R6, RZ, RZ, -R6 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0a06 */
/*04c0*/ SHF.R.U32.HI R5, RZ, R4, R5 ; /* 0x00000004ff057219 */
/* 0x000fc80000011605 */
/*04d0*/ LOP3.LUT P1, RZ, R6, R4, R7, 0xf8, !PT ; /* 0x0000000406ff7212 */
/* 0x000fe4000782f807 */
/*04e0*/ LOP3.LUT P0, RZ, R5.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000105ff7812 */
/* 0x040fe4000780c0ff */
/*04f0*/ LOP3.LUT P2, RZ, R5, 0x2, RZ, 0xc0, !PT ; /* 0x0000000205ff7812 */
/* 0x000fc8000784c0ff */
/*0500*/ PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703c20 */
/*0510*/ LOP3.LUT P1, RZ, R2, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff02ff7812 */
/* 0x000fe4000782c0ff */
/*0520*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fca0004000000 */
/*0530*/ IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff047224 */
/* 0x000fca00078e0a04 */
/*0540*/ ISETP.GE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f06270 */
/*0550*/ IADD3 R4, R3, -0xfc, RZ ; /* 0xffffff0403047810 */
/* 0x000fc80007ffe0ff */
/*0560*/ SHF.R.U32.HI R3, RZ, R4, R7 ; /* 0x00000004ff037219 */
/* 0x000fce0000011607 */
/*0570*/ @!P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103038810 */
/* 0x000fca0007ffe0ff */
/*0580*/ @!P1 IMAD.SHL.U32 R3, R3, 0x2, RZ ; /* 0x0000000203039824 */
/* 0x000fca00078e00ff */
/*0590*/ LOP3.LUT R3, R3, 0x80000000, R2, 0xf8, !PT ; /* 0x8000000003037812 */
/* 0x000fe200078ef802 */
/*05a0*/ BRA 0x5c0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*05b0*/ MUFU.RCP R3, R2 ; /* 0x0000000200037308 */
/* 0x0000640000001000 */
/*05c0*/ IMAD.MOV.U32 R4, RZ, RZ, R3 ; /* 0x000000ffff047224 */
/* 0x002fe400078e0003 */
/*05d0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0000 */
/*05e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*05f0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffffa0002007950 */
/* 0x000fea0003c3ffff */
/*0600*/ BRA 0x600; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii
.globl _Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii
.p2align 8
.type _Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii,@function
_Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii:
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_load_b32 s6, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_le_f32_e64 s2, s6, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_5
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s4, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_cvt_i32_f32_e32 v0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, 1, v0
v_cmp_lt_i32_e64 s2, s4, v0
s_or_b32 s3, vcc_lo, s2
v_readfirstlane_b32 s2, v0
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB0_5
s_load_b64 s[4:5], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1)
s_add_i32 s2, s2, -1
s_mov_b32 s7, 1.0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u64 s[4:5], 0
s_cbranch_scc1 .LBB0_4
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 2
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_load_b32 s7, s[4:5], 0x0
.LBB0_4:
v_div_scale_f32 v0, null, s6, s6, 1.0
v_div_scale_f32 v3, vcc_lo, 1.0, s6, 1.0
s_load_b32 s3, s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v1, v0
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt_depctr 0xfff
v_fma_f32 v2, -v0, v1, 1.0
v_fmac_f32_e32 v1, v2, v1
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v2, v3, v1
s_mov_b32 s3, 0
v_fma_f32 v4, -v0, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, v4, v1
v_fma_f32 v0, -v0, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_div_fmas_f32 v0, v0, v1, v2
v_mov_b32_e32 v1, 0
s_cselect_b32 vcc_lo, -1, 0
s_lshl_b64 s[2:3], s[2:3], 2
s_add_u32 s0, s0, s2
v_div_fixup_f32 v0, v0, s6, 1.0
s_addc_u32 s1, s1, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, 1.0, v0, vcc_lo
v_mul_f32_e64 v0, v0, -s7
global_store_b32 v1, v0, s[0:1]
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii, .Lfunc_end0-_Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001465e2_00000000-6_cunn_ClassNLLCriterion_updateGradInput_kernel1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z74__device_stub__Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_iiPfS_S_S_ii
.type _Z74__device_stub__Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_iiPfS_S_S_ii, @function
_Z74__device_stub__Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_iiPfS_S_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z74__device_stub__Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_iiPfS_S_S_ii, .-_Z74__device_stub__Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_iiPfS_S_S_ii
.globl _Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii
.type _Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii, @function
_Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z74__device_stub__Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_iiPfS_S_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii, .-_Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cunn_ClassNLLCriterion_updateGradInput_kernel1.hip"
.globl _Z61__device_stub__cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii # -- Begin function _Z61__device_stub__cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii
.p2align 4, 0x90
.type _Z61__device_stub__cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii,@function
_Z61__device_stub__cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii: # @_Z61__device_stub__cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z61__device_stub__cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii, .Lfunc_end0-_Z61__device_stub__cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii,@object # @_Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii
.section .rodata,"a",@progbits
.globl _Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii
.p2align 3, 0x0
_Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii:
.quad _Z61__device_stub__cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii
.size _Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii"
.size .L__unnamed_1, 61
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z61__device_stub__cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z46cunn_ClassNLLCriterion_updateGradInput_kernel1PfS_S_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <iostream>
#include <fstream>
#include <string>
#include <vector>
#include <algorithm>
#include <time.h>
#include <cmath>
#include <limits.h>
#define MAXHOPS 4
#define MAX_WAITING_TIME 420
#define BLOCK_LENGTH 512
#define END_OF_ARRAY 2147483647
#define BUFFER_LENGTH 50
#define AIRPORT_PATH "C:/Users/acer/Desktop/Semester 7/Project/AA_airports.txt" //"C:/Users/acer/Desktop/Semester 7/Project/Data/AA_airports.txt"
#define FLIGHT_PATH "C:/Users/acer/Desktop/Semester 7/Project/AA_data1.txt" //"C:/Users/acer/Desktop/Semester 7/Project/Data/OAGX_data_num_1.txt"
bool bool1 = true;
bool bool2 = false;
using namespace std;
cudaError_t addWithCuda(int *c, const int *a, const int *b, size_t size);
// for cuda error checking
#define cudaCheckErrors(msg) \
do { \
cudaError_t __err = cudaGetLastError(); \
if (__err != cudaSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, cudaGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
return 1; \
} \
} while (0)
int ADJ_MATRIX_DIM;
__device__ int DEV_ADJ_MATRIX_DIM;
// FYP_BFS.cpp : Defines the entry point for the console application.
//
///////////////////Global Variables///////////////////
struct Flight{
int flightNumber;
int source;
int destination;
int arrivalTime;
int departureTime;
int price;
string code;
};
vector<string> Airport_List;
vector<Flight> Flight_List;
vector<int>** AdjMatrix;
//////////////////////////////////////////////////////
//////////////////Data Read///////////////////////////
int readAirports(){
ifstream myFile;
myFile.open(AIRPORT_PATH);
int numberOfAirports=0;
if(myFile.is_open()){
string line;
cout<<"Reading Airports"<<endl;
while(myFile.good()){
//------------------------------changed-------------------//
//myFile.ignore(256,' ');
string s;
myFile>>s;
Airport_List.push_back(s);
numberOfAirports++;
}
}
myFile.close();
ADJ_MATRIX_DIM = Airport_List.size();
//cudaMemcpy(DEV_ADJ_MATRIX_DIM,&ADJ_MATRIX_DIM,sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(DEV_ADJ_MATRIX_DIM,&ADJ_MATRIX_DIM,sizeof(int),0,cudaMemcpyHostToDevice);
cudaCheckErrors("Error copying adj matrix dim to device");
cout<<Airport_List.size()<<" Airports Found"<<endl;
return 1;
}
void readFlights(){
//this is a bloody array of pointers
AdjMatrix = new vector<int>*[Airport_List.size()];
for(int i=0;i<Airport_List.size();i++){
//thisi is a bloody array of vectors
AdjMatrix[i] = new vector<int>[Airport_List.size()];
}
ifstream myFile;
myFile.open(FLIGHT_PATH);
int numOfFlights = 0;
if(myFile.is_open()){
string line;
Flight tempFlight;
while(myFile.good()){
//---------------------------------------changed----------------------------------------//
tempFlight.flightNumber= numOfFlights;
/*myFile>>tempFlight.source;
myFile>>tempFlight.destination;
myFile>>tempFlight.departureTime;
myFile>>tempFlight.arrivalTime;
if(tempFlight.arrivalTime<tempFlight.departureTime) tempFlight.arrivalTime+=10080;
myFile>>tempFlight.price;
myFile>>tempFlight.code;*/
myFile>>tempFlight.source;
myFile>>tempFlight.destination;
myFile>>tempFlight.price;
myFile>>tempFlight.departureTime;
myFile>>tempFlight.arrivalTime;
if(tempFlight.arrivalTime<tempFlight.departureTime) tempFlight.arrivalTime+=10080;
myFile>>tempFlight.code;
//add this flight to the adjmatrix;
Flight_List.push_back(tempFlight);
AdjMatrix[tempFlight.source][tempFlight.destination].push_back(tempFlight.flightNumber);
numOfFlights++;
if(numOfFlights%10000==0) cout<<"*";
}
cout<<endl;
}
myFile.close();
cout<<Flight_List.size()<<" Flights Found"<<endl;
}
/////////////////////////////////////////////////////////////////////////////////////
struct route{
vector<int> flights;
int weight;
};
int initializeFlightListInDevice(Flight* &dev_flight_list){
//allocate space for the flight list in cuda
cudaMalloc((void**)&dev_flight_list, Flight_List.size()*sizeof(Flight));
cudaCheckErrors("Failed to allocate memory to flight list");
cudaMemcpy(dev_flight_list,&Flight_List[0],Flight_List.size()*sizeof(Flight),cudaMemcpyHostToDevice);
cudaCheckErrors("Failed to copy flight list");
return 1;
}
int initializeAdjMatrixInDevice(int** &dev_adj_list, int ** &host_adj_vector){
size_t size = ADJ_MATRIX_DIM*ADJ_MATRIX_DIM*sizeof(int*);
//the vector in host that records the pointers in device memory
host_adj_vector = (int **)malloc(size);
//i indicates rows and j indicates columns of the adjacency matrix
//allocate device memory for the boolean vector
//allocate memory for each manhattan in device and store the pointer in memory
for(int i=0;i<ADJ_MATRIX_DIM;i++){
for(int j=0;j<ADJ_MATRIX_DIM;j++){
cudaMalloc((void **)&host_adj_vector[i*ADJ_MATRIX_DIM+j],AdjMatrix[i][j].size()*sizeof(int));
cudaCheckErrors("Failed to allocate memory to airport list manhattan:");
cudaMemcpy(host_adj_vector[i*ADJ_MATRIX_DIM+j],&AdjMatrix[i][j][0],AdjMatrix[i][j].size()*sizeof(int),cudaMemcpyHostToDevice);
cudaCheckErrors("Failed to copy data to airport list manhattan:");
}
if(i%100==0) cout<<"&";
}
cout<<endl;
cudaMalloc((void***)&dev_adj_list,size);
cudaCheckErrors("Failed to allocate memory to pointer list in device");
cudaMemcpy(dev_adj_list,host_adj_vector,size,cudaMemcpyHostToDevice);
cudaCheckErrors("Failed to allocate data to pointer list in device");
return 1;
}
int initializeBooleanMatrixInDevice(int* &boolean_matrix){
int* host_bool_matrix= new int[ADJ_MATRIX_DIM*ADJ_MATRIX_DIM];
for(int i=0;i<ADJ_MATRIX_DIM;i++){
for(int j=0;j<ADJ_MATRIX_DIM;j++){
host_bool_matrix[i*ADJ_MATRIX_DIM+j] = (AdjMatrix[i][j].size() !=0);
}
}
size_t size_bool =ADJ_MATRIX_DIM*ADJ_MATRIX_DIM*sizeof(int);
cudaMalloc((void**)&boolean_matrix,size_bool);
cudaCheckErrors("Failed to allocate memory to boolean adj matrix");
cudaMemcpy(boolean_matrix,host_bool_matrix,size_bool,cudaMemcpyHostToDevice);
cudaCheckErrors("Failed to move data to boolean adj matrix");
delete(host_bool_matrix);
return 1;
}
int initializeBuffer(int* &buffer){
//buffer size
int* host_bool_buffer= new int[ADJ_MATRIX_DIM*ADJ_MATRIX_DIM*MAXHOPS];
//
for(int k=0;k<MAXHOPS;k++){
for(int i=0;i<ADJ_MATRIX_DIM;i++){
for(int j=0;j<ADJ_MATRIX_DIM;j++){
host_bool_buffer[k*ADJ_MATRIX_DIM*ADJ_MATRIX_DIM+ i*ADJ_MATRIX_DIM+j] = false;
}
}
}
size_t size_bool =MAXHOPS*ADJ_MATRIX_DIM*ADJ_MATRIX_DIM*sizeof(int);
cudaMalloc((void**)&buffer,size_bool);
cudaCheckErrors("Failed to allocate memory to boolean buffer");
cudaMemcpy(buffer,host_bool_buffer,size_bool,cudaMemcpyHostToDevice);
cudaCheckErrors("Failed to move data to boolean buffer");
delete(host_bool_buffer);
return 1;
}
__global__ void testBuffer(int* buffer,int* result, int size){
int id =blockIdx.x*blockDim.x+threadIdx.x;
if(id<size){
if(buffer[id])
result[id] = 1234345;
else
result[id] = 0;
}
}
__global__ void testMatrix(int** devVector,int size, int* result, Flight* flights){
//block dimension is the number of threads in a block. since blockid is zero based multiplying gets you somewhre close.
//to gt the correct position all u have to do then is to add the thread id
int i = blockIdx.x*blockDim.x+threadIdx.x;
result[i] = 0;
if(i<size*size && devVector[i]!= NULL )
result[i] = flights[devVector[i][0]].source;
}
__global__ void testMatrixBoolean(int* devMatrixBoolean,int size, int* result){
int i = blockIdx.x*blockDim.x+threadIdx.x;
result[i] = 0;
//put 1 if a manhattan exists for the particular position
if(i<size*size && devMatrixBoolean[i])
result[i] = 1;
}
//initialize buffer to end of array value so that as values are filled the array size will change, but will still be
//indicated by the first end of array value
//__global__ void initializeBuffer(bool* buffer, int size){
// int id = blockIdx.x*blockDim.x+threadIdx.x;
// if(id<size)
// buffer[id] = false;
//}
//give enough threads to span the source row
//maximum id should be adj_matrix_dimension
__global__ void firstExpansion(int* buffer, int*dev_boolean_matrix, int source){
int id = blockIdx.x*blockDim.x+threadIdx.x;
//the source row.
//if(id<DEV_ADJ_MATRIX_DIM*DEV_ADJ_MATRIX_DIM){
// //if(dev_adj_matrix[DEV_ADJ_MATRIX_DIM*(source-1)+id]!=NULL){
// // //set source to the precedant node list of each relevant airport
// // buffer[id*BUFFER_LENGTH] = source;
// //}
//}
}
//max id is number of airports
__global__ void expansion(int* dev_buffer1,int* boolean_matrix, int* dev_source_vector,int matrix_dimension){
int id = blockIdx.x*blockDim.x+threadIdx.x;
int row = (int) floor((double)id/matrix_dimension);
int column = id%matrix_dimension;
for(int k=0;k<MAXHOPS;k++){
if(row<matrix_dimension && column<matrix_dimension ){
//for the source row if the matrix row column position has a manhattan set the buffer position to true
dev_buffer1[k*matrix_dimension*matrix_dimension+id] = (dev_source_vector[row] && boolean_matrix[id]);
}
__syncthreads();
//set the 'next source vector' positions to zero by the first of each row
if(row<matrix_dimension && column<matrix_dimension&& column==0) dev_source_vector[row]= 0;
__syncthreads();
//if the relevant cell in the frame has been set, contribute to making sure the relevant cell in the 'next source vector' is set to 1
if((row<matrix_dimension && column<matrix_dimension) && dev_buffer1[k*matrix_dimension*matrix_dimension+id]){
dev_source_vector[column] = 1;
}
__syncthreads();
}
}
//__global__ void copyNextSource(bool* next_source_array, bool* current_array, int size){
// int id = blockDim.x*blockIdx.x+threadIdx.x;
// if(id<size)
// cudaMemcpy
//}
int main(int argc)
{
readAirports();
readFlights();
int source = 344;
int destination = 190;
Flight* dev_flight_list;
int** dev_adj_list;
int* dev_adj_matrix_boolean;
int** host_adj_vector;
int* dev_level1;
int* dev_level2;
int* frames;
//boolean array containing source airports in the next expansion
int* dev_next_source_array;
size_t matrixSize = ADJ_MATRIX_DIM*ADJ_MATRIX_DIM*sizeof(int);
size_t bufferSize = ADJ_MATRIX_DIM*ADJ_MATRIX_DIM*sizeof(int);
//add the flight array to GPU memory
cout<<"Initializing Flights"<<endl;
initializeFlightListInDevice(dev_flight_list);
cout<<"finished initializing FLights"<<endl;
//add the adjacency matrix with manhattans to GPU
cout<<"Initializing Matrix"<<endl;
initializeAdjMatrixInDevice(dev_adj_list,host_adj_vector);
cout<<"Finished with adj matrix"<<endl;
//add the boolean adjacency matrix (without manhattans) to GPU
cout<<"Initializing Boolean Matrix"<<endl;
initializeBooleanMatrixInDevice(dev_adj_matrix_boolean);
cout<<"Finished with boolean matrix"<<endl;
//allocate memory for the 'next source array' in device
cudaMalloc((void**)&dev_next_source_array,ADJ_MATRIX_DIM*sizeof(int));
cudaCheckErrors("Failed to allocate memory to next source list");
int* source_vector = new int [ADJ_MATRIX_DIM];
//initialize the 'next source vector' with the source row of the adjacency matrix
for(int i=0;i<ADJ_MATRIX_DIM;i++){
source_vector[i] = AdjMatrix[source][i].size()!=0;
}
//intialize 'next source array' in device
cudaMemcpy(dev_next_source_array,source_vector,ADJ_MATRIX_DIM*sizeof(int),cudaMemcpyHostToDevice);
cudaCheckErrors("Failed to move data to next source list");
delete(source_vector);
//////////////////////initialize the buffers for all the levels/////////////////
cout<<"initializing Buffers"<<endl;
initializeBuffer(dev_level1);
//initializeBuffer(dev_level2);
cout<<"initialized buffers"<<endl;
///////////////////////////////////////Interations///////////////////////////////////////
int numBlocks = ceil((double)ADJ_MATRIX_DIM*ADJ_MATRIX_DIM/BLOCK_LENGTH);
ofstream myFile;
myFile.open("nextSource.txt");
int* myArray = (int*) malloc(ADJ_MATRIX_DIM*sizeof(int));
cudaMemcpy(myArray,dev_next_source_array,ADJ_MATRIX_DIM*sizeof(int),cudaMemcpyDeviceToHost);
cudaCheckErrors("Failed to copy data from buffer array to host array");
for(int i=0;i<ADJ_MATRIX_DIM;i++){
//if(myArray[i]!= NULL)
myFile<<myArray[i];
}
myFile<<endl<<endl;
free(myArray);
cout<<"moving into first expansion"<<endl;
ofstream myFile2;
myFile2.open("Frame1.txt");
int* myArray2 = (int*)malloc(MAXHOPS*ADJ_MATRIX_DIM*ADJ_MATRIX_DIM*sizeof(int));
expansion<<<numBlocks,BLOCK_LENGTH>>>(dev_level1,dev_adj_matrix_boolean,dev_next_source_array,ADJ_MATRIX_DIM);
cudaThreadSynchronize();
cudaCheckErrors("Error occured in expansion");
cout<<"finished expansion"<<endl;
cudaMemcpy(myArray2,dev_level1,MAXHOPS*ADJ_MATRIX_DIM*ADJ_MATRIX_DIM*sizeof(int),cudaMemcpyDeviceToHost);
cudaCheckErrors("Failed to retrieve memory from first frame");
for(int j=0;j<MAXHOPS;j++){
for(int i=0;i<ADJ_MATRIX_DIM*ADJ_MATRIX_DIM;i++){
//if(myArray[i]!= NULL)
myFile2<<myArray2[j*ADJ_MATRIX_DIM*ADJ_MATRIX_DIM+i];
}
myFile2<<endl;
}
myFile2<<endl<<endl;
myFile2.close();
free(myArray2);
int* myArray1 = (int*)malloc(ADJ_MATRIX_DIM*sizeof(int));
/* expansion<<<numBlocks,BLOCK_LENGTH>>>(dev_level1,dev_adj_matrix_boolean,dev_next_source_array,ADJ_MATRIX_DIM);
cudaThreadSynchronize();
cudaCheckErrors("Error occured in expansion");
cout<<"finished expansion"<<endl;*/
cudaMemcpy(myArray1,dev_next_source_array,ADJ_MATRIX_DIM*sizeof(int),cudaMemcpyDeviceToHost);
cudaCheckErrors("Failed to retrieve memory from buffer array 1.2 to host");
for(int i=0;i<ADJ_MATRIX_DIM;i++){
//if(myArray[i]!= NULL)
myFile<<myArray1[i];
}
myFile<<endl<<endl;
free(myArray1);
myFile.close();
//cudaFree(dev_next_source_array);
cudaFree(dev_level1);
cudaFree(dev_level2);
cudaFree(dev_flight_list);
//for(int i=0;i<ADJ_MATRIX_DIM*ADJ_MATRIX_DIM;i++){
// //cout<<i<<endl;
// if(host_adj_vector[i] !=NULL)
// cudaFree(host_adj_vector[i]);
//}
cudaFree(dev_adj_list);
free(host_adj_vector);
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <iostream>
#include <fstream>
#include <string>
#include <vector>
#include <algorithm>
#include <time.h>
#include <cmath>
#include <limits.h>
#define MAXHOPS 4
#define MAX_WAITING_TIME 420
#define BLOCK_LENGTH 512
#define END_OF_ARRAY 2147483647
#define BUFFER_LENGTH 50
#define AIRPORT_PATH "C:/Users/acer/Desktop/Semester 7/Project/AA_airports.txt" //"C:/Users/acer/Desktop/Semester 7/Project/Data/AA_airports.txt"
#define FLIGHT_PATH "C:/Users/acer/Desktop/Semester 7/Project/AA_data1.txt" //"C:/Users/acer/Desktop/Semester 7/Project/Data/OAGX_data_num_1.txt"
bool bool1 = true;
bool bool2 = false;
using namespace std;
hipError_t addWithCuda(int *c, const int *a, const int *b, size_t size);
// for cuda error checking
#define cudaCheckErrors(msg) \
do { \
hipError_t __err = hipGetLastError(); \
if (__err != hipSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, hipGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
return 1; \
} \
} while (0)
int ADJ_MATRIX_DIM;
__device__ int DEV_ADJ_MATRIX_DIM;
// FYP_BFS.cpp : Defines the entry point for the console application.
//
///////////////////Global Variables///////////////////
struct Flight{
int flightNumber;
int source;
int destination;
int arrivalTime;
int departureTime;
int price;
string code;
};
vector<string> Airport_List;
vector<Flight> Flight_List;
vector<int>** AdjMatrix;
//////////////////////////////////////////////////////
//////////////////Data Read///////////////////////////
int readAirports(){
ifstream myFile;
myFile.open(AIRPORT_PATH);
int numberOfAirports=0;
if(myFile.is_open()){
string line;
cout<<"Reading Airports"<<endl;
while(myFile.good()){
//------------------------------changed-------------------//
//myFile.ignore(256,' ');
string s;
myFile>>s;
Airport_List.push_back(s);
numberOfAirports++;
}
}
myFile.close();
ADJ_MATRIX_DIM = Airport_List.size();
//cudaMemcpy(DEV_ADJ_MATRIX_DIM,&ADJ_MATRIX_DIM,sizeof(int),cudaMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(DEV_ADJ_MATRIX_DIM),&ADJ_MATRIX_DIM,sizeof(int),0,hipMemcpyHostToDevice);
cudaCheckErrors("Error copying adj matrix dim to device");
cout<<Airport_List.size()<<" Airports Found"<<endl;
return 1;
}
void readFlights(){
//this is a bloody array of pointers
AdjMatrix = new vector<int>*[Airport_List.size()];
for(int i=0;i<Airport_List.size();i++){
//thisi is a bloody array of vectors
AdjMatrix[i] = new vector<int>[Airport_List.size()];
}
ifstream myFile;
myFile.open(FLIGHT_PATH);
int numOfFlights = 0;
if(myFile.is_open()){
string line;
Flight tempFlight;
while(myFile.good()){
//---------------------------------------changed----------------------------------------//
tempFlight.flightNumber= numOfFlights;
/*myFile>>tempFlight.source;
myFile>>tempFlight.destination;
myFile>>tempFlight.departureTime;
myFile>>tempFlight.arrivalTime;
if(tempFlight.arrivalTime<tempFlight.departureTime) tempFlight.arrivalTime+=10080;
myFile>>tempFlight.price;
myFile>>tempFlight.code;*/
myFile>>tempFlight.source;
myFile>>tempFlight.destination;
myFile>>tempFlight.price;
myFile>>tempFlight.departureTime;
myFile>>tempFlight.arrivalTime;
if(tempFlight.arrivalTime<tempFlight.departureTime) tempFlight.arrivalTime+=10080;
myFile>>tempFlight.code;
//add this flight to the adjmatrix;
Flight_List.push_back(tempFlight);
AdjMatrix[tempFlight.source][tempFlight.destination].push_back(tempFlight.flightNumber);
numOfFlights++;
if(numOfFlights%10000==0) cout<<"*";
}
cout<<endl;
}
myFile.close();
cout<<Flight_List.size()<<" Flights Found"<<endl;
}
/////////////////////////////////////////////////////////////////////////////////////
struct route{
vector<int> flights;
int weight;
};
int initializeFlightListInDevice(Flight* &dev_flight_list){
//allocate space for the flight list in cuda
hipMalloc((void**)&dev_flight_list, Flight_List.size()*sizeof(Flight));
cudaCheckErrors("Failed to allocate memory to flight list");
hipMemcpy(dev_flight_list,&Flight_List[0],Flight_List.size()*sizeof(Flight),hipMemcpyHostToDevice);
cudaCheckErrors("Failed to copy flight list");
return 1;
}
int initializeAdjMatrixInDevice(int** &dev_adj_list, int ** &host_adj_vector){
size_t size = ADJ_MATRIX_DIM*ADJ_MATRIX_DIM*sizeof(int*);
//the vector in host that records the pointers in device memory
host_adj_vector = (int **)malloc(size);
//i indicates rows and j indicates columns of the adjacency matrix
//allocate device memory for the boolean vector
//allocate memory for each manhattan in device and store the pointer in memory
for(int i=0;i<ADJ_MATRIX_DIM;i++){
for(int j=0;j<ADJ_MATRIX_DIM;j++){
hipMalloc((void **)&host_adj_vector[i*ADJ_MATRIX_DIM+j],AdjMatrix[i][j].size()*sizeof(int));
cudaCheckErrors("Failed to allocate memory to airport list manhattan:");
hipMemcpy(host_adj_vector[i*ADJ_MATRIX_DIM+j],&AdjMatrix[i][j][0],AdjMatrix[i][j].size()*sizeof(int),hipMemcpyHostToDevice);
cudaCheckErrors("Failed to copy data to airport list manhattan:");
}
if(i%100==0) cout<<"&";
}
cout<<endl;
hipMalloc((void***)&dev_adj_list,size);
cudaCheckErrors("Failed to allocate memory to pointer list in device");
hipMemcpy(dev_adj_list,host_adj_vector,size,hipMemcpyHostToDevice);
cudaCheckErrors("Failed to allocate data to pointer list in device");
return 1;
}
int initializeBooleanMatrixInDevice(int* &boolean_matrix){
int* host_bool_matrix= new int[ADJ_MATRIX_DIM*ADJ_MATRIX_DIM];
for(int i=0;i<ADJ_MATRIX_DIM;i++){
for(int j=0;j<ADJ_MATRIX_DIM;j++){
host_bool_matrix[i*ADJ_MATRIX_DIM+j] = (AdjMatrix[i][j].size() !=0);
}
}
size_t size_bool =ADJ_MATRIX_DIM*ADJ_MATRIX_DIM*sizeof(int);
hipMalloc((void**)&boolean_matrix,size_bool);
cudaCheckErrors("Failed to allocate memory to boolean adj matrix");
hipMemcpy(boolean_matrix,host_bool_matrix,size_bool,hipMemcpyHostToDevice);
cudaCheckErrors("Failed to move data to boolean adj matrix");
delete(host_bool_matrix);
return 1;
}
int initializeBuffer(int* &buffer){
//buffer size
int* host_bool_buffer= new int[ADJ_MATRIX_DIM*ADJ_MATRIX_DIM*MAXHOPS];
//
for(int k=0;k<MAXHOPS;k++){
for(int i=0;i<ADJ_MATRIX_DIM;i++){
for(int j=0;j<ADJ_MATRIX_DIM;j++){
host_bool_buffer[k*ADJ_MATRIX_DIM*ADJ_MATRIX_DIM+ i*ADJ_MATRIX_DIM+j] = false;
}
}
}
size_t size_bool =MAXHOPS*ADJ_MATRIX_DIM*ADJ_MATRIX_DIM*sizeof(int);
hipMalloc((void**)&buffer,size_bool);
cudaCheckErrors("Failed to allocate memory to boolean buffer");
hipMemcpy(buffer,host_bool_buffer,size_bool,hipMemcpyHostToDevice);
cudaCheckErrors("Failed to move data to boolean buffer");
delete(host_bool_buffer);
return 1;
}
__global__ void testBuffer(int* buffer,int* result, int size){
int id =blockIdx.x*blockDim.x+threadIdx.x;
if(id<size){
if(buffer[id])
result[id] = 1234345;
else
result[id] = 0;
}
}
__global__ void testMatrix(int** devVector,int size, int* result, Flight* flights){
//block dimension is the number of threads in a block. since blockid is zero based multiplying gets you somewhre close.
//to gt the correct position all u have to do then is to add the thread id
int i = blockIdx.x*blockDim.x+threadIdx.x;
result[i] = 0;
if(i<size*size && devVector[i]!= NULL )
result[i] = flights[devVector[i][0]].source;
}
__global__ void testMatrixBoolean(int* devMatrixBoolean,int size, int* result){
int i = blockIdx.x*blockDim.x+threadIdx.x;
result[i] = 0;
//put 1 if a manhattan exists for the particular position
if(i<size*size && devMatrixBoolean[i])
result[i] = 1;
}
//initialize buffer to end of array value so that as values are filled the array size will change, but will still be
//indicated by the first end of array value
//__global__ void initializeBuffer(bool* buffer, int size){
// int id = blockIdx.x*blockDim.x+threadIdx.x;
// if(id<size)
// buffer[id] = false;
//}
//give enough threads to span the source row
//maximum id should be adj_matrix_dimension
__global__ void firstExpansion(int* buffer, int*dev_boolean_matrix, int source){
int id = blockIdx.x*blockDim.x+threadIdx.x;
//the source row.
//if(id<DEV_ADJ_MATRIX_DIM*DEV_ADJ_MATRIX_DIM){
// //if(dev_adj_matrix[DEV_ADJ_MATRIX_DIM*(source-1)+id]!=NULL){
// // //set source to the precedant node list of each relevant airport
// // buffer[id*BUFFER_LENGTH] = source;
// //}
//}
}
//max id is number of airports
__global__ void expansion(int* dev_buffer1,int* boolean_matrix, int* dev_source_vector,int matrix_dimension){
int id = blockIdx.x*blockDim.x+threadIdx.x;
int row = (int) floor((double)id/matrix_dimension);
int column = id%matrix_dimension;
for(int k=0;k<MAXHOPS;k++){
if(row<matrix_dimension && column<matrix_dimension ){
//for the source row if the matrix row column position has a manhattan set the buffer position to true
dev_buffer1[k*matrix_dimension*matrix_dimension+id] = (dev_source_vector[row] && boolean_matrix[id]);
}
__syncthreads();
//set the 'next source vector' positions to zero by the first of each row
if(row<matrix_dimension && column<matrix_dimension&& column==0) dev_source_vector[row]= 0;
__syncthreads();
//if the relevant cell in the frame has been set, contribute to making sure the relevant cell in the 'next source vector' is set to 1
if((row<matrix_dimension && column<matrix_dimension) && dev_buffer1[k*matrix_dimension*matrix_dimension+id]){
dev_source_vector[column] = 1;
}
__syncthreads();
}
}
//__global__ void copyNextSource(bool* next_source_array, bool* current_array, int size){
// int id = blockDim.x*blockIdx.x+threadIdx.x;
// if(id<size)
// cudaMemcpy
//}
int main(int argc)
{
readAirports();
readFlights();
int source = 344;
int destination = 190;
Flight* dev_flight_list;
int** dev_adj_list;
int* dev_adj_matrix_boolean;
int** host_adj_vector;
int* dev_level1;
int* dev_level2;
int* frames;
//boolean array containing source airports in the next expansion
int* dev_next_source_array;
size_t matrixSize = ADJ_MATRIX_DIM*ADJ_MATRIX_DIM*sizeof(int);
size_t bufferSize = ADJ_MATRIX_DIM*ADJ_MATRIX_DIM*sizeof(int);
//add the flight array to GPU memory
cout<<"Initializing Flights"<<endl;
initializeFlightListInDevice(dev_flight_list);
cout<<"finished initializing FLights"<<endl;
//add the adjacency matrix with manhattans to GPU
cout<<"Initializing Matrix"<<endl;
initializeAdjMatrixInDevice(dev_adj_list,host_adj_vector);
cout<<"Finished with adj matrix"<<endl;
//add the boolean adjacency matrix (without manhattans) to GPU
cout<<"Initializing Boolean Matrix"<<endl;
initializeBooleanMatrixInDevice(dev_adj_matrix_boolean);
cout<<"Finished with boolean matrix"<<endl;
//allocate memory for the 'next source array' in device
hipMalloc((void**)&dev_next_source_array,ADJ_MATRIX_DIM*sizeof(int));
cudaCheckErrors("Failed to allocate memory to next source list");
int* source_vector = new int [ADJ_MATRIX_DIM];
//initialize the 'next source vector' with the source row of the adjacency matrix
for(int i=0;i<ADJ_MATRIX_DIM;i++){
source_vector[i] = AdjMatrix[source][i].size()!=0;
}
//intialize 'next source array' in device
hipMemcpy(dev_next_source_array,source_vector,ADJ_MATRIX_DIM*sizeof(int),hipMemcpyHostToDevice);
cudaCheckErrors("Failed to move data to next source list");
delete(source_vector);
//////////////////////initialize the buffers for all the levels/////////////////
cout<<"initializing Buffers"<<endl;
initializeBuffer(dev_level1);
//initializeBuffer(dev_level2);
cout<<"initialized buffers"<<endl;
///////////////////////////////////////Interations///////////////////////////////////////
int numBlocks = ceil((double)ADJ_MATRIX_DIM*ADJ_MATRIX_DIM/BLOCK_LENGTH);
ofstream myFile;
myFile.open("nextSource.txt");
int* myArray = (int*) malloc(ADJ_MATRIX_DIM*sizeof(int));
hipMemcpy(myArray,dev_next_source_array,ADJ_MATRIX_DIM*sizeof(int),hipMemcpyDeviceToHost);
cudaCheckErrors("Failed to copy data from buffer array to host array");
for(int i=0;i<ADJ_MATRIX_DIM;i++){
//if(myArray[i]!= NULL)
myFile<<myArray[i];
}
myFile<<endl<<endl;
free(myArray);
cout<<"moving into first expansion"<<endl;
ofstream myFile2;
myFile2.open("Frame1.txt");
int* myArray2 = (int*)malloc(MAXHOPS*ADJ_MATRIX_DIM*ADJ_MATRIX_DIM*sizeof(int));
expansion<<<numBlocks,BLOCK_LENGTH>>>(dev_level1,dev_adj_matrix_boolean,dev_next_source_array,ADJ_MATRIX_DIM);
hipDeviceSynchronize();
cudaCheckErrors("Error occured in expansion");
cout<<"finished expansion"<<endl;
hipMemcpy(myArray2,dev_level1,MAXHOPS*ADJ_MATRIX_DIM*ADJ_MATRIX_DIM*sizeof(int),hipMemcpyDeviceToHost);
cudaCheckErrors("Failed to retrieve memory from first frame");
for(int j=0;j<MAXHOPS;j++){
for(int i=0;i<ADJ_MATRIX_DIM*ADJ_MATRIX_DIM;i++){
//if(myArray[i]!= NULL)
myFile2<<myArray2[j*ADJ_MATRIX_DIM*ADJ_MATRIX_DIM+i];
}
myFile2<<endl;
}
myFile2<<endl<<endl;
myFile2.close();
free(myArray2);
int* myArray1 = (int*)malloc(ADJ_MATRIX_DIM*sizeof(int));
/* expansion<<<numBlocks,BLOCK_LENGTH>>>(dev_level1,dev_adj_matrix_boolean,dev_next_source_array,ADJ_MATRIX_DIM);
cudaThreadSynchronize();
cudaCheckErrors("Error occured in expansion");
cout<<"finished expansion"<<endl;*/
hipMemcpy(myArray1,dev_next_source_array,ADJ_MATRIX_DIM*sizeof(int),hipMemcpyDeviceToHost);
cudaCheckErrors("Failed to retrieve memory from buffer array 1.2 to host");
for(int i=0;i<ADJ_MATRIX_DIM;i++){
//if(myArray[i]!= NULL)
myFile<<myArray1[i];
}
myFile<<endl<<endl;
free(myArray1);
myFile.close();
//cudaFree(dev_next_source_array);
hipFree(dev_level1);
hipFree(dev_level2);
hipFree(dev_flight_list);
//for(int i=0;i<ADJ_MATRIX_DIM*ADJ_MATRIX_DIM;i++){
// //cout<<i<<endl;
// if(host_adj_vector[i] !=NULL)
// cudaFree(host_adj_vector[i]);
//}
hipFree(dev_adj_list);
free(host_adj_vector);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <iostream>
#include <fstream>
#include <string>
#include <vector>
#include <algorithm>
#include <time.h>
#include <cmath>
#include <limits.h>
#define MAXHOPS 4
#define MAX_WAITING_TIME 420
#define BLOCK_LENGTH 512
#define END_OF_ARRAY 2147483647
#define BUFFER_LENGTH 50
#define AIRPORT_PATH "C:/Users/acer/Desktop/Semester 7/Project/AA_airports.txt" //"C:/Users/acer/Desktop/Semester 7/Project/Data/AA_airports.txt"
#define FLIGHT_PATH "C:/Users/acer/Desktop/Semester 7/Project/AA_data1.txt" //"C:/Users/acer/Desktop/Semester 7/Project/Data/OAGX_data_num_1.txt"
bool bool1 = true;
bool bool2 = false;
using namespace std;
hipError_t addWithCuda(int *c, const int *a, const int *b, size_t size);
// for cuda error checking
#define cudaCheckErrors(msg) \
do { \
hipError_t __err = hipGetLastError(); \
if (__err != hipSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, hipGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
return 1; \
} \
} while (0)
int ADJ_MATRIX_DIM;
__device__ int DEV_ADJ_MATRIX_DIM;
// FYP_BFS.cpp : Defines the entry point for the console application.
//
///////////////////Global Variables///////////////////
struct Flight{
int flightNumber;
int source;
int destination;
int arrivalTime;
int departureTime;
int price;
string code;
};
vector<string> Airport_List;
vector<Flight> Flight_List;
vector<int>** AdjMatrix;
//////////////////////////////////////////////////////
//////////////////Data Read///////////////////////////
int readAirports(){
ifstream myFile;
myFile.open(AIRPORT_PATH);
int numberOfAirports=0;
if(myFile.is_open()){
string line;
cout<<"Reading Airports"<<endl;
while(myFile.good()){
//------------------------------changed-------------------//
//myFile.ignore(256,' ');
string s;
myFile>>s;
Airport_List.push_back(s);
numberOfAirports++;
}
}
myFile.close();
ADJ_MATRIX_DIM = Airport_List.size();
//cudaMemcpy(DEV_ADJ_MATRIX_DIM,&ADJ_MATRIX_DIM,sizeof(int),cudaMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(DEV_ADJ_MATRIX_DIM),&ADJ_MATRIX_DIM,sizeof(int),0,hipMemcpyHostToDevice);
cudaCheckErrors("Error copying adj matrix dim to device");
cout<<Airport_List.size()<<" Airports Found"<<endl;
return 1;
}
void readFlights(){
//this is a bloody array of pointers
AdjMatrix = new vector<int>*[Airport_List.size()];
for(int i=0;i<Airport_List.size();i++){
//thisi is a bloody array of vectors
AdjMatrix[i] = new vector<int>[Airport_List.size()];
}
ifstream myFile;
myFile.open(FLIGHT_PATH);
int numOfFlights = 0;
if(myFile.is_open()){
string line;
Flight tempFlight;
while(myFile.good()){
//---------------------------------------changed----------------------------------------//
tempFlight.flightNumber= numOfFlights;
/*myFile>>tempFlight.source;
myFile>>tempFlight.destination;
myFile>>tempFlight.departureTime;
myFile>>tempFlight.arrivalTime;
if(tempFlight.arrivalTime<tempFlight.departureTime) tempFlight.arrivalTime+=10080;
myFile>>tempFlight.price;
myFile>>tempFlight.code;*/
myFile>>tempFlight.source;
myFile>>tempFlight.destination;
myFile>>tempFlight.price;
myFile>>tempFlight.departureTime;
myFile>>tempFlight.arrivalTime;
if(tempFlight.arrivalTime<tempFlight.departureTime) tempFlight.arrivalTime+=10080;
myFile>>tempFlight.code;
//add this flight to the adjmatrix;
Flight_List.push_back(tempFlight);
AdjMatrix[tempFlight.source][tempFlight.destination].push_back(tempFlight.flightNumber);
numOfFlights++;
if(numOfFlights%10000==0) cout<<"*";
}
cout<<endl;
}
myFile.close();
cout<<Flight_List.size()<<" Flights Found"<<endl;
}
/////////////////////////////////////////////////////////////////////////////////////
struct route{
vector<int> flights;
int weight;
};
int initializeFlightListInDevice(Flight* &dev_flight_list){
//allocate space for the flight list in cuda
hipMalloc((void**)&dev_flight_list, Flight_List.size()*sizeof(Flight));
cudaCheckErrors("Failed to allocate memory to flight list");
hipMemcpy(dev_flight_list,&Flight_List[0],Flight_List.size()*sizeof(Flight),hipMemcpyHostToDevice);
cudaCheckErrors("Failed to copy flight list");
return 1;
}
int initializeAdjMatrixInDevice(int** &dev_adj_list, int ** &host_adj_vector){
size_t size = ADJ_MATRIX_DIM*ADJ_MATRIX_DIM*sizeof(int*);
//the vector in host that records the pointers in device memory
host_adj_vector = (int **)malloc(size);
//i indicates rows and j indicates columns of the adjacency matrix
//allocate device memory for the boolean vector
//allocate memory for each manhattan in device and store the pointer in memory
for(int i=0;i<ADJ_MATRIX_DIM;i++){
for(int j=0;j<ADJ_MATRIX_DIM;j++){
hipMalloc((void **)&host_adj_vector[i*ADJ_MATRIX_DIM+j],AdjMatrix[i][j].size()*sizeof(int));
cudaCheckErrors("Failed to allocate memory to airport list manhattan:");
hipMemcpy(host_adj_vector[i*ADJ_MATRIX_DIM+j],&AdjMatrix[i][j][0],AdjMatrix[i][j].size()*sizeof(int),hipMemcpyHostToDevice);
cudaCheckErrors("Failed to copy data to airport list manhattan:");
}
if(i%100==0) cout<<"&";
}
cout<<endl;
hipMalloc((void***)&dev_adj_list,size);
cudaCheckErrors("Failed to allocate memory to pointer list in device");
hipMemcpy(dev_adj_list,host_adj_vector,size,hipMemcpyHostToDevice);
cudaCheckErrors("Failed to allocate data to pointer list in device");
return 1;
}
int initializeBooleanMatrixInDevice(int* &boolean_matrix){
int* host_bool_matrix= new int[ADJ_MATRIX_DIM*ADJ_MATRIX_DIM];
for(int i=0;i<ADJ_MATRIX_DIM;i++){
for(int j=0;j<ADJ_MATRIX_DIM;j++){
host_bool_matrix[i*ADJ_MATRIX_DIM+j] = (AdjMatrix[i][j].size() !=0);
}
}
size_t size_bool =ADJ_MATRIX_DIM*ADJ_MATRIX_DIM*sizeof(int);
hipMalloc((void**)&boolean_matrix,size_bool);
cudaCheckErrors("Failed to allocate memory to boolean adj matrix");
hipMemcpy(boolean_matrix,host_bool_matrix,size_bool,hipMemcpyHostToDevice);
cudaCheckErrors("Failed to move data to boolean adj matrix");
delete(host_bool_matrix);
return 1;
}
int initializeBuffer(int* &buffer){
//buffer size
int* host_bool_buffer= new int[ADJ_MATRIX_DIM*ADJ_MATRIX_DIM*MAXHOPS];
//
for(int k=0;k<MAXHOPS;k++){
for(int i=0;i<ADJ_MATRIX_DIM;i++){
for(int j=0;j<ADJ_MATRIX_DIM;j++){
host_bool_buffer[k*ADJ_MATRIX_DIM*ADJ_MATRIX_DIM+ i*ADJ_MATRIX_DIM+j] = false;
}
}
}
size_t size_bool =MAXHOPS*ADJ_MATRIX_DIM*ADJ_MATRIX_DIM*sizeof(int);
hipMalloc((void**)&buffer,size_bool);
cudaCheckErrors("Failed to allocate memory to boolean buffer");
hipMemcpy(buffer,host_bool_buffer,size_bool,hipMemcpyHostToDevice);
cudaCheckErrors("Failed to move data to boolean buffer");
delete(host_bool_buffer);
return 1;
}
__global__ void testBuffer(int* buffer,int* result, int size){
int id =blockIdx.x*blockDim.x+threadIdx.x;
if(id<size){
if(buffer[id])
result[id] = 1234345;
else
result[id] = 0;
}
}
__global__ void testMatrix(int** devVector,int size, int* result, Flight* flights){
//block dimension is the number of threads in a block. since blockid is zero based multiplying gets you somewhre close.
//to gt the correct position all u have to do then is to add the thread id
int i = blockIdx.x*blockDim.x+threadIdx.x;
result[i] = 0;
if(i<size*size && devVector[i]!= NULL )
result[i] = flights[devVector[i][0]].source;
}
__global__ void testMatrixBoolean(int* devMatrixBoolean,int size, int* result){
int i = blockIdx.x*blockDim.x+threadIdx.x;
result[i] = 0;
//put 1 if a manhattan exists for the particular position
if(i<size*size && devMatrixBoolean[i])
result[i] = 1;
}
//initialize buffer to end of array value so that as values are filled the array size will change, but will still be
//indicated by the first end of array value
//__global__ void initializeBuffer(bool* buffer, int size){
// int id = blockIdx.x*blockDim.x+threadIdx.x;
// if(id<size)
// buffer[id] = false;
//}
//give enough threads to span the source row
//maximum id should be adj_matrix_dimension
__global__ void firstExpansion(int* buffer, int*dev_boolean_matrix, int source){
int id = blockIdx.x*blockDim.x+threadIdx.x;
//the source row.
//if(id<DEV_ADJ_MATRIX_DIM*DEV_ADJ_MATRIX_DIM){
// //if(dev_adj_matrix[DEV_ADJ_MATRIX_DIM*(source-1)+id]!=NULL){
// // //set source to the precedant node list of each relevant airport
// // buffer[id*BUFFER_LENGTH] = source;
// //}
//}
}
//max id is number of airports
__global__ void expansion(int* dev_buffer1,int* boolean_matrix, int* dev_source_vector,int matrix_dimension){
int id = blockIdx.x*blockDim.x+threadIdx.x;
int row = (int) floor((double)id/matrix_dimension);
int column = id%matrix_dimension;
for(int k=0;k<MAXHOPS;k++){
if(row<matrix_dimension && column<matrix_dimension ){
//for the source row if the matrix row column position has a manhattan set the buffer position to true
dev_buffer1[k*matrix_dimension*matrix_dimension+id] = (dev_source_vector[row] && boolean_matrix[id]);
}
__syncthreads();
//set the 'next source vector' positions to zero by the first of each row
if(row<matrix_dimension && column<matrix_dimension&& column==0) dev_source_vector[row]= 0;
__syncthreads();
//if the relevant cell in the frame has been set, contribute to making sure the relevant cell in the 'next source vector' is set to 1
if((row<matrix_dimension && column<matrix_dimension) && dev_buffer1[k*matrix_dimension*matrix_dimension+id]){
dev_source_vector[column] = 1;
}
__syncthreads();
}
}
//__global__ void copyNextSource(bool* next_source_array, bool* current_array, int size){
// int id = blockDim.x*blockIdx.x+threadIdx.x;
// if(id<size)
// cudaMemcpy
//}
int main(int argc)
{
readAirports();
readFlights();
int source = 344;
int destination = 190;
Flight* dev_flight_list;
int** dev_adj_list;
int* dev_adj_matrix_boolean;
int** host_adj_vector;
int* dev_level1;
int* dev_level2;
int* frames;
//boolean array containing source airports in the next expansion
int* dev_next_source_array;
size_t matrixSize = ADJ_MATRIX_DIM*ADJ_MATRIX_DIM*sizeof(int);
size_t bufferSize = ADJ_MATRIX_DIM*ADJ_MATRIX_DIM*sizeof(int);
//add the flight array to GPU memory
cout<<"Initializing Flights"<<endl;
initializeFlightListInDevice(dev_flight_list);
cout<<"finished initializing FLights"<<endl;
//add the adjacency matrix with manhattans to GPU
cout<<"Initializing Matrix"<<endl;
initializeAdjMatrixInDevice(dev_adj_list,host_adj_vector);
cout<<"Finished with adj matrix"<<endl;
//add the boolean adjacency matrix (without manhattans) to GPU
cout<<"Initializing Boolean Matrix"<<endl;
initializeBooleanMatrixInDevice(dev_adj_matrix_boolean);
cout<<"Finished with boolean matrix"<<endl;
//allocate memory for the 'next source array' in device
hipMalloc((void**)&dev_next_source_array,ADJ_MATRIX_DIM*sizeof(int));
cudaCheckErrors("Failed to allocate memory to next source list");
int* source_vector = new int [ADJ_MATRIX_DIM];
//initialize the 'next source vector' with the source row of the adjacency matrix
for(int i=0;i<ADJ_MATRIX_DIM;i++){
source_vector[i] = AdjMatrix[source][i].size()!=0;
}
//intialize 'next source array' in device
hipMemcpy(dev_next_source_array,source_vector,ADJ_MATRIX_DIM*sizeof(int),hipMemcpyHostToDevice);
cudaCheckErrors("Failed to move data to next source list");
delete(source_vector);
//////////////////////initialize the buffers for all the levels/////////////////
cout<<"initializing Buffers"<<endl;
initializeBuffer(dev_level1);
//initializeBuffer(dev_level2);
cout<<"initialized buffers"<<endl;
///////////////////////////////////////Interations///////////////////////////////////////
int numBlocks = ceil((double)ADJ_MATRIX_DIM*ADJ_MATRIX_DIM/BLOCK_LENGTH);
ofstream myFile;
myFile.open("nextSource.txt");
int* myArray = (int*) malloc(ADJ_MATRIX_DIM*sizeof(int));
hipMemcpy(myArray,dev_next_source_array,ADJ_MATRIX_DIM*sizeof(int),hipMemcpyDeviceToHost);
cudaCheckErrors("Failed to copy data from buffer array to host array");
for(int i=0;i<ADJ_MATRIX_DIM;i++){
//if(myArray[i]!= NULL)
myFile<<myArray[i];
}
myFile<<endl<<endl;
free(myArray);
cout<<"moving into first expansion"<<endl;
ofstream myFile2;
myFile2.open("Frame1.txt");
int* myArray2 = (int*)malloc(MAXHOPS*ADJ_MATRIX_DIM*ADJ_MATRIX_DIM*sizeof(int));
expansion<<<numBlocks,BLOCK_LENGTH>>>(dev_level1,dev_adj_matrix_boolean,dev_next_source_array,ADJ_MATRIX_DIM);
hipDeviceSynchronize();
cudaCheckErrors("Error occured in expansion");
cout<<"finished expansion"<<endl;
hipMemcpy(myArray2,dev_level1,MAXHOPS*ADJ_MATRIX_DIM*ADJ_MATRIX_DIM*sizeof(int),hipMemcpyDeviceToHost);
cudaCheckErrors("Failed to retrieve memory from first frame");
for(int j=0;j<MAXHOPS;j++){
for(int i=0;i<ADJ_MATRIX_DIM*ADJ_MATRIX_DIM;i++){
//if(myArray[i]!= NULL)
myFile2<<myArray2[j*ADJ_MATRIX_DIM*ADJ_MATRIX_DIM+i];
}
myFile2<<endl;
}
myFile2<<endl<<endl;
myFile2.close();
free(myArray2);
int* myArray1 = (int*)malloc(ADJ_MATRIX_DIM*sizeof(int));
/* expansion<<<numBlocks,BLOCK_LENGTH>>>(dev_level1,dev_adj_matrix_boolean,dev_next_source_array,ADJ_MATRIX_DIM);
cudaThreadSynchronize();
cudaCheckErrors("Error occured in expansion");
cout<<"finished expansion"<<endl;*/
hipMemcpy(myArray1,dev_next_source_array,ADJ_MATRIX_DIM*sizeof(int),hipMemcpyDeviceToHost);
cudaCheckErrors("Failed to retrieve memory from buffer array 1.2 to host");
for(int i=0;i<ADJ_MATRIX_DIM;i++){
//if(myArray[i]!= NULL)
myFile<<myArray1[i];
}
myFile<<endl<<endl;
free(myArray1);
myFile.close();
//cudaFree(dev_next_source_array);
hipFree(dev_level1);
hipFree(dev_level2);
hipFree(dev_flight_list);
//for(int i=0;i<ADJ_MATRIX_DIM*ADJ_MATRIX_DIM;i++){
// //cout<<i<<endl;
// if(host_adj_vector[i] !=NULL)
// cudaFree(host_adj_vector[i]);
//}
hipFree(dev_adj_list);
free(host_adj_vector);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10testBufferPiS_i
.globl _Z10testBufferPiS_i
.p2align 8
.type _Z10testBufferPiS_i,@function
_Z10testBufferPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 0, v2
v_cndmask_b32_e64 v2, 0x12d5a9, 0, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10testBufferPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10testBufferPiS_i, .Lfunc_end0-_Z10testBufferPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10testMatrixPPiiS_P6Flight
.globl _Z10testMatrixPPiiS_P6Flight
.p2align 8
.type _Z10testMatrixPPiiS_P6Flight,@function
_Z10testMatrixPPiiS_P6Flight:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s5, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x10
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_mul_i32 s5, s5, s5
v_mad_u64_u32 v[2:3], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_mov_b32 s2, exec_lo
global_store_b32 v[0:1], v4, off
v_cmpx_gt_i32_e64 s5, v2
s_cbranch_execz .LBB1_3
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, 0, v[2:3]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_3
flat_load_b32 v4, v[2:3]
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mad_i64_i32 v[2:3], null, v4, 56, s[0:1]
global_load_b32 v2, v[2:3], off offset:4
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10testMatrixPPiiS_P6Flight
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10testMatrixPPiiS_P6Flight, .Lfunc_end1-_Z10testMatrixPPiiS_P6Flight
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z17testMatrixBooleanPiiS_
.globl _Z17testMatrixBooleanPiiS_
.p2align 8
.type _Z17testMatrixBooleanPiiS_,@function
_Z17testMatrixBooleanPiiS_:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s5, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_mul_i32 s5, s5, s5
v_mad_u64_u32 v[4:5], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[2:3], 2, v[4:5]
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
s_mov_b32 s2, exec_lo
global_store_b32 v[0:1], v5, off
v_cmpx_gt_i32_e64 s5, v4
s_cbranch_execz .LBB2_3
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_3
v_mov_b32_e32 v2, 1
global_store_b32 v[0:1], v2, off
.LBB2_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17testMatrixBooleanPiiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z17testMatrixBooleanPiiS_, .Lfunc_end2-_Z17testMatrixBooleanPiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14firstExpansionPiS_i
.globl _Z14firstExpansionPiS_i
.p2align 8
.type _Z14firstExpansionPiS_i,@function
_Z14firstExpansionPiS_i:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14firstExpansionPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z14firstExpansionPiS_i, .Lfunc_end3-_Z14firstExpansionPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9expansionPiS_S_i
.globl _Z9expansionPiS_S_i
.p2align 8
.type _Z9expansionPiS_S_i,@function
_Z9expansionPiS_S_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cvt_f64_i32_e32 v[2:3], s8
s_ashr_i32 s2, s8, 31
s_add_i32 s3, s8, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_xor_b32 s2, s3, s2
v_cvt_f64_i32_e32 v[4:5], v1
v_cvt_f32_u32_e32 v0, s2
s_sub_i32 s3, 0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_iflag_f32_e32 v0, v0
v_div_scale_f64 v[6:7], null, v[2:3], v[2:3], v[4:5]
v_div_scale_f64 v[12:13], vcc_lo, v[4:5], v[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[10:11], v[12:13], v[8:9]
v_fma_f64 v[6:7], -v[6:7], v[10:11], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[10:11]
v_div_fixup_f64 v[2:3], v[6:7], v[2:3], v[4:5]
v_ashrrev_i32_e32 v6, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v0, 0x4f7ffffe, v0 :: v_dual_add_nc_u32 v5, v1, v6
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v5, v5, v6
v_mul_lo_u32 v4, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v0, v4
v_add_nc_u32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v0, v5, v0
v_floor_f64_e32 v[2:3], v[2:3]
v_mul_lo_u32 v0, v0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v5, v0
v_cmp_le_u32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_i32_f64_e32 v5, v[2:3]
v_subrev_nc_u32_e32 v2, s2, v0
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s2, v0
v_cmp_le_u32_e32 vcc_lo, s2, v0
s_load_b64 s[2:3], s[0:1], 0x10
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v0, v0, v6
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v7, v0, v6
v_mov_b32_e32 v0, 0
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
v_ashrrev_i32_e32 v8, 31, v7
v_cmp_eq_u32_e64 s0, 0, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[8:9], 2, v[7:8]
v_ashrrev_i32_e32 v6, 31, v5
v_max_i32_e32 v2, -1, v5
v_lshlrev_b64 v[10:11], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_u32 v5, vcc_lo, s2, v8
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v9, vcc_lo
v_mov_b32_e32 v9, 1
v_cmp_gt_i32_e32 vcc_lo, s8, v2
v_add_co_u32 v7, s1, s2, v10
v_add_co_ci_u32_e64 v8, s1, s3, v11, s1
s_and_b32 s1, vcc_lo, s0
s_mul_i32 s2, s8, s8
s_mov_b32 s3, 4
s_branch .LBB4_2
.LBB4_1:
s_or_b32 exec_lo, exec_lo, s6
v_add_nc_u32_e32 v1, s2, v1
s_add_i32 s3, s3, -1
s_waitcnt_vscnt null, 0x0
s_cmp_eq_u32 s3, 0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB4_11
.LBB4_2:
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB4_6
global_load_b32 v2, v[7:8], off
s_mov_b32 s7, 0
s_mov_b32 s8, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e32 0, v2
s_cbranch_execz .LBB4_5
global_load_b32 v2, v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e64 s0, 0, v2
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s7, s0, exec_lo
.LBB4_5:
s_or_b32 exec_lo, exec_lo, s8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[10:11], 2, v[1:2]
v_cndmask_b32_e64 v2, 0, 1, s7
v_add_co_u32 v10, s0, s4, v10
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v11, s0, s5, v11, s0
global_store_b32 v[10:11], v2, off
.LBB4_6:
s_or_b32 exec_lo, exec_lo, s6
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB4_8
global_store_b32 v[7:8], v0, off
.LBB4_8:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB4_1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], 2, v[1:2]
v_add_co_u32 v10, s0, s4, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v11, s0, s5, v11, s0
global_load_b32 v2, v[10:11], off
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e64 s0, 0, v2
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB4_1
global_store_b32 v[5:6], v9, off
s_branch .LBB4_1
.LBB4_11:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9expansionPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end4:
.size _Z9expansionPiS_S_i, .Lfunc_end4-_Z9expansionPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected DEV_ADJ_MATRIX_DIM
.type DEV_ADJ_MATRIX_DIM,@object
.section .bss,"aw",@nobits
.globl DEV_ADJ_MATRIX_DIM
.p2align 2, 0x0
DEV_ADJ_MATRIX_DIM:
.long 0
.size DEV_ADJ_MATRIX_DIM, 4
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym DEV_ADJ_MATRIX_DIM
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10testBufferPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10testBufferPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10testMatrixPPiiS_P6Flight
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10testMatrixPPiiS_P6Flight.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17testMatrixBooleanPiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17testMatrixBooleanPiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14firstExpansionPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z14firstExpansionPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9expansionPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9expansionPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <fstream>
#include <vector>
#include <sstream>
extern int solveMatrix(double *A_in, int n, double *b_in, double *x_out);
using namespace std;
int main(int argc, char *argv[]){
ifstream mtx(argv[1]);
ifstream vec(argv[2]);
vector<double> A;
vector<double> b;
string line;
int n=0;
double token;
while(getline(mtx,line)){
stringstream input;
input.str(line);
int count = 0;
while(input>>token){
A.push_back(token);
count++;
}
if(n==0) n=count;
}
while(vec>>token){
b.push_back(token);
}
for(int i=0;i<n;i++){
for(int j=0;j<n;j++){
cout<<A[4*i+j]<<"\t";
}
cout<<endl;
}
cout<<endl;
for(int i=0;i<n;i++){
cout<<b[i]<<endl;
}
cout<<endl;
solveMatrix(&A[0], n, &b[0], &b[0]);
for(int i=0;i<n;i++){
cout<<b[i]<<endl;
}
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <fstream>
#include <vector>
#include <sstream>
extern int solveMatrix(double *A_in, int n, double *b_in, double *x_out);
using namespace std;
int main(int argc, char *argv[]){
ifstream mtx(argv[1]);
ifstream vec(argv[2]);
vector<double> A;
vector<double> b;
string line;
int n=0;
double token;
while(getline(mtx,line)){
stringstream input;
input.str(line);
int count = 0;
while(input>>token){
A.push_back(token);
count++;
}
if(n==0) n=count;
}
while(vec>>token){
b.push_back(token);
}
for(int i=0;i<n;i++){
for(int j=0;j<n;j++){
cout<<A[4*i+j]<<"\t";
}
cout<<endl;
}
cout<<endl;
for(int i=0;i<n;i++){
cout<<b[i]<<endl;
}
cout<<endl;
solveMatrix(&A[0], n, &b[0], &b[0]);
for(int i=0;i<n;i++){
cout<<b[i]<<endl;
}
return 0;
} | .file "tmpxft_00189b59_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4234:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4234:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4257:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4257:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIdSaIdEED2Ev,"axG",@progbits,_ZNSt6vectorIdSaIdEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIdSaIdEED2Ev
.type _ZNSt6vectorIdSaIdEED2Ev, @function
_ZNSt6vectorIdSaIdEED2Ev:
.LFB4590:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L8
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L8:
ret
.cfi_endproc
.LFE4590:
.size _ZNSt6vectorIdSaIdEED2Ev, .-_ZNSt6vectorIdSaIdEED2Ev
.weak _ZNSt6vectorIdSaIdEED1Ev
.set _ZNSt6vectorIdSaIdEED1Ev,_ZNSt6vectorIdSaIdEED2Ev
.section .rodata._ZNSt6vectorIdSaIdEE17_M_realloc_insertIJRKdEEEvN9__gnu_cxx17__normal_iteratorIPdS1_EEDpOT_.str1.1,"aMS",@progbits,1
.LC0:
.string "vector::_M_realloc_insert"
.section .text._ZNSt6vectorIdSaIdEE17_M_realloc_insertIJRKdEEEvN9__gnu_cxx17__normal_iteratorIPdS1_EEDpOT_,"axG",@progbits,_ZNSt6vectorIdSaIdEE17_M_realloc_insertIJRKdEEEvN9__gnu_cxx17__normal_iteratorIPdS1_EEDpOT_,comdat
.align 2
.weak _ZNSt6vectorIdSaIdEE17_M_realloc_insertIJRKdEEEvN9__gnu_cxx17__normal_iteratorIPdS1_EEDpOT_
.type _ZNSt6vectorIdSaIdEE17_M_realloc_insertIJRKdEEEvN9__gnu_cxx17__normal_iteratorIPdS1_EEDpOT_, @function
_ZNSt6vectorIdSaIdEE17_M_realloc_insertIJRKdEEEvN9__gnu_cxx17__normal_iteratorIPdS1_EEDpOT_:
.LFB4808:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movq 8(%rdi), %rbp
movq (%rdi), %r13
movq %rbp, %rax
subq %r13, %rax
sarq $3, %rax
movabsq $1152921504606846975, %rdx
cmpq %rdx, %rax
je .L28
movq %rdi, %rbx
cmpq %r13, %rbp
movl $1, %edx
cmovne %rax, %rdx
addq %rdx, %rax
jc .L14
movabsq $1152921504606846975, %r14
cmpq %r14, %rax
cmovbe %rax, %r14
movq (%rsp), %r15
subq %r13, %r15
movl $0, %r12d
testq %rax, %rax
je .L15
jmp .L22
.L28:
leaq .LC0(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L29:
movq %r15, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memmove@PLT
leaq 8(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jg .L17
addq %rbp, %r15
movq 16(%rbx), %rsi
subq %r13, %rsi
jmp .L21
.L14:
movq (%rsp), %r15
subq %r13, %r15
movabsq $1152921504606846975, %r14
.L22:
leaq 0(,%r14,8), %rdi
call _Znwm@PLT
movq %rax, %r12
.L15:
movq 8(%rsp), %rax
movsd (%rax), %xmm0
movsd %xmm0, (%r12,%r15)
testq %r15, %r15
jg .L29
leaq 8(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jle .L19
.L17:
movq %rbp, %rdx
movq (%rsp), %rsi
movq %r15, %rdi
call memcpy@PLT
.L19:
addq %rbp, %r15
testq %r13, %r13
je .L20
movq 16(%rbx), %rsi
subq %r13, %rsi
.L21:
movq %r13, %rdi
call _ZdlPvm@PLT
.L20:
movq %r12, (%rbx)
movq %r15, 8(%rbx)
leaq (%r12,%r14,8), %rax
movq %rax, 16(%rbx)
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4808:
.size _ZNSt6vectorIdSaIdEE17_M_realloc_insertIJRKdEEEvN9__gnu_cxx17__normal_iteratorIPdS1_EEDpOT_, .-_ZNSt6vectorIdSaIdEE17_M_realloc_insertIJRKdEEEvN9__gnu_cxx17__normal_iteratorIPdS1_EEDpOT_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\t"
.text
.globl main
.type main, @function
main:
.LFB4220:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4220
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1592, %rsp
.cfi_def_cfa_offset 1648
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 1576(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rsi
leaq 528(%rsp), %rdi
movl $8, %edx
.LEHB0:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE0:
movq 16(%rbx), %rsi
leaq 1056(%rsp), %rdi
movl $8, %edx
.LEHB1:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE1:
movq $0, 32(%rsp)
movq $0, 40(%rsp)
movq $0, 48(%rsp)
movq $0, 64(%rsp)
movq $0, 72(%rsp)
movq $0, 80(%rsp)
leaq 112(%rsp), %rax
movq %rax, 96(%rsp)
movq $0, 104(%rsp)
movb $0, 112(%rsp)
movq 528(%rsp), %rax
movq -24(%rax), %rax
movq 768(%rsp,%rax), %rbx
testq %rbx, %rbx
je .L31
movl $0, %r15d
jmp .L32
.L98:
movq 32+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %r13
movq %r13, 144(%rsp)
movq -24(%r13), %rax
movq 40+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 144(%rsp,%rax)
movq 144(%rsp), %rax
movq -24(%rax), %rax
leaq 144(%rsp,%rax), %rdi
movl $0, %esi
.LEHB2:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE2:
movq 8+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %r14
movq %r14, 128(%rsp)
movq -24(%r14), %rax
movq 48+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 128(%rsp,%rax)
leaq 24+_ZTVNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 128(%rsp)
leaq 80(%rax), %rax
movq %rax, 256(%rsp)
leaq -40(%rax), %rax
movq %rax, 144(%rsp)
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 152(%rsp)
movq $0, 160(%rsp)
movq $0, 168(%rsp)
movq $0, 176(%rsp)
movq $0, 184(%rsp)
movq $0, 192(%rsp)
movq $0, 200(%rsp)
leaq 208(%rsp), %rdi
call _ZNSt6localeC1Ev@PLT
leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 152(%rsp)
movl $24, 216(%rsp)
leaq 240(%rsp), %rax
movq %rax, 224(%rsp)
movq $0, 232(%rsp)
movb $0, 240(%rsp)
leaq 152(%rsp), %rsi
leaq 256(%rsp), %rdi
.LEHB3:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE3:
jmp .L92
.L84:
endbr64
movq %rax, %rbx
movq %r12, 128(%rsp)
movq -24(%r12), %rax
movq 24+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 128(%rsp,%rax)
movq $0, 136(%rsp)
.L35:
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 256(%rsp)
leaq 256(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
.L38:
leaq 96(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 64(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
leaq 32(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
leaq 1056(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
.L74:
leaq 528(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 1576(%rsp), %rax
subq %fs:40, %rax
je .L75
call __stack_chk_fail@PLT
.L83:
endbr64
movq %rax, %rbx
leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 152(%rsp)
movq 224(%rsp), %rdi
leaq 240(%rsp), %rax
cmpq %rax, %rdi
je .L37
movq 240(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L37:
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 152(%rsp)
leaq 128(%rsp), %rbp
leaq 208(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
leaq 8+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rsi
movq %rbp, %rdi
call _ZNSdD2Ev@PLT
jmp .L35
.L82:
endbr64
movq %rax, %rbx
jmp .L35
.L92:
leaq 224(%rsp), %rdi
movq 104(%rsp), %r8
movq 96(%rsp), %rcx
movq 232(%rsp), %rdx
movl $0, %esi
.LEHB4:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm@PLT
movl $0, %ecx
testb $3, 216(%rsp)
je .L39
movq 232(%rsp), %rcx
.L39:
leaq 152(%rsp), %rdi
movl $0, %edx
movq 224(%rsp), %rsi
call _ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEE7_M_syncEPcmm@PLT
leaq 24(%rsp), %rbp
jmp .L40
.L41:
leaq 32(%rsp), %rdi
movq %rbp, %rdx
call _ZNSt6vectorIdSaIdEE17_M_realloc_insertIJRKdEEEvN9__gnu_cxx17__normal_iteratorIPdS1_EEDpOT_
jmp .L42
.L94:
movq (%rax), %rdx
movq -24(%rdx), %rdx
testb $5, 32(%rax,%rdx)
jne .L93
movq 40(%rsp), %rsi
cmpq 48(%rsp), %rsi
je .L41
movsd 24(%rsp), %xmm0
movsd %xmm0, (%rsi)
addq $8, %rsi
movq %rsi, 40(%rsp)
.L42:
addl $1, %ebx
.L40:
leaq 128(%rsp), %rdi
movq %rbp, %rsi
call _ZNSi10_M_extractIdEERSiRT_@PLT
.LEHE4:
jmp .L94
.L93:
testl %r15d, %r15d
cmove %ebx, %r15d
leaq 24+_ZTVNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 128(%rsp)
leaq 80(%rax), %rax
movq %rax, 256(%rsp)
leaq -40(%rax), %rax
movq %rax, 144(%rsp)
leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 152(%rsp)
movq 224(%rsp), %rdi
leaq 240(%rsp), %rax
cmpq %rax, %rdi
je .L45
movq 240(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L45:
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
movq %r14, 128(%rsp)
movq -24(%r14), %rax
movq 48+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 128(%rsp,%rax)
movq %r13, 144(%rsp)
movq -24(%r13), %rax
movq 40+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 144(%rsp,%rax)
movq %r12, 128(%rsp)
movq -24(%r12), %rax
movq 24+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 128(%rsp,%rax)
movq $0, 136(%rsp)
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 256(%rsp)
leaq 256(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 528(%rsp), %rax
movq -24(%rax), %rax
movq 768(%rsp,%rax), %rbx
testq %rbx, %rbx
je .L31
.L32:
cmpb $0, 56(%rbx)
je .L47
movzbl 67(%rbx), %edx
.L48:
movsbl %dl, %edx
leaq 96(%rsp), %rsi
leaq 528(%rsp), %rdi
.LEHB5:
call _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_@PLT
jmp .L95
.L31:
movq 1576(%rsp), %rax
subq %fs:40, %rax
jne .L96
call _ZSt16__throw_bad_castv@PLT
.L81:
endbr64
movq %rax, %rbx
jmp .L38
.L96:
call __stack_chk_fail@PLT
.L47:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
.LEHE5:
movl %eax, %edx
jmp .L48
.L95:
movq (%rax), %rdx
movq -24(%rdx), %rdx
movl 32(%rax,%rdx), %ebx
andl $5, %ebx
jne .L97
leaq 128(%rsp), %rbp
leaq 256(%rsp), %rdi
call _ZNSt8ios_baseC2Ev@PLT
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 256(%rsp)
movq $0, 472(%rsp)
movb $0, 480(%rsp)
movb $0, 481(%rsp)
movq $0, 488(%rsp)
movq $0, 496(%rsp)
movq $0, 504(%rsp)
movq $0, 512(%rsp)
movq 16+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %r12
movq %r12, 128(%rsp)
movq -24(%r12), %rax
movq 24+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 128(%rsp,%rax)
movq $0, 136(%rsp)
movq 128(%rsp), %rax
movq %rbp, %rdi
addq -24(%rax), %rdi
movl $0, %esi
.LEHB6:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE6:
jmp .L98
.L97:
leaq 24(%rsp), %rbx
jmp .L50
.L51:
leaq 64(%rsp), %rdi
movq %rbx, %rdx
.LEHB7:
call _ZNSt6vectorIdSaIdEE17_M_realloc_insertIJRKdEEEvN9__gnu_cxx17__normal_iteratorIPdS1_EEDpOT_
jmp .L50
.L100:
movq (%rax), %rdx
movq -24(%rdx), %rdx
testb $5, 32(%rax,%rdx)
jne .L99
movq 72(%rsp), %rsi
cmpq 80(%rsp), %rsi
je .L51
movsd 24(%rsp), %xmm0
movsd %xmm0, (%rsi)
addq $8, %rsi
movq %rsi, 72(%rsp)
.L50:
leaq 1056(%rsp), %rdi
movq %rbx, %rsi
call _ZNSi10_M_extractIdEERSiRT_@PLT
jmp .L100
.L99:
testl %r15d, %r15d
jle .L54
movslq %r15d, %rax
movq %rax, 8(%rsp)
leaq 0(,%rax,8), %r12
movl $0, %r14d
leaq _ZSt4cout(%rip), %rbp
leaq .LC1(%rip), %r13
jmp .L55
.L102:
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $8, %rbx
cmpq %rbx, %r12
je .L101
.L56:
movq 32(%rsp), %rax
movsd (%rax,%rbx), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
jmp .L102
.L101:
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L103
cmpb $0, 56(%rbx)
je .L59
movzbl 67(%rbx), %esi
.L60:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
jmp .L104
.L103:
movq 1576(%rsp), %rax
subq %fs:40, %rax
jne .L105
call _ZSt16__throw_bad_castv@PLT
.L105:
call __stack_chk_fail@PLT
.L59:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L60
.L104:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %r14
addq $32, %r12
movq 8(%rsp), %rax
cmpq %rax, %r14
je .L54
.L55:
movq %r14, %rbx
salq $5, %rbx
jmp .L56
.L54:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
testl %r15d, %r15d
jle .L61
movslq %r15d, %r12
salq $3, %r12
movl $0, %ebp
leaq _ZSt4cout(%rip), %r13
jmp .L66
.L109:
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .L106
cmpb $0, 56(%r14)
je .L64
movzbl 67(%r14), %esi
.L65:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L107
.L106:
movq 1576(%rsp), %rax
subq %fs:40, %rax
jne .L108
call _ZSt16__throw_bad_castv@PLT
.L108:
call __stack_chk_fail@PLT
.L64:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L65
.L107:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $8, %rbp
cmpq %rbp, %r12
je .L61
.L66:
movq 64(%rsp), %rax
movsd (%rax,%rbp), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
jmp .L109
.L61:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 64(%rsp), %rbx
movq %rbx, %rcx
movq %rbx, %rdx
movl %r15d, %esi
movq 32(%rsp), %rdi
call _Z11solveMatrixPdiS_S_@PLT
testl %r15d, %r15d
jle .L67
movq %rbx, %rbp
movslq %r15d, %rax
leaq (%rbx,%rax,8), %r12
leaq _ZSt4cout(%rip), %r13
jmp .L72
.L113:
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .L110
cmpb $0, 56(%r14)
je .L70
movzbl 67(%r14), %esi
.L71:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L111
.L110:
movq 1576(%rsp), %rax
subq %fs:40, %rax
jne .L112
call _ZSt16__throw_bad_castv@PLT
.L112:
call __stack_chk_fail@PLT
.L70:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L71
.L111:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $8, %rbp
cmpq %r12, %rbp
je .L67
.L72:
movsd 0(%rbp), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
.LEHE7:
jmp .L113
.L67:
leaq 96(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 64(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
leaq 32(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
leaq 1056(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
leaq 528(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 1576(%rsp), %rax
subq %fs:40, %rax
jne .L114
movl $0, %eax
addq $1592, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L80:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 128(%rsp), %rdi
call _ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@PLT
jmp .L38
.L79:
endbr64
movq %rax, %rbx
jmp .L74
.L75:
movq %rbx, %rdi
.LEHB8:
call _Unwind_Resume@PLT
.LEHE8:
.L114:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4220:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4220:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4220-.LLSDACSB4220
.LLSDACSB4220:
.uleb128 .LEHB0-.LFB4220
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4220
.uleb128 .LEHE1-.LEHB1
.uleb128 .L79-.LFB4220
.uleb128 0
.uleb128 .LEHB2-.LFB4220
.uleb128 .LEHE2-.LEHB2
.uleb128 .L84-.LFB4220
.uleb128 0
.uleb128 .LEHB3-.LFB4220
.uleb128 .LEHE3-.LEHB3
.uleb128 .L83-.LFB4220
.uleb128 0
.uleb128 .LEHB4-.LFB4220
.uleb128 .LEHE4-.LEHB4
.uleb128 .L80-.LFB4220
.uleb128 0
.uleb128 .LEHB5-.LFB4220
.uleb128 .LEHE5-.LEHB5
.uleb128 .L81-.LFB4220
.uleb128 0
.uleb128 .LEHB6-.LFB4220
.uleb128 .LEHE6-.LEHB6
.uleb128 .L82-.LFB4220
.uleb128 0
.uleb128 .LEHB7-.LFB4220
.uleb128 .LEHE7-.LEHB7
.uleb128 .L81-.LFB4220
.uleb128 0
.uleb128 .LEHB8-.LFB4220
.uleb128 .LEHE8-.LEHB8
.uleb128 0
.uleb128 0
.LLSDACSE4220:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <fstream>
#include <vector>
#include <sstream>
extern int solveMatrix(double *A_in, int n, double *b_in, double *x_out);
using namespace std;
int main(int argc, char *argv[]){
ifstream mtx(argv[1]);
ifstream vec(argv[2]);
vector<double> A;
vector<double> b;
string line;
int n=0;
double token;
while(getline(mtx,line)){
stringstream input;
input.str(line);
int count = 0;
while(input>>token){
A.push_back(token);
count++;
}
if(n==0) n=count;
}
while(vec>>token){
b.push_back(token);
}
for(int i=0;i<n;i++){
for(int j=0;j<n;j++){
cout<<A[4*i+j]<<"\t";
}
cout<<endl;
}
cout<<endl;
for(int i=0;i<n;i++){
cout<<b[i]<<endl;
}
cout<<endl;
solveMatrix(&A[0], n, &b[0], &b[0]);
for(int i=0;i<n;i++){
cout<<b[i]<<endl;
}
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <fstream>
#include <vector>
#include <sstream>
extern int solveMatrix(double *A_in, int n, double *b_in, double *x_out);
using namespace std;
int main(int argc, char *argv[]){
ifstream mtx(argv[1]);
ifstream vec(argv[2]);
vector<double> A;
vector<double> b;
string line;
int n=0;
double token;
while(getline(mtx,line)){
stringstream input;
input.str(line);
int count = 0;
while(input>>token){
A.push_back(token);
count++;
}
if(n==0) n=count;
}
while(vec>>token){
b.push_back(token);
}
for(int i=0;i<n;i++){
for(int j=0;j<n;j++){
cout<<A[4*i+j]<<"\t";
}
cout<<endl;
}
cout<<endl;
for(int i=0;i<n;i++){
cout<<b[i]<<endl;
}
cout<<endl;
solveMatrix(&A[0], n, &b[0], &b[0]);
for(int i=0;i<n;i++){
cout<<b[i]<<endl;
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <fstream>
#include <vector>
#include <sstream>
extern int solveMatrix(double *A_in, int n, double *b_in, double *x_out);
using namespace std;
int main(int argc, char *argv[]){
ifstream mtx(argv[1]);
ifstream vec(argv[2]);
vector<double> A;
vector<double> b;
string line;
int n=0;
double token;
while(getline(mtx,line)){
stringstream input;
input.str(line);
int count = 0;
while(input>>token){
A.push_back(token);
count++;
}
if(n==0) n=count;
}
while(vec>>token){
b.push_back(token);
}
for(int i=0;i<n;i++){
for(int j=0;j<n;j++){
cout<<A[4*i+j]<<"\t";
}
cout<<endl;
}
cout<<endl;
for(int i=0;i<n;i++){
cout<<b[i]<<endl;
}
cout<<endl;
solveMatrix(&A[0], n, &b[0], &b[0]);
for(int i=0;i<n;i++){
cout<<b[i]<<endl;
}
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <fstream>
#include <vector>
#include <sstream>
extern int solveMatrix(double *A_in, int n, double *b_in, double *x_out);
using namespace std;
int main(int argc, char *argv[]){
ifstream mtx(argv[1]);
ifstream vec(argv[2]);
vector<double> A;
vector<double> b;
string line;
int n=0;
double token;
while(getline(mtx,line)){
stringstream input;
input.str(line);
int count = 0;
while(input>>token){
A.push_back(token);
count++;
}
if(n==0) n=count;
}
while(vec>>token){
b.push_back(token);
}
for(int i=0;i<n;i++){
for(int j=0;j<n;j++){
cout<<A[4*i+j]<<"\t";
}
cout<<endl;
}
cout<<endl;
for(int i=0;i<n;i++){
cout<<b[i]<<endl;
}
cout<<endl;
solveMatrix(&A[0], n, &b[0], &b[0]);
for(int i=0;i<n;i++){
cout<<b[i]<<endl;
}
return 0;
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1496, %rsp # imm = 0x5D8
.cfi_def_cfa_offset 1552
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq 8(%rsi), %rsi
leaq 456(%rsp), %rdi
movl $8, %edx
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
movq 16(%rbx), %rsi
.Ltmp0:
leaq 976(%rsp), %rdi
movl $8, %edx
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
.Ltmp1:
# %bb.1:
leaq 48(%rsp), %rax
movq %rax, 32(%rsp)
movq $0, 40(%rsp)
movb $0, 48(%rsp)
movq 456(%rsp), %rax
movq -24(%rax), %rax
movq 696(%rsp,%rax), %r15
testq %r15, %r15
je .LBB0_126
# %bb.2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i.lr.ph
leaq 64(%rsp), %r12
movl $0, 20(%rsp) # 4-byte Folded Spill
xorl %ebp, %ebp
xorl %r13d, %r13d
xorl %eax, %eax
movq %rax, 8(%rsp) # 8-byte Spill
jmp .LBB0_4
.p2align 4, 0x90
.LBB0_3: # %_ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev.exit
# in Loop: Header=BB0_4 Depth=1
movq $_ZTVSt15basic_streambufIcSt11char_traitsIcEE+16, 88(%rsp)
leaq 144(%rsp), %rdi
callq _ZNSt6localeD1Ev
movq _ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE+16(%rip), %rax
movq %rax, 64(%rsp)
movq -24(%rax), %rax
movq _ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE+24(%rip), %rcx
movq %rcx, 64(%rsp,%rax)
movq $0, 72(%rsp)
leaq 192(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
movq 456(%rsp), %rax
movq -24(%rax), %rax
movq 696(%rsp,%rax), %r15
testq %r15, %r15
je .LBB0_127
.LBB0_4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# =>This Loop Header: Depth=1
# Child Loop BB0_18 Depth 2
cmpb $0, 56(%r15)
je .LBB0_6
# %bb.5: # in Loop: Header=BB0_4 Depth=1
movzbl 67(%r15), %eax
jmp .LBB0_8
.p2align 4, 0x90
.LBB0_6: # in Loop: Header=BB0_4 Depth=1
.Ltmp3:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp4:
# %bb.7: # %.noexc42
# in Loop: Header=BB0_4 Depth=1
movq (%r15), %rax
.Ltmp5:
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp6:
.LBB0_8: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
# in Loop: Header=BB0_4 Depth=1
.Ltmp7:
movsbl %al, %edx
leaq 456(%rsp), %rdi
leaq 32(%rsp), %rsi
callq _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_
.Ltmp8:
# %bb.9: # %_ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE.exit
# in Loop: Header=BB0_4 Depth=1
movq (%rax), %rcx
movq -24(%rcx), %rcx
testb $5, 32(%rax,%rcx)
jne .LBB0_37
# %bb.10: # in Loop: Header=BB0_4 Depth=1
.Ltmp82:
movq %r12, %rdi
callq _ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEC1Ev
.Ltmp83:
# %bb.11: # in Loop: Header=BB0_4 Depth=1
movq 32(%rsp), %rcx
movq 40(%rsp), %r8
movq 168(%rsp), %rdx
.Ltmp85:
leaq 160(%rsp), %rdi
xorl %esi, %esi
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm
.Ltmp86:
# %bb.12: # %.noexc47
# in Loop: Header=BB0_4 Depth=1
testb $3, 152(%rsp)
movl $0, %ecx
je .LBB0_14
# %bb.13: # %.noexc47
# in Loop: Header=BB0_4 Depth=1
movq 168(%rsp), %rcx
.LBB0_14: # %.noexc47
# in Loop: Header=BB0_4 Depth=1
movq 160(%rsp), %rsi
.Ltmp87:
leaq 88(%rsp), %rdi
xorl %edx, %edx
callq _ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEE7_M_syncEPcmm
.Ltmp88:
# %bb.15: # %_ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEE3strERKNS_12basic_stringIcS2_S3_EE.exit.preheader
# in Loop: Header=BB0_4 Depth=1
xorl %ebx, %ebx
jmp .LBB0_18
.p2align 4, 0x90
.LBB0_16: # in Loop: Header=BB0_18 Depth=2
movsd 24(%rsp), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%r13)
.LBB0_17: # %_ZNSt6vectorIdSaIdEE9push_backERKd.exit
# in Loop: Header=BB0_18 Depth=2
addq $8, %r13
incl %ebx
.LBB0_18: # %_ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEE3strERKNS_12basic_stringIcS2_S3_EE.exit
# Parent Loop BB0_4 Depth=1
# => This Inner Loop Header: Depth=2
.Ltmp90:
movq %r12, %rdi
leaq 24(%rsp), %rsi
callq _ZNSi10_M_extractIdEERSiRT_
.Ltmp91:
# %bb.19: # %_ZNSirsERd.exit
# in Loop: Header=BB0_18 Depth=2
movq (%rax), %rcx
movq -24(%rcx), %rcx
testb $5, 32(%rax,%rcx)
jne .LBB0_35
# %bb.20: # in Loop: Header=BB0_18 Depth=2
cmpq %rbp, %r13
jne .LBB0_16
# %bb.21: # in Loop: Header=BB0_18 Depth=2
subq 8(%rsp), %r13 # 8-byte Folded Reload
movabsq $9223372036854775800, %rax # imm = 0x7FFFFFFFFFFFFFF8
cmpq %rax, %r13
je .LBB0_114
# %bb.22: # %_ZNKSt6vectorIdSaIdEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB0_18 Depth=2
movq %r13, %r14
sarq $3, %r14
cmpq $1, %r14
movq %r14, %rax
adcq $0, %rax
leaq (%rax,%r14), %rcx
movabsq $1152921504606846975, %rbp # imm = 0xFFFFFFFFFFFFFFF
cmpq %rbp, %rcx
jb .LBB0_23
# %bb.27: # %_ZNKSt6vectorIdSaIdEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB0_18 Depth=2
movq %rbp, %rcx
addq %r14, %rax
jae .LBB0_28
.LBB0_24: # %_ZNKSt6vectorIdSaIdEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB0_18 Depth=2
testq %rbp, %rbp
je .LBB0_29
.LBB0_25: # in Loop: Header=BB0_18 Depth=2
leaq (,%rbp,8), %rdi
.Ltmp92:
callq _Znwm
.Ltmp93:
# %bb.26: # in Loop: Header=BB0_18 Depth=2
movq %rax, %r15
jmp .LBB0_30
.p2align 4, 0x90
.LBB0_23: # %_ZNKSt6vectorIdSaIdEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB0_18 Depth=2
addq %r14, %rax
jb .LBB0_24
.LBB0_28: # %_ZNKSt6vectorIdSaIdEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB0_18 Depth=2
movq %rcx, %rbp
testq %rbp, %rbp
jne .LBB0_25
.LBB0_29: # in Loop: Header=BB0_18 Depth=2
xorl %r15d, %r15d
.LBB0_30: # %_ZNSt12_Vector_baseIdSaIdEE11_M_allocateEm.exit.i.i
# in Loop: Header=BB0_18 Depth=2
movsd 24(%rsp), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%r15,%r14,8)
testq %r13, %r13
movq 8(%rsp), %r14 # 8-byte Reload
jle .LBB0_32
# %bb.31: # in Loop: Header=BB0_18 Depth=2
movq %r15, %rdi
movq %r14, %rsi
movq %r13, %rdx
callq memmove@PLT
.LBB0_32: # %_ZNSt6vectorIdSaIdEE11_S_relocateEPdS2_S2_RS0_.exit.i.i
# in Loop: Header=BB0_18 Depth=2
testq %r14, %r14
je .LBB0_34
# %bb.33: # in Loop: Header=BB0_18 Depth=2
movq %r14, %rdi
callq _ZdlPv
.LBB0_34: # %_ZNSt6vectorIdSaIdEE17_M_realloc_insertIJRKdEEEvN9__gnu_cxx17__normal_iteratorIPdS1_EEDpOT_.exit.i
# in Loop: Header=BB0_18 Depth=2
addq %r15, %r13
leaq (%r15,%rbp,8), %rbp
movq %r15, 8(%rsp) # 8-byte Spill
jmp .LBB0_17
.p2align 4, 0x90
.LBB0_35: # in Loop: Header=BB0_4 Depth=1
movl 20(%rsp), %eax # 4-byte Reload
testl %eax, %eax
cmovel %ebx, %eax
movl %eax, 20(%rsp) # 4-byte Spill
movq _ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 64(%rsp)
movq -24(%rax), %rax
movq _ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE+64(%rip), %rcx
movq %rcx, 64(%rsp,%rax)
movq _ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE+72(%rip), %rax
movq %rax, 80(%rsp)
movq $_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE+16, 88(%rsp)
movq 160(%rsp), %rdi
leaq 176(%rsp), %rax
cmpq %rax, %rdi
je .LBB0_3
# %bb.36: # %.critedge.i.i.i.i.i
# in Loop: Header=BB0_4 Depth=1
callq _ZdlPv
jmp .LBB0_3
.LBB0_37: # %.preheader172.preheader
xorl %r12d, %r12d
leaq 24(%rsp), %r15
xorl %r13d, %r13d
xorl %ebp, %ebp
jmp .LBB0_39
.p2align 4, 0x90
.LBB0_38: # in Loop: Header=BB0_39 Depth=1
movsd 24(%rsp), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%r13)
addq $8, %r13
.LBB0_39: # %.preheader172
# =>This Inner Loop Header: Depth=1
.Ltmp10:
leaq 976(%rsp), %rdi
movq %r15, %rsi
callq _ZNSi10_M_extractIdEERSiRT_
.Ltmp11:
# %bb.40: # %_ZNSirsERd.exit56
# in Loop: Header=BB0_39 Depth=1
movq (%rax), %rcx
movq -24(%rcx), %rcx
testb $5, 32(%rax,%rcx)
jne .LBB0_56
# %bb.41: # in Loop: Header=BB0_39 Depth=1
cmpq %rbp, %r13
jne .LBB0_38
# %bb.42: # in Loop: Header=BB0_39 Depth=1
subq %r12, %r13
movabsq $9223372036854775800, %rax # imm = 0x7FFFFFFFFFFFFFF8
cmpq %rax, %r13
je .LBB0_122
# %bb.43: # %_ZNKSt6vectorIdSaIdEE12_M_check_lenEmPKc.exit.i.i59
# in Loop: Header=BB0_39 Depth=1
movq %r13, %rbx
sarq $3, %rbx
cmpq $1, %rbx
movq %rbx, %rax
adcq $0, %rax
leaq (%rax,%rbx), %rcx
movabsq $1152921504606846975, %rdx # imm = 0xFFFFFFFFFFFFFFF
cmpq %rdx, %rcx
movabsq $1152921504606846975, %rbp # imm = 0xFFFFFFFFFFFFFFF
jb .LBB0_44
# %bb.48: # %_ZNKSt6vectorIdSaIdEE12_M_check_lenEmPKc.exit.i.i59
# in Loop: Header=BB0_39 Depth=1
movabsq $1152921504606846975, %rcx # imm = 0xFFFFFFFFFFFFFFF
addq %rbx, %rax
jae .LBB0_49
.LBB0_45: # %_ZNKSt6vectorIdSaIdEE12_M_check_lenEmPKc.exit.i.i59
# in Loop: Header=BB0_39 Depth=1
testq %rbp, %rbp
je .LBB0_50
.LBB0_46: # in Loop: Header=BB0_39 Depth=1
leaq (,%rbp,8), %rdi
.Ltmp77:
callq _Znwm
.Ltmp78:
# %bb.47: # in Loop: Header=BB0_39 Depth=1
movq %rax, %r14
jmp .LBB0_51
.p2align 4, 0x90
.LBB0_44: # %_ZNKSt6vectorIdSaIdEE12_M_check_lenEmPKc.exit.i.i59
# in Loop: Header=BB0_39 Depth=1
addq %rbx, %rax
jb .LBB0_45
.LBB0_49: # %_ZNKSt6vectorIdSaIdEE12_M_check_lenEmPKc.exit.i.i59
# in Loop: Header=BB0_39 Depth=1
movq %rcx, %rbp
testq %rbp, %rbp
jne .LBB0_46
.LBB0_50: # in Loop: Header=BB0_39 Depth=1
xorl %r14d, %r14d
.LBB0_51: # %_ZNSt12_Vector_baseIdSaIdEE11_M_allocateEm.exit.i.i62
# in Loop: Header=BB0_39 Depth=1
movsd 24(%rsp), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%r14,%rbx,8)
testq %r13, %r13
jle .LBB0_53
# %bb.52: # in Loop: Header=BB0_39 Depth=1
movq %r14, %rdi
movq %r12, %rsi
movq %r13, %rdx
callq memmove@PLT
.LBB0_53: # %_ZNSt6vectorIdSaIdEE11_S_relocateEPdS2_S2_RS0_.exit.i.i63
# in Loop: Header=BB0_39 Depth=1
testq %r12, %r12
je .LBB0_55
# %bb.54: # in Loop: Header=BB0_39 Depth=1
movq %r12, %rdi
callq _ZdlPv
.LBB0_55: # %_ZNSt6vectorIdSaIdEE17_M_realloc_insertIJRKdEEEvN9__gnu_cxx17__normal_iteratorIPdS1_EEDpOT_.exit.i65
# in Loop: Header=BB0_39 Depth=1
addq %r14, %r13
leaq (%r14,%rbp,8), %rbp
addq $8, %r13
movq %r14, %r12
jmp .LBB0_39
.LBB0_56: # %.preheader166
movl 20(%rsp), %ebp # 4-byte Reload
movl %ebp, %r13d
testl %ebp, %ebp
jle .LBB0_70
# %bb.57: # %.preheader165.lr.ph
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_58: # %.preheader165
# =>This Loop Header: Depth=1
# Child Loop BB0_59 Depth 2
movl %ebx, %r14d
andl $1073741823, %r14d # imm = 0x3FFFFFFF
shlq $5, %r14
addq 8(%rsp), %r14 # 8-byte Folded Reload
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_59: # Parent Loop BB0_58 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r14,%r15,8), %xmm0 # xmm0 = mem[0],zero
.Ltmp12:
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp13:
# %bb.60: # %_ZNSolsEd.exit
# in Loop: Header=BB0_59 Depth=2
.Ltmp14:
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp15:
# %bb.61: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
# in Loop: Header=BB0_59 Depth=2
incq %r15
cmpq %r15, %r13
jne .LBB0_59
# %bb.62: # %._crit_edge225
# in Loop: Header=BB0_58 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB0_120
# %bb.63: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i105
# in Loop: Header=BB0_58 Depth=1
cmpb $0, 56(%r14)
je .LBB0_65
# %bb.64: # in Loop: Header=BB0_58 Depth=1
movzbl 67(%r14), %eax
jmp .LBB0_67
.p2align 4, 0x90
.LBB0_65: # in Loop: Header=BB0_58 Depth=1
.Ltmp17:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp18:
# %bb.66: # %.noexc110
# in Loop: Header=BB0_58 Depth=1
movq (%r14), %rax
.Ltmp19:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp20:
.LBB0_67: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i107
# in Loop: Header=BB0_58 Depth=1
.Ltmp21:
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp22:
# %bb.68: # %.noexc112
# in Loop: Header=BB0_58 Depth=1
.Ltmp23:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp24:
# %bb.69: # %_ZNSolsEPFRSoS_E.exit71
# in Loop: Header=BB0_58 Depth=1
incq %rbx
cmpq %r13, %rbx
jne .LBB0_58
.LBB0_70: # %._crit_edge228
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB0_124
# %bb.71: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i95
cmpb $0, 56(%r14)
je .LBB0_73
# %bb.72:
movzbl 67(%r14), %eax
jmp .LBB0_75
.LBB0_73:
.Ltmp26:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp27:
# %bb.74: # %.noexc100
movq (%r14), %rax
.Ltmp28:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp29:
.LBB0_75: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i97
.Ltmp30:
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp31:
# %bb.76: # %.noexc102
.Ltmp32:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp33:
# %bb.77: # %_ZNSolsEPFRSoS_E.exit.preheader
testl %ebp, %ebp
jle .LBB0_88
# %bb.78: # %.lr.ph230.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_79: # %.lr.ph230
# =>This Inner Loop Header: Depth=1
movsd (%r12,%rbx,8), %xmm0 # xmm0 = mem[0],zero
.Ltmp34:
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp35:
# %bb.80: # %_ZNSolsEd.exit77
# in Loop: Header=BB0_79 Depth=1
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r14
testq %r14, %r14
je .LBB0_116
# %bb.81: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i127
# in Loop: Header=BB0_79 Depth=1
cmpb $0, 56(%r14)
je .LBB0_83
# %bb.82: # in Loop: Header=BB0_79 Depth=1
movzbl 67(%r14), %eax
jmp .LBB0_85
.p2align 4, 0x90
.LBB0_83: # in Loop: Header=BB0_79 Depth=1
.Ltmp36:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp37:
# %bb.84: # %.noexc132
# in Loop: Header=BB0_79 Depth=1
movq (%r14), %rax
.Ltmp38:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp39:
.LBB0_85: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i129
# in Loop: Header=BB0_79 Depth=1
.Ltmp40:
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
.Ltmp41:
# %bb.86: # %.noexc134
# in Loop: Header=BB0_79 Depth=1
.Ltmp42:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp43:
# %bb.87: # %_ZNSolsEPFRSoS_E.exit79
# in Loop: Header=BB0_79 Depth=1
incq %rbx
cmpq %rbx, %r13
jne .LBB0_79
.LBB0_88: # %_ZNSolsEPFRSoS_E.exit._crit_edge
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB0_124
# %bb.89: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i116
cmpb $0, 56(%r14)
je .LBB0_91
# %bb.90:
movzbl 67(%r14), %eax
jmp .LBB0_93
.LBB0_91:
.Ltmp45:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp46:
# %bb.92: # %.noexc121
movq (%r14), %rax
.Ltmp47:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp48:
.LBB0_93: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i118
.Ltmp49:
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp50:
# %bb.94: # %.noexc123
.Ltmp51:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp52:
# %bb.95: # %_ZNSolsEPFRSoS_E.exit75
.Ltmp53:
movq 8(%rsp), %rdi # 8-byte Reload
movl %ebp, %esi
movq %r12, %rdx
movq %r12, %rcx
callq _Z11solveMatrixPdiS_S_
.Ltmp54:
# %bb.96: # %.preheader
testl %ebp, %ebp
jle .LBB0_107
# %bb.97: # %.lr.ph232.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_98: # %.lr.ph232
# =>This Inner Loop Header: Depth=1
movsd (%r12,%rbx,8), %xmm0 # xmm0 = mem[0],zero
.Ltmp55:
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp56:
# %bb.99: # %_ZNSolsEd.exit84
# in Loop: Header=BB0_98 Depth=1
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r14
testq %r14, %r14
je .LBB0_118
# %bb.100: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i138
# in Loop: Header=BB0_98 Depth=1
cmpb $0, 56(%r14)
je .LBB0_102
# %bb.101: # in Loop: Header=BB0_98 Depth=1
movzbl 67(%r14), %eax
jmp .LBB0_104
.p2align 4, 0x90
.LBB0_102: # in Loop: Header=BB0_98 Depth=1
.Ltmp57:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp58:
# %bb.103: # %.noexc143
# in Loop: Header=BB0_98 Depth=1
movq (%r14), %rax
.Ltmp59:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp60:
.LBB0_104: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i140
# in Loop: Header=BB0_98 Depth=1
.Ltmp61:
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
.Ltmp62:
# %bb.105: # %.noexc145
# in Loop: Header=BB0_98 Depth=1
.Ltmp63:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp64:
# %bb.106: # %_ZNSolsEPFRSoS_E.exit86
# in Loop: Header=BB0_98 Depth=1
incq %rbx
cmpq %rbx, %r13
jne .LBB0_98
.LBB0_107: # %._crit_edge233
movq 32(%rsp), %rdi
leaq 48(%rsp), %rax
cmpq %rax, %rdi
je .LBB0_109
# %bb.108: # %.critedge.i.i
callq _ZdlPv
.LBB0_109: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
testq %r12, %r12
je .LBB0_111
# %bb.110:
movq %r12, %rdi
callq _ZdlPv
.LBB0_111: # %_ZNSt6vectorIdSaIdEED2Ev.exit
movq 8(%rsp), %rdi # 8-byte Reload
testq %rdi, %rdi
je .LBB0_113
# %bb.112:
callq _ZdlPv
.LBB0_113: # %_ZNSt6vectorIdSaIdEED2Ev.exit82
leaq 976(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 1232(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
leaq 456(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 712(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
xorl %eax, %eax
addq $1496, %rsp # imm = 0x5D8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_114:
.cfi_def_cfa_offset 1552
.Ltmp95:
movl $.L.str.1, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp96:
# %bb.115: # %.noexc53
.LBB0_116:
.Ltmp69:
callq _ZSt16__throw_bad_castv
.Ltmp70:
# %bb.117: # %.noexc131
.LBB0_118:
.Ltmp66:
callq _ZSt16__throw_bad_castv
.Ltmp67:
# %bb.119: # %.noexc142
.LBB0_120:
.Ltmp74:
callq _ZSt16__throw_bad_castv
.Ltmp75:
# %bb.121: # %.noexc109
.LBB0_122:
.Ltmp80:
movl $.L.str.1, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp81:
# %bb.123: # %.noexc66
.LBB0_124: # %.invoke
.Ltmp72:
callq _ZSt16__throw_bad_castv
.Ltmp73:
# %bb.125: # %.cont
.LBB0_126:
xorl %eax, %eax
movq %rax, 8(%rsp) # 8-byte Spill
.LBB0_127: # %._crit_edge
xorl %r12d, %r12d
.Ltmp98:
callq _ZSt16__throw_bad_castv
.Ltmp99:
# %bb.128: # %.noexc
.LBB0_129:
.Ltmp2:
movq %rax, %r15
jmp .LBB0_154
.LBB0_130: # %.loopexit.split-lp168
.Ltmp76:
jmp .LBB0_146
.LBB0_131: # %.loopexit.split-lp
.Ltmp68:
jmp .LBB0_146
.LBB0_132: # %.loopexit.split-lp161
.Ltmp71:
jmp .LBB0_146
.LBB0_133:
.Ltmp84:
jmp .LBB0_138
.LBB0_134: # %.loopexit173
.Ltmp79:
jmp .LBB0_146
.LBB0_135: # %.loopexit.split-lp174.loopexit.split-lp
.Ltmp100:
jmp .LBB0_146
.LBB0_136: # %.loopexit167
.Ltmp25:
jmp .LBB0_146
.LBB0_137: # %.loopexit.split-lp174.loopexit
.Ltmp9:
.LBB0_138: # %.loopexit.split-lp174
movq %rax, %r15
xorl %r12d, %r12d
jmp .LBB0_147
.LBB0_139:
.Ltmp89:
jmp .LBB0_144
.LBB0_140: # %.loopexit
.Ltmp65:
jmp .LBB0_146
.LBB0_141: # %.loopexit160
.Ltmp44:
jmp .LBB0_146
.LBB0_142: # %.loopexit.split-lp179
.Ltmp97:
jmp .LBB0_144
.LBB0_143: # %.loopexit178
.Ltmp94:
.LBB0_144:
movq %rax, %r15
leaq 64(%rsp), %rdi
callq _ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev
xorl %r12d, %r12d
jmp .LBB0_147
.LBB0_145:
.Ltmp16:
.LBB0_146: # %.loopexit.split-lp174
movq %rax, %r15
.LBB0_147: # %.loopexit.split-lp174
movq 32(%rsp), %rdi
leaq 48(%rsp), %rax
cmpq %rax, %rdi
je .LBB0_149
# %bb.148: # %.critedge.i.i87
callq _ZdlPv
.LBB0_149: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit89
testq %r12, %r12
je .LBB0_151
# %bb.150:
movq %r12, %rdi
callq _ZdlPv
.LBB0_151: # %_ZNSt6vectorIdSaIdEED2Ev.exit91
movq 8(%rsp), %rdi # 8-byte Reload
testq %rdi, %rdi
je .LBB0_153
# %bb.152:
callq _ZdlPv
.LBB0_153: # %_ZNSt6vectorIdSaIdEED2Ev.exit93
leaq 976(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 1232(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
.LBB0_154:
leaq 456(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 712(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
movq %r15, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp8-.Ltmp3 # Call between .Ltmp3 and .Ltmp8
.uleb128 .Ltmp9-.Lfunc_begin0 # jumps to .Ltmp9
.byte 0 # On action: cleanup
.uleb128 .Ltmp82-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp83-.Ltmp82 # Call between .Ltmp82 and .Ltmp83
.uleb128 .Ltmp84-.Lfunc_begin0 # jumps to .Ltmp84
.byte 0 # On action: cleanup
.uleb128 .Ltmp85-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp88-.Ltmp85 # Call between .Ltmp85 and .Ltmp88
.uleb128 .Ltmp89-.Lfunc_begin0 # jumps to .Ltmp89
.byte 0 # On action: cleanup
.uleb128 .Ltmp90-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp93-.Ltmp90 # Call between .Ltmp90 and .Ltmp93
.uleb128 .Ltmp94-.Lfunc_begin0 # jumps to .Ltmp94
.byte 0 # On action: cleanup
.uleb128 .Ltmp93-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp10-.Ltmp93 # Call between .Ltmp93 and .Ltmp10
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp78-.Ltmp10 # Call between .Ltmp10 and .Ltmp78
.uleb128 .Ltmp79-.Lfunc_begin0 # jumps to .Ltmp79
.byte 0 # On action: cleanup
.uleb128 .Ltmp78-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp12-.Ltmp78 # Call between .Ltmp78 and .Ltmp12
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp15-.Ltmp12 # Call between .Ltmp12 and .Ltmp15
.uleb128 .Ltmp16-.Lfunc_begin0 # jumps to .Ltmp16
.byte 0 # On action: cleanup
.uleb128 .Ltmp17-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp24-.Ltmp17 # Call between .Ltmp17 and .Ltmp24
.uleb128 .Ltmp25-.Lfunc_begin0 # jumps to .Ltmp25
.byte 0 # On action: cleanup
.uleb128 .Ltmp26-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp33-.Ltmp26 # Call between .Ltmp26 and .Ltmp33
.uleb128 .Ltmp100-.Lfunc_begin0 # jumps to .Ltmp100
.byte 0 # On action: cleanup
.uleb128 .Ltmp34-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Ltmp43-.Ltmp34 # Call between .Ltmp34 and .Ltmp43
.uleb128 .Ltmp44-.Lfunc_begin0 # jumps to .Ltmp44
.byte 0 # On action: cleanup
.uleb128 .Ltmp45-.Lfunc_begin0 # >> Call Site 14 <<
.uleb128 .Ltmp54-.Ltmp45 # Call between .Ltmp45 and .Ltmp54
.uleb128 .Ltmp100-.Lfunc_begin0 # jumps to .Ltmp100
.byte 0 # On action: cleanup
.uleb128 .Ltmp55-.Lfunc_begin0 # >> Call Site 15 <<
.uleb128 .Ltmp64-.Ltmp55 # Call between .Ltmp55 and .Ltmp64
.uleb128 .Ltmp65-.Lfunc_begin0 # jumps to .Ltmp65
.byte 0 # On action: cleanup
.uleb128 .Ltmp95-.Lfunc_begin0 # >> Call Site 16 <<
.uleb128 .Ltmp96-.Ltmp95 # Call between .Ltmp95 and .Ltmp96
.uleb128 .Ltmp97-.Lfunc_begin0 # jumps to .Ltmp97
.byte 0 # On action: cleanup
.uleb128 .Ltmp69-.Lfunc_begin0 # >> Call Site 17 <<
.uleb128 .Ltmp70-.Ltmp69 # Call between .Ltmp69 and .Ltmp70
.uleb128 .Ltmp71-.Lfunc_begin0 # jumps to .Ltmp71
.byte 0 # On action: cleanup
.uleb128 .Ltmp66-.Lfunc_begin0 # >> Call Site 18 <<
.uleb128 .Ltmp67-.Ltmp66 # Call between .Ltmp66 and .Ltmp67
.uleb128 .Ltmp68-.Lfunc_begin0 # jumps to .Ltmp68
.byte 0 # On action: cleanup
.uleb128 .Ltmp74-.Lfunc_begin0 # >> Call Site 19 <<
.uleb128 .Ltmp75-.Ltmp74 # Call between .Ltmp74 and .Ltmp75
.uleb128 .Ltmp76-.Lfunc_begin0 # jumps to .Ltmp76
.byte 0 # On action: cleanup
.uleb128 .Ltmp80-.Lfunc_begin0 # >> Call Site 20 <<
.uleb128 .Ltmp99-.Ltmp80 # Call between .Ltmp80 and .Ltmp99
.uleb128 .Ltmp100-.Lfunc_begin0 # jumps to .Ltmp100
.byte 0 # On action: cleanup
.uleb128 .Ltmp99-.Lfunc_begin0 # >> Call Site 21 <<
.uleb128 .Lfunc_end0-.Ltmp99 # Call between .Ltmp99 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm,comdat
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm # -- Begin function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm
.p2align 4, 0x90
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm,@function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm: # @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movq 8(%rdi), %rax
movq %rdx, %rdi
subq %rax, %rdi
movabsq $9223372036854775807, %r9 # imm = 0x7FFFFFFFFFFFFFFF
addq %rdi, %r9
cmpq %r8, %r9
jb .LBB1_19
# %bb.1: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit
movq %r8, %r15
subq %rdx, %r15
addq %rax, %r15
movq (%rbx), %rdi
leaq 16(%rbx), %r10
movl $15, %r9d
cmpq %r10, %rdi
je .LBB1_3
# %bb.2: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit
movq 16(%rbx), %r9
.LBB1_3: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit
cmpq %r9, %r15
jbe .LBB1_4
# %bb.17:
movq %rbx, %rdi
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
jmp .LBB1_18
.LBB1_4:
leaq (%rdi,%rsi), %r14
addq %rdx, %rsi
movq %rax, %r9
subq %rsi, %r9
cmpq %rcx, %rdi
ja .LBB1_6
# %bb.5:
addq %rax, %rdi
cmpq %rcx, %rdi
jae .LBB1_16
.LBB1_6:
cmpq %rdx, %r8
je .LBB1_12
# %bb.7:
cmpq %rsi, %rax
je .LBB1_12
# %bb.8:
testq %r9, %r9
je .LBB1_12
# %bb.9:
leaq (%r14,%r8), %rdi
addq %r14, %rdx
cmpq $1, %r9
jne .LBB1_11
# %bb.10:
movzbl (%rdx), %eax
movb %al, (%rdi)
.LBB1_12: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_moveEPcPKcm.exit
testq %r8, %r8
je .LBB1_18
.LBB1_13: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_moveEPcPKcm.exit
cmpq $1, %r8
jne .LBB1_15
# %bb.14:
movzbl (%rcx), %eax
movb %al, (%r14)
jmp .LBB1_18
.LBB1_15:
movq %r14, %rdi
movq %rcx, %rsi
movq %r8, %rdx
callq memcpy@PLT
.LBB1_18: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit
movq %r15, 8(%rbx)
movq (%rbx), %rax
movb $0, (%rax,%r15)
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_11:
.cfi_def_cfa_offset 48
movq %rdx, %rsi
movq %r9, %rdx
movq %r8, %r12
movq %rcx, %r13
callq memmove@PLT
movq %r13, %rcx
movq %r12, %r8
testq %r8, %r8
jne .LBB1_13
jmp .LBB1_18
.LBB1_16:
movq %rbx, %rdi
movq %r14, %rsi
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_replace_coldEPcmPKcmm
jmp .LBB1_18
.LBB1_19:
movl $.L.str.2, %edi
callq _ZSt20__throw_length_errorPKc
.Lfunc_end1:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm, .Lfunc_end1-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm
.cfi_endproc
# -- End function
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm,comdat
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm # -- Begin function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.p2align 4, 0x90
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm,@function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm: # @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.cfi_startproc
# %bb.0: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %rbp
movq %rcx, 32(%rsp) # 8-byte Spill
movq %rsi, %r15
movq %rdi, %rbx
movq (%rdi), %r14
movq 8(%rdi), %r12
movq %r8, (%rsp) # 8-byte Spill
movq %rdx, 16(%rsp) # 8-byte Spill
subq %rdx, %rbp
leaq 16(%rdi), %rcx
movl $15, %eax
cmpq %rcx, %r14
je .LBB2_2
# %bb.1: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
movq 16(%rbx), %rax
.LBB2_2: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
addq %r12, %rbp
js .LBB2_26
# %bb.3:
cmpq %rax, %rbp
jbe .LBB2_6
# %bb.4:
addq %rax, %rax
cmpq %rax, %rbp
jae .LBB2_6
# %bb.5:
movabsq $9223372036854775807, %rbp # imm = 0x7FFFFFFFFFFFFFFF
cmpq %rbp, %rax
cmovbq %rax, %rbp
.LBB2_6:
movq %rbp, %rdi
incq %rdi
js .LBB2_27
# %bb.7: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit
movq %rcx, 24(%rsp) # 8-byte Spill
callq _Znwm
movq %rax, %r13
testq %r15, %r15
je .LBB2_11
# %bb.8: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit
cmpq $1, %r15
jne .LBB2_10
# %bb.9:
movzbl (%r14), %eax
movb %al, (%r13)
jmp .LBB2_11
.LBB2_10:
movq %r13, %rdi
movq %r14, %rsi
movq %r15, %rdx
callq memcpy@PLT
.LBB2_11: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit
movq %r14, 8(%rsp) # 8-byte Spill
movq 16(%rsp), %rax # 8-byte Reload
leaq (%rax,%r15), %r14
movq 32(%rsp), %rsi # 8-byte Reload
testq %rsi, %rsi
movq (%rsp), %rdx # 8-byte Reload
je .LBB2_18
# %bb.12: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit
testq %rdx, %rdx
je .LBB2_18
# %bb.13:
je .LBB2_18
# %bb.14:
leaq (%r15,%r13), %rdi
cmpq $1, %rdx
jne .LBB2_16
# %bb.15:
movzbl (%rsi), %eax
movb %al, (%rdi)
jmp .LBB2_17
.LBB2_16:
callq memcpy@PLT
.LBB2_17: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit26
movq (%rsp), %rdx # 8-byte Reload
.LBB2_18: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit26
cmpq %r14, %r12
je .LBB2_23
# %bb.19:
subq %r14, %r12
je .LBB2_23
# %bb.20:
movq %r13, %rdi
addq %r15, %rdi
addq %rdx, %rdi
addq 8(%rsp), %r15 # 8-byte Folded Reload
addq 16(%rsp), %r15 # 8-byte Folded Reload
cmpq $1, %r12
jne .LBB2_22
# %bb.21:
movzbl (%r15), %eax
movb %al, (%rdi)
jmp .LBB2_23
.LBB2_22:
movq %r15, %rsi
movq %r12, %rdx
callq memcpy@PLT
.LBB2_23: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit27
movq 8(%rsp), %rdi # 8-byte Reload
cmpq 24(%rsp), %rdi # 8-byte Folded Reload
je .LBB2_25
# %bb.24: # %.critedge.i
callq _ZdlPv
.LBB2_25: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv.exit
movq %r13, (%rbx)
movq %rbp, 16(%rbx)
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_27:
.cfi_def_cfa_offset 96
callq _ZSt17__throw_bad_allocv
.LBB2_26:
movl $.L.str.3, %edi
callq _ZSt20__throw_length_errorPKc
.Lfunc_end2:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm, .Lfunc_end2-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\t"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "vector::_M_realloc_insert"
.size .L.str.1, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "basic_string::_M_replace"
.size .L.str.2, 25
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "basic_string::_M_create"
.size .L.str.3, 24
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void count_characters(int *buffer, int *freq, long file_size, int base) {
int index = threadIdx.x + blockIdx.x * blockDim.x;
int total_threads = gridDim.x * blockDim.x;
long i;
for (i=index; i<file_size; i+=total_threads)
atomicAdd(&(freq[buffer[i] - base]), 1);
} | code for sm_80
Function : _Z16count_charactersPiS_li
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.AND.EX P0, PT, R2, c[0x0][0x174], PT, P0 ; /* 0x00005d0002007a0c */
/* 0x000fda0003f06300 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff037624 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0000 */
/*00b0*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0002 */
/*00c0*/ IMAD R0, R3, c[0x0][0x0], RZ ; /* 0x0000000003007a24 */
/* 0x000fe400078e02ff */
/*00d0*/ LEA R4, P0, R7, c[0x0][0x160], 0x2 ; /* 0x0000580007047a11 */
/* 0x000fc800078010ff */
/*00e0*/ LEA.HI.X R5, R7, c[0x0][0x164], R6, 0x2, P0 ; /* 0x0000590007057a11 */
/* 0x000fca00000f1406 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0100*/ IADD3 R7, P0, R0.reuse, R7, RZ ; /* 0x0000000700077210 */
/* 0x040fe20007f1e0ff */
/*0110*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x001fe200078e00ff */
/*0120*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0130*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fe200078e00ff */
/*0140*/ LEA.HI.X.SX32 R6, R0, R6, 0x1, P0 ; /* 0x0000000600067211 */
/* 0x000fe400000f0eff */
/*0150*/ ISETP.GE.U32.AND P0, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fc80003f06070 */
/*0160*/ ISETP.GE.AND.EX P0, PT, R6, c[0x0][0x174], PT, P0 ; /* 0x00005d0006007a0c */
/* 0x000fe40003f06300 */
/*0170*/ IADD3 R2, R4, -c[0x0][0x178], RZ ; /* 0x80005e0004027a10 */
/* 0x004fca0007ffe0ff */
/*0180*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*0190*/ RED.E.ADD.STRONG.GPU [R2.64], R9 ; /* 0x000000090200798e */
/* 0x0001e2000c10e184 */
/*01a0*/ @!P0 BRA 0xd0 ; /* 0xffffff2000008947 */
/* 0x000fea000383ffff */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void count_characters(int *buffer, int *freq, long file_size, int base) {
int index = threadIdx.x + blockIdx.x * blockDim.x;
int total_threads = gridDim.x * blockDim.x;
long i;
for (i=index; i<file_size; i+=total_threads)
atomicAdd(&(freq[buffer[i] - base]), 1);
} | .file "tmpxft_0007a560_00000000-6_count_characters.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z16count_charactersPiS_liPiS_li
.type _Z40__device_stub__Z16count_charactersPiS_liPiS_li, @function
_Z40__device_stub__Z16count_charactersPiS_liPiS_li:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16count_charactersPiS_li(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z16count_charactersPiS_liPiS_li, .-_Z40__device_stub__Z16count_charactersPiS_liPiS_li
.globl _Z16count_charactersPiS_li
.type _Z16count_charactersPiS_li, @function
_Z16count_charactersPiS_li:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z16count_charactersPiS_liPiS_li
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16count_charactersPiS_li, .-_Z16count_charactersPiS_li
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16count_charactersPiS_li"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16count_charactersPiS_li(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void count_characters(int *buffer, int *freq, long file_size, int base) {
int index = threadIdx.x + blockIdx.x * blockDim.x;
int total_threads = gridDim.x * blockDim.x;
long i;
for (i=index; i<file_size; i+=total_threads)
atomicAdd(&(freq[buffer[i] - base]), 1);
} | #include <hip/hip_runtime.h>
__global__ void count_characters(int *buffer, int *freq, long file_size, int base) {
int index = threadIdx.x + blockIdx.x * blockDim.x;
int total_threads = gridDim.x * blockDim.x;
long i;
for (i=index; i<file_size; i+=total_threads)
atomicAdd(&(freq[buffer[i] - base]), 1);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void count_characters(int *buffer, int *freq, long file_size, int base) {
int index = threadIdx.x + blockIdx.x * blockDim.x;
int total_threads = gridDim.x * blockDim.x;
long i;
for (i=index; i<file_size; i+=total_threads)
atomicAdd(&(freq[buffer[i] - base]), 1);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16count_charactersPiS_li
.globl _Z16count_charactersPiS_li
.p2align 8
.type _Z16count_charactersPiS_li,@function
_Z16count_charactersPiS_li:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_cmpx_gt_i64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b32 s9, s[4:5], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s1, s[0:1], 0x18
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_mov_b32_e32 v0, 1
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s9, s8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_ashr_i32 s9, s8, 31
s_lshl_b64 s[4:5], s[8:9], 2
.p2align 6
.LBB0_2:
global_load_b32 v5, v[3:4], off
v_add_co_u32 v3, s0, v3, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s0, s5, v4, s0
s_waitcnt vmcnt(0)
v_subrev_nc_u32_e32 v5, s1, v5
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, vcc_lo, s6, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, s8
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
global_atomic_add_u32 v[5:6], v0, off
v_cmp_le_i64_e32 vcc_lo, s[2:3], v[1:2]
s_or_b32 s10, vcc_lo, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16count_charactersPiS_li
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16count_charactersPiS_li, .Lfunc_end0-_Z16count_charactersPiS_li
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16count_charactersPiS_li
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16count_charactersPiS_li.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void count_characters(int *buffer, int *freq, long file_size, int base) {
int index = threadIdx.x + blockIdx.x * blockDim.x;
int total_threads = gridDim.x * blockDim.x;
long i;
for (i=index; i<file_size; i+=total_threads)
atomicAdd(&(freq[buffer[i] - base]), 1);
} | .text
.file "count_characters.hip"
.globl _Z31__device_stub__count_charactersPiS_li # -- Begin function _Z31__device_stub__count_charactersPiS_li
.p2align 4, 0x90
.type _Z31__device_stub__count_charactersPiS_li,@function
_Z31__device_stub__count_charactersPiS_li: # @_Z31__device_stub__count_charactersPiS_li
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16count_charactersPiS_li, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__count_charactersPiS_li, .Lfunc_end0-_Z31__device_stub__count_charactersPiS_li
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16count_charactersPiS_li, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16count_charactersPiS_li,@object # @_Z16count_charactersPiS_li
.section .rodata,"a",@progbits
.globl _Z16count_charactersPiS_li
.p2align 3, 0x0
_Z16count_charactersPiS_li:
.quad _Z31__device_stub__count_charactersPiS_li
.size _Z16count_charactersPiS_li, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16count_charactersPiS_li"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__count_charactersPiS_li
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16count_charactersPiS_li
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16count_charactersPiS_li
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.AND.EX P0, PT, R2, c[0x0][0x174], PT, P0 ; /* 0x00005d0002007a0c */
/* 0x000fda0003f06300 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff037624 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0000 */
/*00b0*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0002 */
/*00c0*/ IMAD R0, R3, c[0x0][0x0], RZ ; /* 0x0000000003007a24 */
/* 0x000fe400078e02ff */
/*00d0*/ LEA R4, P0, R7, c[0x0][0x160], 0x2 ; /* 0x0000580007047a11 */
/* 0x000fc800078010ff */
/*00e0*/ LEA.HI.X R5, R7, c[0x0][0x164], R6, 0x2, P0 ; /* 0x0000590007057a11 */
/* 0x000fca00000f1406 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0100*/ IADD3 R7, P0, R0.reuse, R7, RZ ; /* 0x0000000700077210 */
/* 0x040fe20007f1e0ff */
/*0110*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x001fe200078e00ff */
/*0120*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0130*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fe200078e00ff */
/*0140*/ LEA.HI.X.SX32 R6, R0, R6, 0x1, P0 ; /* 0x0000000600067211 */
/* 0x000fe400000f0eff */
/*0150*/ ISETP.GE.U32.AND P0, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fc80003f06070 */
/*0160*/ ISETP.GE.AND.EX P0, PT, R6, c[0x0][0x174], PT, P0 ; /* 0x00005d0006007a0c */
/* 0x000fe40003f06300 */
/*0170*/ IADD3 R2, R4, -c[0x0][0x178], RZ ; /* 0x80005e0004027a10 */
/* 0x004fca0007ffe0ff */
/*0180*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*0190*/ RED.E.ADD.STRONG.GPU [R2.64], R9 ; /* 0x000000090200798e */
/* 0x0001e2000c10e184 */
/*01a0*/ @!P0 BRA 0xd0 ; /* 0xffffff2000008947 */
/* 0x000fea000383ffff */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16count_charactersPiS_li
.globl _Z16count_charactersPiS_li
.p2align 8
.type _Z16count_charactersPiS_li,@function
_Z16count_charactersPiS_li:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_cmpx_gt_i64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b32 s9, s[4:5], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s1, s[0:1], 0x18
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_mov_b32_e32 v0, 1
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s9, s8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_ashr_i32 s9, s8, 31
s_lshl_b64 s[4:5], s[8:9], 2
.p2align 6
.LBB0_2:
global_load_b32 v5, v[3:4], off
v_add_co_u32 v3, s0, v3, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s0, s5, v4, s0
s_waitcnt vmcnt(0)
v_subrev_nc_u32_e32 v5, s1, v5
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, vcc_lo, s6, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, s8
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
global_atomic_add_u32 v[5:6], v0, off
v_cmp_le_i64_e32 vcc_lo, s[2:3], v[1:2]
s_or_b32 s10, vcc_lo, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16count_charactersPiS_li
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16count_charactersPiS_li, .Lfunc_end0-_Z16count_charactersPiS_li
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16count_charactersPiS_li
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16count_charactersPiS_li.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007a560_00000000-6_count_characters.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z16count_charactersPiS_liPiS_li
.type _Z40__device_stub__Z16count_charactersPiS_liPiS_li, @function
_Z40__device_stub__Z16count_charactersPiS_liPiS_li:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16count_charactersPiS_li(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z16count_charactersPiS_liPiS_li, .-_Z40__device_stub__Z16count_charactersPiS_liPiS_li
.globl _Z16count_charactersPiS_li
.type _Z16count_charactersPiS_li, @function
_Z16count_charactersPiS_li:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z16count_charactersPiS_liPiS_li
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16count_charactersPiS_li, .-_Z16count_charactersPiS_li
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16count_charactersPiS_li"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16count_charactersPiS_li(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "count_characters.hip"
.globl _Z31__device_stub__count_charactersPiS_li # -- Begin function _Z31__device_stub__count_charactersPiS_li
.p2align 4, 0x90
.type _Z31__device_stub__count_charactersPiS_li,@function
_Z31__device_stub__count_charactersPiS_li: # @_Z31__device_stub__count_charactersPiS_li
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16count_charactersPiS_li, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__count_charactersPiS_li, .Lfunc_end0-_Z31__device_stub__count_charactersPiS_li
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16count_charactersPiS_li, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16count_charactersPiS_li,@object # @_Z16count_charactersPiS_li
.section .rodata,"a",@progbits
.globl _Z16count_charactersPiS_li
.p2align 3, 0x0
_Z16count_charactersPiS_li:
.quad _Z31__device_stub__count_charactersPiS_li
.size _Z16count_charactersPiS_li, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16count_charactersPiS_li"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__count_charactersPiS_li
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16count_charactersPiS_li
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#define TILE_DIM 16
__global__ void multiMatrix (int *a, int *b, int *c, int N) {
int idx = threadIdx.x + blockDim.x * blockIdx.x;
int idy = threadIdx.y + blockDim.y * blockIdx.y;
int pos = idx + idy * N;
int temp_result = 0;
int posa, posb;
__shared__ int s_a[TILE_DIM][TILE_DIM];
__shared__ int s_b[TILE_DIM][TILE_DIM];
for (int tile_idx = 0; tile_idx < gridDim.x; tile_idx++)
{
posa = idy * N + (tile_idx * TILE_DIM + threadIdx.x);
posb = (tile_idx * TILE_DIM + threadIdx.y) * N + idx;
if (posa < N*N) {
s_a[threadIdx.y][threadIdx.x] = a[posa];
} else {
s_a[threadIdx.y][threadIdx.x] = 0;
}
if (posb < N*N) {
s_b[threadIdx.y][threadIdx.x] = b[posb];
} else {
s_b[threadIdx.y][threadIdx.x] = 0;
}
__syncthreads();
if (idx < N && idy < N) {
for (int i=0; i < TILE_DIM; i++) {
temp_result += s_a[threadIdx.y][i] *
s_b[i][threadIdx.x];
}
}
__syncthreads();
}
__syncthreads();
if(idx < N && idy < N) {
c[pos] = temp_result;
}
}
int main (int argc, char* argv[]){
int N = 4;
size_t size = N*N*sizeof(int);
int num_thread, num_block;
int *h_a, *h_b, *h_c;
h_a = (int*)malloc(size);
h_b = (int*)malloc(size);
h_c = (int*)malloc(size);
int *d_a, *d_b, *d_c;
cudaMalloc(&d_a, size);
cudaMalloc(&d_b, size);
cudaMalloc(&d_c, size);
int i = 0, j = 0;
for (i = 0; i < N*N; i++){
h_a[i] = h_b[i] = i;
}
cudaMemcpy(d_a,h_a,size,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,h_b,size,cudaMemcpyHostToDevice);
cudaMemset(d_c,0,size);
num_block = ceil((float)N/TILE_DIM);
num_thread = N < TILE_DIM ? N : TILE_DIM;
printf("Blocks: %d Threads: %d \n", num_block, num_thread);
dim3 gridsize(num_block,num_block,1);
dim3 blocksize(num_thread,num_thread,1);
multiMatrix<<<gridsize,blocksize>>>(d_a, d_b, d_c, N);
cudaMemcpy(h_c, d_c, size, cudaMemcpyDeviceToHost);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
free(h_a);
free(h_b);
free(h_c);
} | code for sm_80
Function : _Z11multiMatrixPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0xc], PT ; /* 0x00000300ff007a0c */
/* 0x000fe20003f05270 */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0060*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e680000002600 */
/*0070*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0080*/ IMAD R2, R3, c[0x0][0x0], R0 ; /* 0x0000000003027a24 */
/* 0x001fc400078e0200 */
/*0090*/ IMAD R3, R4, c[0x0][0x4], R5 ; /* 0x0000010004037a24 */
/* 0x002fe200078e0205 */
/*00a0*/ @!P0 BRA 0x500 ; /* 0x0000045000008947 */
/* 0x000fea0003800000 */
/*00b0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*00c0*/ IMAD R16, R5.reuse, c[0x0][0x178], R2 ; /* 0x00005e0005107a24 */
/* 0x040fe200078e0202 */
/*00d0*/ SHF.L.U32 R17, R5, 0x6, RZ ; /* 0x0000000605117819 */
/* 0x000fe200000006ff */
/*00e0*/ IMAD R18, R3, c[0x0][0x178], R0 ; /* 0x00005e0003127a24 */
/* 0x000fe200078e0200 */
/*00f0*/ ISETP.LT.AND P0, PT, R2, c[0x0][0x178], !P0 ; /* 0x00005e0002007a0c */
/* 0x000fe20004701270 */
/*0100*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000800 */
/*0110*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe20000000f00 */
/*0120*/ UIMAD UR4, UR4, UR4, URZ ; /* 0x00000004040472a4 */
/* 0x000fe2000f8e023f */
/*0130*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fe40000000f00 */
/*0140*/ LEA R19, R0, R17, 0x2 ; /* 0x0000001100137211 */
/* 0x000fc600078e10ff */
/*0150*/ ISETP.GE.AND P1, PT, R18, UR4, PT ; /* 0x0000000412007c0c */
/* 0x000fe2000bf26270 */
/*0160*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x000fe200000001ff */
/*0170*/ ISETP.GE.AND P2, PT, R16, UR4, PT ; /* 0x0000000410007c0c */
/* 0x000fc4000bf46270 */
/*0180*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fd20000000f00 */
/*0190*/ @!P1 MOV R5, 0x4 ; /* 0x0000000400059802 */
/* 0x000fe40000000f00 */
/*01a0*/ @!P2 MOV R7, 0x4 ; /* 0x000000040007a802 */
/* 0x000fc60000000f00 */
/*01b0*/ @!P1 IMAD.WIDE R4, R18, R5, c[0x0][0x160] ; /* 0x0000580012049625 */
/* 0x000fc800078e0205 */
/*01c0*/ @!P2 IMAD.WIDE R6, R16, R7, c[0x0][0x168] ; /* 0x00005a001006a625 */
/* 0x000fe200078e0207 */
/*01d0*/ @!P1 LDG.E R8, [R4.64] ; /* 0x0000000604089981 */
/* 0x000ea8000c1e1900 */
/*01e0*/ @!P2 LDG.E R10, [R6.64] ; /* 0x00000006060aa981 */
/* 0x000ee2000c1e1900 */
/*01f0*/ BSSY B0, 0x490 ; /* 0x0000029000007945 */
/* 0x000fe60003800000 */
/*0200*/ STS [R19], R8 ; /* 0x0000000813007388 */
/* 0x0041e80000000800 */
/*0210*/ STS [R19+0x400], R10 ; /* 0x0004000a13007388 */
/* 0x0081e80000000800 */
/*0220*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0230*/ @!P0 BRA 0x480 ; /* 0x0000024000008947 */
/* 0x000fea0003800000 */
/*0240*/ LDS R8, [R0.X4+0x400] ; /* 0x0004000000087984 */
/* 0x001fe80000004800 */
/*0250*/ LDS.128 R12, [R17] ; /* 0x00000000110c7984 */
/* 0x000e280000000c00 */
/*0260*/ LDS R10, [R0.X4+0x440] ; /* 0x00044000000a7984 */
/* 0x000e680000004800 */
/*0270*/ LDS R11, [R0.X4+0x480] ; /* 0x00048000000b7984 */
/* 0x000ea80000004800 */
/*0280*/ LDS R22, [R0.X4+0x4c0] ; /* 0x0004c00000167984 */
/* 0x000ee80000004800 */
/*0290*/ LDS R25, [R0.X4+0x500] ; /* 0x0005000000197984 */
/* 0x000fe80000004800 */
/*02a0*/ LDS.128 R4, [R17+0x10] ; /* 0x0000100011047984 */
/* 0x000f280000000c00 */
/*02b0*/ LDS R26, [R0.X4+0x540] ; /* 0x00054000001a7984 */
/* 0x000f680000004800 */
/*02c0*/ LDS R23, [R0.X4+0x580] ; /* 0x0005800000177984 */
/* 0x000f680000004800 */
/*02d0*/ LDS R20, [R0.X4+0x5c0] ; /* 0x0005c00000147984 */
/* 0x000f680000004800 */
/*02e0*/ LDS R21, [R0.X4+0x600] ; /* 0x0006000000157984 */
/* 0x000fe20000004800 */
/*02f0*/ IMAD R8, R12, R8, R9 ; /* 0x000000080c087224 */
/* 0x001fc800078e0209 */
/*0300*/ IMAD R13, R10, R13, R8 ; /* 0x0000000d0a0d7224 */
/* 0x002fc800078e0208 */
/*0310*/ IMAD R13, R11, R14, R13 ; /* 0x0000000e0b0d7224 */
/* 0x004fe400078e020d */
/*0320*/ LDS.128 R8, [R17+0x20] ; /* 0x0000200011087984 */
/* 0x000e240000000c00 */
/*0330*/ IMAD R13, R22, R15, R13 ; /* 0x0000000f160d7224 */
/* 0x008fe400078e020d */
/*0340*/ LDS R22, [R0.X4+0x640] ; /* 0x0006400000167984 */
/* 0x000e640000004800 */
/*0350*/ IMAD R4, R25, R4, R13 ; /* 0x0000000419047224 */
/* 0x010fe400078e020d */
/*0360*/ LDS R25, [R0.X4+0x680] ; /* 0x0006800000197984 */
/* 0x000ea40000004800 */
/*0370*/ IMAD R5, R26, R5, R4 ; /* 0x000000051a057224 */
/* 0x020fc400078e0204 */
/*0380*/ LDS R4, [R0.X4+0x6c0] ; /* 0x0006c00000047984 */
/* 0x000ee40000004800 */
/*0390*/ IMAD R23, R23, R6, R5 ; /* 0x0000000617177224 */
/* 0x000fe400078e0205 */
/*03a0*/ LDS R5, [R0.X4+0x700] ; /* 0x0007000000057984 */
/* 0x000fe40000004800 */
/*03b0*/ IMAD R23, R20, R7, R23 ; /* 0x0000000714177224 */
/* 0x000fe400078e0217 */
/*03c0*/ LDS.128 R12, [R17+0x30] ; /* 0x00003000110c7984 */
/* 0x000f280000000c00 */
/*03d0*/ LDS R6, [R0.X4+0x740] ; /* 0x0007400000067984 */
/* 0x000f680000004800 */
/*03e0*/ LDS R7, [R0.X4+0x780] ; /* 0x0007800000077984 */
/* 0x000f680000004800 */
/*03f0*/ LDS R20, [R0.X4+0x7c0] ; /* 0x0007c00000147984 */
/* 0x000f620000004800 */
/*0400*/ IMAD R8, R21, R8, R23 ; /* 0x0000000815087224 */
/* 0x001fc800078e0217 */
/*0410*/ IMAD R8, R22, R9, R8 ; /* 0x0000000916087224 */
/* 0x002fc800078e0208 */
/*0420*/ IMAD R8, R25, R10, R8 ; /* 0x0000000a19087224 */
/* 0x004fc800078e0208 */
/*0430*/ IMAD R4, R4, R11, R8 ; /* 0x0000000b04047224 */
/* 0x008fc800078e0208 */
/*0440*/ IMAD R4, R5, R12, R4 ; /* 0x0000000c05047224 */
/* 0x010fc800078e0204 */
/*0450*/ IMAD R4, R6, R13, R4 ; /* 0x0000000d06047224 */
/* 0x020fc800078e0204 */
/*0460*/ IMAD R4, R7, R14, R4 ; /* 0x0000000e07047224 */
/* 0x000fc800078e0204 */
/*0470*/ IMAD R9, R20, R15, R4 ; /* 0x0000000f14097224 */
/* 0x000fe400078e0204 */
/*0480*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0490*/ IADD3 R24, R24, 0x1, RZ ; /* 0x0000000118187810 */
/* 0x000fe20007ffe0ff */
/*04a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*04b0*/ MOV R5, c[0x0][0x178] ; /* 0x00005e0000057a02 */
/* 0x000fe40000000f00 */
/*04c0*/ ISETP.GE.U32.AND P1, PT, R24, c[0x0][0xc], PT ; /* 0x0000030018007a0c */
/* 0x000fe40003f26070 */
/*04d0*/ LEA R16, R5, R16, 0x4 ; /* 0x0000001005107211 */
/* 0x000fe400078e20ff */
/*04e0*/ IADD3 R18, R18, 0x10, RZ ; /* 0x0000001012127810 */
/* 0x000fd20007ffe0ff */
/*04f0*/ @!P1 BRA 0x150 ; /* 0xfffffc5000009947 */
/* 0x000fea000383ffff */
/*0500*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0510*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fc80003f06270 */
/*0520*/ ISETP.GE.OR P0, PT, R2, c[0x0][0x178], P0 ; /* 0x00005e0002007a0c */
/* 0x000fda0000706670 */
/*0530*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0540*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0550*/ IMAD R2, R3, c[0x0][0x178], R2 ; /* 0x00005e0003027a24 */
/* 0x000fd200078e0202 */
/*0560*/ IMAD.WIDE R2, R2, R5, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0205 */
/*0570*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101906 */
/*0580*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0590*/ BRA 0x590; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define TILE_DIM 16
__global__ void multiMatrix (int *a, int *b, int *c, int N) {
int idx = threadIdx.x + blockDim.x * blockIdx.x;
int idy = threadIdx.y + blockDim.y * blockIdx.y;
int pos = idx + idy * N;
int temp_result = 0;
int posa, posb;
__shared__ int s_a[TILE_DIM][TILE_DIM];
__shared__ int s_b[TILE_DIM][TILE_DIM];
for (int tile_idx = 0; tile_idx < gridDim.x; tile_idx++)
{
posa = idy * N + (tile_idx * TILE_DIM + threadIdx.x);
posb = (tile_idx * TILE_DIM + threadIdx.y) * N + idx;
if (posa < N*N) {
s_a[threadIdx.y][threadIdx.x] = a[posa];
} else {
s_a[threadIdx.y][threadIdx.x] = 0;
}
if (posb < N*N) {
s_b[threadIdx.y][threadIdx.x] = b[posb];
} else {
s_b[threadIdx.y][threadIdx.x] = 0;
}
__syncthreads();
if (idx < N && idy < N) {
for (int i=0; i < TILE_DIM; i++) {
temp_result += s_a[threadIdx.y][i] *
s_b[i][threadIdx.x];
}
}
__syncthreads();
}
__syncthreads();
if(idx < N && idy < N) {
c[pos] = temp_result;
}
}
int main (int argc, char* argv[]){
int N = 4;
size_t size = N*N*sizeof(int);
int num_thread, num_block;
int *h_a, *h_b, *h_c;
h_a = (int*)malloc(size);
h_b = (int*)malloc(size);
h_c = (int*)malloc(size);
int *d_a, *d_b, *d_c;
cudaMalloc(&d_a, size);
cudaMalloc(&d_b, size);
cudaMalloc(&d_c, size);
int i = 0, j = 0;
for (i = 0; i < N*N; i++){
h_a[i] = h_b[i] = i;
}
cudaMemcpy(d_a,h_a,size,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,h_b,size,cudaMemcpyHostToDevice);
cudaMemset(d_c,0,size);
num_block = ceil((float)N/TILE_DIM);
num_thread = N < TILE_DIM ? N : TILE_DIM;
printf("Blocks: %d Threads: %d \n", num_block, num_thread);
dim3 gridsize(num_block,num_block,1);
dim3 blocksize(num_thread,num_thread,1);
multiMatrix<<<gridsize,blocksize>>>(d_a, d_b, d_c, N);
cudaMemcpy(h_c, d_c, size, cudaMemcpyDeviceToHost);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
free(h_a);
free(h_b);
free(h_c);
} | .file "tmpxft_00017ccb_00000000-6_mult_matrix.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z11multiMatrixPiS_S_iPiS_S_i
.type _Z36__device_stub__Z11multiMatrixPiS_S_iPiS_S_i, @function
_Z36__device_stub__Z11multiMatrixPiS_S_iPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11multiMatrixPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z36__device_stub__Z11multiMatrixPiS_S_iPiS_S_i, .-_Z36__device_stub__Z11multiMatrixPiS_S_iPiS_S_i
.globl _Z11multiMatrixPiS_S_i
.type _Z11multiMatrixPiS_S_i, @function
_Z11multiMatrixPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11multiMatrixPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11multiMatrixPiS_S_i, .-_Z11multiMatrixPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Blocks: %d Threads: %d \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $64, %edi
call malloc@PLT
movq %rax, %rbp
movl $64, %edi
call malloc@PLT
movq %rax, %rbx
movl $64, %edi
call malloc@PLT
movq %rax, %r12
leaq 8(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
movl %eax, (%rbx,%rax,4)
movl %eax, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $16, %rax
jne .L12
movl $1, %ecx
movl $64, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $64, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $64, %edx
movl $0, %esi
movq 24(%rsp), %rdi
call cudaMemset@PLT
movl $4, %ecx
movl $1, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $4, 44(%rsp)
movl $4, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movl $2, %ecx
movl $64, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl $4, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z36__device_stub__Z11multiMatrixPiS_S_iPiS_S_i
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z11multiMatrixPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z11multiMatrixPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define TILE_DIM 16
__global__ void multiMatrix (int *a, int *b, int *c, int N) {
int idx = threadIdx.x + blockDim.x * blockIdx.x;
int idy = threadIdx.y + blockDim.y * blockIdx.y;
int pos = idx + idy * N;
int temp_result = 0;
int posa, posb;
__shared__ int s_a[TILE_DIM][TILE_DIM];
__shared__ int s_b[TILE_DIM][TILE_DIM];
for (int tile_idx = 0; tile_idx < gridDim.x; tile_idx++)
{
posa = idy * N + (tile_idx * TILE_DIM + threadIdx.x);
posb = (tile_idx * TILE_DIM + threadIdx.y) * N + idx;
if (posa < N*N) {
s_a[threadIdx.y][threadIdx.x] = a[posa];
} else {
s_a[threadIdx.y][threadIdx.x] = 0;
}
if (posb < N*N) {
s_b[threadIdx.y][threadIdx.x] = b[posb];
} else {
s_b[threadIdx.y][threadIdx.x] = 0;
}
__syncthreads();
if (idx < N && idy < N) {
for (int i=0; i < TILE_DIM; i++) {
temp_result += s_a[threadIdx.y][i] *
s_b[i][threadIdx.x];
}
}
__syncthreads();
}
__syncthreads();
if(idx < N && idy < N) {
c[pos] = temp_result;
}
}
int main (int argc, char* argv[]){
int N = 4;
size_t size = N*N*sizeof(int);
int num_thread, num_block;
int *h_a, *h_b, *h_c;
h_a = (int*)malloc(size);
h_b = (int*)malloc(size);
h_c = (int*)malloc(size);
int *d_a, *d_b, *d_c;
cudaMalloc(&d_a, size);
cudaMalloc(&d_b, size);
cudaMalloc(&d_c, size);
int i = 0, j = 0;
for (i = 0; i < N*N; i++){
h_a[i] = h_b[i] = i;
}
cudaMemcpy(d_a,h_a,size,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,h_b,size,cudaMemcpyHostToDevice);
cudaMemset(d_c,0,size);
num_block = ceil((float)N/TILE_DIM);
num_thread = N < TILE_DIM ? N : TILE_DIM;
printf("Blocks: %d Threads: %d \n", num_block, num_thread);
dim3 gridsize(num_block,num_block,1);
dim3 blocksize(num_thread,num_thread,1);
multiMatrix<<<gridsize,blocksize>>>(d_a, d_b, d_c, N);
cudaMemcpy(h_c, d_c, size, cudaMemcpyDeviceToHost);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
free(h_a);
free(h_b);
free(h_c);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define TILE_DIM 16
__global__ void multiMatrix (int *a, int *b, int *c, int N) {
int idx = threadIdx.x + blockDim.x * blockIdx.x;
int idy = threadIdx.y + blockDim.y * blockIdx.y;
int pos = idx + idy * N;
int temp_result = 0;
int posa, posb;
__shared__ int s_a[TILE_DIM][TILE_DIM];
__shared__ int s_b[TILE_DIM][TILE_DIM];
for (int tile_idx = 0; tile_idx < gridDim.x; tile_idx++)
{
posa = idy * N + (tile_idx * TILE_DIM + threadIdx.x);
posb = (tile_idx * TILE_DIM + threadIdx.y) * N + idx;
if (posa < N*N) {
s_a[threadIdx.y][threadIdx.x] = a[posa];
} else {
s_a[threadIdx.y][threadIdx.x] = 0;
}
if (posb < N*N) {
s_b[threadIdx.y][threadIdx.x] = b[posb];
} else {
s_b[threadIdx.y][threadIdx.x] = 0;
}
__syncthreads();
if (idx < N && idy < N) {
for (int i=0; i < TILE_DIM; i++) {
temp_result += s_a[threadIdx.y][i] *
s_b[i][threadIdx.x];
}
}
__syncthreads();
}
__syncthreads();
if(idx < N && idy < N) {
c[pos] = temp_result;
}
}
int main (int argc, char* argv[]){
int N = 4;
size_t size = N*N*sizeof(int);
int num_thread, num_block;
int *h_a, *h_b, *h_c;
h_a = (int*)malloc(size);
h_b = (int*)malloc(size);
h_c = (int*)malloc(size);
int *d_a, *d_b, *d_c;
hipMalloc(&d_a, size);
hipMalloc(&d_b, size);
hipMalloc(&d_c, size);
int i = 0, j = 0;
for (i = 0; i < N*N; i++){
h_a[i] = h_b[i] = i;
}
hipMemcpy(d_a,h_a,size,hipMemcpyHostToDevice);
hipMemcpy(d_b,h_b,size,hipMemcpyHostToDevice);
hipMemset(d_c,0,size);
num_block = ceil((float)N/TILE_DIM);
num_thread = N < TILE_DIM ? N : TILE_DIM;
printf("Blocks: %d Threads: %d \n", num_block, num_thread);
dim3 gridsize(num_block,num_block,1);
dim3 blocksize(num_thread,num_thread,1);
multiMatrix<<<gridsize,blocksize>>>(d_a, d_b, d_c, N);
hipMemcpy(h_c, d_c, size, hipMemcpyDeviceToHost);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
free(h_a);
free(h_b);
free(h_c);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define TILE_DIM 16
__global__ void multiMatrix (int *a, int *b, int *c, int N) {
int idx = threadIdx.x + blockDim.x * blockIdx.x;
int idy = threadIdx.y + blockDim.y * blockIdx.y;
int pos = idx + idy * N;
int temp_result = 0;
int posa, posb;
__shared__ int s_a[TILE_DIM][TILE_DIM];
__shared__ int s_b[TILE_DIM][TILE_DIM];
for (int tile_idx = 0; tile_idx < gridDim.x; tile_idx++)
{
posa = idy * N + (tile_idx * TILE_DIM + threadIdx.x);
posb = (tile_idx * TILE_DIM + threadIdx.y) * N + idx;
if (posa < N*N) {
s_a[threadIdx.y][threadIdx.x] = a[posa];
} else {
s_a[threadIdx.y][threadIdx.x] = 0;
}
if (posb < N*N) {
s_b[threadIdx.y][threadIdx.x] = b[posb];
} else {
s_b[threadIdx.y][threadIdx.x] = 0;
}
__syncthreads();
if (idx < N && idy < N) {
for (int i=0; i < TILE_DIM; i++) {
temp_result += s_a[threadIdx.y][i] *
s_b[i][threadIdx.x];
}
}
__syncthreads();
}
__syncthreads();
if(idx < N && idy < N) {
c[pos] = temp_result;
}
}
int main (int argc, char* argv[]){
int N = 4;
size_t size = N*N*sizeof(int);
int num_thread, num_block;
int *h_a, *h_b, *h_c;
h_a = (int*)malloc(size);
h_b = (int*)malloc(size);
h_c = (int*)malloc(size);
int *d_a, *d_b, *d_c;
hipMalloc(&d_a, size);
hipMalloc(&d_b, size);
hipMalloc(&d_c, size);
int i = 0, j = 0;
for (i = 0; i < N*N; i++){
h_a[i] = h_b[i] = i;
}
hipMemcpy(d_a,h_a,size,hipMemcpyHostToDevice);
hipMemcpy(d_b,h_b,size,hipMemcpyHostToDevice);
hipMemset(d_c,0,size);
num_block = ceil((float)N/TILE_DIM);
num_thread = N < TILE_DIM ? N : TILE_DIM;
printf("Blocks: %d Threads: %d \n", num_block, num_thread);
dim3 gridsize(num_block,num_block,1);
dim3 blocksize(num_thread,num_thread,1);
multiMatrix<<<gridsize,blocksize>>>(d_a, d_b, d_c, N);
hipMemcpy(h_c, d_c, size, hipMemcpyDeviceToHost);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
free(h_a);
free(h_b);
free(h_c);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11multiMatrixPiS_S_i
.globl _Z11multiMatrixPiS_S_i
.p2align 8
.type _Z11multiMatrixPiS_S_i,@function
_Z11multiMatrixPiS_S_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_load_b32 s8, s[0:1], 0x20
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_mov_b32 s9, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[4:5], null, s15, s4, v[2:3]
s_cmp_eq_u32 s8, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[0:1], null, s14, s2, v[3:4]
v_mul_lo_u32 v5, v4, s3
v_mov_b32_e32 v1, 0
v_max_i32_e32 v6, v0, v4
s_cbranch_scc1 .LBB0_14
s_load_b128 s[4:7], s[0:1], 0x0
v_dual_mov_b32 v12, 0 :: v_dual_lshlrev_b32 v1, 2, v3
v_lshlrev_b32_e32 v7, 6, v2
v_add_nc_u32_e32 v9, v5, v3
v_cmp_gt_i32_e32 vcc_lo, s3, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v8, 0x400, v1
s_mul_i32 s10, s3, s3
v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v10, v7, v1
v_add_nc_u32_e32 v11, v8, v7
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_add_i32 s9, s9, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s9, s8
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_14
.LBB0_3:
s_lshl_b32 s11, s9, 4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, s11, v9
v_cmp_le_i32_e64 s2, s10, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s12, s2
s_xor_b32 s2, exec_lo, s12
s_cbranch_execz .LBB0_5
ds_store_b32 v10, v12
.LBB0_5:
s_and_not1_saveexec_b32 s12, s2
s_cbranch_execz .LBB0_7
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, s2, s4, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s2, s5, v4, s2
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
ds_store_b32 v10, v3
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s12
v_add_nc_u32_e32 v13, s11, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v13, s3, v[0:1]
v_cmp_le_i32_e64 s2, s10, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s11, s2
s_xor_b32 s2, exec_lo, s11
s_cbranch_execz .LBB0_9
ds_store_b32 v11, v12
.LBB0_9:
s_and_not1_saveexec_b32 s11, s2
s_cbranch_execz .LBB0_11
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, s2, s6, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s2, s7, v4, s2
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
ds_store_b32 v11, v3
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v3, v8
s_mov_b32 s11, 0
.LBB0_13:
s_delay_alu instid0(SALU_CYCLE_1)
v_add_nc_u32_e32 v4, s11, v7
s_add_i32 s11, s11, 4
ds_load_b32 v15, v3
ds_load_b32 v4, v4
v_add_nc_u32_e32 v3, 64, v3
s_cmp_lg_u32 s11, 64
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[13:14], null, v15, v4, v[1:2]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v1, v13
s_cbranch_scc1 .LBB0_13
s_branch .LBB0_2
.LBB0_14:
s_barrier
buffer_gl0_inv
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v6
s_cbranch_execz .LBB0_16
s_load_b64 s[0:1], s[0:1], 0x10
v_add_nc_u32_e32 v2, v5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
.LBB0_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11multiMatrixPiS_S_i
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11multiMatrixPiS_S_i, .Lfunc_end0-_Z11multiMatrixPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11multiMatrixPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11multiMatrixPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define TILE_DIM 16
__global__ void multiMatrix (int *a, int *b, int *c, int N) {
int idx = threadIdx.x + blockDim.x * blockIdx.x;
int idy = threadIdx.y + blockDim.y * blockIdx.y;
int pos = idx + idy * N;
int temp_result = 0;
int posa, posb;
__shared__ int s_a[TILE_DIM][TILE_DIM];
__shared__ int s_b[TILE_DIM][TILE_DIM];
for (int tile_idx = 0; tile_idx < gridDim.x; tile_idx++)
{
posa = idy * N + (tile_idx * TILE_DIM + threadIdx.x);
posb = (tile_idx * TILE_DIM + threadIdx.y) * N + idx;
if (posa < N*N) {
s_a[threadIdx.y][threadIdx.x] = a[posa];
} else {
s_a[threadIdx.y][threadIdx.x] = 0;
}
if (posb < N*N) {
s_b[threadIdx.y][threadIdx.x] = b[posb];
} else {
s_b[threadIdx.y][threadIdx.x] = 0;
}
__syncthreads();
if (idx < N && idy < N) {
for (int i=0; i < TILE_DIM; i++) {
temp_result += s_a[threadIdx.y][i] *
s_b[i][threadIdx.x];
}
}
__syncthreads();
}
__syncthreads();
if(idx < N && idy < N) {
c[pos] = temp_result;
}
}
int main (int argc, char* argv[]){
int N = 4;
size_t size = N*N*sizeof(int);
int num_thread, num_block;
int *h_a, *h_b, *h_c;
h_a = (int*)malloc(size);
h_b = (int*)malloc(size);
h_c = (int*)malloc(size);
int *d_a, *d_b, *d_c;
hipMalloc(&d_a, size);
hipMalloc(&d_b, size);
hipMalloc(&d_c, size);
int i = 0, j = 0;
for (i = 0; i < N*N; i++){
h_a[i] = h_b[i] = i;
}
hipMemcpy(d_a,h_a,size,hipMemcpyHostToDevice);
hipMemcpy(d_b,h_b,size,hipMemcpyHostToDevice);
hipMemset(d_c,0,size);
num_block = ceil((float)N/TILE_DIM);
num_thread = N < TILE_DIM ? N : TILE_DIM;
printf("Blocks: %d Threads: %d \n", num_block, num_thread);
dim3 gridsize(num_block,num_block,1);
dim3 blocksize(num_thread,num_thread,1);
multiMatrix<<<gridsize,blocksize>>>(d_a, d_b, d_c, N);
hipMemcpy(h_c, d_c, size, hipMemcpyDeviceToHost);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
free(h_a);
free(h_b);
free(h_c);
} | .text
.file "mult_matrix.hip"
.globl _Z26__device_stub__multiMatrixPiS_S_i # -- Begin function _Z26__device_stub__multiMatrixPiS_S_i
.p2align 4, 0x90
.type _Z26__device_stub__multiMatrixPiS_S_i,@function
_Z26__device_stub__multiMatrixPiS_S_i: # @_Z26__device_stub__multiMatrixPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11multiMatrixPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__multiMatrixPiS_S_i, .Lfunc_end0-_Z26__device_stub__multiMatrixPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $64, %edi
callq malloc
movq %rax, %rbx
movl $64, %edi
callq malloc
movq %rax, %r14
movl $64, %edi
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movl $64, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $64, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%r14,%rax,4)
movl %eax, (%rbx,%rax,4)
incq %rax
cmpq $16, %rax
jne .LBB1_1
# %bb.2:
movq 24(%rsp), %rdi
movl $64, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $64, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $64, %edx
xorl %esi, %esi
callq hipMemset
movl $.L.str, %edi
movl $1, %esi
movl $4, %edx
xorl %eax, %eax
callq printf
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $17179869188, %rdx # imm = 0x400000004
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $4, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11multiMatrixPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $64, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11multiMatrixPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11multiMatrixPiS_S_i,@object # @_Z11multiMatrixPiS_S_i
.section .rodata,"a",@progbits
.globl _Z11multiMatrixPiS_S_i
.p2align 3, 0x0
_Z11multiMatrixPiS_S_i:
.quad _Z26__device_stub__multiMatrixPiS_S_i
.size _Z11multiMatrixPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Blocks: %d Threads: %d \n"
.size .L.str, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11multiMatrixPiS_S_i"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__multiMatrixPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11multiMatrixPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11multiMatrixPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0xc], PT ; /* 0x00000300ff007a0c */
/* 0x000fe20003f05270 */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0060*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e680000002600 */
/*0070*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0080*/ IMAD R2, R3, c[0x0][0x0], R0 ; /* 0x0000000003027a24 */
/* 0x001fc400078e0200 */
/*0090*/ IMAD R3, R4, c[0x0][0x4], R5 ; /* 0x0000010004037a24 */
/* 0x002fe200078e0205 */
/*00a0*/ @!P0 BRA 0x500 ; /* 0x0000045000008947 */
/* 0x000fea0003800000 */
/*00b0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*00c0*/ IMAD R16, R5.reuse, c[0x0][0x178], R2 ; /* 0x00005e0005107a24 */
/* 0x040fe200078e0202 */
/*00d0*/ SHF.L.U32 R17, R5, 0x6, RZ ; /* 0x0000000605117819 */
/* 0x000fe200000006ff */
/*00e0*/ IMAD R18, R3, c[0x0][0x178], R0 ; /* 0x00005e0003127a24 */
/* 0x000fe200078e0200 */
/*00f0*/ ISETP.LT.AND P0, PT, R2, c[0x0][0x178], !P0 ; /* 0x00005e0002007a0c */
/* 0x000fe20004701270 */
/*0100*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000800 */
/*0110*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe20000000f00 */
/*0120*/ UIMAD UR4, UR4, UR4, URZ ; /* 0x00000004040472a4 */
/* 0x000fe2000f8e023f */
/*0130*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fe40000000f00 */
/*0140*/ LEA R19, R0, R17, 0x2 ; /* 0x0000001100137211 */
/* 0x000fc600078e10ff */
/*0150*/ ISETP.GE.AND P1, PT, R18, UR4, PT ; /* 0x0000000412007c0c */
/* 0x000fe2000bf26270 */
/*0160*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x000fe200000001ff */
/*0170*/ ISETP.GE.AND P2, PT, R16, UR4, PT ; /* 0x0000000410007c0c */
/* 0x000fc4000bf46270 */
/*0180*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fd20000000f00 */
/*0190*/ @!P1 MOV R5, 0x4 ; /* 0x0000000400059802 */
/* 0x000fe40000000f00 */
/*01a0*/ @!P2 MOV R7, 0x4 ; /* 0x000000040007a802 */
/* 0x000fc60000000f00 */
/*01b0*/ @!P1 IMAD.WIDE R4, R18, R5, c[0x0][0x160] ; /* 0x0000580012049625 */
/* 0x000fc800078e0205 */
/*01c0*/ @!P2 IMAD.WIDE R6, R16, R7, c[0x0][0x168] ; /* 0x00005a001006a625 */
/* 0x000fe200078e0207 */
/*01d0*/ @!P1 LDG.E R8, [R4.64] ; /* 0x0000000604089981 */
/* 0x000ea8000c1e1900 */
/*01e0*/ @!P2 LDG.E R10, [R6.64] ; /* 0x00000006060aa981 */
/* 0x000ee2000c1e1900 */
/*01f0*/ BSSY B0, 0x490 ; /* 0x0000029000007945 */
/* 0x000fe60003800000 */
/*0200*/ STS [R19], R8 ; /* 0x0000000813007388 */
/* 0x0041e80000000800 */
/*0210*/ STS [R19+0x400], R10 ; /* 0x0004000a13007388 */
/* 0x0081e80000000800 */
/*0220*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0230*/ @!P0 BRA 0x480 ; /* 0x0000024000008947 */
/* 0x000fea0003800000 */
/*0240*/ LDS R8, [R0.X4+0x400] ; /* 0x0004000000087984 */
/* 0x001fe80000004800 */
/*0250*/ LDS.128 R12, [R17] ; /* 0x00000000110c7984 */
/* 0x000e280000000c00 */
/*0260*/ LDS R10, [R0.X4+0x440] ; /* 0x00044000000a7984 */
/* 0x000e680000004800 */
/*0270*/ LDS R11, [R0.X4+0x480] ; /* 0x00048000000b7984 */
/* 0x000ea80000004800 */
/*0280*/ LDS R22, [R0.X4+0x4c0] ; /* 0x0004c00000167984 */
/* 0x000ee80000004800 */
/*0290*/ LDS R25, [R0.X4+0x500] ; /* 0x0005000000197984 */
/* 0x000fe80000004800 */
/*02a0*/ LDS.128 R4, [R17+0x10] ; /* 0x0000100011047984 */
/* 0x000f280000000c00 */
/*02b0*/ LDS R26, [R0.X4+0x540] ; /* 0x00054000001a7984 */
/* 0x000f680000004800 */
/*02c0*/ LDS R23, [R0.X4+0x580] ; /* 0x0005800000177984 */
/* 0x000f680000004800 */
/*02d0*/ LDS R20, [R0.X4+0x5c0] ; /* 0x0005c00000147984 */
/* 0x000f680000004800 */
/*02e0*/ LDS R21, [R0.X4+0x600] ; /* 0x0006000000157984 */
/* 0x000fe20000004800 */
/*02f0*/ IMAD R8, R12, R8, R9 ; /* 0x000000080c087224 */
/* 0x001fc800078e0209 */
/*0300*/ IMAD R13, R10, R13, R8 ; /* 0x0000000d0a0d7224 */
/* 0x002fc800078e0208 */
/*0310*/ IMAD R13, R11, R14, R13 ; /* 0x0000000e0b0d7224 */
/* 0x004fe400078e020d */
/*0320*/ LDS.128 R8, [R17+0x20] ; /* 0x0000200011087984 */
/* 0x000e240000000c00 */
/*0330*/ IMAD R13, R22, R15, R13 ; /* 0x0000000f160d7224 */
/* 0x008fe400078e020d */
/*0340*/ LDS R22, [R0.X4+0x640] ; /* 0x0006400000167984 */
/* 0x000e640000004800 */
/*0350*/ IMAD R4, R25, R4, R13 ; /* 0x0000000419047224 */
/* 0x010fe400078e020d */
/*0360*/ LDS R25, [R0.X4+0x680] ; /* 0x0006800000197984 */
/* 0x000ea40000004800 */
/*0370*/ IMAD R5, R26, R5, R4 ; /* 0x000000051a057224 */
/* 0x020fc400078e0204 */
/*0380*/ LDS R4, [R0.X4+0x6c0] ; /* 0x0006c00000047984 */
/* 0x000ee40000004800 */
/*0390*/ IMAD R23, R23, R6, R5 ; /* 0x0000000617177224 */
/* 0x000fe400078e0205 */
/*03a0*/ LDS R5, [R0.X4+0x700] ; /* 0x0007000000057984 */
/* 0x000fe40000004800 */
/*03b0*/ IMAD R23, R20, R7, R23 ; /* 0x0000000714177224 */
/* 0x000fe400078e0217 */
/*03c0*/ LDS.128 R12, [R17+0x30] ; /* 0x00003000110c7984 */
/* 0x000f280000000c00 */
/*03d0*/ LDS R6, [R0.X4+0x740] ; /* 0x0007400000067984 */
/* 0x000f680000004800 */
/*03e0*/ LDS R7, [R0.X4+0x780] ; /* 0x0007800000077984 */
/* 0x000f680000004800 */
/*03f0*/ LDS R20, [R0.X4+0x7c0] ; /* 0x0007c00000147984 */
/* 0x000f620000004800 */
/*0400*/ IMAD R8, R21, R8, R23 ; /* 0x0000000815087224 */
/* 0x001fc800078e0217 */
/*0410*/ IMAD R8, R22, R9, R8 ; /* 0x0000000916087224 */
/* 0x002fc800078e0208 */
/*0420*/ IMAD R8, R25, R10, R8 ; /* 0x0000000a19087224 */
/* 0x004fc800078e0208 */
/*0430*/ IMAD R4, R4, R11, R8 ; /* 0x0000000b04047224 */
/* 0x008fc800078e0208 */
/*0440*/ IMAD R4, R5, R12, R4 ; /* 0x0000000c05047224 */
/* 0x010fc800078e0204 */
/*0450*/ IMAD R4, R6, R13, R4 ; /* 0x0000000d06047224 */
/* 0x020fc800078e0204 */
/*0460*/ IMAD R4, R7, R14, R4 ; /* 0x0000000e07047224 */
/* 0x000fc800078e0204 */
/*0470*/ IMAD R9, R20, R15, R4 ; /* 0x0000000f14097224 */
/* 0x000fe400078e0204 */
/*0480*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0490*/ IADD3 R24, R24, 0x1, RZ ; /* 0x0000000118187810 */
/* 0x000fe20007ffe0ff */
/*04a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*04b0*/ MOV R5, c[0x0][0x178] ; /* 0x00005e0000057a02 */
/* 0x000fe40000000f00 */
/*04c0*/ ISETP.GE.U32.AND P1, PT, R24, c[0x0][0xc], PT ; /* 0x0000030018007a0c */
/* 0x000fe40003f26070 */
/*04d0*/ LEA R16, R5, R16, 0x4 ; /* 0x0000001005107211 */
/* 0x000fe400078e20ff */
/*04e0*/ IADD3 R18, R18, 0x10, RZ ; /* 0x0000001012127810 */
/* 0x000fd20007ffe0ff */
/*04f0*/ @!P1 BRA 0x150 ; /* 0xfffffc5000009947 */
/* 0x000fea000383ffff */
/*0500*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0510*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fc80003f06270 */
/*0520*/ ISETP.GE.OR P0, PT, R2, c[0x0][0x178], P0 ; /* 0x00005e0002007a0c */
/* 0x000fda0000706670 */
/*0530*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0540*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0550*/ IMAD R2, R3, c[0x0][0x178], R2 ; /* 0x00005e0003027a24 */
/* 0x000fd200078e0202 */
/*0560*/ IMAD.WIDE R2, R2, R5, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0205 */
/*0570*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101906 */
/*0580*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0590*/ BRA 0x590; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11multiMatrixPiS_S_i
.globl _Z11multiMatrixPiS_S_i
.p2align 8
.type _Z11multiMatrixPiS_S_i,@function
_Z11multiMatrixPiS_S_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_load_b32 s8, s[0:1], 0x20
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_mov_b32 s9, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[4:5], null, s15, s4, v[2:3]
s_cmp_eq_u32 s8, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[0:1], null, s14, s2, v[3:4]
v_mul_lo_u32 v5, v4, s3
v_mov_b32_e32 v1, 0
v_max_i32_e32 v6, v0, v4
s_cbranch_scc1 .LBB0_14
s_load_b128 s[4:7], s[0:1], 0x0
v_dual_mov_b32 v12, 0 :: v_dual_lshlrev_b32 v1, 2, v3
v_lshlrev_b32_e32 v7, 6, v2
v_add_nc_u32_e32 v9, v5, v3
v_cmp_gt_i32_e32 vcc_lo, s3, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v8, 0x400, v1
s_mul_i32 s10, s3, s3
v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v10, v7, v1
v_add_nc_u32_e32 v11, v8, v7
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_add_i32 s9, s9, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s9, s8
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_14
.LBB0_3:
s_lshl_b32 s11, s9, 4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, s11, v9
v_cmp_le_i32_e64 s2, s10, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s12, s2
s_xor_b32 s2, exec_lo, s12
s_cbranch_execz .LBB0_5
ds_store_b32 v10, v12
.LBB0_5:
s_and_not1_saveexec_b32 s12, s2
s_cbranch_execz .LBB0_7
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, s2, s4, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s2, s5, v4, s2
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
ds_store_b32 v10, v3
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s12
v_add_nc_u32_e32 v13, s11, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v13, s3, v[0:1]
v_cmp_le_i32_e64 s2, s10, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s11, s2
s_xor_b32 s2, exec_lo, s11
s_cbranch_execz .LBB0_9
ds_store_b32 v11, v12
.LBB0_9:
s_and_not1_saveexec_b32 s11, s2
s_cbranch_execz .LBB0_11
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, s2, s6, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s2, s7, v4, s2
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
ds_store_b32 v11, v3
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v3, v8
s_mov_b32 s11, 0
.LBB0_13:
s_delay_alu instid0(SALU_CYCLE_1)
v_add_nc_u32_e32 v4, s11, v7
s_add_i32 s11, s11, 4
ds_load_b32 v15, v3
ds_load_b32 v4, v4
v_add_nc_u32_e32 v3, 64, v3
s_cmp_lg_u32 s11, 64
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[13:14], null, v15, v4, v[1:2]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v1, v13
s_cbranch_scc1 .LBB0_13
s_branch .LBB0_2
.LBB0_14:
s_barrier
buffer_gl0_inv
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v6
s_cbranch_execz .LBB0_16
s_load_b64 s[0:1], s[0:1], 0x10
v_add_nc_u32_e32 v2, v5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
.LBB0_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11multiMatrixPiS_S_i
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11multiMatrixPiS_S_i, .Lfunc_end0-_Z11multiMatrixPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11multiMatrixPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11multiMatrixPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00017ccb_00000000-6_mult_matrix.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z11multiMatrixPiS_S_iPiS_S_i
.type _Z36__device_stub__Z11multiMatrixPiS_S_iPiS_S_i, @function
_Z36__device_stub__Z11multiMatrixPiS_S_iPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11multiMatrixPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z36__device_stub__Z11multiMatrixPiS_S_iPiS_S_i, .-_Z36__device_stub__Z11multiMatrixPiS_S_iPiS_S_i
.globl _Z11multiMatrixPiS_S_i
.type _Z11multiMatrixPiS_S_i, @function
_Z11multiMatrixPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11multiMatrixPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11multiMatrixPiS_S_i, .-_Z11multiMatrixPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Blocks: %d Threads: %d \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $64, %edi
call malloc@PLT
movq %rax, %rbp
movl $64, %edi
call malloc@PLT
movq %rax, %rbx
movl $64, %edi
call malloc@PLT
movq %rax, %r12
leaq 8(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
movl %eax, (%rbx,%rax,4)
movl %eax, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $16, %rax
jne .L12
movl $1, %ecx
movl $64, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $64, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $64, %edx
movl $0, %esi
movq 24(%rsp), %rdi
call cudaMemset@PLT
movl $4, %ecx
movl $1, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $4, 44(%rsp)
movl $4, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movl $2, %ecx
movl $64, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl $4, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z36__device_stub__Z11multiMatrixPiS_S_iPiS_S_i
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z11multiMatrixPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z11multiMatrixPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mult_matrix.hip"
.globl _Z26__device_stub__multiMatrixPiS_S_i # -- Begin function _Z26__device_stub__multiMatrixPiS_S_i
.p2align 4, 0x90
.type _Z26__device_stub__multiMatrixPiS_S_i,@function
_Z26__device_stub__multiMatrixPiS_S_i: # @_Z26__device_stub__multiMatrixPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11multiMatrixPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__multiMatrixPiS_S_i, .Lfunc_end0-_Z26__device_stub__multiMatrixPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $64, %edi
callq malloc
movq %rax, %rbx
movl $64, %edi
callq malloc
movq %rax, %r14
movl $64, %edi
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movl $64, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $64, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%r14,%rax,4)
movl %eax, (%rbx,%rax,4)
incq %rax
cmpq $16, %rax
jne .LBB1_1
# %bb.2:
movq 24(%rsp), %rdi
movl $64, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $64, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $64, %edx
xorl %esi, %esi
callq hipMemset
movl $.L.str, %edi
movl $1, %esi
movl $4, %edx
xorl %eax, %eax
callq printf
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $17179869188, %rdx # imm = 0x400000004
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $4, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11multiMatrixPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $64, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11multiMatrixPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11multiMatrixPiS_S_i,@object # @_Z11multiMatrixPiS_S_i
.section .rodata,"a",@progbits
.globl _Z11multiMatrixPiS_S_i
.p2align 3, 0x0
_Z11multiMatrixPiS_S_i:
.quad _Z26__device_stub__multiMatrixPiS_S_i
.size _Z11multiMatrixPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Blocks: %d Threads: %d \n"
.size .L.str, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11multiMatrixPiS_S_i"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__multiMatrixPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11multiMatrixPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
// 这个是kernel函数，就是GPU函数
__global__ void kernelfunction(int*a,int*b,int*c){
*c=*a+*b;
}
int main(void){
printf("Cuda_Performance Hello World\n");
int a,b,c;
int *d_a,*d_b,*d_c;
int size =sizeof(int);
// take the address of d_a,and cast into void**
// 取d_a的地址（一个二级指针），然后类型转换成void**
// Create Status for error check
// 这个是为了错误检查
cudaError_t cudastatus;
// Allocate space for device
// 分配gpu内存
cudastatus=cudaMalloc((void **)&d_a, size);
cudastatus=cudaMalloc((void **)&d_b, size);
cudastatus=cudaMalloc((void **)&d_c, size);
a = 1;
b = 2;
// Start Timing
// 计时模块
cudaEvent_t start, stop;
float timeall;
cudastatus=cudaEventCreate(&start);
cudastatus=cudaEventCreate(&stop);
cudastatus=cudaEventRecord( start, 0 );
// CopyToGPU
// 上传到GPU
cudastatus=cudaMemcpy(d_a,&a,size,cudaMemcpyHostToDevice);
cudastatus=cudaMemcpy(d_b,&b,size,cudaMemcpyHostToDevice);
kernelfunction<<<1,1>>>(d_a,d_b,d_c);
cudastatus=cudaMemcpy(&c,d_c,size,cudaMemcpyDeviceToHost);
// Timing
// 计时结束
cudastatus=cudaEventRecord( stop, 0 );
cudastatus=cudaEventSynchronize( stop );
cudastatus=cudaEventElapsedTime( &timeall, start, stop );
cudastatus=cudaEventDestroy( start );
cudastatus=cudaEventDestroy( stop );
printf("c:%i \n",c);
printf("time:%f \n",timeall);
// 释放内存
cudastatus=cudaFree(d_a);
cudastatus=cudaFree(d_b);
cudastatus=cudaFree(d_c);
if (cudastatus != cudaSuccess) {
fprintf(stderr, "Failed %s\n", cudaGetErrorString(cudastatus));
}
return 0;
} | code for sm_80
Function : _Z14kernelfunctionPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe200078e00ff */
/*0090*/ MOV R7, c[0x0][0x174] ; /* 0x00005d0000077a02 */
/* 0x000fe40000000f00 */
/*00a0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00b0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
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