system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
// 这个是kernel函数，就是GPU函数
__global__ void kernelfunction(int*a,int*b,int*c){
*c=*a+*b;
}
int main(void){
printf("Cuda_Performance Hello World\n");
int a,b,c;
int *d_a,*d_b,*d_c;
int size =sizeof(int);
// take the address of d_a,and cast into void**
// 取d_a的地址（一个二级指针），然后类型转换成void**
// Create Status for error check
// 这个是为了错误检查
cudaError_t cudastatus;
// Allocate space for device
// 分配gpu内存
cudastatus=cudaMalloc((void **)&d_a, size);
cudastatus=cudaMalloc((void **)&d_b, size);
cudastatus=cudaMalloc((void **)&d_c, size);
a = 1;
b = 2;
// Start Timing
// 计时模块
cudaEvent_t start, stop;
float timeall;
cudastatus=cudaEventCreate(&start);
cudastatus=cudaEventCreate(&stop);
cudastatus=cudaEventRecord( start, 0 );
// CopyToGPU
// 上传到GPU
cudastatus=cudaMemcpy(d_a,&a,size,cudaMemcpyHostToDevice);
cudastatus=cudaMemcpy(d_b,&b,size,cudaMemcpyHostToDevice);
kernelfunction<<<1,1>>>(d_a,d_b,d_c);
cudastatus=cudaMemcpy(&c,d_c,size,cudaMemcpyDeviceToHost);
// Timing
// 计时结束
cudastatus=cudaEventRecord( stop, 0 );
cudastatus=cudaEventSynchronize( stop );
cudastatus=cudaEventElapsedTime( &timeall, start, stop );
cudastatus=cudaEventDestroy( start );
cudastatus=cudaEventDestroy( stop );
printf("c:%i \n",c);
printf("time:%f \n",timeall);
// 释放内存
cudastatus=cudaFree(d_a);
cudastatus=cudaFree(d_b);
cudastatus=cudaFree(d_c);
if (cudastatus != cudaSuccess) {
fprintf(stderr, "Failed %s\n", cudaGetErrorString(cudastatus));
}
return 0;
} | .file "tmpxft_0019dbea_00000000-6_1_cuda_performance_hello_world.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z14kernelfunctionPiS_S_PiS_S_
.type _Z38__device_stub__Z14kernelfunctionPiS_S_PiS_S_, @function
_Z38__device_stub__Z14kernelfunctionPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14kernelfunctionPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z38__device_stub__Z14kernelfunctionPiS_S_PiS_S_, .-_Z38__device_stub__Z14kernelfunctionPiS_S_PiS_S_
.globl _Z14kernelfunctionPiS_S_
.type _Z14kernelfunctionPiS_S_, @function
_Z14kernelfunctionPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14kernelfunctionPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z14kernelfunctionPiS_S_, .-_Z14kernelfunctionPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Cuda_Performance Hello World\n"
.LC1:
.string "c:%i \n"
.LC2:
.string "time:%f \n"
.LC3:
.string "Failed %s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, (%rsp)
movl $2, 4(%rsp)
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq %rsp, %rsi
movl $1, %ecx
movl $4, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
leaq 48(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 60(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movl 48(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 60(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L17
.L13:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z38__device_stub__Z14kernelfunctionPiS_S_PiS_S_
jmp .L12
.L17:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z14kernelfunctionPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z14kernelfunctionPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
// 这个是kernel函数，就是GPU函数
__global__ void kernelfunction(int*a,int*b,int*c){
*c=*a+*b;
}
int main(void){
printf("Cuda_Performance Hello World\n");
int a,b,c;
int *d_a,*d_b,*d_c;
int size =sizeof(int);
// take the address of d_a,and cast into void**
// 取d_a的地址（一个二级指针），然后类型转换成void**
// Create Status for error check
// 这个是为了错误检查
cudaError_t cudastatus;
// Allocate space for device
// 分配gpu内存
cudastatus=cudaMalloc((void **)&d_a, size);
cudastatus=cudaMalloc((void **)&d_b, size);
cudastatus=cudaMalloc((void **)&d_c, size);
a = 1;
b = 2;
// Start Timing
// 计时模块
cudaEvent_t start, stop;
float timeall;
cudastatus=cudaEventCreate(&start);
cudastatus=cudaEventCreate(&stop);
cudastatus=cudaEventRecord( start, 0 );
// CopyToGPU
// 上传到GPU
cudastatus=cudaMemcpy(d_a,&a,size,cudaMemcpyHostToDevice);
cudastatus=cudaMemcpy(d_b,&b,size,cudaMemcpyHostToDevice);
kernelfunction<<<1,1>>>(d_a,d_b,d_c);
cudastatus=cudaMemcpy(&c,d_c,size,cudaMemcpyDeviceToHost);
// Timing
// 计时结束
cudastatus=cudaEventRecord( stop, 0 );
cudastatus=cudaEventSynchronize( stop );
cudastatus=cudaEventElapsedTime( &timeall, start, stop );
cudastatus=cudaEventDestroy( start );
cudastatus=cudaEventDestroy( stop );
printf("c:%i \n",c);
printf("time:%f \n",timeall);
// 释放内存
cudastatus=cudaFree(d_a);
cudastatus=cudaFree(d_b);
cudastatus=cudaFree(d_c);
if (cudastatus != cudaSuccess) {
fprintf(stderr, "Failed %s\n", cudaGetErrorString(cudastatus));
}
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
// 这个是kernel函数，就是GPU函数
__global__ void kernelfunction(int*a,int*b,int*c){
*c=*a+*b;
}
int main(void){
printf("Cuda_Performance Hello World\n");
int a,b,c;
int *d_a,*d_b,*d_c;
int size =sizeof(int);
// take the address of d_a,and cast into void**
// 取d_a的地址（一个二级指针），然后类型转换成void**
// Create Status for error check
// 这个是为了错误检查
hipError_t cudastatus;
// Allocate space for device
// 分配gpu内存
cudastatus=hipMalloc((void **)&d_a, size);
cudastatus=hipMalloc((void **)&d_b, size);
cudastatus=hipMalloc((void **)&d_c, size);
a = 1;
b = 2;
// Start Timing
// 计时模块
hipEvent_t start, stop;
float timeall;
cudastatus=hipEventCreate(&start);
cudastatus=hipEventCreate(&stop);
cudastatus=hipEventRecord( start, 0 );
// CopyToGPU
// 上传到GPU
cudastatus=hipMemcpy(d_a,&a,size,hipMemcpyHostToDevice);
cudastatus=hipMemcpy(d_b,&b,size,hipMemcpyHostToDevice);
kernelfunction<<<1,1>>>(d_a,d_b,d_c);
cudastatus=hipMemcpy(&c,d_c,size,hipMemcpyDeviceToHost);
// Timing
// 计时结束
cudastatus=hipEventRecord( stop, 0 );
cudastatus=hipEventSynchronize( stop );
cudastatus=hipEventElapsedTime( &timeall, start, stop );
cudastatus=hipEventDestroy( start );
cudastatus=hipEventDestroy( stop );
printf("c:%i \n",c);
printf("time:%f \n",timeall);
// 释放内存
cudastatus=hipFree(d_a);
cudastatus=hipFree(d_b);
cudastatus=hipFree(d_c);
if (cudastatus != hipSuccess) {
fprintf(stderr, "Failed %s\n", hipGetErrorString(cudastatus));
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
// 这个是kernel函数，就是GPU函数
__global__ void kernelfunction(int*a,int*b,int*c){
*c=*a+*b;
}
int main(void){
printf("Cuda_Performance Hello World\n");
int a,b,c;
int *d_a,*d_b,*d_c;
int size =sizeof(int);
// take the address of d_a,and cast into void**
// 取d_a的地址（一个二级指针），然后类型转换成void**
// Create Status for error check
// 这个是为了错误检查
hipError_t cudastatus;
// Allocate space for device
// 分配gpu内存
cudastatus=hipMalloc((void **)&d_a, size);
cudastatus=hipMalloc((void **)&d_b, size);
cudastatus=hipMalloc((void **)&d_c, size);
a = 1;
b = 2;
// Start Timing
// 计时模块
hipEvent_t start, stop;
float timeall;
cudastatus=hipEventCreate(&start);
cudastatus=hipEventCreate(&stop);
cudastatus=hipEventRecord( start, 0 );
// CopyToGPU
// 上传到GPU
cudastatus=hipMemcpy(d_a,&a,size,hipMemcpyHostToDevice);
cudastatus=hipMemcpy(d_b,&b,size,hipMemcpyHostToDevice);
kernelfunction<<<1,1>>>(d_a,d_b,d_c);
cudastatus=hipMemcpy(&c,d_c,size,hipMemcpyDeviceToHost);
// Timing
// 计时结束
cudastatus=hipEventRecord( stop, 0 );
cudastatus=hipEventSynchronize( stop );
cudastatus=hipEventElapsedTime( &timeall, start, stop );
cudastatus=hipEventDestroy( start );
cudastatus=hipEventDestroy( stop );
printf("c:%i \n",c);
printf("time:%f \n",timeall);
// 释放内存
cudastatus=hipFree(d_a);
cudastatus=hipFree(d_b);
cudastatus=hipFree(d_c);
if (cudastatus != hipSuccess) {
fprintf(stderr, "Failed %s\n", hipGetErrorString(cudastatus));
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14kernelfunctionPiS_S_
.globl _Z14kernelfunctionPiS_S_
.p2align 8
.type _Z14kernelfunctionPiS_S_,@function
_Z14kernelfunctionPiS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_load_b32 s3, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14kernelfunctionPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14kernelfunctionPiS_S_, .Lfunc_end0-_Z14kernelfunctionPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14kernelfunctionPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z14kernelfunctionPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
// 这个是kernel函数，就是GPU函数
__global__ void kernelfunction(int*a,int*b,int*c){
*c=*a+*b;
}
int main(void){
printf("Cuda_Performance Hello World\n");
int a,b,c;
int *d_a,*d_b,*d_c;
int size =sizeof(int);
// take the address of d_a,and cast into void**
// 取d_a的地址（一个二级指针），然后类型转换成void**
// Create Status for error check
// 这个是为了错误检查
hipError_t cudastatus;
// Allocate space for device
// 分配gpu内存
cudastatus=hipMalloc((void **)&d_a, size);
cudastatus=hipMalloc((void **)&d_b, size);
cudastatus=hipMalloc((void **)&d_c, size);
a = 1;
b = 2;
// Start Timing
// 计时模块
hipEvent_t start, stop;
float timeall;
cudastatus=hipEventCreate(&start);
cudastatus=hipEventCreate(&stop);
cudastatus=hipEventRecord( start, 0 );
// CopyToGPU
// 上传到GPU
cudastatus=hipMemcpy(d_a,&a,size,hipMemcpyHostToDevice);
cudastatus=hipMemcpy(d_b,&b,size,hipMemcpyHostToDevice);
kernelfunction<<<1,1>>>(d_a,d_b,d_c);
cudastatus=hipMemcpy(&c,d_c,size,hipMemcpyDeviceToHost);
// Timing
// 计时结束
cudastatus=hipEventRecord( stop, 0 );
cudastatus=hipEventSynchronize( stop );
cudastatus=hipEventElapsedTime( &timeall, start, stop );
cudastatus=hipEventDestroy( start );
cudastatus=hipEventDestroy( stop );
printf("c:%i \n",c);
printf("time:%f \n",timeall);
// 释放内存
cudastatus=hipFree(d_a);
cudastatus=hipFree(d_b);
cudastatus=hipFree(d_c);
if (cudastatus != hipSuccess) {
fprintf(stderr, "Failed %s\n", hipGetErrorString(cudastatus));
}
return 0;
} | .text
.file "1_cuda_performance_hello_world.hip"
.globl _Z29__device_stub__kernelfunctionPiS_S_ # -- Begin function _Z29__device_stub__kernelfunctionPiS_S_
.p2align 4, 0x90
.type _Z29__device_stub__kernelfunctionPiS_S_,@function
_Z29__device_stub__kernelfunctionPiS_S_: # @_Z29__device_stub__kernelfunctionPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14kernelfunctionPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z29__device_stub__kernelfunctionPiS_S_, .Lfunc_end0-_Z29__device_stub__kernelfunctionPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
movl $.Lstr, %edi
callq puts@PLT
leaq 32(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movl $1, 44(%rsp)
movl $2, 40(%rsp)
leaq 8(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
leaq 44(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
leaq 40(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
leaq 136(%rsp), %rax
movq %rax, 64(%rsp)
leaq 128(%rsp), %rax
movq %rax, 72(%rsp)
leaq 120(%rsp), %rax
movq %rax, 80(%rsp)
leaq 48(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14kernelfunctionPiS_S_, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 16(%rsp), %rsi
leaq 64(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rsi
movq (%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movq 8(%rsp), %rdi
callq hipEventDestroy
movq (%rsp), %rdi
callq hipEventDestroy
movl 64(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_3
.LBB1_4:
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_3:
.cfi_def_cfa_offset 160
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB1_4
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14kernelfunctionPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14kernelfunctionPiS_S_,@object # @_Z14kernelfunctionPiS_S_
.section .rodata,"a",@progbits
.globl _Z14kernelfunctionPiS_S_
.p2align 3, 0x0
_Z14kernelfunctionPiS_S_:
.quad _Z29__device_stub__kernelfunctionPiS_S_
.size _Z14kernelfunctionPiS_S_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "c:%i \n"
.size .L.str.1, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "time:%f \n"
.size .L.str.2, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed %s\n"
.size .L.str.3, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14kernelfunctionPiS_S_"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Cuda_Performance Hello World"
.size .Lstr, 29
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__kernelfunctionPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14kernelfunctionPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14kernelfunctionPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe200078e00ff */
/*0090*/ MOV R7, c[0x0][0x174] ; /* 0x00005d0000077a02 */
/* 0x000fe40000000f00 */
/*00a0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00b0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14kernelfunctionPiS_S_
.globl _Z14kernelfunctionPiS_S_
.p2align 8
.type _Z14kernelfunctionPiS_S_,@function
_Z14kernelfunctionPiS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_load_b32 s3, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14kernelfunctionPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14kernelfunctionPiS_S_, .Lfunc_end0-_Z14kernelfunctionPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14kernelfunctionPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z14kernelfunctionPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019dbea_00000000-6_1_cuda_performance_hello_world.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z14kernelfunctionPiS_S_PiS_S_
.type _Z38__device_stub__Z14kernelfunctionPiS_S_PiS_S_, @function
_Z38__device_stub__Z14kernelfunctionPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14kernelfunctionPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z38__device_stub__Z14kernelfunctionPiS_S_PiS_S_, .-_Z38__device_stub__Z14kernelfunctionPiS_S_PiS_S_
.globl _Z14kernelfunctionPiS_S_
.type _Z14kernelfunctionPiS_S_, @function
_Z14kernelfunctionPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14kernelfunctionPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z14kernelfunctionPiS_S_, .-_Z14kernelfunctionPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Cuda_Performance Hello World\n"
.LC1:
.string "c:%i \n"
.LC2:
.string "time:%f \n"
.LC3:
.string "Failed %s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, (%rsp)
movl $2, 4(%rsp)
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq %rsp, %rsi
movl $1, %ecx
movl $4, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
leaq 48(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 60(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movl 48(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 60(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L17
.L13:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z38__device_stub__Z14kernelfunctionPiS_S_PiS_S_
jmp .L12
.L17:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z14kernelfunctionPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z14kernelfunctionPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "1_cuda_performance_hello_world.hip"
.globl _Z29__device_stub__kernelfunctionPiS_S_ # -- Begin function _Z29__device_stub__kernelfunctionPiS_S_
.p2align 4, 0x90
.type _Z29__device_stub__kernelfunctionPiS_S_,@function
_Z29__device_stub__kernelfunctionPiS_S_: # @_Z29__device_stub__kernelfunctionPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14kernelfunctionPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z29__device_stub__kernelfunctionPiS_S_, .Lfunc_end0-_Z29__device_stub__kernelfunctionPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
movl $.Lstr, %edi
callq puts@PLT
leaq 32(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movl $1, 44(%rsp)
movl $2, 40(%rsp)
leaq 8(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
leaq 44(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
leaq 40(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
leaq 136(%rsp), %rax
movq %rax, 64(%rsp)
leaq 128(%rsp), %rax
movq %rax, 72(%rsp)
leaq 120(%rsp), %rax
movq %rax, 80(%rsp)
leaq 48(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14kernelfunctionPiS_S_, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 16(%rsp), %rsi
leaq 64(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rsi
movq (%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movq 8(%rsp), %rdi
callq hipEventDestroy
movq (%rsp), %rdi
callq hipEventDestroy
movl 64(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_3
.LBB1_4:
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_3:
.cfi_def_cfa_offset 160
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB1_4
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14kernelfunctionPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14kernelfunctionPiS_S_,@object # @_Z14kernelfunctionPiS_S_
.section .rodata,"a",@progbits
.globl _Z14kernelfunctionPiS_S_
.p2align 3, 0x0
_Z14kernelfunctionPiS_S_:
.quad _Z29__device_stub__kernelfunctionPiS_S_
.size _Z14kernelfunctionPiS_S_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "c:%i \n"
.size .L.str.1, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "time:%f \n"
.size .L.str.2, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed %s\n"
.size .L.str.3, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14kernelfunctionPiS_S_"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Cuda_Performance Hello World"
.size .Lstr, 29
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__kernelfunctionPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14kernelfunctionPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cstdio>
using namespace std;
#include <cuda_runtime.h>
#define TIMES 24
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////HELP FUNCTIONS/////////////////////////////////////////////////
void RandomInit(float* data, int n)
{
for (int i=0; i<n; i++)
{
data[i] = rand() / (float)RAND_MAX;
}
}
void RandomInit(unsigned* data, int n)
{
for (int i=0; i<n; i++)
{
data[i] = rand() % n;
}
}
#define checkCudaErrors(err) __checkCudaErrors (err, __FILE__, __LINE__)
inline void __checkCudaErrors(cudaError err, const char *file, const int line )
{
if(cudaSuccess != err)
{
fprintf(stderr, "%s(%i) : CUDA Runtime API error %d: %s.\n",file, line, (int)err, cudaGetErrorString( err ) );
exit(-1);
}
}
// This will output the proper error string when calling cudaGetLastError
#define getLastCudaError(msg) __getLastCudaError (msg, __FILE__, __LINE__)
inline void __getLastCudaError(const char *errorMessage, const char *file, const int line )
{
cudaError_t err = cudaGetLastError();
if (cudaSuccess != err)
{
fprintf(stderr, "%s(%i) : getLastCudaError() CUDA error : %s : (%d) %s.\n",
file, line, errorMessage, (int)err, cudaGetErrorString( err ) );
exit(-1);
}
}
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////_VECTOR_ADDITION_///////////////////////////////////////////////////////
// Device code
__global__ void irreguler(const float* A, float* C, float* F)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i == 0)
{
C[i] = A[i];
__syncthreads();
//high latncy
C[i] = C[i] + A[i];
__syncthreads();
F[i] = C[i+1];
}
}
__global__ void mb2(float* A, float* C)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i == 0) {
C[i] = A[i]; //write to C[i] is a miss (cache line is missing)
__syncthreads();
C[i+1] = A[i]; //write to C[i+1] is a hit (cache line is found)
__syncthreads();
C[i] = C[i] + A[i]; //read of C[i] is a miss (entire sector is missing, fetch it from memory)
__syncthreads();
A[i] = C[i] + C[i+1]; //read C[i] and C[i+1] are hits (entire sector exists)
}
}
__global__ void l1(float* A, float* C)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i == 0) {
C[i] = A[i] + A[i+32];
__syncthreads();
C[i] = A[i] + A[i+32] + C[i];
}
}
// Host code
void VectorAddition(int N, int threadsPerBlock)
{
cout<<"Vector Addition for input size "<<N<<" :\n";
// Variables
float* h_A;
float* h_C;
float* d_A;
float* d_C;
float total_time=0;
size_t size = N * sizeof(float);
// Allocate input vectors h_A and h_B in host memory
h_A = (float*)malloc(size);
h_C = (float*)malloc(size);
// Initialize input vectors
RandomInit(h_A, N);
// Allocate vectors in device memory
checkCudaErrors( cudaMalloc((void**)&d_A, size) );
checkCudaErrors( cudaMalloc((void**)&d_C, size) );
// Copy vectors from host memory to device memory
checkCudaErrors( cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice) );
checkCudaErrors(cudaThreadSynchronize());
// Invoke kernel
cout<<"Invoke Kernel\n";
//int threads = 128;
int blocksPerGrid = ((N+ threadsPerBlock-1) / threadsPerBlock);
for (int i = 0; i < 1; i++) {
l1<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_C);
getLastCudaError("kernel launch failure");
checkCudaErrors(cudaThreadSynchronize());
}
float dSeconds = total_time/((float)TIMES * 1000);
float dNumOps = N;
float gflops = 1.0e-9 * dNumOps/dSeconds;
cout<<"Time = "<<dSeconds*1.0e3<< "msec"<<endl<<"gflops = "<<gflops<<endl;
// Copy result from device memory to host memory
// h_C contains the result in host memory
checkCudaErrors( cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost) );
// Verify result
int i;
for (i = 0; i < N; ++i) {
float sum = h_A[i];
if (fabs(h_C[i] - sum) > 1e-5)
break;
}
// Free device memory
if (d_A)
cudaFree(d_A);
if (d_C)
cudaFree(d_C);
// Free host memory
if (h_A)
free(h_A);
if (h_C)
free(h_C);
cudaDeviceReset();
if(i == N)
cout<<"SUCCSESS"<<endl;
else
cout<<"FAILED"<<endl;
}
//////////////////////////////////////////////////////
int main(int argc,char *argv[])
{
if(argc < 3)
printf("Unsuffcient number of arguments!\n");
else
{
VectorAddition(atoi(argv[1]), atoi(argv[2]));
}
} | code for sm_80
Function : _Z2l1PfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0030*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe40000000800 */
/*0040*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x001fe2000f8e023f */
/*0050*/ IADD3 R0, -R0, RZ, RZ ; /* 0x000000ff00007210 */
/* 0x002fca0007ffe1ff */
/*0060*/ ISETP.NE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf05270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0090*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00b0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R7, [R2.64+0x80] ; /* 0x0000800402077981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*00e0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe400078e00ff */
/*00f0*/ FADD R7, R0, R7 ; /* 0x0000000700077221 */
/* 0x004fca0000000000 */
/*0100*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe8000c101904 */
/*0110*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0120*/ LDG.E R0, [R2.64+0x80] ; /* 0x0000800402007981 */
/* 0x000ea8000c1e1900 */
/*0130*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea8000c1e1900 */
/*0140*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000ee2000c1e1900 */
/*0150*/ FADD R0, R0, R9 ; /* 0x0000000900007221 */
/* 0x004fc80000000000 */
/*0160*/ FADD R11, R0, R11 ; /* 0x0000000b000b7221 */
/* 0x008fca0000000000 */
/*0170*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x000fe2000c101904 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z3mb2PfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0030*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe40000000800 */
/*0040*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x001fe2000f8e023f */
/*0050*/ IADD3 R0, -R0, RZ, RZ ; /* 0x000000ff00007210 */
/* 0x002fca0007ffe1ff */
/*0060*/ ISETP.NE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf05270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0090*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00b0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fca00078e00ff */
/*00e0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0041e8000c101904 */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0100*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea8000c1e1900 */
/*0110*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x004fe8000c101904 */
/*0120*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0130*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0140*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000ea4000c1e1900 */
/*0150*/ FADD R11, R0, R11 ; /* 0x0000000b000b7221 */
/* 0x004fca0000000000 */
/*0160*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x000fe8000c101904 */
/*0170*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0180*/ LDG.E R0, [R4.64+0x4] ; /* 0x0000040404007981 */
/* 0x000ea8000c1e1900 */
/*0190*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x001ea4000c1e1900 */
/*01a0*/ FADD R7, R0, R7 ; /* 0x0000000700077221 */
/* 0x004fca0000000000 */
/*01b0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9irregulerPKfPfS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0030*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe40000000800 */
/*0040*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x001fe2000f8e023f */
/*0050*/ IMAD.MOV R0, RZ, RZ, -R0 ; /* 0x000000ffff007224 */
/* 0x002fca00078e0a00 */
/*0060*/ ISETP.NE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf05270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0090*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00b0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fca00078e00ff */
/*00e0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x004fe8000c101904 */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0100*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*0120*/ FADD R11, R0, R7 ; /* 0x00000007000b7221 */
/* 0x004fca0000000000 */
/*0130*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x000fe8000c101904 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0150*/ LDG.E R13, [R4.64+0x4] ; /* 0x00000404040d7981 */
/* 0x000ea2000c1e1900 */
/*0160*/ MOV R6, c[0x0][0x170] ; /* 0x00005c0000067a02 */
/* 0x000fc40000000f00 */
/*0170*/ MOV R7, c[0x0][0x174] ; /* 0x00005d0000077a02 */
/* 0x000fca0000000f00 */
/*0180*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x004fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cstdio>
using namespace std;
#include <cuda_runtime.h>
#define TIMES 24
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////HELP FUNCTIONS/////////////////////////////////////////////////
void RandomInit(float* data, int n)
{
for (int i=0; i<n; i++)
{
data[i] = rand() / (float)RAND_MAX;
}
}
void RandomInit(unsigned* data, int n)
{
for (int i=0; i<n; i++)
{
data[i] = rand() % n;
}
}
#define checkCudaErrors(err) __checkCudaErrors (err, __FILE__, __LINE__)
inline void __checkCudaErrors(cudaError err, const char *file, const int line )
{
if(cudaSuccess != err)
{
fprintf(stderr, "%s(%i) : CUDA Runtime API error %d: %s.\n",file, line, (int)err, cudaGetErrorString( err ) );
exit(-1);
}
}
// This will output the proper error string when calling cudaGetLastError
#define getLastCudaError(msg) __getLastCudaError (msg, __FILE__, __LINE__)
inline void __getLastCudaError(const char *errorMessage, const char *file, const int line )
{
cudaError_t err = cudaGetLastError();
if (cudaSuccess != err)
{
fprintf(stderr, "%s(%i) : getLastCudaError() CUDA error : %s : (%d) %s.\n",
file, line, errorMessage, (int)err, cudaGetErrorString( err ) );
exit(-1);
}
}
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////_VECTOR_ADDITION_///////////////////////////////////////////////////////
// Device code
__global__ void irreguler(const float* A, float* C, float* F)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i == 0)
{
C[i] = A[i];
__syncthreads();
//high latncy
C[i] = C[i] + A[i];
__syncthreads();
F[i] = C[i+1];
}
}
__global__ void mb2(float* A, float* C)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i == 0) {
C[i] = A[i]; //write to C[i] is a miss (cache line is missing)
__syncthreads();
C[i+1] = A[i]; //write to C[i+1] is a hit (cache line is found)
__syncthreads();
C[i] = C[i] + A[i]; //read of C[i] is a miss (entire sector is missing, fetch it from memory)
__syncthreads();
A[i] = C[i] + C[i+1]; //read C[i] and C[i+1] are hits (entire sector exists)
}
}
__global__ void l1(float* A, float* C)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i == 0) {
C[i] = A[i] + A[i+32];
__syncthreads();
C[i] = A[i] + A[i+32] + C[i];
}
}
// Host code
void VectorAddition(int N, int threadsPerBlock)
{
cout<<"Vector Addition for input size "<<N<<" :\n";
// Variables
float* h_A;
float* h_C;
float* d_A;
float* d_C;
float total_time=0;
size_t size = N * sizeof(float);
// Allocate input vectors h_A and h_B in host memory
h_A = (float*)malloc(size);
h_C = (float*)malloc(size);
// Initialize input vectors
RandomInit(h_A, N);
// Allocate vectors in device memory
checkCudaErrors( cudaMalloc((void**)&d_A, size) );
checkCudaErrors( cudaMalloc((void**)&d_C, size) );
// Copy vectors from host memory to device memory
checkCudaErrors( cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice) );
checkCudaErrors(cudaThreadSynchronize());
// Invoke kernel
cout<<"Invoke Kernel\n";
//int threads = 128;
int blocksPerGrid = ((N+ threadsPerBlock-1) / threadsPerBlock);
for (int i = 0; i < 1; i++) {
l1<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_C);
getLastCudaError("kernel launch failure");
checkCudaErrors(cudaThreadSynchronize());
}
float dSeconds = total_time/((float)TIMES * 1000);
float dNumOps = N;
float gflops = 1.0e-9 * dNumOps/dSeconds;
cout<<"Time = "<<dSeconds*1.0e3<< "msec"<<endl<<"gflops = "<<gflops<<endl;
// Copy result from device memory to host memory
// h_C contains the result in host memory
checkCudaErrors( cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost) );
// Verify result
int i;
for (i = 0; i < N; ++i) {
float sum = h_A[i];
if (fabs(h_C[i] - sum) > 1e-5)
break;
}
// Free device memory
if (d_A)
cudaFree(d_A);
if (d_C)
cudaFree(d_C);
// Free host memory
if (h_A)
free(h_A);
if (h_C)
free(h_C);
cudaDeviceReset();
if(i == N)
cout<<"SUCCSESS"<<endl;
else
cout<<"FAILED"<<endl;
}
//////////////////////////////////////////////////////
int main(int argc,char *argv[])
{
if(argc < 3)
printf("Unsuffcient number of arguments!\n");
else
{
VectorAddition(atoi(argv[1]), atoi(argv[2]));
}
} | .file "tmpxft_00029620_00000000-6_l2_write_policy.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3677:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3677:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10RandomInitPfi
.type _Z10RandomInitPfi, @function
_Z10RandomInitPfi:
.LFB3669:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE3669:
.size _Z10RandomInitPfi, .-_Z10RandomInitPfi
.globl _Z10RandomInitPji
.type _Z10RandomInitPji, @function
_Z10RandomInitPji:
.LFB3670:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L16
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %esi, %ebp
movq %rdi, %rbx
movslq %esi, %rax
leaq (%rdi,%rax,4), %r12
.L13:
call rand@PLT
cltd
idivl %ebp
movl %edx, (%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L13
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE3670:
.size _Z10RandomInitPji, .-_Z10RandomInitPji
.globl _Z34__device_stub__Z9irregulerPKfPfS1_PKfPfS1_
.type _Z34__device_stub__Z9irregulerPKfPfS1_PKfPfS1_, @function
_Z34__device_stub__Z9irregulerPKfPfS1_PKfPfS1_:
.LFB3699:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9irregulerPKfPfS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _Z34__device_stub__Z9irregulerPKfPfS1_PKfPfS1_, .-_Z34__device_stub__Z9irregulerPKfPfS1_PKfPfS1_
.globl _Z9irregulerPKfPfS1_
.type _Z9irregulerPKfPfS1_, @function
_Z9irregulerPKfPfS1_:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9irregulerPKfPfS1_PKfPfS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _Z9irregulerPKfPfS1_, .-_Z9irregulerPKfPfS1_
.globl _Z24__device_stub__Z3mb2PfS_PfS_
.type _Z24__device_stub__Z3mb2PfS_PfS_, @function
_Z24__device_stub__Z3mb2PfS_PfS_:
.LFB3701:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3mb2PfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3701:
.size _Z24__device_stub__Z3mb2PfS_PfS_, .-_Z24__device_stub__Z3mb2PfS_PfS_
.globl _Z3mb2PfS_
.type _Z3mb2PfS_, @function
_Z3mb2PfS_:
.LFB3702:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3mb2PfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _Z3mb2PfS_, .-_Z3mb2PfS_
.globl _Z23__device_stub__Z2l1PfS_PfS_
.type _Z23__device_stub__Z2l1PfS_PfS_, @function
_Z23__device_stub__Z2l1PfS_PfS_:
.LFB3703:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z2l1PfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3703:
.size _Z23__device_stub__Z2l1PfS_PfS_, .-_Z23__device_stub__Z2l1PfS_PfS_
.globl _Z2l1PfS_
.type _Z2l1PfS_, @function
_Z2l1PfS_:
.LFB3704:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z2l1PfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3704:
.size _Z2l1PfS_, .-_Z2l1PfS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Vector Addition for input size "
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string " :\n"
.section .rodata.str1.8
.align 8
.LC3:
.string "/home/ubuntu/Datasets/stackv2/train-structured/shen203/GPU_Microbenchmark/master/write_policy/l2_write_policy.cu"
.align 8
.LC4:
.string "%s(%i) : CUDA Runtime API error %d: %s.\n"
.section .rodata.str1.1
.LC5:
.string "Invoke Kernel\n"
.LC6:
.string "kernel launch failure"
.section .rodata.str1.8
.align 8
.LC7:
.string "%s(%i) : getLastCudaError() CUDA error : %s : (%d) %s.\n"
.section .rodata.str1.1
.LC10:
.string "Time = "
.LC11:
.string "msec"
.LC12:
.string "gflops = "
.LC15:
.string "SUCCSESS"
.LC16:
.string "FAILED"
.text
.globl _Z14VectorAdditionii
.type _Z14VectorAdditionii, @function
_Z14VectorAdditionii:
.LFB3673:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movl %edi, %r13d
movl %esi, %r15d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $31, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r13d, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $3, %edx
leaq .LC2(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movslq %r13d, %r12
leaq 0(,%r12,4), %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
movl %r13d, %esi
movq %rbx, %rdi
call _Z10RandomInitPfi
leaq 16(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L86
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L87
movl $1, %ecx
movq %r14, %rdx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L88
call cudaThreadSynchronize@PLT
testl %eax, %eax
jne .L89
movl $14, %edx
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r15d, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leal -1(%r13,%r15), %eax
cltd
idivl %r15d
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L90
.L48:
call cudaGetLastError@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L91
call cudaThreadSynchronize@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L92
pxor %xmm0, %xmm0
cvtsi2ssl %r13d, %xmm0
cvtss2sd %xmm0, %xmm0
mulsd .LC8(%rip), %xmm0
pxor %xmm1, %xmm1
divsd %xmm1, %xmm0
pxor %xmm3, %xmm3
cvtsd2ss %xmm0, %xmm3
movss %xmm3, (%rsp)
movl $7, %edx
leaq .LC10(%rip), %rsi
leaq _ZSt4cout(%rip), %r15
movq %r15, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
movq %r15, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %r15
movq %rax, 8(%rsp)
movl $4, %edx
leaq .LC11(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r15
testq %r15, %r15
je .L93
cmpb $0, 56(%r15)
je .L53
movzbl 67(%r15), %esi
.L54:
movsbl %sil, %esi
movq 8(%rsp), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq %rax, %r15
movl $9, %edx
leaq .LC12(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%rsp), %xmm0
movq %r15, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rcx
movq %rax, (%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rcx,%rax), %r15
testq %r15, %r15
je .L94
cmpb $0, 56(%r15)
je .L57
movzbl 67(%r15), %esi
.L58:
movsbl %sil, %esi
movq (%rsp), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $2, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %r14d
testl %eax, %eax
jne .L59
movl $0, %eax
testl %r13d, %r13d
jle .L83
movss .LC13(%rip), %xmm2
movsd .LC14(%rip), %xmm1
jmp .L60
.L86:
movl %eax, %ebx
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 136
pushq %rax
.cfi_def_cfa_offset 144
movl %ebx, %r9d
movl $123, %r8d
leaq .LC3(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L87:
.cfi_restore_state
movl %eax, %ebx
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 136
pushq %rax
.cfi_def_cfa_offset 144
movl %ebx, %r9d
movl $124, %r8d
leaq .LC3(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L88:
.cfi_restore_state
movl %eax, %ebx
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 136
pushq %rax
.cfi_def_cfa_offset 144
movl %ebx, %r9d
movl $128, %r8d
leaq .LC3(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L89:
.cfi_restore_state
movl %eax, %ebx
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 136
pushq %rax
.cfi_def_cfa_offset 144
movl %ebx, %r9d
movl $130, %r8d
leaq .LC3(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L90:
.cfi_restore_state
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z23__device_stub__Z2l1PfS_PfS_
jmp .L48
.L91:
movl %eax, %edi
call cudaGetErrorString@PLT
pushq %rax
.cfi_remember_state
.cfi_def_cfa_offset 136
pushq %r15
.cfi_def_cfa_offset 144
leaq .LC6(%rip), %r9
movl $139, %r8d
leaq .LC3(%rip), %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L92:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 136
pushq %rax
.cfi_def_cfa_offset 144
movl %r15d, %r9d
movl $140, %r8d
leaq .LC3(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L93:
.cfi_restore_state
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L95
call _ZSt16__throw_bad_castv@PLT
.L95:
call __stack_chk_fail@PLT
.L53:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L54
.L94:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L96
call _ZSt16__throw_bad_castv@PLT
.L96:
call __stack_chk_fail@PLT
.L57:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L58
.L83:
movl $0, %r12d
jmp .L61
.L59:
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 136
pushq %rax
.cfi_def_cfa_offset 144
movl %r14d, %r9d
movl $150, %r8d
leaq .LC3(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L80:
.cfi_restore_state
movq %rdx, %rax
.L60:
movss 0(%rbp,%rax,4), %xmm0
subss (%rbx,%rax,4), %xmm0
andps %xmm2, %xmm0
cvtss2sd %xmm0, %xmm0
comisd %xmm1, %xmm0
ja .L97
leaq 1(%rax), %rdx
cmpq %rdx, %r12
jne .L80
leal 1(%rax), %r12d
jmp .L61
.L97:
movl %eax, %r12d
.L61:
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .L64
call cudaFree@PLT
.L64:
movq 24(%rsp), %rdi
testq %rdi, %rdi
je .L65
call cudaFree@PLT
.L65:
testq %rbx, %rbx
je .L66
movq %rbx, %rdi
call free@PLT
.L66:
testq %rbp, %rbp
je .L67
movq %rbp, %rdi
call free@PLT
.L67:
call cudaDeviceReset@PLT
cmpl %r13d, %r12d
je .L98
movl $6, %edx
leaq .LC16(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L99
cmpb $0, 56(%rbx)
je .L76
movzbl 67(%rbx), %esi
.L77:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.L43:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L100
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L98:
.cfi_restore_state
movl $8, %edx
leaq .LC15(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L101
cmpb $0, 56(%rbx)
je .L71
movzbl 67(%rbx), %esi
.L72:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L43
.L101:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L102
call _ZSt16__throw_bad_castv@PLT
.L102:
call __stack_chk_fail@PLT
.L71:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L72
.L99:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L103
call _ZSt16__throw_bad_castv@PLT
.L103:
call __stack_chk_fail@PLT
.L76:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L77
.L100:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3673:
.size _Z14VectorAdditionii, .-_Z14VectorAdditionii
.section .rodata.str1.8
.align 8
.LC17:
.string "Unsuffcient number of arguments!\n"
.text
.globl main
.type main, @function
main:
.LFB3674:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
cmpl $2, %edi
jg .L105
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L106:
movl $0, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L105:
.cfi_restore_state
movq %rsi, %rbx
movq 16(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %ebp, %esi
movl %eax, %edi
call _Z14VectorAdditionii
jmp .L106
.cfi_endproc
.LFE3674:
.size main, .-main
.section .rodata.str1.1
.LC18:
.string "_Z2l1PfS_"
.LC19:
.string "_Z3mb2PfS_"
.LC20:
.string "_Z9irregulerPKfPfS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3706:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z2l1PfS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z3mb2PfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z9irregulerPKfPfS1_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3706:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC8:
.long -400107883
.long 1041313291
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC13:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC14:
.long -1998362383
.long 1055193269
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cstdio>
using namespace std;
#include <cuda_runtime.h>
#define TIMES 24
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////HELP FUNCTIONS/////////////////////////////////////////////////
void RandomInit(float* data, int n)
{
for (int i=0; i<n; i++)
{
data[i] = rand() / (float)RAND_MAX;
}
}
void RandomInit(unsigned* data, int n)
{
for (int i=0; i<n; i++)
{
data[i] = rand() % n;
}
}
#define checkCudaErrors(err) __checkCudaErrors (err, __FILE__, __LINE__)
inline void __checkCudaErrors(cudaError err, const char *file, const int line )
{
if(cudaSuccess != err)
{
fprintf(stderr, "%s(%i) : CUDA Runtime API error %d: %s.\n",file, line, (int)err, cudaGetErrorString( err ) );
exit(-1);
}
}
// This will output the proper error string when calling cudaGetLastError
#define getLastCudaError(msg) __getLastCudaError (msg, __FILE__, __LINE__)
inline void __getLastCudaError(const char *errorMessage, const char *file, const int line )
{
cudaError_t err = cudaGetLastError();
if (cudaSuccess != err)
{
fprintf(stderr, "%s(%i) : getLastCudaError() CUDA error : %s : (%d) %s.\n",
file, line, errorMessage, (int)err, cudaGetErrorString( err ) );
exit(-1);
}
}
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////_VECTOR_ADDITION_///////////////////////////////////////////////////////
// Device code
__global__ void irreguler(const float* A, float* C, float* F)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i == 0)
{
C[i] = A[i];
__syncthreads();
//high latncy
C[i] = C[i] + A[i];
__syncthreads();
F[i] = C[i+1];
}
}
__global__ void mb2(float* A, float* C)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i == 0) {
C[i] = A[i]; //write to C[i] is a miss (cache line is missing)
__syncthreads();
C[i+1] = A[i]; //write to C[i+1] is a hit (cache line is found)
__syncthreads();
C[i] = C[i] + A[i]; //read of C[i] is a miss (entire sector is missing, fetch it from memory)
__syncthreads();
A[i] = C[i] + C[i+1]; //read C[i] and C[i+1] are hits (entire sector exists)
}
}
__global__ void l1(float* A, float* C)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i == 0) {
C[i] = A[i] + A[i+32];
__syncthreads();
C[i] = A[i] + A[i+32] + C[i];
}
}
// Host code
void VectorAddition(int N, int threadsPerBlock)
{
cout<<"Vector Addition for input size "<<N<<" :\n";
// Variables
float* h_A;
float* h_C;
float* d_A;
float* d_C;
float total_time=0;
size_t size = N * sizeof(float);
// Allocate input vectors h_A and h_B in host memory
h_A = (float*)malloc(size);
h_C = (float*)malloc(size);
// Initialize input vectors
RandomInit(h_A, N);
// Allocate vectors in device memory
checkCudaErrors( cudaMalloc((void**)&d_A, size) );
checkCudaErrors( cudaMalloc((void**)&d_C, size) );
// Copy vectors from host memory to device memory
checkCudaErrors( cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice) );
checkCudaErrors(cudaThreadSynchronize());
// Invoke kernel
cout<<"Invoke Kernel\n";
//int threads = 128;
int blocksPerGrid = ((N+ threadsPerBlock-1) / threadsPerBlock);
for (int i = 0; i < 1; i++) {
l1<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_C);
getLastCudaError("kernel launch failure");
checkCudaErrors(cudaThreadSynchronize());
}
float dSeconds = total_time/((float)TIMES * 1000);
float dNumOps = N;
float gflops = 1.0e-9 * dNumOps/dSeconds;
cout<<"Time = "<<dSeconds*1.0e3<< "msec"<<endl<<"gflops = "<<gflops<<endl;
// Copy result from device memory to host memory
// h_C contains the result in host memory
checkCudaErrors( cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost) );
// Verify result
int i;
for (i = 0; i < N; ++i) {
float sum = h_A[i];
if (fabs(h_C[i] - sum) > 1e-5)
break;
}
// Free device memory
if (d_A)
cudaFree(d_A);
if (d_C)
cudaFree(d_C);
// Free host memory
if (h_A)
free(h_A);
if (h_C)
free(h_C);
cudaDeviceReset();
if(i == N)
cout<<"SUCCSESS"<<endl;
else
cout<<"FAILED"<<endl;
}
//////////////////////////////////////////////////////
int main(int argc,char *argv[])
{
if(argc < 3)
printf("Unsuffcient number of arguments!\n");
else
{
VectorAddition(atoi(argv[1]), atoi(argv[2]));
}
} | #include <iostream>
#include <cstdio>
using namespace std;
#include <hip/hip_runtime.h>
#define TIMES 24
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////HELP FUNCTIONS/////////////////////////////////////////////////
void RandomInit(float* data, int n)
{
for (int i=0; i<n; i++)
{
data[i] = rand() / (float)RAND_MAX;
}
}
void RandomInit(unsigned* data, int n)
{
for (int i=0; i<n; i++)
{
data[i] = rand() % n;
}
}
#define checkCudaErrors(err) __checkCudaErrors (err, __FILE__, __LINE__)
inline void __checkCudaErrors(hipError_t err, const char *file, const int line )
{
if(hipSuccess != err)
{
fprintf(stderr, "%s(%i) : CUDA Runtime API error %d: %s.\n",file, line, (int)err, hipGetErrorString( err ) );
exit(-1);
}
}
// This will output the proper error string when calling cudaGetLastError
#define getLastCudaError(msg) __getLastCudaError (msg, __FILE__, __LINE__)
inline void __getLastCudaError(const char *errorMessage, const char *file, const int line )
{
hipError_t err = hipGetLastError();
if (hipSuccess != err)
{
fprintf(stderr, "%s(%i) : getLastCudaError() CUDA error : %s : (%d) %s.\n",
file, line, errorMessage, (int)err, hipGetErrorString( err ) );
exit(-1);
}
}
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////_VECTOR_ADDITION_///////////////////////////////////////////////////////
// Device code
__global__ void irreguler(const float* A, float* C, float* F)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i == 0)
{
C[i] = A[i];
__syncthreads();
//high latncy
C[i] = C[i] + A[i];
__syncthreads();
F[i] = C[i+1];
}
}
__global__ void mb2(float* A, float* C)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i == 0) {
C[i] = A[i]; //write to C[i] is a miss (cache line is missing)
__syncthreads();
C[i+1] = A[i]; //write to C[i+1] is a hit (cache line is found)
__syncthreads();
C[i] = C[i] + A[i]; //read of C[i] is a miss (entire sector is missing, fetch it from memory)
__syncthreads();
A[i] = C[i] + C[i+1]; //read C[i] and C[i+1] are hits (entire sector exists)
}
}
__global__ void l1(float* A, float* C)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i == 0) {
C[i] = A[i] + A[i+32];
__syncthreads();
C[i] = A[i] + A[i+32] + C[i];
}
}
// Host code
void VectorAddition(int N, int threadsPerBlock)
{
cout<<"Vector Addition for input size "<<N<<" :\n";
// Variables
float* h_A;
float* h_C;
float* d_A;
float* d_C;
float total_time=0;
size_t size = N * sizeof(float);
// Allocate input vectors h_A and h_B in host memory
h_A = (float*)malloc(size);
h_C = (float*)malloc(size);
// Initialize input vectors
RandomInit(h_A, N);
// Allocate vectors in device memory
checkCudaErrors( hipMalloc((void**)&d_A, size) );
checkCudaErrors( hipMalloc((void**)&d_C, size) );
// Copy vectors from host memory to device memory
checkCudaErrors( hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice) );
checkCudaErrors(hipDeviceSynchronize());
// Invoke kernel
cout<<"Invoke Kernel\n";
//int threads = 128;
int blocksPerGrid = ((N+ threadsPerBlock-1) / threadsPerBlock);
for (int i = 0; i < 1; i++) {
l1<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_C);
getLastCudaError("kernel launch failure");
checkCudaErrors(hipDeviceSynchronize());
}
float dSeconds = total_time/((float)TIMES * 1000);
float dNumOps = N;
float gflops = 1.0e-9 * dNumOps/dSeconds;
cout<<"Time = "<<dSeconds*1.0e3<< "msec"<<endl<<"gflops = "<<gflops<<endl;
// Copy result from device memory to host memory
// h_C contains the result in host memory
checkCudaErrors( hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost) );
// Verify result
int i;
for (i = 0; i < N; ++i) {
float sum = h_A[i];
if (fabs(h_C[i] - sum) > 1e-5)
break;
}
// Free device memory
if (d_A)
hipFree(d_A);
if (d_C)
hipFree(d_C);
// Free host memory
if (h_A)
free(h_A);
if (h_C)
free(h_C);
hipDeviceReset();
if(i == N)
cout<<"SUCCSESS"<<endl;
else
cout<<"FAILED"<<endl;
}
//////////////////////////////////////////////////////
int main(int argc,char *argv[])
{
if(argc < 3)
printf("Unsuffcient number of arguments!\n");
else
{
VectorAddition(atoi(argv[1]), atoi(argv[2]));
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <cstdio>
using namespace std;
#include <hip/hip_runtime.h>
#define TIMES 24
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////HELP FUNCTIONS/////////////////////////////////////////////////
void RandomInit(float* data, int n)
{
for (int i=0; i<n; i++)
{
data[i] = rand() / (float)RAND_MAX;
}
}
void RandomInit(unsigned* data, int n)
{
for (int i=0; i<n; i++)
{
data[i] = rand() % n;
}
}
#define checkCudaErrors(err) __checkCudaErrors (err, __FILE__, __LINE__)
inline void __checkCudaErrors(hipError_t err, const char *file, const int line )
{
if(hipSuccess != err)
{
fprintf(stderr, "%s(%i) : CUDA Runtime API error %d: %s.\n",file, line, (int)err, hipGetErrorString( err ) );
exit(-1);
}
}
// This will output the proper error string when calling cudaGetLastError
#define getLastCudaError(msg) __getLastCudaError (msg, __FILE__, __LINE__)
inline void __getLastCudaError(const char *errorMessage, const char *file, const int line )
{
hipError_t err = hipGetLastError();
if (hipSuccess != err)
{
fprintf(stderr, "%s(%i) : getLastCudaError() CUDA error : %s : (%d) %s.\n",
file, line, errorMessage, (int)err, hipGetErrorString( err ) );
exit(-1);
}
}
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////_VECTOR_ADDITION_///////////////////////////////////////////////////////
// Device code
__global__ void irreguler(const float* A, float* C, float* F)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i == 0)
{
C[i] = A[i];
__syncthreads();
//high latncy
C[i] = C[i] + A[i];
__syncthreads();
F[i] = C[i+1];
}
}
__global__ void mb2(float* A, float* C)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i == 0) {
C[i] = A[i]; //write to C[i] is a miss (cache line is missing)
__syncthreads();
C[i+1] = A[i]; //write to C[i+1] is a hit (cache line is found)
__syncthreads();
C[i] = C[i] + A[i]; //read of C[i] is a miss (entire sector is missing, fetch it from memory)
__syncthreads();
A[i] = C[i] + C[i+1]; //read C[i] and C[i+1] are hits (entire sector exists)
}
}
__global__ void l1(float* A, float* C)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i == 0) {
C[i] = A[i] + A[i+32];
__syncthreads();
C[i] = A[i] + A[i+32] + C[i];
}
}
// Host code
void VectorAddition(int N, int threadsPerBlock)
{
cout<<"Vector Addition for input size "<<N<<" :\n";
// Variables
float* h_A;
float* h_C;
float* d_A;
float* d_C;
float total_time=0;
size_t size = N * sizeof(float);
// Allocate input vectors h_A and h_B in host memory
h_A = (float*)malloc(size);
h_C = (float*)malloc(size);
// Initialize input vectors
RandomInit(h_A, N);
// Allocate vectors in device memory
checkCudaErrors( hipMalloc((void**)&d_A, size) );
checkCudaErrors( hipMalloc((void**)&d_C, size) );
// Copy vectors from host memory to device memory
checkCudaErrors( hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice) );
checkCudaErrors(hipDeviceSynchronize());
// Invoke kernel
cout<<"Invoke Kernel\n";
//int threads = 128;
int blocksPerGrid = ((N+ threadsPerBlock-1) / threadsPerBlock);
for (int i = 0; i < 1; i++) {
l1<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_C);
getLastCudaError("kernel launch failure");
checkCudaErrors(hipDeviceSynchronize());
}
float dSeconds = total_time/((float)TIMES * 1000);
float dNumOps = N;
float gflops = 1.0e-9 * dNumOps/dSeconds;
cout<<"Time = "<<dSeconds*1.0e3<< "msec"<<endl<<"gflops = "<<gflops<<endl;
// Copy result from device memory to host memory
// h_C contains the result in host memory
checkCudaErrors( hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost) );
// Verify result
int i;
for (i = 0; i < N; ++i) {
float sum = h_A[i];
if (fabs(h_C[i] - sum) > 1e-5)
break;
}
// Free device memory
if (d_A)
hipFree(d_A);
if (d_C)
hipFree(d_C);
// Free host memory
if (h_A)
free(h_A);
if (h_C)
free(h_C);
hipDeviceReset();
if(i == N)
cout<<"SUCCSESS"<<endl;
else
cout<<"FAILED"<<endl;
}
//////////////////////////////////////////////////////
int main(int argc,char *argv[])
{
if(argc < 3)
printf("Unsuffcient number of arguments!\n");
else
{
VectorAddition(atoi(argv[1]), atoi(argv[2]));
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9irregulerPKfPfS1_
.globl _Z9irregulerPKfPfS1_
.p2align 8
.type _Z9irregulerPKfPfS1_,@function
_Z9irregulerPKfPfS1_:
s_load_b32 s2, s[0:1], 0x24
v_sub_nc_u32_e32 v0, 0, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s15, s15, s2
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e64 s15, v0
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[6:7]
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_clause 0x1
global_load_b32 v1, v0, s[6:7]
global_load_b32 v2, v0, s[4:5]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[6:7]
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_load_b32 s2, s[6:7], 0x4
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v1, s2
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9irregulerPKfPfS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9irregulerPKfPfS1_, .Lfunc_end0-_Z9irregulerPKfPfS1_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3mb2PfS_
.globl _Z3mb2PfS_
.p2align 8
.type _Z3mb2PfS_,@function
_Z3mb2PfS_:
s_load_b32 s2, s[0:1], 0x1c
v_sub_nc_u32_e32 v0, 0, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s15, s15, s2
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e64 s15, v0
s_cbranch_execz .LBB1_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v0, s4
global_store_b32 v2, v0, s[2:3]
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_load_b32 v0, v2, s[0:1]
s_waitcnt vmcnt(0)
global_store_b32 v2, v0, s[2:3] offset:4
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_clause 0x1
global_load_b32 v0, v2, s[2:3]
global_load_b32 v1, v2, s[0:1]
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v1
global_store_b32 v2, v0, s[2:3]
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_load_b64 v[0:1], v2, s[2:3]
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v1
global_store_b32 v2, v0, s[0:1]
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3mb2PfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z3mb2PfS_, .Lfunc_end1-_Z3mb2PfS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z2l1PfS_
.globl _Z2l1PfS_
.p2align 8
.type _Z2l1PfS_,@function
_Z2l1PfS_:
s_load_b32 s2, s[0:1], 0x1c
v_sub_nc_u32_e32 v0, 0, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s15, s15, s2
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e64 s15, v0
s_cbranch_execz .LBB2_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_clause 0x1
s_load_b32 s4, s[0:1], 0x0
s_load_b32 s5, s[0:1], 0x80
s_waitcnt lgkmcnt(0)
v_add_f32_e64 v1, s4, s5
global_store_b32 v0, v1, s[2:3]
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_clause 0x2
global_load_b32 v1, v0, s[0:1]
global_load_b32 v2, v0, s[0:1] offset:128
global_load_b32 v3, v0, s[2:3]
s_waitcnt vmcnt(1)
v_add_f32_e32 v1, v1, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v1, v1, v3
global_store_b32 v0, v1, s[2:3]
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z2l1PfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z2l1PfS_, .Lfunc_end2-_Z2l1PfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9irregulerPKfPfS1_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z9irregulerPKfPfS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3mb2PfS_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3mb2PfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z2l1PfS_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z2l1PfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <cstdio>
using namespace std;
#include <hip/hip_runtime.h>
#define TIMES 24
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////HELP FUNCTIONS/////////////////////////////////////////////////
void RandomInit(float* data, int n)
{
for (int i=0; i<n; i++)
{
data[i] = rand() / (float)RAND_MAX;
}
}
void RandomInit(unsigned* data, int n)
{
for (int i=0; i<n; i++)
{
data[i] = rand() % n;
}
}
#define checkCudaErrors(err) __checkCudaErrors (err, __FILE__, __LINE__)
inline void __checkCudaErrors(hipError_t err, const char *file, const int line )
{
if(hipSuccess != err)
{
fprintf(stderr, "%s(%i) : CUDA Runtime API error %d: %s.\n",file, line, (int)err, hipGetErrorString( err ) );
exit(-1);
}
}
// This will output the proper error string when calling cudaGetLastError
#define getLastCudaError(msg) __getLastCudaError (msg, __FILE__, __LINE__)
inline void __getLastCudaError(const char *errorMessage, const char *file, const int line )
{
hipError_t err = hipGetLastError();
if (hipSuccess != err)
{
fprintf(stderr, "%s(%i) : getLastCudaError() CUDA error : %s : (%d) %s.\n",
file, line, errorMessage, (int)err, hipGetErrorString( err ) );
exit(-1);
}
}
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////_VECTOR_ADDITION_///////////////////////////////////////////////////////
// Device code
__global__ void irreguler(const float* A, float* C, float* F)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i == 0)
{
C[i] = A[i];
__syncthreads();
//high latncy
C[i] = C[i] + A[i];
__syncthreads();
F[i] = C[i+1];
}
}
__global__ void mb2(float* A, float* C)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i == 0) {
C[i] = A[i]; //write to C[i] is a miss (cache line is missing)
__syncthreads();
C[i+1] = A[i]; //write to C[i+1] is a hit (cache line is found)
__syncthreads();
C[i] = C[i] + A[i]; //read of C[i] is a miss (entire sector is missing, fetch it from memory)
__syncthreads();
A[i] = C[i] + C[i+1]; //read C[i] and C[i+1] are hits (entire sector exists)
}
}
__global__ void l1(float* A, float* C)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i == 0) {
C[i] = A[i] + A[i+32];
__syncthreads();
C[i] = A[i] + A[i+32] + C[i];
}
}
// Host code
void VectorAddition(int N, int threadsPerBlock)
{
cout<<"Vector Addition for input size "<<N<<" :\n";
// Variables
float* h_A;
float* h_C;
float* d_A;
float* d_C;
float total_time=0;
size_t size = N * sizeof(float);
// Allocate input vectors h_A and h_B in host memory
h_A = (float*)malloc(size);
h_C = (float*)malloc(size);
// Initialize input vectors
RandomInit(h_A, N);
// Allocate vectors in device memory
checkCudaErrors( hipMalloc((void**)&d_A, size) );
checkCudaErrors( hipMalloc((void**)&d_C, size) );
// Copy vectors from host memory to device memory
checkCudaErrors( hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice) );
checkCudaErrors(hipDeviceSynchronize());
// Invoke kernel
cout<<"Invoke Kernel\n";
//int threads = 128;
int blocksPerGrid = ((N+ threadsPerBlock-1) / threadsPerBlock);
for (int i = 0; i < 1; i++) {
l1<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_C);
getLastCudaError("kernel launch failure");
checkCudaErrors(hipDeviceSynchronize());
}
float dSeconds = total_time/((float)TIMES * 1000);
float dNumOps = N;
float gflops = 1.0e-9 * dNumOps/dSeconds;
cout<<"Time = "<<dSeconds*1.0e3<< "msec"<<endl<<"gflops = "<<gflops<<endl;
// Copy result from device memory to host memory
// h_C contains the result in host memory
checkCudaErrors( hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost) );
// Verify result
int i;
for (i = 0; i < N; ++i) {
float sum = h_A[i];
if (fabs(h_C[i] - sum) > 1e-5)
break;
}
// Free device memory
if (d_A)
hipFree(d_A);
if (d_C)
hipFree(d_C);
// Free host memory
if (h_A)
free(h_A);
if (h_C)
free(h_C);
hipDeviceReset();
if(i == N)
cout<<"SUCCSESS"<<endl;
else
cout<<"FAILED"<<endl;
}
//////////////////////////////////////////////////////
int main(int argc,char *argv[])
{
if(argc < 3)
printf("Unsuffcient number of arguments!\n");
else
{
VectorAddition(atoi(argv[1]), atoi(argv[2]));
}
} | .text
.file "l2_write_policy.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z10RandomInitPfi
.LCPI0_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z10RandomInitPfi
.p2align 4, 0x90
.type _Z10RandomInitPfi,@function
_Z10RandomInitPfi: # @_Z10RandomInitPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI0_0(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB0_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB0_4: # %._crit_edge
retq
.Lfunc_end0:
.size _Z10RandomInitPfi, .Lfunc_end0-_Z10RandomInitPfi
.cfi_endproc
# -- End function
.globl _Z10RandomInitPji # -- Begin function _Z10RandomInitPji
.p2align 4, 0x90
.type _Z10RandomInitPji,@function
_Z10RandomInitPji: # @_Z10RandomInitPji
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %ebx
movq %rdi, %r14
movl %esi, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltd
idivl %ebx
movl %edx, (%r14,%r12,4)
incq %r12
cmpq %r12, %r15
jne .LBB1_2
# %bb.3:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z10RandomInitPji, .Lfunc_end1-_Z10RandomInitPji
.cfi_endproc
# -- End function
.globl _Z24__device_stub__irregulerPKfPfS1_ # -- Begin function _Z24__device_stub__irregulerPKfPfS1_
.p2align 4, 0x90
.type _Z24__device_stub__irregulerPKfPfS1_,@function
_Z24__device_stub__irregulerPKfPfS1_: # @_Z24__device_stub__irregulerPKfPfS1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9irregulerPKfPfS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z24__device_stub__irregulerPKfPfS1_, .Lfunc_end2-_Z24__device_stub__irregulerPKfPfS1_
.cfi_endproc
# -- End function
.globl _Z18__device_stub__mb2PfS_ # -- Begin function _Z18__device_stub__mb2PfS_
.p2align 4, 0x90
.type _Z18__device_stub__mb2PfS_,@function
_Z18__device_stub__mb2PfS_: # @_Z18__device_stub__mb2PfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3mb2PfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z18__device_stub__mb2PfS_, .Lfunc_end3-_Z18__device_stub__mb2PfS_
.cfi_endproc
# -- End function
.globl _Z17__device_stub__l1PfS_ # -- Begin function _Z17__device_stub__l1PfS_
.p2align 4, 0x90
.type _Z17__device_stub__l1PfS_,@function
_Z17__device_stub__l1PfS_: # @_Z17__device_stub__l1PfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z2l1PfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end4:
.size _Z17__device_stub__l1PfS_, .Lfunc_end4-_Z17__device_stub__l1PfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z14VectorAdditionii
.LCPI5_0:
.long 0x30000000 # float 4.65661287E-10
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI5_1:
.quad 0x3e112e0be826d695 # double 1.0000000000000001E-9
.LCPI5_3:
.quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5
.LCPI5_4:
.quad 0x0000000000000000 # double 0
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI5_2:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl _Z14VectorAdditionii
.p2align 4, 0x90
.type _Z14VectorAdditionii,@function
_Z14VectorAdditionii: # @_Z14VectorAdditionii
.cfi_startproc
# %bb.0: # %.critedge
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %r13d
movl %edi, %ebx
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $31, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, (%rsp) # 8-byte Spill
movslq %ebx, %rbp
leaq (,%rbp,4), %r12
movq %r12, %rdi
callq malloc
movq %rax, %r15
movq %r12, %rdi
callq malloc
movq %rax, %r14
movl %ebp, %ebx
testl %ebp, %ebp
jle .LBB5_3
# %bb.1: # %.lr.ph.preheader.i
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB5_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI5_0(%rip), %xmm0
movss %xmm0, (%r15,%rbp,4)
incq %rbp
cmpq %rbp, %rbx
jne .LBB5_2
.LBB5_3: # %_Z10RandomInitPfi.exit
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB5_44
# %bb.4: # %_Z17__checkCudaErrors10hipError_tPKci.exit
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB5_45
# %bb.5: # %_Z17__checkCudaErrors10hipError_tPKci.exit52
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB5_46
# %bb.6: # %_Z17__checkCudaErrors10hipError_tPKci.exit54
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB5_47
# %bb.7: # %_Z17__checkCudaErrors10hipError_tPKci.exit56
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rsp), %rax # 8-byte Reload
addl %r13d, %eax
decl %eax
cltd
idivl %r13d
# kill: def $eax killed $eax def $rax
movabsq $4294967296, %rcx # imm = 0x100000000
leaq (%rax,%rcx), %rdi
movl %r13d, %edx
orq %rcx, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_9
# %bb.8:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z2l1PfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_9:
callq hipGetLastError
testl %eax, %eax
jne .LBB5_48
# %bb.10: # %_Z18__getLastCudaErrorPKcS0_i.exit
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB5_49
# %bb.11: # %_Z17__checkCudaErrors10hipError_tPKci.exit59
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
xorps %xmm0, %xmm0
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r13
movl $.L.str.6, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r13), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %rbp
testq %rbp, %rbp
je .LBB5_43
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
xorps %xmm0, %xmm0
cvtsi2ssl (%rsp), %xmm0 # 4-byte Folded Reload
cvtss2sd %xmm0, %xmm0
mulsd .LCPI5_1(%rip), %xmm0
divsd .LCPI5_4(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 28(%rsp) # 4-byte Spill
cmpb $0, 56(%rbp)
je .LBB5_14
# %bb.13:
movzbl 67(%rbp), %eax
jmp .LBB5_15
.LBB5_14:
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.LBB5_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r13, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rax, %r13
movl $.L.str.7, %esi
movl $9, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 28(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r13
testq %r13, %r13
je .LBB5_43
# %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i63
cmpb $0, 56(%r13)
je .LBB5_18
# %bb.17:
movzbl 67(%r13), %ecx
jmp .LBB5_19
.LBB5_18:
movq %r13, %rdi
movq %rax, %rbp
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbp, %rax
.LBB5_19: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit66
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB5_50
# %bb.20: # %_Z17__checkCudaErrors10hipError_tPKci.exit61.preheader
cmpl $0, (%rsp) # 4-byte Folded Reload
jle .LBB5_25
# %bb.21: # %.lr.ph.preheader
xorl %r12d, %r12d
movaps .LCPI5_2(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movsd .LCPI5_3(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB5_22: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%r14,%r12,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss (%r15,%r12,4), %xmm2
andps %xmm0, %xmm2
cvtss2sd %xmm2, %xmm2
ucomisd %xmm1, %xmm2
ja .LBB5_26
# %bb.23: # %_Z17__checkCudaErrors10hipError_tPKci.exit61
# in Loop: Header=BB5_22 Depth=1
incq %r12
cmpq %r12, %rbx
jne .LBB5_22
# %bb.24: # %._crit_edge.loopexit
movl %ebx, %r12d
jmp .LBB5_26
.LBB5_25:
xorl %r12d, %r12d
.LBB5_26: # %._crit_edge
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB5_28
# %bb.27:
callq hipFree
.LBB5_28:
movq 8(%rsp), %rdi
testq %rdi, %rdi
je .LBB5_30
# %bb.29:
callq hipFree
.LBB5_30:
testq %r15, %r15
je .LBB5_32
# %bb.31:
movq %r15, %rdi
callq free
.LBB5_32:
testq %r14, %r14
je .LBB5_34
# %bb.33:
movq %r14, %rdi
callq free
.LBB5_34:
callq hipDeviceReset
cmpl (%rsp), %r12d # 4-byte Folded Reload
jne .LBB5_38
# %bb.35:
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB5_43
# %bb.36: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i68
cmpb $0, 56(%rbx)
je .LBB5_41
.LBB5_37:
movzbl 67(%rbx), %eax
jmp .LBB5_42
.LBB5_38:
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB5_43
# %bb.39: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i73
cmpb $0, 56(%rbx)
jne .LBB5_37
.LBB5_41:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB5_42: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit71
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_43:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.LBB5_44:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.11, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $123, %ecx
jmp .LBB5_51
.LBB5_45:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.11, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $124, %ecx
jmp .LBB5_51
.LBB5_46:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.11, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $128, %ecx
jmp .LBB5_51
.LBB5_47:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.11, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $130, %ecx
jmp .LBB5_51
.LBB5_48:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movq %rax, %r10
subq $8, %rsp
.cfi_adjust_cfa_offset 8
movl $.L.str.12, %esi
movl $.L.str.2, %edx
movl $.L.str.4, %r8d
movq %rbx, %rdi
movl $139, %ecx
movl %ebp, %r9d
xorl %eax, %eax
pushq %r10
.cfi_adjust_cfa_offset 8
callq fprintf
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $-1, %edi
callq exit
.LBB5_49:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.11, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $140, %ecx
jmp .LBB5_51
.LBB5_50:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.11, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $150, %ecx
.LBB5_51:
movl %ebp, %r8d
movq %rax, %r9
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end5:
.size _Z14VectorAdditionii, .Lfunc_end5-_Z14VectorAdditionii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
cmpl $2, %edi
jg .LBB6_2
# %bb.1:
movl $.Lstr, %edi
callq puts@PLT
jmp .LBB6_3
.LBB6_2:
movq 8(%rsi), %rdi
movq %rsi, %r14
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %ebx, %edi
movl %eax, %esi
callq _Z14VectorAdditionii
.LBB6_3:
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9irregulerPKfPfS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3mb2PfS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2l1PfS_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9irregulerPKfPfS1_,@object # @_Z9irregulerPKfPfS1_
.section .rodata,"a",@progbits
.globl _Z9irregulerPKfPfS1_
.p2align 3, 0x0
_Z9irregulerPKfPfS1_:
.quad _Z24__device_stub__irregulerPKfPfS1_
.size _Z9irregulerPKfPfS1_, 8
.type _Z3mb2PfS_,@object # @_Z3mb2PfS_
.globl _Z3mb2PfS_
.p2align 3, 0x0
_Z3mb2PfS_:
.quad _Z18__device_stub__mb2PfS_
.size _Z3mb2PfS_, 8
.type _Z2l1PfS_,@object # @_Z2l1PfS_
.globl _Z2l1PfS_
.p2align 3, 0x0
_Z2l1PfS_:
.quad _Z17__device_stub__l1PfS_
.size _Z2l1PfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Vector Addition for input size "
.size .L.str, 32
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " :\n"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/shen203/GPU_Microbenchmark/master/write_policy/l2_write_policy.hip"
.size .L.str.2, 124
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Invoke Kernel\n"
.size .L.str.3, 15
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "kernel launch failure"
.size .L.str.4, 22
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Time = "
.size .L.str.5, 8
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "msec"
.size .L.str.6, 5
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "gflops = "
.size .L.str.7, 10
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "SUCCSESS"
.size .L.str.8, 9
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "FAILED"
.size .L.str.9, 7
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "%s(%i) : CUDA Runtime API error %d: %s.\n"
.size .L.str.11, 41
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "%s(%i) : getLastCudaError() CUDA error : %s : (%d) %s.\n"
.size .L.str.12, 56
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9irregulerPKfPfS1_"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3mb2PfS_"
.size .L__unnamed_2, 11
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z2l1PfS_"
.size .L__unnamed_3, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Unsuffcient number of arguments!"
.size .Lstr, 33
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__irregulerPKfPfS1_
.addrsig_sym _Z18__device_stub__mb2PfS_
.addrsig_sym _Z17__device_stub__l1PfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9irregulerPKfPfS1_
.addrsig_sym _Z3mb2PfS_
.addrsig_sym _Z2l1PfS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z2l1PfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0030*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe40000000800 */
/*0040*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x001fe2000f8e023f */
/*0050*/ IADD3 R0, -R0, RZ, RZ ; /* 0x000000ff00007210 */
/* 0x002fca0007ffe1ff */
/*0060*/ ISETP.NE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf05270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0090*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00b0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R7, [R2.64+0x80] ; /* 0x0000800402077981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*00e0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe400078e00ff */
/*00f0*/ FADD R7, R0, R7 ; /* 0x0000000700077221 */
/* 0x004fca0000000000 */
/*0100*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe8000c101904 */
/*0110*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0120*/ LDG.E R0, [R2.64+0x80] ; /* 0x0000800402007981 */
/* 0x000ea8000c1e1900 */
/*0130*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea8000c1e1900 */
/*0140*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000ee2000c1e1900 */
/*0150*/ FADD R0, R0, R9 ; /* 0x0000000900007221 */
/* 0x004fc80000000000 */
/*0160*/ FADD R11, R0, R11 ; /* 0x0000000b000b7221 */
/* 0x008fca0000000000 */
/*0170*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x000fe2000c101904 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z3mb2PfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0030*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe40000000800 */
/*0040*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x001fe2000f8e023f */
/*0050*/ IADD3 R0, -R0, RZ, RZ ; /* 0x000000ff00007210 */
/* 0x002fca0007ffe1ff */
/*0060*/ ISETP.NE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf05270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0090*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00b0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fca00078e00ff */
/*00e0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0041e8000c101904 */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0100*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea8000c1e1900 */
/*0110*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x004fe8000c101904 */
/*0120*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0130*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0140*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000ea4000c1e1900 */
/*0150*/ FADD R11, R0, R11 ; /* 0x0000000b000b7221 */
/* 0x004fca0000000000 */
/*0160*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x000fe8000c101904 */
/*0170*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0180*/ LDG.E R0, [R4.64+0x4] ; /* 0x0000040404007981 */
/* 0x000ea8000c1e1900 */
/*0190*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x001ea4000c1e1900 */
/*01a0*/ FADD R7, R0, R7 ; /* 0x0000000700077221 */
/* 0x004fca0000000000 */
/*01b0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9irregulerPKfPfS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0030*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe40000000800 */
/*0040*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x001fe2000f8e023f */
/*0050*/ IMAD.MOV R0, RZ, RZ, -R0 ; /* 0x000000ffff007224 */
/* 0x002fca00078e0a00 */
/*0060*/ ISETP.NE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf05270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0090*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00b0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fca00078e00ff */
/*00e0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x004fe8000c101904 */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0100*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*0120*/ FADD R11, R0, R7 ; /* 0x00000007000b7221 */
/* 0x004fca0000000000 */
/*0130*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x000fe8000c101904 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0150*/ LDG.E R13, [R4.64+0x4] ; /* 0x00000404040d7981 */
/* 0x000ea2000c1e1900 */
/*0160*/ MOV R6, c[0x0][0x170] ; /* 0x00005c0000067a02 */
/* 0x000fc40000000f00 */
/*0170*/ MOV R7, c[0x0][0x174] ; /* 0x00005d0000077a02 */
/* 0x000fca0000000f00 */
/*0180*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x004fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9irregulerPKfPfS1_
.globl _Z9irregulerPKfPfS1_
.p2align 8
.type _Z9irregulerPKfPfS1_,@function
_Z9irregulerPKfPfS1_:
s_load_b32 s2, s[0:1], 0x24
v_sub_nc_u32_e32 v0, 0, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s15, s15, s2
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e64 s15, v0
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[6:7]
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_clause 0x1
global_load_b32 v1, v0, s[6:7]
global_load_b32 v2, v0, s[4:5]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[6:7]
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_load_b32 s2, s[6:7], 0x4
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v1, s2
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9irregulerPKfPfS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9irregulerPKfPfS1_, .Lfunc_end0-_Z9irregulerPKfPfS1_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3mb2PfS_
.globl _Z3mb2PfS_
.p2align 8
.type _Z3mb2PfS_,@function
_Z3mb2PfS_:
s_load_b32 s2, s[0:1], 0x1c
v_sub_nc_u32_e32 v0, 0, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s15, s15, s2
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e64 s15, v0
s_cbranch_execz .LBB1_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v0, s4
global_store_b32 v2, v0, s[2:3]
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_load_b32 v0, v2, s[0:1]
s_waitcnt vmcnt(0)
global_store_b32 v2, v0, s[2:3] offset:4
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_clause 0x1
global_load_b32 v0, v2, s[2:3]
global_load_b32 v1, v2, s[0:1]
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v1
global_store_b32 v2, v0, s[2:3]
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_load_b64 v[0:1], v2, s[2:3]
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v1
global_store_b32 v2, v0, s[0:1]
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3mb2PfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z3mb2PfS_, .Lfunc_end1-_Z3mb2PfS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z2l1PfS_
.globl _Z2l1PfS_
.p2align 8
.type _Z2l1PfS_,@function
_Z2l1PfS_:
s_load_b32 s2, s[0:1], 0x1c
v_sub_nc_u32_e32 v0, 0, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s15, s15, s2
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e64 s15, v0
s_cbranch_execz .LBB2_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_clause 0x1
s_load_b32 s4, s[0:1], 0x0
s_load_b32 s5, s[0:1], 0x80
s_waitcnt lgkmcnt(0)
v_add_f32_e64 v1, s4, s5
global_store_b32 v0, v1, s[2:3]
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_clause 0x2
global_load_b32 v1, v0, s[0:1]
global_load_b32 v2, v0, s[0:1] offset:128
global_load_b32 v3, v0, s[2:3]
s_waitcnt vmcnt(1)
v_add_f32_e32 v1, v1, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v1, v1, v3
global_store_b32 v0, v1, s[2:3]
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z2l1PfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z2l1PfS_, .Lfunc_end2-_Z2l1PfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9irregulerPKfPfS1_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z9irregulerPKfPfS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3mb2PfS_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3mb2PfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z2l1PfS_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z2l1PfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00029620_00000000-6_l2_write_policy.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3677:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3677:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10RandomInitPfi
.type _Z10RandomInitPfi, @function
_Z10RandomInitPfi:
.LFB3669:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE3669:
.size _Z10RandomInitPfi, .-_Z10RandomInitPfi
.globl _Z10RandomInitPji
.type _Z10RandomInitPji, @function
_Z10RandomInitPji:
.LFB3670:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L16
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %esi, %ebp
movq %rdi, %rbx
movslq %esi, %rax
leaq (%rdi,%rax,4), %r12
.L13:
call rand@PLT
cltd
idivl %ebp
movl %edx, (%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L13
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE3670:
.size _Z10RandomInitPji, .-_Z10RandomInitPji
.globl _Z34__device_stub__Z9irregulerPKfPfS1_PKfPfS1_
.type _Z34__device_stub__Z9irregulerPKfPfS1_PKfPfS1_, @function
_Z34__device_stub__Z9irregulerPKfPfS1_PKfPfS1_:
.LFB3699:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9irregulerPKfPfS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _Z34__device_stub__Z9irregulerPKfPfS1_PKfPfS1_, .-_Z34__device_stub__Z9irregulerPKfPfS1_PKfPfS1_
.globl _Z9irregulerPKfPfS1_
.type _Z9irregulerPKfPfS1_, @function
_Z9irregulerPKfPfS1_:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9irregulerPKfPfS1_PKfPfS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _Z9irregulerPKfPfS1_, .-_Z9irregulerPKfPfS1_
.globl _Z24__device_stub__Z3mb2PfS_PfS_
.type _Z24__device_stub__Z3mb2PfS_PfS_, @function
_Z24__device_stub__Z3mb2PfS_PfS_:
.LFB3701:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3mb2PfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3701:
.size _Z24__device_stub__Z3mb2PfS_PfS_, .-_Z24__device_stub__Z3mb2PfS_PfS_
.globl _Z3mb2PfS_
.type _Z3mb2PfS_, @function
_Z3mb2PfS_:
.LFB3702:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3mb2PfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _Z3mb2PfS_, .-_Z3mb2PfS_
.globl _Z23__device_stub__Z2l1PfS_PfS_
.type _Z23__device_stub__Z2l1PfS_PfS_, @function
_Z23__device_stub__Z2l1PfS_PfS_:
.LFB3703:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z2l1PfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3703:
.size _Z23__device_stub__Z2l1PfS_PfS_, .-_Z23__device_stub__Z2l1PfS_PfS_
.globl _Z2l1PfS_
.type _Z2l1PfS_, @function
_Z2l1PfS_:
.LFB3704:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z2l1PfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3704:
.size _Z2l1PfS_, .-_Z2l1PfS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Vector Addition for input size "
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string " :\n"
.section .rodata.str1.8
.align 8
.LC3:
.string "/home/ubuntu/Datasets/stackv2/train-structured/shen203/GPU_Microbenchmark/master/write_policy/l2_write_policy.cu"
.align 8
.LC4:
.string "%s(%i) : CUDA Runtime API error %d: %s.\n"
.section .rodata.str1.1
.LC5:
.string "Invoke Kernel\n"
.LC6:
.string "kernel launch failure"
.section .rodata.str1.8
.align 8
.LC7:
.string "%s(%i) : getLastCudaError() CUDA error : %s : (%d) %s.\n"
.section .rodata.str1.1
.LC10:
.string "Time = "
.LC11:
.string "msec"
.LC12:
.string "gflops = "
.LC15:
.string "SUCCSESS"
.LC16:
.string "FAILED"
.text
.globl _Z14VectorAdditionii
.type _Z14VectorAdditionii, @function
_Z14VectorAdditionii:
.LFB3673:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movl %edi, %r13d
movl %esi, %r15d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $31, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r13d, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $3, %edx
leaq .LC2(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movslq %r13d, %r12
leaq 0(,%r12,4), %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
movl %r13d, %esi
movq %rbx, %rdi
call _Z10RandomInitPfi
leaq 16(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L86
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L87
movl $1, %ecx
movq %r14, %rdx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L88
call cudaThreadSynchronize@PLT
testl %eax, %eax
jne .L89
movl $14, %edx
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r15d, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leal -1(%r13,%r15), %eax
cltd
idivl %r15d
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L90
.L48:
call cudaGetLastError@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L91
call cudaThreadSynchronize@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L92
pxor %xmm0, %xmm0
cvtsi2ssl %r13d, %xmm0
cvtss2sd %xmm0, %xmm0
mulsd .LC8(%rip), %xmm0
pxor %xmm1, %xmm1
divsd %xmm1, %xmm0
pxor %xmm3, %xmm3
cvtsd2ss %xmm0, %xmm3
movss %xmm3, (%rsp)
movl $7, %edx
leaq .LC10(%rip), %rsi
leaq _ZSt4cout(%rip), %r15
movq %r15, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
movq %r15, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %r15
movq %rax, 8(%rsp)
movl $4, %edx
leaq .LC11(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r15
testq %r15, %r15
je .L93
cmpb $0, 56(%r15)
je .L53
movzbl 67(%r15), %esi
.L54:
movsbl %sil, %esi
movq 8(%rsp), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq %rax, %r15
movl $9, %edx
leaq .LC12(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%rsp), %xmm0
movq %r15, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rcx
movq %rax, (%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rcx,%rax), %r15
testq %r15, %r15
je .L94
cmpb $0, 56(%r15)
je .L57
movzbl 67(%r15), %esi
.L58:
movsbl %sil, %esi
movq (%rsp), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $2, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %r14d
testl %eax, %eax
jne .L59
movl $0, %eax
testl %r13d, %r13d
jle .L83
movss .LC13(%rip), %xmm2
movsd .LC14(%rip), %xmm1
jmp .L60
.L86:
movl %eax, %ebx
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 136
pushq %rax
.cfi_def_cfa_offset 144
movl %ebx, %r9d
movl $123, %r8d
leaq .LC3(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L87:
.cfi_restore_state
movl %eax, %ebx
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 136
pushq %rax
.cfi_def_cfa_offset 144
movl %ebx, %r9d
movl $124, %r8d
leaq .LC3(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L88:
.cfi_restore_state
movl %eax, %ebx
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 136
pushq %rax
.cfi_def_cfa_offset 144
movl %ebx, %r9d
movl $128, %r8d
leaq .LC3(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L89:
.cfi_restore_state
movl %eax, %ebx
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 136
pushq %rax
.cfi_def_cfa_offset 144
movl %ebx, %r9d
movl $130, %r8d
leaq .LC3(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L90:
.cfi_restore_state
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z23__device_stub__Z2l1PfS_PfS_
jmp .L48
.L91:
movl %eax, %edi
call cudaGetErrorString@PLT
pushq %rax
.cfi_remember_state
.cfi_def_cfa_offset 136
pushq %r15
.cfi_def_cfa_offset 144
leaq .LC6(%rip), %r9
movl $139, %r8d
leaq .LC3(%rip), %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L92:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 136
pushq %rax
.cfi_def_cfa_offset 144
movl %r15d, %r9d
movl $140, %r8d
leaq .LC3(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L93:
.cfi_restore_state
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L95
call _ZSt16__throw_bad_castv@PLT
.L95:
call __stack_chk_fail@PLT
.L53:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L54
.L94:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L96
call _ZSt16__throw_bad_castv@PLT
.L96:
call __stack_chk_fail@PLT
.L57:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L58
.L83:
movl $0, %r12d
jmp .L61
.L59:
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 136
pushq %rax
.cfi_def_cfa_offset 144
movl %r14d, %r9d
movl $150, %r8d
leaq .LC3(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L80:
.cfi_restore_state
movq %rdx, %rax
.L60:
movss 0(%rbp,%rax,4), %xmm0
subss (%rbx,%rax,4), %xmm0
andps %xmm2, %xmm0
cvtss2sd %xmm0, %xmm0
comisd %xmm1, %xmm0
ja .L97
leaq 1(%rax), %rdx
cmpq %rdx, %r12
jne .L80
leal 1(%rax), %r12d
jmp .L61
.L97:
movl %eax, %r12d
.L61:
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .L64
call cudaFree@PLT
.L64:
movq 24(%rsp), %rdi
testq %rdi, %rdi
je .L65
call cudaFree@PLT
.L65:
testq %rbx, %rbx
je .L66
movq %rbx, %rdi
call free@PLT
.L66:
testq %rbp, %rbp
je .L67
movq %rbp, %rdi
call free@PLT
.L67:
call cudaDeviceReset@PLT
cmpl %r13d, %r12d
je .L98
movl $6, %edx
leaq .LC16(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L99
cmpb $0, 56(%rbx)
je .L76
movzbl 67(%rbx), %esi
.L77:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.L43:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L100
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L98:
.cfi_restore_state
movl $8, %edx
leaq .LC15(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L101
cmpb $0, 56(%rbx)
je .L71
movzbl 67(%rbx), %esi
.L72:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L43
.L101:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L102
call _ZSt16__throw_bad_castv@PLT
.L102:
call __stack_chk_fail@PLT
.L71:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L72
.L99:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L103
call _ZSt16__throw_bad_castv@PLT
.L103:
call __stack_chk_fail@PLT
.L76:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L77
.L100:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3673:
.size _Z14VectorAdditionii, .-_Z14VectorAdditionii
.section .rodata.str1.8
.align 8
.LC17:
.string "Unsuffcient number of arguments!\n"
.text
.globl main
.type main, @function
main:
.LFB3674:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
cmpl $2, %edi
jg .L105
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L106:
movl $0, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L105:
.cfi_restore_state
movq %rsi, %rbx
movq 16(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %ebp, %esi
movl %eax, %edi
call _Z14VectorAdditionii
jmp .L106
.cfi_endproc
.LFE3674:
.size main, .-main
.section .rodata.str1.1
.LC18:
.string "_Z2l1PfS_"
.LC19:
.string "_Z3mb2PfS_"
.LC20:
.string "_Z9irregulerPKfPfS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3706:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z2l1PfS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z3mb2PfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z9irregulerPKfPfS1_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3706:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC8:
.long -400107883
.long 1041313291
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC13:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC14:
.long -1998362383
.long 1055193269
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "l2_write_policy.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z10RandomInitPfi
.LCPI0_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z10RandomInitPfi
.p2align 4, 0x90
.type _Z10RandomInitPfi,@function
_Z10RandomInitPfi: # @_Z10RandomInitPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI0_0(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB0_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB0_4: # %._crit_edge
retq
.Lfunc_end0:
.size _Z10RandomInitPfi, .Lfunc_end0-_Z10RandomInitPfi
.cfi_endproc
# -- End function
.globl _Z10RandomInitPji # -- Begin function _Z10RandomInitPji
.p2align 4, 0x90
.type _Z10RandomInitPji,@function
_Z10RandomInitPji: # @_Z10RandomInitPji
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %ebx
movq %rdi, %r14
movl %esi, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltd
idivl %ebx
movl %edx, (%r14,%r12,4)
incq %r12
cmpq %r12, %r15
jne .LBB1_2
# %bb.3:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z10RandomInitPji, .Lfunc_end1-_Z10RandomInitPji
.cfi_endproc
# -- End function
.globl _Z24__device_stub__irregulerPKfPfS1_ # -- Begin function _Z24__device_stub__irregulerPKfPfS1_
.p2align 4, 0x90
.type _Z24__device_stub__irregulerPKfPfS1_,@function
_Z24__device_stub__irregulerPKfPfS1_: # @_Z24__device_stub__irregulerPKfPfS1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9irregulerPKfPfS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z24__device_stub__irregulerPKfPfS1_, .Lfunc_end2-_Z24__device_stub__irregulerPKfPfS1_
.cfi_endproc
# -- End function
.globl _Z18__device_stub__mb2PfS_ # -- Begin function _Z18__device_stub__mb2PfS_
.p2align 4, 0x90
.type _Z18__device_stub__mb2PfS_,@function
_Z18__device_stub__mb2PfS_: # @_Z18__device_stub__mb2PfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3mb2PfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z18__device_stub__mb2PfS_, .Lfunc_end3-_Z18__device_stub__mb2PfS_
.cfi_endproc
# -- End function
.globl _Z17__device_stub__l1PfS_ # -- Begin function _Z17__device_stub__l1PfS_
.p2align 4, 0x90
.type _Z17__device_stub__l1PfS_,@function
_Z17__device_stub__l1PfS_: # @_Z17__device_stub__l1PfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z2l1PfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end4:
.size _Z17__device_stub__l1PfS_, .Lfunc_end4-_Z17__device_stub__l1PfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z14VectorAdditionii
.LCPI5_0:
.long 0x30000000 # float 4.65661287E-10
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI5_1:
.quad 0x3e112e0be826d695 # double 1.0000000000000001E-9
.LCPI5_3:
.quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5
.LCPI5_4:
.quad 0x0000000000000000 # double 0
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI5_2:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl _Z14VectorAdditionii
.p2align 4, 0x90
.type _Z14VectorAdditionii,@function
_Z14VectorAdditionii: # @_Z14VectorAdditionii
.cfi_startproc
# %bb.0: # %.critedge
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %r13d
movl %edi, %ebx
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $31, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, (%rsp) # 8-byte Spill
movslq %ebx, %rbp
leaq (,%rbp,4), %r12
movq %r12, %rdi
callq malloc
movq %rax, %r15
movq %r12, %rdi
callq malloc
movq %rax, %r14
movl %ebp, %ebx
testl %ebp, %ebp
jle .LBB5_3
# %bb.1: # %.lr.ph.preheader.i
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB5_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI5_0(%rip), %xmm0
movss %xmm0, (%r15,%rbp,4)
incq %rbp
cmpq %rbp, %rbx
jne .LBB5_2
.LBB5_3: # %_Z10RandomInitPfi.exit
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB5_44
# %bb.4: # %_Z17__checkCudaErrors10hipError_tPKci.exit
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB5_45
# %bb.5: # %_Z17__checkCudaErrors10hipError_tPKci.exit52
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB5_46
# %bb.6: # %_Z17__checkCudaErrors10hipError_tPKci.exit54
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB5_47
# %bb.7: # %_Z17__checkCudaErrors10hipError_tPKci.exit56
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rsp), %rax # 8-byte Reload
addl %r13d, %eax
decl %eax
cltd
idivl %r13d
# kill: def $eax killed $eax def $rax
movabsq $4294967296, %rcx # imm = 0x100000000
leaq (%rax,%rcx), %rdi
movl %r13d, %edx
orq %rcx, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_9
# %bb.8:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z2l1PfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_9:
callq hipGetLastError
testl %eax, %eax
jne .LBB5_48
# %bb.10: # %_Z18__getLastCudaErrorPKcS0_i.exit
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB5_49
# %bb.11: # %_Z17__checkCudaErrors10hipError_tPKci.exit59
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
xorps %xmm0, %xmm0
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r13
movl $.L.str.6, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r13), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %rbp
testq %rbp, %rbp
je .LBB5_43
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
xorps %xmm0, %xmm0
cvtsi2ssl (%rsp), %xmm0 # 4-byte Folded Reload
cvtss2sd %xmm0, %xmm0
mulsd .LCPI5_1(%rip), %xmm0
divsd .LCPI5_4(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 28(%rsp) # 4-byte Spill
cmpb $0, 56(%rbp)
je .LBB5_14
# %bb.13:
movzbl 67(%rbp), %eax
jmp .LBB5_15
.LBB5_14:
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.LBB5_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r13, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rax, %r13
movl $.L.str.7, %esi
movl $9, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 28(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r13
testq %r13, %r13
je .LBB5_43
# %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i63
cmpb $0, 56(%r13)
je .LBB5_18
# %bb.17:
movzbl 67(%r13), %ecx
jmp .LBB5_19
.LBB5_18:
movq %r13, %rdi
movq %rax, %rbp
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbp, %rax
.LBB5_19: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit66
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB5_50
# %bb.20: # %_Z17__checkCudaErrors10hipError_tPKci.exit61.preheader
cmpl $0, (%rsp) # 4-byte Folded Reload
jle .LBB5_25
# %bb.21: # %.lr.ph.preheader
xorl %r12d, %r12d
movaps .LCPI5_2(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movsd .LCPI5_3(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB5_22: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%r14,%r12,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss (%r15,%r12,4), %xmm2
andps %xmm0, %xmm2
cvtss2sd %xmm2, %xmm2
ucomisd %xmm1, %xmm2
ja .LBB5_26
# %bb.23: # %_Z17__checkCudaErrors10hipError_tPKci.exit61
# in Loop: Header=BB5_22 Depth=1
incq %r12
cmpq %r12, %rbx
jne .LBB5_22
# %bb.24: # %._crit_edge.loopexit
movl %ebx, %r12d
jmp .LBB5_26
.LBB5_25:
xorl %r12d, %r12d
.LBB5_26: # %._crit_edge
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB5_28
# %bb.27:
callq hipFree
.LBB5_28:
movq 8(%rsp), %rdi
testq %rdi, %rdi
je .LBB5_30
# %bb.29:
callq hipFree
.LBB5_30:
testq %r15, %r15
je .LBB5_32
# %bb.31:
movq %r15, %rdi
callq free
.LBB5_32:
testq %r14, %r14
je .LBB5_34
# %bb.33:
movq %r14, %rdi
callq free
.LBB5_34:
callq hipDeviceReset
cmpl (%rsp), %r12d # 4-byte Folded Reload
jne .LBB5_38
# %bb.35:
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB5_43
# %bb.36: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i68
cmpb $0, 56(%rbx)
je .LBB5_41
.LBB5_37:
movzbl 67(%rbx), %eax
jmp .LBB5_42
.LBB5_38:
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB5_43
# %bb.39: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i73
cmpb $0, 56(%rbx)
jne .LBB5_37
.LBB5_41:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB5_42: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit71
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_43:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.LBB5_44:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.11, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $123, %ecx
jmp .LBB5_51
.LBB5_45:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.11, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $124, %ecx
jmp .LBB5_51
.LBB5_46:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.11, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $128, %ecx
jmp .LBB5_51
.LBB5_47:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.11, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $130, %ecx
jmp .LBB5_51
.LBB5_48:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movq %rax, %r10
subq $8, %rsp
.cfi_adjust_cfa_offset 8
movl $.L.str.12, %esi
movl $.L.str.2, %edx
movl $.L.str.4, %r8d
movq %rbx, %rdi
movl $139, %ecx
movl %ebp, %r9d
xorl %eax, %eax
pushq %r10
.cfi_adjust_cfa_offset 8
callq fprintf
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $-1, %edi
callq exit
.LBB5_49:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.11, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $140, %ecx
jmp .LBB5_51
.LBB5_50:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.11, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $150, %ecx
.LBB5_51:
movl %ebp, %r8d
movq %rax, %r9
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end5:
.size _Z14VectorAdditionii, .Lfunc_end5-_Z14VectorAdditionii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
cmpl $2, %edi
jg .LBB6_2
# %bb.1:
movl $.Lstr, %edi
callq puts@PLT
jmp .LBB6_3
.LBB6_2:
movq 8(%rsi), %rdi
movq %rsi, %r14
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %ebx, %edi
movl %eax, %esi
callq _Z14VectorAdditionii
.LBB6_3:
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9irregulerPKfPfS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3mb2PfS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2l1PfS_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9irregulerPKfPfS1_,@object # @_Z9irregulerPKfPfS1_
.section .rodata,"a",@progbits
.globl _Z9irregulerPKfPfS1_
.p2align 3, 0x0
_Z9irregulerPKfPfS1_:
.quad _Z24__device_stub__irregulerPKfPfS1_
.size _Z9irregulerPKfPfS1_, 8
.type _Z3mb2PfS_,@object # @_Z3mb2PfS_
.globl _Z3mb2PfS_
.p2align 3, 0x0
_Z3mb2PfS_:
.quad _Z18__device_stub__mb2PfS_
.size _Z3mb2PfS_, 8
.type _Z2l1PfS_,@object # @_Z2l1PfS_
.globl _Z2l1PfS_
.p2align 3, 0x0
_Z2l1PfS_:
.quad _Z17__device_stub__l1PfS_
.size _Z2l1PfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Vector Addition for input size "
.size .L.str, 32
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " :\n"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/shen203/GPU_Microbenchmark/master/write_policy/l2_write_policy.hip"
.size .L.str.2, 124
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Invoke Kernel\n"
.size .L.str.3, 15
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "kernel launch failure"
.size .L.str.4, 22
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Time = "
.size .L.str.5, 8
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "msec"
.size .L.str.6, 5
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "gflops = "
.size .L.str.7, 10
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "SUCCSESS"
.size .L.str.8, 9
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "FAILED"
.size .L.str.9, 7
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "%s(%i) : CUDA Runtime API error %d: %s.\n"
.size .L.str.11, 41
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "%s(%i) : getLastCudaError() CUDA error : %s : (%d) %s.\n"
.size .L.str.12, 56
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9irregulerPKfPfS1_"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3mb2PfS_"
.size .L__unnamed_2, 11
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z2l1PfS_"
.size .L__unnamed_3, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Unsuffcient number of arguments!"
.size .Lstr, 33
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__irregulerPKfPfS1_
.addrsig_sym _Z18__device_stub__mb2PfS_
.addrsig_sym _Z17__device_stub__l1PfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9irregulerPKfPfS1_
.addrsig_sym _Z3mb2PfS_
.addrsig_sym _Z2l1PfS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C"
#include <cuComplex.h>
__global__ void rdiv_double(int n, double *a, double *b, double *sum)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n)
sum[i] = b[i] / a[i];
} | code for sm_80
Function : _Z11rdiv_doubleiPdS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R10, R10, c[0x0][0x0], R3 ; /* 0x000000000a0a7a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R10, c[0x0][0x160], PT ; /* 0x000058000a007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R6, R10, R5, c[0x0][0x168] ; /* 0x00005a000a067625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ IMAD.WIDE R4, R10, R5, c[0x0][0x170] ; /* 0x00005c000a047625 */
/* 0x000fcc00078e0205 */
/*00b0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee2000c1e1b00 */
/*00c0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fe200078e00ff */
/*00d0*/ BSSY B0, 0x200 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*00e0*/ MUFU.RCP64H R3, R7 ; /* 0x0000000700037308 */
/* 0x004e220000001800 */
/*00f0*/ FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; /* 0x036000000500780b */
/* 0x008fc60003f2e200 */
/*0100*/ DFMA R8, -R6, R2, 1 ; /* 0x3ff000000608742b */
/* 0x001e0c0000000102 */
/*0110*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0120*/ DFMA R8, R2, R8, R2 ; /* 0x000000080208722b */
/* 0x001e0c0000000002 */
/*0130*/ DFMA R2, -R6, R8, 1 ; /* 0x3ff000000602742b */
/* 0x001e0c0000000108 */
/*0140*/ DFMA R2, R8, R2, R8 ; /* 0x000000020802722b */
/* 0x001e0c0000000008 */
/*0150*/ DMUL R8, R4, R2 ; /* 0x0000000204087228 */
/* 0x001e0c0000000000 */
/*0160*/ DFMA R12, -R6, R8, R4 ; /* 0x00000008060c722b */
/* 0x001e0c0000000104 */
/*0170*/ DFMA R2, R2, R12, R8 ; /* 0x0000000c0202722b */
/* 0x001e140000000008 */
/*0180*/ FFMA R0, RZ, R7, R3 ; /* 0x00000007ff007223 */
/* 0x001fca0000000003 */
/*0190*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*01a0*/ @P0 BRA P1, 0x1f0 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*01b0*/ MOV R0, 0x1d0 ; /* 0x000001d000007802 */
/* 0x000fe40000000f00 */
/*01c0*/ CALL.REL.NOINC 0x240 ; /* 0x0000007000007944 */
/* 0x000fea0003c00000 */
/*01d0*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000c */
/*01e0*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000d */
/*01f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0200*/ IMAD.MOV.U32 R11, RZ, RZ, 0x8 ; /* 0x00000008ff0b7424 */
/* 0x000fc800078e00ff */
/*0210*/ IMAD.WIDE R10, R10, R11, c[0x0][0x178] ; /* 0x00005e000a0a7625 */
/* 0x000fca00078e020b */
/*0220*/ STG.E.64 [R10.64], R2 ; /* 0x000000020a007986 */
/* 0x000fe2000c101b04 */
/*0230*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0240*/ FSETP.GEU.AND P0, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f0e200 */
/*0250*/ IMAD.MOV.U32 R12, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0c7424 */
/* 0x000fe200078e00ff */
/*0260*/ LOP3.LUT R2, R7, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff07027812 */
/* 0x000fe200078ec0ff */
/*0270*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1 ; /* 0x00000001ff0e7424 */
/* 0x000fe200078e00ff */
/*0280*/ FSETP.GEU.AND P2, PT, |R5|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x040fe20003f4e200 */
/*0290*/ BSSY B1, 0x7d0 ; /* 0x0000053000017945 */
/* 0x000fe20003800000 */
/*02a0*/ LOP3.LUT R3, R2, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000002037812 */
/* 0x000fe200078efcff */
/*02b0*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0006 */
/*02c0*/ LOP3.LUT R11, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000050b7812 */
/* 0x000fe400078ec0ff */
/*02d0*/ LOP3.LUT R16, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007107812 */
/* 0x000fc600078ec0ff */
/*02e0*/ @!P0 DMUL R2, R6, 8.98846567431157953865e+307 ; /* 0x7fe0000006028828 */
/* 0x000e220000000000 */
/*02f0*/ ISETP.GE.U32.AND P1, PT, R11, R16, PT ; /* 0x000000100b00720c */
/* 0x000fe20003f26070 */
/*0300*/ IMAD.MOV.U32 R17, RZ, RZ, R11 ; /* 0x000000ffff117224 */
/* 0x000fe400078e000b */
/*0310*/ @!P2 LOP3.LUT R8, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000708a812 */
/* 0x000fe200078ec0ff */
/*0320*/ @!P2 IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff14a224 */
/* 0x000fe200078e00ff */
/*0330*/ MUFU.RCP64H R15, R3 ; /* 0x00000003000f7308 */
/* 0x001e220000001800 */
/*0340*/ SEL R9, R12, 0x63400000, !P1 ; /* 0x634000000c097807 */
/* 0x000fe40004800000 */
/*0350*/ @!P2 ISETP.GE.U32.AND P3, PT, R11, R8, PT ; /* 0x000000080b00a20c */
/* 0x000fe20003f66070 */
/*0360*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*0370*/ LOP3.LUT R9, R9, 0x800fffff, R5, 0xf8, !PT ; /* 0x800fffff09097812 */
/* 0x000fc400078ef805 */
/*0380*/ @!P2 SEL R13, R12, 0x63400000, !P3 ; /* 0x634000000c0da807 */
/* 0x000fe40005800000 */
/*0390*/ @!P0 LOP3.LUT R16, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003108812 */
/* 0x000fe400078ec0ff */
/*03a0*/ @!P2 LOP3.LUT R13, R13, 0x80000000, R5, 0xf8, !PT ; /* 0x800000000d0da812 */
/* 0x000fe400078ef805 */
/*03b0*/ IADD3 R22, R16, -0x1, RZ ; /* 0xffffffff10167810 */
/* 0x000fe40007ffe0ff */
/*03c0*/ @!P2 LOP3.LUT R21, R13, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000d15a812 */
/* 0x000fe200078efcff */
/*03d0*/ DFMA R18, R14, -R2, 1 ; /* 0x3ff000000e12742b */
/* 0x001e0a0000000802 */
/*03e0*/ @!P2 DFMA R8, R8, 2, -R20 ; /* 0x400000000808a82b */
/* 0x000fc80000000814 */
/*03f0*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x001e0c0000000012 */
/*0400*/ DFMA R14, R14, R18, R14 ; /* 0x000000120e0e722b */
/* 0x001e22000000000e */
/*0410*/ @!P2 LOP3.LUT R17, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000911a812 */
/* 0x000fc800078ec0ff */
/*0420*/ IADD3 R13, R17, -0x1, RZ ; /* 0xffffffff110d7810 */
/* 0x000fe20007ffe0ff */
/*0430*/ DFMA R18, R14, -R2, 1 ; /* 0x3ff000000e12742b */
/* 0x001e060000000802 */
/*0440*/ ISETP.GT.U32.AND P0, PT, R13, 0x7feffffe, PT ; /* 0x7feffffe0d00780c */
/* 0x000fc60003f04070 */
/*0450*/ DFMA R14, R14, R18, R14 ; /* 0x000000120e0e722b */
/* 0x001e22000000000e */
/*0460*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fca0000704470 */
/*0470*/ DMUL R18, R14, R8 ; /* 0x000000080e127228 */
/* 0x001e0c0000000000 */
/*0480*/ DFMA R20, R18, -R2, R8 ; /* 0x800000021214722b */
/* 0x001e0c0000000008 */
/*0490*/ DFMA R14, R14, R20, R18 ; /* 0x000000140e0e722b */
/* 0x0010620000000012 */
/*04a0*/ @P0 BRA 0x670 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*04b0*/ LOP3.LUT R16, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007107812 */
/* 0x000fc800078ec0ff */
/*04c0*/ ISETP.GE.U32.AND P0, PT, R11.reuse, R16, PT ; /* 0x000000100b00720c */
/* 0x040fe20003f06070 */
/*04d0*/ IMAD.IADD R4, R11, 0x1, -R16 ; /* 0x000000010b047824 */
/* 0x000fc600078e0a10 */
/*04e0*/ SEL R11, R12, 0x63400000, !P0 ; /* 0x634000000c0b7807 */
/* 0x000fe40004000000 */
/*04f0*/ IMNMX R4, R4, -0x46a00000, !PT ; /* 0xb960000004047817 */
/* 0x000fc80007800200 */
/*0500*/ IMNMX R4, R4, 0x46a00000, PT ; /* 0x46a0000004047817 */
/* 0x000fca0003800200 */
/*0510*/ IMAD.IADD R11, R4, 0x1, -R11 ; /* 0x00000001040b7824 */
/* 0x000fe400078e0a0b */
/*0520*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc600078e00ff */
/*0530*/ IADD3 R5, R11, 0x7fe00000, RZ ; /* 0x7fe000000b057810 */
/* 0x000fcc0007ffe0ff */
/*0540*/ DMUL R12, R14, R4 ; /* 0x000000040e0c7228 */
/* 0x002e540000000000 */
/*0550*/ FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x002fda0003f0c200 */
/*0560*/ @P0 BRA 0x7c0 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0570*/ DFMA R2, R14, -R2, R8 ; /* 0x800000020e02722b */
/* 0x000e620000000008 */
/*0580*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fd200078e00ff */
/*0590*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x042fe40003f0d000 */
/*05a0*/ LOP3.LUT R7, R3, 0x80000000, R7, 0x48, !PT ; /* 0x8000000003077812 */
/* 0x000fc800078e4807 */
/*05b0*/ LOP3.LUT R5, R7, R5, RZ, 0xfc, !PT ; /* 0x0000000507057212 */
/* 0x000fce00078efcff */
/*05c0*/ @!P0 BRA 0x7c0 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*05d0*/ IMAD.MOV R3, RZ, RZ, -R11 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a0b */
/*05e0*/ DMUL.RP R4, R14, R4 ; /* 0x000000040e047228 */
/* 0x000e620000008000 */
/*05f0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*0600*/ IADD3 R11, -R11, -0x43300000, RZ ; /* 0xbcd000000b0b7810 */
/* 0x000fca0007ffe1ff */
/*0610*/ DFMA R2, R12, -R2, R14 ; /* 0x800000020c02722b */
/* 0x000e86000000000e */
/*0620*/ LOP3.LUT R7, R5, R7, RZ, 0x3c, !PT ; /* 0x0000000705077212 */
/* 0x002fce00078e3cff */
/*0630*/ FSETP.NEU.AND P0, PT, |R3|, R11, PT ; /* 0x0000000b0300720b */
/* 0x004fc80003f0d200 */
/*0640*/ FSEL R12, R4, R12, !P0 ; /* 0x0000000c040c7208 */
/* 0x000fe40004000000 */
/*0650*/ FSEL R13, R7, R13, !P0 ; /* 0x0000000d070d7208 */
/* 0x000fe20004000000 */
/*0660*/ BRA 0x7c0 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0670*/ DSETP.NAN.AND P0, PT, R4, R4, PT ; /* 0x000000040400722a */
/* 0x000e9c0003f08000 */
/*0680*/ @P0 BRA 0x7a0 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*0690*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x000e9c0003f08000 */
/*06a0*/ @P0 BRA 0x770 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*06b0*/ ISETP.NE.AND P0, PT, R17, R16, PT ; /* 0x000000101100720c */
/* 0x000fe20003f05270 */
/*06c0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x000fe400078e00ff */
/*06d0*/ IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; /* 0xfff80000ff0d7424 */
/* 0x000fd400078e00ff */
/*06e0*/ @!P0 BRA 0x7c0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*06f0*/ ISETP.NE.AND P0, PT, R17, 0x7ff00000, PT ; /* 0x7ff000001100780c */
/* 0x000fe40003f05270 */
/*0700*/ LOP3.LUT R13, R5, 0x80000000, R7, 0x48, !PT ; /* 0x80000000050d7812 */
/* 0x000fe400078e4807 */
/*0710*/ ISETP.EQ.OR P0, PT, R16, RZ, !P0 ; /* 0x000000ff1000720c */
/* 0x000fda0004702670 */
/*0720*/ @P0 LOP3.LUT R2, R13, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000d020812 */
/* 0x000fe200078efcff */
/*0730*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c8224 */
/* 0x000fe400078e00ff */
/*0740*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c0224 */
/* 0x000fe400078e00ff */
/*0750*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, R2 ; /* 0x000000ffff0d0224 */
/* 0x000fe200078e0002 */
/*0760*/ BRA 0x7c0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0770*/ LOP3.LUT R13, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000070d7812 */
/* 0x000fe200078efcff */
/*0780*/ IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0006 */
/*0790*/ BRA 0x7c0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*07a0*/ LOP3.LUT R13, R5, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000050d7812 */
/* 0x000fe200078efcff */
/*07b0*/ IMAD.MOV.U32 R12, RZ, RZ, R4 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0004 */
/*07c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*07d0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*07e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*07f0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff80002007950 */
/* 0x000fea0003c3ffff */
/*0800*/ BRA 0x800; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C"
#include <cuComplex.h>
__global__ void rdiv_double(int n, double *a, double *b, double *sum)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n)
sum[i] = b[i] / a[i];
} | .file "tmpxft_000eb26a_00000000-6_rdiv.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z11rdiv_doubleiPdS_S_iPdS_S_
.type _Z36__device_stub__Z11rdiv_doubleiPdS_S_iPdS_S_, @function
_Z36__device_stub__Z11rdiv_doubleiPdS_S_iPdS_S_:
.LFB2074:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11rdiv_doubleiPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2074:
.size _Z36__device_stub__Z11rdiv_doubleiPdS_S_iPdS_S_, .-_Z36__device_stub__Z11rdiv_doubleiPdS_S_iPdS_S_
.globl _Z11rdiv_doubleiPdS_S_
.type _Z11rdiv_doubleiPdS_S_, @function
_Z11rdiv_doubleiPdS_S_:
.LFB2075:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11rdiv_doubleiPdS_S_iPdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2075:
.size _Z11rdiv_doubleiPdS_S_, .-_Z11rdiv_doubleiPdS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11rdiv_doubleiPdS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2077:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11rdiv_doubleiPdS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2077:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C"
#include <cuComplex.h>
__global__ void rdiv_double(int n, double *a, double *b, double *sum)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n)
sum[i] = b[i] / a[i];
} | extern "C"
#include <hip/hip_runtime.h>
#include <hip/hip_complex.h>
__global__ void rdiv_double(int n, double *a, double *b, double *sum)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n)
sum[i] = b[i] / a[i];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | extern "C"
#include <hip/hip_runtime.h>
#include <hip/hip_complex.h>
__global__ void rdiv_double(int n, double *a, double *b, double *sum)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n)
sum[i] = b[i] / a[i];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11rdiv_doubleiPdS_S_
.globl _Z11rdiv_doubleiPdS_S_
.p2align 8
.type _Z11rdiv_doubleiPdS_S_,@function
_Z11rdiv_doubleiPdS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
s_waitcnt vmcnt(0)
v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_div_scale_f64 v[10:11], vcc_lo, v[2:3], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[12:13], v[10:11], v[8:9]
v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_div_fixup_f64 v[2:3], v[6:7], v[4:5], v[2:3]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11rdiv_doubleiPdS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11rdiv_doubleiPdS_S_, .Lfunc_end0-_Z11rdiv_doubleiPdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11rdiv_doubleiPdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11rdiv_doubleiPdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | extern "C"
#include <hip/hip_runtime.h>
#include <hip/hip_complex.h>
__global__ void rdiv_double(int n, double *a, double *b, double *sum)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n)
sum[i] = b[i] / a[i];
} | .text
.file "rdiv.hip"
.globl _Z26__device_stub__rdiv_doubleiPdS_S_ # -- Begin function _Z26__device_stub__rdiv_doubleiPdS_S_
.p2align 4, 0x90
.type _Z26__device_stub__rdiv_doubleiPdS_S_,@function
_Z26__device_stub__rdiv_doubleiPdS_S_: # @_Z26__device_stub__rdiv_doubleiPdS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11rdiv_doubleiPdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__rdiv_doubleiPdS_S_, .Lfunc_end0-_Z26__device_stub__rdiv_doubleiPdS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11rdiv_doubleiPdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11rdiv_doubleiPdS_S_,@object # @_Z11rdiv_doubleiPdS_S_
.section .rodata,"a",@progbits
.globl _Z11rdiv_doubleiPdS_S_
.p2align 3, 0x0
_Z11rdiv_doubleiPdS_S_:
.quad _Z26__device_stub__rdiv_doubleiPdS_S_
.size _Z11rdiv_doubleiPdS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11rdiv_doubleiPdS_S_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__rdiv_doubleiPdS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11rdiv_doubleiPdS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11rdiv_doubleiPdS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R10, R10, c[0x0][0x0], R3 ; /* 0x000000000a0a7a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R10, c[0x0][0x160], PT ; /* 0x000058000a007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R6, R10, R5, c[0x0][0x168] ; /* 0x00005a000a067625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ IMAD.WIDE R4, R10, R5, c[0x0][0x170] ; /* 0x00005c000a047625 */
/* 0x000fcc00078e0205 */
/*00b0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee2000c1e1b00 */
/*00c0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fe200078e00ff */
/*00d0*/ BSSY B0, 0x200 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*00e0*/ MUFU.RCP64H R3, R7 ; /* 0x0000000700037308 */
/* 0x004e220000001800 */
/*00f0*/ FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; /* 0x036000000500780b */
/* 0x008fc60003f2e200 */
/*0100*/ DFMA R8, -R6, R2, 1 ; /* 0x3ff000000608742b */
/* 0x001e0c0000000102 */
/*0110*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0120*/ DFMA R8, R2, R8, R2 ; /* 0x000000080208722b */
/* 0x001e0c0000000002 */
/*0130*/ DFMA R2, -R6, R8, 1 ; /* 0x3ff000000602742b */
/* 0x001e0c0000000108 */
/*0140*/ DFMA R2, R8, R2, R8 ; /* 0x000000020802722b */
/* 0x001e0c0000000008 */
/*0150*/ DMUL R8, R4, R2 ; /* 0x0000000204087228 */
/* 0x001e0c0000000000 */
/*0160*/ DFMA R12, -R6, R8, R4 ; /* 0x00000008060c722b */
/* 0x001e0c0000000104 */
/*0170*/ DFMA R2, R2, R12, R8 ; /* 0x0000000c0202722b */
/* 0x001e140000000008 */
/*0180*/ FFMA R0, RZ, R7, R3 ; /* 0x00000007ff007223 */
/* 0x001fca0000000003 */
/*0190*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*01a0*/ @P0 BRA P1, 0x1f0 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*01b0*/ MOV R0, 0x1d0 ; /* 0x000001d000007802 */
/* 0x000fe40000000f00 */
/*01c0*/ CALL.REL.NOINC 0x240 ; /* 0x0000007000007944 */
/* 0x000fea0003c00000 */
/*01d0*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000c */
/*01e0*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000d */
/*01f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0200*/ IMAD.MOV.U32 R11, RZ, RZ, 0x8 ; /* 0x00000008ff0b7424 */
/* 0x000fc800078e00ff */
/*0210*/ IMAD.WIDE R10, R10, R11, c[0x0][0x178] ; /* 0x00005e000a0a7625 */
/* 0x000fca00078e020b */
/*0220*/ STG.E.64 [R10.64], R2 ; /* 0x000000020a007986 */
/* 0x000fe2000c101b04 */
/*0230*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0240*/ FSETP.GEU.AND P0, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f0e200 */
/*0250*/ IMAD.MOV.U32 R12, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0c7424 */
/* 0x000fe200078e00ff */
/*0260*/ LOP3.LUT R2, R7, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff07027812 */
/* 0x000fe200078ec0ff */
/*0270*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1 ; /* 0x00000001ff0e7424 */
/* 0x000fe200078e00ff */
/*0280*/ FSETP.GEU.AND P2, PT, |R5|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x040fe20003f4e200 */
/*0290*/ BSSY B1, 0x7d0 ; /* 0x0000053000017945 */
/* 0x000fe20003800000 */
/*02a0*/ LOP3.LUT R3, R2, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000002037812 */
/* 0x000fe200078efcff */
/*02b0*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0006 */
/*02c0*/ LOP3.LUT R11, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000050b7812 */
/* 0x000fe400078ec0ff */
/*02d0*/ LOP3.LUT R16, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007107812 */
/* 0x000fc600078ec0ff */
/*02e0*/ @!P0 DMUL R2, R6, 8.98846567431157953865e+307 ; /* 0x7fe0000006028828 */
/* 0x000e220000000000 */
/*02f0*/ ISETP.GE.U32.AND P1, PT, R11, R16, PT ; /* 0x000000100b00720c */
/* 0x000fe20003f26070 */
/*0300*/ IMAD.MOV.U32 R17, RZ, RZ, R11 ; /* 0x000000ffff117224 */
/* 0x000fe400078e000b */
/*0310*/ @!P2 LOP3.LUT R8, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000708a812 */
/* 0x000fe200078ec0ff */
/*0320*/ @!P2 IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff14a224 */
/* 0x000fe200078e00ff */
/*0330*/ MUFU.RCP64H R15, R3 ; /* 0x00000003000f7308 */
/* 0x001e220000001800 */
/*0340*/ SEL R9, R12, 0x63400000, !P1 ; /* 0x634000000c097807 */
/* 0x000fe40004800000 */
/*0350*/ @!P2 ISETP.GE.U32.AND P3, PT, R11, R8, PT ; /* 0x000000080b00a20c */
/* 0x000fe20003f66070 */
/*0360*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*0370*/ LOP3.LUT R9, R9, 0x800fffff, R5, 0xf8, !PT ; /* 0x800fffff09097812 */
/* 0x000fc400078ef805 */
/*0380*/ @!P2 SEL R13, R12, 0x63400000, !P3 ; /* 0x634000000c0da807 */
/* 0x000fe40005800000 */
/*0390*/ @!P0 LOP3.LUT R16, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003108812 */
/* 0x000fe400078ec0ff */
/*03a0*/ @!P2 LOP3.LUT R13, R13, 0x80000000, R5, 0xf8, !PT ; /* 0x800000000d0da812 */
/* 0x000fe400078ef805 */
/*03b0*/ IADD3 R22, R16, -0x1, RZ ; /* 0xffffffff10167810 */
/* 0x000fe40007ffe0ff */
/*03c0*/ @!P2 LOP3.LUT R21, R13, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000d15a812 */
/* 0x000fe200078efcff */
/*03d0*/ DFMA R18, R14, -R2, 1 ; /* 0x3ff000000e12742b */
/* 0x001e0a0000000802 */
/*03e0*/ @!P2 DFMA R8, R8, 2, -R20 ; /* 0x400000000808a82b */
/* 0x000fc80000000814 */
/*03f0*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x001e0c0000000012 */
/*0400*/ DFMA R14, R14, R18, R14 ; /* 0x000000120e0e722b */
/* 0x001e22000000000e */
/*0410*/ @!P2 LOP3.LUT R17, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000911a812 */
/* 0x000fc800078ec0ff */
/*0420*/ IADD3 R13, R17, -0x1, RZ ; /* 0xffffffff110d7810 */
/* 0x000fe20007ffe0ff */
/*0430*/ DFMA R18, R14, -R2, 1 ; /* 0x3ff000000e12742b */
/* 0x001e060000000802 */
/*0440*/ ISETP.GT.U32.AND P0, PT, R13, 0x7feffffe, PT ; /* 0x7feffffe0d00780c */
/* 0x000fc60003f04070 */
/*0450*/ DFMA R14, R14, R18, R14 ; /* 0x000000120e0e722b */
/* 0x001e22000000000e */
/*0460*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fca0000704470 */
/*0470*/ DMUL R18, R14, R8 ; /* 0x000000080e127228 */
/* 0x001e0c0000000000 */
/*0480*/ DFMA R20, R18, -R2, R8 ; /* 0x800000021214722b */
/* 0x001e0c0000000008 */
/*0490*/ DFMA R14, R14, R20, R18 ; /* 0x000000140e0e722b */
/* 0x0010620000000012 */
/*04a0*/ @P0 BRA 0x670 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*04b0*/ LOP3.LUT R16, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007107812 */
/* 0x000fc800078ec0ff */
/*04c0*/ ISETP.GE.U32.AND P0, PT, R11.reuse, R16, PT ; /* 0x000000100b00720c */
/* 0x040fe20003f06070 */
/*04d0*/ IMAD.IADD R4, R11, 0x1, -R16 ; /* 0x000000010b047824 */
/* 0x000fc600078e0a10 */
/*04e0*/ SEL R11, R12, 0x63400000, !P0 ; /* 0x634000000c0b7807 */
/* 0x000fe40004000000 */
/*04f0*/ IMNMX R4, R4, -0x46a00000, !PT ; /* 0xb960000004047817 */
/* 0x000fc80007800200 */
/*0500*/ IMNMX R4, R4, 0x46a00000, PT ; /* 0x46a0000004047817 */
/* 0x000fca0003800200 */
/*0510*/ IMAD.IADD R11, R4, 0x1, -R11 ; /* 0x00000001040b7824 */
/* 0x000fe400078e0a0b */
/*0520*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc600078e00ff */
/*0530*/ IADD3 R5, R11, 0x7fe00000, RZ ; /* 0x7fe000000b057810 */
/* 0x000fcc0007ffe0ff */
/*0540*/ DMUL R12, R14, R4 ; /* 0x000000040e0c7228 */
/* 0x002e540000000000 */
/*0550*/ FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x002fda0003f0c200 */
/*0560*/ @P0 BRA 0x7c0 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0570*/ DFMA R2, R14, -R2, R8 ; /* 0x800000020e02722b */
/* 0x000e620000000008 */
/*0580*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fd200078e00ff */
/*0590*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x042fe40003f0d000 */
/*05a0*/ LOP3.LUT R7, R3, 0x80000000, R7, 0x48, !PT ; /* 0x8000000003077812 */
/* 0x000fc800078e4807 */
/*05b0*/ LOP3.LUT R5, R7, R5, RZ, 0xfc, !PT ; /* 0x0000000507057212 */
/* 0x000fce00078efcff */
/*05c0*/ @!P0 BRA 0x7c0 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*05d0*/ IMAD.MOV R3, RZ, RZ, -R11 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a0b */
/*05e0*/ DMUL.RP R4, R14, R4 ; /* 0x000000040e047228 */
/* 0x000e620000008000 */
/*05f0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*0600*/ IADD3 R11, -R11, -0x43300000, RZ ; /* 0xbcd000000b0b7810 */
/* 0x000fca0007ffe1ff */
/*0610*/ DFMA R2, R12, -R2, R14 ; /* 0x800000020c02722b */
/* 0x000e86000000000e */
/*0620*/ LOP3.LUT R7, R5, R7, RZ, 0x3c, !PT ; /* 0x0000000705077212 */
/* 0x002fce00078e3cff */
/*0630*/ FSETP.NEU.AND P0, PT, |R3|, R11, PT ; /* 0x0000000b0300720b */
/* 0x004fc80003f0d200 */
/*0640*/ FSEL R12, R4, R12, !P0 ; /* 0x0000000c040c7208 */
/* 0x000fe40004000000 */
/*0650*/ FSEL R13, R7, R13, !P0 ; /* 0x0000000d070d7208 */
/* 0x000fe20004000000 */
/*0660*/ BRA 0x7c0 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0670*/ DSETP.NAN.AND P0, PT, R4, R4, PT ; /* 0x000000040400722a */
/* 0x000e9c0003f08000 */
/*0680*/ @P0 BRA 0x7a0 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*0690*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x000e9c0003f08000 */
/*06a0*/ @P0 BRA 0x770 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*06b0*/ ISETP.NE.AND P0, PT, R17, R16, PT ; /* 0x000000101100720c */
/* 0x000fe20003f05270 */
/*06c0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x000fe400078e00ff */
/*06d0*/ IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; /* 0xfff80000ff0d7424 */
/* 0x000fd400078e00ff */
/*06e0*/ @!P0 BRA 0x7c0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*06f0*/ ISETP.NE.AND P0, PT, R17, 0x7ff00000, PT ; /* 0x7ff000001100780c */
/* 0x000fe40003f05270 */
/*0700*/ LOP3.LUT R13, R5, 0x80000000, R7, 0x48, !PT ; /* 0x80000000050d7812 */
/* 0x000fe400078e4807 */
/*0710*/ ISETP.EQ.OR P0, PT, R16, RZ, !P0 ; /* 0x000000ff1000720c */
/* 0x000fda0004702670 */
/*0720*/ @P0 LOP3.LUT R2, R13, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000d020812 */
/* 0x000fe200078efcff */
/*0730*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c8224 */
/* 0x000fe400078e00ff */
/*0740*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c0224 */
/* 0x000fe400078e00ff */
/*0750*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, R2 ; /* 0x000000ffff0d0224 */
/* 0x000fe200078e0002 */
/*0760*/ BRA 0x7c0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0770*/ LOP3.LUT R13, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000070d7812 */
/* 0x000fe200078efcff */
/*0780*/ IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0006 */
/*0790*/ BRA 0x7c0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*07a0*/ LOP3.LUT R13, R5, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000050d7812 */
/* 0x000fe200078efcff */
/*07b0*/ IMAD.MOV.U32 R12, RZ, RZ, R4 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0004 */
/*07c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*07d0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*07e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*07f0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff80002007950 */
/* 0x000fea0003c3ffff */
/*0800*/ BRA 0x800; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11rdiv_doubleiPdS_S_
.globl _Z11rdiv_doubleiPdS_S_
.p2align 8
.type _Z11rdiv_doubleiPdS_S_,@function
_Z11rdiv_doubleiPdS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
s_waitcnt vmcnt(0)
v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_div_scale_f64 v[10:11], vcc_lo, v[2:3], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[12:13], v[10:11], v[8:9]
v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_div_fixup_f64 v[2:3], v[6:7], v[4:5], v[2:3]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11rdiv_doubleiPdS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11rdiv_doubleiPdS_S_, .Lfunc_end0-_Z11rdiv_doubleiPdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11rdiv_doubleiPdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11rdiv_doubleiPdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000eb26a_00000000-6_rdiv.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z11rdiv_doubleiPdS_S_iPdS_S_
.type _Z36__device_stub__Z11rdiv_doubleiPdS_S_iPdS_S_, @function
_Z36__device_stub__Z11rdiv_doubleiPdS_S_iPdS_S_:
.LFB2074:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11rdiv_doubleiPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2074:
.size _Z36__device_stub__Z11rdiv_doubleiPdS_S_iPdS_S_, .-_Z36__device_stub__Z11rdiv_doubleiPdS_S_iPdS_S_
.globl _Z11rdiv_doubleiPdS_S_
.type _Z11rdiv_doubleiPdS_S_, @function
_Z11rdiv_doubleiPdS_S_:
.LFB2075:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11rdiv_doubleiPdS_S_iPdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2075:
.size _Z11rdiv_doubleiPdS_S_, .-_Z11rdiv_doubleiPdS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11rdiv_doubleiPdS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2077:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11rdiv_doubleiPdS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2077:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "rdiv.hip"
.globl _Z26__device_stub__rdiv_doubleiPdS_S_ # -- Begin function _Z26__device_stub__rdiv_doubleiPdS_S_
.p2align 4, 0x90
.type _Z26__device_stub__rdiv_doubleiPdS_S_,@function
_Z26__device_stub__rdiv_doubleiPdS_S_: # @_Z26__device_stub__rdiv_doubleiPdS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11rdiv_doubleiPdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__rdiv_doubleiPdS_S_, .Lfunc_end0-_Z26__device_stub__rdiv_doubleiPdS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11rdiv_doubleiPdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11rdiv_doubleiPdS_S_,@object # @_Z11rdiv_doubleiPdS_S_
.section .rodata,"a",@progbits
.globl _Z11rdiv_doubleiPdS_S_
.p2align 3, 0x0
_Z11rdiv_doubleiPdS_S_:
.quad _Z26__device_stub__rdiv_doubleiPdS_S_
.size _Z11rdiv_doubleiPdS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11rdiv_doubleiPdS_S_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__rdiv_doubleiPdS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11rdiv_doubleiPdS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
#include "SDTorus.cuh"
#include "cuda_runtime.h"
SDTorus::SDTorus(float outer, float radius, glm::vec3 position) : dimensions(glm::vec2(outer, radius)), position(position)
{
}
inline DistancePrimitive*
SDTorus::copyToDevice()
{
SDTorus* deviceTorus;
cudaMalloc((void **)&deviceTorus, sizeof(SDTorus));
cudaMemcpy(deviceTorus, this, sizeof(SDTorus), cudaMemcpyHostToDevice);
return deviceTorus;
}
inline float
SDTorus::distanceFromPoint(glm::vec3 point)
{
point -= position;
glm::vec2 q = glm::vec2(GLMUtil::length(glm::vec2(point.x, point.y)) - dimensions.x, point.z);
return GLMUtil::length(q) - dimensions.y;
}
inline AABB
SDTorus::calculateBoundingVolume()
{
return AABB(glm::vec2(0, 0), glm::vec2(0, 0));
}
*/ | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
#include "SDTorus.cuh"
#include "cuda_runtime.h"
SDTorus::SDTorus(float outer, float radius, glm::vec3 position) : dimensions(glm::vec2(outer, radius)), position(position)
{
}
inline DistancePrimitive*
SDTorus::copyToDevice()
{
SDTorus* deviceTorus;
cudaMalloc((void **)&deviceTorus, sizeof(SDTorus));
cudaMemcpy(deviceTorus, this, sizeof(SDTorus), cudaMemcpyHostToDevice);
return deviceTorus;
}
inline float
SDTorus::distanceFromPoint(glm::vec3 point)
{
point -= position;
glm::vec2 q = glm::vec2(GLMUtil::length(glm::vec2(point.x, point.y)) - dimensions.x, point.z);
return GLMUtil::length(q) - dimensions.y;
}
inline AABB
SDTorus::calculateBoundingVolume()
{
return AABB(glm::vec2(0, 0), glm::vec2(0, 0));
}
*/ | .file "tmpxft_001b6da0_00000000-6_SDTorus.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
#include "SDTorus.cuh"
#include "cuda_runtime.h"
SDTorus::SDTorus(float outer, float radius, glm::vec3 position) : dimensions(glm::vec2(outer, radius)), position(position)
{
}
inline DistancePrimitive*
SDTorus::copyToDevice()
{
SDTorus* deviceTorus;
cudaMalloc((void **)&deviceTorus, sizeof(SDTorus));
cudaMemcpy(deviceTorus, this, sizeof(SDTorus), cudaMemcpyHostToDevice);
return deviceTorus;
}
inline float
SDTorus::distanceFromPoint(glm::vec3 point)
{
point -= position;
glm::vec2 q = glm::vec2(GLMUtil::length(glm::vec2(point.x, point.y)) - dimensions.x, point.z);
return GLMUtil::length(q) - dimensions.y;
}
inline AABB
SDTorus::calculateBoundingVolume()
{
return AABB(glm::vec2(0, 0), glm::vec2(0, 0));
}
*/ | #include <hip/hip_runtime.h>
/*
#include "SDTorus.cuh"
#include "cuda_runtime.h"
SDTorus::SDTorus(float outer, float radius, glm::vec3 position) : dimensions(glm::vec2(outer, radius)), position(position)
{
}
inline DistancePrimitive*
SDTorus::copyToDevice()
{
SDTorus* deviceTorus;
cudaMalloc((void **)&deviceTorus, sizeof(SDTorus));
cudaMemcpy(deviceTorus, this, sizeof(SDTorus), cudaMemcpyHostToDevice);
return deviceTorus;
}
inline float
SDTorus::distanceFromPoint(glm::vec3 point)
{
point -= position;
glm::vec2 q = glm::vec2(GLMUtil::length(glm::vec2(point.x, point.y)) - dimensions.x, point.z);
return GLMUtil::length(q) - dimensions.y;
}
inline AABB
SDTorus::calculateBoundingVolume()
{
return AABB(glm::vec2(0, 0), glm::vec2(0, 0));
}
*/ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*
#include "SDTorus.cuh"
#include "cuda_runtime.h"
SDTorus::SDTorus(float outer, float radius, glm::vec3 position) : dimensions(glm::vec2(outer, radius)), position(position)
{
}
inline DistancePrimitive*
SDTorus::copyToDevice()
{
SDTorus* deviceTorus;
cudaMalloc((void **)&deviceTorus, sizeof(SDTorus));
cudaMemcpy(deviceTorus, this, sizeof(SDTorus), cudaMemcpyHostToDevice);
return deviceTorus;
}
inline float
SDTorus::distanceFromPoint(glm::vec3 point)
{
point -= position;
glm::vec2 q = glm::vec2(GLMUtil::length(glm::vec2(point.x, point.y)) - dimensions.x, point.z);
return GLMUtil::length(q) - dimensions.y;
}
inline AABB
SDTorus::calculateBoundingVolume()
{
return AABB(glm::vec2(0, 0), glm::vec2(0, 0));
}
*/ | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*
#include "SDTorus.cuh"
#include "cuda_runtime.h"
SDTorus::SDTorus(float outer, float radius, glm::vec3 position) : dimensions(glm::vec2(outer, radius)), position(position)
{
}
inline DistancePrimitive*
SDTorus::copyToDevice()
{
SDTorus* deviceTorus;
cudaMalloc((void **)&deviceTorus, sizeof(SDTorus));
cudaMemcpy(deviceTorus, this, sizeof(SDTorus), cudaMemcpyHostToDevice);
return deviceTorus;
}
inline float
SDTorus::distanceFromPoint(glm::vec3 point)
{
point -= position;
glm::vec2 q = glm::vec2(GLMUtil::length(glm::vec2(point.x, point.y)) - dimensions.x, point.z);
return GLMUtil::length(q) - dimensions.y;
}
inline AABB
SDTorus::calculateBoundingVolume()
{
return AABB(glm::vec2(0, 0), glm::vec2(0, 0));
}
*/ | .text
.file "SDTorus.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b6da0_00000000-6_SDTorus.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "SDTorus.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <limits.h>
#include <time.h>
#define NV 5 // number of vertices
void createGraph(float *arr, int N) {
time_t t; // used for randomizing values
int col;
int row;
int maxWeight = 100; // limit the weight an edge can have
srand((unsigned) time(&t)); // generate random
for (col = 0; col < sqrt(N); col++) {
for(row = 0; row < sqrt(N); row++) {
if( col != row){
arr[(int)(row*sqrt(N)) + col] = rand() % maxWeight; // assign random
// have a symmetric graph
arr[(int)(col*sqrt(N)) + row] = arr[(int)(row*sqrt(N)) + col];
}
else
arr[(int)(row*sqrt(N)) + col] = 0; // NO LOOPS
}
}
}
void printGraph(float *arr, int n) {
for (int i = 0; i < n; i++) {
for(int j = 0; j < n; j++) {
printf("%f ", arr[i * n + j]);
}
printf("\n");
}
}
__global__ void gpuFloyd(int n, float* arr, int k) {
int tid = threadIdx.x;
int gid = blockIdx.x * blockDim.x + threadIdx.x;
if(gid >= n) {
return;
}
int idx = n * blockIdx.y + gid;
__shared__ int shortest_distance;
if(tid == 0) {
shortest_distance = arr[n * blockIdx.y + k];
}
__syncthreads();
int node_distance = arr[k * n + gid];
int total_distance = shortest_distance + node_distance;
if (arr[idx] > total_distance){
arr[idx] = total_distance;
}
__syncthreads();
}
void cpuFloyd(int n, float* cpuGraph) {
for (int k = 0; k < n; k++) {
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
if (cpuGraph[i * n + j] > (cpuGraph[i * n + k] + cpuGraph[k * n + j])) {
cpuGraph[i * n + j] = cpuGraph[i * n + k] + cpuGraph[k * n + j];
}
}
}
}
}
void valid(int n, float* cpuGraph, float* gpuGraph) {
printf("VALIDATING that cpuGraph array from CPU and gpuGraph array from GPU match... \n");
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
if (cpuGraph[i * n + j] != gpuGraph[i * n + j]) {
printf("ERROR MISMATCH in array cpuGraph i %d j %d CPU SAYS %f and GPU SAYS %f \n", i, j, cpuGraph[i * n + j], gpuGraph[i * n + j]);
}
}
}
printf("OK \n\n");
}
int main(int argc, char **argv) {
clock_t t;
float *hostArr, *gpuGraph;
float *devArr;
float *graph, *cpuGraph;
int i, j;
int n = NV;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
printf("\n");
printf("RUNNING WITH %d VERTICES \n", n);
printf("\n");
cudaMalloc(&devArr, n * n * sizeof (float));
//CPU arrays
graph = (float *) malloc(n * n * sizeof (float));
cpuGraph = (float *) malloc(n * n * sizeof (float));
//GPU arrays
hostArr = (float *) malloc(n * n * sizeof (float));
gpuGraph = (float *) malloc(n * n * sizeof (float));
// Randomize distances in between each node
createGraph(graph, (n*n));
// Printing graph
//printGraph(graph, n);
for (i = 0; i < n; i++) {
for (j = 0; j < n; j++) {
cpuGraph[i * n + j] = graph[i * n + j];
hostArr[i * n + j] = graph[i * n + j];
}
}
// First Mem Copy
cudaMemcpy(devArr, hostArr, n * n * sizeof (float), cudaMemcpyHostToDevice);
// For GPU Calculation
int gputhreads = 512;
// Kernel call
// dim3 dimGrid(n, n, 1);
dim3 dimGrid((n + gputhreads - 1) / gputhreads, n);
cudaEventRecord(start);
for(int k = 0; k < n; k++) {
gpuFloyd<<<dimGrid, gputhreads>>>(n, devArr, k);
}
cudaEventRecord(stop);
// Second Mem Copy
cudaMemcpy(gpuGraph, devArr, n * n * sizeof (float), cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("GPU Calculation Time elapsed: %.20f milliseconds\n", milliseconds);
// CPU calculation
t = clock();
cpuFloyd(n, cpuGraph);
t = clock() - t;
printf("CPU Calculation Time elapsed: %.20f milliseconds\n\n", (((float)t)/CLOCKS_PER_SEC)*1000);
// Check validation of cpuGraph array from CPU calc and gpuGraph array from GPU calc
// See if the two arrays match
valid(n, cpuGraph, gpuGraph);
/*
printf("Graph from GPU:\n");
printGraph(gpuGraph, n);
printf("\n");
printf("Graph from CPU:\n");
printGraph(cpuGraph, n);
printf("\n");
*/
cudaFree(devArr);
free(graph);
free(cpuGraph);
free(hostArr);
free(gpuGraph);
printf("FINISHED!!! \n");
return 0;
} | code for sm_80
Function : _Z8gpuFloydiPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e220000002600 */
/*0070*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f05270 */
/*0080*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0090*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd40000000a00 */
/*00b0*/ @!P0 IMAD R2, R7, R4, c[0x0][0x170] ; /* 0x00005c0007028624 */
/* 0x001fc800078e0204 */
/*00c0*/ @!P0 IMAD.WIDE.U32 R2, R2, R9, c[0x0][0x168] ; /* 0x00005a0002028625 */
/* 0x000fcc00078e0009 */
/*00d0*/ @!P0 LDG.E R2, [R2.64] ; /* 0x0000000402028981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD R4, R4, c[0x0][0x170], R0 ; /* 0x00005c0004047a24 */
/* 0x000fc800078e0200 */
/*00f0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0209 */
/*0100*/ IMAD R6, R7, c[0x0][0x160], R0 ; /* 0x0000580007067a24 */
/* 0x000fc800078e0200 */
/*0110*/ IMAD.WIDE R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fe200078e0209 */
/*0120*/ @!P0 F2I.TRUNC.NTZ R8, R2 ; /* 0x0000000200088305 */
/* 0x004e24000020f100 */
/*0130*/ @!P0 STS [RZ], R8 ; /* 0x00000008ff008388 */
/* 0x001fe80000000800 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0150*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0160*/ LDG.E R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x000ee8000c1e1900 */
/*0170*/ LDS R9, [RZ] ; /* 0x00000000ff097984 */
/* 0x000e220000000800 */
/*0180*/ F2I.TRUNC.NTZ R0, R4 ; /* 0x0000000400007305 */
/* 0x004e24000020f100 */
/*0190*/ IADD3 R0, R0, R9, RZ ; /* 0x0000000900007210 */
/* 0x001fcc0007ffe0ff */
/*01a0*/ I2F R3, R0 ; /* 0x0000000000037306 */
/* 0x000ee40000201400 */
/*01b0*/ FSETP.GT.AND P0, PT, R10, R3, PT ; /* 0x000000030a00720b */
/* 0x008fda0003f04000 */
/*01c0*/ @P0 STG.E [R6.64], R3 ; /* 0x0000000306000986 */
/* 0x000fe8000c101904 */
/*01d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <limits.h>
#include <time.h>
#define NV 5 // number of vertices
void createGraph(float *arr, int N) {
time_t t; // used for randomizing values
int col;
int row;
int maxWeight = 100; // limit the weight an edge can have
srand((unsigned) time(&t)); // generate random
for (col = 0; col < sqrt(N); col++) {
for(row = 0; row < sqrt(N); row++) {
if( col != row){
arr[(int)(row*sqrt(N)) + col] = rand() % maxWeight; // assign random
// have a symmetric graph
arr[(int)(col*sqrt(N)) + row] = arr[(int)(row*sqrt(N)) + col];
}
else
arr[(int)(row*sqrt(N)) + col] = 0; // NO LOOPS
}
}
}
void printGraph(float *arr, int n) {
for (int i = 0; i < n; i++) {
for(int j = 0; j < n; j++) {
printf("%f ", arr[i * n + j]);
}
printf("\n");
}
}
__global__ void gpuFloyd(int n, float* arr, int k) {
int tid = threadIdx.x;
int gid = blockIdx.x * blockDim.x + threadIdx.x;
if(gid >= n) {
return;
}
int idx = n * blockIdx.y + gid;
__shared__ int shortest_distance;
if(tid == 0) {
shortest_distance = arr[n * blockIdx.y + k];
}
__syncthreads();
int node_distance = arr[k * n + gid];
int total_distance = shortest_distance + node_distance;
if (arr[idx] > total_distance){
arr[idx] = total_distance;
}
__syncthreads();
}
void cpuFloyd(int n, float* cpuGraph) {
for (int k = 0; k < n; k++) {
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
if (cpuGraph[i * n + j] > (cpuGraph[i * n + k] + cpuGraph[k * n + j])) {
cpuGraph[i * n + j] = cpuGraph[i * n + k] + cpuGraph[k * n + j];
}
}
}
}
}
void valid(int n, float* cpuGraph, float* gpuGraph) {
printf("VALIDATING that cpuGraph array from CPU and gpuGraph array from GPU match... \n");
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
if (cpuGraph[i * n + j] != gpuGraph[i * n + j]) {
printf("ERROR MISMATCH in array cpuGraph i %d j %d CPU SAYS %f and GPU SAYS %f \n", i, j, cpuGraph[i * n + j], gpuGraph[i * n + j]);
}
}
}
printf("OK \n\n");
}
int main(int argc, char **argv) {
clock_t t;
float *hostArr, *gpuGraph;
float *devArr;
float *graph, *cpuGraph;
int i, j;
int n = NV;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
printf("\n");
printf("RUNNING WITH %d VERTICES \n", n);
printf("\n");
cudaMalloc(&devArr, n * n * sizeof (float));
//CPU arrays
graph = (float *) malloc(n * n * sizeof (float));
cpuGraph = (float *) malloc(n * n * sizeof (float));
//GPU arrays
hostArr = (float *) malloc(n * n * sizeof (float));
gpuGraph = (float *) malloc(n * n * sizeof (float));
// Randomize distances in between each node
createGraph(graph, (n*n));
// Printing graph
//printGraph(graph, n);
for (i = 0; i < n; i++) {
for (j = 0; j < n; j++) {
cpuGraph[i * n + j] = graph[i * n + j];
hostArr[i * n + j] = graph[i * n + j];
}
}
// First Mem Copy
cudaMemcpy(devArr, hostArr, n * n * sizeof (float), cudaMemcpyHostToDevice);
// For GPU Calculation
int gputhreads = 512;
// Kernel call
// dim3 dimGrid(n, n, 1);
dim3 dimGrid((n + gputhreads - 1) / gputhreads, n);
cudaEventRecord(start);
for(int k = 0; k < n; k++) {
gpuFloyd<<<dimGrid, gputhreads>>>(n, devArr, k);
}
cudaEventRecord(stop);
// Second Mem Copy
cudaMemcpy(gpuGraph, devArr, n * n * sizeof (float), cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("GPU Calculation Time elapsed: %.20f milliseconds\n", milliseconds);
// CPU calculation
t = clock();
cpuFloyd(n, cpuGraph);
t = clock() - t;
printf("CPU Calculation Time elapsed: %.20f milliseconds\n\n", (((float)t)/CLOCKS_PER_SEC)*1000);
// Check validation of cpuGraph array from CPU calc and gpuGraph array from GPU calc
// See if the two arrays match
valid(n, cpuGraph, gpuGraph);
/*
printf("Graph from GPU:\n");
printGraph(gpuGraph, n);
printf("\n");
printf("Graph from CPU:\n");
printGraph(cpuGraph, n);
printf("\n");
*/
cudaFree(devArr);
free(graph);
free(cpuGraph);
free(hostArr);
free(gpuGraph);
printf("FINISHED!!! \n");
return 0;
} | .file "tmpxft_0006d97f_00000000-6_FloydWarshall.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11createGraphPfi
.type _Z11createGraphPfi, @function
_Z11createGraphPfi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r13
movl %esi, %ebx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rdi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $0, %ebp
pxor %xmm4, %xmm4
cvtsi2sdl %ebx, %xmm4
movsd %xmm4, 16(%rsp)
movl $0x000000000, %r12d
jmp .L4
.L27:
movsd 16(%rsp), %xmm0
call sqrt@PLT
mulsd 8(%rsp), %xmm0
cvttsd2sil %xmm0, %eax
addl %ebp, %eax
cltq
movl %r14d, 0(%r13,%rax,4)
movsd 16(%rsp), %xmm0
call sqrt@PLT
mulsd 8(%rsp), %xmm0
cvttsd2sil %xmm0, %eax
addl %ebp, %eax
cltq
movl 0(%r13,%rax,4), %r14d
movsd 16(%rsp), %xmm0
call sqrt@PLT
.L8:
mulsd 24(%rsp), %xmm0
cvttsd2sil %xmm0, %eax
addl %ebx, %eax
cltq
movl %r14d, 0(%r13,%rax,4)
.L9:
addl $1, %ebx
.L20:
pxor %xmm4, %xmm4
cvtsi2sdl %ebx, %xmm4
movsd %xmm4, 8(%rsp)
movq %r12, %xmm5
movsd 16(%rsp), %xmm2
ucomisd %xmm2, %xmm5
ja .L29
sqrtsd %xmm2, %xmm2
movapd %xmm2, %xmm0
.L15:
comisd 8(%rsp), %xmm0
jbe .L32
cmpl %ebx, %ebp
je .L5
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm4, %xmm4
cvtsi2ssl %eax, %xmm4
movd %xmm4, %r14d
movq %r12, %xmm5
movsd 16(%rsp), %xmm3
ucomisd %xmm3, %xmm5
ja .L27
sqrtsd %xmm3, %xmm3
movapd %xmm3, %xmm0
movsd 8(%rsp), %xmm1
mulsd %xmm3, %xmm1
cvttsd2sil %xmm1, %eax
addl %ebp, %eax
cltq
movss %xmm4, 0(%r13,%rax,4)
jmp .L8
.L5:
movq %r12, %xmm1
movsd 16(%rsp), %xmm7
ucomisd %xmm7, %xmm1
ja .L28
sqrtsd %xmm7, %xmm7
movapd %xmm7, %xmm0
.L12:
mulsd 8(%rsp), %xmm0
cvttsd2sil %xmm0, %eax
addl %ebp, %eax
cltq
movl $0x00000000, 0(%r13,%rax,4)
jmp .L9
.L28:
movsd 16(%rsp), %xmm0
call sqrt@PLT
jmp .L12
.L29:
movsd 16(%rsp), %xmm0
call sqrt@PLT
jmp .L15
.L32:
addl $1, %ebp
.L4:
pxor %xmm4, %xmm4
cvtsi2sdl %ebp, %xmm4
movsd %xmm4, 24(%rsp)
movq %r12, %xmm5
movsd 16(%rsp), %xmm7
ucomisd %xmm7, %xmm5
ja .L30
sqrtsd %xmm7, %xmm7
movapd %xmm7, %xmm0
.L19:
comisd 24(%rsp), %xmm0
jbe .L33
movl $0, %ebx
jmp .L20
.L30:
movsd 16(%rsp), %xmm0
call sqrt@PLT
jmp .L19
.L33:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z11createGraphPfi, .-_Z11createGraphPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%f "
.LC3:
.string "\n"
.text
.globl _Z10printGraphPfi
.type _Z10printGraphPfi, @function
_Z10printGraphPfi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L35
movslq %esi, %r14
leaq 0(,%r14,4), %r15
leaq (%rdi,%r15), %rbp
negq %r14
salq $2, %r14
movl $0, %r13d
leaq .LC2(%rip), %r12
.L37:
leaq 0(%rbp,%r14), %rbx
.L38:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L38
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addq %r15, %rbp
cmpl %r13d, 12(%rsp)
jne .L37
.L35:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z10printGraphPfi, .-_Z10printGraphPfi
.globl _Z8cpuFloydiPf
.type _Z8cpuFloydiPf, @function
_Z8cpuFloydiPf:
.LFB2059:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L52
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl %edi, %r10d
movq %rsi, %r13
movq %rsi, %rbp
movslq %edi, %r9
leaq 0(,%r9,4), %r8
addq %r8, %r13
movq %r9, %r11
negq %r11
salq $2, %r11
movl $0, %ebx
movl $0, %r12d
movl $0, %r14d
jmp .L43
.L44:
addq $4, %rax
cmpq %rdx, %rax
je .L55
.L46:
movss (%rcx), %xmm0
addss (%rax,%rsi,4), %xmm0
movss (%rax), %xmm1
comiss %xmm0, %xmm1
jbe .L44
movss %xmm0, (%rax)
jmp .L44
.L55:
leal 1(%rdi), %eax
addq %r8, %rdx
addq %r8, %rcx
subq %r9, %rsi
cmpl %eax, %r10d
je .L47
movl %eax, %edi
.L48:
leaq (%rdx,%r11), %rax
jmp .L46
.L47:
leal 1(%r12), %eax
addq $4, %rbp
addq %r9, %rbx
cmpl %edi, %r12d
je .L41
movl %eax, %r12d
.L43:
movq %rbx, %rsi
movq %rbp, %rcx
movq %r13, %rdx
movl %r14d, %edi
jmp .L48
.L41:
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
ret
.cfi_endproc
.LFE2059:
.size _Z8cpuFloydiPf, .-_Z8cpuFloydiPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "VALIDATING that cpuGraph array from CPU and gpuGraph array from GPU match... \n"
.align 8
.LC5:
.string "ERROR MISMATCH in array cpuGraph i %d j %d CPU SAYS %f and GPU SAYS %f \n"
.section .rodata.str1.1
.LC6:
.string "OK \n\n"
.text
.globl _Z5validiPfS_
.type _Z5validiPfS_, @function
_Z5validiPfS_:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %edi, %ebx
movl %edi, 12(%rsp)
movq %rsi, %r12
movq %rdx, %rbp
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jle .L57
movslq %ebx, %r13
leaq 0(,%r13,4), %r15
movl $0, %r14d
jmp .L58
.L62:
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl %ebx, %ecx
movl %r14d, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
.L59:
addq $1, %rbx
cmpq %r13, %rbx
je .L65
.L61:
movss (%r12,%rbx,4), %xmm0
movss 0(%rbp,%rbx,4), %xmm1
ucomiss %xmm1, %xmm0
jp .L62
je .L59
jmp .L62
.L65:
addl $1, %r14d
addq %r15, %r12
addq %r15, %rbp
cmpl %r14d, 12(%rsp)
je .L57
.L58:
movl $0, %ebx
jmp .L61
.L57:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z5validiPfS_, .-_Z5validiPfS_
.globl _Z29__device_stub__Z8gpuFloydiPfiiPfi
.type _Z29__device_stub__Z8gpuFloydiPfiiPfi, @function
_Z29__device_stub__Z8gpuFloydiPfiiPfi:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L70
.L66:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L71
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L70:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8gpuFloydiPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L66
.L71:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z29__device_stub__Z8gpuFloydiPfiiPfi, .-_Z29__device_stub__Z8gpuFloydiPfiiPfi
.globl _Z8gpuFloydiPfi
.type _Z8gpuFloydiPfi, @function
_Z8gpuFloydiPfi:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z8gpuFloydiPfiiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z8gpuFloydiPfi, .-_Z8gpuFloydiPfi
.section .rodata.str1.1
.LC7:
.string "RUNNING WITH %d VERTICES \n"
.section .rodata.str1.8
.align 8
.LC8:
.string "GPU Calculation Time elapsed: %.20f milliseconds\n"
.align 8
.LC11:
.string "CPU Calculation Time elapsed: %.20f milliseconds\n\n"
.section .rodata.str1.1
.LC12:
.string "FINISHED!!! \n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq .LC3(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $5, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $100, %esi
call cudaMalloc@PLT
movl $100, %edi
call malloc@PLT
movq %rax, %r12
movl $100, %edi
call malloc@PLT
movq %rax, %rbx
movl $100, %edi
call malloc@PLT
movq %rax, %rbp
movl $100, %edi
call malloc@PLT
movq %rax, %r13
movl $25, %esi
movq %r12, %rdi
call _Z11createGraphPfi
movl $20, %edx
.L75:
leaq -20(%rdx), %rax
.L76:
movss (%r12,%rax), %xmm0
movss %xmm0, (%rbx,%rax)
movss %xmm0, 0(%rbp,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L76
addq $20, %rdx
cmpq $120, %rdx
jne .L75
movl $1, %ecx
movl $100, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 32(%rsp)
movl $5, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %r14d
jmp .L79
.L85:
movl %r14d, %edx
movq 8(%rsp), %rsi
movl $5, %edi
call _Z29__device_stub__Z8gpuFloydiPfiiPfi
.L78:
addl $1, %r14d
cmpl $5, %r14d
je .L84
.L79:
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L78
jmp .L85
.L84:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $100, %edx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 44(%rsp)
leaq 44(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call clock@PLT
movq %rax, %r14
movq %rbx, %rsi
movl $5, %edi
call _Z8cpuFloydiPf
call clock@PLT
subq %r14, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC9(%rip), %xmm0
mulss .LC10(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r13, %rdx
movq %rbx, %rsi
movl $5, %edi
call _Z5validiPfS_
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L86
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L86:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z8gpuFloydiPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z8gpuFloydiPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC9:
.long 1232348160
.align 4
.LC10:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <limits.h>
#include <time.h>
#define NV 5 // number of vertices
void createGraph(float *arr, int N) {
time_t t; // used for randomizing values
int col;
int row;
int maxWeight = 100; // limit the weight an edge can have
srand((unsigned) time(&t)); // generate random
for (col = 0; col < sqrt(N); col++) {
for(row = 0; row < sqrt(N); row++) {
if( col != row){
arr[(int)(row*sqrt(N)) + col] = rand() % maxWeight; // assign random
// have a symmetric graph
arr[(int)(col*sqrt(N)) + row] = arr[(int)(row*sqrt(N)) + col];
}
else
arr[(int)(row*sqrt(N)) + col] = 0; // NO LOOPS
}
}
}
void printGraph(float *arr, int n) {
for (int i = 0; i < n; i++) {
for(int j = 0; j < n; j++) {
printf("%f ", arr[i * n + j]);
}
printf("\n");
}
}
__global__ void gpuFloyd(int n, float* arr, int k) {
int tid = threadIdx.x;
int gid = blockIdx.x * blockDim.x + threadIdx.x;
if(gid >= n) {
return;
}
int idx = n * blockIdx.y + gid;
__shared__ int shortest_distance;
if(tid == 0) {
shortest_distance = arr[n * blockIdx.y + k];
}
__syncthreads();
int node_distance = arr[k * n + gid];
int total_distance = shortest_distance + node_distance;
if (arr[idx] > total_distance){
arr[idx] = total_distance;
}
__syncthreads();
}
void cpuFloyd(int n, float* cpuGraph) {
for (int k = 0; k < n; k++) {
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
if (cpuGraph[i * n + j] > (cpuGraph[i * n + k] + cpuGraph[k * n + j])) {
cpuGraph[i * n + j] = cpuGraph[i * n + k] + cpuGraph[k * n + j];
}
}
}
}
}
void valid(int n, float* cpuGraph, float* gpuGraph) {
printf("VALIDATING that cpuGraph array from CPU and gpuGraph array from GPU match... \n");
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
if (cpuGraph[i * n + j] != gpuGraph[i * n + j]) {
printf("ERROR MISMATCH in array cpuGraph i %d j %d CPU SAYS %f and GPU SAYS %f \n", i, j, cpuGraph[i * n + j], gpuGraph[i * n + j]);
}
}
}
printf("OK \n\n");
}
int main(int argc, char **argv) {
clock_t t;
float *hostArr, *gpuGraph;
float *devArr;
float *graph, *cpuGraph;
int i, j;
int n = NV;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
printf("\n");
printf("RUNNING WITH %d VERTICES \n", n);
printf("\n");
cudaMalloc(&devArr, n * n * sizeof (float));
//CPU arrays
graph = (float *) malloc(n * n * sizeof (float));
cpuGraph = (float *) malloc(n * n * sizeof (float));
//GPU arrays
hostArr = (float *) malloc(n * n * sizeof (float));
gpuGraph = (float *) malloc(n * n * sizeof (float));
// Randomize distances in between each node
createGraph(graph, (n*n));
// Printing graph
//printGraph(graph, n);
for (i = 0; i < n; i++) {
for (j = 0; j < n; j++) {
cpuGraph[i * n + j] = graph[i * n + j];
hostArr[i * n + j] = graph[i * n + j];
}
}
// First Mem Copy
cudaMemcpy(devArr, hostArr, n * n * sizeof (float), cudaMemcpyHostToDevice);
// For GPU Calculation
int gputhreads = 512;
// Kernel call
// dim3 dimGrid(n, n, 1);
dim3 dimGrid((n + gputhreads - 1) / gputhreads, n);
cudaEventRecord(start);
for(int k = 0; k < n; k++) {
gpuFloyd<<<dimGrid, gputhreads>>>(n, devArr, k);
}
cudaEventRecord(stop);
// Second Mem Copy
cudaMemcpy(gpuGraph, devArr, n * n * sizeof (float), cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("GPU Calculation Time elapsed: %.20f milliseconds\n", milliseconds);
// CPU calculation
t = clock();
cpuFloyd(n, cpuGraph);
t = clock() - t;
printf("CPU Calculation Time elapsed: %.20f milliseconds\n\n", (((float)t)/CLOCKS_PER_SEC)*1000);
// Check validation of cpuGraph array from CPU calc and gpuGraph array from GPU calc
// See if the two arrays match
valid(n, cpuGraph, gpuGraph);
/*
printf("Graph from GPU:\n");
printGraph(gpuGraph, n);
printf("\n");
printf("Graph from CPU:\n");
printGraph(cpuGraph, n);
printf("\n");
*/
cudaFree(devArr);
free(graph);
free(cpuGraph);
free(hostArr);
free(gpuGraph);
printf("FINISHED!!! \n");
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <limits.h>
#include <time.h>
#define NV 5 // number of vertices
void createGraph(float *arr, int N) {
time_t t; // used for randomizing values
int col;
int row;
int maxWeight = 100; // limit the weight an edge can have
srand((unsigned) time(&t)); // generate random
for (col = 0; col < sqrt(N); col++) {
for(row = 0; row < sqrt(N); row++) {
if( col != row){
arr[(int)(row*sqrt(N)) + col] = rand() % maxWeight; // assign random
// have a symmetric graph
arr[(int)(col*sqrt(N)) + row] = arr[(int)(row*sqrt(N)) + col];
}
else
arr[(int)(row*sqrt(N)) + col] = 0; // NO LOOPS
}
}
}
void printGraph(float *arr, int n) {
for (int i = 0; i < n; i++) {
for(int j = 0; j < n; j++) {
printf("%f ", arr[i * n + j]);
}
printf("\n");
}
}
__global__ void gpuFloyd(int n, float* arr, int k) {
int tid = threadIdx.x;
int gid = blockIdx.x * blockDim.x + threadIdx.x;
if(gid >= n) {
return;
}
int idx = n * blockIdx.y + gid;
__shared__ int shortest_distance;
if(tid == 0) {
shortest_distance = arr[n * blockIdx.y + k];
}
__syncthreads();
int node_distance = arr[k * n + gid];
int total_distance = shortest_distance + node_distance;
if (arr[idx] > total_distance){
arr[idx] = total_distance;
}
__syncthreads();
}
void cpuFloyd(int n, float* cpuGraph) {
for (int k = 0; k < n; k++) {
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
if (cpuGraph[i * n + j] > (cpuGraph[i * n + k] + cpuGraph[k * n + j])) {
cpuGraph[i * n + j] = cpuGraph[i * n + k] + cpuGraph[k * n + j];
}
}
}
}
}
void valid(int n, float* cpuGraph, float* gpuGraph) {
printf("VALIDATING that cpuGraph array from CPU and gpuGraph array from GPU match... \n");
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
if (cpuGraph[i * n + j] != gpuGraph[i * n + j]) {
printf("ERROR MISMATCH in array cpuGraph i %d j %d CPU SAYS %f and GPU SAYS %f \n", i, j, cpuGraph[i * n + j], gpuGraph[i * n + j]);
}
}
}
printf("OK \n\n");
}
int main(int argc, char **argv) {
clock_t t;
float *hostArr, *gpuGraph;
float *devArr;
float *graph, *cpuGraph;
int i, j;
int n = NV;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
printf("\n");
printf("RUNNING WITH %d VERTICES \n", n);
printf("\n");
hipMalloc(&devArr, n * n * sizeof (float));
//CPU arrays
graph = (float *) malloc(n * n * sizeof (float));
cpuGraph = (float *) malloc(n * n * sizeof (float));
//GPU arrays
hostArr = (float *) malloc(n * n * sizeof (float));
gpuGraph = (float *) malloc(n * n * sizeof (float));
// Randomize distances in between each node
createGraph(graph, (n*n));
// Printing graph
//printGraph(graph, n);
for (i = 0; i < n; i++) {
for (j = 0; j < n; j++) {
cpuGraph[i * n + j] = graph[i * n + j];
hostArr[i * n + j] = graph[i * n + j];
}
}
// First Mem Copy
hipMemcpy(devArr, hostArr, n * n * sizeof (float), hipMemcpyHostToDevice);
// For GPU Calculation
int gputhreads = 512;
// Kernel call
// dim3 dimGrid(n, n, 1);
dim3 dimGrid((n + gputhreads - 1) / gputhreads, n);
hipEventRecord(start);
for(int k = 0; k < n; k++) {
gpuFloyd<<<dimGrid, gputhreads>>>(n, devArr, k);
}
hipEventRecord(stop);
// Second Mem Copy
hipMemcpy(gpuGraph, devArr, n * n * sizeof (float), hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("GPU Calculation Time elapsed: %.20f milliseconds\n", milliseconds);
// CPU calculation
t = clock();
cpuFloyd(n, cpuGraph);
t = clock() - t;
printf("CPU Calculation Time elapsed: %.20f milliseconds\n\n", (((float)t)/CLOCKS_PER_SEC)*1000);
// Check validation of cpuGraph array from CPU calc and gpuGraph array from GPU calc
// See if the two arrays match
valid(n, cpuGraph, gpuGraph);
/*
printf("Graph from GPU:\n");
printGraph(gpuGraph, n);
printf("\n");
printf("Graph from CPU:\n");
printGraph(cpuGraph, n);
printf("\n");
*/
hipFree(devArr);
free(graph);
free(cpuGraph);
free(hostArr);
free(gpuGraph);
printf("FINISHED!!! \n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <limits.h>
#include <time.h>
#define NV 5 // number of vertices
void createGraph(float *arr, int N) {
time_t t; // used for randomizing values
int col;
int row;
int maxWeight = 100; // limit the weight an edge can have
srand((unsigned) time(&t)); // generate random
for (col = 0; col < sqrt(N); col++) {
for(row = 0; row < sqrt(N); row++) {
if( col != row){
arr[(int)(row*sqrt(N)) + col] = rand() % maxWeight; // assign random
// have a symmetric graph
arr[(int)(col*sqrt(N)) + row] = arr[(int)(row*sqrt(N)) + col];
}
else
arr[(int)(row*sqrt(N)) + col] = 0; // NO LOOPS
}
}
}
void printGraph(float *arr, int n) {
for (int i = 0; i < n; i++) {
for(int j = 0; j < n; j++) {
printf("%f ", arr[i * n + j]);
}
printf("\n");
}
}
__global__ void gpuFloyd(int n, float* arr, int k) {
int tid = threadIdx.x;
int gid = blockIdx.x * blockDim.x + threadIdx.x;
if(gid >= n) {
return;
}
int idx = n * blockIdx.y + gid;
__shared__ int shortest_distance;
if(tid == 0) {
shortest_distance = arr[n * blockIdx.y + k];
}
__syncthreads();
int node_distance = arr[k * n + gid];
int total_distance = shortest_distance + node_distance;
if (arr[idx] > total_distance){
arr[idx] = total_distance;
}
__syncthreads();
}
void cpuFloyd(int n, float* cpuGraph) {
for (int k = 0; k < n; k++) {
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
if (cpuGraph[i * n + j] > (cpuGraph[i * n + k] + cpuGraph[k * n + j])) {
cpuGraph[i * n + j] = cpuGraph[i * n + k] + cpuGraph[k * n + j];
}
}
}
}
}
void valid(int n, float* cpuGraph, float* gpuGraph) {
printf("VALIDATING that cpuGraph array from CPU and gpuGraph array from GPU match... \n");
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
if (cpuGraph[i * n + j] != gpuGraph[i * n + j]) {
printf("ERROR MISMATCH in array cpuGraph i %d j %d CPU SAYS %f and GPU SAYS %f \n", i, j, cpuGraph[i * n + j], gpuGraph[i * n + j]);
}
}
}
printf("OK \n\n");
}
int main(int argc, char **argv) {
clock_t t;
float *hostArr, *gpuGraph;
float *devArr;
float *graph, *cpuGraph;
int i, j;
int n = NV;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
printf("\n");
printf("RUNNING WITH %d VERTICES \n", n);
printf("\n");
hipMalloc(&devArr, n * n * sizeof (float));
//CPU arrays
graph = (float *) malloc(n * n * sizeof (float));
cpuGraph = (float *) malloc(n * n * sizeof (float));
//GPU arrays
hostArr = (float *) malloc(n * n * sizeof (float));
gpuGraph = (float *) malloc(n * n * sizeof (float));
// Randomize distances in between each node
createGraph(graph, (n*n));
// Printing graph
//printGraph(graph, n);
for (i = 0; i < n; i++) {
for (j = 0; j < n; j++) {
cpuGraph[i * n + j] = graph[i * n + j];
hostArr[i * n + j] = graph[i * n + j];
}
}
// First Mem Copy
hipMemcpy(devArr, hostArr, n * n * sizeof (float), hipMemcpyHostToDevice);
// For GPU Calculation
int gputhreads = 512;
// Kernel call
// dim3 dimGrid(n, n, 1);
dim3 dimGrid((n + gputhreads - 1) / gputhreads, n);
hipEventRecord(start);
for(int k = 0; k < n; k++) {
gpuFloyd<<<dimGrid, gputhreads>>>(n, devArr, k);
}
hipEventRecord(stop);
// Second Mem Copy
hipMemcpy(gpuGraph, devArr, n * n * sizeof (float), hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("GPU Calculation Time elapsed: %.20f milliseconds\n", milliseconds);
// CPU calculation
t = clock();
cpuFloyd(n, cpuGraph);
t = clock() - t;
printf("CPU Calculation Time elapsed: %.20f milliseconds\n\n", (((float)t)/CLOCKS_PER_SEC)*1000);
// Check validation of cpuGraph array from CPU calc and gpuGraph array from GPU calc
// See if the two arrays match
valid(n, cpuGraph, gpuGraph);
/*
printf("Graph from GPU:\n");
printGraph(gpuGraph, n);
printf("\n");
printf("Graph from CPU:\n");
printGraph(cpuGraph, n);
printf("\n");
*/
hipFree(devArr);
free(graph);
free(cpuGraph);
free(hostArr);
free(gpuGraph);
printf("FINISHED!!! \n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8gpuFloydiPfi
.globl _Z8gpuFloydiPfi
.p2align 8
.type _Z8gpuFloydiPfi,@function
_Z8gpuFloydiPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s6, s[0:1], 0x10
s_mul_i32 s5, s15, s4
s_mov_b32 s1, 0
s_mov_b32 s7, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_3
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s5, s6
v_mov_b32_e32 v2, 0
s_lshl_b64 s[0:1], s[0:1], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
s_load_b32 s0, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_cvt_i32_f32_e32 v0, s0
ds_store_b32 v2, v0
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s7
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, s6, s4, v[1:2]
v_add_nc_u32_e32 v0, s5, v1
s_barrier
buffer_gl0_inv
v_mov_b32_e32 v4, 0
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v3, 31, v2
ds_load_b32 v4, v4
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_clause 0x1
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(1)
v_cvt_i32_f32_e32 v2, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v4, v2
v_cvt_f32_i32_e32 v2, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_f32_e32 vcc_lo, v3, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
global_store_b32 v[0:1], v2, off
.LBB0_5:
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB0_6:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8gpuFloydiPfi
.amdhsa_group_segment_fixed_size 4
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8gpuFloydiPfi, .Lfunc_end0-_Z8gpuFloydiPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8gpuFloydiPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8gpuFloydiPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <limits.h>
#include <time.h>
#define NV 5 // number of vertices
void createGraph(float *arr, int N) {
time_t t; // used for randomizing values
int col;
int row;
int maxWeight = 100; // limit the weight an edge can have
srand((unsigned) time(&t)); // generate random
for (col = 0; col < sqrt(N); col++) {
for(row = 0; row < sqrt(N); row++) {
if( col != row){
arr[(int)(row*sqrt(N)) + col] = rand() % maxWeight; // assign random
// have a symmetric graph
arr[(int)(col*sqrt(N)) + row] = arr[(int)(row*sqrt(N)) + col];
}
else
arr[(int)(row*sqrt(N)) + col] = 0; // NO LOOPS
}
}
}
void printGraph(float *arr, int n) {
for (int i = 0; i < n; i++) {
for(int j = 0; j < n; j++) {
printf("%f ", arr[i * n + j]);
}
printf("\n");
}
}
__global__ void gpuFloyd(int n, float* arr, int k) {
int tid = threadIdx.x;
int gid = blockIdx.x * blockDim.x + threadIdx.x;
if(gid >= n) {
return;
}
int idx = n * blockIdx.y + gid;
__shared__ int shortest_distance;
if(tid == 0) {
shortest_distance = arr[n * blockIdx.y + k];
}
__syncthreads();
int node_distance = arr[k * n + gid];
int total_distance = shortest_distance + node_distance;
if (arr[idx] > total_distance){
arr[idx] = total_distance;
}
__syncthreads();
}
void cpuFloyd(int n, float* cpuGraph) {
for (int k = 0; k < n; k++) {
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
if (cpuGraph[i * n + j] > (cpuGraph[i * n + k] + cpuGraph[k * n + j])) {
cpuGraph[i * n + j] = cpuGraph[i * n + k] + cpuGraph[k * n + j];
}
}
}
}
}
void valid(int n, float* cpuGraph, float* gpuGraph) {
printf("VALIDATING that cpuGraph array from CPU and gpuGraph array from GPU match... \n");
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
if (cpuGraph[i * n + j] != gpuGraph[i * n + j]) {
printf("ERROR MISMATCH in array cpuGraph i %d j %d CPU SAYS %f and GPU SAYS %f \n", i, j, cpuGraph[i * n + j], gpuGraph[i * n + j]);
}
}
}
printf("OK \n\n");
}
int main(int argc, char **argv) {
clock_t t;
float *hostArr, *gpuGraph;
float *devArr;
float *graph, *cpuGraph;
int i, j;
int n = NV;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
printf("\n");
printf("RUNNING WITH %d VERTICES \n", n);
printf("\n");
hipMalloc(&devArr, n * n * sizeof (float));
//CPU arrays
graph = (float *) malloc(n * n * sizeof (float));
cpuGraph = (float *) malloc(n * n * sizeof (float));
//GPU arrays
hostArr = (float *) malloc(n * n * sizeof (float));
gpuGraph = (float *) malloc(n * n * sizeof (float));
// Randomize distances in between each node
createGraph(graph, (n*n));
// Printing graph
//printGraph(graph, n);
for (i = 0; i < n; i++) {
for (j = 0; j < n; j++) {
cpuGraph[i * n + j] = graph[i * n + j];
hostArr[i * n + j] = graph[i * n + j];
}
}
// First Mem Copy
hipMemcpy(devArr, hostArr, n * n * sizeof (float), hipMemcpyHostToDevice);
// For GPU Calculation
int gputhreads = 512;
// Kernel call
// dim3 dimGrid(n, n, 1);
dim3 dimGrid((n + gputhreads - 1) / gputhreads, n);
hipEventRecord(start);
for(int k = 0; k < n; k++) {
gpuFloyd<<<dimGrid, gputhreads>>>(n, devArr, k);
}
hipEventRecord(stop);
// Second Mem Copy
hipMemcpy(gpuGraph, devArr, n * n * sizeof (float), hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("GPU Calculation Time elapsed: %.20f milliseconds\n", milliseconds);
// CPU calculation
t = clock();
cpuFloyd(n, cpuGraph);
t = clock() - t;
printf("CPU Calculation Time elapsed: %.20f milliseconds\n\n", (((float)t)/CLOCKS_PER_SEC)*1000);
// Check validation of cpuGraph array from CPU calc and gpuGraph array from GPU calc
// See if the two arrays match
valid(n, cpuGraph, gpuGraph);
/*
printf("Graph from GPU:\n");
printGraph(gpuGraph, n);
printf("\n");
printf("Graph from CPU:\n");
printGraph(cpuGraph, n);
printf("\n");
*/
hipFree(devArr);
free(graph);
free(cpuGraph);
free(hostArr);
free(gpuGraph);
printf("FINISHED!!! \n");
return 0;
} | .text
.file "FloydWarshall.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z11createGraphPfi
.LCPI0_0:
.quad 0x0000000000000000 # double 0
.text
.globl _Z11createGraphPfi
.p2align 4, 0x90
.type _Z11createGraphPfi,@function
_Z11createGraphPfi: # @_Z11createGraphPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $56, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
leaq 48(%rsp), %rdi
callq time
movl %eax, %edi
callq srand
cvtsi2sd %ebp, %xmm2
xorpd %xmm1, %xmm1
ucomisd %xmm1, %xmm2
movsd %xmm2, 8(%rsp) # 8-byte Spill
jb .LBB0_2
# %bb.1:
sqrtsd %xmm2, %xmm0
ucomisd %xmm1, %xmm0
ja .LBB0_4
jmp .LBB0_24
.LBB0_2: # %call.sqrt
movapd %xmm2, %xmm0
callq sqrt
xorpd %xmm1, %xmm1
movsd 8(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
ucomisd %xmm1, %xmm0
jbe .LBB0_24
.LBB0_4: # %.preheader.preheader
xorl %r14d, %r14d
xorps %xmm0, %xmm0
sqrtsd %xmm2, %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
xorpd %xmm0, %xmm0
movsd %xmm0, 40(%rsp) # 8-byte Spill
jmp .LBB0_5
.p2align 4, 0x90
.LBB0_23: # %._crit_edge.split
# in Loop: Header=BB0_5 Depth=1
incl %r14d
xorps %xmm1, %xmm1
cvtsi2sd %r14d, %xmm1
movsd %xmm1, 40(%rsp) # 8-byte Spill
ucomisd %xmm1, %xmm0
jbe .LBB0_24
.LBB0_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_9 Depth 2
ucomisd .LCPI0_0(%rip), %xmm2
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
jae .LBB0_7
# %bb.6: # %call.sqrt37
# in Loop: Header=BB0_5 Depth=1
movapd %xmm2, %xmm0
callq sqrt
movsd 8(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
.LBB0_7: # %.preheader.split
# in Loop: Header=BB0_5 Depth=1
ucomisd .LCPI0_0(%rip), %xmm0
jbe .LBB0_21
# %bb.8: # %.lr.ph.preheader
# in Loop: Header=BB0_5 Depth=1
xorl %r15d, %r15d
xorpd %xmm1, %xmm1
jmp .LBB0_9
.p2align 4, 0x90
.LBB0_20: # %.split41.split
# in Loop: Header=BB0_9 Depth=2
incl %r15d
xorps %xmm1, %xmm1
cvtsi2sd %r15d, %xmm1
ucomisd %xmm1, %xmm0
jbe .LBB0_21
.LBB0_9: # %.lr.ph
# Parent Loop BB0_5 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm3, %xmm3
cmpl %r15d, %r14d
jne .LBB0_11
# %bb.10: # in Loop: Header=BB0_9 Depth=2
movl %r14d, %ebp
jmp .LBB0_16
.p2align 4, 0x90
.LBB0_11: # in Loop: Header=BB0_9 Depth=2
movsd %xmm1, 24(%rsp) # 8-byte Spill
callq rand
movsd 8(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
movl %eax, %ebp
ucomisd .LCPI0_0(%rip), %xmm2
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
jae .LBB0_13
# %bb.12: # %call.sqrt39
# in Loop: Header=BB0_9 Depth=2
movapd %xmm2, %xmm0
callq sqrt
movsd 8(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
.LBB0_13: # %.split38
# in Loop: Header=BB0_9 Depth=2
movslq %ebp, %rax
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
movsd 24(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
mulsd %xmm3, %xmm0
cvttsd2si %xmm0, %eax
addl %r14d, %eax
cltq
movss %xmm1, (%rbx,%rax,4)
ucomisd .LCPI0_0(%rip), %xmm2
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
jae .LBB0_15
# %bb.14: # %call.sqrt40
# in Loop: Header=BB0_9 Depth=2
movapd %xmm2, %xmm0
callq sqrt
movsd 24(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
movsd 8(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
.LBB0_15: # %.split38.split
# in Loop: Header=BB0_9 Depth=2
mulsd %xmm0, %xmm3
cvttsd2si %xmm3, %eax
addl %r14d, %eax
cltq
movss (%rbx,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
movsd 40(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
movl %r15d, %ebp
.LBB0_16: # in Loop: Header=BB0_9 Depth=2
ucomisd .LCPI0_0(%rip), %xmm2
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
jae .LBB0_18
# %bb.17: # %call.sqrt42
# in Loop: Header=BB0_9 Depth=2
movapd %xmm2, %xmm0
movsd %xmm1, 24(%rsp) # 8-byte Spill
movss %xmm3, 36(%rsp) # 4-byte Spill
callq sqrt
movss 36(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movsd 24(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
movsd 8(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
.LBB0_18: # %.split41
# in Loop: Header=BB0_9 Depth=2
mulsd %xmm0, %xmm1
cvttsd2si %xmm1, %eax
addl %eax, %ebp
movslq %ebp, %rax
movss %xmm3, (%rbx,%rax,4)
ucomisd .LCPI0_0(%rip), %xmm2
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
jae .LBB0_20
# %bb.19: # %call.sqrt43
# in Loop: Header=BB0_9 Depth=2
movapd %xmm2, %xmm0
callq sqrt
movsd 8(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
jmp .LBB0_20
.p2align 4, 0x90
.LBB0_21: # %._crit_edge
# in Loop: Header=BB0_5 Depth=1
ucomisd .LCPI0_0(%rip), %xmm2
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
jae .LBB0_23
# %bb.22: # %call.sqrt44
# in Loop: Header=BB0_5 Depth=1
movapd %xmm2, %xmm0
callq sqrt
movsd 8(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
jmp .LBB0_23
.LBB0_24: # %._crit_edge29
addq $56, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z11createGraphPfi, .Lfunc_end0-_Z11createGraphPfi
.cfi_endproc
# -- End function
.globl _Z10printGraphPfi # -- Begin function _Z10printGraphPfi
.p2align 4, 0x90
.type _Z10printGraphPfi,@function
_Z10printGraphPfi: # @_Z10printGraphPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, (%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB1_5
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebx
movl %esi, %r15d
xorl %r12d, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movl %r12d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbp,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %r15
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addl %ebx, %r12d
cmpq %r15, %r13
jne .LBB1_2
.LBB1_5: # %._crit_edge13
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z10printGraphPfi, .Lfunc_end1-_Z10printGraphPfi
.cfi_endproc
# -- End function
.globl _Z23__device_stub__gpuFloydiPfi # -- Begin function _Z23__device_stub__gpuFloydiPfi
.p2align 4, 0x90
.type _Z23__device_stub__gpuFloydiPfi,@function
_Z23__device_stub__gpuFloydiPfi: # @_Z23__device_stub__gpuFloydiPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
movl %edx, (%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8gpuFloydiPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z23__device_stub__gpuFloydiPfi, .Lfunc_end2-_Z23__device_stub__gpuFloydiPfi
.cfi_endproc
# -- End function
.globl _Z8cpuFloydiPf # -- Begin function _Z8cpuFloydiPf
.p2align 4, 0x90
.type _Z8cpuFloydiPf,@function
_Z8cpuFloydiPf: # @_Z8cpuFloydiPf
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB3_10
# %bb.1: # %.preheader36.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %edi, %eax
xorl %ecx, %ecx
xorl %edx, %edx
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_8: # %._crit_edge39
# in Loop: Header=BB3_2 Depth=1
incq %rdx
addl %edi, %ecx
cmpq %rax, %rdx
je .LBB3_9
.LBB3_2: # %.preheader36
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
# Child Loop BB3_4 Depth 3
movl %ecx, %r8d
leaq (%rsi,%r8,4), %r8
leaq (%rsi,%rdx,4), %r9
xorl %r10d, %r10d
xorl %r11d, %r11d
jmp .LBB3_3
.p2align 4, 0x90
.LBB3_7: # %._crit_edge
# in Loop: Header=BB3_3 Depth=2
incq %r11
addl %edi, %r10d
cmpq %rax, %r11
je .LBB3_8
.LBB3_3: # %.preheader
# Parent Loop BB3_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_4 Depth 3
movl %r10d, %ebx
leaq (%rsi,%rbx,4), %rbx
movq %r11, %r14
imulq %rax, %r14
xorl %r15d, %r15d
jmp .LBB3_4
.p2align 4, 0x90
.LBB3_6: # in Loop: Header=BB3_4 Depth=3
incq %r15
cmpq %r15, %rax
je .LBB3_7
.LBB3_4: # Parent Loop BB3_2 Depth=1
# Parent Loop BB3_3 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rbx,%r15,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss (%r9,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%r8,%r15,4), %xmm0
ucomiss %xmm0, %xmm1
jbe .LBB3_6
# %bb.5: # in Loop: Header=BB3_4 Depth=3
movss %xmm0, (%rbx,%r15,4)
jmp .LBB3_6
.LBB3_9:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB3_10: # %._crit_edge41
retq
.Lfunc_end3:
.size _Z8cpuFloydiPf, .Lfunc_end3-_Z8cpuFloydiPf
.cfi_endproc
# -- End function
.globl _Z5validiPfS_ # -- Begin function _Z5validiPfS_
.p2align 4, 0x90
.type _Z5validiPfS_,@function
_Z5validiPfS_: # @_Z5validiPfS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, 16(%rsp) # 8-byte Spill
movq %rsi, 8(%rsp) # 8-byte Spill
movl %edi, %ebx
movl $.Lstr, %edi
callq puts@PLT
movl %ebx, 4(%rsp) # 4-byte Spill
testl %ebx, %ebx
jle .LBB4_7
# %bb.1: # %.preheader.lr.ph
movl 4(%rsp), %r13d # 4-byte Reload
xorl %ebx, %ebx
xorl %r15d, %r15d
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_6: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
incq %r15
addl 4(%rsp), %ebx # 4-byte Folded Reload
cmpq %r13, %r15
je .LBB4_7
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_3 Depth 2
movl %ebx, %eax
movq 16(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %r12d, %r12d
jmp .LBB4_3
.p2align 4, 0x90
.LBB4_5: # in Loop: Header=BB4_3 Depth=2
incq %r12
cmpq %r12, %r13
je .LBB4_6
.LBB4_3: # Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbp,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%r14,%r12,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jne .LBB4_4
jnp .LBB4_5
.LBB4_4: # in Loop: Header=BB4_3 Depth=2
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.3, %edi
movl %r15d, %esi
movl %r12d, %edx
movb $2, %al
callq printf
jmp .LBB4_5
.LBB4_7: # %._crit_edge30
movl $.Lstr.1, %edi
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end4:
.size _Z5validiPfS_, .Lfunc_end4-_Z5validiPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI5_0:
.long 0x49742400 # float 1.0E+6
.LCPI5_1:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movl $10, %edi
callq putchar@PLT
xorl %ebx, %ebx
movl $.L.str.5, %edi
movl $5, %esi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
movq %rsp, %rdi
movl $100, %esi
callq hipMalloc
movl $100, %edi
callq malloc
movq %rax, %r15
movl $100, %edi
callq malloc
movq %rax, %r14
movl $100, %edi
callq malloc
movq %rax, %r12
movl $100, %edi
callq malloc
movq %rax, 56(%rsp) # 8-byte Spill
movq %r15, %rdi
movl $25, %esi
callq _Z11createGraphPfi
movl 96(%r15), %eax
movl %eax, 96(%r14)
movups 80(%r15), %xmm0
movups %xmm0, 80(%r14)
movups 64(%r15), %xmm0
movups %xmm0, 64(%r14)
movups (%r15), %xmm0
movups 16(%r15), %xmm1
movups 32(%r15), %xmm2
movups 48(%r15), %xmm3
movups %xmm3, 48(%r14)
movups %xmm2, 32(%r14)
movups %xmm1, 16(%r14)
movups %xmm0, (%r14)
movl 96(%r15), %eax
movl %eax, 96(%r12)
movups 80(%r15), %xmm0
movups %xmm0, 80(%r12)
movups 64(%r15), %xmm0
movups %xmm0, 64(%r12)
movups (%r15), %xmm0
movups 16(%r15), %xmm1
movups 32(%r15), %xmm2
movq %r15, 72(%rsp) # 8-byte Spill
movups 48(%r15), %xmm3
movups %xmm3, 48(%r12)
movups %xmm2, 32(%r12)
movups %xmm1, 16(%r12)
movups %xmm0, (%r12)
movq (%rsp), %rdi
movl $100, %edx
movq %r12, 64(%rsp) # 8-byte Spill
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $21474836481, %r13 # imm = 0x500000001
movabsq $4294967808, %rbp # imm = 0x100000200
leaq 80(%rsp), %r12
leaq 32(%rsp), %r15
jmp .LBB5_1
.p2align 4, 0x90
.LBB5_3: # in Loop: Header=BB5_1 Depth=1
incl %ebx
cmpl $5, %ebx
je .LBB5_4
.LBB5_1: # =>This Inner Loop Header: Depth=1
movq %r13, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_3
# %bb.2: # in Loop: Header=BB5_1 Depth=1
movq (%rsp), %rax
movl $5, 20(%rsp)
movq %rax, 128(%rsp)
movl %ebx, 16(%rsp)
leaq 20(%rsp), %rax
movq %rax, 32(%rsp)
leaq 128(%rsp), %rax
movq %rax, 40(%rsp)
leaq 16(%rsp), %rax
movq %rax, 48(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
movl $_Z8gpuFloydiPfi, %edi
movq %r15, %r9
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB5_3
.LBB5_4:
movq 8(%rsp), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rsi
movl $100, %edx
movq 56(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipEventSynchronize
movl $0, 32(%rsp)
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
callq clock
movq %rax, %r15
movq %r14, %rax
jmp .LBB5_5
.p2align 4, 0x90
.LBB5_11: # %._crit_edge39.i
# in Loop: Header=BB5_5 Depth=1
incq %rbx
addq $20, %rax
cmpq $5, %rbx
je .LBB5_12
.LBB5_5: # %.preheader36.i
# =>This Loop Header: Depth=1
# Child Loop BB5_6 Depth 2
# Child Loop BB5_7 Depth 3
leaq (%r14,%rbx,4), %rcx
movq %r14, %rdx
xorl %esi, %esi
jmp .LBB5_6
.p2align 4, 0x90
.LBB5_10: # %._crit_edge.i
# in Loop: Header=BB5_6 Depth=2
incq %rsi
addq $20, %rdx
cmpq $5, %rsi
je .LBB5_11
.LBB5_6: # %.preheader.i
# Parent Loop BB5_5 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB5_7 Depth 3
leaq (%rsi,%rsi,4), %rdi
xorl %r8d, %r8d
jmp .LBB5_7
.p2align 4, 0x90
.LBB5_9: # in Loop: Header=BB5_7 Depth=3
incq %r8
cmpq $5, %r8
je .LBB5_10
.LBB5_7: # Parent Loop BB5_5 Depth=1
# Parent Loop BB5_6 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rdx,%r8,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss (%rcx,%rdi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rax,%r8,4), %xmm0
ucomiss %xmm0, %xmm1
jbe .LBB5_9
# %bb.8: # in Loop: Header=BB5_7 Depth=3
movss %xmm0, (%rdx,%r8,4)
jmp .LBB5_9
.LBB5_12: # %_Z8cpuFloydiPf.exit
callq clock
subq %r15, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
divss .LCPI5_0(%rip), %xmm0
mulss .LCPI5_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
movq %r14, %r12
movq %rbp, %r13
jmp .LBB5_13
.p2align 4, 0x90
.LBB5_17: # %._crit_edge.i73
# in Loop: Header=BB5_13 Depth=1
incq %rbx
addq $20, %r13
addq $20, %r12
cmpq $5, %rbx
je .LBB5_18
.LBB5_13: # %.preheader.i69
# =>This Loop Header: Depth=1
# Child Loop BB5_14 Depth 2
xorl %r15d, %r15d
jmp .LBB5_14
.p2align 4, 0x90
.LBB5_16: # in Loop: Header=BB5_14 Depth=2
incq %r15
cmpq $5, %r15
je .LBB5_17
.LBB5_14: # Parent Loop BB5_13 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%r13,%r15,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jne .LBB5_15
jnp .LBB5_16
.LBB5_15: # in Loop: Header=BB5_14 Depth=2
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.3, %edi
movl %ebx, %esi
movl %r15d, %edx
movb $2, %al
callq printf
jmp .LBB5_16
.LBB5_18: # %_Z5validiPfS_.exit
movl $.Lstr.1, %edi
callq puts@PLT
movq (%rsp), %rdi
callq hipFree
movq 72(%rsp), %rdi # 8-byte Reload
callq free
movq %r14, %rdi
callq free
movq 64(%rsp), %rdi # 8-byte Reload
callq free
movq %rbp, %rdi
callq free
movl $.Lstr.2, %edi
callq puts@PLT
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8gpuFloydiPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 9
.type _Z8gpuFloydiPfi,@object # @_Z8gpuFloydiPfi
.section .rodata,"a",@progbits
.globl _Z8gpuFloydiPfi
.p2align 3, 0x0
_Z8gpuFloydiPfi:
.quad _Z23__device_stub__gpuFloydiPfi
.size _Z8gpuFloydiPfi, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "ERROR MISMATCH in array cpuGraph i %d j %d CPU SAYS %f and GPU SAYS %f \n"
.size .L.str.3, 73
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "RUNNING WITH %d VERTICES \n"
.size .L.str.5, 27
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "GPU Calculation Time elapsed: %.20f milliseconds\n"
.size .L.str.6, 50
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "CPU Calculation Time elapsed: %.20f milliseconds\n\n"
.size .L.str.7, 51
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8gpuFloydiPfi"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "VALIDATING that cpuGraph array from CPU and gpuGraph array from GPU match... "
.size .Lstr, 78
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "OK \n"
.size .Lstr.1, 5
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "FINISHED!!! "
.size .Lstr.2, 13
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__gpuFloydiPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8gpuFloydiPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8gpuFloydiPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e220000002600 */
/*0070*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f05270 */
/*0080*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0090*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd40000000a00 */
/*00b0*/ @!P0 IMAD R2, R7, R4, c[0x0][0x170] ; /* 0x00005c0007028624 */
/* 0x001fc800078e0204 */
/*00c0*/ @!P0 IMAD.WIDE.U32 R2, R2, R9, c[0x0][0x168] ; /* 0x00005a0002028625 */
/* 0x000fcc00078e0009 */
/*00d0*/ @!P0 LDG.E R2, [R2.64] ; /* 0x0000000402028981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD R4, R4, c[0x0][0x170], R0 ; /* 0x00005c0004047a24 */
/* 0x000fc800078e0200 */
/*00f0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0209 */
/*0100*/ IMAD R6, R7, c[0x0][0x160], R0 ; /* 0x0000580007067a24 */
/* 0x000fc800078e0200 */
/*0110*/ IMAD.WIDE R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fe200078e0209 */
/*0120*/ @!P0 F2I.TRUNC.NTZ R8, R2 ; /* 0x0000000200088305 */
/* 0x004e24000020f100 */
/*0130*/ @!P0 STS [RZ], R8 ; /* 0x00000008ff008388 */
/* 0x001fe80000000800 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0150*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0160*/ LDG.E R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x000ee8000c1e1900 */
/*0170*/ LDS R9, [RZ] ; /* 0x00000000ff097984 */
/* 0x000e220000000800 */
/*0180*/ F2I.TRUNC.NTZ R0, R4 ; /* 0x0000000400007305 */
/* 0x004e24000020f100 */
/*0190*/ IADD3 R0, R0, R9, RZ ; /* 0x0000000900007210 */
/* 0x001fcc0007ffe0ff */
/*01a0*/ I2F R3, R0 ; /* 0x0000000000037306 */
/* 0x000ee40000201400 */
/*01b0*/ FSETP.GT.AND P0, PT, R10, R3, PT ; /* 0x000000030a00720b */
/* 0x008fda0003f04000 */
/*01c0*/ @P0 STG.E [R6.64], R3 ; /* 0x0000000306000986 */
/* 0x000fe8000c101904 */
/*01d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8gpuFloydiPfi
.globl _Z8gpuFloydiPfi
.p2align 8
.type _Z8gpuFloydiPfi,@function
_Z8gpuFloydiPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s6, s[0:1], 0x10
s_mul_i32 s5, s15, s4
s_mov_b32 s1, 0
s_mov_b32 s7, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_3
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s5, s6
v_mov_b32_e32 v2, 0
s_lshl_b64 s[0:1], s[0:1], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
s_load_b32 s0, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_cvt_i32_f32_e32 v0, s0
ds_store_b32 v2, v0
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s7
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, s6, s4, v[1:2]
v_add_nc_u32_e32 v0, s5, v1
s_barrier
buffer_gl0_inv
v_mov_b32_e32 v4, 0
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v3, 31, v2
ds_load_b32 v4, v4
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_clause 0x1
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(1)
v_cvt_i32_f32_e32 v2, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v4, v2
v_cvt_f32_i32_e32 v2, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_f32_e32 vcc_lo, v3, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
global_store_b32 v[0:1], v2, off
.LBB0_5:
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB0_6:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8gpuFloydiPfi
.amdhsa_group_segment_fixed_size 4
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8gpuFloydiPfi, .Lfunc_end0-_Z8gpuFloydiPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8gpuFloydiPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8gpuFloydiPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006d97f_00000000-6_FloydWarshall.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11createGraphPfi
.type _Z11createGraphPfi, @function
_Z11createGraphPfi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r13
movl %esi, %ebx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rdi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $0, %ebp
pxor %xmm4, %xmm4
cvtsi2sdl %ebx, %xmm4
movsd %xmm4, 16(%rsp)
movl $0x000000000, %r12d
jmp .L4
.L27:
movsd 16(%rsp), %xmm0
call sqrt@PLT
mulsd 8(%rsp), %xmm0
cvttsd2sil %xmm0, %eax
addl %ebp, %eax
cltq
movl %r14d, 0(%r13,%rax,4)
movsd 16(%rsp), %xmm0
call sqrt@PLT
mulsd 8(%rsp), %xmm0
cvttsd2sil %xmm0, %eax
addl %ebp, %eax
cltq
movl 0(%r13,%rax,4), %r14d
movsd 16(%rsp), %xmm0
call sqrt@PLT
.L8:
mulsd 24(%rsp), %xmm0
cvttsd2sil %xmm0, %eax
addl %ebx, %eax
cltq
movl %r14d, 0(%r13,%rax,4)
.L9:
addl $1, %ebx
.L20:
pxor %xmm4, %xmm4
cvtsi2sdl %ebx, %xmm4
movsd %xmm4, 8(%rsp)
movq %r12, %xmm5
movsd 16(%rsp), %xmm2
ucomisd %xmm2, %xmm5
ja .L29
sqrtsd %xmm2, %xmm2
movapd %xmm2, %xmm0
.L15:
comisd 8(%rsp), %xmm0
jbe .L32
cmpl %ebx, %ebp
je .L5
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm4, %xmm4
cvtsi2ssl %eax, %xmm4
movd %xmm4, %r14d
movq %r12, %xmm5
movsd 16(%rsp), %xmm3
ucomisd %xmm3, %xmm5
ja .L27
sqrtsd %xmm3, %xmm3
movapd %xmm3, %xmm0
movsd 8(%rsp), %xmm1
mulsd %xmm3, %xmm1
cvttsd2sil %xmm1, %eax
addl %ebp, %eax
cltq
movss %xmm4, 0(%r13,%rax,4)
jmp .L8
.L5:
movq %r12, %xmm1
movsd 16(%rsp), %xmm7
ucomisd %xmm7, %xmm1
ja .L28
sqrtsd %xmm7, %xmm7
movapd %xmm7, %xmm0
.L12:
mulsd 8(%rsp), %xmm0
cvttsd2sil %xmm0, %eax
addl %ebp, %eax
cltq
movl $0x00000000, 0(%r13,%rax,4)
jmp .L9
.L28:
movsd 16(%rsp), %xmm0
call sqrt@PLT
jmp .L12
.L29:
movsd 16(%rsp), %xmm0
call sqrt@PLT
jmp .L15
.L32:
addl $1, %ebp
.L4:
pxor %xmm4, %xmm4
cvtsi2sdl %ebp, %xmm4
movsd %xmm4, 24(%rsp)
movq %r12, %xmm5
movsd 16(%rsp), %xmm7
ucomisd %xmm7, %xmm5
ja .L30
sqrtsd %xmm7, %xmm7
movapd %xmm7, %xmm0
.L19:
comisd 24(%rsp), %xmm0
jbe .L33
movl $0, %ebx
jmp .L20
.L30:
movsd 16(%rsp), %xmm0
call sqrt@PLT
jmp .L19
.L33:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z11createGraphPfi, .-_Z11createGraphPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%f "
.LC3:
.string "\n"
.text
.globl _Z10printGraphPfi
.type _Z10printGraphPfi, @function
_Z10printGraphPfi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L35
movslq %esi, %r14
leaq 0(,%r14,4), %r15
leaq (%rdi,%r15), %rbp
negq %r14
salq $2, %r14
movl $0, %r13d
leaq .LC2(%rip), %r12
.L37:
leaq 0(%rbp,%r14), %rbx
.L38:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L38
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addq %r15, %rbp
cmpl %r13d, 12(%rsp)
jne .L37
.L35:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z10printGraphPfi, .-_Z10printGraphPfi
.globl _Z8cpuFloydiPf
.type _Z8cpuFloydiPf, @function
_Z8cpuFloydiPf:
.LFB2059:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L52
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl %edi, %r10d
movq %rsi, %r13
movq %rsi, %rbp
movslq %edi, %r9
leaq 0(,%r9,4), %r8
addq %r8, %r13
movq %r9, %r11
negq %r11
salq $2, %r11
movl $0, %ebx
movl $0, %r12d
movl $0, %r14d
jmp .L43
.L44:
addq $4, %rax
cmpq %rdx, %rax
je .L55
.L46:
movss (%rcx), %xmm0
addss (%rax,%rsi,4), %xmm0
movss (%rax), %xmm1
comiss %xmm0, %xmm1
jbe .L44
movss %xmm0, (%rax)
jmp .L44
.L55:
leal 1(%rdi), %eax
addq %r8, %rdx
addq %r8, %rcx
subq %r9, %rsi
cmpl %eax, %r10d
je .L47
movl %eax, %edi
.L48:
leaq (%rdx,%r11), %rax
jmp .L46
.L47:
leal 1(%r12), %eax
addq $4, %rbp
addq %r9, %rbx
cmpl %edi, %r12d
je .L41
movl %eax, %r12d
.L43:
movq %rbx, %rsi
movq %rbp, %rcx
movq %r13, %rdx
movl %r14d, %edi
jmp .L48
.L41:
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
ret
.cfi_endproc
.LFE2059:
.size _Z8cpuFloydiPf, .-_Z8cpuFloydiPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "VALIDATING that cpuGraph array from CPU and gpuGraph array from GPU match... \n"
.align 8
.LC5:
.string "ERROR MISMATCH in array cpuGraph i %d j %d CPU SAYS %f and GPU SAYS %f \n"
.section .rodata.str1.1
.LC6:
.string "OK \n\n"
.text
.globl _Z5validiPfS_
.type _Z5validiPfS_, @function
_Z5validiPfS_:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %edi, %ebx
movl %edi, 12(%rsp)
movq %rsi, %r12
movq %rdx, %rbp
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jle .L57
movslq %ebx, %r13
leaq 0(,%r13,4), %r15
movl $0, %r14d
jmp .L58
.L62:
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl %ebx, %ecx
movl %r14d, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
.L59:
addq $1, %rbx
cmpq %r13, %rbx
je .L65
.L61:
movss (%r12,%rbx,4), %xmm0
movss 0(%rbp,%rbx,4), %xmm1
ucomiss %xmm1, %xmm0
jp .L62
je .L59
jmp .L62
.L65:
addl $1, %r14d
addq %r15, %r12
addq %r15, %rbp
cmpl %r14d, 12(%rsp)
je .L57
.L58:
movl $0, %ebx
jmp .L61
.L57:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z5validiPfS_, .-_Z5validiPfS_
.globl _Z29__device_stub__Z8gpuFloydiPfiiPfi
.type _Z29__device_stub__Z8gpuFloydiPfiiPfi, @function
_Z29__device_stub__Z8gpuFloydiPfiiPfi:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L70
.L66:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L71
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L70:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8gpuFloydiPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L66
.L71:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z29__device_stub__Z8gpuFloydiPfiiPfi, .-_Z29__device_stub__Z8gpuFloydiPfiiPfi
.globl _Z8gpuFloydiPfi
.type _Z8gpuFloydiPfi, @function
_Z8gpuFloydiPfi:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z8gpuFloydiPfiiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z8gpuFloydiPfi, .-_Z8gpuFloydiPfi
.section .rodata.str1.1
.LC7:
.string "RUNNING WITH %d VERTICES \n"
.section .rodata.str1.8
.align 8
.LC8:
.string "GPU Calculation Time elapsed: %.20f milliseconds\n"
.align 8
.LC11:
.string "CPU Calculation Time elapsed: %.20f milliseconds\n\n"
.section .rodata.str1.1
.LC12:
.string "FINISHED!!! \n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq .LC3(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $5, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $100, %esi
call cudaMalloc@PLT
movl $100, %edi
call malloc@PLT
movq %rax, %r12
movl $100, %edi
call malloc@PLT
movq %rax, %rbx
movl $100, %edi
call malloc@PLT
movq %rax, %rbp
movl $100, %edi
call malloc@PLT
movq %rax, %r13
movl $25, %esi
movq %r12, %rdi
call _Z11createGraphPfi
movl $20, %edx
.L75:
leaq -20(%rdx), %rax
.L76:
movss (%r12,%rax), %xmm0
movss %xmm0, (%rbx,%rax)
movss %xmm0, 0(%rbp,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L76
addq $20, %rdx
cmpq $120, %rdx
jne .L75
movl $1, %ecx
movl $100, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 32(%rsp)
movl $5, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %r14d
jmp .L79
.L85:
movl %r14d, %edx
movq 8(%rsp), %rsi
movl $5, %edi
call _Z29__device_stub__Z8gpuFloydiPfiiPfi
.L78:
addl $1, %r14d
cmpl $5, %r14d
je .L84
.L79:
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L78
jmp .L85
.L84:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $100, %edx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 44(%rsp)
leaq 44(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call clock@PLT
movq %rax, %r14
movq %rbx, %rsi
movl $5, %edi
call _Z8cpuFloydiPf
call clock@PLT
subq %r14, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC9(%rip), %xmm0
mulss .LC10(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r13, %rdx
movq %rbx, %rsi
movl $5, %edi
call _Z5validiPfS_
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L86
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L86:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z8gpuFloydiPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z8gpuFloydiPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC9:
.long 1232348160
.align 4
.LC10:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "FloydWarshall.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z11createGraphPfi
.LCPI0_0:
.quad 0x0000000000000000 # double 0
.text
.globl _Z11createGraphPfi
.p2align 4, 0x90
.type _Z11createGraphPfi,@function
_Z11createGraphPfi: # @_Z11createGraphPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $56, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
leaq 48(%rsp), %rdi
callq time
movl %eax, %edi
callq srand
cvtsi2sd %ebp, %xmm2
xorpd %xmm1, %xmm1
ucomisd %xmm1, %xmm2
movsd %xmm2, 8(%rsp) # 8-byte Spill
jb .LBB0_2
# %bb.1:
sqrtsd %xmm2, %xmm0
ucomisd %xmm1, %xmm0
ja .LBB0_4
jmp .LBB0_24
.LBB0_2: # %call.sqrt
movapd %xmm2, %xmm0
callq sqrt
xorpd %xmm1, %xmm1
movsd 8(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
ucomisd %xmm1, %xmm0
jbe .LBB0_24
.LBB0_4: # %.preheader.preheader
xorl %r14d, %r14d
xorps %xmm0, %xmm0
sqrtsd %xmm2, %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
xorpd %xmm0, %xmm0
movsd %xmm0, 40(%rsp) # 8-byte Spill
jmp .LBB0_5
.p2align 4, 0x90
.LBB0_23: # %._crit_edge.split
# in Loop: Header=BB0_5 Depth=1
incl %r14d
xorps %xmm1, %xmm1
cvtsi2sd %r14d, %xmm1
movsd %xmm1, 40(%rsp) # 8-byte Spill
ucomisd %xmm1, %xmm0
jbe .LBB0_24
.LBB0_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_9 Depth 2
ucomisd .LCPI0_0(%rip), %xmm2
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
jae .LBB0_7
# %bb.6: # %call.sqrt37
# in Loop: Header=BB0_5 Depth=1
movapd %xmm2, %xmm0
callq sqrt
movsd 8(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
.LBB0_7: # %.preheader.split
# in Loop: Header=BB0_5 Depth=1
ucomisd .LCPI0_0(%rip), %xmm0
jbe .LBB0_21
# %bb.8: # %.lr.ph.preheader
# in Loop: Header=BB0_5 Depth=1
xorl %r15d, %r15d
xorpd %xmm1, %xmm1
jmp .LBB0_9
.p2align 4, 0x90
.LBB0_20: # %.split41.split
# in Loop: Header=BB0_9 Depth=2
incl %r15d
xorps %xmm1, %xmm1
cvtsi2sd %r15d, %xmm1
ucomisd %xmm1, %xmm0
jbe .LBB0_21
.LBB0_9: # %.lr.ph
# Parent Loop BB0_5 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm3, %xmm3
cmpl %r15d, %r14d
jne .LBB0_11
# %bb.10: # in Loop: Header=BB0_9 Depth=2
movl %r14d, %ebp
jmp .LBB0_16
.p2align 4, 0x90
.LBB0_11: # in Loop: Header=BB0_9 Depth=2
movsd %xmm1, 24(%rsp) # 8-byte Spill
callq rand
movsd 8(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
movl %eax, %ebp
ucomisd .LCPI0_0(%rip), %xmm2
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
jae .LBB0_13
# %bb.12: # %call.sqrt39
# in Loop: Header=BB0_9 Depth=2
movapd %xmm2, %xmm0
callq sqrt
movsd 8(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
.LBB0_13: # %.split38
# in Loop: Header=BB0_9 Depth=2
movslq %ebp, %rax
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
movsd 24(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
mulsd %xmm3, %xmm0
cvttsd2si %xmm0, %eax
addl %r14d, %eax
cltq
movss %xmm1, (%rbx,%rax,4)
ucomisd .LCPI0_0(%rip), %xmm2
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
jae .LBB0_15
# %bb.14: # %call.sqrt40
# in Loop: Header=BB0_9 Depth=2
movapd %xmm2, %xmm0
callq sqrt
movsd 24(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
movsd 8(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
.LBB0_15: # %.split38.split
# in Loop: Header=BB0_9 Depth=2
mulsd %xmm0, %xmm3
cvttsd2si %xmm3, %eax
addl %r14d, %eax
cltq
movss (%rbx,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
movsd 40(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
movl %r15d, %ebp
.LBB0_16: # in Loop: Header=BB0_9 Depth=2
ucomisd .LCPI0_0(%rip), %xmm2
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
jae .LBB0_18
# %bb.17: # %call.sqrt42
# in Loop: Header=BB0_9 Depth=2
movapd %xmm2, %xmm0
movsd %xmm1, 24(%rsp) # 8-byte Spill
movss %xmm3, 36(%rsp) # 4-byte Spill
callq sqrt
movss 36(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movsd 24(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
movsd 8(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
.LBB0_18: # %.split41
# in Loop: Header=BB0_9 Depth=2
mulsd %xmm0, %xmm1
cvttsd2si %xmm1, %eax
addl %eax, %ebp
movslq %ebp, %rax
movss %xmm3, (%rbx,%rax,4)
ucomisd .LCPI0_0(%rip), %xmm2
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
jae .LBB0_20
# %bb.19: # %call.sqrt43
# in Loop: Header=BB0_9 Depth=2
movapd %xmm2, %xmm0
callq sqrt
movsd 8(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
jmp .LBB0_20
.p2align 4, 0x90
.LBB0_21: # %._crit_edge
# in Loop: Header=BB0_5 Depth=1
ucomisd .LCPI0_0(%rip), %xmm2
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
jae .LBB0_23
# %bb.22: # %call.sqrt44
# in Loop: Header=BB0_5 Depth=1
movapd %xmm2, %xmm0
callq sqrt
movsd 8(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
jmp .LBB0_23
.LBB0_24: # %._crit_edge29
addq $56, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z11createGraphPfi, .Lfunc_end0-_Z11createGraphPfi
.cfi_endproc
# -- End function
.globl _Z10printGraphPfi # -- Begin function _Z10printGraphPfi
.p2align 4, 0x90
.type _Z10printGraphPfi,@function
_Z10printGraphPfi: # @_Z10printGraphPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, (%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB1_5
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebx
movl %esi, %r15d
xorl %r12d, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movl %r12d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbp,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %r15
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addl %ebx, %r12d
cmpq %r15, %r13
jne .LBB1_2
.LBB1_5: # %._crit_edge13
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z10printGraphPfi, .Lfunc_end1-_Z10printGraphPfi
.cfi_endproc
# -- End function
.globl _Z23__device_stub__gpuFloydiPfi # -- Begin function _Z23__device_stub__gpuFloydiPfi
.p2align 4, 0x90
.type _Z23__device_stub__gpuFloydiPfi,@function
_Z23__device_stub__gpuFloydiPfi: # @_Z23__device_stub__gpuFloydiPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
movl %edx, (%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8gpuFloydiPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z23__device_stub__gpuFloydiPfi, .Lfunc_end2-_Z23__device_stub__gpuFloydiPfi
.cfi_endproc
# -- End function
.globl _Z8cpuFloydiPf # -- Begin function _Z8cpuFloydiPf
.p2align 4, 0x90
.type _Z8cpuFloydiPf,@function
_Z8cpuFloydiPf: # @_Z8cpuFloydiPf
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB3_10
# %bb.1: # %.preheader36.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %edi, %eax
xorl %ecx, %ecx
xorl %edx, %edx
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_8: # %._crit_edge39
# in Loop: Header=BB3_2 Depth=1
incq %rdx
addl %edi, %ecx
cmpq %rax, %rdx
je .LBB3_9
.LBB3_2: # %.preheader36
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
# Child Loop BB3_4 Depth 3
movl %ecx, %r8d
leaq (%rsi,%r8,4), %r8
leaq (%rsi,%rdx,4), %r9
xorl %r10d, %r10d
xorl %r11d, %r11d
jmp .LBB3_3
.p2align 4, 0x90
.LBB3_7: # %._crit_edge
# in Loop: Header=BB3_3 Depth=2
incq %r11
addl %edi, %r10d
cmpq %rax, %r11
je .LBB3_8
.LBB3_3: # %.preheader
# Parent Loop BB3_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_4 Depth 3
movl %r10d, %ebx
leaq (%rsi,%rbx,4), %rbx
movq %r11, %r14
imulq %rax, %r14
xorl %r15d, %r15d
jmp .LBB3_4
.p2align 4, 0x90
.LBB3_6: # in Loop: Header=BB3_4 Depth=3
incq %r15
cmpq %r15, %rax
je .LBB3_7
.LBB3_4: # Parent Loop BB3_2 Depth=1
# Parent Loop BB3_3 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rbx,%r15,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss (%r9,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%r8,%r15,4), %xmm0
ucomiss %xmm0, %xmm1
jbe .LBB3_6
# %bb.5: # in Loop: Header=BB3_4 Depth=3
movss %xmm0, (%rbx,%r15,4)
jmp .LBB3_6
.LBB3_9:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB3_10: # %._crit_edge41
retq
.Lfunc_end3:
.size _Z8cpuFloydiPf, .Lfunc_end3-_Z8cpuFloydiPf
.cfi_endproc
# -- End function
.globl _Z5validiPfS_ # -- Begin function _Z5validiPfS_
.p2align 4, 0x90
.type _Z5validiPfS_,@function
_Z5validiPfS_: # @_Z5validiPfS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, 16(%rsp) # 8-byte Spill
movq %rsi, 8(%rsp) # 8-byte Spill
movl %edi, %ebx
movl $.Lstr, %edi
callq puts@PLT
movl %ebx, 4(%rsp) # 4-byte Spill
testl %ebx, %ebx
jle .LBB4_7
# %bb.1: # %.preheader.lr.ph
movl 4(%rsp), %r13d # 4-byte Reload
xorl %ebx, %ebx
xorl %r15d, %r15d
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_6: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
incq %r15
addl 4(%rsp), %ebx # 4-byte Folded Reload
cmpq %r13, %r15
je .LBB4_7
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_3 Depth 2
movl %ebx, %eax
movq 16(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %r12d, %r12d
jmp .LBB4_3
.p2align 4, 0x90
.LBB4_5: # in Loop: Header=BB4_3 Depth=2
incq %r12
cmpq %r12, %r13
je .LBB4_6
.LBB4_3: # Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbp,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%r14,%r12,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jne .LBB4_4
jnp .LBB4_5
.LBB4_4: # in Loop: Header=BB4_3 Depth=2
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.3, %edi
movl %r15d, %esi
movl %r12d, %edx
movb $2, %al
callq printf
jmp .LBB4_5
.LBB4_7: # %._crit_edge30
movl $.Lstr.1, %edi
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end4:
.size _Z5validiPfS_, .Lfunc_end4-_Z5validiPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI5_0:
.long 0x49742400 # float 1.0E+6
.LCPI5_1:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movl $10, %edi
callq putchar@PLT
xorl %ebx, %ebx
movl $.L.str.5, %edi
movl $5, %esi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
movq %rsp, %rdi
movl $100, %esi
callq hipMalloc
movl $100, %edi
callq malloc
movq %rax, %r15
movl $100, %edi
callq malloc
movq %rax, %r14
movl $100, %edi
callq malloc
movq %rax, %r12
movl $100, %edi
callq malloc
movq %rax, 56(%rsp) # 8-byte Spill
movq %r15, %rdi
movl $25, %esi
callq _Z11createGraphPfi
movl 96(%r15), %eax
movl %eax, 96(%r14)
movups 80(%r15), %xmm0
movups %xmm0, 80(%r14)
movups 64(%r15), %xmm0
movups %xmm0, 64(%r14)
movups (%r15), %xmm0
movups 16(%r15), %xmm1
movups 32(%r15), %xmm2
movups 48(%r15), %xmm3
movups %xmm3, 48(%r14)
movups %xmm2, 32(%r14)
movups %xmm1, 16(%r14)
movups %xmm0, (%r14)
movl 96(%r15), %eax
movl %eax, 96(%r12)
movups 80(%r15), %xmm0
movups %xmm0, 80(%r12)
movups 64(%r15), %xmm0
movups %xmm0, 64(%r12)
movups (%r15), %xmm0
movups 16(%r15), %xmm1
movups 32(%r15), %xmm2
movq %r15, 72(%rsp) # 8-byte Spill
movups 48(%r15), %xmm3
movups %xmm3, 48(%r12)
movups %xmm2, 32(%r12)
movups %xmm1, 16(%r12)
movups %xmm0, (%r12)
movq (%rsp), %rdi
movl $100, %edx
movq %r12, 64(%rsp) # 8-byte Spill
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $21474836481, %r13 # imm = 0x500000001
movabsq $4294967808, %rbp # imm = 0x100000200
leaq 80(%rsp), %r12
leaq 32(%rsp), %r15
jmp .LBB5_1
.p2align 4, 0x90
.LBB5_3: # in Loop: Header=BB5_1 Depth=1
incl %ebx
cmpl $5, %ebx
je .LBB5_4
.LBB5_1: # =>This Inner Loop Header: Depth=1
movq %r13, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_3
# %bb.2: # in Loop: Header=BB5_1 Depth=1
movq (%rsp), %rax
movl $5, 20(%rsp)
movq %rax, 128(%rsp)
movl %ebx, 16(%rsp)
leaq 20(%rsp), %rax
movq %rax, 32(%rsp)
leaq 128(%rsp), %rax
movq %rax, 40(%rsp)
leaq 16(%rsp), %rax
movq %rax, 48(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
movl $_Z8gpuFloydiPfi, %edi
movq %r15, %r9
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB5_3
.LBB5_4:
movq 8(%rsp), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rsi
movl $100, %edx
movq 56(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipEventSynchronize
movl $0, 32(%rsp)
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
callq clock
movq %rax, %r15
movq %r14, %rax
jmp .LBB5_5
.p2align 4, 0x90
.LBB5_11: # %._crit_edge39.i
# in Loop: Header=BB5_5 Depth=1
incq %rbx
addq $20, %rax
cmpq $5, %rbx
je .LBB5_12
.LBB5_5: # %.preheader36.i
# =>This Loop Header: Depth=1
# Child Loop BB5_6 Depth 2
# Child Loop BB5_7 Depth 3
leaq (%r14,%rbx,4), %rcx
movq %r14, %rdx
xorl %esi, %esi
jmp .LBB5_6
.p2align 4, 0x90
.LBB5_10: # %._crit_edge.i
# in Loop: Header=BB5_6 Depth=2
incq %rsi
addq $20, %rdx
cmpq $5, %rsi
je .LBB5_11
.LBB5_6: # %.preheader.i
# Parent Loop BB5_5 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB5_7 Depth 3
leaq (%rsi,%rsi,4), %rdi
xorl %r8d, %r8d
jmp .LBB5_7
.p2align 4, 0x90
.LBB5_9: # in Loop: Header=BB5_7 Depth=3
incq %r8
cmpq $5, %r8
je .LBB5_10
.LBB5_7: # Parent Loop BB5_5 Depth=1
# Parent Loop BB5_6 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rdx,%r8,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss (%rcx,%rdi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rax,%r8,4), %xmm0
ucomiss %xmm0, %xmm1
jbe .LBB5_9
# %bb.8: # in Loop: Header=BB5_7 Depth=3
movss %xmm0, (%rdx,%r8,4)
jmp .LBB5_9
.LBB5_12: # %_Z8cpuFloydiPf.exit
callq clock
subq %r15, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
divss .LCPI5_0(%rip), %xmm0
mulss .LCPI5_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
movq %r14, %r12
movq %rbp, %r13
jmp .LBB5_13
.p2align 4, 0x90
.LBB5_17: # %._crit_edge.i73
# in Loop: Header=BB5_13 Depth=1
incq %rbx
addq $20, %r13
addq $20, %r12
cmpq $5, %rbx
je .LBB5_18
.LBB5_13: # %.preheader.i69
# =>This Loop Header: Depth=1
# Child Loop BB5_14 Depth 2
xorl %r15d, %r15d
jmp .LBB5_14
.p2align 4, 0x90
.LBB5_16: # in Loop: Header=BB5_14 Depth=2
incq %r15
cmpq $5, %r15
je .LBB5_17
.LBB5_14: # Parent Loop BB5_13 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%r13,%r15,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jne .LBB5_15
jnp .LBB5_16
.LBB5_15: # in Loop: Header=BB5_14 Depth=2
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.3, %edi
movl %ebx, %esi
movl %r15d, %edx
movb $2, %al
callq printf
jmp .LBB5_16
.LBB5_18: # %_Z5validiPfS_.exit
movl $.Lstr.1, %edi
callq puts@PLT
movq (%rsp), %rdi
callq hipFree
movq 72(%rsp), %rdi # 8-byte Reload
callq free
movq %r14, %rdi
callq free
movq 64(%rsp), %rdi # 8-byte Reload
callq free
movq %rbp, %rdi
callq free
movl $.Lstr.2, %edi
callq puts@PLT
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8gpuFloydiPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 9
.type _Z8gpuFloydiPfi,@object # @_Z8gpuFloydiPfi
.section .rodata,"a",@progbits
.globl _Z8gpuFloydiPfi
.p2align 3, 0x0
_Z8gpuFloydiPfi:
.quad _Z23__device_stub__gpuFloydiPfi
.size _Z8gpuFloydiPfi, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "ERROR MISMATCH in array cpuGraph i %d j %d CPU SAYS %f and GPU SAYS %f \n"
.size .L.str.3, 73
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "RUNNING WITH %d VERTICES \n"
.size .L.str.5, 27
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "GPU Calculation Time elapsed: %.20f milliseconds\n"
.size .L.str.6, 50
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "CPU Calculation Time elapsed: %.20f milliseconds\n\n"
.size .L.str.7, 51
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8gpuFloydiPfi"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "VALIDATING that cpuGraph array from CPU and gpuGraph array from GPU match... "
.size .Lstr, 78
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "OK \n"
.size .Lstr.1, 5
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "FINISHED!!! "
.size .Lstr.2, 13
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__gpuFloydiPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8gpuFloydiPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <stdio.h>
#include <cstdlib>
#include <ctime>
using namespace std;
void matrix_multiplication(float* M, float* N, float* P, int witdh) {
for (int i = 0; i < witdh; i++) {
for (int j = 0; j < witdh; j++) {
int sum = 0;
for (int k = 0; k < witdh; k++) {
float a = M[i * witdh + k];
float b = N[k * witdh + j];
sum += a * b;
}
P[i * witdh + j] = sum;
}
}
}
int main(int argc, char **argv) {
int witdh = 200;
float* A;
float* B;
float* C;
A = (float*) malloc(witdh * witdh * sizeof(float));
B = (float*) malloc(witdh * witdh * sizeof(float));
C = (float*) malloc(witdh * witdh * sizeof(float));
srand (time(NULL));
// for (int i = 0; i < witdh; i++) {
// for (int j = 0; j < witdh; j++) {
// A[i * witdh + j] = (rand() % 100) + 1;
// B[i * witdh + j] = (rand() % 200) + 1;
// }
// }
// cout << endl;
// for (int i = 0; i < witdh; i++) {
// for (int j = 0; j < witdh; j++) {
// cout << A[i * witdh + j] << "\t";
// }
// cout << endl;
// }
// cout << endl;
// for (int i = 0; i < witdh; i++) {
// for (int j = 0; j < witdh; j++) {
// cout << B[i * witdh + j] << "\t";
// }
// cout << endl;
// }
matrix_multiplication(A, B, C, witdh);
/*for (int i = 0; i < witdh; i++) {
for (int j = 0; j < witdh; j++) {
cout << C[i * witdh + j] << "\t";
}
cout << endl;
}*/
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <stdio.h>
#include <cstdlib>
#include <ctime>
using namespace std;
void matrix_multiplication(float* M, float* N, float* P, int witdh) {
for (int i = 0; i < witdh; i++) {
for (int j = 0; j < witdh; j++) {
int sum = 0;
for (int k = 0; k < witdh; k++) {
float a = M[i * witdh + k];
float b = N[k * witdh + j];
sum += a * b;
}
P[i * witdh + j] = sum;
}
}
}
int main(int argc, char **argv) {
int witdh = 200;
float* A;
float* B;
float* C;
A = (float*) malloc(witdh * witdh * sizeof(float));
B = (float*) malloc(witdh * witdh * sizeof(float));
C = (float*) malloc(witdh * witdh * sizeof(float));
srand (time(NULL));
// for (int i = 0; i < witdh; i++) {
// for (int j = 0; j < witdh; j++) {
// A[i * witdh + j] = (rand() % 100) + 1;
// B[i * witdh + j] = (rand() % 200) + 1;
// }
// }
// cout << endl;
// for (int i = 0; i < witdh; i++) {
// for (int j = 0; j < witdh; j++) {
// cout << A[i * witdh + j] << "\t";
// }
// cout << endl;
// }
// cout << endl;
// for (int i = 0; i < witdh; i++) {
// for (int j = 0; j < witdh; j++) {
// cout << B[i * witdh + j] << "\t";
// }
// cout << endl;
// }
matrix_multiplication(A, B, C, witdh);
/*for (int i = 0; i < witdh; i++) {
for (int j = 0; j < witdh; j++) {
cout << C[i * witdh + j] << "\t";
}
cout << endl;
}*/
return 0;
} | .file "tmpxft_0016fb01_00000000-6_matrix_mul_host.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z21matrix_multiplicationPfS_S_i
.type _Z21matrix_multiplicationPfS_S_i, @function
_Z21matrix_multiplicationPfS_S_i:
.LFB3669:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L11
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rsi, %rbp
movq %rdx, %r10
movl %ecx, %r13d
movslq %ecx, %rbx
leaq 0(,%rbx,4), %rsi
movq %rdi, %r11
addq %rsi, %rdi
movl $0, %r14d
movl $0, %r12d
.L5:
movq %rbp, %r9
movl $0, %r8d
.L8:
movq %r9, %rdx
movq %r11, %rax
movl %r12d, %ecx
.L6:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %ecx, %xmm1
addss %xmm1, %xmm0
cvttss2sil %xmm0, %ecx
addq $4, %rax
addq %rsi, %rdx
cmpq %rdi, %rax
jne .L6
pxor %xmm0, %xmm0
cvtsi2ssl %ecx, %xmm0
movss %xmm0, (%r10,%r8,4)
addq $1, %r8
addq $4, %r9
cmpq %rbx, %r8
jne .L8
addl $1, %r14d
addq %rsi, %r10
addq %rsi, %r11
addq %rsi, %rdi
cmpl %r14d, %r13d
jne .L5
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
ret
.cfi_endproc
.LFE3669:
.size _Z21matrix_multiplicationPfS_S_i, .-_Z21matrix_multiplicationPfS_S_i
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl $160000, %edi
call malloc@PLT
movq %rax, %rbx
movl $160000, %edi
call malloc@PLT
movq %rax, %rbp
movl $160000, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $200, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z21matrix_multiplicationPfS_S_i
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <stdio.h>
#include <cstdlib>
#include <ctime>
using namespace std;
void matrix_multiplication(float* M, float* N, float* P, int witdh) {
for (int i = 0; i < witdh; i++) {
for (int j = 0; j < witdh; j++) {
int sum = 0;
for (int k = 0; k < witdh; k++) {
float a = M[i * witdh + k];
float b = N[k * witdh + j];
sum += a * b;
}
P[i * witdh + j] = sum;
}
}
}
int main(int argc, char **argv) {
int witdh = 200;
float* A;
float* B;
float* C;
A = (float*) malloc(witdh * witdh * sizeof(float));
B = (float*) malloc(witdh * witdh * sizeof(float));
C = (float*) malloc(witdh * witdh * sizeof(float));
srand (time(NULL));
// for (int i = 0; i < witdh; i++) {
// for (int j = 0; j < witdh; j++) {
// A[i * witdh + j] = (rand() % 100) + 1;
// B[i * witdh + j] = (rand() % 200) + 1;
// }
// }
// cout << endl;
// for (int i = 0; i < witdh; i++) {
// for (int j = 0; j < witdh; j++) {
// cout << A[i * witdh + j] << "\t";
// }
// cout << endl;
// }
// cout << endl;
// for (int i = 0; i < witdh; i++) {
// for (int j = 0; j < witdh; j++) {
// cout << B[i * witdh + j] << "\t";
// }
// cout << endl;
// }
matrix_multiplication(A, B, C, witdh);
/*for (int i = 0; i < witdh; i++) {
for (int j = 0; j < witdh; j++) {
cout << C[i * witdh + j] << "\t";
}
cout << endl;
}*/
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <cstdlib>
#include <ctime>
using namespace std;
void matrix_multiplication(float* M, float* N, float* P, int witdh) {
for (int i = 0; i < witdh; i++) {
for (int j = 0; j < witdh; j++) {
int sum = 0;
for (int k = 0; k < witdh; k++) {
float a = M[i * witdh + k];
float b = N[k * witdh + j];
sum += a * b;
}
P[i * witdh + j] = sum;
}
}
}
int main(int argc, char **argv) {
int witdh = 200;
float* A;
float* B;
float* C;
A = (float*) malloc(witdh * witdh * sizeof(float));
B = (float*) malloc(witdh * witdh * sizeof(float));
C = (float*) malloc(witdh * witdh * sizeof(float));
srand (time(NULL));
// for (int i = 0; i < witdh; i++) {
// for (int j = 0; j < witdh; j++) {
// A[i * witdh + j] = (rand() % 100) + 1;
// B[i * witdh + j] = (rand() % 200) + 1;
// }
// }
// cout << endl;
// for (int i = 0; i < witdh; i++) {
// for (int j = 0; j < witdh; j++) {
// cout << A[i * witdh + j] << "\t";
// }
// cout << endl;
// }
// cout << endl;
// for (int i = 0; i < witdh; i++) {
// for (int j = 0; j < witdh; j++) {
// cout << B[i * witdh + j] << "\t";
// }
// cout << endl;
// }
matrix_multiplication(A, B, C, witdh);
/*for (int i = 0; i < witdh; i++) {
for (int j = 0; j < witdh; j++) {
cout << C[i * witdh + j] << "\t";
}
cout << endl;
}*/
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <cstdlib>
#include <ctime>
using namespace std;
void matrix_multiplication(float* M, float* N, float* P, int witdh) {
for (int i = 0; i < witdh; i++) {
for (int j = 0; j < witdh; j++) {
int sum = 0;
for (int k = 0; k < witdh; k++) {
float a = M[i * witdh + k];
float b = N[k * witdh + j];
sum += a * b;
}
P[i * witdh + j] = sum;
}
}
}
int main(int argc, char **argv) {
int witdh = 200;
float* A;
float* B;
float* C;
A = (float*) malloc(witdh * witdh * sizeof(float));
B = (float*) malloc(witdh * witdh * sizeof(float));
C = (float*) malloc(witdh * witdh * sizeof(float));
srand (time(NULL));
// for (int i = 0; i < witdh; i++) {
// for (int j = 0; j < witdh; j++) {
// A[i * witdh + j] = (rand() % 100) + 1;
// B[i * witdh + j] = (rand() % 200) + 1;
// }
// }
// cout << endl;
// for (int i = 0; i < witdh; i++) {
// for (int j = 0; j < witdh; j++) {
// cout << A[i * witdh + j] << "\t";
// }
// cout << endl;
// }
// cout << endl;
// for (int i = 0; i < witdh; i++) {
// for (int j = 0; j < witdh; j++) {
// cout << B[i * witdh + j] << "\t";
// }
// cout << endl;
// }
matrix_multiplication(A, B, C, witdh);
/*for (int i = 0; i < witdh; i++) {
for (int j = 0; j < witdh; j++) {
cout << C[i * witdh + j] << "\t";
}
cout << endl;
}*/
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <cstdlib>
#include <ctime>
using namespace std;
void matrix_multiplication(float* M, float* N, float* P, int witdh) {
for (int i = 0; i < witdh; i++) {
for (int j = 0; j < witdh; j++) {
int sum = 0;
for (int k = 0; k < witdh; k++) {
float a = M[i * witdh + k];
float b = N[k * witdh + j];
sum += a * b;
}
P[i * witdh + j] = sum;
}
}
}
int main(int argc, char **argv) {
int witdh = 200;
float* A;
float* B;
float* C;
A = (float*) malloc(witdh * witdh * sizeof(float));
B = (float*) malloc(witdh * witdh * sizeof(float));
C = (float*) malloc(witdh * witdh * sizeof(float));
srand (time(NULL));
// for (int i = 0; i < witdh; i++) {
// for (int j = 0; j < witdh; j++) {
// A[i * witdh + j] = (rand() % 100) + 1;
// B[i * witdh + j] = (rand() % 200) + 1;
// }
// }
// cout << endl;
// for (int i = 0; i < witdh; i++) {
// for (int j = 0; j < witdh; j++) {
// cout << A[i * witdh + j] << "\t";
// }
// cout << endl;
// }
// cout << endl;
// for (int i = 0; i < witdh; i++) {
// for (int j = 0; j < witdh; j++) {
// cout << B[i * witdh + j] << "\t";
// }
// cout << endl;
// }
matrix_multiplication(A, B, C, witdh);
/*for (int i = 0; i < witdh; i++) {
for (int j = 0; j < witdh; j++) {
cout << C[i * witdh + j] << "\t";
}
cout << endl;
}*/
return 0;
} | .text
.file "matrix_mul_host.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21matrix_multiplicationPfS_S_i # -- Begin function _Z21matrix_multiplicationPfS_S_i
.p2align 4, 0x90
.type _Z21matrix_multiplicationPfS_S_i,@function
_Z21matrix_multiplicationPfS_S_i: # @_Z21matrix_multiplicationPfS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB0_8
# %bb.1: # %.preheader28.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %eax
leaq (,%rax,4), %r8
xorl %r9d, %r9d
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB0_2: # %.preheader28
# =>This Loop Header: Depth=1
# Child Loop BB0_3 Depth 2
# Child Loop BB0_4 Depth 3
movl %r9d, %r11d
leaq (%rdi,%r11,4), %r11
movq %r10, %rbx
imulq %rax, %rbx
leaq (%rdx,%rbx,4), %rbx
movq %rsi, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_3: # %.preheader
# Parent Loop BB0_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_4 Depth 3
xorl %r12d, %r12d
movq %r14, %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# Parent Loop BB0_3 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r11,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%r13), %xmm0
xorps %xmm1, %xmm1
cvtsi2ss %ebp, %xmm1
addss %xmm0, %xmm1
cvttss2si %xmm1, %ebp
incq %r12
addq %r8, %r13
cmpq %r12, %rax
jne .LBB0_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB0_3 Depth=2
xorps %xmm0, %xmm0
cvtsi2ss %ebp, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
addq $4, %r14
cmpq %rax, %r15
jne .LBB0_3
# %bb.6: # %._crit_edge32
# in Loop: Header=BB0_2 Depth=1
incq %r10
addl %ecx, %r9d
cmpq %rax, %r10
jne .LBB0_2
# %bb.7:
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB0_8: # %._crit_edge34
retq
.Lfunc_end0:
.size _Z21matrix_multiplicationPfS_S_i, .Lfunc_end0-_Z21matrix_multiplicationPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0: # %_Z21matrix_multiplicationPfS_S_i.exit
pushq %rax
.cfi_def_cfa_offset 16
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016fb01_00000000-6_matrix_mul_host.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z21matrix_multiplicationPfS_S_i
.type _Z21matrix_multiplicationPfS_S_i, @function
_Z21matrix_multiplicationPfS_S_i:
.LFB3669:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L11
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rsi, %rbp
movq %rdx, %r10
movl %ecx, %r13d
movslq %ecx, %rbx
leaq 0(,%rbx,4), %rsi
movq %rdi, %r11
addq %rsi, %rdi
movl $0, %r14d
movl $0, %r12d
.L5:
movq %rbp, %r9
movl $0, %r8d
.L8:
movq %r9, %rdx
movq %r11, %rax
movl %r12d, %ecx
.L6:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %ecx, %xmm1
addss %xmm1, %xmm0
cvttss2sil %xmm0, %ecx
addq $4, %rax
addq %rsi, %rdx
cmpq %rdi, %rax
jne .L6
pxor %xmm0, %xmm0
cvtsi2ssl %ecx, %xmm0
movss %xmm0, (%r10,%r8,4)
addq $1, %r8
addq $4, %r9
cmpq %rbx, %r8
jne .L8
addl $1, %r14d
addq %rsi, %r10
addq %rsi, %r11
addq %rsi, %rdi
cmpl %r14d, %r13d
jne .L5
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
ret
.cfi_endproc
.LFE3669:
.size _Z21matrix_multiplicationPfS_S_i, .-_Z21matrix_multiplicationPfS_S_i
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl $160000, %edi
call malloc@PLT
movq %rax, %rbx
movl $160000, %edi
call malloc@PLT
movq %rax, %rbp
movl $160000, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $200, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z21matrix_multiplicationPfS_S_i
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix_mul_host.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21matrix_multiplicationPfS_S_i # -- Begin function _Z21matrix_multiplicationPfS_S_i
.p2align 4, 0x90
.type _Z21matrix_multiplicationPfS_S_i,@function
_Z21matrix_multiplicationPfS_S_i: # @_Z21matrix_multiplicationPfS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB0_8
# %bb.1: # %.preheader28.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %eax
leaq (,%rax,4), %r8
xorl %r9d, %r9d
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB0_2: # %.preheader28
# =>This Loop Header: Depth=1
# Child Loop BB0_3 Depth 2
# Child Loop BB0_4 Depth 3
movl %r9d, %r11d
leaq (%rdi,%r11,4), %r11
movq %r10, %rbx
imulq %rax, %rbx
leaq (%rdx,%rbx,4), %rbx
movq %rsi, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_3: # %.preheader
# Parent Loop BB0_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_4 Depth 3
xorl %r12d, %r12d
movq %r14, %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# Parent Loop BB0_3 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r11,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%r13), %xmm0
xorps %xmm1, %xmm1
cvtsi2ss %ebp, %xmm1
addss %xmm0, %xmm1
cvttss2si %xmm1, %ebp
incq %r12
addq %r8, %r13
cmpq %r12, %rax
jne .LBB0_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB0_3 Depth=2
xorps %xmm0, %xmm0
cvtsi2ss %ebp, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
addq $4, %r14
cmpq %rax, %r15
jne .LBB0_3
# %bb.6: # %._crit_edge32
# in Loop: Header=BB0_2 Depth=1
incq %r10
addl %ecx, %r9d
cmpq %rax, %r10
jne .LBB0_2
# %bb.7:
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB0_8: # %._crit_edge34
retq
.Lfunc_end0:
.size _Z21matrix_multiplicationPfS_S_i, .Lfunc_end0-_Z21matrix_multiplicationPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0: # %_Z21matrix_multiplicationPfS_S_i.exit
pushq %rax
.cfi_def_cfa_offset 16
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
int main(){
printf("\n\n");
// CUDA device properties struct
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, 0);
// Device name
printf("Device Name: %s\n",prop.name);
// Compute capability
printf("Compute capability: major: %d\tminor: %d\n\n", prop.major, prop.minor);
// Maximum block dimension
printf("Maximum block dimension in x: %d\n", prop.maxThreadsDim[0]);
printf("Maximum block dimension in y: %d\n", prop.maxThreadsDim[1]);
printf("Maximum block dimension in z: %d\n\n", prop.maxThreadsDim[2]);
// Maximum block dimension
printf("Maximum grid dimension in x: %d\n", prop.maxGridSize[0]);
printf("Maximum grid dimension in y: %d\n", prop.maxGridSize[1]);
printf("Maximum grid dimension in z: %d\n\n", prop.maxGridSize[2]);
// Shared Memory Per Block
printf("Shared memory per block: %zu\n", prop.sharedMemPerBlock);
// Total Global Memory
printf("Total global memory: %zu\n", prop.totalGlobalMem);
// Total Constant Memory
printf("Total constant memory: %zu\n\n", prop.totalConstMem);
// Warp size
printf("Warp size: %d\n", prop.warpSize);
printf("\n\n");
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
int main(){
printf("\n\n");
// CUDA device properties struct
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, 0);
// Device name
printf("Device Name: %s\n",prop.name);
// Compute capability
printf("Compute capability: major: %d\tminor: %d\n\n", prop.major, prop.minor);
// Maximum block dimension
printf("Maximum block dimension in x: %d\n", prop.maxThreadsDim[0]);
printf("Maximum block dimension in y: %d\n", prop.maxThreadsDim[1]);
printf("Maximum block dimension in z: %d\n\n", prop.maxThreadsDim[2]);
// Maximum block dimension
printf("Maximum grid dimension in x: %d\n", prop.maxGridSize[0]);
printf("Maximum grid dimension in y: %d\n", prop.maxGridSize[1]);
printf("Maximum grid dimension in z: %d\n\n", prop.maxGridSize[2]);
// Shared Memory Per Block
printf("Shared memory per block: %zu\n", prop.sharedMemPerBlock);
// Total Global Memory
printf("Total global memory: %zu\n", prop.totalGlobalMem);
// Total Constant Memory
printf("Total constant memory: %zu\n\n", prop.totalConstMem);
// Warp size
printf("Warp size: %d\n", prop.warpSize);
printf("\n\n");
} | .file "tmpxft_00048696_00000000-6_q1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n\n"
.LC1:
.string "Device Name: %s\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Compute capability: major: %d\tminor: %d\n\n"
.align 8
.LC3:
.string "Maximum block dimension in x: %d\n"
.align 8
.LC4:
.string "Maximum block dimension in y: %d\n"
.align 8
.LC5:
.string "Maximum block dimension in z: %d\n\n"
.align 8
.LC6:
.string "Maximum grid dimension in x: %d\n"
.align 8
.LC7:
.string "Maximum grid dimension in y: %d\n"
.align 8
.LC8:
.string "Maximum grid dimension in z: %d\n\n"
.section .rodata.str1.1
.LC9:
.string "Shared memory per block: %zu\n"
.LC10:
.string "Total global memory: %zu\n"
.LC11:
.string "Total constant memory: %zu\n\n"
.LC12:
.string "Warp size: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1048, %rsp
.cfi_def_cfa_offset 1072
movq %fs:40, %rax
movq %rax, 1032(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
call __printf_chk@PLT
movq %rsp, %rbp
movl $0, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbp, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 364(%rsp), %ecx
movl 360(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 324(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 328(%rsp), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 332(%rsp), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 340(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 344(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 296(%rsp), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 288(%rsp), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 352(%rsp), %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 308(%rsp), %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $1048, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
int main(){
printf("\n\n");
// CUDA device properties struct
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, 0);
// Device name
printf("Device Name: %s\n",prop.name);
// Compute capability
printf("Compute capability: major: %d\tminor: %d\n\n", prop.major, prop.minor);
// Maximum block dimension
printf("Maximum block dimension in x: %d\n", prop.maxThreadsDim[0]);
printf("Maximum block dimension in y: %d\n", prop.maxThreadsDim[1]);
printf("Maximum block dimension in z: %d\n\n", prop.maxThreadsDim[2]);
// Maximum block dimension
printf("Maximum grid dimension in x: %d\n", prop.maxGridSize[0]);
printf("Maximum grid dimension in y: %d\n", prop.maxGridSize[1]);
printf("Maximum grid dimension in z: %d\n\n", prop.maxGridSize[2]);
// Shared Memory Per Block
printf("Shared memory per block: %zu\n", prop.sharedMemPerBlock);
// Total Global Memory
printf("Total global memory: %zu\n", prop.totalGlobalMem);
// Total Constant Memory
printf("Total constant memory: %zu\n\n", prop.totalConstMem);
// Warp size
printf("Warp size: %d\n", prop.warpSize);
printf("\n\n");
} | #include <hip/hip_runtime.h>
#include <stdio.h>
int main(){
printf("\n\n");
// CUDA device properties struct
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, 0);
// Device name
printf("Device Name: %s\n",prop.name);
// Compute capability
printf("Compute capability: major: %d\tminor: %d\n\n", prop.major, prop.minor);
// Maximum block dimension
printf("Maximum block dimension in x: %d\n", prop.maxThreadsDim[0]);
printf("Maximum block dimension in y: %d\n", prop.maxThreadsDim[1]);
printf("Maximum block dimension in z: %d\n\n", prop.maxThreadsDim[2]);
// Maximum block dimension
printf("Maximum grid dimension in x: %d\n", prop.maxGridSize[0]);
printf("Maximum grid dimension in y: %d\n", prop.maxGridSize[1]);
printf("Maximum grid dimension in z: %d\n\n", prop.maxGridSize[2]);
// Shared Memory Per Block
printf("Shared memory per block: %zu\n", prop.sharedMemPerBlock);
// Total Global Memory
printf("Total global memory: %zu\n", prop.totalGlobalMem);
// Total Constant Memory
printf("Total constant memory: %zu\n\n", prop.totalConstMem);
// Warp size
printf("Warp size: %d\n", prop.warpSize);
printf("\n\n");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
int main(){
printf("\n\n");
// CUDA device properties struct
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, 0);
// Device name
printf("Device Name: %s\n",prop.name);
// Compute capability
printf("Compute capability: major: %d\tminor: %d\n\n", prop.major, prop.minor);
// Maximum block dimension
printf("Maximum block dimension in x: %d\n", prop.maxThreadsDim[0]);
printf("Maximum block dimension in y: %d\n", prop.maxThreadsDim[1]);
printf("Maximum block dimension in z: %d\n\n", prop.maxThreadsDim[2]);
// Maximum block dimension
printf("Maximum grid dimension in x: %d\n", prop.maxGridSize[0]);
printf("Maximum grid dimension in y: %d\n", prop.maxGridSize[1]);
printf("Maximum grid dimension in z: %d\n\n", prop.maxGridSize[2]);
// Shared Memory Per Block
printf("Shared memory per block: %zu\n", prop.sharedMemPerBlock);
// Total Global Memory
printf("Total global memory: %zu\n", prop.totalGlobalMem);
// Total Constant Memory
printf("Total constant memory: %zu\n\n", prop.totalConstMem);
// Warp size
printf("Warp size: %d\n", prop.warpSize);
printf("\n\n");
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
int main(){
printf("\n\n");
// CUDA device properties struct
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, 0);
// Device name
printf("Device Name: %s\n",prop.name);
// Compute capability
printf("Compute capability: major: %d\tminor: %d\n\n", prop.major, prop.minor);
// Maximum block dimension
printf("Maximum block dimension in x: %d\n", prop.maxThreadsDim[0]);
printf("Maximum block dimension in y: %d\n", prop.maxThreadsDim[1]);
printf("Maximum block dimension in z: %d\n\n", prop.maxThreadsDim[2]);
// Maximum block dimension
printf("Maximum grid dimension in x: %d\n", prop.maxGridSize[0]);
printf("Maximum grid dimension in y: %d\n", prop.maxGridSize[1]);
printf("Maximum grid dimension in z: %d\n\n", prop.maxGridSize[2]);
// Shared Memory Per Block
printf("Shared memory per block: %zu\n", prop.sharedMemPerBlock);
// Total Global Memory
printf("Total global memory: %zu\n", prop.totalGlobalMem);
// Total Constant Memory
printf("Total constant memory: %zu\n\n", prop.totalConstMem);
// Warp size
printf("Warp size: %d\n", prop.warpSize);
printf("\n\n");
} | .text
.file "q1.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1472, %rsp # imm = 0x5C0
.cfi_def_cfa_offset 1488
.cfi_offset %rbx, -16
movl $.Lstr.1, %edi
callq puts@PLT
movq %rsp, %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 360(%rsp), %esi
movl 364(%rsp), %edx
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl 324(%rsp), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl 328(%rsp), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl 332(%rsp), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 336(%rsp), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl 340(%rsp), %esi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 344(%rsp), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movq 296(%rsp), %rsi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movq 288(%rsp), %rsi
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movq 352(%rsp), %rsi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl 308(%rsp), %esi
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
xorl %eax, %eax
addq $1472, %rsp # imm = 0x5C0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Device Name: %s\n"
.size .L.str.1, 17
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Compute capability: major: %d\tminor: %d\n\n"
.size .L.str.2, 42
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Maximum block dimension in x: %d\n"
.size .L.str.3, 34
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Maximum block dimension in y: %d\n"
.size .L.str.4, 34
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Maximum block dimension in z: %d\n\n"
.size .L.str.5, 35
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Maximum grid dimension in x: %d\n"
.size .L.str.6, 33
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Maximum grid dimension in y: %d\n"
.size .L.str.7, 33
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Maximum grid dimension in z: %d\n\n"
.size .L.str.8, 34
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Shared memory per block: %zu\n"
.size .L.str.9, 30
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Total global memory: %zu\n"
.size .L.str.10, 26
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Total constant memory: %zu\n\n"
.size .L.str.11, 29
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Warp size: %d\n"
.size .L.str.12, 15
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "\n"
.size .Lstr.1, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00048696_00000000-6_q1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n\n"
.LC1:
.string "Device Name: %s\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Compute capability: major: %d\tminor: %d\n\n"
.align 8
.LC3:
.string "Maximum block dimension in x: %d\n"
.align 8
.LC4:
.string "Maximum block dimension in y: %d\n"
.align 8
.LC5:
.string "Maximum block dimension in z: %d\n\n"
.align 8
.LC6:
.string "Maximum grid dimension in x: %d\n"
.align 8
.LC7:
.string "Maximum grid dimension in y: %d\n"
.align 8
.LC8:
.string "Maximum grid dimension in z: %d\n\n"
.section .rodata.str1.1
.LC9:
.string "Shared memory per block: %zu\n"
.LC10:
.string "Total global memory: %zu\n"
.LC11:
.string "Total constant memory: %zu\n\n"
.LC12:
.string "Warp size: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1048, %rsp
.cfi_def_cfa_offset 1072
movq %fs:40, %rax
movq %rax, 1032(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
call __printf_chk@PLT
movq %rsp, %rbp
movl $0, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbp, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 364(%rsp), %ecx
movl 360(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 324(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 328(%rsp), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 332(%rsp), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 340(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 344(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 296(%rsp), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 288(%rsp), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 352(%rsp), %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 308(%rsp), %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $1048, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "q1.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1472, %rsp # imm = 0x5C0
.cfi_def_cfa_offset 1488
.cfi_offset %rbx, -16
movl $.Lstr.1, %edi
callq puts@PLT
movq %rsp, %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 360(%rsp), %esi
movl 364(%rsp), %edx
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl 324(%rsp), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl 328(%rsp), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl 332(%rsp), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 336(%rsp), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl 340(%rsp), %esi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 344(%rsp), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movq 296(%rsp), %rsi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movq 288(%rsp), %rsi
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movq 352(%rsp), %rsi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl 308(%rsp), %esi
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
xorl %eax, %eax
addq $1472, %rsp # imm = 0x5C0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Device Name: %s\n"
.size .L.str.1, 17
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Compute capability: major: %d\tminor: %d\n\n"
.size .L.str.2, 42
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Maximum block dimension in x: %d\n"
.size .L.str.3, 34
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Maximum block dimension in y: %d\n"
.size .L.str.4, 34
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Maximum block dimension in z: %d\n\n"
.size .L.str.5, 35
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Maximum grid dimension in x: %d\n"
.size .L.str.6, 33
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Maximum grid dimension in y: %d\n"
.size .L.str.7, 33
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Maximum grid dimension in z: %d\n\n"
.size .L.str.8, 34
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Shared memory per block: %zu\n"
.size .L.str.9, 30
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Total global memory: %zu\n"
.size .L.str.10, 26
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Total constant memory: %zu\n\n"
.size .L.str.11, 29
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Warp size: %d\n"
.size .L.str.12, 15
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "\n"
.size .Lstr.1, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
__global__ void matmult_gpu1Kernel(int m, int n, int k, double * d_A, double * d_B, double * d_C);
extern "C" {
void matmult_gpu1(int m, int n, int k, double * A, double * B, double * C){
double * d_A, * d_B, * d_C;
cudaMalloc((void **)&d_A, m * k * sizeof(double *));
cudaMalloc((void **)&d_B, k * n * sizeof(double *));
cudaMalloc((void **)&d_C, m * n * sizeof(double *));
cudaMemcpy(d_A, A, m * k * sizeof(double *), cudaMemcpyHostToDevice);
cudaMemcpy(d_B, B, k * n * sizeof(double *), cudaMemcpyHostToDevice);
matmult_gpu1Kernel<<<1,1>>>(m, n, k, d_A, d_B, d_C);
cudaMemcpy(C, d_C, m * n * sizeof(double *), cudaMemcpyDeviceToHost);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
}
}
__global__ void matmult_gpu1Kernel(int m, int n, int k, double * d_A, double * d_B, double * d_C){
int i, j, l;
double x;
for(i=0;i < m; i++){
for(j=0;j<n;j++){
d_C[i*n + j]=0;
}
for(l=0;l < k;l++){
x = d_A[i*k + l];
for(j=0;j < n; j++){
d_C[i*n + j] += x * d_B[l*n + j];
}
}
}
} | code for sm_80
Function : _Z18matmult_gpu1KerneliiiPdS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.LE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f03270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ ISETP.LE.AND P0, PT, R0, c[0x0][0x164], PT ; /* 0x0000590000007a0c */
/* 0x000fda0003f03270 */
/*0050*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff007624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, 0x1 ; /* 0x00000001ff037424 */
/* 0x000fe400078e00ff */
/*0090*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*00a0*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe400078ec0ff */
/*00b0*/ IADD3 R3, -R3, c[0x0][0x164], RZ ; /* 0x0000590003037a10 */
/* 0x000fe40007ffe1ff */
/*00c0*/ IADD3 R4, -R0, c[0x0][0x164], RZ ; /* 0x0000590000047a10 */
/* 0x000fe40007ffe1ff */
/*00d0*/ ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe20003f26070 */
/*00e0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00f0*/ IMAD R5, R2, c[0x0][0x164], RZ ; /* 0x0000590002057a24 */
/* 0x000fd600078e02ff */
/*0100*/ @!P1 BRA 0x520 ; /* 0x0000041000009947 */
/* 0x023fea0003800000 */
/*0110*/ ISETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f04270 */
/*0120*/ HFMA2.MMA R6, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff067435 */
/* 0x000fe200000001ff */
/*0130*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0140*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fd000078e0004 */
/*0150*/ IMAD.WIDE R6, R5, R6, c[0x0][0x180] ; /* 0x0000600005067625 */
/* 0x000fe400078e0206 */
/*0160*/ @!P0 BRA 0x460 ; /* 0x000002f000008947 */
/* 0x000fea0003800000 */
/*0170*/ ISETP.GT.AND P2, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f44270 */
/*0180*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0190*/ @!P2 BRA 0x330 ; /* 0x000001900000a947 */
/* 0x000fea0003800000 */
/*01a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01b0*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fe20007ffe0ff */
/*01c0*/ STG.E.64 [R6.64], RZ ; /* 0x000000ff06007986 */
/* 0x000fe2000c101b06 */
/*01d0*/ IADD3 R9, P3, R6, 0x80, RZ ; /* 0x0000008006097810 */
/* 0x000fe20007f7e0ff */
/*01e0*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*01f0*/ ISETP.GT.AND P2, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe20003f44270 */
/*0200*/ STG.E.64 [R6.64+0x8], RZ ; /* 0x000008ff06007986 */
/* 0x000fe4000c101b06 */
/*0210*/ IMAD.X R10, RZ, RZ, R7, P3 ; /* 0x000000ffff0a7224 */
/* 0x000fe400018e0607 */
/*0220*/ STG.E.64 [R6.64+0x10], RZ ; /* 0x000010ff06007986 */
/* 0x000fe8000c101b06 */
/*0230*/ STG.E.64 [R6.64+0x18], RZ ; /* 0x000018ff06007986 */
/* 0x000fe8000c101b06 */
/*0240*/ STG.E.64 [R6.64+0x20], RZ ; /* 0x000020ff06007986 */
/* 0x000fe8000c101b06 */
/*0250*/ STG.E.64 [R6.64+0x28], RZ ; /* 0x000028ff06007986 */
/* 0x000fe8000c101b06 */
/*0260*/ STG.E.64 [R6.64+0x30], RZ ; /* 0x000030ff06007986 */
/* 0x000fe8000c101b06 */
/*0270*/ STG.E.64 [R6.64+0x38], RZ ; /* 0x000038ff06007986 */
/* 0x000fe8000c101b06 */
/*0280*/ STG.E.64 [R6.64+0x40], RZ ; /* 0x000040ff06007986 */
/* 0x000fe8000c101b06 */
/*0290*/ STG.E.64 [R6.64+0x48], RZ ; /* 0x000048ff06007986 */
/* 0x000fe8000c101b06 */
/*02a0*/ STG.E.64 [R6.64+0x50], RZ ; /* 0x000050ff06007986 */
/* 0x000fe8000c101b06 */
/*02b0*/ STG.E.64 [R6.64+0x58], RZ ; /* 0x000058ff06007986 */
/* 0x000fe8000c101b06 */
/*02c0*/ STG.E.64 [R6.64+0x60], RZ ; /* 0x000060ff06007986 */
/* 0x000fe8000c101b06 */
/*02d0*/ STG.E.64 [R6.64+0x68], RZ ; /* 0x000068ff06007986 */
/* 0x000fe8000c101b06 */
/*02e0*/ STG.E.64 [R6.64+0x70], RZ ; /* 0x000070ff06007986 */
/* 0x000fe8000c101b06 */
/*02f0*/ STG.E.64 [R6.64+0x78], RZ ; /* 0x000078ff06007986 */
/* 0x0001e4000c101b06 */
/*0300*/ IMAD.MOV.U32 R6, RZ, RZ, R9 ; /* 0x000000ffff067224 */
/* 0x001fc400078e0009 */
/*0310*/ IMAD.MOV.U32 R7, RZ, RZ, R10 ; /* 0x000000ffff077224 */
/* 0x000fe200078e000a */
/*0320*/ @P2 BRA 0x1b0 ; /* 0xfffffe8000002947 */
/* 0x000fea000383ffff */
/*0330*/ ISETP.GT.AND P2, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f44270 */
/*0340*/ @!P2 BRA 0x440 ; /* 0x000000f00000a947 */
/* 0x000fea0003800000 */
/*0350*/ IADD3 R9, P2, R6, 0x40, RZ ; /* 0x0000004006097810 */
/* 0x000fe20007f5e0ff */
/*0360*/ STG.E.64 [R6.64], RZ ; /* 0x000000ff06007986 */
/* 0x000fe2000c101b06 */
/*0370*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0380*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0390*/ IADD3.X R10, RZ, R7, RZ, P2, !PT ; /* 0x00000007ff0a7210 */
/* 0x000fe200017fe4ff */
/*03a0*/ STG.E.64 [R6.64+0x8], RZ ; /* 0x000008ff06007986 */
/* 0x000fe2000c101b06 */
/*03b0*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fc60007ffe0ff */
/*03c0*/ STG.E.64 [R6.64+0x10], RZ ; /* 0x000010ff06007986 */
/* 0x000fe8000c101b06 */
/*03d0*/ STG.E.64 [R6.64+0x18], RZ ; /* 0x000018ff06007986 */
/* 0x000fe8000c101b06 */
/*03e0*/ STG.E.64 [R6.64+0x20], RZ ; /* 0x000020ff06007986 */
/* 0x000fe8000c101b06 */
/*03f0*/ STG.E.64 [R6.64+0x28], RZ ; /* 0x000028ff06007986 */
/* 0x000fe8000c101b06 */
/*0400*/ STG.E.64 [R6.64+0x30], RZ ; /* 0x000030ff06007986 */
/* 0x000fe8000c101b06 */
/*0410*/ STG.E.64 [R6.64+0x38], RZ ; /* 0x000038ff06007986 */
/* 0x0001e4000c101b06 */
/*0420*/ IMAD.MOV.U32 R6, RZ, RZ, R9 ; /* 0x000000ffff067224 */
/* 0x001fc400078e0009 */
/*0430*/ IMAD.MOV.U32 R7, RZ, RZ, R10 ; /* 0x000000ffff077224 */
/* 0x000fe400078e000a */
/*0440*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*0450*/ @!P0 BRA 0x520 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0460*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe20007ffe0ff */
/*0470*/ STG.E.64 [R6.64], RZ ; /* 0x000000ff06007986 */
/* 0x000fe2000c101b06 */
/*0480*/ IADD3 R9, P2, R6, 0x20, RZ ; /* 0x0000002006097810 */
/* 0x000fe20007f5e0ff */
/*0490*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*04a0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*04b0*/ STG.E.64 [R6.64+0x8], RZ ; /* 0x000008ff06007986 */
/* 0x000fe4000c101b06 */
/*04c0*/ IMAD.X R10, RZ, RZ, R7, P2 ; /* 0x000000ffff0a7224 */
/* 0x000fe400010e0607 */
/*04d0*/ STG.E.64 [R6.64+0x10], RZ ; /* 0x000010ff06007986 */
/* 0x000fe8000c101b06 */
/*04e0*/ STG.E.64 [R6.64+0x18], RZ ; /* 0x000018ff06007986 */
/* 0x0001e4000c101b06 */
/*04f0*/ IMAD.MOV.U32 R6, RZ, RZ, R9 ; /* 0x000000ffff067224 */
/* 0x001fe200078e0009 */
/*0500*/ MOV R7, R10 ; /* 0x0000000a00077202 */
/* 0x000fe20000000f00 */
/*0510*/ @P0 BRA 0x460 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*0520*/ ISETP.NE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f45270 */
/*0530*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff067624 */
/* 0x000fca00078e00ff */
/*0540*/ ISETP.GE.AND P3, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fce0003f66270 */
/*0550*/ @!P2 BRA 0x5f0 ; /* 0x000000900000a947 */
/* 0x000fec0003800000 */
/*0560*/ ISETP.NE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f05270 */
/*0570*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fe200078e00ff */
/*0580*/ IADD3 R6, R5, UR4, RZ ; /* 0x0000000405067c10 */
/* 0x000fca000fffe0ff */
/*0590*/ IMAD.WIDE R6, R6, R7, c[0x0][0x180] ; /* 0x0000600006067625 */
/* 0x000fca00078e0207 */
/*05a0*/ STG.E.64 [R6.64], RZ ; /* 0x000000ff06007986 */
/* 0x0001e2000c101b06 */
/*05b0*/ @!P0 BRA 0x5f0 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*05c0*/ ISETP.NE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f05270 */
/*05d0*/ STG.E.64 [R6.64+0x8], RZ ; /* 0x000008ff06007986 */
/* 0x0003d8000c101b06 */
/*05e0*/ @P0 STG.E.64 [R6.64+0x10], RZ ; /* 0x000010ff06000986 */
/* 0x0003e4000c101b06 */
/*05f0*/ @!P3 BRA 0x1270 ; /* 0x00000c700000b947 */
/* 0x000fea0003800000 */
/*0600*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x003fe400078e00ff */
/*0610*/ IMAD.MOV.U32 R6, RZ, RZ, 0x8 ; /* 0x00000008ff067424 */
/* 0x000fe400078e00ff */
/*0620*/ IMAD R11, R2, c[0x0][0x168], R7 ; /* 0x00005a00020b7a24 */
/* 0x020fc800078e0207 */
/*0630*/ IMAD.WIDE R10, R11, R6, c[0x0][0x170] ; /* 0x00005c000b0a7625 */
/* 0x000fe200078e0206 */
/*0640*/ MOV R8, R7 ; /* 0x0000000700087202 */
/* 0x000fe40000000f00 */
/*0650*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fc60007ffe0ff */
/*0660*/ LDG.E.64 R10, [R10.64] ; /* 0x000000060a0a7981 */
/* 0x000f62000c1e1b00 */
/*0670*/ ISETP.GE.AND P3, PT, R7, c[0x0][0x168], PT ; /* 0x00005a0007007a0c */
/* 0x000fe20003f66270 */
/*0680*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0690*/ @!P1 BRA 0x1110 ; /* 0x00000a7000009947 */
/* 0x003fec0003800000 */
/*06a0*/ ISETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f04270 */
/*06b0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe400078e00ff */
/*06c0*/ IMAD.MOV.U32 R22, RZ, RZ, R4 ; /* 0x000000ffff167224 */
/* 0x000fd400078e0004 */
/*06d0*/ @!P0 BRA 0xf90 ; /* 0x000008b000008947 */
/* 0x000fea0003800000 */
/*06e0*/ ISETP.GT.AND P4, PT, R22, 0xc, PT ; /* 0x0000000c1600780c */
/* 0x000fe40003f84270 */
/*06f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0700*/ @!P4 BRA 0xc90 ; /* 0x000005800000c947 */
/* 0x000fea0003800000 */
/*0710*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0720*/ IMAD R19, R8, c[0x0][0x164], R9.reuse ; /* 0x0000590008137a24 */
/* 0x100fe400078e0209 */
/*0730*/ IMAD.IADD R29, R5, 0x1, R9 ; /* 0x00000001051d7824 */
/* 0x000fe400078e0209 */
/*0740*/ IMAD.WIDE R18, R19, R6, c[0x0][0x178] ; /* 0x00005e0013127625 */
/* 0x000fc800078e0206 */
/*0750*/ IMAD.WIDE R28, R29, R6, c[0x0][0x180] ; /* 0x000060001d1c7625 */
/* 0x000fe200078e0206 */
/*0760*/ LDG.E.64 R12, [R18.64] ; /* 0x00000006120c7981 */
/* 0x002ea8000c1e1b00 */
/*0770*/ LDG.E.64 R16, [R28.64] ; /* 0x000000061c107981 */
/* 0x000ea8000c1e1b00 */
/*0780*/ LDG.E.64 R20, [R28.64+0x8] ; /* 0x000008061c147981 */
/* 0x000ee8000c1e1b00 */
/*0790*/ LDG.E.64 R14, [R28.64+0x10] ; /* 0x000010061c0e7981 */
/* 0x000f28000c1e1b00 */
/*07a0*/ LDG.E.64 R24, [R28.64+0x18] ; /* 0x000018061c187981 */
/* 0x000ee2000c1e1b00 */
/*07b0*/ DFMA R16, R10, R12, R16 ; /* 0x0000000c0a10722b */
/* 0x024e0e0000000010 */
/*07c0*/ STG.E.64 [R28.64], R16 ; /* 0x000000101c007986 */
/* 0x0011e8000c101b06 */
/*07d0*/ LDG.E.64 R12, [R18.64+0x8] ; /* 0x00000806120c7981 */
/* 0x000ee4000c1e1b00 */
/*07e0*/ DFMA R20, R10, R12, R20 ; /* 0x0000000c0a14722b */
/* 0x008e4e0000000014 */
/*07f0*/ STG.E.64 [R28.64+0x8], R20 ; /* 0x000008141c007986 */
/* 0x0023e8000c101b06 */
/*0800*/ LDG.E.64 R12, [R18.64+0x10] ; /* 0x00001006120c7981 */
/* 0x000f24000c1e1b00 */
/*0810*/ DFMA R14, R10, R12, R14 ; /* 0x0000000c0a0e722b */
/* 0x010e8e000000000e */
/*0820*/ STG.E.64 [R28.64+0x10], R14 ; /* 0x0000100e1c007986 */
/* 0x0045e8000c101b06 */
/*0830*/ LDG.E.64 R12, [R18.64+0x18] ; /* 0x00001806120c7981 */
/* 0x000ee2000c1e1b00 */
/*0840*/ IADD3 R23, R9, 0x4, RZ ; /* 0x0000000409177810 */
/* 0x000fc80007ffe0ff */
/*0850*/ IADD3 R27, R5, R23, RZ ; /* 0x00000017051b7210 */
/* 0x000fe20007ffe0ff */
/*0860*/ IMAD R17, R8, c[0x0][0x164], R23 ; /* 0x0000590008117a24 */
/* 0x001fc800078e0217 */
/*0870*/ IMAD.WIDE R16, R17, R6, c[0x0][0x178] ; /* 0x00005e0011107625 */
/* 0x000fc800078e0206 */
/*0880*/ IMAD.WIDE R26, R27, R6, c[0x0][0x180] ; /* 0x000060001b1a7625 */
/* 0x000fe200078e0206 */
/*0890*/ DFMA R24, R10, R12, R24 ; /* 0x0000000c0a18722b */
/* 0x008e0e0000000018 */
/*08a0*/ STG.E.64 [R28.64+0x18], R24 ; /* 0x000018181c007986 */
/* 0x0011e8000c101b06 */
/*08b0*/ LDG.E.64 R12, [R16.64] ; /* 0x00000006100c7981 */
/* 0x000ee8000c1e1b00 */
/*08c0*/ LDG.E.64 R20, [R26.64] ; /* 0x000000061a147981 */
/* 0x002ee8000c1e1b00 */
/*08d0*/ LDG.E.64 R18, [R26.64+0x8] ; /* 0x000008061a127981 */
/* 0x000f28000c1e1b00 */
/*08e0*/ LDG.E.64 R14, [R26.64+0x10] ; /* 0x000010061a0e7981 */
/* 0x004ea8000c1e1b00 */
/*08f0*/ LDG.E.64 R24, [R26.64+0x18] ; /* 0x000018061a187981 */
/* 0x001ea2000c1e1b00 */
/*0900*/ DFMA R20, R10, R12, R20 ; /* 0x0000000c0a14722b */
/* 0x008e0e0000000014 */
/*0910*/ STG.E.64 [R26.64], R20 ; /* 0x000000141a007986 */
/* 0x0011e8000c101b06 */
/*0920*/ LDG.E.64 R12, [R16.64+0x8] ; /* 0x00000806100c7981 */
/* 0x000f24000c1e1b00 */
/*0930*/ DFMA R18, R10, R12, R18 ; /* 0x0000000c0a12722b */
/* 0x010e4e0000000012 */
/*0940*/ STG.E.64 [R26.64+0x8], R18 ; /* 0x000008121a007986 */
/* 0x0023e8000c101b06 */
/*0950*/ LDG.E.64 R12, [R16.64+0x10] ; /* 0x00001006100c7981 */
/* 0x000ea4000c1e1b00 */
/*0960*/ DFMA R14, R10, R12, R14 ; /* 0x0000000c0a0e722b */
/* 0x004e8e000000000e */
/*0970*/ STG.E.64 [R26.64+0x10], R14 ; /* 0x0000100e1a007986 */
/* 0x0045e8000c101b06 */
/*0980*/ LDG.E.64 R12, [R16.64+0x18] ; /* 0x00001806100c7981 */
/* 0x000ee2000c1e1b00 */
/*0990*/ IADD3 R23, R9, 0x8, RZ ; /* 0x0000000809177810 */
/* 0x000fca0007ffe0ff */
/*09a0*/ IMAD R21, R8, c[0x0][0x164], R23.reuse ; /* 0x0000590008157a24 */
/* 0x101fe400078e0217 */
/*09b0*/ IMAD.IADD R29, R5, 0x1, R23 ; /* 0x00000001051d7824 */
/* 0x000fe400078e0217 */
/*09c0*/ IMAD.WIDE R20, R21, R6, c[0x0][0x178] ; /* 0x00005e0015147625 */
/* 0x000fc800078e0206 */
/*09d0*/ IMAD.WIDE R28, R29, R6, c[0x0][0x180] ; /* 0x000060001d1c7625 */
/* 0x000fe200078e0206 */
/*09e0*/ DFMA R24, R10, R12, R24 ; /* 0x0000000c0a18722b */
/* 0x008e0e0000000018 */
/*09f0*/ STG.E.64 [R26.64+0x18], R24 ; /* 0x000018181a007986 */
/* 0x0011e8000c101b06 */
/*0a00*/ LDG.E.64 R12, [R20.64] ; /* 0x00000006140c7981 */
/* 0x000ee8000c1e1b00 */
/*0a10*/ LDG.E.64 R18, [R28.64] ; /* 0x000000061c127981 */
/* 0x002ee8000c1e1b00 */
/*0a20*/ LDG.E.64 R14, [R28.64+0x8] ; /* 0x000008061c0e7981 */
/* 0x004ea8000c1e1b00 */
/*0a30*/ LDG.E.64 R16, [R28.64+0x10] ; /* 0x000010061c107981 */
/* 0x000f28000c1e1b00 */
/*0a40*/ LDG.E.64 R26, [R28.64+0x18] ; /* 0x000018061c1a7981 */
/* 0x001ea2000c1e1b00 */
/*0a50*/ DFMA R18, R10, R12, R18 ; /* 0x0000000c0a12722b */
/* 0x008e0e0000000012 */
/*0a60*/ STG.E.64 [R28.64], R18 ; /* 0x000000121c007986 */
/* 0x0011e8000c101b06 */
/*0a70*/ LDG.E.64 R12, [R20.64+0x8] ; /* 0x00000806140c7981 */
/* 0x000ea4000c1e1b00 */
/*0a80*/ DFMA R14, R10, R12, R14 ; /* 0x0000000c0a0e722b */
/* 0x004e4e000000000e */
/*0a90*/ STG.E.64 [R28.64+0x8], R14 ; /* 0x0000080e1c007986 */
/* 0x0023e8000c101b06 */
/*0aa0*/ LDG.E.64 R12, [R20.64+0x10] ; /* 0x00001006140c7981 */
/* 0x000f24000c1e1b00 */
/*0ab0*/ DFMA R16, R10, R12, R16 ; /* 0x0000000c0a10722b */
/* 0x010e8e0000000010 */
/*0ac0*/ STG.E.64 [R28.64+0x10], R16 ; /* 0x000010101c007986 */
/* 0x0045e8000c101b06 */
/*0ad0*/ LDG.E.64 R12, [R20.64+0x18] ; /* 0x00001806140c7981 */
/* 0x000ee2000c1e1b00 */
/*0ae0*/ IADD3 R23, R9, 0xc, RZ ; /* 0x0000000c09177810 */
/* 0x000fca0007ffe0ff */
/*0af0*/ IMAD R19, R8, c[0x0][0x164], R23.reuse ; /* 0x0000590008137a24 */
/* 0x101fe400078e0217 */
/*0b00*/ IMAD.IADD R23, R5, 0x1, R23 ; /* 0x0000000105177824 */
/* 0x000fe400078e0217 */
/*0b10*/ IMAD.WIDE R18, R19, R6, c[0x0][0x178] ; /* 0x00005e0013127625 */
/* 0x000fe200078e0206 */
/*0b20*/ DFMA R26, R10, R12, R26 ; /* 0x0000000c0a1a722b */
/* 0x0080c6000000001a */
/*0b30*/ IMAD.WIDE R12, R23, R6, c[0x0][0x180] ; /* 0x00006000170c7625 */
/* 0x001fc800078e0206 */
/*0b40*/ STG.E.64 [R28.64+0x18], R26 ; /* 0x0000181a1c007986 */
/* 0x0081e8000c101b06 */
/*0b50*/ LDG.E.64 R14, [R18.64] ; /* 0x00000006120e7981 */
/* 0x002ee8000c1e1b00 */
/*0b60*/ LDG.E.64 R24, [R12.64] ; /* 0x000000060c187981 */
/* 0x000ee8000c1e1b00 */
/*0b70*/ LDG.E.64 R20, [R12.64+0x8] ; /* 0x000008060c147981 */
/* 0x000f22000c1e1b00 */
/*0b80*/ DFMA R24, R10, R14, R24 ; /* 0x0000000e0a18722b */
/* 0x008e4e0000000018 */
/*0b90*/ STG.E.64 [R12.64], R24 ; /* 0x000000180c007986 */
/* 0x0023e8000c101b06 */
/*0ba0*/ LDG.E.64 R14, [R18.64+0x8] ; /* 0x00000806120e7981 */
/* 0x000f24000c1e1b00 */
/*0bb0*/ DFMA R20, R10.reuse, R14, R20 ; /* 0x0000000e0a14722b */
/* 0x0507240000000014 */
/*0bc0*/ LDG.E.64 R14, [R12.64+0x10] ; /* 0x000010060c0e7981 */
/* 0x008eea000c1e1b00 */
/*0bd0*/ STG.E.64 [R12.64+0x8], R20 ; /* 0x000008140c007986 */
/* 0x0103e8000c101b06 */
/*0be0*/ LDG.E.64 R16, [R18.64+0x10] ; /* 0x0000100612107981 */
/* 0x004ee2000c1e1b00 */
/*0bf0*/ IADD3 R22, R22, -0x10, RZ ; /* 0xfffffff016167810 */
/* 0x000fe20007ffe0ff */
/*0c00*/ DFMA R14, R10, R16, R14 ; /* 0x000000100a0e722b */
/* 0x0084c4000000000e */
/*0c10*/ LDG.E.64 R16, [R12.64+0x18] ; /* 0x000018060c107981 */
/* 0x004eaa000c1e1b00 */
/*0c20*/ STG.E.64 [R12.64+0x10], R14 ; /* 0x0000100e0c007986 */
/* 0x0083e8000c101b06 */
/*0c30*/ LDG.E.64 R26, [R18.64+0x18] ; /* 0x00001806121a7981 */
/* 0x001ea2000c1e1b00 */
/*0c40*/ ISETP.GT.AND P4, PT, R22, 0xc, PT ; /* 0x0000000c1600780c */
/* 0x000fc40003f84270 */
/*0c50*/ IADD3 R9, R9, 0x10, RZ ; /* 0x0000001009097810 */
/* 0x000fe20007ffe0ff */
/*0c60*/ DFMA R16, R10, R26, R16 ; /* 0x0000001a0a10722b */
/* 0x004e0e0000000010 */
/*0c70*/ STG.E.64 [R12.64+0x18], R16 ; /* 0x000018100c007986 */
/* 0x0013e6000c101b06 */
/*0c80*/ @P4 BRA 0x720 ; /* 0xfffffa9000004947 */
/* 0x000fea000383ffff */
/*0c90*/ ISETP.GT.AND P4, PT, R22, 0x4, PT ; /* 0x000000041600780c */
/* 0x000fda0003f84270 */
/*0ca0*/ @!P4 BRA 0xf70 ; /* 0x000002c00000c947 */
/* 0x000fea0003800000 */
/*0cb0*/ IMAD R21, R8, c[0x0][0x164], R9.reuse ; /* 0x0000590008157a24 */
/* 0x102fe400078e0209 */
/*0cc0*/ IMAD.IADD R29, R5, 0x1, R9 ; /* 0x00000001051d7824 */
/* 0x000fe400078e0209 */
/*0cd0*/ IMAD.WIDE R20, R21, R6, c[0x0][0x178] ; /* 0x00005e0015147625 */
/* 0x000fc800078e0206 */
/*0ce0*/ IMAD.WIDE R28, R29, R6, c[0x0][0x180] ; /* 0x000060001d1c7625 */
/* 0x000fe200078e0206 */
/*0cf0*/ LDG.E.64 R12, [R20.64] ; /* 0x00000006140c7981 */
/* 0x000ea8000c1e1b00 */
/*0d00*/ LDG.E.64 R14, [R28.64] ; /* 0x000000061c0e7981 */
/* 0x000ea8000c1e1b00 */
/*0d10*/ LDG.E.64 R16, [R28.64+0x8] ; /* 0x000008061c107981 */
/* 0x000ee8000c1e1b00 */
/*0d20*/ LDG.E.64 R18, [R28.64+0x10] ; /* 0x000010061c127981 */
/* 0x000f28000c1e1b00 */
/*0d30*/ LDG.E.64 R26, [R28.64+0x18] ; /* 0x000018061c1a7981 */
/* 0x000ee2000c1e1b00 */
/*0d40*/ DFMA R14, R10, R12, R14 ; /* 0x0000000c0a0e722b */
/* 0x024e0e000000000e */
/*0d50*/ STG.E.64 [R28.64], R14 ; /* 0x0000000e1c007986 */
/* 0x0011e8000c101b06 */
/*0d60*/ LDG.E.64 R12, [R20.64+0x8] ; /* 0x00000806140c7981 */
/* 0x000ee4000c1e1b00 */
/*0d70*/ DFMA R16, R10, R12, R16 ; /* 0x0000000c0a10722b */
/* 0x008e4e0000000010 */
/*0d80*/ STG.E.64 [R28.64+0x8], R16 ; /* 0x000008101c007986 */
/* 0x0023e8000c101b06 */
/*0d90*/ LDG.E.64 R12, [R20.64+0x10] ; /* 0x00001006140c7981 */
/* 0x000f24000c1e1b00 */
/*0da0*/ DFMA R18, R10, R12, R18 ; /* 0x0000000c0a12722b */
/* 0x010e8e0000000012 */
/*0db0*/ STG.E.64 [R28.64+0x10], R18 ; /* 0x000010121c007986 */
/* 0x0045e8000c101b06 */
/*0dc0*/ LDG.E.64 R12, [R20.64+0x18] ; /* 0x00001806140c7981 */
/* 0x000ee2000c1e1b00 */
/*0dd0*/ IADD3 R23, R9, 0x4, RZ ; /* 0x0000000409177810 */
/* 0x000fca0007ffe0ff */
/*0de0*/ IMAD R15, R8, c[0x0][0x164], R23 ; /* 0x00005900080f7a24 */
/* 0x001fe200078e0217 */
/*0df0*/ IADD3 R23, R5, R23, RZ ; /* 0x0000001705177210 */
/* 0x000fc60007ffe0ff */
/*0e00*/ IMAD.WIDE R14, R15, R6, c[0x0][0x178] ; /* 0x00005e000f0e7625 */
/* 0x000fe200078e0206 */
/*0e10*/ DFMA R26, R10, R12, R26 ; /* 0x0000000c0a1a722b */
/* 0x0080c6000000001a */
/*0e20*/ IMAD.WIDE R12, R23, R6, c[0x0][0x180] ; /* 0x00006000170c7625 */
/* 0x001fc800078e0206 */
/*0e30*/ STG.E.64 [R28.64+0x18], R26 ; /* 0x0000181a1c007986 */
/* 0x0081e8000c101b06 */
/*0e40*/ LDG.E.64 R16, [R14.64] ; /* 0x000000060e107981 */
/* 0x002ee8000c1e1b00 */
/*0e50*/ LDG.E.64 R24, [R12.64] ; /* 0x000000060c187981 */
/* 0x000ee8000c1e1b00 */
/*0e60*/ LDG.E.64 R18, [R12.64+0x8] ; /* 0x000008060c127981 */
/* 0x004ea2000c1e1b00 */
/*0e70*/ DFMA R24, R10, R16, R24 ; /* 0x000000100a18722b */
/* 0x008e4e0000000018 */
/*0e80*/ STG.E.64 [R12.64], R24 ; /* 0x000000180c007986 */
/* 0x0023e8000c101b06 */
/*0e90*/ LDG.E.64 R16, [R14.64+0x8] ; /* 0x000008060e107981 */
/* 0x000ea4000c1e1b00 */
/*0ea0*/ DFMA R18, R10.reuse, R16, R18 ; /* 0x000000100a12722b */
/* 0x0444e40000000012 */
/*0eb0*/ LDG.E.64 R16, [R12.64+0x10] ; /* 0x000010060c107981 */
/* 0x004eaa000c1e1b00 */
/*0ec0*/ STG.E.64 [R12.64+0x8], R18 ; /* 0x000008120c007986 */
/* 0x0083e8000c101b06 */
/*0ed0*/ LDG.E.64 R20, [R14.64+0x10] ; /* 0x000010060e147981 */
/* 0x000ea4000c1e1b00 */
/*0ee0*/ DFMA R16, R10, R20, R16 ; /* 0x000000140a10722b */
/* 0x0044c40000000010 */
/*0ef0*/ LDG.E.64 R20, [R12.64+0x18] ; /* 0x000018060c147981 */
/* 0x004eaa000c1e1b00 */
/*0f00*/ STG.E.64 [R12.64+0x10], R16 ; /* 0x000010100c007986 */
/* 0x0083e8000c101b06 */
/*0f10*/ LDG.E.64 R26, [R14.64+0x18] ; /* 0x000018060e1a7981 */
/* 0x001ea2000c1e1b00 */
/*0f20*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0f30*/ IADD3 R22, R22, -0x8, RZ ; /* 0xfffffff816167810 */
/* 0x000fe40007ffe0ff */
/*0f40*/ IADD3 R9, R9, 0x8, RZ ; /* 0x0000000809097810 */
/* 0x000fe20007ffe0ff */
/*0f50*/ DFMA R20, R10, R26, R20 ; /* 0x0000001a0a14722b */
/* 0x004e0e0000000014 */
/*0f60*/ STG.E.64 [R12.64+0x18], R20 ; /* 0x000018140c007986 */
/* 0x0013e8000c101b06 */
/*0f70*/ ISETP.NE.OR P0, PT, R22, RZ, P0 ; /* 0x000000ff1600720c */
/* 0x000fda0000705670 */
/*0f80*/ @!P0 BRA 0x1110 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0f90*/ IMAD R15, R8, c[0x0][0x164], R9.reuse ; /* 0x00005900080f7a24 */
/* 0x102fe400078e0209 */
/*0fa0*/ IMAD.IADD R13, R5, 0x1, R9 ; /* 0x00000001050d7824 */
/* 0x000fe400078e0209 */
/*0fb0*/ IMAD.WIDE R14, R15, R6, c[0x0][0x178] ; /* 0x00005e000f0e7625 */
/* 0x000fc800078e0206 */
/*0fc0*/ IMAD.WIDE R12, R13, R6, c[0x0][0x180] ; /* 0x000060000d0c7625 */
/* 0x000fe200078e0206 */
/*0fd0*/ LDG.E.64 R16, [R14.64] ; /* 0x000000060e107981 */
/* 0x000ea8000c1e1b00 */
/*0fe0*/ LDG.E.64 R24, [R12.64] ; /* 0x000000060c187981 */
/* 0x000ea8000c1e1b00 */
/*0ff0*/ LDG.E.64 R20, [R12.64+0x8] ; /* 0x000008060c147981 */
/* 0x000ee8000c1e1b00 */
/*1000*/ LDG.E.64 R18, [R12.64+0x10] ; /* 0x000010060c127981 */
/* 0x000f22000c1e1b00 */
/*1010*/ DFMA R24, R10, R16, R24 ; /* 0x000000100a18722b */
/* 0x024e0e0000000018 */
/*1020*/ STG.E.64 [R12.64], R24 ; /* 0x000000180c007986 */
/* 0x0011e8000c101b06 */
/*1030*/ LDG.E.64 R16, [R14.64+0x8] ; /* 0x000008060e107981 */
/* 0x000ee4000c1e1b00 */
/*1040*/ DFMA R20, R10, R16, R20 ; /* 0x000000100a14722b */
/* 0x008e4e0000000014 */
/*1050*/ STG.E.64 [R12.64+0x8], R20 ; /* 0x000008140c007986 */
/* 0x0021e8000c101b06 */
/*1060*/ LDG.E.64 R16, [R14.64+0x10] ; /* 0x000010060e107981 */
/* 0x000f22000c1e1b00 */
/*1070*/ IADD3 R22, R22, -0x4, RZ ; /* 0xfffffffc16167810 */
/* 0x000fe20007ffe0ff */
/*1080*/ DFMA R18, R10, R16, R18 ; /* 0x000000100a12722b */
/* 0x0102a40000000012 */
/*1090*/ LDG.E.64 R16, [R12.64+0x18] ; /* 0x000018060c107981 */
/* 0x002eea000c1e1b00 */
/*10a0*/ STG.E.64 [R12.64+0x10], R18 ; /* 0x000010120c007986 */
/* 0x0041e8000c101b06 */
/*10b0*/ LDG.E.64 R26, [R14.64+0x18] ; /* 0x000018060e1a7981 */
/* 0x000ee2000c1e1b00 */
/*10c0*/ ISETP.NE.AND P0, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fc40003f05270 */
/*10d0*/ IADD3 R9, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe20007ffe0ff */
/*10e0*/ DFMA R16, R10, R26, R16 ; /* 0x0000001a0a10722b */
/* 0x008e4e0000000010 */
/*10f0*/ STG.E.64 [R12.64+0x18], R16 ; /* 0x000018100c007986 */
/* 0x0021e6000c101b06 */
/*1100*/ @P0 BRA 0xf90 ; /* 0xfffffe8000000947 */
/* 0x001fea000383ffff */
/*1110*/ @!P2 BRA 0x1260 ; /* 0x000001400000a947 */
/* 0x000fea0003800000 */
/*1120*/ IMAD R13, R8, c[0x0][0x164], R9.reuse ; /* 0x00005900080d7a24 */
/* 0x102fe400078e0209 */
/*1130*/ IMAD.IADD R15, R5, 0x1, R9 ; /* 0x00000001050f7824 */
/* 0x000fe400078e0209 */
/*1140*/ IMAD.WIDE R8, R13, R6, c[0x0][0x178] ; /* 0x00005e000d087625 */
/* 0x000fc800078e0206 */
/*1150*/ IMAD.WIDE R12, R15, R6, c[0x0][0x180] ; /* 0x000060000f0c7625 */
/* 0x000fe400078e0206 */
/*1160*/ LDG.E.64 R14, [R8.64] ; /* 0x00000006080e7981 */
/* 0x000ea8000c1e1b00 */
/*1170*/ LDG.E.64 R16, [R12.64] ; /* 0x000000060c107981 */
/* 0x000ea2000c1e1b00 */
/*1180*/ ISETP.NE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f05270 */
/*1190*/ DFMA R14, R10, R14, R16 ; /* 0x0000000e0a0e722b */
/* 0x024e0e0000000010 */
/*11a0*/ STG.E.64 [R12.64], R14 ; /* 0x0000000e0c007986 */
/* 0x0011ea000c101b06 */
/*11b0*/ @!P0 BRA 0x1260 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*11c0*/ LDG.E.64 R14, [R8.64+0x8] ; /* 0x00000806080e7981 */
/* 0x001ea8000c1e1b00 */
/*11d0*/ LDG.E.64 R16, [R12.64+0x8] ; /* 0x000008060c107981 */
/* 0x000ea2000c1e1b00 */
/*11e0*/ ISETP.NE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f05270 */
/*11f0*/ DFMA R14, R10, R14, R16 ; /* 0x0000000e0a0e722b */
/* 0x004e0e0000000010 */
/*1200*/ STG.E.64 [R12.64+0x8], R14 ; /* 0x0000080e0c007986 */
/* 0x0011ea000c101b06 */
/*1210*/ @!P0 BRA 0x1260 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*1220*/ LDG.E.64 R8, [R8.64+0x10] ; /* 0x0000100608087981 */
/* 0x000ea8000c1e1b00 */
/*1230*/ LDG.E.64 R14, [R12.64+0x10] ; /* 0x000010060c0e7981 */
/* 0x001ea4000c1e1b00 */
/*1240*/ DFMA R14, R10, R8, R14 ; /* 0x000000080a0e722b */
/* 0x004e0e000000000e */
/*1250*/ STG.E.64 [R12.64+0x10], R14 ; /* 0x0000100e0c007986 */
/* 0x0011e8000c101b06 */
/*1260*/ @!P3 BRA 0x610 ; /* 0xfffff3a00000b947 */
/* 0x000fea000383ffff */
/*1270*/ IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x000fc80007ffe0ff */
/*1280*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06270 */
/*1290*/ @P0 CALL.REL.NOINC 0x12b0 ; /* 0x0000001000000944 */
/* 0x000fe20003c00000 */
/*12a0*/ BRA 0xd0 ; /* 0xffffee2000007947 */
/* 0x000fea000383ffff */
/*12b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*12c0*/ BRA 0x12c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*12d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
__global__ void matmult_gpu1Kernel(int m, int n, int k, double * d_A, double * d_B, double * d_C);
extern "C" {
void matmult_gpu1(int m, int n, int k, double * A, double * B, double * C){
double * d_A, * d_B, * d_C;
cudaMalloc((void **)&d_A, m * k * sizeof(double *));
cudaMalloc((void **)&d_B, k * n * sizeof(double *));
cudaMalloc((void **)&d_C, m * n * sizeof(double *));
cudaMemcpy(d_A, A, m * k * sizeof(double *), cudaMemcpyHostToDevice);
cudaMemcpy(d_B, B, k * n * sizeof(double *), cudaMemcpyHostToDevice);
matmult_gpu1Kernel<<<1,1>>>(m, n, k, d_A, d_B, d_C);
cudaMemcpy(C, d_C, m * n * sizeof(double *), cudaMemcpyDeviceToHost);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
}
}
__global__ void matmult_gpu1Kernel(int m, int n, int k, double * d_A, double * d_B, double * d_C){
int i, j, l;
double x;
for(i=0;i < m; i++){
for(j=0;j<n;j++){
d_C[i*n + j]=0;
}
for(l=0;l < k;l++){
x = d_A[i*k + l];
for(j=0;j < n; j++){
d_C[i*n + j] += x * d_B[l*n + j];
}
}
}
} | .file "tmpxft_0011ba8f_00000000-6_matmult_gpu1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z18matmult_gpu1KerneliiiPdS_S_iiiPdS_S_
.type _Z45__device_stub__Z18matmult_gpu1KerneliiiPdS_S_iiiPdS_S_, @function
_Z45__device_stub__Z18matmult_gpu1KerneliiiPdS_S_iiiPdS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18matmult_gpu1KerneliiiPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z45__device_stub__Z18matmult_gpu1KerneliiiPdS_S_iiiPdS_S_, .-_Z45__device_stub__Z18matmult_gpu1KerneliiiPdS_S_iiiPdS_S_
.globl _Z18matmult_gpu1KerneliiiPdS_S_
.type _Z18matmult_gpu1KerneliiiPdS_S_, @function
_Z18matmult_gpu1KerneliiiPdS_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z18matmult_gpu1KerneliiiPdS_S_iiiPdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z18matmult_gpu1KerneliiiPdS_S_, .-_Z18matmult_gpu1KerneliiiPdS_S_
.globl matmult_gpu1
.type matmult_gpu1, @function
matmult_gpu1:
.LFB2027:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movl %edi, %r13d
movl %esi, %r14d
movl %edx, %r15d
movq %rcx, 8(%rsp)
movq %r8, 16(%rsp)
movq %r9, 24(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl %edi, %r12d
imull %edx, %r12d
movslq %r12d, %r12
salq $3, %r12
leaq 40(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl %r15d, %ebp
imull %r14d, %ebp
movslq %ebp, %rbp
salq $3, %rbp
leaq 48(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %r13d, %ebx
imull %r14d, %ebx
movslq %ebx, %rbx
salq $3, %rbx
leaq 56(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq 8(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 16(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %rbx, %rdx
movq 56(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 56(%rsp), %r9
movq 48(%rsp), %r8
movq 40(%rsp), %rcx
movl %r15d, %edx
movl %r14d, %esi
movl %r13d, %edi
call _Z45__device_stub__Z18matmult_gpu1KerneliiiPdS_S_iiiPdS_S_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size matmult_gpu1, .-matmult_gpu1
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18matmult_gpu1KerneliiiPdS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18matmult_gpu1KerneliiiPdS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
__global__ void matmult_gpu1Kernel(int m, int n, int k, double * d_A, double * d_B, double * d_C);
extern "C" {
void matmult_gpu1(int m, int n, int k, double * A, double * B, double * C){
double * d_A, * d_B, * d_C;
cudaMalloc((void **)&d_A, m * k * sizeof(double *));
cudaMalloc((void **)&d_B, k * n * sizeof(double *));
cudaMalloc((void **)&d_C, m * n * sizeof(double *));
cudaMemcpy(d_A, A, m * k * sizeof(double *), cudaMemcpyHostToDevice);
cudaMemcpy(d_B, B, k * n * sizeof(double *), cudaMemcpyHostToDevice);
matmult_gpu1Kernel<<<1,1>>>(m, n, k, d_A, d_B, d_C);
cudaMemcpy(C, d_C, m * n * sizeof(double *), cudaMemcpyDeviceToHost);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
}
}
__global__ void matmult_gpu1Kernel(int m, int n, int k, double * d_A, double * d_B, double * d_C){
int i, j, l;
double x;
for(i=0;i < m; i++){
for(j=0;j<n;j++){
d_C[i*n + j]=0;
}
for(l=0;l < k;l++){
x = d_A[i*k + l];
for(j=0;j < n; j++){
d_C[i*n + j] += x * d_B[l*n + j];
}
}
}
} | #include <hip/hip_runtime.h>
__global__ void matmult_gpu1Kernel(int m, int n, int k, double * d_A, double * d_B, double * d_C);
extern "C" {
void matmult_gpu1(int m, int n, int k, double * A, double * B, double * C){
double * d_A, * d_B, * d_C;
hipMalloc((void **)&d_A, m * k * sizeof(double *));
hipMalloc((void **)&d_B, k * n * sizeof(double *));
hipMalloc((void **)&d_C, m * n * sizeof(double *));
hipMemcpy(d_A, A, m * k * sizeof(double *), hipMemcpyHostToDevice);
hipMemcpy(d_B, B, k * n * sizeof(double *), hipMemcpyHostToDevice);
matmult_gpu1Kernel<<<1,1>>>(m, n, k, d_A, d_B, d_C);
hipMemcpy(C, d_C, m * n * sizeof(double *), hipMemcpyDeviceToHost);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
}
}
__global__ void matmult_gpu1Kernel(int m, int n, int k, double * d_A, double * d_B, double * d_C){
int i, j, l;
double x;
for(i=0;i < m; i++){
for(j=0;j<n;j++){
d_C[i*n + j]=0;
}
for(l=0;l < k;l++){
x = d_A[i*k + l];
for(j=0;j < n; j++){
d_C[i*n + j] += x * d_B[l*n + j];
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void matmult_gpu1Kernel(int m, int n, int k, double * d_A, double * d_B, double * d_C);
extern "C" {
void matmult_gpu1(int m, int n, int k, double * A, double * B, double * C){
double * d_A, * d_B, * d_C;
hipMalloc((void **)&d_A, m * k * sizeof(double *));
hipMalloc((void **)&d_B, k * n * sizeof(double *));
hipMalloc((void **)&d_C, m * n * sizeof(double *));
hipMemcpy(d_A, A, m * k * sizeof(double *), hipMemcpyHostToDevice);
hipMemcpy(d_B, B, k * n * sizeof(double *), hipMemcpyHostToDevice);
matmult_gpu1Kernel<<<1,1>>>(m, n, k, d_A, d_B, d_C);
hipMemcpy(C, d_C, m * n * sizeof(double *), hipMemcpyDeviceToHost);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
}
}
__global__ void matmult_gpu1Kernel(int m, int n, int k, double * d_A, double * d_B, double * d_C){
int i, j, l;
double x;
for(i=0;i < m; i++){
for(j=0;j<n;j++){
d_C[i*n + j]=0;
}
for(l=0;l < k;l++){
x = d_A[i*k + l];
for(j=0;j < n; j++){
d_C[i*n + j] += x * d_B[l*n + j];
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18matmult_gpu1KerneliiiPdS_S_
.globl _Z18matmult_gpu1KerneliiiPdS_S_
.p2align 8
.type _Z18matmult_gpu1KerneliiiPdS_S_,@function
_Z18matmult_gpu1KerneliiiPdS_S_:
s_load_b32 s20, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s20, 1
s_cbranch_scc1 .LBB0_12
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x4
s_load_b128 s[4:7], s[0:1], 0x10
s_load_b64 s[8:9], s[0:1], 0x20
v_mov_b32_e32 v2, 0
s_mov_b32 s11, 0
s_mov_b32 s21, 0
s_mov_b32 s12, s11
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s3, 0
s_cselect_b32 s0, -1, 0
s_cmp_gt_i32 s2, 0
v_cndmask_b32_e64 v1, 0, 1, s0
s_cselect_b32 s1, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v0, 0, 1, s1
v_cmp_ne_u32_e64 s1, 1, v1
s_delay_alu instid0(VALU_DEP_2)
v_cmp_ne_u32_e64 s0, 1, v0
s_branch .LBB0_3
.LBB0_2:
s_set_inst_prefetch_distance 0x2
s_add_i32 s21, s21, 1
s_add_i32 s12, s12, s2
s_cmp_lg_u32 s21, s20
s_cbranch_scc0 .LBB0_12
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB0_6
s_mov_b32 s13, s11
s_mov_b32 s10, s2
s_lshl_b64 s[14:15], s[12:13], 3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s14, s8, s14
s_addc_u32 s15, s9, s15
.LBB0_5:
v_mov_b32_e32 v0, 0
s_add_i32 s10, s10, -1
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v1, v0
global_store_b64 v2, v[0:1], s[14:15]
s_add_u32 s14, s14, 8
s_addc_u32 s15, s15, 0
s_cmp_eq_u32 s10, 0
s_cbranch_scc0 .LBB0_5
.LBB0_6:
s_and_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_2
s_mov_b32 s13, s11
s_mov_b32 s10, 0
s_lshl_b64 s[14:15], s[12:13], 3
s_mul_i32 s22, s21, s3
s_add_u32 s14, s8, s14
s_addc_u32 s15, s9, s15
s_mov_b32 s13, s10
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_9
.p2align 6
.LBB0_8:
s_add_i32 s13, s13, 1
s_add_i32 s10, s10, s2
s_cmp_lg_u32 s13, s3
s_cbranch_scc0 .LBB0_2
.LBB0_9:
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB0_8
s_lshl_b64 s[16:17], s[10:11], 3
s_mov_b32 s19, s11
s_add_u32 s16, s6, s16
s_addc_u32 s17, s7, s17
s_add_i32 s18, s13, s22
s_mov_b32 s23, s2
s_lshl_b64 s[18:19], s[18:19], 3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s18, s4, s18
s_addc_u32 s19, s5, s19
global_load_b64 v[0:1], v2, s[18:19]
s_mov_b64 s[18:19], s[14:15]
.LBB0_11:
s_clause 0x1
global_load_b64 v[3:4], v2, s[16:17]
global_load_b64 v[5:6], v2, s[18:19]
s_add_i32 s23, s23, -1
s_waitcnt vmcnt(0)
v_fma_f64 v[3:4], v[0:1], v[3:4], v[5:6]
global_store_b64 v2, v[3:4], s[18:19]
s_add_u32 s18, s18, 8
s_addc_u32 s19, s19, 0
s_add_u32 s16, s16, 8
s_addc_u32 s17, s17, 0
s_cmp_lg_u32 s23, 0
s_cbranch_scc1 .LBB0_11
s_branch .LBB0_8
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18matmult_gpu1KerneliiiPdS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18matmult_gpu1KerneliiiPdS_S_, .Lfunc_end0-_Z18matmult_gpu1KerneliiiPdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18matmult_gpu1KerneliiiPdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z18matmult_gpu1KerneliiiPdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void matmult_gpu1Kernel(int m, int n, int k, double * d_A, double * d_B, double * d_C);
extern "C" {
void matmult_gpu1(int m, int n, int k, double * A, double * B, double * C){
double * d_A, * d_B, * d_C;
hipMalloc((void **)&d_A, m * k * sizeof(double *));
hipMalloc((void **)&d_B, k * n * sizeof(double *));
hipMalloc((void **)&d_C, m * n * sizeof(double *));
hipMemcpy(d_A, A, m * k * sizeof(double *), hipMemcpyHostToDevice);
hipMemcpy(d_B, B, k * n * sizeof(double *), hipMemcpyHostToDevice);
matmult_gpu1Kernel<<<1,1>>>(m, n, k, d_A, d_B, d_C);
hipMemcpy(C, d_C, m * n * sizeof(double *), hipMemcpyDeviceToHost);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
}
}
__global__ void matmult_gpu1Kernel(int m, int n, int k, double * d_A, double * d_B, double * d_C){
int i, j, l;
double x;
for(i=0;i < m; i++){
for(j=0;j<n;j++){
d_C[i*n + j]=0;
}
for(l=0;l < k;l++){
x = d_A[i*k + l];
for(j=0;j < n; j++){
d_C[i*n + j] += x * d_B[l*n + j];
}
}
}
} | .text
.file "matmult_gpu1.hip"
.globl matmult_gpu1 # -- Begin function matmult_gpu1
.p2align 4, 0x90
.type matmult_gpu1,@function
matmult_gpu1: # @matmult_gpu1
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 64(%rsp) # 8-byte Spill
movq %r8, 56(%rsp) # 8-byte Spill
movq %rcx, 48(%rsp) # 8-byte Spill
movl %edx, %ebp
movl %esi, %r15d
movl %edi, %r12d
movl %edx, %eax
imull %edi, %eax
movslq %eax, %r13
shlq $3, %r13
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movl %ebp, %eax
imull %r15d, %eax
movslq %eax, %rbx
shlq $3, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movl %r15d, %eax
imull %r12d, %eax
movslq %eax, %r14
shlq $3, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq 48(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 56(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl %r12d, 44(%rsp)
movl %r15d, 40(%rsp)
movl %ebp, 36(%rsp)
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 36(%rsp), %rax
movq %rax, 160(%rsp)
leaq 136(%rsp), %rax
movq %rax, 168(%rsp)
leaq 128(%rsp), %rax
movq %rax, 176(%rsp)
leaq 120(%rsp), %rax
movq %rax, 184(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z18matmult_gpu1KerneliiiPdS_S_, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
movq 8(%rsp), %rsi
movq 64(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size matmult_gpu1, .Lfunc_end0-matmult_gpu1
.cfi_endproc
# -- End function
.globl _Z33__device_stub__matmult_gpu1KerneliiiPdS_S_ # -- Begin function _Z33__device_stub__matmult_gpu1KerneliiiPdS_S_
.p2align 4, 0x90
.type _Z33__device_stub__matmult_gpu1KerneliiiPdS_S_,@function
_Z33__device_stub__matmult_gpu1KerneliiiPdS_S_: # @_Z33__device_stub__matmult_gpu1KerneliiiPdS_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18matmult_gpu1KerneliiiPdS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z33__device_stub__matmult_gpu1KerneliiiPdS_S_, .Lfunc_end1-_Z33__device_stub__matmult_gpu1KerneliiiPdS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18matmult_gpu1KerneliiiPdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18matmult_gpu1KerneliiiPdS_S_,@object # @_Z18matmult_gpu1KerneliiiPdS_S_
.section .rodata,"a",@progbits
.globl _Z18matmult_gpu1KerneliiiPdS_S_
.p2align 3, 0x0
_Z18matmult_gpu1KerneliiiPdS_S_:
.quad _Z33__device_stub__matmult_gpu1KerneliiiPdS_S_
.size _Z18matmult_gpu1KerneliiiPdS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18matmult_gpu1KerneliiiPdS_S_"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__matmult_gpu1KerneliiiPdS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18matmult_gpu1KerneliiiPdS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011ba8f_00000000-6_matmult_gpu1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z18matmult_gpu1KerneliiiPdS_S_iiiPdS_S_
.type _Z45__device_stub__Z18matmult_gpu1KerneliiiPdS_S_iiiPdS_S_, @function
_Z45__device_stub__Z18matmult_gpu1KerneliiiPdS_S_iiiPdS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18matmult_gpu1KerneliiiPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z45__device_stub__Z18matmult_gpu1KerneliiiPdS_S_iiiPdS_S_, .-_Z45__device_stub__Z18matmult_gpu1KerneliiiPdS_S_iiiPdS_S_
.globl _Z18matmult_gpu1KerneliiiPdS_S_
.type _Z18matmult_gpu1KerneliiiPdS_S_, @function
_Z18matmult_gpu1KerneliiiPdS_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z18matmult_gpu1KerneliiiPdS_S_iiiPdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z18matmult_gpu1KerneliiiPdS_S_, .-_Z18matmult_gpu1KerneliiiPdS_S_
.globl matmult_gpu1
.type matmult_gpu1, @function
matmult_gpu1:
.LFB2027:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movl %edi, %r13d
movl %esi, %r14d
movl %edx, %r15d
movq %rcx, 8(%rsp)
movq %r8, 16(%rsp)
movq %r9, 24(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl %edi, %r12d
imull %edx, %r12d
movslq %r12d, %r12
salq $3, %r12
leaq 40(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl %r15d, %ebp
imull %r14d, %ebp
movslq %ebp, %rbp
salq $3, %rbp
leaq 48(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %r13d, %ebx
imull %r14d, %ebx
movslq %ebx, %rbx
salq $3, %rbx
leaq 56(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq 8(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 16(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %rbx, %rdx
movq 56(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 56(%rsp), %r9
movq 48(%rsp), %r8
movq 40(%rsp), %rcx
movl %r15d, %edx
movl %r14d, %esi
movl %r13d, %edi
call _Z45__device_stub__Z18matmult_gpu1KerneliiiPdS_S_iiiPdS_S_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size matmult_gpu1, .-matmult_gpu1
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18matmult_gpu1KerneliiiPdS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18matmult_gpu1KerneliiiPdS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matmult_gpu1.hip"
.globl matmult_gpu1 # -- Begin function matmult_gpu1
.p2align 4, 0x90
.type matmult_gpu1,@function
matmult_gpu1: # @matmult_gpu1
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 64(%rsp) # 8-byte Spill
movq %r8, 56(%rsp) # 8-byte Spill
movq %rcx, 48(%rsp) # 8-byte Spill
movl %edx, %ebp
movl %esi, %r15d
movl %edi, %r12d
movl %edx, %eax
imull %edi, %eax
movslq %eax, %r13
shlq $3, %r13
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movl %ebp, %eax
imull %r15d, %eax
movslq %eax, %rbx
shlq $3, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movl %r15d, %eax
imull %r12d, %eax
movslq %eax, %r14
shlq $3, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq 48(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 56(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl %r12d, 44(%rsp)
movl %r15d, 40(%rsp)
movl %ebp, 36(%rsp)
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 36(%rsp), %rax
movq %rax, 160(%rsp)
leaq 136(%rsp), %rax
movq %rax, 168(%rsp)
leaq 128(%rsp), %rax
movq %rax, 176(%rsp)
leaq 120(%rsp), %rax
movq %rax, 184(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z18matmult_gpu1KerneliiiPdS_S_, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
movq 8(%rsp), %rsi
movq 64(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size matmult_gpu1, .Lfunc_end0-matmult_gpu1
.cfi_endproc
# -- End function
.globl _Z33__device_stub__matmult_gpu1KerneliiiPdS_S_ # -- Begin function _Z33__device_stub__matmult_gpu1KerneliiiPdS_S_
.p2align 4, 0x90
.type _Z33__device_stub__matmult_gpu1KerneliiiPdS_S_,@function
_Z33__device_stub__matmult_gpu1KerneliiiPdS_S_: # @_Z33__device_stub__matmult_gpu1KerneliiiPdS_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18matmult_gpu1KerneliiiPdS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z33__device_stub__matmult_gpu1KerneliiiPdS_S_, .Lfunc_end1-_Z33__device_stub__matmult_gpu1KerneliiiPdS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18matmult_gpu1KerneliiiPdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18matmult_gpu1KerneliiiPdS_S_,@object # @_Z18matmult_gpu1KerneliiiPdS_S_
.section .rodata,"a",@progbits
.globl _Z18matmult_gpu1KerneliiiPdS_S_
.p2align 3, 0x0
_Z18matmult_gpu1KerneliiiPdS_S_:
.quad _Z33__device_stub__matmult_gpu1KerneliiiPdS_S_
.size _Z18matmult_gpu1KerneliiiPdS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18matmult_gpu1KerneliiiPdS_S_"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__matmult_gpu1KerneliiiPdS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18matmult_gpu1KerneliiiPdS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // nvcc vector_add.cu -o vector_add
#include <stdio.h>
#include <stdlib.h>
#define N 10000000
__global__ void vector_add(float *out, float *a, float *b, int n) {
for (int i = 0; i < n; i++) {
out[i] = a[i] + b[i];
}
}
int main() {
float *a, *b, *out;
a = (float *)malloc(sizeof(float) * N);
b = (float *)malloc(sizeof(float) * N);
out = (float *)malloc(sizeof(float) * N);
// Initialize array
for (int i = 0; i < N; i++) {
a[i] = 1.0f; b[i] = 2.0f;
}
vector_add<<<1,1>>>(out, a, b, N);
} | code for sm_80
Function : _Z10vector_addPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0050*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0060*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*0070*/ ULDC.64 UR12, c[0x0][0x118] ; /* 0x00004600000c7ab9 */
/* 0x000fe20000000a00 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0090*/ @!P0 BRA 0xb80 ; /* 0x00000ae000008947 */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R8, -R0, c[0x0][0x178], RZ ; /* 0x00005e0000087a10 */
/* 0x000fe20007ffe1ff */
/*00b0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00c0*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*00e0*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f04270 */
/*00f0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fe200078e00ff */
/*0100*/ MOV R2, c[0x0][0x170] ; /* 0x00005c0000027a02 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff077624 */
/* 0x000fe200078e00ff */
/*0120*/ MOV R6, c[0x0][0x168] ; /* 0x00005a0000067a02 */
/* 0x000fd20000000f00 */
/*0130*/ @!P0 BRA 0x990 ; /* 0x0000085000008947 */
/* 0x000fea0003800000 */
/*0140*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*0150*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0160*/ @!P1 BRA 0x670 ; /* 0x0000050000009947 */
/* 0x000fea0003800000 */
/*0170*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0180*/ LDG.E R9, [R2.64] ; /* 0x0000000c02097981 */
/* 0x000ea8000c1e1900 */
/*0190*/ LDG.E R10, [R6.64] ; /* 0x0000000c060a7981 */
/* 0x000ea4000c1e1900 */
/*01a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x004fca0000000000 */
/*01b0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e8000c10190c */
/*01c0*/ LDG.E R10, [R2.64+0x4] ; /* 0x0000040c020a7981 */
/* 0x000ea8000c1e1900 */
/*01d0*/ LDG.E R11, [R6.64+0x4] ; /* 0x0000040c060b7981 */
/* 0x000ea4000c1e1900 */
/*01e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*01f0*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0003e8000c10190c */
/*0200*/ LDG.E R10, [R2.64+0x8] ; /* 0x0000080c020a7981 */
/* 0x000ea8000c1e1900 */
/*0210*/ LDG.E R13, [R6.64+0x8] ; /* 0x0000080c060d7981 */
/* 0x000ea4000c1e1900 */
/*0220*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x004fca0000000000 */
/*0230*/ STG.E [R4.64+0x8], R13 ; /* 0x0000080d04007986 */
/* 0x0005e8000c10190c */
/*0240*/ LDG.E R10, [R2.64+0xc] ; /* 0x00000c0c020a7981 */
/* 0x000ee8000c1e1900 */
/*0250*/ LDG.E R15, [R6.64+0xc] ; /* 0x00000c0c060f7981 */
/* 0x000ee4000c1e1900 */
/*0260*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x008fca0000000000 */
/*0270*/ STG.E [R4.64+0xc], R15 ; /* 0x00000c0f04007986 */
/* 0x0007e8000c10190c */
/*0280*/ LDG.E R9, [R2.64+0x10] ; /* 0x0000100c02097981 */
/* 0x001f28000c1e1900 */
/*0290*/ LDG.E R10, [R6.64+0x10] ; /* 0x0000100c060a7981 */
/* 0x000f24000c1e1900 */
/*02a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*02b0*/ STG.E [R4.64+0x10], R9 ; /* 0x0000100904007986 */
/* 0x0001e8000c10190c */
/*02c0*/ LDG.E R10, [R2.64+0x14] ; /* 0x0000140c020a7981 */
/* 0x000f28000c1e1900 */
/*02d0*/ LDG.E R11, [R6.64+0x14] ; /* 0x0000140c060b7981 */
/* 0x002f24000c1e1900 */
/*02e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*02f0*/ STG.E [R4.64+0x14], R11 ; /* 0x0000140b04007986 */
/* 0x0003e8000c10190c */
/*0300*/ LDG.E R10, [R2.64+0x18] ; /* 0x0000180c020a7981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R13, [R6.64+0x18] ; /* 0x0000180c060d7981 */
/* 0x004f24000c1e1900 */
/*0320*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0330*/ STG.E [R4.64+0x18], R13 ; /* 0x0000180d04007986 */
/* 0x0005e8000c10190c */
/*0340*/ LDG.E R10, [R2.64+0x1c] ; /* 0x00001c0c020a7981 */
/* 0x000f28000c1e1900 */
/*0350*/ LDG.E R15, [R6.64+0x1c] ; /* 0x00001c0c060f7981 */
/* 0x008f24000c1e1900 */
/*0360*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x010fca0000000000 */
/*0370*/ STG.E [R4.64+0x1c], R15 ; /* 0x00001c0f04007986 */
/* 0x0007e8000c10190c */
/*0380*/ LDG.E R9, [R2.64+0x20] ; /* 0x0000200c02097981 */
/* 0x001f28000c1e1900 */
/*0390*/ LDG.E R10, [R6.64+0x20] ; /* 0x0000200c060a7981 */
/* 0x000f24000c1e1900 */
/*03a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*03b0*/ STG.E [R4.64+0x20], R9 ; /* 0x0000200904007986 */
/* 0x0001e8000c10190c */
/*03c0*/ LDG.E R10, [R2.64+0x24] ; /* 0x0000240c020a7981 */
/* 0x000f28000c1e1900 */
/*03d0*/ LDG.E R11, [R6.64+0x24] ; /* 0x0000240c060b7981 */
/* 0x002f24000c1e1900 */
/*03e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*03f0*/ STG.E [R4.64+0x24], R11 ; /* 0x0000240b04007986 */
/* 0x0003e8000c10190c */
/*0400*/ LDG.E R10, [R2.64+0x28] ; /* 0x0000280c020a7981 */
/* 0x000f28000c1e1900 */
/*0410*/ LDG.E R13, [R6.64+0x28] ; /* 0x0000280c060d7981 */
/* 0x004f24000c1e1900 */
/*0420*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0430*/ STG.E [R4.64+0x28], R13 ; /* 0x0000280d04007986 */
/* 0x0005e8000c10190c */
/*0440*/ LDG.E R10, [R2.64+0x2c] ; /* 0x00002c0c020a7981 */
/* 0x000f28000c1e1900 */
/*0450*/ LDG.E R15, [R6.64+0x2c] ; /* 0x00002c0c060f7981 */
/* 0x008f24000c1e1900 */
/*0460*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x010fca0000000000 */
/*0470*/ STG.E [R4.64+0x2c], R15 ; /* 0x00002c0f04007986 */
/* 0x0007e8000c10190c */
/*0480*/ LDG.E R9, [R2.64+0x30] ; /* 0x0000300c02097981 */
/* 0x001f28000c1e1900 */
/*0490*/ LDG.E R10, [R6.64+0x30] ; /* 0x0000300c060a7981 */
/* 0x000f24000c1e1900 */
/*04a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*04b0*/ STG.E [R4.64+0x30], R9 ; /* 0x0000300904007986 */
/* 0x000fe8000c10190c */
/*04c0*/ LDG.E R10, [R2.64+0x34] ; /* 0x0000340c020a7981 */
/* 0x000f28000c1e1900 */
/*04d0*/ LDG.E R11, [R6.64+0x34] ; /* 0x0000340c060b7981 */
/* 0x002f24000c1e1900 */
/*04e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*04f0*/ STG.E [R4.64+0x34], R11 ; /* 0x0000340b04007986 */
/* 0x0001e8000c10190c */
/*0500*/ LDG.E R10, [R2.64+0x38] ; /* 0x0000380c020a7981 */
/* 0x000f28000c1e1900 */
/*0510*/ LDG.E R13, [R6.64+0x38] ; /* 0x0000380c060d7981 */
/* 0x004f22000c1e1900 */
/*0520*/ IADD3 R12, P1, R2, 0x40, RZ ; /* 0x00000040020c7810 */
/* 0x000fe40007f3e0ff */
/*0530*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fe20007ffe0ff */
/*0540*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0550*/ STG.E [R4.64+0x38], R13 ; /* 0x0000380d04007986 */
/* 0x000fe8000c10190c */
/*0560*/ LDG.E R10, [R2.64+0x3c] ; /* 0x00003c0c020a7981 */
/* 0x0002a8000c1e1900 */
/*0570*/ LDG.E R15, [R6.64+0x3c] ; /* 0x00003c0c060f7981 */
/* 0x0086a2000c1e1900 */
/*0580*/ IADD3.X R11, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff0b7210 */
/* 0x001fe20000ffe4ff */
/*0590*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*05a0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fc40003f24270 */
/*05b0*/ IADD3 R9, P3, R4, 0x40, RZ ; /* 0x0000004004097810 */
/* 0x000fe20007f7e0ff */
/*05c0*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x002fe200078e000c */
/*05d0*/ IADD3 R14, P2, R6, 0x40, RZ ; /* 0x00000040060e7810 */
/* 0x000fe40007f5e0ff */
/*05e0*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fc60000000f00 */
/*05f0*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x008fe400010e0607 */
/*0600*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000e */
/*0610*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x004fe20000000000 */
/*0620*/ IADD3.X R10, RZ, R5, RZ, P3, !PT ; /* 0x00000005ff0a7210 */
/* 0x000fc80001ffe4ff */
/*0630*/ STG.E [R4.64+0x3c], R15 ; /* 0x00003c0f04007986 */
/* 0x0001e4000c10190c */
/*0640*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x001fe20000000f00 */
/*0650*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000a */
/*0660*/ @P1 BRA 0x180 ; /* 0xfffffb1000001947 */
/* 0x000fea000383ffff */
/*0670*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0680*/ @!P1 BRA 0x970 ; /* 0x000002e000009947 */
/* 0x000fea0003800000 */
/*0690*/ LDG.E R9, [R2.64] ; /* 0x0000000c02097981 */
/* 0x000ea8000c1e1900 */
/*06a0*/ LDG.E R10, [R6.64] ; /* 0x0000000c060a7981 */
/* 0x000ea4000c1e1900 */
/*06b0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x004fca0000000000 */
/*06c0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e8000c10190c */
/*06d0*/ LDG.E R10, [R2.64+0x4] ; /* 0x0000040c020a7981 */
/* 0x000ea8000c1e1900 */
/*06e0*/ LDG.E R11, [R6.64+0x4] ; /* 0x0000040c060b7981 */
/* 0x000ea4000c1e1900 */
/*06f0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*0700*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0003e8000c10190c */
/*0710*/ LDG.E R10, [R2.64+0x8] ; /* 0x0000080c020a7981 */
/* 0x000ea8000c1e1900 */
/*0720*/ LDG.E R13, [R6.64+0x8] ; /* 0x0000080c060d7981 */
/* 0x000ea4000c1e1900 */
/*0730*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x004fca0000000000 */
/*0740*/ STG.E [R4.64+0x8], R13 ; /* 0x0000080d04007986 */
/* 0x0005e8000c10190c */
/*0750*/ LDG.E R10, [R2.64+0xc] ; /* 0x00000c0c020a7981 */
/* 0x000ee8000c1e1900 */
/*0760*/ LDG.E R15, [R6.64+0xc] ; /* 0x00000c0c060f7981 */
/* 0x000ee4000c1e1900 */
/*0770*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x008fca0000000000 */
/*0780*/ STG.E [R4.64+0xc], R15 ; /* 0x00000c0f04007986 */
/* 0x0007e8000c10190c */
/*0790*/ LDG.E R9, [R2.64+0x10] ; /* 0x0000100c02097981 */
/* 0x001f28000c1e1900 */
/*07a0*/ LDG.E R10, [R6.64+0x10] ; /* 0x0000100c060a7981 */
/* 0x000f24000c1e1900 */
/*07b0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*07c0*/ STG.E [R4.64+0x10], R9 ; /* 0x0000100904007986 */
/* 0x000fe8000c10190c */
/*07d0*/ LDG.E R10, [R2.64+0x14] ; /* 0x0000140c020a7981 */
/* 0x000f28000c1e1900 */
/*07e0*/ LDG.E R11, [R6.64+0x14] ; /* 0x0000140c060b7981 */
/* 0x002f24000c1e1900 */
/*07f0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*0800*/ STG.E [R4.64+0x14], R11 ; /* 0x0000140b04007986 */
/* 0x0001e8000c10190c */
/*0810*/ LDG.E R10, [R2.64+0x18] ; /* 0x0000180c020a7981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R13, [R6.64+0x18] ; /* 0x0000180c060d7981 */
/* 0x004f24000c1e1900 */
/*0830*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0840*/ STG.E [R4.64+0x18], R13 ; /* 0x0000180d04007986 */
/* 0x000fe8000c10190c */
/*0850*/ LDG.E R10, [R2.64+0x1c] ; /* 0x00001c0c020a7981 */
/* 0x0002a8000c1e1900 */
/*0860*/ LDG.E R15, [R6.64+0x1c] ; /* 0x00001c0c060f7981 */
/* 0x0086a2000c1e1900 */
/*0870*/ IADD3 R11, P2, R2, 0x20, RZ ; /* 0x00000020020b7810 */
/* 0x001fe20007f5e0ff */
/*0880*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0890*/ IADD3 R9, P3, R4, 0x20, RZ ; /* 0x0000002004097810 */
/* 0x000fc40007f7e0ff */
/*08a0*/ IADD3 R14, P1, R6, 0x20, RZ ; /* 0x00000020060e7810 */
/* 0x000fe20007f3e0ff */
/*08b0*/ IMAD.X R12, RZ, RZ, R3, P2 ; /* 0x000000ffff0c7224 */
/* 0x000fe200010e0603 */
/*08c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*08d0*/ IMAD.MOV.U32 R2, RZ, RZ, R11 ; /* 0x000000ffff027224 */
/* 0x002fe200078e000b */
/*08e0*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe20007ffe0ff */
/*08f0*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x008fe200078e000e */
/*0900*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe40000ffe4ff */
/*0910*/ MOV R3, R12 ; /* 0x0000000c00037202 */
/* 0x000fe20000000f00 */
/*0920*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x004fe20000000000 */
/*0930*/ IADD3.X R10, RZ, R5, RZ, P3, !PT ; /* 0x00000005ff0a7210 */
/* 0x000fc80001ffe4ff */
/*0940*/ STG.E [R4.64+0x1c], R15 ; /* 0x00001c0f04007986 */
/* 0x0001e4000c10190c */
/*0950*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x001fe20000000f00 */
/*0960*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000a */
/*0970*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*0980*/ @!P0 BRA 0xb80 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0990*/ LDG.E R9, [R2.64] ; /* 0x0000000c02097981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ LDG.E R10, [R6.64] ; /* 0x0000000c060a7981 */
/* 0x000ea4000c1e1900 */
/*09b0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x004fca0000000000 */
/*09c0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe8000c10190c */
/*09d0*/ LDG.E R10, [R2.64+0x4] ; /* 0x0000040c020a7981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R11, [R6.64+0x4] ; /* 0x0000040c060b7981 */
/* 0x000ea4000c1e1900 */
/*09f0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*0a00*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0001e8000c10190c */
/*0a10*/ LDG.E R10, [R2.64+0x8] ; /* 0x0000080c020a7981 */
/* 0x000ea8000c1e1900 */
/*0a20*/ LDG.E R13, [R6.64+0x8] ; /* 0x0000080c060d7981 */
/* 0x000ea2000c1e1900 */
/*0a30*/ IADD3 R12, P0, R2, 0x10, RZ ; /* 0x00000010020c7810 */
/* 0x000fe40007f1e0ff */
/*0a40*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe20007ffe0ff */
/*0a50*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x004fca0000000000 */
/*0a60*/ STG.E [R4.64+0x8], R13 ; /* 0x0000080d04007986 */
/* 0x000fe8000c10190c */
/*0a70*/ LDG.E R10, [R2.64+0xc] ; /* 0x00000c0c020a7981 */
/* 0x0002a8000c1e1900 */
/*0a80*/ LDG.E R15, [R6.64+0xc] ; /* 0x00000c0c060f7981 */
/* 0x0006a2000c1e1900 */
/*0a90*/ IADD3.X R11, RZ, R3, RZ, P0, !PT ; /* 0x00000003ff0b7210 */
/* 0x001fe200007fe4ff */
/*0aa0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0ab0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc40003f05270 */
/*0ac0*/ IADD3 R9, P2, R4, 0x10, RZ ; /* 0x0000001004097810 */
/* 0x000fe20007f5e0ff */
/*0ad0*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x002fe200078e000c */
/*0ae0*/ IADD3 R14, P1, R6, 0x10, RZ ; /* 0x00000010060e7810 */
/* 0x000fe40007f3e0ff */
/*0af0*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fc60000000f00 */
/*0b00*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x008fe400008e0607 */
/*0b10*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000e */
/*0b20*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x004fe20000000000 */
/*0b30*/ IADD3.X R10, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff0a7210 */
/* 0x000fc800017fe4ff */
/*0b40*/ STG.E [R4.64+0xc], R15 ; /* 0x00000c0f04007986 */
/* 0x0001e4000c10190c */
/*0b50*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x001fe20000000f00 */
/*0b60*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000a */
/*0b70*/ @P0 BRA 0x990 ; /* 0xfffffe1000000947 */
/* 0x000fea000383ffff */
/*0b80*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0b90*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0ba0*/ UMOV UR5, 0x4 ; /* 0x0000000400057882 */
/* 0x000fe40000000000 */
/*0bb0*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe40000000a00 */
/*0bc0*/ ULDC.64 UR8, c[0x0][0x170] ; /* 0x00005c0000087ab9 */
/* 0x000fe40000000a00 */
/*0bd0*/ ULDC.64 UR10, c[0x0][0x168] ; /* 0x00005a00000a7ab9 */
/* 0x000fe40000000a00 */
/*0be0*/ UIMAD.WIDE UR6, UR4, UR5, UR6 ; /* 0x00000005040672a5 */
/* 0x000fe4000f8e0206 */
/*0bf0*/ UIMAD.WIDE UR8, UR4, UR5, UR8 ; /* 0x00000005040872a5 */
/* 0x000fc4000f8e0208 */
/*0c00*/ UIMAD.WIDE UR4, UR4, UR5, UR10 ; /* 0x00000005040472a5 */
/* 0x000fca000f8e020a */
/*0c10*/ MOV R2, UR8 ; /* 0x0000000800027c02 */
/* 0x000fe20008000f00 */
/*0c20*/ IMAD.U32 R5, RZ, RZ, UR5 ; /* 0x00000005ff057e24 */
/* 0x000fe2000f8e00ff */
/*0c30*/ MOV R4, UR4 ; /* 0x0000000400047c02 */
/* 0x000fe20008000f00 */
/*0c40*/ IMAD.U32 R3, RZ, RZ, UR9 ; /* 0x00000009ff037e24 */
/* 0x000fc8000f8e00ff */
/*0c50*/ LDG.E R5, [R4.64] ; /* 0x0000000c04057981 */
/* 0x000ea8000c1e1900 */
/*0c60*/ LDG.E R2, [R2.64] ; /* 0x0000000c02027981 */
/* 0x000ea2000c1e1900 */
/*0c70*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc80007ffe0ff */
/*0c80*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0c90*/ UIADD3 UR8, UP1, UR8, 0x4, URZ ; /* 0x0000000408087890 */
/* 0x000fe2000ff3e03f */
/*0ca0*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x001fe20008000f00 */
/*0cb0*/ UIADD3 UR6, UP0, UR6, 0x4, URZ ; /* 0x0000000406067890 */
/* 0x000fe2000ff1e03f */
/*0cc0*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fe20008000f00 */
/*0cd0*/ UIADD3 UR4, UP2, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe4000ff5e03f */
/*0ce0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe400087fe43f */
/*0cf0*/ UIADD3.X UR9, URZ, UR9, URZ, UP1, !UPT ; /* 0x000000093f097290 */
/* 0x000fe40008ffe43f */
/*0d00*/ UIADD3.X UR5, URZ, UR5, URZ, UP2, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200097fe43f */
/*0d10*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*0d20*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e2000c10190c */
/*0d30*/ @P0 BRA 0xc10 ; /* 0xfffffed000000947 */
/* 0x000fea000383ffff */
/*0d40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d50*/ BRA 0xd50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // nvcc vector_add.cu -o vector_add
#include <stdio.h>
#include <stdlib.h>
#define N 10000000
__global__ void vector_add(float *out, float *a, float *b, int n) {
for (int i = 0; i < n; i++) {
out[i] = a[i] + b[i];
}
}
int main() {
float *a, *b, *out;
a = (float *)malloc(sizeof(float) * N);
b = (float *)malloc(sizeof(float) * N);
out = (float *)malloc(sizeof(float) * N);
// Initialize array
for (int i = 0; i < N; i++) {
a[i] = 1.0f; b[i] = 2.0f;
}
vector_add<<<1,1>>>(out, a, b, N);
} | .file "tmpxft_000951e2_00000000-6_vector_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
.type _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10vector_addPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i, .-_Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
.globl _Z10vector_addPfS_S_i
.type _Z10vector_addPfS_S_i, @function
_Z10vector_addPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10vector_addPfS_S_i, .-_Z10vector_addPfS_S_i
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movl $40000000, %edi
call malloc@PLT
movq %rax, %rbx
movl $40000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $40000000, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %eax
movss .LC0(%rip), %xmm1
movss .LC1(%rip), %xmm0
.L12:
movss %xmm1, (%rbx,%rax)
movss %xmm0, 0(%rbp,%rax)
addq $4, %rax
cmpq $40000000, %rax
jne .L12
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L13:
movl $0, %eax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl $10000000, %ecx
movq %rbp, %rdx
movq %rbx, %rsi
movq %r12, %rdi
call _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
jmp .L13
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z10vector_addPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10vector_addPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.align 4
.LC1:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // nvcc vector_add.cu -o vector_add
#include <stdio.h>
#include <stdlib.h>
#define N 10000000
__global__ void vector_add(float *out, float *a, float *b, int n) {
for (int i = 0; i < n; i++) {
out[i] = a[i] + b[i];
}
}
int main() {
float *a, *b, *out;
a = (float *)malloc(sizeof(float) * N);
b = (float *)malloc(sizeof(float) * N);
out = (float *)malloc(sizeof(float) * N);
// Initialize array
for (int i = 0; i < N; i++) {
a[i] = 1.0f; b[i] = 2.0f;
}
vector_add<<<1,1>>>(out, a, b, N);
} | // nvcc vector_add.cu -o vector_add
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 10000000
__global__ void vector_add(float *out, float *a, float *b, int n) {
for (int i = 0; i < n; i++) {
out[i] = a[i] + b[i];
}
}
int main() {
float *a, *b, *out;
a = (float *)malloc(sizeof(float) * N);
b = (float *)malloc(sizeof(float) * N);
out = (float *)malloc(sizeof(float) * N);
// Initialize array
for (int i = 0; i < N; i++) {
a[i] = 1.0f; b[i] = 2.0f;
}
vector_add<<<1,1>>>(out, a, b, N);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // nvcc vector_add.cu -o vector_add
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 10000000
__global__ void vector_add(float *out, float *a, float *b, int n) {
for (int i = 0; i < n; i++) {
out[i] = a[i] + b[i];
}
}
int main() {
float *a, *b, *out;
a = (float *)malloc(sizeof(float) * N);
b = (float *)malloc(sizeof(float) * N);
out = (float *)malloc(sizeof(float) * N);
// Initialize array
for (int i = 0; i < N; i++) {
a[i] = 1.0f; b[i] = 2.0f;
}
vector_add<<<1,1>>>(out, a, b, N);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10vector_addPfS_S_i
.globl _Z10vector_addPfS_S_i
.p2align 8
.type _Z10vector_addPfS_S_i,@function
_Z10vector_addPfS_S_i:
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v0, 0
.LBB0_2:
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[6:7]
global_load_b32 v2, v0, s[0:1]
s_add_i32 s2, s2, -1
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[4:5]
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s2, 0
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10vector_addPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10vector_addPfS_S_i, .Lfunc_end0-_Z10vector_addPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10vector_addPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z10vector_addPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // nvcc vector_add.cu -o vector_add
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 10000000
__global__ void vector_add(float *out, float *a, float *b, int n) {
for (int i = 0; i < n; i++) {
out[i] = a[i] + b[i];
}
}
int main() {
float *a, *b, *out;
a = (float *)malloc(sizeof(float) * N);
b = (float *)malloc(sizeof(float) * N);
out = (float *)malloc(sizeof(float) * N);
// Initialize array
for (int i = 0; i < N; i++) {
a[i] = 1.0f; b[i] = 2.0f;
}
vector_add<<<1,1>>>(out, a, b, N);
} | .text
.file "vector_add.hip"
.globl _Z25__device_stub__vector_addPfS_S_i # -- Begin function _Z25__device_stub__vector_addPfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__vector_addPfS_S_i,@function
_Z25__device_stub__vector_addPfS_S_i: # @_Z25__device_stub__vector_addPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10vector_addPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__vector_addPfS_S_i, .Lfunc_end0-_Z25__device_stub__vector_addPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $40000000, %edi # imm = 0x2625A00
callq malloc
movq %rax, %rbx
movl $40000000, %edi # imm = 0x2625A00
callq malloc
movq %rax, %r14
movl $40000000, %edi # imm = 0x2625A00
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
movl $1073741824, (%r14,%rax,4) # imm = 0x40000000
incq %rax
cmpq $10000000, %rax # imm = 0x989680
jne .LBB1_1
# %bb.2:
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq %r15, 72(%rsp)
movq %rbx, 64(%rsp)
movq %r14, 56(%rsp)
movl $10000000, 4(%rsp) # imm = 0x989680
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10vector_addPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10vector_addPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10vector_addPfS_S_i,@object # @_Z10vector_addPfS_S_i
.section .rodata,"a",@progbits
.globl _Z10vector_addPfS_S_i
.p2align 3, 0x0
_Z10vector_addPfS_S_i:
.quad _Z25__device_stub__vector_addPfS_S_i
.size _Z10vector_addPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10vector_addPfS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__vector_addPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10vector_addPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10vector_addPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0050*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0060*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*0070*/ ULDC.64 UR12, c[0x0][0x118] ; /* 0x00004600000c7ab9 */
/* 0x000fe20000000a00 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0090*/ @!P0 BRA 0xb80 ; /* 0x00000ae000008947 */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R8, -R0, c[0x0][0x178], RZ ; /* 0x00005e0000087a10 */
/* 0x000fe20007ffe1ff */
/*00b0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00c0*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*00e0*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f04270 */
/*00f0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fe200078e00ff */
/*0100*/ MOV R2, c[0x0][0x170] ; /* 0x00005c0000027a02 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff077624 */
/* 0x000fe200078e00ff */
/*0120*/ MOV R6, c[0x0][0x168] ; /* 0x00005a0000067a02 */
/* 0x000fd20000000f00 */
/*0130*/ @!P0 BRA 0x990 ; /* 0x0000085000008947 */
/* 0x000fea0003800000 */
/*0140*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*0150*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0160*/ @!P1 BRA 0x670 ; /* 0x0000050000009947 */
/* 0x000fea0003800000 */
/*0170*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0180*/ LDG.E R9, [R2.64] ; /* 0x0000000c02097981 */
/* 0x000ea8000c1e1900 */
/*0190*/ LDG.E R10, [R6.64] ; /* 0x0000000c060a7981 */
/* 0x000ea4000c1e1900 */
/*01a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x004fca0000000000 */
/*01b0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e8000c10190c */
/*01c0*/ LDG.E R10, [R2.64+0x4] ; /* 0x0000040c020a7981 */
/* 0x000ea8000c1e1900 */
/*01d0*/ LDG.E R11, [R6.64+0x4] ; /* 0x0000040c060b7981 */
/* 0x000ea4000c1e1900 */
/*01e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*01f0*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0003e8000c10190c */
/*0200*/ LDG.E R10, [R2.64+0x8] ; /* 0x0000080c020a7981 */
/* 0x000ea8000c1e1900 */
/*0210*/ LDG.E R13, [R6.64+0x8] ; /* 0x0000080c060d7981 */
/* 0x000ea4000c1e1900 */
/*0220*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x004fca0000000000 */
/*0230*/ STG.E [R4.64+0x8], R13 ; /* 0x0000080d04007986 */
/* 0x0005e8000c10190c */
/*0240*/ LDG.E R10, [R2.64+0xc] ; /* 0x00000c0c020a7981 */
/* 0x000ee8000c1e1900 */
/*0250*/ LDG.E R15, [R6.64+0xc] ; /* 0x00000c0c060f7981 */
/* 0x000ee4000c1e1900 */
/*0260*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x008fca0000000000 */
/*0270*/ STG.E [R4.64+0xc], R15 ; /* 0x00000c0f04007986 */
/* 0x0007e8000c10190c */
/*0280*/ LDG.E R9, [R2.64+0x10] ; /* 0x0000100c02097981 */
/* 0x001f28000c1e1900 */
/*0290*/ LDG.E R10, [R6.64+0x10] ; /* 0x0000100c060a7981 */
/* 0x000f24000c1e1900 */
/*02a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*02b0*/ STG.E [R4.64+0x10], R9 ; /* 0x0000100904007986 */
/* 0x0001e8000c10190c */
/*02c0*/ LDG.E R10, [R2.64+0x14] ; /* 0x0000140c020a7981 */
/* 0x000f28000c1e1900 */
/*02d0*/ LDG.E R11, [R6.64+0x14] ; /* 0x0000140c060b7981 */
/* 0x002f24000c1e1900 */
/*02e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*02f0*/ STG.E [R4.64+0x14], R11 ; /* 0x0000140b04007986 */
/* 0x0003e8000c10190c */
/*0300*/ LDG.E R10, [R2.64+0x18] ; /* 0x0000180c020a7981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R13, [R6.64+0x18] ; /* 0x0000180c060d7981 */
/* 0x004f24000c1e1900 */
/*0320*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0330*/ STG.E [R4.64+0x18], R13 ; /* 0x0000180d04007986 */
/* 0x0005e8000c10190c */
/*0340*/ LDG.E R10, [R2.64+0x1c] ; /* 0x00001c0c020a7981 */
/* 0x000f28000c1e1900 */
/*0350*/ LDG.E R15, [R6.64+0x1c] ; /* 0x00001c0c060f7981 */
/* 0x008f24000c1e1900 */
/*0360*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x010fca0000000000 */
/*0370*/ STG.E [R4.64+0x1c], R15 ; /* 0x00001c0f04007986 */
/* 0x0007e8000c10190c */
/*0380*/ LDG.E R9, [R2.64+0x20] ; /* 0x0000200c02097981 */
/* 0x001f28000c1e1900 */
/*0390*/ LDG.E R10, [R6.64+0x20] ; /* 0x0000200c060a7981 */
/* 0x000f24000c1e1900 */
/*03a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*03b0*/ STG.E [R4.64+0x20], R9 ; /* 0x0000200904007986 */
/* 0x0001e8000c10190c */
/*03c0*/ LDG.E R10, [R2.64+0x24] ; /* 0x0000240c020a7981 */
/* 0x000f28000c1e1900 */
/*03d0*/ LDG.E R11, [R6.64+0x24] ; /* 0x0000240c060b7981 */
/* 0x002f24000c1e1900 */
/*03e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*03f0*/ STG.E [R4.64+0x24], R11 ; /* 0x0000240b04007986 */
/* 0x0003e8000c10190c */
/*0400*/ LDG.E R10, [R2.64+0x28] ; /* 0x0000280c020a7981 */
/* 0x000f28000c1e1900 */
/*0410*/ LDG.E R13, [R6.64+0x28] ; /* 0x0000280c060d7981 */
/* 0x004f24000c1e1900 */
/*0420*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0430*/ STG.E [R4.64+0x28], R13 ; /* 0x0000280d04007986 */
/* 0x0005e8000c10190c */
/*0440*/ LDG.E R10, [R2.64+0x2c] ; /* 0x00002c0c020a7981 */
/* 0x000f28000c1e1900 */
/*0450*/ LDG.E R15, [R6.64+0x2c] ; /* 0x00002c0c060f7981 */
/* 0x008f24000c1e1900 */
/*0460*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x010fca0000000000 */
/*0470*/ STG.E [R4.64+0x2c], R15 ; /* 0x00002c0f04007986 */
/* 0x0007e8000c10190c */
/*0480*/ LDG.E R9, [R2.64+0x30] ; /* 0x0000300c02097981 */
/* 0x001f28000c1e1900 */
/*0490*/ LDG.E R10, [R6.64+0x30] ; /* 0x0000300c060a7981 */
/* 0x000f24000c1e1900 */
/*04a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*04b0*/ STG.E [R4.64+0x30], R9 ; /* 0x0000300904007986 */
/* 0x000fe8000c10190c */
/*04c0*/ LDG.E R10, [R2.64+0x34] ; /* 0x0000340c020a7981 */
/* 0x000f28000c1e1900 */
/*04d0*/ LDG.E R11, [R6.64+0x34] ; /* 0x0000340c060b7981 */
/* 0x002f24000c1e1900 */
/*04e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*04f0*/ STG.E [R4.64+0x34], R11 ; /* 0x0000340b04007986 */
/* 0x0001e8000c10190c */
/*0500*/ LDG.E R10, [R2.64+0x38] ; /* 0x0000380c020a7981 */
/* 0x000f28000c1e1900 */
/*0510*/ LDG.E R13, [R6.64+0x38] ; /* 0x0000380c060d7981 */
/* 0x004f22000c1e1900 */
/*0520*/ IADD3 R12, P1, R2, 0x40, RZ ; /* 0x00000040020c7810 */
/* 0x000fe40007f3e0ff */
/*0530*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fe20007ffe0ff */
/*0540*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0550*/ STG.E [R4.64+0x38], R13 ; /* 0x0000380d04007986 */
/* 0x000fe8000c10190c */
/*0560*/ LDG.E R10, [R2.64+0x3c] ; /* 0x00003c0c020a7981 */
/* 0x0002a8000c1e1900 */
/*0570*/ LDG.E R15, [R6.64+0x3c] ; /* 0x00003c0c060f7981 */
/* 0x0086a2000c1e1900 */
/*0580*/ IADD3.X R11, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff0b7210 */
/* 0x001fe20000ffe4ff */
/*0590*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*05a0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fc40003f24270 */
/*05b0*/ IADD3 R9, P3, R4, 0x40, RZ ; /* 0x0000004004097810 */
/* 0x000fe20007f7e0ff */
/*05c0*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x002fe200078e000c */
/*05d0*/ IADD3 R14, P2, R6, 0x40, RZ ; /* 0x00000040060e7810 */
/* 0x000fe40007f5e0ff */
/*05e0*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fc60000000f00 */
/*05f0*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x008fe400010e0607 */
/*0600*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000e */
/*0610*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x004fe20000000000 */
/*0620*/ IADD3.X R10, RZ, R5, RZ, P3, !PT ; /* 0x00000005ff0a7210 */
/* 0x000fc80001ffe4ff */
/*0630*/ STG.E [R4.64+0x3c], R15 ; /* 0x00003c0f04007986 */
/* 0x0001e4000c10190c */
/*0640*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x001fe20000000f00 */
/*0650*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000a */
/*0660*/ @P1 BRA 0x180 ; /* 0xfffffb1000001947 */
/* 0x000fea000383ffff */
/*0670*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0680*/ @!P1 BRA 0x970 ; /* 0x000002e000009947 */
/* 0x000fea0003800000 */
/*0690*/ LDG.E R9, [R2.64] ; /* 0x0000000c02097981 */
/* 0x000ea8000c1e1900 */
/*06a0*/ LDG.E R10, [R6.64] ; /* 0x0000000c060a7981 */
/* 0x000ea4000c1e1900 */
/*06b0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x004fca0000000000 */
/*06c0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e8000c10190c */
/*06d0*/ LDG.E R10, [R2.64+0x4] ; /* 0x0000040c020a7981 */
/* 0x000ea8000c1e1900 */
/*06e0*/ LDG.E R11, [R6.64+0x4] ; /* 0x0000040c060b7981 */
/* 0x000ea4000c1e1900 */
/*06f0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*0700*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0003e8000c10190c */
/*0710*/ LDG.E R10, [R2.64+0x8] ; /* 0x0000080c020a7981 */
/* 0x000ea8000c1e1900 */
/*0720*/ LDG.E R13, [R6.64+0x8] ; /* 0x0000080c060d7981 */
/* 0x000ea4000c1e1900 */
/*0730*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x004fca0000000000 */
/*0740*/ STG.E [R4.64+0x8], R13 ; /* 0x0000080d04007986 */
/* 0x0005e8000c10190c */
/*0750*/ LDG.E R10, [R2.64+0xc] ; /* 0x00000c0c020a7981 */
/* 0x000ee8000c1e1900 */
/*0760*/ LDG.E R15, [R6.64+0xc] ; /* 0x00000c0c060f7981 */
/* 0x000ee4000c1e1900 */
/*0770*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x008fca0000000000 */
/*0780*/ STG.E [R4.64+0xc], R15 ; /* 0x00000c0f04007986 */
/* 0x0007e8000c10190c */
/*0790*/ LDG.E R9, [R2.64+0x10] ; /* 0x0000100c02097981 */
/* 0x001f28000c1e1900 */
/*07a0*/ LDG.E R10, [R6.64+0x10] ; /* 0x0000100c060a7981 */
/* 0x000f24000c1e1900 */
/*07b0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*07c0*/ STG.E [R4.64+0x10], R9 ; /* 0x0000100904007986 */
/* 0x000fe8000c10190c */
/*07d0*/ LDG.E R10, [R2.64+0x14] ; /* 0x0000140c020a7981 */
/* 0x000f28000c1e1900 */
/*07e0*/ LDG.E R11, [R6.64+0x14] ; /* 0x0000140c060b7981 */
/* 0x002f24000c1e1900 */
/*07f0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*0800*/ STG.E [R4.64+0x14], R11 ; /* 0x0000140b04007986 */
/* 0x0001e8000c10190c */
/*0810*/ LDG.E R10, [R2.64+0x18] ; /* 0x0000180c020a7981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R13, [R6.64+0x18] ; /* 0x0000180c060d7981 */
/* 0x004f24000c1e1900 */
/*0830*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0840*/ STG.E [R4.64+0x18], R13 ; /* 0x0000180d04007986 */
/* 0x000fe8000c10190c */
/*0850*/ LDG.E R10, [R2.64+0x1c] ; /* 0x00001c0c020a7981 */
/* 0x0002a8000c1e1900 */
/*0860*/ LDG.E R15, [R6.64+0x1c] ; /* 0x00001c0c060f7981 */
/* 0x0086a2000c1e1900 */
/*0870*/ IADD3 R11, P2, R2, 0x20, RZ ; /* 0x00000020020b7810 */
/* 0x001fe20007f5e0ff */
/*0880*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0890*/ IADD3 R9, P3, R4, 0x20, RZ ; /* 0x0000002004097810 */
/* 0x000fc40007f7e0ff */
/*08a0*/ IADD3 R14, P1, R6, 0x20, RZ ; /* 0x00000020060e7810 */
/* 0x000fe20007f3e0ff */
/*08b0*/ IMAD.X R12, RZ, RZ, R3, P2 ; /* 0x000000ffff0c7224 */
/* 0x000fe200010e0603 */
/*08c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*08d0*/ IMAD.MOV.U32 R2, RZ, RZ, R11 ; /* 0x000000ffff027224 */
/* 0x002fe200078e000b */
/*08e0*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe20007ffe0ff */
/*08f0*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x008fe200078e000e */
/*0900*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe40000ffe4ff */
/*0910*/ MOV R3, R12 ; /* 0x0000000c00037202 */
/* 0x000fe20000000f00 */
/*0920*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x004fe20000000000 */
/*0930*/ IADD3.X R10, RZ, R5, RZ, P3, !PT ; /* 0x00000005ff0a7210 */
/* 0x000fc80001ffe4ff */
/*0940*/ STG.E [R4.64+0x1c], R15 ; /* 0x00001c0f04007986 */
/* 0x0001e4000c10190c */
/*0950*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x001fe20000000f00 */
/*0960*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000a */
/*0970*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*0980*/ @!P0 BRA 0xb80 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0990*/ LDG.E R9, [R2.64] ; /* 0x0000000c02097981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ LDG.E R10, [R6.64] ; /* 0x0000000c060a7981 */
/* 0x000ea4000c1e1900 */
/*09b0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x004fca0000000000 */
/*09c0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe8000c10190c */
/*09d0*/ LDG.E R10, [R2.64+0x4] ; /* 0x0000040c020a7981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R11, [R6.64+0x4] ; /* 0x0000040c060b7981 */
/* 0x000ea4000c1e1900 */
/*09f0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*0a00*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0001e8000c10190c */
/*0a10*/ LDG.E R10, [R2.64+0x8] ; /* 0x0000080c020a7981 */
/* 0x000ea8000c1e1900 */
/*0a20*/ LDG.E R13, [R6.64+0x8] ; /* 0x0000080c060d7981 */
/* 0x000ea2000c1e1900 */
/*0a30*/ IADD3 R12, P0, R2, 0x10, RZ ; /* 0x00000010020c7810 */
/* 0x000fe40007f1e0ff */
/*0a40*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe20007ffe0ff */
/*0a50*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x004fca0000000000 */
/*0a60*/ STG.E [R4.64+0x8], R13 ; /* 0x0000080d04007986 */
/* 0x000fe8000c10190c */
/*0a70*/ LDG.E R10, [R2.64+0xc] ; /* 0x00000c0c020a7981 */
/* 0x0002a8000c1e1900 */
/*0a80*/ LDG.E R15, [R6.64+0xc] ; /* 0x00000c0c060f7981 */
/* 0x0006a2000c1e1900 */
/*0a90*/ IADD3.X R11, RZ, R3, RZ, P0, !PT ; /* 0x00000003ff0b7210 */
/* 0x001fe200007fe4ff */
/*0aa0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0ab0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc40003f05270 */
/*0ac0*/ IADD3 R9, P2, R4, 0x10, RZ ; /* 0x0000001004097810 */
/* 0x000fe20007f5e0ff */
/*0ad0*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x002fe200078e000c */
/*0ae0*/ IADD3 R14, P1, R6, 0x10, RZ ; /* 0x00000010060e7810 */
/* 0x000fe40007f3e0ff */
/*0af0*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fc60000000f00 */
/*0b00*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x008fe400008e0607 */
/*0b10*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000e */
/*0b20*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x004fe20000000000 */
/*0b30*/ IADD3.X R10, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff0a7210 */
/* 0x000fc800017fe4ff */
/*0b40*/ STG.E [R4.64+0xc], R15 ; /* 0x00000c0f04007986 */
/* 0x0001e4000c10190c */
/*0b50*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x001fe20000000f00 */
/*0b60*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000a */
/*0b70*/ @P0 BRA 0x990 ; /* 0xfffffe1000000947 */
/* 0x000fea000383ffff */
/*0b80*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0b90*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0ba0*/ UMOV UR5, 0x4 ; /* 0x0000000400057882 */
/* 0x000fe40000000000 */
/*0bb0*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe40000000a00 */
/*0bc0*/ ULDC.64 UR8, c[0x0][0x170] ; /* 0x00005c0000087ab9 */
/* 0x000fe40000000a00 */
/*0bd0*/ ULDC.64 UR10, c[0x0][0x168] ; /* 0x00005a00000a7ab9 */
/* 0x000fe40000000a00 */
/*0be0*/ UIMAD.WIDE UR6, UR4, UR5, UR6 ; /* 0x00000005040672a5 */
/* 0x000fe4000f8e0206 */
/*0bf0*/ UIMAD.WIDE UR8, UR4, UR5, UR8 ; /* 0x00000005040872a5 */
/* 0x000fc4000f8e0208 */
/*0c00*/ UIMAD.WIDE UR4, UR4, UR5, UR10 ; /* 0x00000005040472a5 */
/* 0x000fca000f8e020a */
/*0c10*/ MOV R2, UR8 ; /* 0x0000000800027c02 */
/* 0x000fe20008000f00 */
/*0c20*/ IMAD.U32 R5, RZ, RZ, UR5 ; /* 0x00000005ff057e24 */
/* 0x000fe2000f8e00ff */
/*0c30*/ MOV R4, UR4 ; /* 0x0000000400047c02 */
/* 0x000fe20008000f00 */
/*0c40*/ IMAD.U32 R3, RZ, RZ, UR9 ; /* 0x00000009ff037e24 */
/* 0x000fc8000f8e00ff */
/*0c50*/ LDG.E R5, [R4.64] ; /* 0x0000000c04057981 */
/* 0x000ea8000c1e1900 */
/*0c60*/ LDG.E R2, [R2.64] ; /* 0x0000000c02027981 */
/* 0x000ea2000c1e1900 */
/*0c70*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc80007ffe0ff */
/*0c80*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0c90*/ UIADD3 UR8, UP1, UR8, 0x4, URZ ; /* 0x0000000408087890 */
/* 0x000fe2000ff3e03f */
/*0ca0*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x001fe20008000f00 */
/*0cb0*/ UIADD3 UR6, UP0, UR6, 0x4, URZ ; /* 0x0000000406067890 */
/* 0x000fe2000ff1e03f */
/*0cc0*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fe20008000f00 */
/*0cd0*/ UIADD3 UR4, UP2, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe4000ff5e03f */
/*0ce0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe400087fe43f */
/*0cf0*/ UIADD3.X UR9, URZ, UR9, URZ, UP1, !UPT ; /* 0x000000093f097290 */
/* 0x000fe40008ffe43f */
/*0d00*/ UIADD3.X UR5, URZ, UR5, URZ, UP2, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200097fe43f */
/*0d10*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*0d20*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e2000c10190c */
/*0d30*/ @P0 BRA 0xc10 ; /* 0xfffffed000000947 */
/* 0x000fea000383ffff */
/*0d40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d50*/ BRA 0xd50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10vector_addPfS_S_i
.globl _Z10vector_addPfS_S_i
.p2align 8
.type _Z10vector_addPfS_S_i,@function
_Z10vector_addPfS_S_i:
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v0, 0
.LBB0_2:
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[6:7]
global_load_b32 v2, v0, s[0:1]
s_add_i32 s2, s2, -1
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[4:5]
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s2, 0
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10vector_addPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10vector_addPfS_S_i, .Lfunc_end0-_Z10vector_addPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10vector_addPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z10vector_addPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000951e2_00000000-6_vector_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
.type _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10vector_addPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i, .-_Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
.globl _Z10vector_addPfS_S_i
.type _Z10vector_addPfS_S_i, @function
_Z10vector_addPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10vector_addPfS_S_i, .-_Z10vector_addPfS_S_i
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movl $40000000, %edi
call malloc@PLT
movq %rax, %rbx
movl $40000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $40000000, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %eax
movss .LC0(%rip), %xmm1
movss .LC1(%rip), %xmm0
.L12:
movss %xmm1, (%rbx,%rax)
movss %xmm0, 0(%rbp,%rax)
addq $4, %rax
cmpq $40000000, %rax
jne .L12
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L13:
movl $0, %eax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl $10000000, %ecx
movq %rbp, %rdx
movq %rbx, %rsi
movq %r12, %rdi
call _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
jmp .L13
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z10vector_addPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10vector_addPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.align 4
.LC1:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vector_add.hip"
.globl _Z25__device_stub__vector_addPfS_S_i # -- Begin function _Z25__device_stub__vector_addPfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__vector_addPfS_S_i,@function
_Z25__device_stub__vector_addPfS_S_i: # @_Z25__device_stub__vector_addPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10vector_addPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__vector_addPfS_S_i, .Lfunc_end0-_Z25__device_stub__vector_addPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $40000000, %edi # imm = 0x2625A00
callq malloc
movq %rax, %rbx
movl $40000000, %edi # imm = 0x2625A00
callq malloc
movq %rax, %r14
movl $40000000, %edi # imm = 0x2625A00
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
movl $1073741824, (%r14,%rax,4) # imm = 0x40000000
incq %rax
cmpq $10000000, %rax # imm = 0x989680
jne .LBB1_1
# %bb.2:
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq %r15, 72(%rsp)
movq %rbx, 64(%rsp)
movq %r14, 56(%rsp)
movl $10000000, 4(%rsp) # imm = 0x989680
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10vector_addPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10vector_addPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10vector_addPfS_S_i,@object # @_Z10vector_addPfS_S_i
.section .rodata,"a",@progbits
.globl _Z10vector_addPfS_S_i
.p2align 3, 0x0
_Z10vector_addPfS_S_i:
.quad _Z25__device_stub__vector_addPfS_S_i
.size _Z10vector_addPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10vector_addPfS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__vector_addPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10vector_addPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/*
* Copyright 1993-2010 NVIDIA Corporation. All rights reserved.
*
* NVIDIA Corporation and its licensors retain all intellectual property and
* proprietary rights in and to this software and related documentation.
* Any use, reproduction, disclosure, or distribution of this software
* and related documentation without an express license agreement from
* NVIDIA Corporation is strictly prohibited.
*
* Please refer to the applicable NVIDIA end user license agreement (EULA)
* associated with this source code for terms and conditions that govern
* your use of this NVIDIA software.
*
*/
#define N (1024*1024)
#define FULL_DATA_SIZE (N*20)
__global__ void kernel( int *a, int *b, int *c ) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < N) {
int idx1 = (idx + 1) % 256;
int idx2 = (idx + 2) % 256;
float as = (a[idx] + a[idx1] + a[idx2]) / 3.0f;
float bs = (b[idx] + b[idx1] + b[idx2]) / 3.0f;
c[idx] = (as + bs) / 2;
}
} | code for sm_80
Function : _Z6kernelPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0xfffff, PT ; /* 0x000fffff0000780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R3, R0.reuse, 0x1, RZ ; /* 0x0000000100037810 */
/* 0x040fe20007ffe0ff */
/*0070*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0080*/ IADD3 R4, R0, 0x2, RZ ; /* 0x0000000200047810 */
/* 0x000fe20007ffe0ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ SHF.R.S32.HI R2, RZ, 0x1f, R3 ; /* 0x0000001fff027819 */
/* 0x000fe40000011403 */
/*00b0*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fe40000011404 */
/*00c0*/ LEA.HI R2, R2, R3, RZ, 0x8 ; /* 0x0000000302027211 */
/* 0x000fe400078f40ff */
/*00d0*/ LEA.HI R5, R5, R4, RZ, 0x8 ; /* 0x0000000405057211 */
/* 0x000fc400078f40ff */
/*00e0*/ LOP3.LUT R2, R2, 0xffffff00, RZ, 0xc0, !PT ; /* 0xffffff0002027812 */
/* 0x000fe400078ec0ff */
/*00f0*/ LOP3.LUT R5, R5, 0xffffff00, RZ, 0xc0, !PT ; /* 0xffffff0005057812 */
/* 0x000fc600078ec0ff */
/*0100*/ IMAD.IADD R3, R3, 0x1, -R2 ; /* 0x0000000103037824 */
/* 0x000fe400078e0a02 */
/*0110*/ IMAD.IADD R2, R4, 0x1, -R5 ; /* 0x0000000104027824 */
/* 0x000fe400078e0a05 */
/*0120*/ IMAD.WIDE R4, R0, R9, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e0209 */
/*0130*/ IMAD.WIDE R6, R3, R9.reuse, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x080fe400078e0209 */
/*0140*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*0150*/ IMAD.WIDE R8, R2, R9, c[0x0][0x160] ; /* 0x0000580002087625 */
/* 0x000fe400078e0209 */
/*0160*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1900 */
/*0180*/ IMAD.MOV.U32 R12, RZ, RZ, 0x3eaaaaab ; /* 0x3eaaaaabff0c7424 */
/* 0x000fc400078e00ff */
/*0190*/ IMAD.MOV.U32 R13, RZ, RZ, 0x40400000 ; /* 0x40400000ff0d7424 */
/* 0x000fc800078e00ff */
/*01a0*/ FFMA R11, R12, -R13, 1 ; /* 0x3f8000000c0b7423 */
/* 0x000fc8000000080d */
/*01b0*/ FFMA R11, R11, R12, 0.3333333432674407959 ; /* 0x3eaaaaab0b0b7423 */
/* 0x000fe2000000000c */
/*01c0*/ BSSY B0, 0x280 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*01d0*/ IADD3 R10, R8, R6, R5 ; /* 0x00000006080a7210 */
/* 0x004fcc0007ffe005 */
/*01e0*/ I2F R10, R10 ; /* 0x0000000a000a7306 */
/* 0x000e300000201400 */
/*01f0*/ FCHK P0, R10, 3 ; /* 0x404000000a007902 */
/* 0x001e220000000000 */
/*0200*/ FFMA R12, R10, R11, RZ ; /* 0x0000000b0a0c7223 */
/* 0x000fc800000000ff */
/*0210*/ FFMA R4, R12, -3, R10 ; /* 0xc04000000c047823 */
/* 0x000fc8000000000a */
/*0220*/ FFMA R4, R11, R4, R12 ; /* 0x000000040b047223 */
/* 0x000fe2000000000c */
/*0230*/ @!P0 BRA 0x270 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*0240*/ MOV R6, 0x260 ; /* 0x0000026000067802 */
/* 0x000fe40000000f00 */
/*0250*/ CALL.REL.NOINC 0x470 ; /* 0x0000021000007944 */
/* 0x000fea0003c00000 */
/*0260*/ IMAD.MOV.U32 R4, RZ, RZ, R5 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0005 */
/*0270*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0280*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0290*/ IMAD.WIDE R8, R3, R5, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fc800078e0205 */
/*02a0*/ IMAD.WIDE R6, R0, R5.reuse, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x080fe400078e0205 */
/*02b0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea4000c1e1900 */
/*02c0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fe400078e0205 */
/*02d0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea8000c1e1900 */
/*02e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*02f0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x3eaaaaab ; /* 0x3eaaaaabff0a7424 */
/* 0x000fc400078e00ff */
/*0300*/ IMAD.MOV.U32 R13, RZ, RZ, 0x40400000 ; /* 0x40400000ff0d7424 */
/* 0x000fc800078e00ff */
/*0310*/ FFMA R11, R10, -R13, 1 ; /* 0x3f8000000a0b7423 */
/* 0x000fc8000000080d */
/*0320*/ FFMA R12, R11, R10, 0.3333333432674407959 ; /* 0x3eaaaaab0b0c7423 */
/* 0x000fe2000000000a */
/*0330*/ BSSY B0, 0x400 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*0340*/ IADD3 R5, R2, R8, R7 ; /* 0x0000000802057210 */
/* 0x004fcc0007ffe007 */
/*0350*/ I2F R5, R5 ; /* 0x0000000500057306 */
/* 0x000e300000201400 */
/*0360*/ FCHK P0, R5, 3 ; /* 0x4040000005007902 */
/* 0x001e220000000000 */
/*0370*/ FFMA R10, R12, R5, RZ ; /* 0x000000050c0a7223 */
/* 0x000fc800000000ff */
/*0380*/ FFMA R9, R10, -3, R5 ; /* 0xc04000000a097823 */
/* 0x000fc80000000005 */
/*0390*/ FFMA R9, R12, R9, R10 ; /* 0x000000090c097223 */
/* 0x000fe2000000000a */
/*03a0*/ @!P0 BRA 0x3f0 ; /* 0x0000004000008947 */
/* 0x001fea0003800000 */
/*03b0*/ IMAD.MOV.U32 R10, RZ, RZ, R5 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0005 */
/*03c0*/ MOV R6, 0x3e0 ; /* 0x000003e000067802 */
/* 0x000fe40000000f00 */
/*03d0*/ CALL.REL.NOINC 0x470 ; /* 0x0000009000007944 */
/* 0x000fea0003c00000 */
/*03e0*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x001fe400078e0005 */
/*03f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0400*/ FADD R4, R9, R4 ; /* 0x0000000409047221 */
/* 0x000fe40000000000 */
/*0410*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*0420*/ FMUL R4, R4, 0.5 ; /* 0x3f00000004047820 */
/* 0x000fe40000400000 */
/*0430*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fe400078e0203 */
/*0440*/ F2I.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000e26000020f100 */
/*0450*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0460*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0470*/ SHF.R.U32.HI R7, RZ, 0x17, R13.reuse ; /* 0x00000017ff077819 */
/* 0x100fe2000001160d */
/*0480*/ BSSY B1, 0xad0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0490*/ SHF.R.U32.HI R5, RZ, 0x17, R10 ; /* 0x00000017ff057819 */
/* 0x000fe2000001160a */
/*04a0*/ IMAD.MOV.U32 R8, RZ, RZ, R13 ; /* 0x000000ffff087224 */
/* 0x000fe200078e000d */
/*04b0*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fc400078ec0ff */
/*04c0*/ LOP3.LUT R14, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff050e7812 */
/* 0x000fe200078ec0ff */
/*04d0*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000a */
/*04e0*/ IADD3 R11, R7, -0x1, RZ ; /* 0xffffffff070b7810 */
/* 0x000fe40007ffe0ff */
/*04f0*/ IADD3 R12, R14, -0x1, RZ ; /* 0xffffffff0e0c7810 */
/* 0x000fe40007ffe0ff */
/*0500*/ ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; /* 0x000000fd0b00780c */
/* 0x000fc80003f04070 */
/*0510*/ ISETP.GT.U32.OR P0, PT, R12, 0xfd, P0 ; /* 0x000000fd0c00780c */
/* 0x000fda0000704470 */
/*0520*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*0530*/ @!P0 BRA 0x6b0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0540*/ FSETP.GTU.FTZ.AND P0, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fe40003f1c200 */
/*0550*/ FSETP.GTU.FTZ.AND P1, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fc80003f3c200 */
/*0560*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0570*/ @P0 BRA 0xab0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0580*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R5, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c805 */
/*0590*/ @!P0 BRA 0xa90 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*05a0*/ FSETP.NEU.FTZ.AND P2, PT, |R10|.reuse, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x040fe40003f5d200 */
/*05b0*/ FSETP.NEU.FTZ.AND P1, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fe40003f3d200 */
/*05c0*/ FSETP.NEU.FTZ.AND P0, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fd60003f1d200 */
/*05d0*/ @!P1 BRA !P2, 0xa90 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*05e0*/ LOP3.LUT P2, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fc8000784c0ff */
/*05f0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0600*/ @P1 BRA 0xa70 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0610*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*0620*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0630*/ @P0 BRA 0xa40 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0640*/ ISETP.GE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f06270 */
/*0650*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f26270 */
/*0660*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*0670*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*0680*/ @!P0 FFMA R5, R10, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000a058823 */
/* 0x000fe400000000ff */
/*0690*/ @!P1 FFMA R8, R13, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000d089823 */
/* 0x000fe200000000ff */
/*06a0*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*06b0*/ LEA R11, R7, 0xc0800000, 0x17 ; /* 0xc0800000070b7811 */
/* 0x000fe200078eb8ff */
/*06c0*/ BSSY B2, 0xa30 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*06d0*/ IMAD.IADD R11, R8, 0x1, -R11 ; /* 0x00000001080b7824 */
/* 0x000fe200078e0a0b */
/*06e0*/ IADD3 R8, R14, -0x7f, RZ ; /* 0xffffff810e087810 */
/* 0x000fc60007ffe0ff */
/*06f0*/ MUFU.RCP R10, R11 ; /* 0x0000000b000a7308 */
/* 0x000e220000001000 */
/*0700*/ FADD.FTZ R12, -R11, -RZ ; /* 0x800000ff0b0c7221 */
/* 0x000fe40000010100 */
/*0710*/ IMAD R5, R8.reuse, -0x800000, R5 ; /* 0xff80000008057824 */
/* 0x040fe200078e0205 */
/*0720*/ IADD3 R8, R8, 0x7f, -R7 ; /* 0x0000007f08087810 */
/* 0x000fca0007ffe807 */
/*0730*/ IMAD.IADD R8, R8, 0x1, R9 ; /* 0x0000000108087824 */
/* 0x000fe400078e0209 */
/*0740*/ FFMA R13, R10, R12, 1 ; /* 0x3f8000000a0d7423 */
/* 0x001fc8000000000c */
/*0750*/ FFMA R14, R10, R13, R10 ; /* 0x0000000d0a0e7223 */
/* 0x000fc8000000000a */
/*0760*/ FFMA R10, R5, R14, RZ ; /* 0x0000000e050a7223 */
/* 0x000fc800000000ff */
/*0770*/ FFMA R13, R12, R10, R5 ; /* 0x0000000a0c0d7223 */
/* 0x000fc80000000005 */
/*0780*/ FFMA R13, R14, R13, R10 ; /* 0x0000000d0e0d7223 */
/* 0x000fc8000000000a */
/*0790*/ FFMA R12, R12, R13, R5 ; /* 0x0000000d0c0c7223 */
/* 0x000fc80000000005 */
/*07a0*/ FFMA R5, R14, R12, R13 ; /* 0x0000000c0e057223 */
/* 0x000fca000000000d */
/*07b0*/ SHF.R.U32.HI R7, RZ, 0x17, R5 ; /* 0x00000017ff077819 */
/* 0x000fc80000011605 */
/*07c0*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fca00078ec0ff */
/*07d0*/ IMAD.IADD R11, R7, 0x1, R8 ; /* 0x00000001070b7824 */
/* 0x000fca00078e0208 */
/*07e0*/ IADD3 R7, R11, -0x1, RZ ; /* 0xffffffff0b077810 */
/* 0x000fc80007ffe0ff */
/*07f0*/ ISETP.GE.U32.AND P0, PT, R7, 0xfe, PT ; /* 0x000000fe0700780c */
/* 0x000fda0003f06070 */
/*0800*/ @!P0 BRA 0xa10 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0810*/ ISETP.GT.AND P0, PT, R11, 0xfe, PT ; /* 0x000000fe0b00780c */
/* 0x000fda0003f04270 */
/*0820*/ @P0 BRA 0x9e0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0830*/ ISETP.GE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fda0003f06270 */
/*0840*/ @P0 BRA 0xa20 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0850*/ ISETP.GE.AND P0, PT, R11, -0x18, PT ; /* 0xffffffe80b00780c */
/* 0x000fe40003f06270 */
/*0860*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fd600078ec0ff */
/*0870*/ @!P0 BRA 0xa20 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0880*/ FFMA.RZ R7, R14.reuse, R12.reuse, R13.reuse ; /* 0x0000000c0e077223 */
/* 0x1c0fe2000000c00d */
/*0890*/ IADD3 R10, R11.reuse, 0x20, RZ ; /* 0x000000200b0a7810 */
/* 0x040fe20007ffe0ff */
/*08a0*/ FFMA.RM R8, R14.reuse, R12.reuse, R13.reuse ; /* 0x0000000c0e087223 */
/* 0x1c0fe2000000400d */
/*08b0*/ ISETP.NE.AND P2, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f45270 */
/*08c0*/ LOP3.LUT R9, R7, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff07097812 */
/* 0x000fe200078ec0ff */
/*08d0*/ FFMA.RP R7, R14, R12, R13 ; /* 0x0000000c0e077223 */
/* 0x000fe2000000800d */
/*08e0*/ ISETP.NE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f25270 */
/*08f0*/ IMAD.MOV R11, RZ, RZ, -R11 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a0b */
/*0900*/ LOP3.LUT R9, R9, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000009097812 */
/* 0x000fe400078efcff */
/*0910*/ FSETP.NEU.FTZ.AND P0, PT, R7, R8, PT ; /* 0x000000080700720b */
/* 0x000fc40003f1d000 */
/*0920*/ SHF.L.U32 R10, R9, R10, RZ ; /* 0x0000000a090a7219 */
/* 0x000fe400000006ff */
/*0930*/ SEL R8, R11, RZ, P2 ; /* 0x000000ff0b087207 */
/* 0x000fe40001000000 */
/*0940*/ ISETP.NE.AND P1, PT, R10, RZ, P1 ; /* 0x000000ff0a00720c */
/* 0x000fe40000f25270 */
/*0950*/ SHF.R.U32.HI R8, RZ, R8, R9 ; /* 0x00000008ff087219 */
/* 0x000fe40000011609 */
/*0960*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0970*/ SHF.R.U32.HI R10, RZ, 0x1, R8 ; /* 0x00000001ff0a7819 */
/* 0x000fc40000011608 */
/*0980*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fc80004000000 */
/*0990*/ LOP3.LUT R7, R7, 0x1, R10, 0xf8, !PT ; /* 0x0000000107077812 */
/* 0x000fc800078ef80a */
/*09a0*/ LOP3.LUT R7, R7, R8, RZ, 0xc0, !PT ; /* 0x0000000807077212 */
/* 0x000fca00078ec0ff */
/*09b0*/ IMAD.IADD R10, R10, 0x1, R7 ; /* 0x000000010a0a7824 */
/* 0x000fca00078e0207 */
/*09c0*/ LOP3.LUT R5, R10, R5, RZ, 0xfc, !PT ; /* 0x000000050a057212 */
/* 0x000fe200078efcff */
/*09d0*/ BRA 0xa20 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*09e0*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fc800078ec0ff */
/*09f0*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*0a00*/ BRA 0xa20 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0a10*/ IMAD R5, R8, 0x800000, R5 ; /* 0x0080000008057824 */
/* 0x000fe400078e0205 */
/*0a20*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0a30*/ BRA 0xac0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0a40*/ LOP3.LUT R5, R8, 0x80000000, R5, 0x48, !PT ; /* 0x8000000008057812 */
/* 0x000fc800078e4805 */
/*0a50*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*0a60*/ BRA 0xac0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0a70*/ LOP3.LUT R5, R8, 0x80000000, R5, 0x48, !PT ; /* 0x8000000008057812 */
/* 0x000fe200078e4805 */
/*0a80*/ BRA 0xac0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0a90*/ MUFU.RSQ R5, -QNAN ; /* 0xffc0000000057908 */
/* 0x000e220000001400 */
/*0aa0*/ BRA 0xac0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0ab0*/ FADD.FTZ R5, R10, R13 ; /* 0x0000000d0a057221 */
/* 0x000fe40000010000 */
/*0ac0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0ad0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc800078e00ff */
/*0ae0*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff51006007950 */
/* 0x000fea0003c3ffff */
/*0af0*/ BRA 0xaf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/*
* Copyright 1993-2010 NVIDIA Corporation. All rights reserved.
*
* NVIDIA Corporation and its licensors retain all intellectual property and
* proprietary rights in and to this software and related documentation.
* Any use, reproduction, disclosure, or distribution of this software
* and related documentation without an express license agreement from
* NVIDIA Corporation is strictly prohibited.
*
* Please refer to the applicable NVIDIA end user license agreement (EULA)
* associated with this source code for terms and conditions that govern
* your use of this NVIDIA software.
*
*/
#define N (1024*1024)
#define FULL_DATA_SIZE (N*20)
__global__ void kernel( int *a, int *b, int *c ) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < N) {
int idx1 = (idx + 1) % 256;
int idx2 = (idx + 2) % 256;
float as = (a[idx] + a[idx1] + a[idx2]) / 3.0f;
float bs = (b[idx] + b[idx1] + b[idx2]) / 3.0f;
c[idx] = (as + bs) / 2;
}
} | .file "tmpxft_0014693e_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6kernelPiS_S_PiS_S_
.type _Z29__device_stub__Z6kernelPiS_S_PiS_S_, @function
_Z29__device_stub__Z6kernelPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z6kernelPiS_S_PiS_S_, .-_Z29__device_stub__Z6kernelPiS_S_PiS_S_
.globl _Z6kernelPiS_S_
.type _Z6kernelPiS_S_, @function
_Z6kernelPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6kernelPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6kernelPiS_S_, .-_Z6kernelPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/*
* Copyright 1993-2010 NVIDIA Corporation. All rights reserved.
*
* NVIDIA Corporation and its licensors retain all intellectual property and
* proprietary rights in and to this software and related documentation.
* Any use, reproduction, disclosure, or distribution of this software
* and related documentation without an express license agreement from
* NVIDIA Corporation is strictly prohibited.
*
* Please refer to the applicable NVIDIA end user license agreement (EULA)
* associated with this source code for terms and conditions that govern
* your use of this NVIDIA software.
*
*/
#define N (1024*1024)
#define FULL_DATA_SIZE (N*20)
__global__ void kernel( int *a, int *b, int *c ) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < N) {
int idx1 = (idx + 1) % 256;
int idx2 = (idx + 2) % 256;
float as = (a[idx] + a[idx1] + a[idx2]) / 3.0f;
float bs = (b[idx] + b[idx1] + b[idx2]) / 3.0f;
c[idx] = (as + bs) / 2;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
/*
* Copyright 1993-2010 NVIDIA Corporation. All rights reserved.
*
* NVIDIA Corporation and its licensors retain all intellectual property and
* proprietary rights in and to this software and related documentation.
* Any use, reproduction, disclosure, or distribution of this software
* and related documentation without an express license agreement from
* NVIDIA Corporation is strictly prohibited.
*
* Please refer to the applicable NVIDIA end user license agreement (EULA)
* associated with this source code for terms and conditions that govern
* your use of this NVIDIA software.
*
*/
#define N (1024*1024)
#define FULL_DATA_SIZE (N*20)
__global__ void kernel( int *a, int *b, int *c ) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < N) {
int idx1 = (idx + 1) % 256;
int idx2 = (idx + 2) % 256;
float as = (a[idx] + a[idx1] + a[idx2]) / 3.0f;
float bs = (b[idx] + b[idx1] + b[idx2]) / 3.0f;
c[idx] = (as + bs) / 2;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/*
* Copyright 1993-2010 NVIDIA Corporation. All rights reserved.
*
* NVIDIA Corporation and its licensors retain all intellectual property and
* proprietary rights in and to this software and related documentation.
* Any use, reproduction, disclosure, or distribution of this software
* and related documentation without an express license agreement from
* NVIDIA Corporation is strictly prohibited.
*
* Please refer to the applicable NVIDIA end user license agreement (EULA)
* associated with this source code for terms and conditions that govern
* your use of this NVIDIA software.
*
*/
#define N (1024*1024)
#define FULL_DATA_SIZE (N*20)
__global__ void kernel( int *a, int *b, int *c ) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < N) {
int idx1 = (idx + 1) % 256;
int idx2 = (idx + 2) % 256;
float as = (a[idx] + a[idx1] + a[idx2]) / 3.0f;
float bs = (b[idx] + b[idx1] + b[idx2]) / 3.0f;
c[idx] = (as + bs) / 2;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPiS_S_
.globl _Z6kernelPiS_S_
.p2align 8
.type _Z6kernelPiS_S_,@function
_Z6kernelPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x100000, v1
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v0, 1, v1
v_add_nc_u32_e32 v4, 2, v1
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v0
v_ashrrev_i32_e32 v3, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshrrev_b32_e32 v2, 24, v2
v_lshrrev_b32_e32 v3, 24, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v0, v2
v_add_nc_u32_e32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v5, 0xffffff00, v2
v_and_b32_e32 v6, 0xffffff00, v3
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v0, v0, v5
v_sub_nc_u32_e32 v4, v4, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v5, 31, v4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v2
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v10, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v12, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
s_clause 0x2
global_load_b32 v6, v[6:7], off
global_load_b32 v7, v[10:11], off
global_load_b32 v10, v[12:13], off
s_clause 0x2
global_load_b32 v8, v[8:9], off
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v[4:5], off
s_waitcnt vmcnt(3)
v_add3_u32 v4, v7, v6, v10
s_waitcnt vmcnt(0)
v_add3_u32 v0, v0, v8, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v1, v4
v_cvt_f32_i32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_scale_f32 v4, null, 0x40400000, 0x40400000, v1
v_div_scale_f32 v10, vcc_lo, v1, 0x40400000, v1
v_div_scale_f32 v5, null, 0x40400000, 0x40400000, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v6, v4
v_rcp_f32_e32 v7, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v4, v6, 1.0
v_fma_f32 v9, -v5, v7, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v6, v8, v6
v_div_scale_f32 v8, s0, v0, 0x40400000, v0
v_fmac_f32_e32 v7, v9, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v9, v10, v6
v_mul_f32_e32 v11, v8, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v12, -v4, v9, v10
v_fma_f32 v13, -v5, v11, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v9, v12, v6
v_fmac_f32_e32 v11, v13, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v4, -v4, v9, v10
v_fma_f32 v5, -v5, v11, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v4, v4, v6, v9
s_mov_b32 vcc_lo, s0
v_div_fmas_f32 v5, v5, v7, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f32 v1, v4, 0x40400000, v1
v_div_fixup_f32 v0, v5, 0x40400000, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v1, v0
v_mul_f32_e32 v0, 0.5, v0
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v4, v0
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPiS_S_, .Lfunc_end0-_Z6kernelPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/*
* Copyright 1993-2010 NVIDIA Corporation. All rights reserved.
*
* NVIDIA Corporation and its licensors retain all intellectual property and
* proprietary rights in and to this software and related documentation.
* Any use, reproduction, disclosure, or distribution of this software
* and related documentation without an express license agreement from
* NVIDIA Corporation is strictly prohibited.
*
* Please refer to the applicable NVIDIA end user license agreement (EULA)
* associated with this source code for terms and conditions that govern
* your use of this NVIDIA software.
*
*/
#define N (1024*1024)
#define FULL_DATA_SIZE (N*20)
__global__ void kernel( int *a, int *b, int *c ) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < N) {
int idx1 = (idx + 1) % 256;
int idx2 = (idx + 2) % 256;
float as = (a[idx] + a[idx1] + a[idx2]) / 3.0f;
float bs = (b[idx] + b[idx1] + b[idx2]) / 3.0f;
c[idx] = (as + bs) / 2;
}
} | .text
.file "kernel.hip"
.globl _Z21__device_stub__kernelPiS_S_ # -- Begin function _Z21__device_stub__kernelPiS_S_
.p2align 4, 0x90
.type _Z21__device_stub__kernelPiS_S_,@function
_Z21__device_stub__kernelPiS_S_: # @_Z21__device_stub__kernelPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPiS_S_, .Lfunc_end0-_Z21__device_stub__kernelPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPiS_S_,@object # @_Z6kernelPiS_S_
.section .rodata,"a",@progbits
.globl _Z6kernelPiS_S_
.p2align 3, 0x0
_Z6kernelPiS_S_:
.quad _Z21__device_stub__kernelPiS_S_
.size _Z6kernelPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelPiS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0xfffff, PT ; /* 0x000fffff0000780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R3, R0.reuse, 0x1, RZ ; /* 0x0000000100037810 */
/* 0x040fe20007ffe0ff */
/*0070*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0080*/ IADD3 R4, R0, 0x2, RZ ; /* 0x0000000200047810 */
/* 0x000fe20007ffe0ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ SHF.R.S32.HI R2, RZ, 0x1f, R3 ; /* 0x0000001fff027819 */
/* 0x000fe40000011403 */
/*00b0*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fe40000011404 */
/*00c0*/ LEA.HI R2, R2, R3, RZ, 0x8 ; /* 0x0000000302027211 */
/* 0x000fe400078f40ff */
/*00d0*/ LEA.HI R5, R5, R4, RZ, 0x8 ; /* 0x0000000405057211 */
/* 0x000fc400078f40ff */
/*00e0*/ LOP3.LUT R2, R2, 0xffffff00, RZ, 0xc0, !PT ; /* 0xffffff0002027812 */
/* 0x000fe400078ec0ff */
/*00f0*/ LOP3.LUT R5, R5, 0xffffff00, RZ, 0xc0, !PT ; /* 0xffffff0005057812 */
/* 0x000fc600078ec0ff */
/*0100*/ IMAD.IADD R3, R3, 0x1, -R2 ; /* 0x0000000103037824 */
/* 0x000fe400078e0a02 */
/*0110*/ IMAD.IADD R2, R4, 0x1, -R5 ; /* 0x0000000104027824 */
/* 0x000fe400078e0a05 */
/*0120*/ IMAD.WIDE R4, R0, R9, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e0209 */
/*0130*/ IMAD.WIDE R6, R3, R9.reuse, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x080fe400078e0209 */
/*0140*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*0150*/ IMAD.WIDE R8, R2, R9, c[0x0][0x160] ; /* 0x0000580002087625 */
/* 0x000fe400078e0209 */
/*0160*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1900 */
/*0180*/ IMAD.MOV.U32 R12, RZ, RZ, 0x3eaaaaab ; /* 0x3eaaaaabff0c7424 */
/* 0x000fc400078e00ff */
/*0190*/ IMAD.MOV.U32 R13, RZ, RZ, 0x40400000 ; /* 0x40400000ff0d7424 */
/* 0x000fc800078e00ff */
/*01a0*/ FFMA R11, R12, -R13, 1 ; /* 0x3f8000000c0b7423 */
/* 0x000fc8000000080d */
/*01b0*/ FFMA R11, R11, R12, 0.3333333432674407959 ; /* 0x3eaaaaab0b0b7423 */
/* 0x000fe2000000000c */
/*01c0*/ BSSY B0, 0x280 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*01d0*/ IADD3 R10, R8, R6, R5 ; /* 0x00000006080a7210 */
/* 0x004fcc0007ffe005 */
/*01e0*/ I2F R10, R10 ; /* 0x0000000a000a7306 */
/* 0x000e300000201400 */
/*01f0*/ FCHK P0, R10, 3 ; /* 0x404000000a007902 */
/* 0x001e220000000000 */
/*0200*/ FFMA R12, R10, R11, RZ ; /* 0x0000000b0a0c7223 */
/* 0x000fc800000000ff */
/*0210*/ FFMA R4, R12, -3, R10 ; /* 0xc04000000c047823 */
/* 0x000fc8000000000a */
/*0220*/ FFMA R4, R11, R4, R12 ; /* 0x000000040b047223 */
/* 0x000fe2000000000c */
/*0230*/ @!P0 BRA 0x270 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*0240*/ MOV R6, 0x260 ; /* 0x0000026000067802 */
/* 0x000fe40000000f00 */
/*0250*/ CALL.REL.NOINC 0x470 ; /* 0x0000021000007944 */
/* 0x000fea0003c00000 */
/*0260*/ IMAD.MOV.U32 R4, RZ, RZ, R5 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0005 */
/*0270*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0280*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0290*/ IMAD.WIDE R8, R3, R5, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fc800078e0205 */
/*02a0*/ IMAD.WIDE R6, R0, R5.reuse, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x080fe400078e0205 */
/*02b0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea4000c1e1900 */
/*02c0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fe400078e0205 */
/*02d0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea8000c1e1900 */
/*02e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*02f0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x3eaaaaab ; /* 0x3eaaaaabff0a7424 */
/* 0x000fc400078e00ff */
/*0300*/ IMAD.MOV.U32 R13, RZ, RZ, 0x40400000 ; /* 0x40400000ff0d7424 */
/* 0x000fc800078e00ff */
/*0310*/ FFMA R11, R10, -R13, 1 ; /* 0x3f8000000a0b7423 */
/* 0x000fc8000000080d */
/*0320*/ FFMA R12, R11, R10, 0.3333333432674407959 ; /* 0x3eaaaaab0b0c7423 */
/* 0x000fe2000000000a */
/*0330*/ BSSY B0, 0x400 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*0340*/ IADD3 R5, R2, R8, R7 ; /* 0x0000000802057210 */
/* 0x004fcc0007ffe007 */
/*0350*/ I2F R5, R5 ; /* 0x0000000500057306 */
/* 0x000e300000201400 */
/*0360*/ FCHK P0, R5, 3 ; /* 0x4040000005007902 */
/* 0x001e220000000000 */
/*0370*/ FFMA R10, R12, R5, RZ ; /* 0x000000050c0a7223 */
/* 0x000fc800000000ff */
/*0380*/ FFMA R9, R10, -3, R5 ; /* 0xc04000000a097823 */
/* 0x000fc80000000005 */
/*0390*/ FFMA R9, R12, R9, R10 ; /* 0x000000090c097223 */
/* 0x000fe2000000000a */
/*03a0*/ @!P0 BRA 0x3f0 ; /* 0x0000004000008947 */
/* 0x001fea0003800000 */
/*03b0*/ IMAD.MOV.U32 R10, RZ, RZ, R5 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0005 */
/*03c0*/ MOV R6, 0x3e0 ; /* 0x000003e000067802 */
/* 0x000fe40000000f00 */
/*03d0*/ CALL.REL.NOINC 0x470 ; /* 0x0000009000007944 */
/* 0x000fea0003c00000 */
/*03e0*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x001fe400078e0005 */
/*03f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0400*/ FADD R4, R9, R4 ; /* 0x0000000409047221 */
/* 0x000fe40000000000 */
/*0410*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*0420*/ FMUL R4, R4, 0.5 ; /* 0x3f00000004047820 */
/* 0x000fe40000400000 */
/*0430*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fe400078e0203 */
/*0440*/ F2I.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000e26000020f100 */
/*0450*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0460*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0470*/ SHF.R.U32.HI R7, RZ, 0x17, R13.reuse ; /* 0x00000017ff077819 */
/* 0x100fe2000001160d */
/*0480*/ BSSY B1, 0xad0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0490*/ SHF.R.U32.HI R5, RZ, 0x17, R10 ; /* 0x00000017ff057819 */
/* 0x000fe2000001160a */
/*04a0*/ IMAD.MOV.U32 R8, RZ, RZ, R13 ; /* 0x000000ffff087224 */
/* 0x000fe200078e000d */
/*04b0*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fc400078ec0ff */
/*04c0*/ LOP3.LUT R14, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff050e7812 */
/* 0x000fe200078ec0ff */
/*04d0*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000a */
/*04e0*/ IADD3 R11, R7, -0x1, RZ ; /* 0xffffffff070b7810 */
/* 0x000fe40007ffe0ff */
/*04f0*/ IADD3 R12, R14, -0x1, RZ ; /* 0xffffffff0e0c7810 */
/* 0x000fe40007ffe0ff */
/*0500*/ ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; /* 0x000000fd0b00780c */
/* 0x000fc80003f04070 */
/*0510*/ ISETP.GT.U32.OR P0, PT, R12, 0xfd, P0 ; /* 0x000000fd0c00780c */
/* 0x000fda0000704470 */
/*0520*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*0530*/ @!P0 BRA 0x6b0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0540*/ FSETP.GTU.FTZ.AND P0, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fe40003f1c200 */
/*0550*/ FSETP.GTU.FTZ.AND P1, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fc80003f3c200 */
/*0560*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0570*/ @P0 BRA 0xab0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0580*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R5, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c805 */
/*0590*/ @!P0 BRA 0xa90 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*05a0*/ FSETP.NEU.FTZ.AND P2, PT, |R10|.reuse, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x040fe40003f5d200 */
/*05b0*/ FSETP.NEU.FTZ.AND P1, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fe40003f3d200 */
/*05c0*/ FSETP.NEU.FTZ.AND P0, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fd60003f1d200 */
/*05d0*/ @!P1 BRA !P2, 0xa90 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*05e0*/ LOP3.LUT P2, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fc8000784c0ff */
/*05f0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0600*/ @P1 BRA 0xa70 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0610*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*0620*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0630*/ @P0 BRA 0xa40 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0640*/ ISETP.GE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f06270 */
/*0650*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f26270 */
/*0660*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*0670*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*0680*/ @!P0 FFMA R5, R10, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000a058823 */
/* 0x000fe400000000ff */
/*0690*/ @!P1 FFMA R8, R13, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000d089823 */
/* 0x000fe200000000ff */
/*06a0*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*06b0*/ LEA R11, R7, 0xc0800000, 0x17 ; /* 0xc0800000070b7811 */
/* 0x000fe200078eb8ff */
/*06c0*/ BSSY B2, 0xa30 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*06d0*/ IMAD.IADD R11, R8, 0x1, -R11 ; /* 0x00000001080b7824 */
/* 0x000fe200078e0a0b */
/*06e0*/ IADD3 R8, R14, -0x7f, RZ ; /* 0xffffff810e087810 */
/* 0x000fc60007ffe0ff */
/*06f0*/ MUFU.RCP R10, R11 ; /* 0x0000000b000a7308 */
/* 0x000e220000001000 */
/*0700*/ FADD.FTZ R12, -R11, -RZ ; /* 0x800000ff0b0c7221 */
/* 0x000fe40000010100 */
/*0710*/ IMAD R5, R8.reuse, -0x800000, R5 ; /* 0xff80000008057824 */
/* 0x040fe200078e0205 */
/*0720*/ IADD3 R8, R8, 0x7f, -R7 ; /* 0x0000007f08087810 */
/* 0x000fca0007ffe807 */
/*0730*/ IMAD.IADD R8, R8, 0x1, R9 ; /* 0x0000000108087824 */
/* 0x000fe400078e0209 */
/*0740*/ FFMA R13, R10, R12, 1 ; /* 0x3f8000000a0d7423 */
/* 0x001fc8000000000c */
/*0750*/ FFMA R14, R10, R13, R10 ; /* 0x0000000d0a0e7223 */
/* 0x000fc8000000000a */
/*0760*/ FFMA R10, R5, R14, RZ ; /* 0x0000000e050a7223 */
/* 0x000fc800000000ff */
/*0770*/ FFMA R13, R12, R10, R5 ; /* 0x0000000a0c0d7223 */
/* 0x000fc80000000005 */
/*0780*/ FFMA R13, R14, R13, R10 ; /* 0x0000000d0e0d7223 */
/* 0x000fc8000000000a */
/*0790*/ FFMA R12, R12, R13, R5 ; /* 0x0000000d0c0c7223 */
/* 0x000fc80000000005 */
/*07a0*/ FFMA R5, R14, R12, R13 ; /* 0x0000000c0e057223 */
/* 0x000fca000000000d */
/*07b0*/ SHF.R.U32.HI R7, RZ, 0x17, R5 ; /* 0x00000017ff077819 */
/* 0x000fc80000011605 */
/*07c0*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fca00078ec0ff */
/*07d0*/ IMAD.IADD R11, R7, 0x1, R8 ; /* 0x00000001070b7824 */
/* 0x000fca00078e0208 */
/*07e0*/ IADD3 R7, R11, -0x1, RZ ; /* 0xffffffff0b077810 */
/* 0x000fc80007ffe0ff */
/*07f0*/ ISETP.GE.U32.AND P0, PT, R7, 0xfe, PT ; /* 0x000000fe0700780c */
/* 0x000fda0003f06070 */
/*0800*/ @!P0 BRA 0xa10 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0810*/ ISETP.GT.AND P0, PT, R11, 0xfe, PT ; /* 0x000000fe0b00780c */
/* 0x000fda0003f04270 */
/*0820*/ @P0 BRA 0x9e0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0830*/ ISETP.GE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fda0003f06270 */
/*0840*/ @P0 BRA 0xa20 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0850*/ ISETP.GE.AND P0, PT, R11, -0x18, PT ; /* 0xffffffe80b00780c */
/* 0x000fe40003f06270 */
/*0860*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fd600078ec0ff */
/*0870*/ @!P0 BRA 0xa20 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0880*/ FFMA.RZ R7, R14.reuse, R12.reuse, R13.reuse ; /* 0x0000000c0e077223 */
/* 0x1c0fe2000000c00d */
/*0890*/ IADD3 R10, R11.reuse, 0x20, RZ ; /* 0x000000200b0a7810 */
/* 0x040fe20007ffe0ff */
/*08a0*/ FFMA.RM R8, R14.reuse, R12.reuse, R13.reuse ; /* 0x0000000c0e087223 */
/* 0x1c0fe2000000400d */
/*08b0*/ ISETP.NE.AND P2, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f45270 */
/*08c0*/ LOP3.LUT R9, R7, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff07097812 */
/* 0x000fe200078ec0ff */
/*08d0*/ FFMA.RP R7, R14, R12, R13 ; /* 0x0000000c0e077223 */
/* 0x000fe2000000800d */
/*08e0*/ ISETP.NE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f25270 */
/*08f0*/ IMAD.MOV R11, RZ, RZ, -R11 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a0b */
/*0900*/ LOP3.LUT R9, R9, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000009097812 */
/* 0x000fe400078efcff */
/*0910*/ FSETP.NEU.FTZ.AND P0, PT, R7, R8, PT ; /* 0x000000080700720b */
/* 0x000fc40003f1d000 */
/*0920*/ SHF.L.U32 R10, R9, R10, RZ ; /* 0x0000000a090a7219 */
/* 0x000fe400000006ff */
/*0930*/ SEL R8, R11, RZ, P2 ; /* 0x000000ff0b087207 */
/* 0x000fe40001000000 */
/*0940*/ ISETP.NE.AND P1, PT, R10, RZ, P1 ; /* 0x000000ff0a00720c */
/* 0x000fe40000f25270 */
/*0950*/ SHF.R.U32.HI R8, RZ, R8, R9 ; /* 0x00000008ff087219 */
/* 0x000fe40000011609 */
/*0960*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0970*/ SHF.R.U32.HI R10, RZ, 0x1, R8 ; /* 0x00000001ff0a7819 */
/* 0x000fc40000011608 */
/*0980*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fc80004000000 */
/*0990*/ LOP3.LUT R7, R7, 0x1, R10, 0xf8, !PT ; /* 0x0000000107077812 */
/* 0x000fc800078ef80a */
/*09a0*/ LOP3.LUT R7, R7, R8, RZ, 0xc0, !PT ; /* 0x0000000807077212 */
/* 0x000fca00078ec0ff */
/*09b0*/ IMAD.IADD R10, R10, 0x1, R7 ; /* 0x000000010a0a7824 */
/* 0x000fca00078e0207 */
/*09c0*/ LOP3.LUT R5, R10, R5, RZ, 0xfc, !PT ; /* 0x000000050a057212 */
/* 0x000fe200078efcff */
/*09d0*/ BRA 0xa20 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*09e0*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fc800078ec0ff */
/*09f0*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*0a00*/ BRA 0xa20 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0a10*/ IMAD R5, R8, 0x800000, R5 ; /* 0x0080000008057824 */
/* 0x000fe400078e0205 */
/*0a20*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0a30*/ BRA 0xac0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0a40*/ LOP3.LUT R5, R8, 0x80000000, R5, 0x48, !PT ; /* 0x8000000008057812 */
/* 0x000fc800078e4805 */
/*0a50*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*0a60*/ BRA 0xac0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0a70*/ LOP3.LUT R5, R8, 0x80000000, R5, 0x48, !PT ; /* 0x8000000008057812 */
/* 0x000fe200078e4805 */
/*0a80*/ BRA 0xac0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0a90*/ MUFU.RSQ R5, -QNAN ; /* 0xffc0000000057908 */
/* 0x000e220000001400 */
/*0aa0*/ BRA 0xac0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0ab0*/ FADD.FTZ R5, R10, R13 ; /* 0x0000000d0a057221 */
/* 0x000fe40000010000 */
/*0ac0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0ad0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc800078e00ff */
/*0ae0*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff51006007950 */
/* 0x000fea0003c3ffff */
/*0af0*/ BRA 0xaf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPiS_S_
.globl _Z6kernelPiS_S_
.p2align 8
.type _Z6kernelPiS_S_,@function
_Z6kernelPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x100000, v1
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v0, 1, v1
v_add_nc_u32_e32 v4, 2, v1
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v0
v_ashrrev_i32_e32 v3, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshrrev_b32_e32 v2, 24, v2
v_lshrrev_b32_e32 v3, 24, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v0, v2
v_add_nc_u32_e32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v5, 0xffffff00, v2
v_and_b32_e32 v6, 0xffffff00, v3
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v0, v0, v5
v_sub_nc_u32_e32 v4, v4, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v5, 31, v4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v2
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v10, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v12, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
s_clause 0x2
global_load_b32 v6, v[6:7], off
global_load_b32 v7, v[10:11], off
global_load_b32 v10, v[12:13], off
s_clause 0x2
global_load_b32 v8, v[8:9], off
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v[4:5], off
s_waitcnt vmcnt(3)
v_add3_u32 v4, v7, v6, v10
s_waitcnt vmcnt(0)
v_add3_u32 v0, v0, v8, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v1, v4
v_cvt_f32_i32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_scale_f32 v4, null, 0x40400000, 0x40400000, v1
v_div_scale_f32 v10, vcc_lo, v1, 0x40400000, v1
v_div_scale_f32 v5, null, 0x40400000, 0x40400000, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v6, v4
v_rcp_f32_e32 v7, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v4, v6, 1.0
v_fma_f32 v9, -v5, v7, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v6, v8, v6
v_div_scale_f32 v8, s0, v0, 0x40400000, v0
v_fmac_f32_e32 v7, v9, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v9, v10, v6
v_mul_f32_e32 v11, v8, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v12, -v4, v9, v10
v_fma_f32 v13, -v5, v11, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v9, v12, v6
v_fmac_f32_e32 v11, v13, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v4, -v4, v9, v10
v_fma_f32 v5, -v5, v11, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v4, v4, v6, v9
s_mov_b32 vcc_lo, s0
v_div_fmas_f32 v5, v5, v7, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f32 v1, v4, 0x40400000, v1
v_div_fixup_f32 v0, v5, 0x40400000, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v1, v0
v_mul_f32_e32 v0, 0.5, v0
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v4, v0
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPiS_S_, .Lfunc_end0-_Z6kernelPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014693e_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6kernelPiS_S_PiS_S_
.type _Z29__device_stub__Z6kernelPiS_S_PiS_S_, @function
_Z29__device_stub__Z6kernelPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z6kernelPiS_S_PiS_S_, .-_Z29__device_stub__Z6kernelPiS_S_PiS_S_
.globl _Z6kernelPiS_S_
.type _Z6kernelPiS_S_, @function
_Z6kernelPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6kernelPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6kernelPiS_S_, .-_Z6kernelPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z21__device_stub__kernelPiS_S_ # -- Begin function _Z21__device_stub__kernelPiS_S_
.p2align 4, 0x90
.type _Z21__device_stub__kernelPiS_S_,@function
_Z21__device_stub__kernelPiS_S_: # @_Z21__device_stub__kernelPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPiS_S_, .Lfunc_end0-_Z21__device_stub__kernelPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPiS_S_,@object # @_Z6kernelPiS_S_
.section .rodata,"a",@progbits
.globl _Z6kernelPiS_S_
.p2align 3, 0x0
_Z6kernelPiS_S_:
.quad _Z21__device_stub__kernelPiS_S_
.size _Z6kernelPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelPiS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/device_vector.h>
#include <thrust/random.h>
#include <iostream>
struct fillRng {
thrust::uniform_real_distribution<double> distribution;
thrust::default_random_engine rng;
fillRng(thrust::uniform_real_distribution<double> dist, thrust::default_random_engine engine) {
distribution = dist;
rng = engine;
}
__device__ __host__
double operator() (const int &i) {
return distribution(rng);
}
};
int main()
{
thrust::uniform_real_distribution<double> dist(25, 40);
thrust::default_random_engine rng;
thrust::device_vector<double> dev(10, 0);
thrust::transform(
dev.begin(),
dev.end(),
dev.begin(),
fillRng(dist, rng)
);
for (auto i = dev.begin(); i != dev.end(); i++) {
std::cout << *i << " "; // este acesso é lento! -- GPU
}
std::cout << std::endl;
} | #include <hip/hip_runtime.h>
#include <thrust/device_vector.h>
#include <thrust/random.h>
#include <iostream>
struct fillRng {
thrust::uniform_real_distribution<double> distribution;
thrust::default_random_engine rng;
fillRng(thrust::uniform_real_distribution<double> dist, thrust::default_random_engine engine) {
distribution = dist;
rng = engine;
}
__device__ __host__
double operator() (const int &i) {
return distribution(rng);
}
};
int main()
{
thrust::uniform_real_distribution<double> dist(25, 40);
thrust::default_random_engine rng;
thrust::device_vector<double> dev(10, 0);
thrust::transform(
dev.begin(),
dev.end(),
dev.begin(),
fillRng(dist, rng)
);
for (auto i = dev.begin(); i != dev.end(); i++) {
std::cout << *i << " "; // este acesso é lento! -- GPU
}
std::cout << std::endl;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <thrust/device_vector.h>
#include <thrust/random.h>
#include <iostream>
struct fillRng {
thrust::uniform_real_distribution<double> distribution;
thrust::default_random_engine rng;
fillRng(thrust::uniform_real_distribution<double> dist, thrust::default_random_engine engine) {
distribution = dist;
rng = engine;
}
__device__ __host__
double operator() (const int &i) {
return distribution(rng);
}
};
int main()
{
thrust::uniform_real_distribution<double> dist(25, 40);
thrust::default_random_engine rng;
thrust::device_vector<double> dev(10, 0);
thrust::transform(
dev.begin(),
dev.end(),
dev.begin(),
fillRng(dist, rng)
);
for (auto i = dev.begin(); i != dev.end(); i++) {
std::cout << *i << " "; // este acesso é lento! -- GPU
}
std::cout << std::endl;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_:
s_load_b128 s[4:7], s[0:1], 0x10
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 3, v0
s_lshl_b64 s[0:1], s[2:3], 3
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
s_addc_u32 s1, s5, s1
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
flat_store_b64 v[0:1], v[2:3]
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_,comdat
.Lfunc_end0:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_, .Lfunc_end0-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_NS3_14no_stencil_tagE7fillRngNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_NS3_14no_stencil_tagE7fillRngNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_NS3_14no_stencil_tagE7fillRngNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_NS3_14no_stencil_tagE7fillRngNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_NS3_14no_stencil_tagE7fillRngNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_NS3_14no_stencil_tagE7fillRngNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_:
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x30
s_load_b32 s5, s[0:1], 0x20
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s10
s_addc_u32 s3, 0, s11
s_sub_u32 s6, s8, s2
s_subb_u32 s7, s9, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s4, 0x100, s[6:7]
s_and_b32 s4, s4, exec_lo
s_cselect_b32 s6, s6, 0x100
s_mov_b32 s4, 0
s_cmpk_lg_i32 s6, 0x100
s_cbranch_scc0 .LBB1_4
v_cmp_gt_u32_e32 vcc_lo, s6, v0
s_mov_b32 s9, 0
s_and_saveexec_b32 s10, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s10, exec_lo, s10
s_mul_hi_u32 s6, s5, 0xbc8f1391
s_mov_b32 s4, exec_lo
s_lshr_b32 s7, s6, 15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s7, 0xadc8
s_mulk_i32 s7, 0xd47
s_sub_i32 s6, s5, s6
s_mul_i32 s6, s6, 0xbc8f
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_u32 s6, s7
s_cselect_b32 s8, -1, 0
s_or_b32 exec_lo, exec_lo, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s9
s_cbranch_vccnz .LBB1_5
s_branch .LBB1_6
.LBB1_4:
s_cbranch_execz .LBB1_6
.LBB1_5:
s_mul_hi_u32 s6, s5, 0xbc8f1391
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshr_b32 s6, s6, 15
s_mul_i32 s7, s6, 0xadc8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_sub_i32 s5, s5, s7
s_mul_i32 s7, s6, 0xd47
s_mul_i32 s6, s5, 0xbc8f
s_cmp_lt_u32 s6, s7
s_cselect_b32 s8, -1, 0
s_or_b32 s4, s4, exec_lo
.LBB1_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execnz .LBB1_8
s_endpgm
.LBB1_8:
s_xor_b32 s4, s7, 0x7fffffff
s_sub_i32 s5, 0, s7
s_and_b32 s7, s8, exec_lo
s_cselect_b32 s4, s4, s5
s_mov_b32 s9, 0x41dfffff
s_add_i32 s4, s6, s4
s_mov_b32 s8, 0xff800000
s_add_i32 s4, s4, -1
v_lshlrev_b32_e32 v0, 3, v0
v_cvt_f64_u32_e32 v[1:2], s4
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[3:4], null, s[8:9], s[8:9], v[1:2]
v_div_scale_f64 v[9:10], vcc_lo, v[1:2], s[8:9], v[1:2]
v_rcp_f64_e32 v[5:6], v[3:4]
s_waitcnt_depctr 0xfff
v_fma_f64 v[7:8], -v[3:4], v[5:6], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[5:6], v[5:6], v[7:8], v[5:6]
v_fma_f64 v[7:8], -v[3:4], v[5:6], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[5:6], v[5:6], v[7:8], v[5:6]
v_mul_f64 v[7:8], v[9:10], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[3:4], -v[3:4], v[7:8], v[9:10]
v_div_fmas_f64 v[3:4], v[3:4], v[5:6], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_div_fixup_f64 v[1:2], v[3:4], s[8:9], v[1:2]
s_waitcnt lgkmcnt(0)
v_add_f64 v[3:4], s[0:1], -s[6:7]
s_lshl_b64 s[0:1], s[2:3], 3
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[1:2], v[3:4], v[1:2], s[6:7]
v_add_co_u32 v3, s0, s0, v0
v_add_co_ci_u32_e64 v4, null, s1, 0, s0
flat_store_b64 v[3:4], v[1:2]
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_NS3_14no_stencil_tagE7fillRngNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 64
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_NS3_14no_stencil_tagE7fillRngNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_NS3_14no_stencil_tagE7fillRngNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,comdat
.Lfunc_end1:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_NS3_14no_stencil_tagE7fillRngNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_, .Lfunc_end1-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_NS3_14no_stencil_tagE7fillRngNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 48
.value_kind: by_value
- .offset: 48
.size: 8
.value_kind: by_value
- .offset: 56
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 64
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_NS3_14no_stencil_tagE7fillRngNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_NS3_14no_stencil_tagE7fillRngNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "ppm.h"
const int BLUR_SIZE=10;
//used to blur a 2d color ppm image
__global__
void blurKernel(int* in, int* out,int w,int h){
int curpix=blockIdx.x*blockDim.x+threadIdx.x;
int row=curpix / w;
int col=curpix % w;
if ( row>=h ) return;
int pixr=0;
int pixg=0;
int pixb=0;
int pixels=0;
for (int br=-BLUR_SIZE; br<=BLUR_SIZE;br++){
for (int bc=-BLUR_SIZE; bc<=BLUR_SIZE;bc++){
int currow=row+br;
int curcol=col+bc;
if(currow>=0 && currow<h && curcol>=0 && curcol <w ){
pixels++;
int pdex= 3*(currow*w+curcol);
pixr+=in[pdex];
pixg+=in[pdex+1];
pixb+=in[pdex+2];
}
}
}
int dex=3*(row*w+col);
out[dex]= round((float)pixr/pixels);
out[dex+1]= round((float)pixg/pixels);
out[dex+2]= round((float)pixb/pixels);
}
int main(){
ppm football("football.ppm");
int numpixels=football.height*football.width;
int size=3*numpixels;
int arsize=sizeof(int)*size;
std::cout <<"Size is: "<< size;
int* d_football_data;
int* d_bfootball_data;
cudaMalloc((void**)&d_football_data,arsize);
cudaMalloc((void**)&d_bfootball_data,arsize );
cudaMemcpy(d_football_data,football.data,arsize,cudaMemcpyHostToDevice);
cudaMemcpy(d_bfootball_data,football.data,arsize,cudaMemcpyHostToDevice);
blurKernel<<<ceil(numpixels/256) ,256>>>(d_football_data,d_bfootball_data,football.width,football.height);
ppm bfootball(football);
cudaMemcpy(bfootball.data,d_bfootball_data,arsize,cudaMemcpyDeviceToHost);
bfootball.write("bfootball.ppm");
cudaFree(d_football_data);
cudaFree(d_bfootball_data);
} | code for sm_80
Function : _Z10blurKernelPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R7, c[0x0][0x170] ; /* 0x00005c0000077a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e260000002500 */
/*0030*/ I2F.RP R0, R7 ; /* 0x0000000700007306 */
/* 0x000e620000209400 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e2e0000002100 */
/*0050*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x002e620000001000 */
/*0060*/ IMAD R8, R8, c[0x0][0x0], R5 ; /* 0x0000000008087a24 */
/* 0x001fe200078e0205 */
/*0070*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x002fc80007ffe0ff */
/*0080*/ IABS R0, R8 ; /* 0x0000000800007213 */
/* 0x000fe40000000000 */
/*0090*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00b0*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x002fc800078e0a03 */
/*00c0*/ IMAD R5, R4, R7, RZ ; /* 0x0000000704057224 */
/* 0x000fc800078e02ff */
/*00d0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*00e0*/ IMAD.HI.U32 R5, R3, R0, RZ ; /* 0x0000000003057227 */
/* 0x000fc800078e00ff */
/*00f0*/ IMAD.MOV R3, RZ, RZ, -R5 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a05 */
/*0100*/ IMAD R0, R7, R3, R0 ; /* 0x0000000307007224 */
/* 0x000fca00078e0200 */
/*0110*/ ISETP.GT.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f24070 */
/*0120*/ @!P1 IMAD.IADD R0, R0, 0x1, -R7 ; /* 0x0000000100009824 */
/* 0x000fe200078e0a07 */
/*0130*/ @!P1 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105059810 */
/* 0x000fe40007ffe0ff */
/*0140*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fe40003f25270 */
/*0150*/ ISETP.GE.U32.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fe40003f06070 */
/*0160*/ LOP3.LUT R0, R8, c[0x0][0x170], RZ, 0x3c, !PT ; /* 0x00005c0008007a12 */
/* 0x000fc800078e3cff */
/*0170*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fce0003f46270 */
/*0180*/ @P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105050810 */
/* 0x000fcc0007ffe0ff */
/*0190*/ @!P2 IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff05a224 */
/* 0x000fe200078e0a05 */
/*01a0*/ @!P1 LOP3.LUT R5, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff059a12 */
/* 0x000fc800078e33ff */
/*01b0*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x174], PT ; /* 0x00005d0005007a0c */
/* 0x000fe20003f06270 */
/*01c0*/ IMAD.MOV R3, RZ, RZ, -R5 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a05 */
/*01d0*/ IMAD R8, R3, c[0x0][0x170], R8 ; /* 0x00005c0003087a24 */
/* 0x000fd000078e0208 */
/*01e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01f0*/ IADD3 R9, R8, -0x9, RZ ; /* 0xfffffff708097810 */
/* 0x000fe20007ffe0ff */
/*0200*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0210*/ IMAD.MOV.U32 R10, RZ, RZ, -0xa ; /* 0xfffffff6ff0a7424 */
/* 0x000fe200078e00ff */
/*0220*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0230*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe400078e00ff */
/*0240*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe400078e00ff */
/*0250*/ IMAD.IADD R12, R5, 0x1, R10 ; /* 0x00000001050c7824 */
/* 0x000fe200078e020a */
/*0260*/ IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a7810 */
/* 0x000fe20007ffe0ff */
/*0270*/ IMAD.MOV.U32 R11, RZ, RZ, R9.reuse ; /* 0x000000ffff0b7224 */
/* 0x100fe400078e0009 */
/*0280*/ IMAD R14, R12.reuse, c[0x0][0x170], R9 ; /* 0x00005c000c0e7a24 */
/* 0x040fe200078e0209 */
/*0290*/ ISETP.GE.AND P3, PT, R12, c[0x0][0x174], PT ; /* 0x00005d000c007a0c */
/* 0x000fe20003f66270 */
/*02a0*/ IMAD.MOV.U32 R13, RZ, RZ, -0xa ; /* 0xfffffff6ff0d7424 */
/* 0x000fe200078e00ff */
/*02b0*/ ISETP.GE.AND P4, PT, R10, 0xb, PT ; /* 0x0000000b0a00780c */
/* 0x000fe20003f86270 */
/*02c0*/ IMAD R14, R14, 0x3, RZ ; /* 0x000000030e0e7824 */
/* 0x000fc400078e02ff */
/*02d0*/ IMAD.IADD R3, R8, 0x1, R13 ; /* 0x0000000108037824 */
/* 0x000fe200078e020d */
/*02e0*/ BSSY B0, 0x3f0 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*02f0*/ ISETP.NE.AND P1, PT, R13, 0xa, PT ; /* 0x0000000a0d00780c */
/* 0x000fc60003f25270 */
/*0300*/ LOP3.LUT R2, R3, R12, RZ, 0xfc, !PT ; /* 0x0000000c03027212 */
/* 0x000fc800078efcff */
/*0310*/ ISETP.LT.OR P0, PT, R2, RZ, P3 ; /* 0x000000ff0200720c */
/* 0x000fe40001f01670 */
/*0320*/ IADD3 R2, R14, -0x3, RZ ; /* 0xfffffffd0e027810 */
/* 0x000fe40007ffe0ff */
/*0330*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x170], P0 ; /* 0x00005c0003007a0c */
/* 0x000fe20000706670 */
/*0340*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0350*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fd000078e0203 */
/*0360*/ @P0 BRA 0x3e0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0370*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ea8000c1e1900 */
/*0380*/ LDG.E R17, [R2.64+0x4] ; /* 0x0000040402117981 */
/* 0x000ee8000c1e1900 */
/*0390*/ LDG.E R19, [R2.64+0x8] ; /* 0x0000080402137981 */
/* 0x000f22000c1e1900 */
/*03a0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe20007ffe0ff */
/*03b0*/ IMAD.IADD R6, R6, 0x1, R15 ; /* 0x0000000106067824 */
/* 0x004fc400078e020f */
/*03c0*/ IMAD.IADD R4, R4, 0x1, R17 ; /* 0x0000000104047824 */
/* 0x008fe400078e0211 */
/*03d0*/ IMAD.IADD R0, R0, 0x1, R19 ; /* 0x0000000100007824 */
/* 0x010fe400078e0213 */
/*03e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03f0*/ @!P1 BRA 0x640 ; /* 0x0000024000009947 */
/* 0x000fea0003800000 */
/*0400*/ IADD3 R15, R11.reuse, 0x1, RZ ; /* 0x000000010b0f7810 */
/* 0x040fe40007ffe0ff */
/*0410*/ LOP3.LUT R16, R11.reuse, R12.reuse, RZ, 0xfc, !PT ; /* 0x0000000c0b107212 */
/* 0x0c0fe400078efcff */
/*0420*/ IADD3 R17, R11, 0x2, RZ ; /* 0x000000020b117810 */
/* 0x000fe40007ffe0ff */
/*0430*/ LOP3.LUT R18, R15, R12, RZ, 0xfc, !PT ; /* 0x0000000c0f127212 */
/* 0x000fe400078efcff */
/*0440*/ ISETP.LT.OR P0, PT, R16, RZ, P3 ; /* 0x000000ff1000720c */
/* 0x000fc40001f01670 */
/*0450*/ LOP3.LUT R16, R17, R12, RZ, 0xfc, !PT ; /* 0x0000000c11107212 */
/* 0x000fe400078efcff */
/*0460*/ ISETP.LT.OR P2, PT, R18, RZ, P3 ; /* 0x000000ff1200720c */
/* 0x000fe40001f41670 */
/*0470*/ ISETP.GE.OR P0, PT, R11, c[0x0][0x170], P0 ; /* 0x00005c000b007a0c */
/* 0x000fe40000706670 */
/*0480*/ ISETP.LT.OR P1, PT, R16, RZ, P3 ; /* 0x000000ff1000720c */
/* 0x000fe40001f21670 */
/*0490*/ ISETP.GE.OR P2, PT, R15, c[0x0][0x170], P2 ; /* 0x00005c000f007a0c */
/* 0x000fe40001746670 */
/*04a0*/ ISETP.GE.OR P1, PT, R17, c[0x0][0x170], P1 ; /* 0x00005c0011007a0c */
/* 0x000fce0000f26670 */
/*04b0*/ @!P0 LDG.E R15, [R2.64+0xc] ; /* 0x00000c04020f8981 */
/* 0x000ea8000c1e1900 */
/*04c0*/ @!P0 LDG.E R17, [R2.64+0x10] ; /* 0x0000100402118981 */
/* 0x000ee8000c1e1900 */
/*04d0*/ @!P0 LDG.E R19, [R2.64+0x14] ; /* 0x0000140402138981 */
/* 0x000f28000c1e1900 */
/*04e0*/ @!P2 LDG.E R21, [R2.64+0x18] ; /* 0x000018040215a981 */
/* 0x000f68000c1e1900 */
/*04f0*/ @!P2 LDG.E R23, [R2.64+0x1c] ; /* 0x00001c040217a981 */
/* 0x000f68000c1e1900 */
/*0500*/ @!P2 LDG.E R25, [R2.64+0x20] ; /* 0x000020040219a981 */
/* 0x000f68000c1e1900 */
/*0510*/ @!P1 LDG.E R27, [R2.64+0x24] ; /* 0x00002404021b9981 */
/* 0x000f68000c1e1900 */
/*0520*/ @!P1 LDG.E R29, [R2.64+0x28] ; /* 0x00002804021d9981 */
/* 0x000f68000c1e1900 */
/*0530*/ @!P1 LDG.E R16, [R2.64+0x2c] ; /* 0x00002c0402109981 */
/* 0x000f62000c1e1900 */
/*0540*/ @!P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107078810 */
/* 0x000fc40007ffe0ff */
/*0550*/ IADD3 R13, R13, 0x4, RZ ; /* 0x000000040d0d7810 */
/* 0x000fe40007ffe0ff */
/*0560*/ @!P2 IADD3 R7, R7, 0x1, RZ ; /* 0x000000010707a810 */
/* 0x000fe40007ffe0ff */
/*0570*/ IADD3 R14, R14, 0xc, RZ ; /* 0x0000000c0e0e7810 */
/* 0x000fe40007ffe0ff */
/*0580*/ IADD3 R11, R11, 0x4, RZ ; /* 0x000000040b0b7810 */
/* 0x000fe40007ffe0ff */
/*0590*/ @!P1 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107079810 */
/* 0x000fe20007ffe0ff */
/*05a0*/ @!P0 IMAD.IADD R6, R6, 0x1, R15 ; /* 0x0000000106068824 */
/* 0x004fe400078e020f */
/*05b0*/ @!P0 IMAD.IADD R4, R4, 0x1, R17 ; /* 0x0000000104048824 */
/* 0x008fc400078e0211 */
/*05c0*/ @!P0 IMAD.IADD R0, R0, 0x1, R19 ; /* 0x0000000100008824 */
/* 0x010fe400078e0213 */
/*05d0*/ @!P2 IMAD.IADD R6, R6, 0x1, R21 ; /* 0x000000010606a824 */
/* 0x020fe400078e0215 */
/*05e0*/ @!P2 IMAD.IADD R4, R4, 0x1, R23 ; /* 0x000000010404a824 */
/* 0x000fe400078e0217 */
/*05f0*/ @!P2 IMAD.IADD R0, R0, 0x1, R25 ; /* 0x000000010000a824 */
/* 0x000fe400078e0219 */
/*0600*/ @!P1 IMAD.IADD R6, R6, 0x1, R27 ; /* 0x0000000106069824 */
/* 0x000fe400078e021b */
/*0610*/ @!P1 IMAD.IADD R4, R4, 0x1, R29 ; /* 0x0000000104049824 */
/* 0x000fc400078e021d */
/*0620*/ @!P1 IMAD.IADD R0, R0, 0x1, R16 ; /* 0x0000000100009824 */
/* 0x000fe200078e0210 */
/*0630*/ BRA 0x2d0 ; /* 0xfffffc9000007947 */
/* 0x000fea000383ffff */
/*0640*/ @!P4 BRA 0x250 ; /* 0xfffffc000000c947 */
/* 0x000fea000383ffff */
/*0650*/ I2F R7, R7 ; /* 0x0000000700077306 */
/* 0x000e220000201400 */
/*0660*/ BSSY B0, 0x760 ; /* 0x000000f000007945 */
/* 0x000fee0003800000 */
/*0670*/ I2F R11, R6 ; /* 0x00000006000b7306 */
/* 0x000e700000201400 */
/*0680*/ MUFU.RCP R2, R7 ; /* 0x0000000700027308 */
/* 0x001e300000001000 */
/*0690*/ FCHK P0, R11, R7 ; /* 0x000000070b007302 */
/* 0x002e620000000000 */
/*06a0*/ FFMA R3, -R7, R2, 1 ; /* 0x3f80000007037423 */
/* 0x001fc80000000102 */
/*06b0*/ FFMA R3, R2, R3, R2 ; /* 0x0000000302037223 */
/* 0x000fe40000000002 */
/*06c0*/ IMAD R2, R5, c[0x0][0x170], R8 ; /* 0x00005c0005027a24 */
/* 0x000fe400078e0208 */
/*06d0*/ FFMA R10, R11, R3, RZ ; /* 0x000000030b0a7223 */
/* 0x000fe400000000ff */
/*06e0*/ IMAD R2, R2, 0x3, RZ ; /* 0x0000000302027824 */
/* 0x000fe400078e02ff */
/*06f0*/ FFMA R5, -R7, R10, R11 ; /* 0x0000000a07057223 */
/* 0x000fc8000000010b */
/*0700*/ FFMA R3, R3, R5, R10 ; /* 0x0000000503037223 */
/* 0x000fe2000000000a */
/*0710*/ @!P0 BRA 0x750 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*0720*/ MOV R6, 0x740 ; /* 0x0000074000067802 */
/* 0x000fe40000000f00 */
/*0730*/ CALL.REL.NOINC 0xa40 ; /* 0x0000030000007944 */
/* 0x000fea0003c00000 */
/*0740*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */
/* 0x001fe400078e0005 */
/*0750*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0760*/ LOP3.LUT R5, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003057812 */
/* 0x000fe200078ec0ff */
/*0770*/ I2F R11, R4 ; /* 0x00000004000b7306 */
/* 0x000e220000201400 */
/*0780*/ BSSY B0, 0x8b0 ; /* 0x0000012000007945 */
/* 0x000fe40003800000 */
/*0790*/ LOP3.LUT R6, R5, 0x3f000000, RZ, 0xfc, !PT ; /* 0x3f00000005067812 */
/* 0x000fca00078efcff */
/*07a0*/ FADD.RZ R6, R6, R3 ; /* 0x0000000306067221 */
/* 0x000fe2000000c000 */
/*07b0*/ MUFU.RCP R8, R7 ; /* 0x0000000700087308 */
/* 0x000e620000001000 */
/*07c0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*07d0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc600078e0203 */
/*07e0*/ F2I.TRUNC.NTZ R5, R6 ; /* 0x0000000600057305 */
/* 0x000eb0000020f100 */
/*07f0*/ FCHK P0, R11, R7 ; /* 0x000000070b007302 */
/* 0x001e220000000000 */
/*0800*/ FFMA R9, -R7, R8, 1 ; /* 0x3f80000007097423 */
/* 0x002fc80000000108 */
/*0810*/ FFMA R10, R8, R9, R8 ; /* 0x00000009080a7223 */
/* 0x000fe20000000008 */
/*0820*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0043e6000c101904 */
/*0830*/ FFMA R8, R10, R11, RZ ; /* 0x0000000b0a087223 */
/* 0x000fc800000000ff */
/*0840*/ FFMA R9, -R7, R8, R11 ; /* 0x0000000807097223 */
/* 0x000fc8000000010b */
/*0850*/ FFMA R8, R10, R9, R8 ; /* 0x000000090a087223 */
/* 0x000fe20000000008 */
/*0860*/ @!P0 BRA 0x8a0 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*0870*/ MOV R6, 0x890 ; /* 0x0000089000067802 */
/* 0x000fe40000000f00 */
/*0880*/ CALL.REL.NOINC 0xa40 ; /* 0x000001b000007944 */
/* 0x002fea0003c00000 */
/*0890*/ IMAD.MOV.U32 R8, RZ, RZ, R5 ; /* 0x000000ffff087224 */
/* 0x001fe400078e0005 */
/*08a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08b0*/ LOP3.LUT R4, R8, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000008047812 */
/* 0x000fe200078ec0ff */
/*08c0*/ I2F R11, R0 ; /* 0x00000000000b7306 */
/* 0x000e220000201400 */
/*08d0*/ BSSY B0, 0x9e0 ; /* 0x0000010000007945 */
/* 0x000fe40003800000 */
/*08e0*/ LOP3.LUT R5, R4, 0x3f000000, RZ, 0xfc, !PT ; /* 0x3f00000004057812 */
/* 0x002fca00078efcff */
/*08f0*/ FADD.RZ R5, R5, R8 ; /* 0x0000000805057221 */
/* 0x000fe2000000c000 */
/*0900*/ MUFU.RCP R4, R7 ; /* 0x0000000700047308 */
/* 0x000e700000001000 */
/*0910*/ F2I.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000eb0000020f100 */
/*0920*/ FCHK P0, R11, R7 ; /* 0x000000070b007302 */
/* 0x001e220000000000 */
/*0930*/ FFMA R9, -R7, R4, 1 ; /* 0x3f80000007097423 */
/* 0x002fc80000000104 */
/*0940*/ FFMA R6, R4, R9, R4 ; /* 0x0000000904067223 */
/* 0x000fe20000000004 */
/*0950*/ STG.E [R2.64+0x4], R5 ; /* 0x0000040502007986 */
/* 0x0043e6000c101904 */
/*0960*/ FFMA R4, R6, R11, RZ ; /* 0x0000000b06047223 */
/* 0x000fc800000000ff */
/*0970*/ FFMA R9, -R7, R4, R11 ; /* 0x0000000407097223 */
/* 0x000fc8000000010b */
/*0980*/ FFMA R4, R6, R9, R4 ; /* 0x0000000906047223 */
/* 0x000fe20000000004 */
/*0990*/ @!P0 BRA 0x9d0 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*09a0*/ MOV R6, 0x9c0 ; /* 0x000009c000067802 */
/* 0x000fe40000000f00 */
/*09b0*/ CALL.REL.NOINC 0xa40 ; /* 0x0000008000007944 */
/* 0x002fea0003c00000 */
/*09c0*/ IMAD.MOV.U32 R4, RZ, RZ, R5 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0005 */
/*09d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*09e0*/ LOP3.LUT R0, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004007812 */
/* 0x000fc800078ec0ff */
/*09f0*/ LOP3.LUT R5, R0, 0x3f000000, RZ, 0xfc, !PT ; /* 0x3f00000000057812 */
/* 0x002fca00078efcff */
/*0a00*/ FADD.RZ R5, R5, R4 ; /* 0x0000000405057221 */
/* 0x000fcc000000c000 */
/*0a10*/ F2I.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e24000020f100 */
/*0a20*/ STG.E [R2.64+0x8], R5 ; /* 0x0000080502007986 */
/* 0x001fe2000c101904 */
/*0a30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a40*/ SHF.R.U32.HI R9, RZ, 0x17, R7 ; /* 0x00000017ff097819 */
/* 0x000fe20000011607 */
/*0a50*/ BSSY B1, 0x10a0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0a60*/ SHF.R.U32.HI R5, RZ, 0x17, R11 ; /* 0x00000017ff057819 */
/* 0x000fe2000001160b */
/*0a70*/ IMAD.MOV.U32 R10, RZ, RZ, R7 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0007 */
/*0a80*/ LOP3.LUT R9, R9, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff09097812 */
/* 0x000fe400078ec0ff */
/*0a90*/ LOP3.LUT R13, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff050d7812 */
/* 0x000fe200078ec0ff */
/*0aa0*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000b */
/*0ab0*/ IADD3 R14, R9, -0x1, RZ ; /* 0xffffffff090e7810 */
/* 0x000fc40007ffe0ff */
/*0ac0*/ IADD3 R12, R13, -0x1, RZ ; /* 0xffffffff0d0c7810 */
/* 0x000fe40007ffe0ff */
/*0ad0*/ ISETP.GT.U32.AND P0, PT, R14, 0xfd, PT ; /* 0x000000fd0e00780c */
/* 0x000fc80003f04070 */
/*0ae0*/ ISETP.GT.U32.OR P0, PT, R12, 0xfd, P0 ; /* 0x000000fd0c00780c */
/* 0x000fda0000704470 */
/*0af0*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff088224 */
/* 0x000fe200078e00ff */
/*0b00*/ @!P0 BRA 0xc80 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0b10*/ FSETP.GTU.FTZ.AND P0, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fe40003f1c200 */
/*0b20*/ FSETP.GTU.FTZ.AND P1, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fc80003f3c200 */
/*0b30*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0b40*/ @P0 BRA 0x1080 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0b50*/ LOP3.LUT P0, RZ, R10, 0x7fffffff, R5, 0xc8, !PT ; /* 0x7fffffff0aff7812 */
/* 0x000fda000780c805 */
/*0b60*/ @!P0 BRA 0x1060 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0b70*/ FSETP.NEU.FTZ.AND P1, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fe40003f3d200 */
/*0b80*/ FSETP.NEU.FTZ.AND P2, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fe40003f5d200 */
/*0b90*/ FSETP.NEU.FTZ.AND P0, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fd60003f1d200 */
/*0ba0*/ @!P2 BRA !P1, 0x1060 ; /* 0x000004b00000a947 */
/* 0x000fea0004800000 */
/*0bb0*/ LOP3.LUT P1, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fc8000782c0ff */
/*0bc0*/ PLOP3.LUT P1, PT, P2, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0001722572 */
/*0bd0*/ @P1 BRA 0x1040 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0be0*/ LOP3.LUT P1, RZ, R10, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0aff7812 */
/* 0x000fc8000782c0ff */
/*0bf0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0c00*/ @P0 BRA 0x1010 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0c10*/ ISETP.GE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f06270 */
/*0c20*/ ISETP.GE.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fd60003f26270 */
/*0c30*/ @P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff080224 */
/* 0x000fe400078e00ff */
/*0c40*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, -0x40 ; /* 0xffffffc0ff088424 */
/* 0x000fe400078e00ff */
/*0c50*/ @!P0 FFMA R5, R11, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000b058823 */
/* 0x000fe400000000ff */
/*0c60*/ @!P1 FFMA R10, R7, 1.84467440737095516160e+19, RZ ; /* 0x5f800000070a9823 */
/* 0x000fe200000000ff */
/*0c70*/ @!P1 IADD3 R8, R8, 0x40, RZ ; /* 0x0000004008089810 */
/* 0x000fe40007ffe0ff */
/*0c80*/ LEA R11, R9, 0xc0800000, 0x17 ; /* 0xc0800000090b7811 */
/* 0x000fe200078eb8ff */
/*0c90*/ BSSY B2, 0x1000 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*0ca0*/ IMAD.IADD R11, R10, 0x1, -R11 ; /* 0x000000010a0b7824 */
/* 0x000fe200078e0a0b */
/*0cb0*/ IADD3 R10, R13, -0x7f, RZ ; /* 0xffffff810d0a7810 */
/* 0x000fc60007ffe0ff */
/*0cc0*/ MUFU.RCP R12, R11 ; /* 0x0000000b000c7308 */
/* 0x0000620000001000 */
/*0cd0*/ FADD.FTZ R14, -R11, -RZ ; /* 0x800000ff0b0e7221 */
/* 0x000fe40000010100 */
/*0ce0*/ IMAD R5, R10.reuse, -0x800000, R5 ; /* 0xff8000000a057824 */
/* 0x040fe200078e0205 */
/*0cf0*/ IADD3 R11, R10, 0x7f, -R9 ; /* 0x0000007f0a0b7810 */
/* 0x001fca0007ffe809 */
/*0d00*/ IMAD.IADD R8, R11, 0x1, R8 ; /* 0x000000010b087824 */
/* 0x000fe400078e0208 */
/*0d10*/ FFMA R13, R12, R14, 1 ; /* 0x3f8000000c0d7423 */
/* 0x002fc8000000000e */
/*0d20*/ FFMA R16, R12, R13, R12 ; /* 0x0000000d0c107223 */
/* 0x000fc8000000000c */
/*0d30*/ FFMA R12, R5, R16, RZ ; /* 0x00000010050c7223 */
/* 0x000fc800000000ff */
/*0d40*/ FFMA R13, R14, R12, R5 ; /* 0x0000000c0e0d7223 */
/* 0x000fc80000000005 */
/*0d50*/ FFMA R13, R16, R13, R12 ; /* 0x0000000d100d7223 */
/* 0x000fc8000000000c */
/*0d60*/ FFMA R14, R14, R13, R5 ; /* 0x0000000d0e0e7223 */
/* 0x000fc80000000005 */
/*0d70*/ FFMA R5, R16, R14, R13 ; /* 0x0000000e10057223 */
/* 0x000fca000000000d */
/*0d80*/ SHF.R.U32.HI R9, RZ, 0x17, R5 ; /* 0x00000017ff097819 */
/* 0x000fc80000011605 */
/*0d90*/ LOP3.LUT R9, R9, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff09097812 */
/* 0x000fca00078ec0ff */
/*0da0*/ IMAD.IADD R12, R9, 0x1, R8 ; /* 0x00000001090c7824 */
/* 0x000fca00078e0208 */
/*0db0*/ IADD3 R9, R12, -0x1, RZ ; /* 0xffffffff0c097810 */
/* 0x000fc80007ffe0ff */
/*0dc0*/ ISETP.GE.U32.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f06070 */
/*0dd0*/ @!P0 BRA 0xfe0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0de0*/ ISETP.GT.AND P0, PT, R12, 0xfe, PT ; /* 0x000000fe0c00780c */
/* 0x000fda0003f04270 */
/*0df0*/ @P0 BRA 0xfb0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0e00*/ ISETP.GE.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fda0003f06270 */
/*0e10*/ @P0 BRA 0xff0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0e20*/ ISETP.GE.AND P0, PT, R12, -0x18, PT ; /* 0xffffffe80c00780c */
/* 0x000fe40003f06270 */
/*0e30*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fd600078ec0ff */
/*0e40*/ @!P0 BRA 0xff0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0e50*/ FFMA.RZ R8, R16, R14.reuse, R13.reuse ; /* 0x0000000e10087223 */
/* 0x180fe2000000c00d */
/*0e60*/ IADD3 R11, R12, 0x20, RZ ; /* 0x000000200c0b7810 */
/* 0x000fe20007ffe0ff */
/*0e70*/ FFMA.RM R9, R16, R14.reuse, R13.reuse ; /* 0x0000000e10097223 */
/* 0x180fe2000000400d */
/*0e80*/ ISETP.NE.AND P2, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f45270 */
/*0e90*/ LOP3.LUT R10, R8, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff080a7812 */
/* 0x000fe200078ec0ff */
/*0ea0*/ FFMA.RP R8, R16, R14, R13 ; /* 0x0000000e10087223 */
/* 0x000fe2000000800d */
/*0eb0*/ ISETP.NE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f25270 */
/*0ec0*/ IMAD.MOV R12, RZ, RZ, -R12 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0a0c */
/*0ed0*/ LOP3.LUT R10, R10, 0x800000, RZ, 0xfc, !PT ; /* 0x008000000a0a7812 */
/* 0x000fe400078efcff */
/*0ee0*/ FSETP.NEU.FTZ.AND P0, PT, R8, R9, PT ; /* 0x000000090800720b */
/* 0x000fc40003f1d000 */
/*0ef0*/ SHF.L.U32 R11, R10, R11, RZ ; /* 0x0000000b0a0b7219 */
/* 0x000fe400000006ff */
/*0f00*/ SEL R9, R12, RZ, P2 ; /* 0x000000ff0c097207 */
/* 0x000fe40001000000 */
/*0f10*/ ISETP.NE.AND P1, PT, R11, RZ, P1 ; /* 0x000000ff0b00720c */
/* 0x000fe40000f25270 */
/*0f20*/ SHF.R.U32.HI R9, RZ, R9, R10 ; /* 0x00000009ff097219 */
/* 0x000fe4000001160a */
/*0f30*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0f40*/ SHF.R.U32.HI R11, RZ, 0x1, R9 ; /* 0x00000001ff0b7819 */
/* 0x000fc40000011609 */
/*0f50*/ SEL R8, RZ, 0x1, !P0 ; /* 0x00000001ff087807 */
/* 0x000fc80004000000 */
/*0f60*/ LOP3.LUT R8, R8, 0x1, R11, 0xf8, !PT ; /* 0x0000000108087812 */
/* 0x000fc800078ef80b */
/*0f70*/ LOP3.LUT R8, R8, R9, RZ, 0xc0, !PT ; /* 0x0000000908087212 */
/* 0x000fca00078ec0ff */
/*0f80*/ IMAD.IADD R8, R11, 0x1, R8 ; /* 0x000000010b087824 */
/* 0x000fca00078e0208 */
/*0f90*/ LOP3.LUT R5, R8, R5, RZ, 0xfc, !PT ; /* 0x0000000508057212 */
/* 0x000fe200078efcff */
/*0fa0*/ BRA 0xff0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0fb0*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fc800078ec0ff */
/*0fc0*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*0fd0*/ BRA 0xff0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0fe0*/ IMAD R5, R8, 0x800000, R5 ; /* 0x0080000008057824 */
/* 0x000fe400078e0205 */
/*0ff0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*1000*/ BRA 0x1090 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*1010*/ LOP3.LUT R5, R10, 0x80000000, R5, 0x48, !PT ; /* 0x800000000a057812 */
/* 0x000fc800078e4805 */
/*1020*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*1030*/ BRA 0x1090 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*1040*/ LOP3.LUT R5, R10, 0x80000000, R5, 0x48, !PT ; /* 0x800000000a057812 */
/* 0x000fe200078e4805 */
/*1050*/ BRA 0x1090 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*1060*/ MUFU.RSQ R5, -QNAN ; /* 0xffc0000000057908 */
/* 0x000e220000001400 */
/*1070*/ BRA 0x1090 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*1080*/ FADD.FTZ R5, R11, R7 ; /* 0x000000070b057221 */
/* 0x000fe40000010000 */
/*1090*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*10a0*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0006 */
/*10b0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x0 ; /* 0x00000000ff097424 */
/* 0x000fc800078e00ff */
/*10c0*/ RET.REL.NODEC R8 0x0 ; /* 0xffffef3008007950 */
/* 0x000fea0003c3ffff */
/*10d0*/ BRA 0x10d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "ppm.h"
const int BLUR_SIZE=10;
//used to blur a 2d color ppm image
__global__
void blurKernel(int* in, int* out,int w,int h){
int curpix=blockIdx.x*blockDim.x+threadIdx.x;
int row=curpix / w;
int col=curpix % w;
if ( row>=h ) return;
int pixr=0;
int pixg=0;
int pixb=0;
int pixels=0;
for (int br=-BLUR_SIZE; br<=BLUR_SIZE;br++){
for (int bc=-BLUR_SIZE; bc<=BLUR_SIZE;bc++){
int currow=row+br;
int curcol=col+bc;
if(currow>=0 && currow<h && curcol>=0 && curcol <w ){
pixels++;
int pdex= 3*(currow*w+curcol);
pixr+=in[pdex];
pixg+=in[pdex+1];
pixb+=in[pdex+2];
}
}
}
int dex=3*(row*w+col);
out[dex]= round((float)pixr/pixels);
out[dex+1]= round((float)pixg/pixels);
out[dex+2]= round((float)pixb/pixels);
}
int main(){
ppm football("football.ppm");
int numpixels=football.height*football.width;
int size=3*numpixels;
int arsize=sizeof(int)*size;
std::cout <<"Size is: "<< size;
int* d_football_data;
int* d_bfootball_data;
cudaMalloc((void**)&d_football_data,arsize);
cudaMalloc((void**)&d_bfootball_data,arsize );
cudaMemcpy(d_football_data,football.data,arsize,cudaMemcpyHostToDevice);
cudaMemcpy(d_bfootball_data,football.data,arsize,cudaMemcpyHostToDevice);
blurKernel<<<ceil(numpixels/256) ,256>>>(d_football_data,d_bfootball_data,football.width,football.height);
ppm bfootball(football);
cudaMemcpy(bfootball.data,d_bfootball_data,arsize,cudaMemcpyDeviceToHost);
bfootball.write("bfootball.ppm");
cudaFree(d_football_data);
cudaFree(d_bfootball_data);
} | .file "tmpxft_00119ae2_00000000-6_blurKernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4710:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4710:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z10blurKernelPiS_iiPiS_ii
.type _Z34__device_stub__Z10blurKernelPiS_iiPiS_ii, @function
_Z34__device_stub__Z10blurKernelPiS_iiPiS_ii:
.LFB4732:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10blurKernelPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4732:
.size _Z34__device_stub__Z10blurKernelPiS_iiPiS_ii, .-_Z34__device_stub__Z10blurKernelPiS_iiPiS_ii
.globl _Z10blurKernelPiS_ii
.type _Z10blurKernelPiS_ii, @function
_Z10blurKernelPiS_ii:
.LFB4733:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10blurKernelPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4733:
.size _Z10blurKernelPiS_ii, .-_Z10blurKernelPiS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10blurKernelPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4735:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10blurKernelPiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4735:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "basic_string: construction from null is not valid"
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC5IS3_EEPKcRKS3_,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_:
.LFB5080:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 16(%rdi), %r12
movq %r12, (%rdi)
testq %rsi, %rsi
je .L22
movq %rdi, %rbx
movq %rsi, %r13
movq %rsi, %rdi
call strlen@PLT
movq %rax, %rbp
movq %rax, (%rsp)
cmpq $15, %rax
ja .L23
cmpq $1, %rax
jne .L18
movzbl 0(%r13), %eax
movb %al, 16(%rbx)
.L19:
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L25
leaq .LC1(%rip), %rdi
call _ZSt19__throw_logic_errorPKc@PLT
.L25:
call __stack_chk_fail@PLT
.L23:
movq %rsp, %rsi
movl $0, %edx
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %r12
movq %rax, (%rbx)
movq (%rsp), %rax
movq %rax, 16(%rbx)
.L17:
movq %rbp, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memcpy@PLT
jmp .L19
.L18:
testq %rax, %rax
je .L19
jmp .L17
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5080:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.set _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.section .rodata._ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE.str1.1,"aMS",@progbits,1
.LC2:
.string "P3"
.LC3:
.string "Wrong image type!!"
.LC4:
.string "255"
.LC5:
.string "Wrong image color depth!!"
.section .text._ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,"axG",@progbits,_ZN3ppmC5ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,comdat
.align 2
.weak _ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.type _ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, @function
_ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE:
.LFB4703:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4703
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $568, %rsp
.cfi_def_cfa_offset 624
movq %rdi, %rbx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 552(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %r12
leaq 288(%rsp), %rdi
call _ZNSt8ios_baseC2Ev@PLT
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 288(%rsp)
movq $0, 504(%rsp)
movb $0, 512(%rsp)
movb $0, 513(%rsp)
movq $0, 520(%rsp)
movq $0, 528(%rsp)
movq $0, 536(%rsp)
movq $0, 544(%rsp)
movq 8+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %r15
movq %r15, 32(%rsp)
movq -24(%r15), %rax
movq 16+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rcx
movq %rcx, 32(%rsp,%rax)
movq $0, 40(%rsp)
movq 32(%rsp), %rax
movq %r12, %rdi
addq -24(%rax), %rdi
movl $0, %esi
.LEHB0:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE0:
leaq 24+_ZTVSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 32(%rsp)
leaq 40(%rax), %rax
movq %rax, 288(%rsp)
leaq 48(%rsp), %rdi
.LEHB1:
call _ZNSt13basic_filebufIcSt11char_traitsIcEEC1Ev@PLT
.LEHE1:
leaq 48(%rsp), %rsi
leaq 288(%rsp), %rdi
.LEHB2:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE2:
jmp .L73
.L65:
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt13basic_filebufIcSt11char_traitsIcEED1Ev@PLT
.L29:
movq %r15, 32(%rsp)
movq -24(%r15), %rax
movq 16+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rcx
movq %rcx, 32(%rsp,%rax)
movq $0, 40(%rsp)
.L30:
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 288(%rsp)
leaq 288(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 552(%rsp), %rax
subq %fs:40, %rax
je .L31
call __stack_chk_fail@PLT
.L64:
endbr64
movq %rax, %rbx
jmp .L29
.L63:
endbr64
movq %rax, %rbx
jmp .L30
.L31:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L73:
movq 0(%rbp), %rsi
leaq 48(%rsp), %rdi
movl $8, %edx
.LEHB4:
call _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
testq %rax, %rax
je .L74
movq 32(%rsp), %rax
movq -24(%rax), %rax
leaq 32(%rsp,%rax), %rdi
movl $0, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L33
.L74:
movq 32(%rsp), %rax
movq -24(%rax), %rax
leaq 32(%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $4, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.LEHE4:
.L33:
movq %rsp, %rsi
leaq 16(%rsp), %rax
movq %rax, (%rsp)
movq $0, 8(%rsp)
movb $0, 16(%rsp)
leaq 32(%rsp), %rdi
.LEHB5:
call _ZStrsIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE@PLT
.LEHE5:
cmpq $2, 8(%rsp)
je .L75
.L34:
movl $16, %edi
call __cxa_allocate_exception@PLT
movq %rax, %rbp
leaq .LC3(%rip), %rsi
movq %rax, %rdi
.LEHB6:
call _ZNSt12out_of_rangeC1EPKc@PLT
.LEHE6:
jmp .L76
.L75:
movl $2, %edx
leaq .LC2(%rip), %rsi
movq (%rsp), %rdi
call memcmp@PLT
testl %eax, %eax
jne .L34
leaq 32(%rsp), %rdi
movq %rbx, %rsi
.LEHB7:
call _ZNSirsERi@PLT
jmp .L77
.L76:
movq 552(%rsp), %rax
subq %fs:40, %rax
je .L36
call __stack_chk_fail@PLT
.L36:
movq _ZNSt12out_of_rangeD1Ev@GOTPCREL(%rip), %rdx
leaq _ZTISt12out_of_range(%rip), %rsi
movq %rbp, %rdi
call __cxa_throw@PLT
.L60:
endbr64
movq %rax, %rbx
jmp .L52
.L77:
leaq 4(%rbx), %rsi
leaq 32(%rsp), %rdi
call _ZNSirsERi@PLT
movq %rsp, %rsi
leaq 32(%rsp), %rdi
call _ZStrsIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE@PLT
.LEHE7:
cmpq $3, 8(%rsp)
je .L78
.L37:
movl $16, %edi
call __cxa_allocate_exception@PLT
movq %rax, %rbp
leaq .LC5(%rip), %rsi
movq %rax, %rdi
.LEHB8:
call _ZNSt12out_of_rangeC1EPKc@PLT
.LEHE8:
jmp .L79
.L78:
movl $3, %edx
leaq .LC4(%rip), %rsi
movq (%rsp), %rdi
call memcmp@PLT
movl %eax, %r14d
testl %eax, %eax
jne .L37
movl 4(%rbx), %eax
imull (%rbx), %eax
leal (%rax,%rax,2), %eax
cltq
movabsq $2305843009213693950, %rdx
cmpq %rax, %rdx
jb .L40
leaq 0(,%rax,4), %rdi
.LEHB9:
call _Znam@PLT
jmp .L80
.L79:
movq 552(%rsp), %rax
subq %fs:40, %rax
je .L39
call __stack_chk_fail@PLT
.L39:
movq _ZNSt12out_of_rangeD1Ev@GOTPCREL(%rip), %rdx
leaq _ZTISt12out_of_range(%rip), %rsi
movq %rbp, %rdi
call __cxa_throw@PLT
.L80:
movq %rax, 8(%rbx)
movl %r14d, %r12d
leaq 32(%rsp), %r13
cmpl $0, 4(%rbx)
jg .L43
.L44:
leaq 48(%rsp), %rdi
call _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv@PLT
jmp .L81
.L40:
movq 552(%rsp), %rax
subq %fs:40, %rax
je .L42
call __stack_chk_fail@PLT
.L42:
call __cxa_throw_bad_array_new_length@PLT
.L82:
movl %r12d, %eax
imull (%rbx), %eax
leal (%rax,%rax,2), %eax
addl %ebp, %eax
cltq
movq 8(%rbx), %rdx
leaq 4(%rdx,%rax,4), %rsi
movq %r13, %rdi
call _ZNSirsERi@PLT
movl %r12d, %eax
imull (%rbx), %eax
leal (%rax,%rax,2), %eax
addl %ebp, %eax
cltq
movq 8(%rbx), %rdx
leaq 8(%rdx,%rax,4), %rsi
movq %r13, %rdi
call _ZNSirsERi@PLT
addl $3, %ebp
movl (%rbx), %eax
leal (%rax,%rax,2), %edx
cmpl %ebp, %edx
jle .L46
.L45:
imull %r12d, %eax
leal (%rax,%rax,2), %eax
addl %ebp, %eax
cltq
movq 8(%rbx), %rdx
leaq (%rdx,%rax,4), %rsi
movq %r13, %rdi
call _ZNSirsERi@PLT
.LEHE9:
jmp .L82
.L46:
addl $1, %r12d
cmpl %r12d, 4(%rbx)
jle .L44
.L43:
movl (%rbx), %eax
movl %r14d, %ebp
testl %eax, %eax
jg .L45
jmp .L46
.L81:
testq %rax, %rax
je .L83
.L47:
movq (%rsp), %rdi
leaq 16(%rsp), %rax
cmpq %rax, %rdi
je .L48
movq 16(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L48:
leaq 24+_ZTVSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 32(%rsp)
leaq 40(%rax), %rax
movq %rax, 288(%rsp)
leaq 16+_ZTVSt13basic_filebufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 48(%rsp)
leaq 48(%rsp), %rdi
.LEHB10:
call _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv@PLT
.LEHE10:
jmp .L50
.L83:
movq 32(%rsp), %rax
movq -24(%rax), %rax
leaq 32(%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $4, %esi
.LEHB11:
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.LEHE11:
jmp .L47
.L66:
endbr64
movq %rax, %rdi
call __cxa_begin_catch@PLT
call __cxa_end_catch@PLT
.L50:
leaq 152(%rsp), %rdi
call _ZNSt12__basic_fileIcED1Ev@PLT
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 48(%rsp)
leaq 104(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
movq %r15, 32(%rsp)
movq -24(%r15), %rax
movq 16+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rcx
movq %rcx, 32(%rsp,%rax)
movq $0, 40(%rsp)
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 288(%rsp)
leaq 288(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 552(%rsp), %rax
subq %fs:40, %rax
jne .L84
addq $568, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L61:
.cfi_restore_state
endbr64
movq %rax, %rbx
movq %rbp, %rdi
call __cxa_free_exception@PLT
.L52:
movq %rsp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L54:
leaq 32(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 552(%rsp), %rax
subq %fs:40, %rax
je .L55
call __stack_chk_fail@PLT
.L62:
endbr64
movq %rax, %rbx
movq %rbp, %rdi
call __cxa_free_exception@PLT
jmp .L52
.L59:
endbr64
movq %rax, %rbx
jmp .L54
.L55:
movq %rbx, %rdi
.LEHB12:
call _Unwind_Resume@PLT
.LEHE12:
.L84:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4703:
.globl __gxx_personality_v0
.section .gcc_except_table._ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,"aG",@progbits,_ZN3ppmC5ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,comdat
.align 4
.LLSDA4703:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT4703-.LLSDATTD4703
.LLSDATTD4703:
.byte 0x1
.uleb128 .LLSDACSE4703-.LLSDACSB4703
.LLSDACSB4703:
.uleb128 .LEHB0-.LFB4703
.uleb128 .LEHE0-.LEHB0
.uleb128 .L63-.LFB4703
.uleb128 0
.uleb128 .LEHB1-.LFB4703
.uleb128 .LEHE1-.LEHB1
.uleb128 .L64-.LFB4703
.uleb128 0
.uleb128 .LEHB2-.LFB4703
.uleb128 .LEHE2-.LEHB2
.uleb128 .L65-.LFB4703
.uleb128 0
.uleb128 .LEHB3-.LFB4703
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.uleb128 .LEHB4-.LFB4703
.uleb128 .LEHE4-.LEHB4
.uleb128 .L59-.LFB4703
.uleb128 0
.uleb128 .LEHB5-.LFB4703
.uleb128 .LEHE5-.LEHB5
.uleb128 .L60-.LFB4703
.uleb128 0
.uleb128 .LEHB6-.LFB4703
.uleb128 .LEHE6-.LEHB6
.uleb128 .L61-.LFB4703
.uleb128 0
.uleb128 .LEHB7-.LFB4703
.uleb128 .LEHE7-.LEHB7
.uleb128 .L60-.LFB4703
.uleb128 0
.uleb128 .LEHB8-.LFB4703
.uleb128 .LEHE8-.LEHB8
.uleb128 .L62-.LFB4703
.uleb128 0
.uleb128 .LEHB9-.LFB4703
.uleb128 .LEHE9-.LEHB9
.uleb128 .L60-.LFB4703
.uleb128 0
.uleb128 .LEHB10-.LFB4703
.uleb128 .LEHE10-.LEHB10
.uleb128 .L66-.LFB4703
.uleb128 0x1
.uleb128 .LEHB11-.LFB4703
.uleb128 .LEHE11-.LEHB11
.uleb128 .L60-.LFB4703
.uleb128 0
.uleb128 .LEHB12-.LFB4703
.uleb128 .LEHE12-.LEHB12
.uleb128 0
.uleb128 0
.LLSDACSE4703:
.byte 0x1
.byte 0
.align 4
.long 0
.LLSDATT4703:
.section .text._ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,"axG",@progbits,_ZN3ppmC5ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,comdat
.size _ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .-_ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.weak _ZN3ppmC1ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.set _ZN3ppmC1ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,_ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.section .rodata._ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE.str1.1,"aMS",@progbits,1
.LC6:
.string "P3\n"
.LC7:
.string " "
.LC8:
.string "\n"
.LC9:
.string "255\n"
.section .text._ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,"axG",@progbits,_ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,comdat
.align 2
.weak _ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.type _ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, @function
_ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE:
.LFB4705:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4705
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $536, %rsp
.cfi_def_cfa_offset 592
movq %rdi, %rbx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 520(%rsp)
xorl %eax, %eax
movq %rsp, %r12
leaq 248(%rsp), %rdi
call _ZNSt8ios_baseC2Ev@PLT
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 248(%rsp)
movq $0, 464(%rsp)
movb $0, 472(%rsp)
movb $0, 473(%rsp)
movq $0, 480(%rsp)
movq $0, 488(%rsp)
movq $0, 496(%rsp)
movq $0, 504(%rsp)
movq 8+_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %r14
movq %r14, (%rsp)
movq 16+_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %r15
movq -24(%r14), %rax
movq %r15, (%rsp,%rax)
movq (%rsp), %rax
movq %r12, %rdi
addq -24(%rax), %rdi
movl $0, %esi
.LEHB13:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE13:
leaq 24+_ZTVSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, (%rsp)
leaq 40(%rax), %rax
movq %rax, 248(%rsp)
leaq 8(%rsp), %rdi
.LEHB14:
call _ZNSt13basic_filebufIcSt11char_traitsIcEEC1Ev@PLT
.LEHE14:
leaq 8(%rsp), %rsi
leaq 248(%rsp), %rdi
.LEHB15:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
movq 0(%rbp), %rsi
leaq 8(%rsp), %rdi
movl $16, %edx
call _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
testq %rax, %rax
je .L116
movq (%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
movl $0, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L87
.L116:
movq (%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $4, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.LEHE15:
.L87:
movq %rsp, %rdi
movl $3, %edx
leaq .LC6(%rip), %rsi
.LEHB16:
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.LEHE16:
jmp .L117
.L108:
endbr64
movq %rax, %rbx
leaq 8(%rsp), %rdi
call _ZNSt13basic_filebufIcSt11char_traitsIcEED1Ev@PLT
.L90:
movq %r14, (%rsp)
movq -24(%r14), %rax
movq %r15, (%rsp,%rax)
.L91:
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 248(%rsp)
leaq 248(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 520(%rsp), %rax
subq %fs:40, %rax
je .L92
call __stack_chk_fail@PLT
.L107:
endbr64
movq %rax, %rbx
jmp .L90
.L106:
endbr64
movq %rax, %rbx
jmp .L91
.L92:
movq %rbx, %rdi
.LEHB17:
call _Unwind_Resume@PLT
.LEHE17:
.L117:
movl (%rbx), %esi
movq %rsp, %rdi
.LEHB18:
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $1, %edx
leaq .LC7(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 4(%rbx), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC8(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rsp, %rdi
movl $4, %edx
leaq .LC9(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $0, %r12d
leaq .LC8(%rip), %r13
cmpl $0, 4(%rbx)
jg .L93
.L94:
leaq 8(%rsp), %rdi
call _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv@PLT
jmp .L118
.L119:
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r12d, %eax
imull (%rbx), %eax
leal (%rax,%rax,2), %eax
addl %ebp, %eax
cltq
movq 8(%rbx), %rdx
movl 4(%rdx,%rax,4), %esi
movq %rsp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r12d, %eax
imull (%rbx), %eax
leal (%rax,%rax,2), %eax
addl %ebp, %eax
cltq
movq 8(%rbx), %rdx
movl 8(%rdx,%rax,4), %esi
movq %rsp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addl $3, %ebp
movl (%rbx), %eax
leal (%rax,%rax,2), %edx
cmpl %ebp, %edx
jle .L96
.L95:
imull %r12d, %eax
leal (%rax,%rax,2), %eax
addl %ebp, %eax
cltq
movq 8(%rbx), %rdx
movl (%rdx,%rax,4), %esi
movq %rsp, %rdi
call _ZNSolsEi@PLT
.LEHE18:
jmp .L119
.L96:
addl $1, %r12d
cmpl %r12d, 4(%rbx)
jle .L94
.L93:
movl (%rbx), %eax
movl $0, %ebp
testl %eax, %eax
jg .L95
jmp .L96
.L118:
testq %rax, %rax
je .L120
.L97:
leaq 24+_ZTVSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, (%rsp)
leaq 40(%rax), %rax
movq %rax, 248(%rsp)
leaq 16+_ZTVSt13basic_filebufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 8(%rsp)
leaq 8(%rsp), %rdi
.LEHB19:
call _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv@PLT
.LEHE19:
jmp .L99
.L120:
movq (%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $4, %esi
.LEHB20:
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.LEHE20:
jmp .L97
.L109:
endbr64
movq %rax, %rdi
call __cxa_begin_catch@PLT
call __cxa_end_catch@PLT
.L99:
leaq 112(%rsp), %rdi
call _ZNSt12__basic_fileIcED1Ev@PLT
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 8(%rsp)
leaq 64(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
movq %r14, (%rsp)
movq -24(%r14), %rax
movq %r15, (%rsp,%rax)
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 248(%rsp)
leaq 248(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 520(%rsp), %rax
subq %fs:40, %rax
jne .L121
addq $536, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L105:
.cfi_restore_state
endbr64
movq %rax, %rbx
movq %rsp, %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 520(%rsp), %rax
subq %fs:40, %rax
je .L101
call __stack_chk_fail@PLT
.L101:
movq %rbx, %rdi
.LEHB21:
call _Unwind_Resume@PLT
.LEHE21:
.L121:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4705:
.section .gcc_except_table._ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,"aG",@progbits,_ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,comdat
.align 4
.LLSDA4705:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT4705-.LLSDATTD4705
.LLSDATTD4705:
.byte 0x1
.uleb128 .LLSDACSE4705-.LLSDACSB4705
.LLSDACSB4705:
.uleb128 .LEHB13-.LFB4705
.uleb128 .LEHE13-.LEHB13
.uleb128 .L106-.LFB4705
.uleb128 0
.uleb128 .LEHB14-.LFB4705
.uleb128 .LEHE14-.LEHB14
.uleb128 .L107-.LFB4705
.uleb128 0
.uleb128 .LEHB15-.LFB4705
.uleb128 .LEHE15-.LEHB15
.uleb128 .L108-.LFB4705
.uleb128 0
.uleb128 .LEHB16-.LFB4705
.uleb128 .LEHE16-.LEHB16
.uleb128 .L105-.LFB4705
.uleb128 0
.uleb128 .LEHB17-.LFB4705
.uleb128 .LEHE17-.LEHB17
.uleb128 0
.uleb128 0
.uleb128 .LEHB18-.LFB4705
.uleb128 .LEHE18-.LEHB18
.uleb128 .L105-.LFB4705
.uleb128 0
.uleb128 .LEHB19-.LFB4705
.uleb128 .LEHE19-.LEHB19
.uleb128 .L109-.LFB4705
.uleb128 0x1
.uleb128 .LEHB20-.LFB4705
.uleb128 .LEHE20-.LEHB20
.uleb128 .L105-.LFB4705
.uleb128 0
.uleb128 .LEHB21-.LFB4705
.uleb128 .LEHE21-.LEHB21
.uleb128 0
.uleb128 0
.LLSDACSE4705:
.byte 0x1
.byte 0
.align 4
.long 0
.LLSDATT4705:
.section .text._ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,"axG",@progbits,_ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,comdat
.size _ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .-_ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.section .rodata.str1.1
.LC10:
.string "football.ppm"
.LC11:
.string "Size is: "
.LC12:
.string "bfootball.ppm"
.text
.globl main
.type main, @function
main:
.LFB4707:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4707
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $144, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 64(%rsp), %rdx
leaq 96(%rsp), %rbx
leaq .LC10(%rip), %rsi
movq %rbx, %rdi
.LEHB22:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE22:
leaq 32(%rsp), %rdi
movq %rbx, %rsi
.LEHB23:
call _ZN3ppmC1ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.LEHE23:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl 36(%rsp), %ebp
imull 32(%rsp), %ebp
leal 0(%rbp,%rbp,2), %r12d
leal 0(,%r12,4), %ebx
leaq .LC11(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB24:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r12d, %esi
call _ZNSolsEi@PLT
movslq %ebx, %rbx
movq %rsp, %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
leal 255(%rbp), %eax
testl %ebp, %ebp
cmovns %ebp, %eax
sarl $8, %eax
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L123
movl 36(%rsp), %ecx
movl 32(%rsp), %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z34__device_stub__Z10blurKernelPiS_iiPiS_ii
.L123:
movl 32(%rsp), %eax
movl %eax, 64(%rsp)
movl 36(%rsp), %edx
movl %edx, 68(%rsp)
imull %edx, %eax
leal (%rax,%rax,2), %edi
movslq %edi, %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L124
salq $2, %rdi
call _Znam@PLT
.LEHE24:
movq %rax, %rbp
movq %rax, 72(%rsp)
movq 40(%rsp), %rsi
movl 32(%rsp), %eax
imull 36(%rsp), %eax
leal (%rax,%rax,2), %edx
movslq %edx, %rdx
salq $2, %rdx
cmpq $4, %rdx
jle .L125
movq %rbp, %rdi
call memmove@PLT
.L126:
movl $2, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq %rbp, %rdi
.LEHB25:
call cudaMemcpy@PLT
.LEHE25:
jmp .L145
.L125:
jne .L126
movl (%rsi), %eax
movl %eax, 0(%rbp)
jmp .L126
.L124:
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L128
call __stack_chk_fail@PLT
.L128:
.LEHB26:
call __cxa_throw_bad_array_new_length@PLT
.LEHE26:
.L139:
endbr64
movq %rax, %rbx
jmp .L134
.L145:
leaq 20(%rsp), %rdx
leaq 96(%rsp), %rdi
leaq .LC12(%rip), %rsi
.LEHB27:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE27:
leaq 96(%rsp), %rsi
leaq 64(%rsp), %rdi
.LEHB28:
call _ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.LEHE28:
leaq 96(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq (%rsp), %rdi
.LEHB29:
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
.LEHE29:
movq %rbp, %rdi
call _ZdaPv@PLT
movq 40(%rsp), %rdi
testq %rdi, %rdi
je .L129
call _ZdaPv@PLT
.L129:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L146
movl $0, %eax
addq $144, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L138:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L131
call __stack_chk_fail@PLT
.L131:
movq %rbx, %rdi
.LEHB30:
call _Unwind_Resume@PLT
.L141:
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L133:
movq %rbp, %rdi
call _ZdaPv@PLT
.L134:
movq 40(%rsp), %rdi
testq %rdi, %rdi
je .L135
call _ZdaPv@PLT
.L135:
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L136
call __stack_chk_fail@PLT
.L140:
endbr64
movq %rax, %rbx
jmp .L133
.L136:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE30:
.L146:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4707:
.section .gcc_except_table,"a",@progbits
.LLSDA4707:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4707-.LLSDACSB4707
.LLSDACSB4707:
.uleb128 .LEHB22-.LFB4707
.uleb128 .LEHE22-.LEHB22
.uleb128 0
.uleb128 0
.uleb128 .LEHB23-.LFB4707
.uleb128 .LEHE23-.LEHB23
.uleb128 .L138-.LFB4707
.uleb128 0
.uleb128 .LEHB24-.LFB4707
.uleb128 .LEHE24-.LEHB24
.uleb128 .L139-.LFB4707
.uleb128 0
.uleb128 .LEHB25-.LFB4707
.uleb128 .LEHE25-.LEHB25
.uleb128 .L140-.LFB4707
.uleb128 0
.uleb128 .LEHB26-.LFB4707
.uleb128 .LEHE26-.LEHB26
.uleb128 .L139-.LFB4707
.uleb128 0
.uleb128 .LEHB27-.LFB4707
.uleb128 .LEHE27-.LEHB27
.uleb128 .L140-.LFB4707
.uleb128 0
.uleb128 .LEHB28-.LFB4707
.uleb128 .LEHE28-.LEHB28
.uleb128 .L141-.LFB4707
.uleb128 0
.uleb128 .LEHB29-.LFB4707
.uleb128 .LEHE29-.LEHB29
.uleb128 .L140-.LFB4707
.uleb128 0
.uleb128 .LEHB30-.LFB4707
.uleb128 .LEHE30-.LEHB30
.uleb128 0
.uleb128 0
.LLSDACSE4707:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "ppm.h"
const int BLUR_SIZE=10;
//used to blur a 2d color ppm image
__global__
void blurKernel(int* in, int* out,int w,int h){
int curpix=blockIdx.x*blockDim.x+threadIdx.x;
int row=curpix / w;
int col=curpix % w;
if ( row>=h ) return;
int pixr=0;
int pixg=0;
int pixb=0;
int pixels=0;
for (int br=-BLUR_SIZE; br<=BLUR_SIZE;br++){
for (int bc=-BLUR_SIZE; bc<=BLUR_SIZE;bc++){
int currow=row+br;
int curcol=col+bc;
if(currow>=0 && currow<h && curcol>=0 && curcol <w ){
pixels++;
int pdex= 3*(currow*w+curcol);
pixr+=in[pdex];
pixg+=in[pdex+1];
pixb+=in[pdex+2];
}
}
}
int dex=3*(row*w+col);
out[dex]= round((float)pixr/pixels);
out[dex+1]= round((float)pixg/pixels);
out[dex+2]= round((float)pixb/pixels);
}
int main(){
ppm football("football.ppm");
int numpixels=football.height*football.width;
int size=3*numpixels;
int arsize=sizeof(int)*size;
std::cout <<"Size is: "<< size;
int* d_football_data;
int* d_bfootball_data;
cudaMalloc((void**)&d_football_data,arsize);
cudaMalloc((void**)&d_bfootball_data,arsize );
cudaMemcpy(d_football_data,football.data,arsize,cudaMemcpyHostToDevice);
cudaMemcpy(d_bfootball_data,football.data,arsize,cudaMemcpyHostToDevice);
blurKernel<<<ceil(numpixels/256) ,256>>>(d_football_data,d_bfootball_data,football.width,football.height);
ppm bfootball(football);
cudaMemcpy(bfootball.data,d_bfootball_data,arsize,cudaMemcpyDeviceToHost);
bfootball.write("bfootball.ppm");
cudaFree(d_football_data);
cudaFree(d_bfootball_data);
} | #include <hip/hip_runtime.h>
#include "ppm.h"
const int BLUR_SIZE=10;
//used to blur a 2d color ppm image
__global__
void blurKernel(int* in, int* out,int w,int h){
int curpix=blockIdx.x*blockDim.x+threadIdx.x;
int row=curpix / w;
int col=curpix % w;
if ( row>=h ) return;
int pixr=0;
int pixg=0;
int pixb=0;
int pixels=0;
for (int br=-BLUR_SIZE; br<=BLUR_SIZE;br++){
for (int bc=-BLUR_SIZE; bc<=BLUR_SIZE;bc++){
int currow=row+br;
int curcol=col+bc;
if(currow>=0 && currow<h && curcol>=0 && curcol <w ){
pixels++;
int pdex= 3*(currow*w+curcol);
pixr+=in[pdex];
pixg+=in[pdex+1];
pixb+=in[pdex+2];
}
}
}
int dex=3*(row*w+col);
out[dex]= round((float)pixr/pixels);
out[dex+1]= round((float)pixg/pixels);
out[dex+2]= round((float)pixb/pixels);
}
int main(){
ppm football("football.ppm");
int numpixels=football.height*football.width;
int size=3*numpixels;
int arsize=sizeof(int)*size;
std::cout <<"Size is: "<< size;
int* d_football_data;
int* d_bfootball_data;
hipMalloc((void**)&d_football_data,arsize);
hipMalloc((void**)&d_bfootball_data,arsize );
hipMemcpy(d_football_data,football.data,arsize,hipMemcpyHostToDevice);
hipMemcpy(d_bfootball_data,football.data,arsize,hipMemcpyHostToDevice);
blurKernel<<<ceil(numpixels/256) ,256>>>(d_football_data,d_bfootball_data,football.width,football.height);
ppm bfootball(football);
hipMemcpy(bfootball.data,d_bfootball_data,arsize,hipMemcpyDeviceToHost);
bfootball.write("bfootball.ppm");
hipFree(d_football_data);
hipFree(d_bfootball_data);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "ppm.h"
const int BLUR_SIZE=10;
//used to blur a 2d color ppm image
__global__
void blurKernel(int* in, int* out,int w,int h){
int curpix=blockIdx.x*blockDim.x+threadIdx.x;
int row=curpix / w;
int col=curpix % w;
if ( row>=h ) return;
int pixr=0;
int pixg=0;
int pixb=0;
int pixels=0;
for (int br=-BLUR_SIZE; br<=BLUR_SIZE;br++){
for (int bc=-BLUR_SIZE; bc<=BLUR_SIZE;bc++){
int currow=row+br;
int curcol=col+bc;
if(currow>=0 && currow<h && curcol>=0 && curcol <w ){
pixels++;
int pdex= 3*(currow*w+curcol);
pixr+=in[pdex];
pixg+=in[pdex+1];
pixb+=in[pdex+2];
}
}
}
int dex=3*(row*w+col);
out[dex]= round((float)pixr/pixels);
out[dex+1]= round((float)pixg/pixels);
out[dex+2]= round((float)pixb/pixels);
}
int main(){
ppm football("football.ppm");
int numpixels=football.height*football.width;
int size=3*numpixels;
int arsize=sizeof(int)*size;
std::cout <<"Size is: "<< size;
int* d_football_data;
int* d_bfootball_data;
hipMalloc((void**)&d_football_data,arsize);
hipMalloc((void**)&d_bfootball_data,arsize );
hipMemcpy(d_football_data,football.data,arsize,hipMemcpyHostToDevice);
hipMemcpy(d_bfootball_data,football.data,arsize,hipMemcpyHostToDevice);
blurKernel<<<ceil(numpixels/256) ,256>>>(d_football_data,d_bfootball_data,football.width,football.height);
ppm bfootball(football);
hipMemcpy(bfootball.data,d_bfootball_data,arsize,hipMemcpyDeviceToHost);
bfootball.write("bfootball.ppm");
hipFree(d_football_data);
hipFree(d_bfootball_data);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10blurKernelPiS_ii
.globl _Z10blurKernelPiS_ii
.p2align 8
.type _Z10blurKernelPiS_ii,@function
_Z10blurKernelPiS_ii:
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x10
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_ashr_i32 s3, s6, 31
s_and_b32 s2, s2, 0xffff
s_add_i32 s4, s6, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s4, s4, s3
v_cvt_f32_u32_e32 v1, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_sub_i32 s2, 0, s4
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s2, v3
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v2
v_xor_b32_e32 v4, v4, v2
v_xor_b32_e32 v2, s3, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v0
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v0, s4
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s4, v3
v_cmp_le_u32_e32 vcc_lo, s4, v3
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s4, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v0, v2
v_cmpx_gt_i32_e64 s7, v4
s_cbranch_execz .LBB0_10
s_load_b64 s[8:9], s[0:1], 0x0
v_mul_lo_u32 v0, v4, s6
s_mul_i32 s2, s6, 10
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v6, 0
v_subrev_nc_u32_e32 v3, s2, v1
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v8, 0
s_mul_i32 s5, s6, 3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v0, v1, v0
v_mad_u64_u32 v[1:2], null, v3, 3, 0xffffffffffffffe2
s_mov_b32 s10, -10
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v1, s5, v1
s_add_i32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s10, 11
s_cbranch_scc1 .LBB0_9
.LBB0_3:
v_add_nc_u32_e32 v2, s10, v4
s_mov_b32 s11, -10
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v2
v_cmp_gt_i32_e64 s2, s7, v2
v_mov_b32_e32 v2, v1
s_branch .LBB0_6
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s4
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s12
v_add_nc_u32_e32 v2, 3, v2
s_add_i32 s11, s11, 1
s_cmp_eq_u32 s11, 11
s_cbranch_scc1 .LBB0_2
.LBB0_6:
s_and_saveexec_b32 s12, vcc_lo
s_cbranch_execz .LBB0_5
v_add_nc_u32_e32 v3, s11, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_lt_i32_e64 s3, -1, v3
v_cmp_gt_i32_e64 s4, s6, v3
s_and_b32 s3, s2, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s3, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB0_4
v_ashrrev_i32_e32 v3, 31, v2
v_add_nc_u32_e32 v8, 1, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, s3, s8, v9
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v10, s3, s9, v10, s3
global_load_b96 v[9:11], v[9:10], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v7, v9, v7
v_add_nc_u32_e32 v6, v10, v6
v_add_nc_u32_e32 v5, v11, v5
s_branch .LBB0_4
.LBB0_9:
s_set_inst_prefetch_distance 0x2
v_cvt_f32_i32_e32 v1, v7
v_cvt_f32_i32_e32 v3, v8
v_cvt_f32_i32_e32 v2, v6
v_cvt_f32_i32_e32 v5, v5
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_scale_f32 v6, null, v3, v3, v1
v_div_scale_f32 v7, null, v3, v3, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_scale_f32 v8, null, v3, v3, v5
v_rcp_f32_e32 v9, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v10, v7
v_div_scale_f32 v12, vcc_lo, v1, v3, v1
v_rcp_f32_e32 v11, v8
v_div_scale_f32 v13, s2, v2, v3, v2
v_div_scale_f32 v17, s3, v5, v3, v5
s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_fma_f32 v14, -v6, v9, 1.0
s_waitcnt_depctr 0xfff
v_fma_f32 v15, -v7, v10, 1.0
v_fma_f32 v16, -v8, v11, 1.0
v_dual_fmac_f32 v9, v14, v9 :: v_dual_fmac_f32 v10, v15, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v14, v12, v9 :: v_dual_mul_f32 v15, v13, v10
v_fma_f32 v18, -v6, v14, v12
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v11, v16, v11
v_fma_f32 v19, -v7, v15, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v14, v18, v9
v_dual_mul_f32 v16, v17, v11 :: v_dual_fmac_f32 v15, v19, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v6, -v6, v14, v12
v_fma_f32 v20, -v8, v16, v17
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v7, -v7, v15, v13
v_div_fmas_f32 v6, v6, v9, v14
s_mov_b32 vcc_lo, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v7, v7, v10, v15
s_mov_b32 vcc_lo, s3
v_div_fixup_f32 v6, v6, v3, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fixup_f32 v7, v7, v3, v2
v_mad_u64_u32 v[1:2], null, v4, s6, v[0:1]
v_trunc_f32_e32 v4, v7
v_fmac_f32_e32 v16, v20, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshl_add_u32 v0, v1, 1, v1
v_sub_f32_e32 v9, v7, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v8, v16, v17
v_div_fmas_f32 v8, v8, v11, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fixup_f32 v2, v8, v3, v5
v_trunc_f32_e32 v3, v6
v_trunc_f32_e32 v5, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v8, v6, v3
v_cmp_ge_f32_e64 s2, |v8|, 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v8, 0, 1.0, s2
v_cmp_ge_f32_e64 s2, |v9|, 0.5
v_bfi_b32 v6, 0x7fffffff, v8, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v9, 0, 1.0, s2
v_add_f32_e32 v3, v3, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_bfi_b32 v7, 0x7fffffff, v9, v7
v_dual_sub_f32 v1, v2, v5 :: v_dual_add_f32 v6, v4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_ge_f32_e64 s2, |v1|, 0.5
v_ashrrev_i32_e32 v1, 31, v0
v_cndmask_b32_e64 v10, 0, 1.0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_bfi_b32 v8, 0x7fffffff, v10, v2
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_cvt_i32_f32_e32 v0, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f32_e32 v5, v5, v8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v2, vcc_lo
v_cvt_i32_f32_e32 v1, v6
v_cvt_i32_f32_e32 v2, v5
global_store_b96 v[3:4], v[0:2], off
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10blurKernelPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10blurKernelPiS_ii, .Lfunc_end0-_Z10blurKernelPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10blurKernelPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10blurKernelPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "ppm.h"
const int BLUR_SIZE=10;
//used to blur a 2d color ppm image
__global__
void blurKernel(int* in, int* out,int w,int h){
int curpix=blockIdx.x*blockDim.x+threadIdx.x;
int row=curpix / w;
int col=curpix % w;
if ( row>=h ) return;
int pixr=0;
int pixg=0;
int pixb=0;
int pixels=0;
for (int br=-BLUR_SIZE; br<=BLUR_SIZE;br++){
for (int bc=-BLUR_SIZE; bc<=BLUR_SIZE;bc++){
int currow=row+br;
int curcol=col+bc;
if(currow>=0 && currow<h && curcol>=0 && curcol <w ){
pixels++;
int pdex= 3*(currow*w+curcol);
pixr+=in[pdex];
pixg+=in[pdex+1];
pixb+=in[pdex+2];
}
}
}
int dex=3*(row*w+col);
out[dex]= round((float)pixr/pixels);
out[dex+1]= round((float)pixg/pixels);
out[dex+2]= round((float)pixb/pixels);
}
int main(){
ppm football("football.ppm");
int numpixels=football.height*football.width;
int size=3*numpixels;
int arsize=sizeof(int)*size;
std::cout <<"Size is: "<< size;
int* d_football_data;
int* d_bfootball_data;
hipMalloc((void**)&d_football_data,arsize);
hipMalloc((void**)&d_bfootball_data,arsize );
hipMemcpy(d_football_data,football.data,arsize,hipMemcpyHostToDevice);
hipMemcpy(d_bfootball_data,football.data,arsize,hipMemcpyHostToDevice);
blurKernel<<<ceil(numpixels/256) ,256>>>(d_football_data,d_bfootball_data,football.width,football.height);
ppm bfootball(football);
hipMemcpy(bfootball.data,d_bfootball_data,arsize,hipMemcpyDeviceToHost);
bfootball.write("bfootball.ppm");
hipFree(d_football_data);
hipFree(d_bfootball_data);
} | .text
.file "blurKernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z25__device_stub__blurKernelPiS_ii # -- Begin function _Z25__device_stub__blurKernelPiS_ii
.p2align 4, 0x90
.type _Z25__device_stub__blurKernelPiS_ii,@function
_Z25__device_stub__blurKernelPiS_ii: # @_Z25__device_stub__blurKernelPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10blurKernelPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__blurKernelPiS_ii, .Lfunc_end0-_Z25__device_stub__blurKernelPiS_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $216, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 136(%rsp), %r14
movq %r14, 120(%rsp)
movabsq $7812726529069117286, %rax # imm = 0x6C6C6162746F6F66
movq %rax, 136(%rsp)
movl $1836085294, 144(%rsp) # imm = 0x6D70702E
movq $12, 128(%rsp)
movb $0, 148(%rsp)
.Ltmp0:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
leaq 120(%rsp), %rsi
callq _ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Ltmp1:
# %bb.1:
movq 120(%rsp), %rdi
cmpq %r14, %rdi
je .LBB1_3
# %bb.2: # %.critedge.i.i
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_3: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movl 16(%rsp), %r14d
imull 20(%rsp), %r14d
.Ltmp3:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp4:
# %bb.4: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
leal (%r14,%r14,2), %esi
.Ltmp5:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSolsEi
.Ltmp6:
# %bb.5:
leal (,%r14,4), %eax
leal (%rax,%rax,2), %eax
movslq %eax, %rbx
.Ltmp8:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
.Ltmp9:
# %bb.6:
.Ltmp10:
.cfi_escape 0x2e, 0x00
movq %rsp, %rdi
movq %rbx, %rsi
callq hipMalloc
.Ltmp11:
# %bb.7:
movq 8(%rsp), %rdi
movq 24(%rsp), %rsi
.Ltmp12:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
.Ltmp13:
# %bb.8:
movq (%rsp), %rdi
movq 24(%rsp), %rsi
.Ltmp14:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
.Ltmp15:
# %bb.9:
leal 255(%r14), %eax
testl %r14d, %r14d
cmovnsl %r14d, %eax
sarl $8, %eax
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rax, %rdi
.Ltmp16:
.cfi_escape 0x2e, 0x00
movabsq $4294967552, %rdx # imm = 0x100000100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp17:
# %bb.10:
testl %eax, %eax
jne .LBB1_13
# %bb.11:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movl 16(%rsp), %edx
movl 20(%rsp), %esi
movq %rax, 208(%rsp)
movq %rcx, 200(%rsp)
movl %edx, 44(%rsp)
movl %esi, 40(%rsp)
leaq 208(%rsp), %rax
movq %rax, 48(%rsp)
leaq 200(%rsp), %rax
movq %rax, 56(%rsp)
leaq 44(%rsp), %rax
movq %rax, 64(%rsp)
leaq 40(%rsp), %rax
movq %rax, 72(%rsp)
.Ltmp18:
.cfi_escape 0x2e, 0x00
leaq 184(%rsp), %rdi
leaq 168(%rsp), %rsi
leaq 160(%rsp), %rdx
leaq 152(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp19:
# %bb.12: # %.noexc32
movq 184(%rsp), %rsi
movl 192(%rsp), %edx
movq 168(%rsp), %rcx
movl 176(%rsp), %r8d
.Ltmp20:
.cfi_escape 0x2e, 0x10
leaq 48(%rsp), %r9
movl $_Z10blurKernelPiS_ii, %edi
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 168(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp21:
.LBB1_13:
movl 16(%rsp), %eax
movl 20(%rsp), %r15d
movl %eax, 48(%rsp)
movl %r15d, 52(%rsp)
imull %eax, %r15d
leal (%r15,%r15,2), %ebp
movslq %ebp, %rax
shlq $2, %rax
testl %r15d, %r15d
movq $-1, %rdi
cmovnsq %rax, %rdi
.Ltmp23:
.cfi_escape 0x2e, 0x00
callq _Znam
.Ltmp24:
# %bb.14: # %.noexc37
movq %rax, %r14
movq %rax, 56(%rsp)
testl %r15d, %r15d
jle .LBB1_16
# %bb.15:
movq 24(%rsp), %rsi
movl %ebp, %edx
shlq $2, %rdx
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq memmove@PLT
.LBB1_16: # %_ZN3ppmC2ERS_.exit
movq (%rsp), %rsi
.Ltmp26:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
.Ltmp27:
# %bb.17: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit44
leaq 104(%rsp), %r14
movq %r14, 88(%rsp)
movabsq $7809631481062450786, %rax # imm = 0x6C6162746F6F6662
movq %rax, 104(%rsp)
movabsq $7885926292215587170, %rax # imm = 0x6D70702E6C6C6162
movq %rax, 109(%rsp)
movq $13, 96(%rsp)
movb $0, 117(%rsp)
.Ltmp28:
.cfi_escape 0x2e, 0x00
leaq 48(%rsp), %rdi
leaq 88(%rsp), %rsi
callq _ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Ltmp29:
# %bb.18:
movq 88(%rsp), %rdi
cmpq %r14, %rdi
je .LBB1_20
# %bb.19: # %.critedge.i.i45
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_20: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit47
movq 8(%rsp), %rdi
.Ltmp31:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp32:
# %bb.21:
movq (%rsp), %rdi
.Ltmp33:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp34:
# %bb.22:
movq 56(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_24
# %bb.23:
.cfi_escape 0x2e, 0x00
callq _ZdaPv
.LBB1_24: # %_ZN3ppmD2Ev.exit
movq 24(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_26
# %bb.25:
.cfi_escape 0x2e, 0x00
callq _ZdaPv
.LBB1_26: # %_ZN3ppmD2Ev.exit48
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_27:
.cfi_def_cfa_offset 256
.Ltmp30:
movq %rax, %rbx
movq 88(%rsp), %rdi
cmpq %r14, %rdi
je .LBB1_34
# %bb.28: # %.critedge.i.i49
.cfi_escape 0x2e, 0x00
callq _ZdlPv
jmp .LBB1_34
.LBB1_29:
.Ltmp25:
jmp .LBB1_37
.LBB1_30:
.Ltmp2:
movq %rax, %rbx
movq 120(%rsp), %rdi
cmpq %r14, %rdi
je .LBB1_40
# %bb.31: # %.critedge.i.i34
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.LBB1_32:
.Ltmp7:
jmp .LBB1_37
.LBB1_33:
.Ltmp35:
movq %rax, %rbx
.LBB1_34: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit51
movq 56(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_38
# %bb.35:
.cfi_escape 0x2e, 0x00
callq _ZdaPv
jmp .LBB1_38
.LBB1_36:
.Ltmp22:
.LBB1_37:
movq %rax, %rbx
.LBB1_38:
movq 24(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_40
# %bb.39:
.cfi_escape 0x2e, 0x00
callq _ZdaPv
.LBB1_40: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit36
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp6-.Ltmp3 # Call between .Ltmp3 and .Ltmp6
.uleb128 .Ltmp7-.Lfunc_begin0 # jumps to .Ltmp7
.byte 0 # On action: cleanup
.uleb128 .Ltmp8-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp21-.Ltmp8 # Call between .Ltmp8 and .Ltmp21
.uleb128 .Ltmp22-.Lfunc_begin0 # jumps to .Ltmp22
.byte 0 # On action: cleanup
.uleb128 .Ltmp23-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp24-.Ltmp23 # Call between .Ltmp23 and .Ltmp24
.uleb128 .Ltmp25-.Lfunc_begin0 # jumps to .Ltmp25
.byte 0 # On action: cleanup
.uleb128 .Ltmp24-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp26-.Ltmp24 # Call between .Ltmp24 and .Ltmp26
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp26-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp27-.Ltmp26 # Call between .Ltmp26 and .Ltmp27
.uleb128 .Ltmp35-.Lfunc_begin0 # jumps to .Ltmp35
.byte 0 # On action: cleanup
.uleb128 .Ltmp28-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp29-.Ltmp28 # Call between .Ltmp28 and .Ltmp29
.uleb128 .Ltmp30-.Lfunc_begin0 # jumps to .Ltmp30
.byte 0 # On action: cleanup
.uleb128 .Ltmp31-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp34-.Ltmp31 # Call between .Ltmp31 and .Ltmp34
.uleb128 .Ltmp35-.Lfunc_begin0 # jumps to .Ltmp35
.byte 0 # On action: cleanup
.uleb128 .Ltmp34-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Lfunc_end1-.Ltmp34 # Call between .Ltmp34 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .text._ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,"axG",@progbits,_ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,comdat
.weak _ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE # -- Begin function _ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.p2align 4, 0x90
.type _ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,@function
_ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE: # @_ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $552, %rsp # imm = 0x228
.cfi_def_cfa_offset 608
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r12
movq %rdi, %rbx
leaq 32(%rsp), %r15
movq %r15, %rdi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev
leaq 48(%rsp), %rdi
movq (%r12), %rsi
.Ltmp36:
movl $8, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp37:
# %bb.1: # %.noexc
movq 32(%rsp), %rcx
addq -24(%rcx), %r15
xorl %esi, %esi
testq %rax, %rax
jne .LBB2_3
# %bb.2:
movl 32(%r15), %esi
orl $4, %esi
.LBB2_3: # %.invoke
.Ltmp38:
movq %r15, %rdi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp39:
# %bb.4: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openERKNSt7__cxx1112basic_stringIcS1_SaIcEEESt13_Ios_Openmode.exit
leaq 16(%rsp), %rax
movq %rax, (%rsp)
movq $0, 8(%rsp)
movb $0, 16(%rsp)
.Ltmp41:
leaq 32(%rsp), %rdi
movq %rsp, %rsi
callq _ZStrsIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE
.Ltmp42:
# %bb.5:
movq 8(%rsp), %rdx
cmpq $2, %rdx
jne .LBB2_7
# %bb.6: # %_ZSteqIcSt11char_traitsIcESaIcEEbRKNSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_.exit
movq (%rsp), %rdi
movl $.L.str.5, %esi
callq bcmp@PLT
testl %eax, %eax
jne .LBB2_7
# %bb.11: # %.critedge29
.Ltmp46:
leaq 32(%rsp), %rdi
movq %rbx, %rsi
callq _ZNSirsERi
.Ltmp47:
# %bb.12:
leaq 4(%rbx), %r15
.Ltmp48:
leaq 32(%rsp), %rdi
movq %r15, %rsi
callq _ZNSirsERi
.Ltmp49:
# %bb.13:
.Ltmp50:
leaq 32(%rsp), %rdi
movq %rsp, %rsi
callq _ZStrsIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE
.Ltmp51:
# %bb.14:
movq 8(%rsp), %rdx
cmpq $3, %rdx
jne .LBB2_16
# %bb.15: # %_ZSteqIcSt11char_traitsIcESaIcEEbRKNSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_.exit22
movq (%rsp), %rdi
movl $.L.str.7, %esi
callq bcmp@PLT
testl %eax, %eax
jne .LBB2_16
# %bb.20: # %.critedge31
movslq 4(%rbx), %rax
movslq (%rbx), %rcx
imulq %rax, %rcx
movq %rcx, %rax
shlq $2, %rax
testl %ecx, %ecx
leaq (%rax,%rax,2), %rax
movq $-1, %rdi
cmovnsq %rax, %rdi
.Ltmp57:
callq _Znam
.Ltmp58:
# %bb.21:
movq %rax, 8(%rbx)
cmpl $0, 4(%rbx)
jle .LBB2_30
# %bb.22: # %.preheader.preheader
xorl %ebp, %ebp
leaq 32(%rsp), %r12
xorl %r13d, %r13d
jmp .LBB2_23
.p2align 4, 0x90
.LBB2_29: # %._crit_edge
# in Loop: Header=BB2_23 Depth=1
incl %r13d
addl $3, %ebp
cmpl (%r15), %r13d
jge .LBB2_30
.LBB2_23: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_25 Depth 2
movl (%rbx), %eax
testl %eax, %eax
jle .LBB2_29
# %bb.24: # %.lr.ph
# in Loop: Header=BB2_23 Depth=1
leal (%rax,%rax,2), %eax
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_25: # Parent Loop BB2_23 Depth=1
# => This Inner Loop Header: Depth=2
imull %r13d, %eax
movslq %eax, %rsi
addq %r14, %rsi
shlq $2, %rsi
addq 8(%rbx), %rsi
.Ltmp59:
movq %r12, %rdi
callq _ZNSirsERi
.Ltmp60:
# %bb.26: # in Loop: Header=BB2_25 Depth=2
movq 8(%rbx), %rax
movl (%rbx), %ecx
imull %ebp, %ecx
movslq %ecx, %rcx
addq %r14, %rcx
leaq (%rax,%rcx,4), %rsi
addq $4, %rsi
.Ltmp61:
movq %r12, %rdi
callq _ZNSirsERi
.Ltmp62:
# %bb.27: # in Loop: Header=BB2_25 Depth=2
movq 8(%rbx), %rax
movl (%rbx), %ecx
imull %ebp, %ecx
movslq %ecx, %rcx
addq %r14, %rcx
leaq (%rax,%rcx,4), %rsi
addq $8, %rsi
.Ltmp63:
movq %r12, %rdi
callq _ZNSirsERi
.Ltmp64:
# %bb.28: # in Loop: Header=BB2_25 Depth=2
movl (%rbx), %eax
leal (%rax,%rax,2), %eax
addq $3, %r14
cmpl %eax, %r14d
jl .LBB2_25
jmp .LBB2_29
.LBB2_30: # %._crit_edge34
.Ltmp66:
leaq 48(%rsp), %rdi
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp67:
# %bb.31: # %.noexc24
testq %rax, %rax
jne .LBB2_33
# %bb.32:
movq 32(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $32, %rdi
movl 64(%rsp,%rax), %esi
orl $4, %esi
.Ltmp68:
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp69:
.LBB2_33: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv.exit
movq (%rsp), %rdi
leaq 16(%rsp), %rax
cmpq %rax, %rdi
je .LBB2_35
# %bb.34: # %.critedge.i.i
callq _ZdlPv
.LBB2_35: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
leaq 32(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 288(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
addq $552, %rsp # imm = 0x228
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_7: # %.critedge
.cfi_def_cfa_offset 608
movl $16, %edi
callq __cxa_allocate_exception
movq %rax, %r14
.Ltmp43:
movl $.L.str.6, %esi
movq %rax, %rdi
callq _ZNSt12out_of_rangeC1EPKc
.Ltmp44:
jmp .LBB2_17
.LBB2_16: # %.critedge30
movl $16, %edi
callq __cxa_allocate_exception
movq %rax, %r14
.Ltmp52:
movl $.L.str.8, %esi
movq %rax, %rdi
callq _ZNSt12out_of_rangeC1EPKc
.Ltmp53:
.LBB2_17: # %.invoke35
.Ltmp55:
movl $_ZTISt12out_of_range, %esi
movl $_ZNSt12out_of_rangeD1Ev, %edx
movq %r14, %rdi
callq __cxa_throw
.Ltmp56:
# %bb.18: # %.cont
.LBB2_19:
.Ltmp54:
jmp .LBB2_10
.LBB2_9:
.Ltmp45:
.LBB2_10:
movq %rax, %rbx
movq %r14, %rdi
callq __cxa_free_exception
jmp .LBB2_38
.LBB2_8:
.Ltmp40:
movq %rax, %rbx
jmp .LBB2_40
.LBB2_36:
.Ltmp70:
jmp .LBB2_37
.LBB2_41:
.Ltmp65:
.LBB2_37:
movq %rax, %rbx
.LBB2_38:
movq (%rsp), %rdi
leaq 16(%rsp), %rax
cmpq %rax, %rdi
je .LBB2_40
# %bb.39: # %.critedge.i.i26
callq _ZdlPv
.LBB2_40:
leaq 32(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 288(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size _ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .Lfunc_end2-_ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.cfi_endproc
.section .gcc_except_table._ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,"aG",@progbits,_ZN3ppmC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,comdat
.p2align 2, 0x0
GCC_except_table2:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Lfunc_begin1-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp36-.Lfunc_begin1 # Call between .Lfunc_begin1 and .Ltmp36
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp36-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Ltmp39-.Ltmp36 # Call between .Ltmp36 and .Ltmp39
.uleb128 .Ltmp40-.Lfunc_begin1 # jumps to .Ltmp40
.byte 0 # On action: cleanup
.uleb128 .Ltmp41-.Lfunc_begin1 # >> Call Site 3 <<
.uleb128 .Ltmp58-.Ltmp41 # Call between .Ltmp41 and .Ltmp58
.uleb128 .Ltmp70-.Lfunc_begin1 # jumps to .Ltmp70
.byte 0 # On action: cleanup
.uleb128 .Ltmp59-.Lfunc_begin1 # >> Call Site 4 <<
.uleb128 .Ltmp64-.Ltmp59 # Call between .Ltmp59 and .Ltmp64
.uleb128 .Ltmp65-.Lfunc_begin1 # jumps to .Ltmp65
.byte 0 # On action: cleanup
.uleb128 .Ltmp66-.Lfunc_begin1 # >> Call Site 5 <<
.uleb128 .Ltmp69-.Ltmp66 # Call between .Ltmp66 and .Ltmp69
.uleb128 .Ltmp70-.Lfunc_begin1 # jumps to .Ltmp70
.byte 0 # On action: cleanup
.uleb128 .Ltmp69-.Lfunc_begin1 # >> Call Site 6 <<
.uleb128 .Ltmp43-.Ltmp69 # Call between .Ltmp69 and .Ltmp43
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp43-.Lfunc_begin1 # >> Call Site 7 <<
.uleb128 .Ltmp44-.Ltmp43 # Call between .Ltmp43 and .Ltmp44
.uleb128 .Ltmp45-.Lfunc_begin1 # jumps to .Ltmp45
.byte 0 # On action: cleanup
.uleb128 .Ltmp44-.Lfunc_begin1 # >> Call Site 8 <<
.uleb128 .Ltmp52-.Ltmp44 # Call between .Ltmp44 and .Ltmp52
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp52-.Lfunc_begin1 # >> Call Site 9 <<
.uleb128 .Ltmp53-.Ltmp52 # Call between .Ltmp52 and .Ltmp53
.uleb128 .Ltmp54-.Lfunc_begin1 # jumps to .Ltmp54
.byte 0 # On action: cleanup
.uleb128 .Ltmp55-.Lfunc_begin1 # >> Call Site 10 <<
.uleb128 .Ltmp56-.Ltmp55 # Call between .Ltmp55 and .Ltmp56
.uleb128 .Ltmp70-.Lfunc_begin1 # jumps to .Ltmp70
.byte 0 # On action: cleanup
.uleb128 .Ltmp56-.Lfunc_begin1 # >> Call Site 11 <<
.uleb128 .Lfunc_end2-.Ltmp56 # Call between .Ltmp56 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.p2align 2, 0x0
# -- End function
.section .text._ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,"axG",@progbits,_ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,comdat
.weak _ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE # -- Begin function _ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.p2align 4, 0x90
.type _ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,@function
_ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE: # @_ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Lfunc_begin2:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception2
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $512, %rsp # imm = 0x200
.cfi_def_cfa_offset 560
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
movq %rsp, %r14
movq %r14, %rdi
movl $16, %edx
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1ERKNSt7__cxx1112basic_stringIcS1_SaIcEEESt13_Ios_Openmode
.Ltmp71:
movl $.L.str.9, %esi
movl $3, %edx
movq %r14, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp72:
# %bb.1: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movl (%rbx), %esi
.Ltmp73:
movq %rsp, %rdi
callq _ZNSolsEi
.Ltmp74:
# %bb.2:
.Ltmp75:
movq %rax, %r14
movl $.L.str.10, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp76:
# %bb.3: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit17
movl 4(%rbx), %esi
.Ltmp77:
movq %r14, %rdi
callq _ZNSolsEi
.Ltmp78:
# %bb.4:
.Ltmp79:
movl $.L.str.11, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp80:
# %bb.5: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit18
.Ltmp81:
movq %rsp, %rdi
movl $.L.str.12, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp82:
# %bb.6: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit19.preheader
cmpl $0, 4(%rbx)
jle .LBB3_18
# %bb.7: # %.preheader.lr.ph
xorl %r15d, %r15d
movq %rsp, %r14
xorl %ebp, %ebp
jmp .LBB3_8
.p2align 4, 0x90
.LBB3_17: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit19
# in Loop: Header=BB3_8 Depth=1
incl %ebp
addl $3, %r15d
cmpl 4(%rbx), %ebp
jge .LBB3_18
.LBB3_8: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_10 Depth 2
movl (%rbx), %eax
testl %eax, %eax
jle .LBB3_17
# %bb.9: # %.lr.ph
# in Loop: Header=BB3_8 Depth=1
leal (%rax,%rax,2), %eax
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_10: # Parent Loop BB3_8 Depth=1
# => This Inner Loop Header: Depth=2
movq 8(%rbx), %rcx
imull %ebp, %eax
cltq
addq %r12, %rax
movl (%rcx,%rax,4), %esi
.Ltmp83:
movq %r14, %rdi
callq _ZNSolsEi
.Ltmp84:
# %bb.11: # in Loop: Header=BB3_10 Depth=2
.Ltmp85:
movl $.L.str.11, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp86:
# %bb.12: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit22
# in Loop: Header=BB3_10 Depth=2
movq 8(%rbx), %rax
movl (%rbx), %ecx
imull %r15d, %ecx
movslq %ecx, %rcx
addq %r12, %rcx
movl 4(%rax,%rcx,4), %esi
.Ltmp87:
movq %r14, %rdi
callq _ZNSolsEi
.Ltmp88:
# %bb.13: # in Loop: Header=BB3_10 Depth=2
.Ltmp89:
movl $.L.str.11, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp90:
# %bb.14: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit24
# in Loop: Header=BB3_10 Depth=2
movq 8(%rbx), %rax
movl (%rbx), %ecx
imull %r15d, %ecx
movslq %ecx, %rcx
addq %r12, %rcx
movl 8(%rax,%rcx,4), %esi
.Ltmp91:
movq %r14, %rdi
callq _ZNSolsEi
.Ltmp92:
# %bb.15: # in Loop: Header=BB3_10 Depth=2
.Ltmp93:
movl $.L.str.11, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp94:
# %bb.16: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit26
# in Loop: Header=BB3_10 Depth=2
movl (%rbx), %eax
leal (%rax,%rax,2), %eax
addq $3, %r12
cmpl %eax, %r12d
jl .LBB3_10
jmp .LBB3_17
.LBB3_18: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit19._crit_edge
leaq 8(%rsp), %rdi
.Ltmp96:
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp97:
# %bb.19: # %.noexc
testq %rax, %rax
jne .LBB3_21
# %bb.20:
movq (%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
movl 32(%rsp,%rax), %esi
orl $4, %esi
.Ltmp98:
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp99:
.LBB3_21: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv.exit
movq %rsp, %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
addq $512, %rsp # imm = 0x200
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_22:
.cfi_def_cfa_offset 560
.Ltmp100:
jmp .LBB3_23
.LBB3_24:
.Ltmp95:
.LBB3_23:
movq %rax, %rbx
movq %rsp, %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end3:
.size _ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .Lfunc_end3-_ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.cfi_endproc
.section .gcc_except_table._ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,"aG",@progbits,_ZN3ppm5writeENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,comdat
.p2align 2, 0x0
GCC_except_table3:
.Lexception2:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end2-.Lcst_begin2
.Lcst_begin2:
.uleb128 .Lfunc_begin2-.Lfunc_begin2 # >> Call Site 1 <<
.uleb128 .Ltmp71-.Lfunc_begin2 # Call between .Lfunc_begin2 and .Ltmp71
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp71-.Lfunc_begin2 # >> Call Site 2 <<
.uleb128 .Ltmp82-.Ltmp71 # Call between .Ltmp71 and .Ltmp82
.uleb128 .Ltmp100-.Lfunc_begin2 # jumps to .Ltmp100
.byte 0 # On action: cleanup
.uleb128 .Ltmp83-.Lfunc_begin2 # >> Call Site 3 <<
.uleb128 .Ltmp94-.Ltmp83 # Call between .Ltmp83 and .Ltmp94
.uleb128 .Ltmp95-.Lfunc_begin2 # jumps to .Ltmp95
.byte 0 # On action: cleanup
.uleb128 .Ltmp96-.Lfunc_begin2 # >> Call Site 4 <<
.uleb128 .Ltmp99-.Ltmp96 # Call between .Ltmp96 and .Ltmp99
.uleb128 .Ltmp100-.Lfunc_begin2 # jumps to .Ltmp100
.byte 0 # On action: cleanup
.uleb128 .Ltmp99-.Lfunc_begin2 # >> Call Site 5 <<
.uleb128 .Lfunc_end3-.Ltmp99 # Call between .Ltmp99 and .Lfunc_end3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end2:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10blurKernelPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10blurKernelPiS_ii,@object # @_Z10blurKernelPiS_ii
.section .rodata,"a",@progbits
.globl _Z10blurKernelPiS_ii
.p2align 3, 0x0
_Z10blurKernelPiS_ii:
.quad _Z25__device_stub__blurKernelPiS_ii
.size _Z10blurKernelPiS_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "football.ppm"
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Size is: "
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "bfootball.ppm"
.size .L.str.2, 14
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "P3"
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Wrong image type!!"
.size .L.str.6, 19
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "255"
.size .L.str.7, 4
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Wrong image color depth!!"
.size .L.str.8, 26
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "P3\n"
.size .L.str.9, 4
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz " "
.size .L.str.10, 2
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "\n"
.size .L.str.11, 2
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "255\n"
.size .L.str.12, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10blurKernelPiS_ii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__blurKernelPiS_ii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z10blurKernelPiS_ii
.addrsig_sym _ZSt4cout
.addrsig_sym _ZTISt12out_of_range
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void diffuseProject_k(float2 *vx, float2 *vy, int dx, int dy, float dt, float visc, int lb) {
int gtidx = blockIdx.x * blockDim.x + threadIdx.x;
int gtidy = blockIdx.y * (lb * blockDim.y) + threadIdx.y * lb;
int p;
float2 xterm, yterm;
// gtidx is the domain location in x for this thread
if (gtidx < dx) {
for (p = 0; p < lb; p++) {
// fi is the domain location in y for this thread
int fi = gtidy + p;
if (fi < dy) {
int fj = fi * dx + gtidx;
xterm = vx[fj];
yterm = vy[fj];
// Compute the index of the wavenumber based on the
// data order produced by a standard NN FFT.
int iix = gtidx;
int iiy = (fi>dy/2)?(fi-(dy)):fi;
// Velocity diffusion
float kk = (float)(iix * iix + iiy * iiy); // k^2
float diff = 1.f / (1.f + visc * dt * kk);
xterm.x *= diff; xterm.y *= diff;
yterm.x *= diff; yterm.y *= diff;
// Velocity projection
if (kk > 0.f) {
float rkk = 1.f / kk;
// Real portion of velocity projection
float rkp = (iix * xterm.x + iiy * yterm.x);
// Imaginary portion of velocity projection
float ikp = (iix * xterm.y + iiy * yterm.y);
xterm.x -= rkk * rkp * iix;
xterm.y -= rkk * ikp * iix;
yterm.x -= rkk * rkp * iiy;
yterm.y -= rkk * ikp * iiy;
}
vx[fj] = xterm;
vy[fj] = yterm;
}
}
}
} | code for sm_80
Function : _Z16diffuseProject_kP6float2S0_iiffi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R18, SR_CTAID.X ; /* 0x0000000000127919 */
/* 0x000e220000002500 */
/*0020*/ MOV R17, c[0x0][0x180] ; /* 0x0000600000117a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0040*/ ISETP.GE.AND P0, PT, R17, 0x1, PT ; /* 0x000000011100780c */
/* 0x000fe20003f06270 */
/*0050*/ IMAD R18, R18, c[0x0][0x0], R3 ; /* 0x0000000012127a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.OR P0, PT, R18, c[0x0][0x170], !P0 ; /* 0x00005c0012007a0c */
/* 0x000fda0004706670 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ S2R R19, SR_TID.Y ; /* 0x0000000000137919 */
/* 0x000e220000002200 */
/*0090*/ ISETP.NE.AND P0, PT, R17.reuse, 0x1, PT ; /* 0x000000011100780c */
/* 0x040fe20003f05270 */
/*00a0*/ I2F R4, R18 ; /* 0x0000001200047306 */
/* 0x0002a20000201400 */
/*00b0*/ ULDC UR4, c[0x0][0x174] ; /* 0x00005d0000047ab9 */
/* 0x000fe20000000800 */
/*00c0*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*00d0*/ ULEA.HI UR4, UR4, UR4, URZ, 0x1 ; /* 0x0000000404047291 */
/* 0x000fe2000f8f083f */
/*00e0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00f0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0100*/ HFMA2.MMA R16, -RZ, RZ, 0, 0 ; /* 0x00000000ff107435 */
/* 0x000fe200000001ff */
/*0110*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011404 */
/*0120*/ LOP3.LUT R17, R17, 0x1, RZ, 0xc0, !PT ; /* 0x0000000111117812 */
/* 0x000fe200078ec0ff */
/*0130*/ IMAD R3, R18, R18, RZ ; /* 0x0000001212037224 */
/* 0x000fc400078e02ff */
/*0140*/ FMUL R2, R2, c[0x0][0x17c] ; /* 0x00005f0002027a20 */
/* 0x000fe40000400000 */
/*0150*/ IMAD R19, R0, c[0x0][0x4], R19 ; /* 0x0000010000137a24 */
/* 0x001fe200078e0213 */
/*0160*/ @!P0 BRA 0xa10 ; /* 0x000008a000008947 */
/* 0x000fea0003800000 */
/*0170*/ IADD3 R11, -R17, c[0x0][0x180], RZ ; /* 0x00006000110b7a10 */
/* 0x006fe40007ffe1ff */
/*0180*/ MOV R16, RZ ; /* 0x000000ff00107202 */
/* 0x000fca0000000f00 */
/*0190*/ IMAD R25, R19, c[0x0][0x180], R16 ; /* 0x0000600013197a24 */
/* 0x002fe200078e0210 */
/*01a0*/ IADD3 R11, R11, -0x2, RZ ; /* 0xfffffffe0b0b7810 */
/* 0x000fe20007ffe0ff */
/*01b0*/ BSSY B0, 0x5d0 ; /* 0x0000041000007945 */
/* 0x000fe60003800000 */
/*01c0*/ ISETP.GE.AND P0, PT, R25, c[0x0][0x174], PT ; /* 0x00005d0019007a0c */
/* 0x000fc40003f06270 */
/*01d0*/ ISETP.NE.AND P3, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f65270 */
/*01e0*/ @P0 BRA 0x5c0 ; /* 0x000003d000000947 */
/* 0x001fea0003800000 */
/*01f0*/ HFMA2.MMA R27, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff1b7435 */
/* 0x000fe200000001ff */
/*0200*/ IMAD R26, R25, c[0x0][0x170], R18 ; /* 0x00005c00191a7a24 */
/* 0x000fd200078e0212 */
/*0210*/ IMAD.WIDE R28, R26, R27, c[0x0][0x160] ; /* 0x000058001a1c7625 */
/* 0x000fc800078e021b */
/*0220*/ IMAD.WIDE R26, R26, R27, c[0x0][0x168] ; /* 0x00005a001a1a7625 */
/* 0x000fe200078e021b */
/*0230*/ LDG.E.64 R14, [R28.64] ; /* 0x000000061c0e7981 */
/* 0x000168000c1e1b00 */
/*0240*/ LDG.E.64 R12, [R26.64] ; /* 0x000000061a0c7981 */
/* 0x000162000c1e1b00 */
/*0250*/ ISETP.GT.AND P0, PT, R25, UR4, PT ; /* 0x0000000419007c0c */
/* 0x000fe2000bf04270 */
/*0260*/ BSSY B1, 0x390 ; /* 0x0000012000017945 */
/* 0x000fe60003800000 */
/*0270*/ SEL R20, RZ, c[0x0][0x174], !P0 ; /* 0x00005d00ff147a07 */
/* 0x000fc80004000000 */
/*0280*/ IADD3 R20, R25, -R20, RZ ; /* 0x8000001419147210 */
/* 0x000fca0007ffe0ff */
/*0290*/ IMAD R22, R20, R20, R3 ; /* 0x0000001414167224 */
/* 0x000fc800078e0203 */
/*02a0*/ I2F R23, R22 ; /* 0x0000001600177306 */
/* 0x000e640000201400 */
/*02b0*/ FFMA R6, R2, R23, 1 ; /* 0x3f80000002067423 */
/* 0x002fca0000000017 */
/*02c0*/ IADD3 R0, R6, 0x1800000, RZ ; /* 0x0180000006007810 */
/* 0x000fc80007ffe0ff */
/*02d0*/ LOP3.LUT R0, R0, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000000007812 */
/* 0x000fc800078ec0ff */
/*02e0*/ ISETP.GT.U32.AND P0, PT, R0, 0x1ffffff, PT ; /* 0x01ffffff0000780c */
/* 0x000fda0003f04070 */
/*02f0*/ @P0 BRA 0x340 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0300*/ IMAD.MOV.U32 R0, RZ, RZ, R6 ; /* 0x000000ffff007224 */
/* 0x001fe200078e0006 */
/*0310*/ MOV R6, 0x330 ; /* 0x0000033000067802 */
/* 0x000fe40000000f00 */
/*0320*/ CALL.REL.NOINC 0xe40 ; /* 0x00000b1000007944 */
/* 0x020fea0003c00000 */
/*0330*/ BRA 0x380 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0340*/ MUFU.RCP R7, R6 ; /* 0x0000000600077308 */
/* 0x001e240000001000 */
/*0350*/ FFMA R0, R6, R7, -1 ; /* 0xbf80000006007423 */
/* 0x001fc80000000007 */
/*0360*/ FADD.FTZ R0, -R0, -RZ ; /* 0x800000ff00007221 */
/* 0x000fc80000010100 */
/*0370*/ FFMA R7, R7, R0, R7 ; /* 0x0000000007077223 */
/* 0x000fe40000000007 */
/*0380*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0390*/ ISETP.NE.AND P0, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fe20003f05270 */
/*03a0*/ BSSY B1, 0x5a0 ; /* 0x000001f000017945 */
/* 0x000fe20003800000 */
/*03b0*/ FMUL R14, R14, R7.reuse ; /* 0x000000070e0e7220 */
/* 0x0a2fe40000400000 */
/*03c0*/ FMUL R15, R15, R7.reuse ; /* 0x000000070f0f7220 */
/* 0x080fe40000400000 */
/*03d0*/ FMUL R12, R12, R7.reuse ; /* 0x000000070c0c7220 */
/* 0x080fe40000400000 */
/*03e0*/ FMUL R13, R13, R7 ; /* 0x000000070d0d7220 */
/* 0x000fca0000400000 */
/*03f0*/ @!P0 BRA 0x590 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0400*/ IADD3 R0, R23, 0x1800000, RZ ; /* 0x0180000017007810 */
/* 0x001fe20007ffe0ff */
/*0410*/ BSSY B2, 0x4e0 ; /* 0x000000c000027945 */
/* 0x000fe60003800000 */
/*0420*/ LOP3.LUT R0, R0, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000000007812 */
/* 0x000fc800078ec0ff */
/*0430*/ ISETP.GT.U32.AND P0, PT, R0, 0x1ffffff, PT ; /* 0x01ffffff0000780c */
/* 0x000fda0003f04070 */
/*0440*/ @P0 BRA 0x490 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0450*/ MOV R0, R23 ; /* 0x0000001700007202 */
/* 0x000fe40000000f00 */
/*0460*/ MOV R6, 0x480 ; /* 0x0000048000067802 */
/* 0x000fe40000000f00 */
/*0470*/ CALL.REL.NOINC 0xe40 ; /* 0x000009c000007944 */
/* 0x000fea0003c00000 */
/*0480*/ BRA 0x4d0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0490*/ MUFU.RCP R0, R23 ; /* 0x0000001700007308 */
/* 0x000e240000001000 */
/*04a0*/ FFMA R5, R23, R0, -1 ; /* 0xbf80000017057423 */
/* 0x001fc80000000000 */
/*04b0*/ FADD.FTZ R5, -R5, -RZ ; /* 0x800000ff05057221 */
/* 0x000fc80000010100 */
/*04c0*/ FFMA R7, R0, R5, R0 ; /* 0x0000000500077223 */
/* 0x000fe40000000000 */
/*04d0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*04e0*/ I2F R20, R20 ; /* 0x0000001400147306 */
/* 0x000ea40000201400 */
/*04f0*/ FMUL R5, R12, R20.reuse ; /* 0x000000140c057220 */
/* 0x084fe40000400000 */
/*0500*/ FMUL R6, R13, R20 ; /* 0x000000140d067220 */
/* 0x000fe40000400000 */
/*0510*/ FFMA R0, R4.reuse, R14, R5 ; /* 0x0000000e04007223 */
/* 0x041fe40000000005 */
/*0520*/ FFMA R6, R4, R15, R6 ; /* 0x0000000f04067223 */
/* 0x000fe40000000006 */
/*0530*/ FMUL R5, R0, R7 ; /* 0x0000000700057220 */
/* 0x002fc40000400000 */
/*0540*/ FMUL R6, R6, R7 ; /* 0x0000000706067220 */
/* 0x000fe40000400000 */
/*0550*/ FFMA R14, R4, -R5.reuse, R14 ; /* 0x80000005040e7223 */
/* 0x080fe4000000000e */
/*0560*/ FFMA R12, R20.reuse, -R5, R12 ; /* 0x80000005140c7223 */
/* 0x040fe4000000000c */
/*0570*/ FFMA R13, R20, -R6.reuse, R13 ; /* 0x80000006140d7223 */
/* 0x080fe4000000000d */
/*0580*/ FFMA R15, R4, -R6, R15 ; /* 0x80000006040f7223 */
/* 0x000fe4000000000f */
/*0590*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*05a0*/ STG.E.64 [R28.64], R14 ; /* 0x0000000e1c007986 */
/* 0x0003e8000c101b06 */
/*05b0*/ STG.E.64 [R26.64], R12 ; /* 0x0000000c1a007986 */
/* 0x0003e4000c101b06 */
/*05c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05d0*/ IADD3 R5, R25, 0x1, RZ ; /* 0x0000000119057810 */
/* 0x000fe20007ffe0ff */
/*05e0*/ BSSY B0, 0x9f0 ; /* 0x0000040000007945 */
/* 0x000fe60003800000 */
/*05f0*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x174], PT ; /* 0x00005d0005007a0c */
/* 0x000fda0003f06270 */
/*0600*/ @P0 BRA 0x9e0 ; /* 0x000003d000000947 */
/* 0x000fea0003800000 */
/*0610*/ HFMA2.MMA R25, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff197435 */
/* 0x000fe200000001ff */
/*0620*/ IMAD R24, R5, c[0x0][0x170], R18 ; /* 0x00005c0005187a24 */
/* 0x000fd200078e0212 */
/*0630*/ IMAD.WIDE R26, R24, R25, c[0x0][0x160] ; /* 0x00005800181a7625 */
/* 0x002fc800078e0219 */
/*0640*/ IMAD.WIDE R24, R24, R25, c[0x0][0x168] ; /* 0x00005a0018187625 */
/* 0x000fe200078e0219 */
/*0650*/ LDG.E.64 R14, [R26.64] ; /* 0x000000061a0e7981 */
/* 0x000368000c1e1b00 */
/*0660*/ LDG.E.64 R12, [R24.64] ; /* 0x00000006180c7981 */
/* 0x000362000c1e1b00 */
/*0670*/ ISETP.GT.AND P0, PT, R5, UR4, PT ; /* 0x0000000405007c0c */
/* 0x000fe2000bf04270 */
/*0680*/ BSSY B1, 0x7b0 ; /* 0x0000012000017945 */
/* 0x000fe60003800000 */
/*0690*/ SEL R20, RZ, c[0x0][0x174], !P0 ; /* 0x00005d00ff147a07 */
/* 0x000fc80004000000 */
/*06a0*/ IADD3 R20, R5, -R20, RZ ; /* 0x8000001405147210 */
/* 0x000fca0007ffe0ff */
/*06b0*/ IMAD R22, R20, R20, R3 ; /* 0x0000001414167224 */
/* 0x000fc800078e0203 */
/*06c0*/ I2F R23, R22 ; /* 0x0000001600177306 */
/* 0x000ea40000201400 */
/*06d0*/ FFMA R6, R2, R23, 1 ; /* 0x3f80000002067423 */
/* 0x004fca0000000017 */
/*06e0*/ IADD3 R0, R6, 0x1800000, RZ ; /* 0x0180000006007810 */
/* 0x001fc80007ffe0ff */
/*06f0*/ LOP3.LUT R0, R0, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000000007812 */
/* 0x000fc800078ec0ff */
/*0700*/ ISETP.GT.U32.AND P0, PT, R0, 0x1ffffff, PT ; /* 0x01ffffff0000780c */
/* 0x000fda0003f04070 */
/*0710*/ @P0 BRA 0x760 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0720*/ MOV R0, R6 ; /* 0x0000000600007202 */
/* 0x002fe40000000f00 */
/*0730*/ MOV R6, 0x750 ; /* 0x0000075000067802 */
/* 0x000fe40000000f00 */
/*0740*/ CALL.REL.NOINC 0xe40 ; /* 0x000006f000007944 */
/* 0x020fea0003c00000 */
/*0750*/ BRA 0x7a0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0760*/ MUFU.RCP R7, R6 ; /* 0x0000000600077308 */
/* 0x002e240000001000 */
/*0770*/ FFMA R0, R6, R7, -1 ; /* 0xbf80000006007423 */
/* 0x001fc80000000007 */
/*0780*/ FADD.FTZ R0, -R0, -RZ ; /* 0x800000ff00007221 */
/* 0x000fc80000010100 */
/*0790*/ FFMA R7, R7, R0, R7 ; /* 0x0000000007077223 */
/* 0x000fe40000000007 */
/*07a0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*07b0*/ ISETP.NE.AND P0, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fe20003f05270 */
/*07c0*/ BSSY B1, 0x9c0 ; /* 0x000001f000017945 */
/* 0x000fe20003800000 */
/*07d0*/ FMUL R14, R14, R7.reuse ; /* 0x000000070e0e7220 */
/* 0x0a2fe40000400000 */
/*07e0*/ FMUL R15, R15, R7.reuse ; /* 0x000000070f0f7220 */
/* 0x080fe40000400000 */
/*07f0*/ FMUL R12, R12, R7.reuse ; /* 0x000000070c0c7220 */
/* 0x080fe40000400000 */
/*0800*/ FMUL R13, R13, R7 ; /* 0x000000070d0d7220 */
/* 0x000fca0000400000 */
/*0810*/ @!P0 BRA 0x9b0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0820*/ IADD3 R0, R23, 0x1800000, RZ ; /* 0x0180000017007810 */
/* 0x001fe20007ffe0ff */
/*0830*/ BSSY B2, 0x900 ; /* 0x000000c000027945 */
/* 0x000fe60003800000 */
/*0840*/ LOP3.LUT R0, R0, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000000007812 */
/* 0x000fc800078ec0ff */
/*0850*/ ISETP.GT.U32.AND P0, PT, R0, 0x1ffffff, PT ; /* 0x01ffffff0000780c */
/* 0x000fda0003f04070 */
/*0860*/ @P0 BRA 0x8b0 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0870*/ MOV R0, R23 ; /* 0x0000001700007202 */
/* 0x000fe40000000f00 */
/*0880*/ MOV R6, 0x8a0 ; /* 0x000008a000067802 */
/* 0x000fe40000000f00 */
/*0890*/ CALL.REL.NOINC 0xe40 ; /* 0x000005a000007944 */
/* 0x000fea0003c00000 */
/*08a0*/ BRA 0x8f0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*08b0*/ MUFU.RCP R0, R23 ; /* 0x0000001700007308 */
/* 0x000e240000001000 */
/*08c0*/ FFMA R5, R23, R0, -1 ; /* 0xbf80000017057423 */
/* 0x001fc80000000000 */
/*08d0*/ FADD.FTZ R5, -R5, -RZ ; /* 0x800000ff05057221 */
/* 0x000fc80000010100 */
/*08e0*/ FFMA R7, R0, R5, R0 ; /* 0x0000000500077223 */
/* 0x000fe40000000000 */
/*08f0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0900*/ I2F R20, R20 ; /* 0x0000001400147306 */
/* 0x000ea40000201400 */
/*0910*/ FMUL R5, R12, R20.reuse ; /* 0x000000140c057220 */
/* 0x084fe40000400000 */
/*0920*/ FMUL R6, R13, R20 ; /* 0x000000140d067220 */
/* 0x000fe40000400000 */
/*0930*/ FFMA R0, R4.reuse, R14, R5 ; /* 0x0000000e04007223 */
/* 0x041fe40000000005 */
/*0940*/ FFMA R6, R4, R15, R6 ; /* 0x0000000f04067223 */
/* 0x000fe40000000006 */
/*0950*/ FMUL R5, R0, R7 ; /* 0x0000000700057220 */
/* 0x002fc40000400000 */
/*0960*/ FMUL R6, R6, R7 ; /* 0x0000000706067220 */
/* 0x000fe40000400000 */
/*0970*/ FFMA R14, R4, -R5.reuse, R14 ; /* 0x80000005040e7223 */
/* 0x080fe4000000000e */
/*0980*/ FFMA R12, R20.reuse, -R5, R12 ; /* 0x80000005140c7223 */
/* 0x040fe4000000000c */
/*0990*/ FFMA R13, R20, -R6.reuse, R13 ; /* 0x80000006140d7223 */
/* 0x080fe4000000000d */
/*09a0*/ FFMA R15, R4, -R6, R15 ; /* 0x80000006040f7223 */
/* 0x000fe4000000000f */
/*09b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*09c0*/ STG.E.64 [R26.64], R14 ; /* 0x0000000e1a007986 */
/* 0x0003e8000c101b06 */
/*09d0*/ STG.E.64 [R24.64], R12 ; /* 0x0000000c18007986 */
/* 0x0003e4000c101b06 */
/*09e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*09f0*/ IADD3 R16, R16, 0x2, RZ ; /* 0x0000000210107810 */
/* 0x000fe20007ffe0ff */
/*0a00*/ @P3 BRA 0x190 ; /* 0xfffff78000003947 */
/* 0x000fea000383ffff */
/*0a10*/ ISETP.NE.AND P0, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x006fda0003f05270 */
/*0a20*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0a30*/ IMAD R5, R19, c[0x0][0x180], R16 ; /* 0x0000600013057a24 */
/* 0x000fca00078e0210 */
/*0a40*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x174], PT ; /* 0x00005d0005007a0c */
/* 0x000fda0003f06270 */
/*0a50*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0a60*/ IMAD.MOV.U32 R19, RZ, RZ, 0x8 ; /* 0x00000008ff137424 */
/* 0x000fe400078e00ff */
/*0a70*/ IMAD R18, R5, c[0x0][0x170], R18 ; /* 0x00005c0005127a24 */
/* 0x000fc800078e0212 */
/*0a80*/ IMAD.WIDE R22, R18, R19, c[0x0][0x160] ; /* 0x0000580012167625 */
/* 0x000fc800078e0213 */
/*0a90*/ IMAD.WIDE R18, R18, R19, c[0x0][0x168] ; /* 0x00005a0012127625 */
/* 0x000fe200078e0213 */
/*0aa0*/ LDG.E.64 R12, [R22.64] ; /* 0x00000006160c7981 */
/* 0x000368000c1e1b00 */
/*0ab0*/ LDG.E.64 R14, [R18.64] ; /* 0x00000006120e7981 */
/* 0x000362000c1e1b00 */
/*0ac0*/ ISETP.GT.AND P0, PT, R5, UR4, PT ; /* 0x0000000405007c0c */
/* 0x000fe2000bf04270 */
/*0ad0*/ BSSY B0, 0xc00 ; /* 0x0000012000007945 */
/* 0x000fe60003800000 */
/*0ae0*/ SEL R16, RZ, c[0x0][0x174], !P0 ; /* 0x00005d00ff107a07 */
/* 0x000fc80004000000 */
/*0af0*/ IADD3 R16, R5, -R16, RZ ; /* 0x8000001005107210 */
/* 0x000fca0007ffe0ff */
/*0b00*/ IMAD R11, R16, R16, R3 ; /* 0x00000010100b7224 */
/* 0x000fc800078e0203 */
/*0b10*/ I2F R3, R11 ; /* 0x0000000b00037306 */
/* 0x000ea40000201400 */
/*0b20*/ FFMA R2, R2, R3, 1 ; /* 0x3f80000002027423 */
/* 0x004fca0000000003 */
/*0b30*/ IADD3 R0, R2, 0x1800000, RZ ; /* 0x0180000002007810 */
/* 0x001fc80007ffe0ff */
/*0b40*/ LOP3.LUT R0, R0, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000000007812 */
/* 0x000fc800078ec0ff */
/*0b50*/ ISETP.GT.U32.AND P0, PT, R0, 0x1ffffff, PT ; /* 0x01ffffff0000780c */
/* 0x000fda0003f04070 */
/*0b60*/ @P0 BRA 0xbb0 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0b70*/ MOV R0, R2 ; /* 0x0000000200007202 */
/* 0x002fe40000000f00 */
/*0b80*/ MOV R6, 0xba0 ; /* 0x00000ba000067802 */
/* 0x000fe40000000f00 */
/*0b90*/ CALL.REL.NOINC 0xe40 ; /* 0x000002a000007944 */
/* 0x020fea0003c00000 */
/*0ba0*/ BRA 0xbf0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0bb0*/ MUFU.RCP R7, R2 ; /* 0x0000000200077308 */
/* 0x002e240000001000 */
/*0bc0*/ FFMA R0, R2, R7, -1 ; /* 0xbf80000002007423 */
/* 0x001fc80000000007 */
/*0bd0*/ FADD.FTZ R0, -R0, -RZ ; /* 0x800000ff00007221 */
/* 0x000fc80000010100 */
/*0be0*/ FFMA R7, R7, R0, R7 ; /* 0x0000000007077223 */
/* 0x000fe40000000007 */
/*0bf0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0c00*/ ISETP.NE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f05270 */
/*0c10*/ BSSY B0, 0xe10 ; /* 0x000001f000007945 */
/* 0x000fe20003800000 */
/*0c20*/ FMUL R12, R12, R7.reuse ; /* 0x000000070c0c7220 */
/* 0x0a2fe40000400000 */
/*0c30*/ FMUL R13, R13, R7.reuse ; /* 0x000000070d0d7220 */
/* 0x080fe40000400000 */
/*0c40*/ FMUL R14, R14, R7.reuse ; /* 0x000000070e0e7220 */
/* 0x080fe40000400000 */
/*0c50*/ FMUL R15, R15, R7 ; /* 0x000000070f0f7220 */
/* 0x000fca0000400000 */
/*0c60*/ @!P0 BRA 0xe00 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0c70*/ IADD3 R0, R3, 0x1800000, RZ ; /* 0x0180000003007810 */
/* 0x001fe20007ffe0ff */
/*0c80*/ BSSY B1, 0xd50 ; /* 0x000000c000017945 */
/* 0x000fe60003800000 */
/*0c90*/ LOP3.LUT R0, R0, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000000007812 */
/* 0x000fc800078ec0ff */
/*0ca0*/ ISETP.GT.U32.AND P0, PT, R0, 0x1ffffff, PT ; /* 0x01ffffff0000780c */
/* 0x000fda0003f04070 */
/*0cb0*/ @P0 BRA 0xd00 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0cc0*/ MOV R0, R3 ; /* 0x0000000300007202 */
/* 0x000fe40000000f00 */
/*0cd0*/ MOV R6, 0xcf0 ; /* 0x00000cf000067802 */
/* 0x000fe40000000f00 */
/*0ce0*/ CALL.REL.NOINC 0xe40 ; /* 0x0000015000007944 */
/* 0x000fea0003c00000 */
/*0cf0*/ BRA 0xd40 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0d00*/ MUFU.RCP R0, R3 ; /* 0x0000000300007308 */
/* 0x000e240000001000 */
/*0d10*/ FFMA R2, R3, R0, -1 ; /* 0xbf80000003027423 */
/* 0x001fc80000000000 */
/*0d20*/ FADD.FTZ R7, -R2, -RZ ; /* 0x800000ff02077221 */
/* 0x000fc80000010100 */
/*0d30*/ FFMA R7, R0, R7, R0 ; /* 0x0000000700077223 */
/* 0x000fe40000000000 */
/*0d40*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0d50*/ I2F R16, R16 ; /* 0x0000001000107306 */
/* 0x000ea40000201400 */
/*0d60*/ FMUL R3, R14, R16.reuse ; /* 0x000000100e037220 */
/* 0x084fe40000400000 */
/*0d70*/ FMUL R2, R15, R16 ; /* 0x000000100f027220 */
/* 0x000fe40000400000 */
/*0d80*/ FFMA R0, R4.reuse, R12, R3 ; /* 0x0000000c04007223 */
/* 0x041fe40000000003 */
/*0d90*/ FFMA R2, R4, R13, R2 ; /* 0x0000000d04027223 */
/* 0x000fe40000000002 */
/*0da0*/ FMUL R3, R0, R7 ; /* 0x0000000700037220 */
/* 0x002fc40000400000 */
/*0db0*/ FMUL R2, R2, R7 ; /* 0x0000000702027220 */
/* 0x000fe40000400000 */
/*0dc0*/ FFMA R12, R4.reuse, -R3.reuse, R12 ; /* 0x80000003040c7223 */
/* 0x0c0fe4000000000c */
/*0dd0*/ FFMA R13, R4, -R2.reuse, R13 ; /* 0x80000002040d7223 */
/* 0x080fe4000000000d */
/*0de0*/ FFMA R14, R16.reuse, -R3, R14 ; /* 0x80000003100e7223 */
/* 0x040fe4000000000e */
/*0df0*/ FFMA R15, R16, -R2, R15 ; /* 0x80000002100f7223 */
/* 0x000fe4000000000f */
/*0e00*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0e10*/ STG.E.64 [R22.64], R12 ; /* 0x0000000c16007986 */
/* 0x000fe8000c101b06 */
/*0e20*/ STG.E.64 [R18.64], R14 ; /* 0x0000000e12007986 */
/* 0x000fe2000c101b06 */
/*0e30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e40*/ SHF.L.U32 R5, R0, 0x1, RZ ; /* 0x0000000100057819 */
/* 0x000fe200000006ff */
/*0e50*/ BSSY B3, 0x1160 ; /* 0x0000030000037945 */
/* 0x000fe60003800000 */
/*0e60*/ SHF.R.U32.HI R5, RZ, 0x18, R5 ; /* 0x00000018ff057819 */
/* 0x000fc80000011605 */
/*0e70*/ ISETP.NE.U32.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05070 */
/*0e80*/ @P0 BRA 0xf30 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0e90*/ SHF.L.U32 R5, R0, 0x1, RZ ; /* 0x0000000100057819 */
/* 0x000fc800000006ff */
/*0ea0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0eb0*/ @P0 FFMA R8, R0, 1.84467440737095516160e+19, RZ ; /* 0x5f80000000080823 */
/* 0x000fe200000000ff */
/*0ec0*/ @!P0 MUFU.RCP R7, R0 ; /* 0x0000000000078308 */
/* 0x000ff00000001000 */
/*0ed0*/ @P0 MUFU.RCP R5, R8 ; /* 0x0000000800050308 */
/* 0x000e240000001000 */
/*0ee0*/ @P0 FFMA R10, R8, R5, -1 ; /* 0xbf800000080a0423 */
/* 0x001fc80000000005 */
/*0ef0*/ @P0 FADD.FTZ R10, -R10, -RZ ; /* 0x800000ff0a0a0221 */
/* 0x000fc80000010100 */
/*0f00*/ @P0 FFMA R10, R5, R10, R5 ; /* 0x0000000a050a0223 */
/* 0x000fc80000000005 */
/*0f10*/ @P0 FFMA R7, R10, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000a070823 */
/* 0x000fe200000000ff */
/*0f20*/ BRA 0x1150 ; /* 0x0000022000007947 */
/* 0x000fea0003800000 */
/*0f30*/ IADD3 R7, R5, -0xfd, RZ ; /* 0xffffff0305077810 */
/* 0x000fc80007ffe0ff */
/*0f40*/ ISETP.GT.U32.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fda0003f04070 */
/*0f50*/ @P0 BRA 0x1140 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*0f60*/ LOP3.LUT R21, R0, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff00157812 */
/* 0x000fe400078ec0ff */
/*0f70*/ IADD3 R5, R5, -0xfc, RZ ; /* 0xffffff0405057810 */
/* 0x000fe40007ffe0ff */
/*0f80*/ LOP3.LUT R21, R21, 0x3f800000, RZ, 0xfc, !PT ; /* 0x3f80000015157812 */
/* 0x000fc800078efcff */
/*0f90*/ MUFU.RCP R10, R21 ; /* 0x00000015000a7308 */
/* 0x000e240000001000 */
/*0fa0*/ FFMA R9, R21, R10, -1 ; /* 0xbf80000015097423 */
/* 0x001fc8000000000a */
/*0fb0*/ FADD.FTZ R9, -R9, -RZ ; /* 0x800000ff09097221 */
/* 0x000fc80000010100 */
/*0fc0*/ FFMA.RM R8, R10.reuse, R9.reuse, R10.reuse ; /* 0x000000090a087223 */
/* 0x1c0fe4000000400a */
/*0fd0*/ FFMA.RP R9, R10, R9, R10 ; /* 0x000000090a097223 */
/* 0x000fe4000000800a */
/*0fe0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x3 ; /* 0x00000003ff0a7424 */
/* 0x000fc600078e00ff */
/*0ff0*/ FSETP.NEU.FTZ.AND P0, PT, R8.reuse, R9, PT ; /* 0x000000090800720b */
/* 0x040fe40003f1d000 */
/*1000*/ LOP3.LUT R8, R8, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff08087812 */
/* 0x000fe400078ec0ff */
/*1010*/ SHF.L.U32 R9, R10, R7, RZ ; /* 0x000000070a097219 */
/* 0x000fe400000006ff */
/*1020*/ LOP3.LUT R8, R8, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000008087812 */
/* 0x000fc800078efcff */
/*1030*/ LOP3.LUT R10, R9, R8, RZ, 0xc0, !PT ; /* 0x00000008090a7212 */
/* 0x000fe400078ec0ff */
/*1040*/ SEL R9, RZ, 0xffffffff, !P0 ; /* 0xffffffffff097807 */
/* 0x000fe40004000000 */
/*1050*/ SHF.R.U32.HI R10, RZ, R7.reuse, R10 ; /* 0x00000007ff0a7219 */
/* 0x080fe4000001160a */
/*1060*/ IADD3 R9, -R9, RZ, RZ ; /* 0x000000ff09097210 */
/* 0x000fe40007ffe1ff */
/*1070*/ LOP3.LUT P0, RZ, R10, 0x1, RZ, 0xc0, !PT ; /* 0x000000010aff7812 */
/* 0x000fe4000780c0ff */
/*1080*/ LOP3.LUT P1, RZ, R9, R7, R8, 0xf8, !PT ; /* 0x0000000709ff7212 */
/* 0x000fc4000782f808 */
/*1090*/ LOP3.LUT P2, RZ, R10, 0x2, RZ, 0xc0, !PT ; /* 0x000000020aff7812 */
/* 0x000fe4000784c0ff */
/*10a0*/ SHF.R.U32.HI R5, RZ, R5, R8 ; /* 0x00000005ff057219 */
/* 0x000fe40000011608 */
/*10b0*/ PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703c20 */
/*10c0*/ LOP3.LUT P1, RZ, R0, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff00ff7812 */
/* 0x000fe4000782c0ff */
/*10d0*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fc80004000000 */
/*10e0*/ IADD3 R7, -R7, RZ, RZ ; /* 0x000000ff07077210 */
/* 0x000fc80007ffe1ff */
/*10f0*/ ISETP.GE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f06270 */
/*1100*/ @!P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105058810 */
/* 0x000fc80007ffe0ff */
/*1110*/ @!P1 SHF.L.U32 R5, R5, 0x1, RZ ; /* 0x0000000105059819 */
/* 0x000fc800000006ff */
/*1120*/ LOP3.LUT R7, R5, 0x80000000, R0, 0xf8, !PT ; /* 0x8000000005077812 */
/* 0x000fe200078ef800 */
/*1130*/ BRA 0x1150 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*1140*/ MUFU.RCP R7, R0 ; /* 0x0000000000077308 */
/* 0x0000640000001000 */
/*1150*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*1160*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe200000001ff */
/*1170*/ MOV R8, R6 ; /* 0x0000000600087202 */
/* 0x000fca0000000f00 */
/*1180*/ RET.REL.NODEC R8 0x0 ; /* 0xffffee7008007950 */
/* 0x000fea0003c3ffff */
/*1190*/ BRA 0x1190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*11a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void diffuseProject_k(float2 *vx, float2 *vy, int dx, int dy, float dt, float visc, int lb) {
int gtidx = blockIdx.x * blockDim.x + threadIdx.x;
int gtidy = blockIdx.y * (lb * blockDim.y) + threadIdx.y * lb;
int p;
float2 xterm, yterm;
// gtidx is the domain location in x for this thread
if (gtidx < dx) {
for (p = 0; p < lb; p++) {
// fi is the domain location in y for this thread
int fi = gtidy + p;
if (fi < dy) {
int fj = fi * dx + gtidx;
xterm = vx[fj];
yterm = vy[fj];
// Compute the index of the wavenumber based on the
// data order produced by a standard NN FFT.
int iix = gtidx;
int iiy = (fi>dy/2)?(fi-(dy)):fi;
// Velocity diffusion
float kk = (float)(iix * iix + iiy * iiy); // k^2
float diff = 1.f / (1.f + visc * dt * kk);
xterm.x *= diff; xterm.y *= diff;
yterm.x *= diff; yterm.y *= diff;
// Velocity projection
if (kk > 0.f) {
float rkk = 1.f / kk;
// Real portion of velocity projection
float rkp = (iix * xterm.x + iiy * yterm.x);
// Imaginary portion of velocity projection
float ikp = (iix * xterm.y + iiy * yterm.y);
xterm.x -= rkk * rkp * iix;
xterm.y -= rkk * ikp * iix;
yterm.x -= rkk * rkp * iiy;
yterm.y -= rkk * ikp * iiy;
}
vx[fj] = xterm;
vy[fj] = yterm;
}
}
}
} | .file "tmpxft_000abd9f_00000000-6_diffuseProject_k.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z16diffuseProject_kP6float2S0_iiffiP6float2S0_iiffi
.type _Z50__device_stub__Z16diffuseProject_kP6float2S0_iiffiP6float2S0_iiffi, @function
_Z50__device_stub__Z16diffuseProject_kP6float2S0_iiffiP6float2S0_iiffi:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16diffuseProject_kP6float2S0_iiffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z16diffuseProject_kP6float2S0_iiffiP6float2S0_iiffi, .-_Z50__device_stub__Z16diffuseProject_kP6float2S0_iiffiP6float2S0_iiffi
.globl _Z16diffuseProject_kP6float2S0_iiffi
.type _Z16diffuseProject_kP6float2S0_iiffi, @function
_Z16diffuseProject_kP6float2S0_iiffi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z16diffuseProject_kP6float2S0_iiffiP6float2S0_iiffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16diffuseProject_kP6float2S0_iiffi, .-_Z16diffuseProject_kP6float2S0_iiffi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z16diffuseProject_kP6float2S0_iiffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16diffuseProject_kP6float2S0_iiffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void diffuseProject_k(float2 *vx, float2 *vy, int dx, int dy, float dt, float visc, int lb) {
int gtidx = blockIdx.x * blockDim.x + threadIdx.x;
int gtidy = blockIdx.y * (lb * blockDim.y) + threadIdx.y * lb;
int p;
float2 xterm, yterm;
// gtidx is the domain location in x for this thread
if (gtidx < dx) {
for (p = 0; p < lb; p++) {
// fi is the domain location in y for this thread
int fi = gtidy + p;
if (fi < dy) {
int fj = fi * dx + gtidx;
xterm = vx[fj];
yterm = vy[fj];
// Compute the index of the wavenumber based on the
// data order produced by a standard NN FFT.
int iix = gtidx;
int iiy = (fi>dy/2)?(fi-(dy)):fi;
// Velocity diffusion
float kk = (float)(iix * iix + iiy * iiy); // k^2
float diff = 1.f / (1.f + visc * dt * kk);
xterm.x *= diff; xterm.y *= diff;
yterm.x *= diff; yterm.y *= diff;
// Velocity projection
if (kk > 0.f) {
float rkk = 1.f / kk;
// Real portion of velocity projection
float rkp = (iix * xterm.x + iiy * yterm.x);
// Imaginary portion of velocity projection
float ikp = (iix * xterm.y + iiy * yterm.y);
xterm.x -= rkk * rkp * iix;
xterm.y -= rkk * ikp * iix;
yterm.x -= rkk * rkp * iiy;
yterm.y -= rkk * ikp * iiy;
}
vx[fj] = xterm;
vy[fj] = yterm;
}
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void diffuseProject_k(float2 *vx, float2 *vy, int dx, int dy, float dt, float visc, int lb) {
int gtidx = blockIdx.x * blockDim.x + threadIdx.x;
int gtidy = blockIdx.y * (lb * blockDim.y) + threadIdx.y * lb;
int p;
float2 xterm, yterm;
// gtidx is the domain location in x for this thread
if (gtidx < dx) {
for (p = 0; p < lb; p++) {
// fi is the domain location in y for this thread
int fi = gtidy + p;
if (fi < dy) {
int fj = fi * dx + gtidx;
xterm = vx[fj];
yterm = vy[fj];
// Compute the index of the wavenumber based on the
// data order produced by a standard NN FFT.
int iix = gtidx;
int iiy = (fi>dy/2)?(fi-(dy)):fi;
// Velocity diffusion
float kk = (float)(iix * iix + iiy * iiy); // k^2
float diff = 1.f / (1.f + visc * dt * kk);
xterm.x *= diff; xterm.y *= diff;
yterm.x *= diff; yterm.y *= diff;
// Velocity projection
if (kk > 0.f) {
float rkk = 1.f / kk;
// Real portion of velocity projection
float rkp = (iix * xterm.x + iiy * yterm.x);
// Imaginary portion of velocity projection
float ikp = (iix * xterm.y + iiy * yterm.y);
xterm.x -= rkk * rkp * iix;
xterm.y -= rkk * ikp * iix;
yterm.x -= rkk * rkp * iiy;
yterm.y -= rkk * ikp * iiy;
}
vx[fj] = xterm;
vy[fj] = yterm;
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void diffuseProject_k(float2 *vx, float2 *vy, int dx, int dy, float dt, float visc, int lb) {
int gtidx = blockIdx.x * blockDim.x + threadIdx.x;
int gtidy = blockIdx.y * (lb * blockDim.y) + threadIdx.y * lb;
int p;
float2 xterm, yterm;
// gtidx is the domain location in x for this thread
if (gtidx < dx) {
for (p = 0; p < lb; p++) {
// fi is the domain location in y for this thread
int fi = gtidy + p;
if (fi < dy) {
int fj = fi * dx + gtidx;
xterm = vx[fj];
yterm = vy[fj];
// Compute the index of the wavenumber based on the
// data order produced by a standard NN FFT.
int iix = gtidx;
int iiy = (fi>dy/2)?(fi-(dy)):fi;
// Velocity diffusion
float kk = (float)(iix * iix + iiy * iiy); // k^2
float diff = 1.f / (1.f + visc * dt * kk);
xterm.x *= diff; xterm.y *= diff;
yterm.x *= diff; yterm.y *= diff;
// Velocity projection
if (kk > 0.f) {
float rkk = 1.f / kk;
// Real portion of velocity projection
float rkp = (iix * xterm.x + iiy * yterm.x);
// Imaginary portion of velocity projection
float ikp = (iix * xterm.y + iiy * yterm.y);
xterm.x -= rkk * rkp * iix;
xterm.y -= rkk * ikp * iix;
yterm.x -= rkk * rkp * iiy;
yterm.y -= rkk * ikp * iiy;
}
vx[fj] = xterm;
vy[fj] = yterm;
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi
.globl _Z16diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi
.p2align 8
.type _Z16diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi,@function
_Z16diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s6, s[0:1], 0x10
s_load_b32 s7, s[0:1], 0x20
s_add_u32 s2, s0, 40
v_and_b32_e32 v1, 0x3ff, v0
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_mul_i32 s14, s14, s4
s_cmp_gt_i32 s7, 0
v_add_nc_u32_e32 v2, s14, v1
s_cselect_b32 s4, -1, 0
v_cmp_gt_i32_e32 vcc_lo, s6, v2
s_and_b32 s4, vcc_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_7
s_load_b32 s2, s[2:3], 0xc
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x14
s_load_b32 s8, s[0:1], 0x1c
v_bfe_u32 v0, v0, 10, 10
s_mul_i32 s9, s7, s6
v_cvt_f32_i32_e32 v12, v2
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_load_b128 s[0:3], s[0:1], 0x0
v_mul_lo_u32 v0, v2, v2
v_mul_f32_e64 v11, s5, s8
v_mul_lo_u32 v4, s9, v3
v_mul_lo_u32 v10, v3, s7
s_lshr_b32 s9, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s4, s9
s_ashr_i32 s5, s5, 1
s_delay_alu instid0(VALU_DEP_2)
v_add3_u32 v1, v1, v4, s14
s_branch .LBB0_4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s9
global_store_b64 v[2:3], v[8:9], off
global_store_b64 v[4:5], v[6:7], off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s8
v_add_nc_u32_e32 v10, 1, v10
v_add_nc_u32_e32 v1, s6, v1
s_add_i32 s7, s7, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s7, 0
s_cbranch_scc0 .LBB0_7
.LBB0_4:
s_mov_b32 s8, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_gt_i32_e64 s4, v10
s_cbranch_execz .LBB0_3
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s9, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, s5, v10
global_load_b64 v[6:7], v[2:3], off
global_load_b64 v[15:16], v[4:5], off
v_cndmask_b32_e64 v8, 0, s4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v14, v10, v8
v_mad_u64_u32 v[17:18], null, v14, v14, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v13, v17
v_fma_f32 v8, v11, v13, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v9, null, v8, v8, 1.0
v_div_scale_f32 v20, vcc_lo, 1.0, v8, 1.0
v_rcp_f32_e32 v18, v9
s_waitcnt_depctr 0xfff
v_fma_f32 v19, -v9, v18, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v18, v19, v18
v_mul_f32_e32 v19, v20, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v21, -v9, v19, v20
v_fmac_f32_e32 v19, v21, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v9, -v9, v19, v20
v_div_fmas_f32 v9, v9, v18, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fixup_f32 v18, v9, v8, 1.0
s_waitcnt vmcnt(1)
v_mul_f32_e32 v8, v18, v6
s_waitcnt vmcnt(0)
v_mul_f32_e32 v6, v18, v15
v_mul_f32_e32 v9, v18, v7
v_mul_f32_e32 v7, v18, v16
v_cmpx_ne_u32_e32 0, v17
s_cbranch_execz .LBB0_2
v_div_scale_f32 v15, null, v13, v13, 1.0
v_div_scale_f32 v18, vcc_lo, 1.0, v13, 1.0
v_cvt_f32_i32_e32 v14, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v16, v15
s_waitcnt_depctr 0xfff
v_fma_f32 v17, -v15, v16, 1.0
v_fmac_f32_e32 v16, v17, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v17, v18, v16
v_fma_f32 v19, -v15, v17, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v17, v19, v16
v_fma_f32 v15, -v15, v17, v18
v_mul_f32_e32 v18, v6, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_fmas_f32 v15, v15, v16, v17
v_mul_f32_e32 v16, v7, v14
v_fmac_f32_e32 v18, v8, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fixup_f32 v13, v15, v13, 1.0
v_fmac_f32_e32 v16, v9, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v15, v13, v18
v_mul_f32_e32 v13, v13, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v8, -v15, v12, v8
v_fma_f32 v9, -v13, v12, v9
v_fma_f32 v6, -v15, v14, v6
v_fma_f32 v7, -v13, v14, v7
s_branch .LBB0_2
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 22
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi, .Lfunc_end0-_Z16diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 22
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void diffuseProject_k(float2 *vx, float2 *vy, int dx, int dy, float dt, float visc, int lb) {
int gtidx = blockIdx.x * blockDim.x + threadIdx.x;
int gtidy = blockIdx.y * (lb * blockDim.y) + threadIdx.y * lb;
int p;
float2 xterm, yterm;
// gtidx is the domain location in x for this thread
if (gtidx < dx) {
for (p = 0; p < lb; p++) {
// fi is the domain location in y for this thread
int fi = gtidy + p;
if (fi < dy) {
int fj = fi * dx + gtidx;
xterm = vx[fj];
yterm = vy[fj];
// Compute the index of the wavenumber based on the
// data order produced by a standard NN FFT.
int iix = gtidx;
int iiy = (fi>dy/2)?(fi-(dy)):fi;
// Velocity diffusion
float kk = (float)(iix * iix + iiy * iiy); // k^2
float diff = 1.f / (1.f + visc * dt * kk);
xterm.x *= diff; xterm.y *= diff;
yterm.x *= diff; yterm.y *= diff;
// Velocity projection
if (kk > 0.f) {
float rkk = 1.f / kk;
// Real portion of velocity projection
float rkp = (iix * xterm.x + iiy * yterm.x);
// Imaginary portion of velocity projection
float ikp = (iix * xterm.y + iiy * yterm.y);
xterm.x -= rkk * rkp * iix;
xterm.y -= rkk * ikp * iix;
yterm.x -= rkk * rkp * iiy;
yterm.y -= rkk * ikp * iiy;
}
vx[fj] = xterm;
vy[fj] = yterm;
}
}
}
} | .text
.file "diffuseProject_k.hip"
.globl _Z31__device_stub__diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi # -- Begin function _Z31__device_stub__diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi
.p2align 4, 0x90
.type _Z31__device_stub__diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi,@function
_Z31__device_stub__diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi: # @_Z31__device_stub__diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z31__device_stub__diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi, .Lfunc_end0-_Z31__device_stub__diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi,@object # @_Z16diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi
.section .rodata,"a",@progbits
.globl _Z16diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi
.p2align 3, 0x0
_Z16diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi:
.quad _Z31__device_stub__diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi
.size _Z16diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi"
.size .L__unnamed_1, 54
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000abd9f_00000000-6_diffuseProject_k.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z16diffuseProject_kP6float2S0_iiffiP6float2S0_iiffi
.type _Z50__device_stub__Z16diffuseProject_kP6float2S0_iiffiP6float2S0_iiffi, @function
_Z50__device_stub__Z16diffuseProject_kP6float2S0_iiffiP6float2S0_iiffi:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16diffuseProject_kP6float2S0_iiffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z16diffuseProject_kP6float2S0_iiffiP6float2S0_iiffi, .-_Z50__device_stub__Z16diffuseProject_kP6float2S0_iiffiP6float2S0_iiffi
.globl _Z16diffuseProject_kP6float2S0_iiffi
.type _Z16diffuseProject_kP6float2S0_iiffi, @function
_Z16diffuseProject_kP6float2S0_iiffi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z16diffuseProject_kP6float2S0_iiffiP6float2S0_iiffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16diffuseProject_kP6float2S0_iiffi, .-_Z16diffuseProject_kP6float2S0_iiffi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z16diffuseProject_kP6float2S0_iiffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16diffuseProject_kP6float2S0_iiffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "diffuseProject_k.hip"
.globl _Z31__device_stub__diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi # -- Begin function _Z31__device_stub__diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi
.p2align 4, 0x90
.type _Z31__device_stub__diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi,@function
_Z31__device_stub__diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi: # @_Z31__device_stub__diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z31__device_stub__diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi, .Lfunc_end0-_Z31__device_stub__diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi,@object # @_Z16diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi
.section .rodata,"a",@progbits
.globl _Z16diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi
.p2align 3, 0x0
_Z16diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi:
.quad _Z31__device_stub__diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi
.size _Z16diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi"
.size .L__unnamed_1, 54
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16diffuseProject_kP15HIP_vector_typeIfLj2EES1_iiffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
using namespace std;
#include <thrust/device_vector.h>
#include <thrust/sequence.h>
int main(int argc, char* argv[])
{
int nGPU;
if(argc < 2) {
cerr << "Use: number of integers" << endl;
return(1);
}
cudaGetDeviceCount(&nGPU);
int n = atoi(argv[1]);
int size = nGPU * n * sizeof(int);
cout << "nGPU " << nGPU << " " << (n*nGPU*sizeof(int)/1e6) << "MB" << endl;
int *h_A;
cudaHostAlloc(&h_A, size, cudaHostAllocMapped);
for(int i=0; i < nGPU; i++) {
cudaSetDevice(i);
thrust::sequence(thrust::device_pointer_cast(h_A + i*n),
thrust::device_pointer_cast(h_A + (i+1)*n),
i*n);
}
cudaDeviceSynchronize(); // synchronize the writes
for(int i=0; i < nGPU*n; i++)
if(h_A[i] != i) { cout << "Error " << h_A[i] << endl; exit(1); }
cout << "Success!\n" << endl;
cudaFreeHost(h_A);
return(0);
} | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tElN6thrust20THRUST_200700_800_NS8cuda_cub10__tabulate7functorINS7_10device_ptrIiEENS7_6system6detail7generic6detail22compute_sequence_valueIivEElEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R4, R4, 0x200, RZ ; /* 0x0000020004047825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R6, P1, -R4.reuse, c[0x0][0x160], RZ ; /* 0x0000580004067a10 */
/* 0x040fe40007f3e1ff */
/*0060*/ IADD3 R7, P2, R4, R9, RZ ; /* 0x0000000904077210 */
/* 0x002fe40007f5e0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R6, 0x1ff, PT ; /* 0x000001ff0600780c */
/* 0x000fe40003f04070 */
/*0080*/ IADD3.X R3, ~R5, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590005037a10 */
/* 0x000fe20000ffe5ff */
/*0090*/ IMAD.X R0, RZ, RZ, R5, P2 ; /* 0x000000ffff007224 */
/* 0x000fe200010e0605 */
/*00a0*/ LEA R2, P1, R7, c[0x0][0x168], 0x2 ; /* 0x00005a0007027a11 */
/* 0x000fe400078210ff */
/*00b0*/ ISETP.GT.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fc40003f04300 */
/*00c0*/ LEA.HI.X R3, R7, c[0x0][0x16c], R0, 0x2, P1 ; /* 0x00005b0007037a11 */
/* 0x000fd600008f1400 */
/*00d0*/ @P0 BRA 0x1d0 ; /* 0x000000f000000947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R8, RZ, 0x1f, R6 ; /* 0x0000001fff087819 */
/* 0x000fe40000011406 */
/*0100*/ IADD3 R9, R9, 0x100, RZ ; /* 0x0000010009097810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GT.AND.EX P0, PT, R8, RZ, PT, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0003f04300 */
/*0120*/ @P0 IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff000624 */
/* 0x000fc800078e00ff */
/*0130*/ @P0 IMAD R7, R7, R0, c[0x0][0x170] ; /* 0x00005c0007070624 */
/* 0x000fca00078e0200 */
/*0140*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e2000c101904 */
/*0150*/ ISETP.GT.U32.AND P0, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x000fc80003f04070 */
/*0160*/ ISETP.GT.AND.EX P0, PT, R8, RZ, PT, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0003f04300 */
/*0170*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0180*/ IMAD.IADD R5, R4, 0x1, R9 ; /* 0x0000000104057824 */
/* 0x001fe400078e0209 */
/*0190*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff007624 */
/* 0x000fc800078e00ff */
/*01a0*/ IMAD R5, R5, R0, c[0x0][0x170] ; /* 0x00005c0005057624 */
/* 0x000fca00078e0200 */
/*01b0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ IADD3 R5, R4, 0x100, R9 ; /* 0x0000010004057810 */
/* 0x000fe20007ffe009 */
/*01e0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff007624 */
/* 0x000fc800078e00ff */
/*01f0*/ IMAD R7, R7, R0.reuse, c[0x0][0x170] ; /* 0x00005c0007077624 */
/* 0x080fe400078e0200 */
/*0200*/ IMAD R5, R5, R0, c[0x0][0x170] ; /* 0x00005c0005057624 */
/* 0x000fc600078e0200 */
/*0210*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*0220*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*0230*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0240*/ BRA 0x240; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
using namespace std;
#include <thrust/device_vector.h>
#include <thrust/sequence.h>
int main(int argc, char* argv[])
{
int nGPU;
if(argc < 2) {
cerr << "Use: number of integers" << endl;
return(1);
}
cudaGetDeviceCount(&nGPU);
int n = atoi(argv[1]);
int size = nGPU * n * sizeof(int);
cout << "nGPU " << nGPU << " " << (n*nGPU*sizeof(int)/1e6) << "MB" << endl;
int *h_A;
cudaHostAlloc(&h_A, size, cudaHostAllocMapped);
for(int i=0; i < nGPU; i++) {
cudaSetDevice(i);
thrust::sequence(thrust::device_pointer_cast(h_A + i*n),
thrust::device_pointer_cast(h_A + (i+1)*n),
i*n);
}
cudaDeviceSynchronize(); // synchronize the writes
for(int i=0; i < nGPU*n; i++)
if(h_A[i] != i) { cout << "Error " << h_A[i] << endl; exit(1); }
cout << "Success!\n" << endl;
cudaFreeHost(h_A);
return(0);
} | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
#include <thrust/device_vector.h>
#include <thrust/sequence.h>
int main(int argc, char* argv[])
{
int nGPU;
if(argc < 2) {
cerr << "Use: number of integers" << endl;
return(1);
}
hipGetDeviceCount(&nGPU);
int n = atoi(argv[1]);
int size = nGPU * n * sizeof(int);
cout << "nGPU " << nGPU << " " << (n*nGPU*sizeof(int)/1e6) << "MB" << endl;
int *h_A;
hipHostAlloc(&h_A, size, hipHostMallocMapped);
for(int i=0; i < nGPU; i++) {
hipSetDevice(i);
thrust::sequence(thrust::device_pointer_cast(h_A + i*n),
thrust::device_pointer_cast(h_A + (i+1)*n),
i*n);
}
hipDeviceSynchronize(); // synchronize the writes
for(int i=0; i < nGPU*n; i++)
if(h_A[i] != i) { cout << "Error " << h_A[i] << endl; exit(1); }
cout << "Success!\n" << endl;
hipHostFree(h_A);
return(0);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
#include <thrust/device_vector.h>
#include <thrust/sequence.h>
int main(int argc, char* argv[])
{
int nGPU;
if(argc < 2) {
cerr << "Use: number of integers" << endl;
return(1);
}
hipGetDeviceCount(&nGPU);
int n = atoi(argv[1]);
int size = nGPU * n * sizeof(int);
cout << "nGPU " << nGPU << " " << (n*nGPU*sizeof(int)/1e6) << "MB" << endl;
int *h_A;
hipHostAlloc(&h_A, size, hipHostMallocMapped);
for(int i=0; i < nGPU; i++) {
hipSetDevice(i);
thrust::sequence(thrust::device_pointer_cast(h_A + i*n),
thrust::device_pointer_cast(h_A + (i+1)*n),
i*n);
}
hipDeviceSynchronize(); // synchronize the writes
for(int i=0; i < nGPU*n; i++)
if(h_A[i] != i) { cout << "Error " << h_A[i] << endl; exit(1); }
cout << "Success!\n" << endl;
hipHostFree(h_A);
return(0);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_10device_ptrIiEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SF_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_10device_ptrIiEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SF_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_10device_ptrIiEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SF_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_10device_ptrIiEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SF_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_10device_ptrIiEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SF_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_10device_ptrIiEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SF_:
s_load_b128 s[4:7], s[0:1], 0x10
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_add_co_u32 v0, s0, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s3, 0, s0
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[3:4], null, s7, v0, s[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v2, vcc_lo
flat_store_b32 v[0:1], v3
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_10device_ptrIiEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SF_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_10device_ptrIiEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SF_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_10device_ptrIiEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SF_,comdat
.Lfunc_end0:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_10device_ptrIiEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SF_, .Lfunc_end0-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_10device_ptrIiEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SF_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_10device_ptrIiEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SF_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_10device_ptrIiEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SF_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tElN6thrust20THRUST_200700_800_NS8cuda_cub10__tabulate7functorINS7_10device_ptrIiEENS7_6system6detail7generic6detail22compute_sequence_valueIivEElEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R4, R4, 0x200, RZ ; /* 0x0000020004047825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R6, P1, -R4.reuse, c[0x0][0x160], RZ ; /* 0x0000580004067a10 */
/* 0x040fe40007f3e1ff */
/*0060*/ IADD3 R7, P2, R4, R9, RZ ; /* 0x0000000904077210 */
/* 0x002fe40007f5e0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R6, 0x1ff, PT ; /* 0x000001ff0600780c */
/* 0x000fe40003f04070 */
/*0080*/ IADD3.X R3, ~R5, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590005037a10 */
/* 0x000fe20000ffe5ff */
/*0090*/ IMAD.X R0, RZ, RZ, R5, P2 ; /* 0x000000ffff007224 */
/* 0x000fe200010e0605 */
/*00a0*/ LEA R2, P1, R7, c[0x0][0x168], 0x2 ; /* 0x00005a0007027a11 */
/* 0x000fe400078210ff */
/*00b0*/ ISETP.GT.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fc40003f04300 */
/*00c0*/ LEA.HI.X R3, R7, c[0x0][0x16c], R0, 0x2, P1 ; /* 0x00005b0007037a11 */
/* 0x000fd600008f1400 */
/*00d0*/ @P0 BRA 0x1d0 ; /* 0x000000f000000947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R8, RZ, 0x1f, R6 ; /* 0x0000001fff087819 */
/* 0x000fe40000011406 */
/*0100*/ IADD3 R9, R9, 0x100, RZ ; /* 0x0000010009097810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GT.AND.EX P0, PT, R8, RZ, PT, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0003f04300 */
/*0120*/ @P0 IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff000624 */
/* 0x000fc800078e00ff */
/*0130*/ @P0 IMAD R7, R7, R0, c[0x0][0x170] ; /* 0x00005c0007070624 */
/* 0x000fca00078e0200 */
/*0140*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e2000c101904 */
/*0150*/ ISETP.GT.U32.AND P0, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x000fc80003f04070 */
/*0160*/ ISETP.GT.AND.EX P0, PT, R8, RZ, PT, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0003f04300 */
/*0170*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0180*/ IMAD.IADD R5, R4, 0x1, R9 ; /* 0x0000000104057824 */
/* 0x001fe400078e0209 */
/*0190*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff007624 */
/* 0x000fc800078e00ff */
/*01a0*/ IMAD R5, R5, R0, c[0x0][0x170] ; /* 0x00005c0005057624 */
/* 0x000fca00078e0200 */
/*01b0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ IADD3 R5, R4, 0x100, R9 ; /* 0x0000010004057810 */
/* 0x000fe20007ffe009 */
/*01e0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff007624 */
/* 0x000fc800078e00ff */
/*01f0*/ IMAD R7, R7, R0.reuse, c[0x0][0x170] ; /* 0x00005c0007077624 */
/* 0x080fe400078e0200 */
/*0200*/ IMAD R5, R5, R0, c[0x0][0x170] ; /* 0x00005c0005057624 */
/* 0x000fc600078e0200 */
/*0210*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*0220*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*0230*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0240*/ BRA 0x240; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_10device_ptrIiEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SF_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_10device_ptrIiEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SF_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_10device_ptrIiEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SF_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_10device_ptrIiEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SF_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_10device_ptrIiEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SF_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_10device_ptrIiEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SF_:
s_load_b128 s[4:7], s[0:1], 0x10
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_add_co_u32 v0, s0, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s3, 0, s0
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[3:4], null, s7, v0, s[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v2, vcc_lo
flat_store_b32 v[0:1], v3
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_10device_ptrIiEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SF_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_10device_ptrIiEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SF_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_10device_ptrIiEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SF_,comdat
.Lfunc_end0:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_10device_ptrIiEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SF_, .Lfunc_end0-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_10device_ptrIiEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SF_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_10device_ptrIiEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SF_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_10device_ptrIiEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SF_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void suma( int *a, int *b, int *c, int n, int m) {
int index = blockIdx.x + blockIdx.y * blockDim.y;
if(index < n*m){
c[index] = a[index] + b[index];
}
} | code for sm_80
Function : _Z4sumaPiS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002600 */
/*0050*/ IMAD R6, R3, c[0x0][0x4], R6 ; /* 0x0000010003067a24 */
/* 0x001fca00078e0206 */
/*0060*/ ISETP.GE.AND P0, PT, R6, UR4, PT ; /* 0x0000000406007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00c0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00f0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*0100*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void suma( int *a, int *b, int *c, int n, int m) {
int index = blockIdx.x + blockIdx.y * blockDim.y;
if(index < n*m){
c[index] = a[index] + b[index];
}
} | .file "tmpxft_001a2b3e_00000000-6_suma.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z4sumaPiS_S_iiPiS_S_ii
.type _Z29__device_stub__Z4sumaPiS_S_iiPiS_S_ii, @function
_Z29__device_stub__Z4sumaPiS_S_iiPiS_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4sumaPiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z4sumaPiS_S_iiPiS_S_ii, .-_Z29__device_stub__Z4sumaPiS_S_iiPiS_S_ii
.globl _Z4sumaPiS_S_ii
.type _Z4sumaPiS_S_ii, @function
_Z4sumaPiS_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z4sumaPiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4sumaPiS_S_ii, .-_Z4sumaPiS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4sumaPiS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4sumaPiS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void suma( int *a, int *b, int *c, int n, int m) {
int index = blockIdx.x + blockIdx.y * blockDim.y;
if(index < n*m){
c[index] = a[index] + b[index];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void suma( int *a, int *b, int *c, int n, int m) {
int index = blockIdx.x + blockIdx.y * blockDim.y;
if(index < n*m){
c[index] = a[index] + b[index];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void suma( int *a, int *b, int *c, int n, int m) {
int index = blockIdx.x + blockIdx.y * blockDim.y;
if(index < n*m){
c[index] = a[index] + b[index];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4sumaPiS_S_ii
.globl _Z4sumaPiS_S_ii
.p2align 8
.type _Z4sumaPiS_S_ii,@function
_Z4sumaPiS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s2, 16
s_mul_i32 s3, s5, s4
s_mul_i32 s2, s15, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s14
s_cmp_ge_i32 s2, s3
s_cbranch_scc1 .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_ashr_i32 s3, s2, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4sumaPiS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4sumaPiS_S_ii, .Lfunc_end0-_Z4sumaPiS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4sumaPiS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z4sumaPiS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void suma( int *a, int *b, int *c, int n, int m) {
int index = blockIdx.x + blockIdx.y * blockDim.y;
if(index < n*m){
c[index] = a[index] + b[index];
}
} | .text
.file "suma.hip"
.globl _Z19__device_stub__sumaPiS_S_ii # -- Begin function _Z19__device_stub__sumaPiS_S_ii
.p2align 4, 0x90
.type _Z19__device_stub__sumaPiS_S_ii,@function
_Z19__device_stub__sumaPiS_S_ii: # @_Z19__device_stub__sumaPiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4sumaPiS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__sumaPiS_S_ii, .Lfunc_end0-_Z19__device_stub__sumaPiS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4sumaPiS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4sumaPiS_S_ii,@object # @_Z4sumaPiS_S_ii
.section .rodata,"a",@progbits
.globl _Z4sumaPiS_S_ii
.p2align 3, 0x0
_Z4sumaPiS_S_ii:
.quad _Z19__device_stub__sumaPiS_S_ii
.size _Z4sumaPiS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4sumaPiS_S_ii"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__sumaPiS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4sumaPiS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4sumaPiS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002600 */
/*0050*/ IMAD R6, R3, c[0x0][0x4], R6 ; /* 0x0000010003067a24 */
/* 0x001fca00078e0206 */
/*0060*/ ISETP.GE.AND P0, PT, R6, UR4, PT ; /* 0x0000000406007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00c0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00f0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*0100*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4sumaPiS_S_ii
.globl _Z4sumaPiS_S_ii
.p2align 8
.type _Z4sumaPiS_S_ii,@function
_Z4sumaPiS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s2, 16
s_mul_i32 s3, s5, s4
s_mul_i32 s2, s15, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s14
s_cmp_ge_i32 s2, s3
s_cbranch_scc1 .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_ashr_i32 s3, s2, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4sumaPiS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4sumaPiS_S_ii, .Lfunc_end0-_Z4sumaPiS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4sumaPiS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z4sumaPiS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a2b3e_00000000-6_suma.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z4sumaPiS_S_iiPiS_S_ii
.type _Z29__device_stub__Z4sumaPiS_S_iiPiS_S_ii, @function
_Z29__device_stub__Z4sumaPiS_S_iiPiS_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4sumaPiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z4sumaPiS_S_iiPiS_S_ii, .-_Z29__device_stub__Z4sumaPiS_S_iiPiS_S_ii
.globl _Z4sumaPiS_S_ii
.type _Z4sumaPiS_S_ii, @function
_Z4sumaPiS_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z4sumaPiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4sumaPiS_S_ii, .-_Z4sumaPiS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4sumaPiS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4sumaPiS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "suma.hip"
.globl _Z19__device_stub__sumaPiS_S_ii # -- Begin function _Z19__device_stub__sumaPiS_S_ii
.p2align 4, 0x90
.type _Z19__device_stub__sumaPiS_S_ii,@function
_Z19__device_stub__sumaPiS_S_ii: # @_Z19__device_stub__sumaPiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4sumaPiS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__sumaPiS_S_ii, .Lfunc_end0-_Z19__device_stub__sumaPiS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4sumaPiS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4sumaPiS_S_ii,@object # @_Z4sumaPiS_S_ii
.section .rodata,"a",@progbits
.globl _Z4sumaPiS_S_ii
.p2align 3, 0x0
_Z4sumaPiS_S_ii:
.quad _Z19__device_stub__sumaPiS_S_ii
.size _Z4sumaPiS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4sumaPiS_S_ii"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__sumaPiS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4sumaPiS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void __initSeq(int *A, int nrows, int ncols) {
int ip = threadIdx.x + blockDim.x * (blockIdx.x + gridDim.x * blockIdx.y);
for (int i = ip; i < nrows*ncols; i += blockDim.x * gridDim.x * gridDim.y) {
A[i] = i % nrows;
}
} | code for sm_80
Function : _Z9__initSeqPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IABS R11, c[0x0][0x168] ; /* 0x00005a00000b7a13 */
/* 0x000fe20000000000 */
/*00b0*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*00c0*/ MOV R5, c[0x0][0x0] ; /* 0x0000000000057a02 */
/* 0x000fe20000000f00 */
/*00d0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00e0*/ I2F.RP R4, R11 ; /* 0x0000000b00047306 */
/* 0x000e220000209400 */
/*00f0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe40003f05270 */
/*0100*/ IABS R15, c[0x0][0x168] ; /* 0x00005a00000f7a13 */
/* 0x000fe20000000000 */
/*0110*/ IMAD R5, R5, c[0x0][0xc], RZ ; /* 0x0000030005057a24 */
/* 0x000fc800078e02ff */
/*0120*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0130*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0140*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0150*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0160*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*0170*/ IMAD R7, R6, R11, RZ ; /* 0x0000000b06077224 */
/* 0x000fc800078e02ff */
/*0180*/ IMAD.HI.U32 R6, R3, R7, R2 ; /* 0x0000000703067227 */
/* 0x000fe200078e0002 */
/*0190*/ LOP3.LUT R7, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff077a12 */
/* 0x000fc600078e33ff */
/*01a0*/ IABS R3, R0 ; /* 0x0000000000037213 */
/* 0x001fe40000000000 */
/*01b0*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc60003f46270 */
/*01c0*/ IMAD.HI.U32 R2, R6, R3, RZ ; /* 0x0000000306027227 */
/* 0x000fc800078e00ff */
/*01d0*/ IMAD.MOV R2, RZ, RZ, -R2 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0a02 */
/*01e0*/ IMAD R2, R15, R2, R3 ; /* 0x000000020f027224 */
/* 0x000fca00078e0203 */
/*01f0*/ ISETP.GT.U32.AND P1, PT, R11, R2, PT ; /* 0x000000020b00720c */
/* 0x000fda0003f24070 */
/*0200*/ @!P1 IADD3 R2, R2, -R15, RZ ; /* 0x8000000f02029210 */
/* 0x000fc80007ffe0ff */
/*0210*/ ISETP.GT.U32.AND P1, PT, R11, R2, PT ; /* 0x000000020b00720c */
/* 0x000fda0003f24070 */
/*0220*/ @!P1 IMAD.IADD R2, R2, 0x1, -R15 ; /* 0x0000000102029824 */
/* 0x000fca00078e0a0f */
/*0230*/ MOV R4, R2 ; /* 0x0000000200047202 */
/* 0x000fe20000000f00 */
/*0240*/ IMAD.WIDE R2, R0, R13, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e020d */
/*0250*/ @!P2 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff04a224 */
/* 0x000fe400078e0a04 */
/*0260*/ IMAD R0, R5, c[0x0][0x10], R0 ; /* 0x0000040005007a24 */
/* 0x000fc600078e0200 */
/*0270*/ SEL R9, R7, R4, !P0 ; /* 0x0000000407097207 */
/* 0x000fe40004000000 */
/*0280*/ ISETP.GE.AND P1, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fc6000bf26270 */
/*0290*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001f4000c101906 */
/*02a0*/ @!P1 BRA 0x1a0 ; /* 0xfffffef000009947 */
/* 0x000fea000383ffff */
/*02b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02c0*/ BRA 0x2c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void __initSeq(int *A, int nrows, int ncols) {
int ip = threadIdx.x + blockDim.x * (blockIdx.x + gridDim.x * blockIdx.y);
for (int i = ip; i < nrows*ncols; i += blockDim.x * gridDim.x * gridDim.y) {
A[i] = i % nrows;
}
} | .file "tmpxft_000487a5_00000000-6___initSeq.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9__initSeqPiiiPiii
.type _Z30__device_stub__Z9__initSeqPiiiPiii, @function
_Z30__device_stub__Z9__initSeqPiiiPiii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9__initSeqPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z9__initSeqPiiiPiii, .-_Z30__device_stub__Z9__initSeqPiiiPiii
.globl _Z9__initSeqPiii
.type _Z9__initSeqPiii, @function
_Z9__initSeqPiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9__initSeqPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9__initSeqPiii, .-_Z9__initSeqPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9__initSeqPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9__initSeqPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void __initSeq(int *A, int nrows, int ncols) {
int ip = threadIdx.x + blockDim.x * (blockIdx.x + gridDim.x * blockIdx.y);
for (int i = ip; i < nrows*ncols; i += blockDim.x * gridDim.x * gridDim.y) {
A[i] = i % nrows;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void __initSeq(int *A, int nrows, int ncols) {
int ip = threadIdx.x + blockDim.x * (blockIdx.x + gridDim.x * blockIdx.y);
for (int i = ip; i < nrows*ncols; i += blockDim.x * gridDim.x * gridDim.y) {
A[i] = i % nrows;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void __initSeq(int *A, int nrows, int ncols) {
int ip = threadIdx.x + blockDim.x * (blockIdx.x + gridDim.x * blockIdx.y);
for (int i = ip; i < nrows*ncols; i += blockDim.x * gridDim.x * gridDim.y) {
A[i] = i % nrows;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9__initSeqPiii
.globl _Z9__initSeqPiii
.p2align 8
.type _Z9__initSeqPiii,@function
_Z9__initSeqPiii:
s_clause 0x2
s_load_b32 s6, s[0:1], 0x10
s_load_b32 s7, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x8
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s6, s15
s_and_b32 s7, s7, 0xffff
s_add_i32 s8, s8, s14
s_mul_i32 s5, s5, s4
v_mad_u64_u32 v[1:2], null, s8, s7, v[0:1]
s_mov_b32 s8, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB0_3
s_ashr_i32 s8, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s4, s4, s8
s_xor_b32 s4, s4, s8
s_load_b32 s8, s[2:3], 0x4
v_cvt_f32_u32_e32 v0, s4
s_sub_i32 s2, 0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v2, s2, v0
s_load_b64 s[2:3], s[0:1], 0x0
s_mul_i32 s1, s6, s7
s_mov_b32 s6, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s1, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v4, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v1, v4
v_xor_b32_e32 v2, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v2, v0
v_mul_lo_u32 v3, v3, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v3
v_subrev_nc_u32_e32 v3, s4, v2
v_cmp_le_u32_e32 vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v5, v2, v3, vcc_lo
v_ashrrev_i32_e32 v2, 31, v1
v_subrev_nc_u32_e32 v6, s4, v5
v_cmp_le_u32_e32 vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_le_i32_e32 vcc_lo, s5, v1
v_add_co_u32 v2, s0, s2, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_xor_b32_e32 v5, v5, v4
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_or_b32 s6, vcc_lo, s6
v_sub_nc_u32_e32 v4, v5, v4
global_store_b32 v[2:3], v4, off
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9__initSeqPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9__initSeqPiii, .Lfunc_end0-_Z9__initSeqPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9__initSeqPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9__initSeqPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void __initSeq(int *A, int nrows, int ncols) {
int ip = threadIdx.x + blockDim.x * (blockIdx.x + gridDim.x * blockIdx.y);
for (int i = ip; i < nrows*ncols; i += blockDim.x * gridDim.x * gridDim.y) {
A[i] = i % nrows;
}
} | .text
.file "__initSeq.hip"
.globl _Z24__device_stub____initSeqPiii # -- Begin function _Z24__device_stub____initSeqPiii
.p2align 4, 0x90
.type _Z24__device_stub____initSeqPiii,@function
_Z24__device_stub____initSeqPiii: # @_Z24__device_stub____initSeqPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9__initSeqPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub____initSeqPiii, .Lfunc_end0-_Z24__device_stub____initSeqPiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9__initSeqPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9__initSeqPiii,@object # @_Z9__initSeqPiii
.section .rodata,"a",@progbits
.globl _Z9__initSeqPiii
.p2align 3, 0x0
_Z9__initSeqPiii:
.quad _Z24__device_stub____initSeqPiii
.size _Z9__initSeqPiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9__initSeqPiii"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub____initSeqPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9__initSeqPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9__initSeqPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IABS R11, c[0x0][0x168] ; /* 0x00005a00000b7a13 */
/* 0x000fe20000000000 */
/*00b0*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*00c0*/ MOV R5, c[0x0][0x0] ; /* 0x0000000000057a02 */
/* 0x000fe20000000f00 */
/*00d0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00e0*/ I2F.RP R4, R11 ; /* 0x0000000b00047306 */
/* 0x000e220000209400 */
/*00f0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe40003f05270 */
/*0100*/ IABS R15, c[0x0][0x168] ; /* 0x00005a00000f7a13 */
/* 0x000fe20000000000 */
/*0110*/ IMAD R5, R5, c[0x0][0xc], RZ ; /* 0x0000030005057a24 */
/* 0x000fc800078e02ff */
/*0120*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0130*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0140*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0150*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0160*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*0170*/ IMAD R7, R6, R11, RZ ; /* 0x0000000b06077224 */
/* 0x000fc800078e02ff */
/*0180*/ IMAD.HI.U32 R6, R3, R7, R2 ; /* 0x0000000703067227 */
/* 0x000fe200078e0002 */
/*0190*/ LOP3.LUT R7, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff077a12 */
/* 0x000fc600078e33ff */
/*01a0*/ IABS R3, R0 ; /* 0x0000000000037213 */
/* 0x001fe40000000000 */
/*01b0*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc60003f46270 */
/*01c0*/ IMAD.HI.U32 R2, R6, R3, RZ ; /* 0x0000000306027227 */
/* 0x000fc800078e00ff */
/*01d0*/ IMAD.MOV R2, RZ, RZ, -R2 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0a02 */
/*01e0*/ IMAD R2, R15, R2, R3 ; /* 0x000000020f027224 */
/* 0x000fca00078e0203 */
/*01f0*/ ISETP.GT.U32.AND P1, PT, R11, R2, PT ; /* 0x000000020b00720c */
/* 0x000fda0003f24070 */
/*0200*/ @!P1 IADD3 R2, R2, -R15, RZ ; /* 0x8000000f02029210 */
/* 0x000fc80007ffe0ff */
/*0210*/ ISETP.GT.U32.AND P1, PT, R11, R2, PT ; /* 0x000000020b00720c */
/* 0x000fda0003f24070 */
/*0220*/ @!P1 IMAD.IADD R2, R2, 0x1, -R15 ; /* 0x0000000102029824 */
/* 0x000fca00078e0a0f */
/*0230*/ MOV R4, R2 ; /* 0x0000000200047202 */
/* 0x000fe20000000f00 */
/*0240*/ IMAD.WIDE R2, R0, R13, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e020d */
/*0250*/ @!P2 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff04a224 */
/* 0x000fe400078e0a04 */
/*0260*/ IMAD R0, R5, c[0x0][0x10], R0 ; /* 0x0000040005007a24 */
/* 0x000fc600078e0200 */
/*0270*/ SEL R9, R7, R4, !P0 ; /* 0x0000000407097207 */
/* 0x000fe40004000000 */
/*0280*/ ISETP.GE.AND P1, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fc6000bf26270 */
/*0290*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001f4000c101906 */
/*02a0*/ @!P1 BRA 0x1a0 ; /* 0xfffffef000009947 */
/* 0x000fea000383ffff */
/*02b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02c0*/ BRA 0x2c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9__initSeqPiii
.globl _Z9__initSeqPiii
.p2align 8
.type _Z9__initSeqPiii,@function
_Z9__initSeqPiii:
s_clause 0x2
s_load_b32 s6, s[0:1], 0x10
s_load_b32 s7, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x8
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s6, s15
s_and_b32 s7, s7, 0xffff
s_add_i32 s8, s8, s14
s_mul_i32 s5, s5, s4
v_mad_u64_u32 v[1:2], null, s8, s7, v[0:1]
s_mov_b32 s8, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB0_3
s_ashr_i32 s8, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s4, s4, s8
s_xor_b32 s4, s4, s8
s_load_b32 s8, s[2:3], 0x4
v_cvt_f32_u32_e32 v0, s4
s_sub_i32 s2, 0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v2, s2, v0
s_load_b64 s[2:3], s[0:1], 0x0
s_mul_i32 s1, s6, s7
s_mov_b32 s6, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s1, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v4, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v1, v4
v_xor_b32_e32 v2, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v2, v0
v_mul_lo_u32 v3, v3, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v3
v_subrev_nc_u32_e32 v3, s4, v2
v_cmp_le_u32_e32 vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v5, v2, v3, vcc_lo
v_ashrrev_i32_e32 v2, 31, v1
v_subrev_nc_u32_e32 v6, s4, v5
v_cmp_le_u32_e32 vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_le_i32_e32 vcc_lo, s5, v1
v_add_co_u32 v2, s0, s2, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_xor_b32_e32 v5, v5, v4
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_or_b32 s6, vcc_lo, s6
v_sub_nc_u32_e32 v4, v5, v4
global_store_b32 v[2:3], v4, off
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9__initSeqPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9__initSeqPiii, .Lfunc_end0-_Z9__initSeqPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9__initSeqPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9__initSeqPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000487a5_00000000-6___initSeq.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9__initSeqPiiiPiii
.type _Z30__device_stub__Z9__initSeqPiiiPiii, @function
_Z30__device_stub__Z9__initSeqPiiiPiii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9__initSeqPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z9__initSeqPiiiPiii, .-_Z30__device_stub__Z9__initSeqPiiiPiii
.globl _Z9__initSeqPiii
.type _Z9__initSeqPiii, @function
_Z9__initSeqPiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9__initSeqPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9__initSeqPiii, .-_Z9__initSeqPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9__initSeqPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9__initSeqPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "__initSeq.hip"
.globl _Z24__device_stub____initSeqPiii # -- Begin function _Z24__device_stub____initSeqPiii
.p2align 4, 0x90
.type _Z24__device_stub____initSeqPiii,@function
_Z24__device_stub____initSeqPiii: # @_Z24__device_stub____initSeqPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9__initSeqPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub____initSeqPiii, .Lfunc_end0-_Z24__device_stub____initSeqPiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9__initSeqPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9__initSeqPiii,@object # @_Z9__initSeqPiii
.section .rodata,"a",@progbits
.globl _Z9__initSeqPiii
.p2align 3, 0x0
_Z9__initSeqPiii:
.quad _Z24__device_stub____initSeqPiii
.size _Z9__initSeqPiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9__initSeqPiii"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub____initSeqPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9__initSeqPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cuda_runtime.h>
#include <stdio.h>
#include <stdbool.h>
#define TILE_SIZE 512
#define WARP_SIZE 32
extern "C" void CSRmatvecmult(int* start, int* J, float* Val, int N, int nnz, float* x, float *y, bool bVectorized);
extern "C" void ELLmatvecmult(int N, int num_cols_per_row , int * indices, float * data , float * x , float * y);
/**
* Custom CUDA error check wrapper.
*/
#define checkCUDAError() do { \
cudaError_t error = cudaGetLastError(); \
if (error != cudaSuccess) { \
printf("(CUDA) %s", cudaGetErrorString(error)); \
printf(" (" __FILE__ ":%d)\n", __LINE__); \
}\
} while (0)
/**
* Cuda kernel for: CSR_s(A)x = y
*/
__global__ void k_csr_mat_vec_mm(int *start, int* j, float *a_content, int num_rows, float *x, float* y) {
// TODO: implement the scalar crs kernel
int row = blockDim.x * blockIdx.x + threadIdx.x;
float result = 0.0f;
for(int i=start[row];i<start[row+1];i++) {
int value = a_content[i];
int column = j[i];
result += x[column] * value;
}
y[row] += result;
}
/**
* Cuda kernel for: CSR_v(A)x = y
*/
__global__ void k_csr2_mat_vec_mm(int *start, int* j, float *a_content, int num_rows, float *x, float* y) {
//TODO: implement the vectorized csr kernel
}
/**
* Cuda kernel for: ELL(A)x = y
*/
__global__ void k_ell_mat_vec_mm ( int N, int num_cols_per_row , int * indices,
float * data , float * x , float * y ) {
//NYI: ellpack kernel
}
/**
* Perform: CSR(A)x = y
*/
void CSRmatvecmult(int* start, int* J, float* Val, int N, int nnz, float* x, float *y, bool bVectorized) {
int *start_d, *J_d;
float *Val_d, *x_d, *y_d;
/************************/
/* copy to device */
/************************/
cudaMalloc((void **) &start_d, (N+1) * sizeof(int));
checkCUDAError();
cudaMemcpy(start_d, start, (N+1) * sizeof(int), cudaMemcpyHostToDevice);
checkCUDAError();
cudaMalloc((void **) &J_d, nnz * sizeof(int));
checkCUDAError();
cudaMemcpy(J_d, J, nnz * sizeof(int), cudaMemcpyHostToDevice);
checkCUDAError();
cudaMalloc((void **) &Val_d, nnz * sizeof(float));
checkCUDAError();
cudaMemcpy(Val_d, Val, nnz * sizeof(float), cudaMemcpyHostToDevice);
checkCUDAError();
cudaMalloc((void **) &x_d, N * sizeof(float));
checkCUDAError();
cudaMemcpy(x_d, x, N * sizeof(float), cudaMemcpyHostToDevice);
checkCUDAError();
cudaMalloc((void **) &y_d, N * sizeof(float));
checkCUDAError();
cudaMemcpy(y_d, y, N * sizeof(float) , cudaMemcpyHostToDevice);
checkCUDAError();
/************************/
/* start kernel */
/************************/
if (bVectorized) {
//TODO: define grid and block size correctly
dim3 grid(1, 1, N/TILE_SIZE);
dim3 block(1, 1, TILE_SIZE);
k_csr2_mat_vec_mm <<< grid, block >>> (start_d, J_d, Val_d, N, x_d, y_d);
} else {
dim3 grid((N - 1)/TILE_SIZE + 1, 1, 1);
dim3 block(TILE_SIZE, 1, 1);
k_csr_mat_vec_mm <<< grid, block >>> (start_d, J_d, Val_d, N, x_d, y_d);
}
checkCUDAError();
/************************/
/* copy back */
/************************/
cudaMemcpy(y, y_d, N * sizeof(float), cudaMemcpyDeviceToHost);
checkCUDAError();
/************************/
/* free memory */
/************************/
cudaFree(start_d);
cudaFree(J_d);
cudaFree(Val_d);
cudaFree(x_d);
cudaFree(y_d);
}
/**
* Perform: ELL(A)x = y
*/
void ELLmatvecmult(int N, int num_cols_per_row , int * indices,
float * data , float * x , float * y) {
int *indices_d;
float *data_d, *x_d, *y_d;
/************************/
/* copy to device */
/************************/
cudaMalloc((void **) &indices_d, N * num_cols_per_row * sizeof(int));
checkCUDAError();
cudaMemcpy(indices_d, indices, N * num_cols_per_row * sizeof(int), cudaMemcpyHostToDevice);
checkCUDAError();
cudaMalloc((void **) &data_d, N * num_cols_per_row * sizeof(float));
checkCUDAError();
cudaMemcpy(data_d, data, N * num_cols_per_row * sizeof(float), cudaMemcpyHostToDevice);
checkCUDAError();
cudaMalloc((void **) &x_d, N * sizeof(float));
checkCUDAError();
cudaMemcpy(x_d, x, N * sizeof(float), cudaMemcpyHostToDevice);
checkCUDAError();
cudaMalloc((void **) &y_d, N * sizeof(float));
checkCUDAError();
cudaMemcpy(y_d, y, N * sizeof(float), cudaMemcpyHostToDevice);
checkCUDAError();
/************************/
/* start kernel */
/************************/
//NYI: define grid and block size
//k_ell_mat_vec_mm <<< grid, block >>> (N, num_cols_per_row, indices_d, data_d , x_d, y_d);
checkCUDAError();
/************************/
/* copy back */
/************************/
cudaMemcpy(y, y_d, N * sizeof(float), cudaMemcpyDeviceToHost);
checkCUDAError();
/************************/
/* free memory */
/************************/
cudaFree(indices_d);
cudaFree(data_d);
cudaFree(x_d);
cudaFree(y_d);
} | .file "tmpxft_000f5882_00000000-6_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "(CUDA) %s"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string " (/home/ubuntu/Datasets/stackv2/train-structured/PCXDME/CUDA/master/kernels.cu:%d)\n"
.text
.globl ELLmatvecmult
.type ELLmatvecmult, @function
ELLmatvecmult:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl %edi, %ebx
movq %rdx, %r15
movq %rcx, %r14
movq %r8, %r13
movq %r9, %r12
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
imull %edi, %esi
movslq %esi, %rbp
salq $2, %rbp
leaq 8(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L16
.L4:
movl $1, %ecx
movq %rbp, %rdx
movq %r15, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L17
.L5:
leaq 16(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L18
.L6:
movl $1, %ecx
movq %rbp, %rdx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L19
.L7:
movslq %ebx, %rbx
salq $2, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L20
.L8:
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L21
.L9:
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L22
.L10:
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L23
.L11:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L24
.L12:
movl $2, %ecx
movq %rbx, %rdx
movq 32(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L25
.L13:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $142, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L4
.L17:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $144, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L5
.L18:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $147, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L6
.L19:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $149, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L7
.L20:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $152, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L8
.L21:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $154, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L9
.L22:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $157, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L10
.L23:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $159, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L11
.L24:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $167, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L12
.L25:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $174, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L13
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size ELLmatvecmult, .-ELLmatvecmult
.globl _Z47__device_stub__Z16k_csr_mat_vec_mmPiS_PfiS0_S0_PiS_PfiS0_S0_
.type _Z47__device_stub__Z16k_csr_mat_vec_mmPiS_PfiS0_S0_PiS_PfiS0_S0_, @function
_Z47__device_stub__Z16k_csr_mat_vec_mmPiS_PfiS0_S0_PiS_PfiS0_S0_:
.LFB2083:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16k_csr_mat_vec_mmPiS_PfiS0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z47__device_stub__Z16k_csr_mat_vec_mmPiS_PfiS0_S0_PiS_PfiS0_S0_, .-_Z47__device_stub__Z16k_csr_mat_vec_mmPiS_PfiS0_S0_PiS_PfiS0_S0_
.globl _Z16k_csr_mat_vec_mmPiS_PfiS0_S0_
.type _Z16k_csr_mat_vec_mmPiS_PfiS0_S0_, @function
_Z16k_csr_mat_vec_mmPiS_PfiS0_S0_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z16k_csr_mat_vec_mmPiS_PfiS0_S0_PiS_PfiS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z16k_csr_mat_vec_mmPiS_PfiS0_S0_, .-_Z16k_csr_mat_vec_mmPiS_PfiS0_S0_
.globl _Z48__device_stub__Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_PiS_PfiS0_S0_
.type _Z48__device_stub__Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_PiS_PfiS0_S0_, @function
_Z48__device_stub__Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_PiS_PfiS0_S0_:
.LFB2085:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z48__device_stub__Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_PiS_PfiS0_S0_, .-_Z48__device_stub__Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_PiS_PfiS0_S0_
.globl _Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_
.type _Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_, @function
_Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_PiS_PfiS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_, .-_Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_
.globl CSRmatvecmult
.type CSRmatvecmult, @function
CSRmatvecmult:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rdi, %r13
movq %rsi, 8(%rsp)
movq %rdx, 16(%rsp)
movl %ecx, %r12d
movl %r8d, %ebp
movq %r9, 24(%rsp)
movq 176(%rsp), %r14
movl 184(%rsp), %r15d
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leal 1(%rcx), %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L62
.L44:
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L63
.L45:
movslq %ebp, %rbp
salq $2, %rbp
leaq 48(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L64
.L46:
movl $1, %ecx
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L65
.L47:
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L66
.L48:
movl $1, %ecx
movq %rbp, %rdx
movq 16(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L67
.L49:
subq $4, %rbx
leaq 64(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L68
.L50:
movl $1, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L69
.L51:
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L70
.L52:
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L71
.L53:
testb %r15b, %r15b
je .L54
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leal 511(%r12), %esi
testl %r12d, %r12d
cmovns %r12d, %esi
sarl $9, %esi
movl %esi, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $512, 100(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $512, %ecx
movq 80(%rsp), %rdi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L72
.L56:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L73
.L58:
movl $2, %ecx
movq %rbx, %rdx
movq 72(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L74
.L59:
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L75
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L62:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $69, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L44
.L63:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $71, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L45
.L64:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $74, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L46
.L65:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $76, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L47
.L66:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $79, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L48
.L67:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $81, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L49
.L68:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $84, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L50
.L69:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $86, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L51
.L70:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $89, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L52
.L71:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $91, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L53
.L72:
movq 72(%rsp), %r9
movq 64(%rsp), %r8
movl %r12d, %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z48__device_stub__Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_PiS_PfiS0_S0_
jmp .L56
.L54:
leal 510(%r12), %eax
movl %r12d, %edx
subl $1, %edx
cmovns %edx, %eax
sarl $9, %eax
addl $1, %eax
movl %eax, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $512, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L56
movq 72(%rsp), %r9
movq 64(%rsp), %r8
movl %r12d, %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z47__device_stub__Z16k_csr_mat_vec_mmPiS_PfiS0_S0_PiS_PfiS0_S0_
jmp .L56
.L73:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $110, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L58
.L74:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $117, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L59
.L75:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size CSRmatvecmult, .-CSRmatvecmult
.globl _Z46__device_stub__Z16k_ell_mat_vec_mmiiPiPfS0_S0_iiPiPfS0_S0_
.type _Z46__device_stub__Z16k_ell_mat_vec_mmiiPiPfS0_S0_iiPiPfS0_S0_, @function
_Z46__device_stub__Z16k_ell_mat_vec_mmiiPiPfS0_S0_iiPiPfS0_S0_:
.LFB2087:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L80
.L76:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L81
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L80:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16k_ell_mat_vec_mmiiPiPfS0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L76
.L81:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z46__device_stub__Z16k_ell_mat_vec_mmiiPiPfS0_S0_iiPiPfS0_S0_, .-_Z46__device_stub__Z16k_ell_mat_vec_mmiiPiPfS0_S0_iiPiPfS0_S0_
.globl _Z16k_ell_mat_vec_mmiiPiPfS0_S0_
.type _Z16k_ell_mat_vec_mmiiPiPfS0_S0_, @function
_Z16k_ell_mat_vec_mmiiPiPfS0_S0_:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z16k_ell_mat_vec_mmiiPiPfS0_S0_iiPiPfS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z16k_ell_mat_vec_mmiiPiPfS0_S0_, .-_Z16k_ell_mat_vec_mmiiPiPfS0_S0_
.section .rodata.str1.8
.align 8
.LC2:
.string "_Z16k_ell_mat_vec_mmiiPiPfS0_S0_"
.align 8
.LC3:
.string "_Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_"
.align 8
.LC4:
.string "_Z16k_csr_mat_vec_mmPiS_PfiS0_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z16k_ell_mat_vec_mmiiPiPfS0_S0_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z16k_csr_mat_vec_mmPiS_PfiS0_S0_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
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