system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cuda_runtime.h>
#include <stdio.h>
#include <stdbool.h>
#define TILE_SIZE 512
#define WARP_SIZE 32
extern "C" void CSRmatvecmult(int* start, int* J, float* Val, int N, int nnz, float* x, float *y, bool bVectorized);
extern "C" void ELLmatvecmult(int N, int num_cols_per_row , int * indices, float * data , float * x , float * y);
/**
* Custom CUDA error check wrapper.
*/
#define checkCUDAError() do { \
cudaError_t error = cudaGetLastError(); \
if (error != cudaSuccess) { \
printf("(CUDA) %s", cudaGetErrorString(error)); \
printf(" (" __FILE__ ":%d)\n", __LINE__); \
}\
} while (0)
/**
* Cuda kernel for: CSR_s(A)x = y
*/
__global__ void k_csr_mat_vec_mm(int *start, int* j, float *a_content, int num_rows, float *x, float* y) {
// TODO: implement the scalar crs kernel
int row = blockDim.x * blockIdx.x + threadIdx.x;
float result = 0.0f;
for(int i=start[row];i<start[row+1];i++) {
int value = a_content[i];
int column = j[i];
result += x[column] * value;
}
y[row] += result;
}
/**
* Cuda kernel for: CSR_v(A)x = y
*/
__global__ void k_csr2_mat_vec_mm(int *start, int* j, float *a_content, int num_rows, float *x, float* y) {
//TODO: implement the vectorized csr kernel
}
/**
* Cuda kernel for: ELL(A)x = y
*/
__global__ void k_ell_mat_vec_mm ( int N, int num_cols_per_row , int * indices,
float * data , float * x , float * y ) {
//NYI: ellpack kernel
}
/**
* Perform: CSR(A)x = y
*/
void CSRmatvecmult(int* start, int* J, float* Val, int N, int nnz, float* x, float *y, bool bVectorized) {
int *start_d, *J_d;
float *Val_d, *x_d, *y_d;
/************************/
/* copy to device */
/************************/
cudaMalloc((void **) &start_d, (N+1) * sizeof(int));
checkCUDAError();
cudaMemcpy(start_d, start, (N+1) * sizeof(int), cudaMemcpyHostToDevice);
checkCUDAError();
cudaMalloc((void **) &J_d, nnz * sizeof(int));
checkCUDAError();
cudaMemcpy(J_d, J, nnz * sizeof(int), cudaMemcpyHostToDevice);
checkCUDAError();
cudaMalloc((void **) &Val_d, nnz * sizeof(float));
checkCUDAError();
cudaMemcpy(Val_d, Val, nnz * sizeof(float), cudaMemcpyHostToDevice);
checkCUDAError();
cudaMalloc((void **) &x_d, N * sizeof(float));
checkCUDAError();
cudaMemcpy(x_d, x, N * sizeof(float), cudaMemcpyHostToDevice);
checkCUDAError();
cudaMalloc((void **) &y_d, N * sizeof(float));
checkCUDAError();
cudaMemcpy(y_d, y, N * sizeof(float) , cudaMemcpyHostToDevice);
checkCUDAError();
/************************/
/* start kernel */
/************************/
if (bVectorized) {
//TODO: define grid and block size correctly
dim3 grid(1, 1, N/TILE_SIZE);
dim3 block(1, 1, TILE_SIZE);
k_csr2_mat_vec_mm <<< grid, block >>> (start_d, J_d, Val_d, N, x_d, y_d);
} else {
dim3 grid((N - 1)/TILE_SIZE + 1, 1, 1);
dim3 block(TILE_SIZE, 1, 1);
k_csr_mat_vec_mm <<< grid, block >>> (start_d, J_d, Val_d, N, x_d, y_d);
}
checkCUDAError();
/************************/
/* copy back */
/************************/
cudaMemcpy(y, y_d, N * sizeof(float), cudaMemcpyDeviceToHost);
checkCUDAError();
/************************/
/* free memory */
/************************/
cudaFree(start_d);
cudaFree(J_d);
cudaFree(Val_d);
cudaFree(x_d);
cudaFree(y_d);
}
/**
* Perform: ELL(A)x = y
*/
void ELLmatvecmult(int N, int num_cols_per_row , int * indices,
float * data , float * x , float * y) {
int *indices_d;
float *data_d, *x_d, *y_d;
/************************/
/* copy to device */
/************************/
cudaMalloc((void **) &indices_d, N * num_cols_per_row * sizeof(int));
checkCUDAError();
cudaMemcpy(indices_d, indices, N * num_cols_per_row * sizeof(int), cudaMemcpyHostToDevice);
checkCUDAError();
cudaMalloc((void **) &data_d, N * num_cols_per_row * sizeof(float));
checkCUDAError();
cudaMemcpy(data_d, data, N * num_cols_per_row * sizeof(float), cudaMemcpyHostToDevice);
checkCUDAError();
cudaMalloc((void **) &x_d, N * sizeof(float));
checkCUDAError();
cudaMemcpy(x_d, x, N * sizeof(float), cudaMemcpyHostToDevice);
checkCUDAError();
cudaMalloc((void **) &y_d, N * sizeof(float));
checkCUDAError();
cudaMemcpy(y_d, y, N * sizeof(float), cudaMemcpyHostToDevice);
checkCUDAError();
/************************/
/* start kernel */
/************************/
//NYI: define grid and block size
//k_ell_mat_vec_mm <<< grid, block >>> (N, num_cols_per_row, indices_d, data_d , x_d, y_d);
checkCUDAError();
/************************/
/* copy back */
/************************/
cudaMemcpy(y, y_d, N * sizeof(float), cudaMemcpyDeviceToHost);
checkCUDAError();
/************************/
/* free memory */
/************************/
cudaFree(indices_d);
cudaFree(data_d);
cudaFree(x_d);
cudaFree(y_d);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdbool.h>
#define TILE_SIZE 512
#define WARP_SIZE 32
extern "C" void CSRmatvecmult(int* start, int* J, float* Val, int N, int nnz, float* x, float *y, bool bVectorized);
extern "C" void ELLmatvecmult(int N, int num_cols_per_row , int * indices, float * data , float * x , float * y);
/**
* Custom CUDA error check wrapper.
*/
#define checkCUDAError() do { \
hipError_t error = hipGetLastError(); \
if (error != hipSuccess) { \
printf("(CUDA) %s", hipGetErrorString(error)); \
printf(" (" __FILE__ ":%d)\n", __LINE__); \
}\
} while (0)
/**
* Cuda kernel for: CSR_s(A)x = y
*/
__global__ void k_csr_mat_vec_mm(int *start, int* j, float *a_content, int num_rows, float *x, float* y) {
// TODO: implement the scalar crs kernel
int row = blockDim.x * blockIdx.x + threadIdx.x;
float result = 0.0f;
for(int i=start[row];i<start[row+1];i++) {
int value = a_content[i];
int column = j[i];
result += x[column] * value;
}
y[row] += result;
}
/**
* Cuda kernel for: CSR_v(A)x = y
*/
__global__ void k_csr2_mat_vec_mm(int *start, int* j, float *a_content, int num_rows, float *x, float* y) {
//TODO: implement the vectorized csr kernel
}
/**
* Cuda kernel for: ELL(A)x = y
*/
__global__ void k_ell_mat_vec_mm ( int N, int num_cols_per_row , int * indices,
float * data , float * x , float * y ) {
//NYI: ellpack kernel
}
/**
* Perform: CSR(A)x = y
*/
void CSRmatvecmult(int* start, int* J, float* Val, int N, int nnz, float* x, float *y, bool bVectorized) {
int *start_d, *J_d;
float *Val_d, *x_d, *y_d;
/************************/
/* copy to device */
/************************/
hipMalloc((void **) &start_d, (N+1) * sizeof(int));
checkCUDAError();
hipMemcpy(start_d, start, (N+1) * sizeof(int), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) &J_d, nnz * sizeof(int));
checkCUDAError();
hipMemcpy(J_d, J, nnz * sizeof(int), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) &Val_d, nnz * sizeof(float));
checkCUDAError();
hipMemcpy(Val_d, Val, nnz * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) &x_d, N * sizeof(float));
checkCUDAError();
hipMemcpy(x_d, x, N * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) &y_d, N * sizeof(float));
checkCUDAError();
hipMemcpy(y_d, y, N * sizeof(float) , hipMemcpyHostToDevice);
checkCUDAError();
/************************/
/* start kernel */
/************************/
if (bVectorized) {
//TODO: define grid and block size correctly
dim3 grid(1, 1, N/TILE_SIZE);
dim3 block(1, 1, TILE_SIZE);
k_csr2_mat_vec_mm <<< grid, block >>> (start_d, J_d, Val_d, N, x_d, y_d);
} else {
dim3 grid((N - 1)/TILE_SIZE + 1, 1, 1);
dim3 block(TILE_SIZE, 1, 1);
k_csr_mat_vec_mm <<< grid, block >>> (start_d, J_d, Val_d, N, x_d, y_d);
}
checkCUDAError();
/************************/
/* copy back */
/************************/
hipMemcpy(y, y_d, N * sizeof(float), hipMemcpyDeviceToHost);
checkCUDAError();
/************************/
/* free memory */
/************************/
hipFree(start_d);
hipFree(J_d);
hipFree(Val_d);
hipFree(x_d);
hipFree(y_d);
}
/**
* Perform: ELL(A)x = y
*/
void ELLmatvecmult(int N, int num_cols_per_row , int * indices,
float * data , float * x , float * y) {
int *indices_d;
float *data_d, *x_d, *y_d;
/************************/
/* copy to device */
/************************/
hipMalloc((void **) &indices_d, N * num_cols_per_row * sizeof(int));
checkCUDAError();
hipMemcpy(indices_d, indices, N * num_cols_per_row * sizeof(int), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) &data_d, N * num_cols_per_row * sizeof(float));
checkCUDAError();
hipMemcpy(data_d, data, N * num_cols_per_row * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) &x_d, N * sizeof(float));
checkCUDAError();
hipMemcpy(x_d, x, N * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) &y_d, N * sizeof(float));
checkCUDAError();
hipMemcpy(y_d, y, N * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
/************************/
/* start kernel */
/************************/
//NYI: define grid and block size
//k_ell_mat_vec_mm <<< grid, block >>> (N, num_cols_per_row, indices_d, data_d , x_d, y_d);
checkCUDAError();
/************************/
/* copy back */
/************************/
hipMemcpy(y, y_d, N * sizeof(float), hipMemcpyDeviceToHost);
checkCUDAError();
/************************/
/* free memory */
/************************/
hipFree(indices_d);
hipFree(data_d);
hipFree(x_d);
hipFree(y_d);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdbool.h>
#define TILE_SIZE 512
#define WARP_SIZE 32
extern "C" void CSRmatvecmult(int* start, int* J, float* Val, int N, int nnz, float* x, float *y, bool bVectorized);
extern "C" void ELLmatvecmult(int N, int num_cols_per_row , int * indices, float * data , float * x , float * y);
/**
* Custom CUDA error check wrapper.
*/
#define checkCUDAError() do { \
hipError_t error = hipGetLastError(); \
if (error != hipSuccess) { \
printf("(CUDA) %s", hipGetErrorString(error)); \
printf(" (" __FILE__ ":%d)\n", __LINE__); \
}\
} while (0)
/**
* Cuda kernel for: CSR_s(A)x = y
*/
__global__ void k_csr_mat_vec_mm(int *start, int* j, float *a_content, int num_rows, float *x, float* y) {
// TODO: implement the scalar crs kernel
int row = blockDim.x * blockIdx.x + threadIdx.x;
float result = 0.0f;
for(int i=start[row];i<start[row+1];i++) {
int value = a_content[i];
int column = j[i];
result += x[column] * value;
}
y[row] += result;
}
/**
* Cuda kernel for: CSR_v(A)x = y
*/
__global__ void k_csr2_mat_vec_mm(int *start, int* j, float *a_content, int num_rows, float *x, float* y) {
//TODO: implement the vectorized csr kernel
}
/**
* Cuda kernel for: ELL(A)x = y
*/
__global__ void k_ell_mat_vec_mm ( int N, int num_cols_per_row , int * indices,
float * data , float * x , float * y ) {
//NYI: ellpack kernel
}
/**
* Perform: CSR(A)x = y
*/
void CSRmatvecmult(int* start, int* J, float* Val, int N, int nnz, float* x, float *y, bool bVectorized) {
int *start_d, *J_d;
float *Val_d, *x_d, *y_d;
/************************/
/* copy to device */
/************************/
hipMalloc((void **) &start_d, (N+1) * sizeof(int));
checkCUDAError();
hipMemcpy(start_d, start, (N+1) * sizeof(int), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) &J_d, nnz * sizeof(int));
checkCUDAError();
hipMemcpy(J_d, J, nnz * sizeof(int), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) &Val_d, nnz * sizeof(float));
checkCUDAError();
hipMemcpy(Val_d, Val, nnz * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) &x_d, N * sizeof(float));
checkCUDAError();
hipMemcpy(x_d, x, N * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) &y_d, N * sizeof(float));
checkCUDAError();
hipMemcpy(y_d, y, N * sizeof(float) , hipMemcpyHostToDevice);
checkCUDAError();
/************************/
/* start kernel */
/************************/
if (bVectorized) {
//TODO: define grid and block size correctly
dim3 grid(1, 1, N/TILE_SIZE);
dim3 block(1, 1, TILE_SIZE);
k_csr2_mat_vec_mm <<< grid, block >>> (start_d, J_d, Val_d, N, x_d, y_d);
} else {
dim3 grid((N - 1)/TILE_SIZE + 1, 1, 1);
dim3 block(TILE_SIZE, 1, 1);
k_csr_mat_vec_mm <<< grid, block >>> (start_d, J_d, Val_d, N, x_d, y_d);
}
checkCUDAError();
/************************/
/* copy back */
/************************/
hipMemcpy(y, y_d, N * sizeof(float), hipMemcpyDeviceToHost);
checkCUDAError();
/************************/
/* free memory */
/************************/
hipFree(start_d);
hipFree(J_d);
hipFree(Val_d);
hipFree(x_d);
hipFree(y_d);
}
/**
* Perform: ELL(A)x = y
*/
void ELLmatvecmult(int N, int num_cols_per_row , int * indices,
float * data , float * x , float * y) {
int *indices_d;
float *data_d, *x_d, *y_d;
/************************/
/* copy to device */
/************************/
hipMalloc((void **) &indices_d, N * num_cols_per_row * sizeof(int));
checkCUDAError();
hipMemcpy(indices_d, indices, N * num_cols_per_row * sizeof(int), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) &data_d, N * num_cols_per_row * sizeof(float));
checkCUDAError();
hipMemcpy(data_d, data, N * num_cols_per_row * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) &x_d, N * sizeof(float));
checkCUDAError();
hipMemcpy(x_d, x, N * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) &y_d, N * sizeof(float));
checkCUDAError();
hipMemcpy(y_d, y, N * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
/************************/
/* start kernel */
/************************/
//NYI: define grid and block size
//k_ell_mat_vec_mm <<< grid, block >>> (N, num_cols_per_row, indices_d, data_d , x_d, y_d);
checkCUDAError();
/************************/
/* copy back */
/************************/
hipMemcpy(y, y_d, N * sizeof(float), hipMemcpyDeviceToHost);
checkCUDAError();
/************************/
/* free memory */
/************************/
hipFree(indices_d);
hipFree(data_d);
hipFree(x_d);
hipFree(y_d);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16k_csr_mat_vec_mmPiS_PfiS0_S0_
.globl _Z16k_csr_mat_vec_mmPiS_PfiS0_S0_
.p2align 8
.type _Z16k_csr_mat_vec_mmPiS_PfiS0_S0_,@function
_Z16k_csr_mat_vec_mmPiS_PfiS0_S0_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v0, 0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_mov_b32 s3, exec_lo
global_load_b64 v[3:4], v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v3, v4
s_cbranch_execz .LBB0_4
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x8
s_load_b64 s[4:5], s[0:1], 0x20
v_ashrrev_i32_e32 v6, 31, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v0, 0
s_mov_b32 s6, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s10, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s11, v8, vcc_lo
v_add_co_u32 v7, vcc_lo, s8, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
.p2align 6
.LBB0_2:
global_load_b32 v9, v[7:8], off
global_load_b32 v11, v[5:6], off
s_waitcnt vmcnt(1)
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_add_co_u32 v9, vcc_lo, s4, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
global_load_b32 v9, v[9:10], off
s_waitcnt vmcnt(1)
v_cvt_i32_f32_e32 v10, v11
v_add_co_u32 v7, vcc_lo, v7, 4
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v10, v10
s_waitcnt vmcnt(0)
v_dual_fmac_f32 v0, v9, v10 :: v_dual_add_nc_u32 v3, 1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s2, v3, v4
s_or_b32 s6, s2, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s6
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x28
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v3, v[1:2], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v3
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16k_csr_mat_vec_mmPiS_PfiS0_S0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16k_csr_mat_vec_mmPiS_PfiS0_S0_, .Lfunc_end0-_Z16k_csr_mat_vec_mmPiS_PfiS0_S0_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_
.globl _Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_
.p2align 8
.type _Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_,@function
_Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_, .Lfunc_end1-_Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16k_ell_mat_vec_mmiiPiPfS0_S0_
.globl _Z16k_ell_mat_vec_mmiiPiPfS0_S0_
.p2align 8
.type _Z16k_ell_mat_vec_mmiiPiPfS0_S0_,@function
_Z16k_ell_mat_vec_mmiiPiPfS0_S0_:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16k_ell_mat_vec_mmiiPiPfS0_S0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z16k_ell_mat_vec_mmiiPiPfS0_S0_, .Lfunc_end2-_Z16k_ell_mat_vec_mmiiPiPfS0_S0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16k_csr_mat_vec_mmPiS_PfiS0_S0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16k_csr_mat_vec_mmPiS_PfiS0_S0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16k_ell_mat_vec_mmiiPiPfS0_S0_
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z16k_ell_mat_vec_mmiiPiPfS0_S0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdbool.h>
#define TILE_SIZE 512
#define WARP_SIZE 32
extern "C" void CSRmatvecmult(int* start, int* J, float* Val, int N, int nnz, float* x, float *y, bool bVectorized);
extern "C" void ELLmatvecmult(int N, int num_cols_per_row , int * indices, float * data , float * x , float * y);
/**
* Custom CUDA error check wrapper.
*/
#define checkCUDAError() do { \
hipError_t error = hipGetLastError(); \
if (error != hipSuccess) { \
printf("(CUDA) %s", hipGetErrorString(error)); \
printf(" (" __FILE__ ":%d)\n", __LINE__); \
}\
} while (0)
/**
* Cuda kernel for: CSR_s(A)x = y
*/
__global__ void k_csr_mat_vec_mm(int *start, int* j, float *a_content, int num_rows, float *x, float* y) {
// TODO: implement the scalar crs kernel
int row = blockDim.x * blockIdx.x + threadIdx.x;
float result = 0.0f;
for(int i=start[row];i<start[row+1];i++) {
int value = a_content[i];
int column = j[i];
result += x[column] * value;
}
y[row] += result;
}
/**
* Cuda kernel for: CSR_v(A)x = y
*/
__global__ void k_csr2_mat_vec_mm(int *start, int* j, float *a_content, int num_rows, float *x, float* y) {
//TODO: implement the vectorized csr kernel
}
/**
* Cuda kernel for: ELL(A)x = y
*/
__global__ void k_ell_mat_vec_mm ( int N, int num_cols_per_row , int * indices,
float * data , float * x , float * y ) {
//NYI: ellpack kernel
}
/**
* Perform: CSR(A)x = y
*/
void CSRmatvecmult(int* start, int* J, float* Val, int N, int nnz, float* x, float *y, bool bVectorized) {
int *start_d, *J_d;
float *Val_d, *x_d, *y_d;
/************************/
/* copy to device */
/************************/
hipMalloc((void **) &start_d, (N+1) * sizeof(int));
checkCUDAError();
hipMemcpy(start_d, start, (N+1) * sizeof(int), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) &J_d, nnz * sizeof(int));
checkCUDAError();
hipMemcpy(J_d, J, nnz * sizeof(int), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) &Val_d, nnz * sizeof(float));
checkCUDAError();
hipMemcpy(Val_d, Val, nnz * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) &x_d, N * sizeof(float));
checkCUDAError();
hipMemcpy(x_d, x, N * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) &y_d, N * sizeof(float));
checkCUDAError();
hipMemcpy(y_d, y, N * sizeof(float) , hipMemcpyHostToDevice);
checkCUDAError();
/************************/
/* start kernel */
/************************/
if (bVectorized) {
//TODO: define grid and block size correctly
dim3 grid(1, 1, N/TILE_SIZE);
dim3 block(1, 1, TILE_SIZE);
k_csr2_mat_vec_mm <<< grid, block >>> (start_d, J_d, Val_d, N, x_d, y_d);
} else {
dim3 grid((N - 1)/TILE_SIZE + 1, 1, 1);
dim3 block(TILE_SIZE, 1, 1);
k_csr_mat_vec_mm <<< grid, block >>> (start_d, J_d, Val_d, N, x_d, y_d);
}
checkCUDAError();
/************************/
/* copy back */
/************************/
hipMemcpy(y, y_d, N * sizeof(float), hipMemcpyDeviceToHost);
checkCUDAError();
/************************/
/* free memory */
/************************/
hipFree(start_d);
hipFree(J_d);
hipFree(Val_d);
hipFree(x_d);
hipFree(y_d);
}
/**
* Perform: ELL(A)x = y
*/
void ELLmatvecmult(int N, int num_cols_per_row , int * indices,
float * data , float * x , float * y) {
int *indices_d;
float *data_d, *x_d, *y_d;
/************************/
/* copy to device */
/************************/
hipMalloc((void **) &indices_d, N * num_cols_per_row * sizeof(int));
checkCUDAError();
hipMemcpy(indices_d, indices, N * num_cols_per_row * sizeof(int), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) &data_d, N * num_cols_per_row * sizeof(float));
checkCUDAError();
hipMemcpy(data_d, data, N * num_cols_per_row * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) &x_d, N * sizeof(float));
checkCUDAError();
hipMemcpy(x_d, x, N * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) &y_d, N * sizeof(float));
checkCUDAError();
hipMemcpy(y_d, y, N * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
/************************/
/* start kernel */
/************************/
//NYI: define grid and block size
//k_ell_mat_vec_mm <<< grid, block >>> (N, num_cols_per_row, indices_d, data_d , x_d, y_d);
checkCUDAError();
/************************/
/* copy back */
/************************/
hipMemcpy(y, y_d, N * sizeof(float), hipMemcpyDeviceToHost);
checkCUDAError();
/************************/
/* free memory */
/************************/
hipFree(indices_d);
hipFree(data_d);
hipFree(x_d);
hipFree(y_d);
} | .text
.file "kernels.hip"
.globl _Z31__device_stub__k_csr_mat_vec_mmPiS_PfiS0_S0_ # -- Begin function _Z31__device_stub__k_csr_mat_vec_mmPiS_PfiS0_S0_
.p2align 4, 0x90
.type _Z31__device_stub__k_csr_mat_vec_mmPiS_PfiS0_S0_,@function
_Z31__device_stub__k_csr_mat_vec_mmPiS_PfiS0_S0_: # @_Z31__device_stub__k_csr_mat_vec_mmPiS_PfiS0_S0_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16k_csr_mat_vec_mmPiS_PfiS0_S0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z31__device_stub__k_csr_mat_vec_mmPiS_PfiS0_S0_, .Lfunc_end0-_Z31__device_stub__k_csr_mat_vec_mmPiS_PfiS0_S0_
.cfi_endproc
# -- End function
.globl _Z32__device_stub__k_csr2_mat_vec_mmPiS_PfiS0_S0_ # -- Begin function _Z32__device_stub__k_csr2_mat_vec_mmPiS_PfiS0_S0_
.p2align 4, 0x90
.type _Z32__device_stub__k_csr2_mat_vec_mmPiS_PfiS0_S0_,@function
_Z32__device_stub__k_csr2_mat_vec_mmPiS_PfiS0_S0_: # @_Z32__device_stub__k_csr2_mat_vec_mmPiS_PfiS0_S0_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z32__device_stub__k_csr2_mat_vec_mmPiS_PfiS0_S0_, .Lfunc_end1-_Z32__device_stub__k_csr2_mat_vec_mmPiS_PfiS0_S0_
.cfi_endproc
# -- End function
.globl _Z31__device_stub__k_ell_mat_vec_mmiiPiPfS0_S0_ # -- Begin function _Z31__device_stub__k_ell_mat_vec_mmiiPiPfS0_S0_
.p2align 4, 0x90
.type _Z31__device_stub__k_ell_mat_vec_mmiiPiPfS0_S0_,@function
_Z31__device_stub__k_ell_mat_vec_mmiiPiPfS0_S0_: # @_Z31__device_stub__k_ell_mat_vec_mmiiPiPfS0_S0_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16k_ell_mat_vec_mmiiPiPfS0_S0_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z31__device_stub__k_ell_mat_vec_mmiiPiPfS0_S0_, .Lfunc_end2-_Z31__device_stub__k_ell_mat_vec_mmiiPiPfS0_S0_
.cfi_endproc
# -- End function
.globl CSRmatvecmult # -- Begin function CSRmatvecmult
.p2align 4, 0x90
.type CSRmatvecmult,@function
CSRmatvecmult: # @CSRmatvecmult
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 208(%rsp) # 8-byte Spill
movl %r8d, %ebp
movl %ecx, %r14d
movq %rdx, 200(%rsp) # 8-byte Spill
movq %rsi, %r13
movq %rdi, %r15
movslq %ecx, %rbx
leaq 4(,%rbx,4), %r12
leaq 48(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
je .LBB3_2
# %bb.1:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $69, %esi
xorl %eax, %eax
callq printf
.LBB3_2:
movq 48(%rsp), %rdi
movq %r15, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB3_4
# %bb.3:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $71, %esi
xorl %eax, %eax
callq printf
.LBB3_4:
movslq %ebp, %rbp
shlq $2, %rbp
leaq 40(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
je .LBB3_6
# %bb.5:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $74, %esi
xorl %eax, %eax
callq printf
.LBB3_6:
movq 40(%rsp), %rdi
movq %r13, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB3_8
# %bb.7:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $76, %esi
xorl %eax, %eax
callq printf
.LBB3_8:
leaq 32(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
je .LBB3_10
# %bb.9:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $79, %esi
xorl %eax, %eax
callq printf
.LBB3_10:
movq 32(%rsp), %rdi
movq 200(%rsp), %rsi # 8-byte Reload
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB3_12
# %bb.11:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $81, %esi
xorl %eax, %eax
callq printf
.LBB3_12:
shlq $2, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
je .LBB3_14
# %bb.13:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $84, %esi
xorl %eax, %eax
callq printf
.LBB3_14:
movq 24(%rsp), %rdi
movq 208(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB3_16
# %bb.15:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $86, %esi
xorl %eax, %eax
callq printf
.LBB3_16:
movq 272(%rsp), %r15
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
je .LBB3_18
# %bb.17:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $89, %esi
xorl %eax, %eax
callq printf
.LBB3_18:
movzbl 280(%rsp), %ebp
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB3_20
# %bb.19:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $91, %esi
xorl %eax, %eax
callq printf
.LBB3_20:
movabsq $4294967297, %rdx # imm = 0x100000001
testb %bpl, %bpl
je .LBB3_23
# %bb.21:
leal 511(%r14), %esi
testl %r14d, %r14d
cmovnsl %r14d, %esi
sarl $9, %esi
movq %rdx, %rdi
movl $512, %ecx # imm = 0x200
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_26
# %bb.22:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl %r14d, 12(%rsp)
movq %rsi, 112(%rsp)
movq %rdi, 104(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 112(%rsp), %rax
movq %rax, 176(%rsp)
leaq 104(%rsp), %rax
movq %rax, 184(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_, %edi
jmp .LBB3_25
.LBB3_23:
leal -1(%r14), %eax
leal 510(%r14), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $9, %ecx
incl %ecx
leaq (%rdx,%rcx), %rdi
decq %rdi
addq $511, %rdx # imm = 0x1FF
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_26
# %bb.24:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl %r14d, 12(%rsp)
movq %rsi, 112(%rsp)
movq %rdi, 104(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 112(%rsp), %rax
movq %rax, 176(%rsp)
leaq 104(%rsp), %rax
movq %rax, 184(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z16k_csr_mat_vec_mmPiS_PfiS0_S0_, %edi
.LBB3_25:
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_26:
callq hipGetLastError
testl %eax, %eax
je .LBB3_28
# %bb.27:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $110, %esi
xorl %eax, %eax
callq printf
.LBB3_28:
movq 16(%rsp), %rsi
movq %r15, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB3_30
# %bb.29:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $117, %esi
xorl %eax, %eax
callq printf
.LBB3_30:
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size CSRmatvecmult, .Lfunc_end3-CSRmatvecmult
.cfi_endproc
# -- End function
.globl ELLmatvecmult # -- Begin function ELLmatvecmult
.p2align 4, 0x90
.type ELLmatvecmult,@function
ELLmatvecmult: # @ELLmatvecmult
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, %r14
movq %rcx, %r15
movq %rdx, %r13
movl %edi, %ebp
imull %edi, %esi
movslq %esi, %r12
shlq $2, %r12
leaq 32(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
je .LBB4_2
# %bb.1:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $142, %esi
xorl %eax, %eax
callq printf
.LBB4_2:
movq 32(%rsp), %rdi
movq %r13, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB4_4
# %bb.3:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $144, %esi
xorl %eax, %eax
callq printf
.LBB4_4:
leaq 24(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
je .LBB4_6
# %bb.5:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $147, %esi
xorl %eax, %eax
callq printf
.LBB4_6:
movq 24(%rsp), %rdi
movq %r15, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB4_8
# %bb.7:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $149, %esi
xorl %eax, %eax
callq printf
.LBB4_8:
movslq %ebp, %r15
shlq $2, %r15
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
je .LBB4_10
# %bb.9:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $152, %esi
xorl %eax, %eax
callq printf
.LBB4_10:
movq 16(%rsp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB4_12
# %bb.11:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $154, %esi
xorl %eax, %eax
callq printf
.LBB4_12:
leaq 8(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
je .LBB4_14
# %bb.13:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $157, %esi
xorl %eax, %eax
callq printf
.LBB4_14:
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB4_16
# %bb.15:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $159, %esi
xorl %eax, %eax
callq printf
.LBB4_16:
callq hipGetLastError
testl %eax, %eax
je .LBB4_18
# %bb.17:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $167, %esi
xorl %eax, %eax
callq printf
.LBB4_18:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB4_20
# %bb.19:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $174, %esi
xorl %eax, %eax
callq printf
.LBB4_20:
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size ELLmatvecmult, .Lfunc_end4-ELLmatvecmult
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16k_csr_mat_vec_mmPiS_PfiS0_S0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16k_ell_mat_vec_mmiiPiPfS0_S0_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16k_csr_mat_vec_mmPiS_PfiS0_S0_,@object # @_Z16k_csr_mat_vec_mmPiS_PfiS0_S0_
.section .rodata,"a",@progbits
.globl _Z16k_csr_mat_vec_mmPiS_PfiS0_S0_
.p2align 3, 0x0
_Z16k_csr_mat_vec_mmPiS_PfiS0_S0_:
.quad _Z31__device_stub__k_csr_mat_vec_mmPiS_PfiS0_S0_
.size _Z16k_csr_mat_vec_mmPiS_PfiS0_S0_, 8
.type _Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_,@object # @_Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_
.globl _Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_
.p2align 3, 0x0
_Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_:
.quad _Z32__device_stub__k_csr2_mat_vec_mmPiS_PfiS0_S0_
.size _Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_, 8
.type _Z16k_ell_mat_vec_mmiiPiPfS0_S0_,@object # @_Z16k_ell_mat_vec_mmiiPiPfS0_S0_
.globl _Z16k_ell_mat_vec_mmiiPiPfS0_S0_
.p2align 3, 0x0
_Z16k_ell_mat_vec_mmiiPiPfS0_S0_:
.quad _Z31__device_stub__k_ell_mat_vec_mmiiPiPfS0_S0_
.size _Z16k_ell_mat_vec_mmiiPiPfS0_S0_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "(CUDA) %s"
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " (/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/PCXDME/CUDA/master/kernels.hip:%d)\n"
.size .L.str.1, 95
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16k_csr_mat_vec_mmPiS_PfiS0_S0_"
.size .L__unnamed_1, 34
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_"
.size .L__unnamed_2, 35
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z16k_ell_mat_vec_mmiiPiPfS0_S0_"
.size .L__unnamed_3, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__k_csr_mat_vec_mmPiS_PfiS0_S0_
.addrsig_sym _Z32__device_stub__k_csr2_mat_vec_mmPiS_PfiS0_S0_
.addrsig_sym _Z31__device_stub__k_ell_mat_vec_mmiiPiPfS0_S0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16k_csr_mat_vec_mmPiS_PfiS0_S0_
.addrsig_sym _Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_
.addrsig_sym _Z16k_ell_mat_vec_mmiiPiPfS0_S0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f5882_00000000-6_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "(CUDA) %s"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string " (/home/ubuntu/Datasets/stackv2/train-structured/PCXDME/CUDA/master/kernels.cu:%d)\n"
.text
.globl ELLmatvecmult
.type ELLmatvecmult, @function
ELLmatvecmult:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl %edi, %ebx
movq %rdx, %r15
movq %rcx, %r14
movq %r8, %r13
movq %r9, %r12
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
imull %edi, %esi
movslq %esi, %rbp
salq $2, %rbp
leaq 8(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L16
.L4:
movl $1, %ecx
movq %rbp, %rdx
movq %r15, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L17
.L5:
leaq 16(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L18
.L6:
movl $1, %ecx
movq %rbp, %rdx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L19
.L7:
movslq %ebx, %rbx
salq $2, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L20
.L8:
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L21
.L9:
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L22
.L10:
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L23
.L11:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L24
.L12:
movl $2, %ecx
movq %rbx, %rdx
movq 32(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L25
.L13:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $142, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L4
.L17:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $144, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L5
.L18:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $147, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L6
.L19:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $149, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L7
.L20:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $152, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L8
.L21:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $154, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L9
.L22:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $157, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L10
.L23:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $159, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L11
.L24:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $167, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L12
.L25:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $174, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L13
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size ELLmatvecmult, .-ELLmatvecmult
.globl _Z47__device_stub__Z16k_csr_mat_vec_mmPiS_PfiS0_S0_PiS_PfiS0_S0_
.type _Z47__device_stub__Z16k_csr_mat_vec_mmPiS_PfiS0_S0_PiS_PfiS0_S0_, @function
_Z47__device_stub__Z16k_csr_mat_vec_mmPiS_PfiS0_S0_PiS_PfiS0_S0_:
.LFB2083:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16k_csr_mat_vec_mmPiS_PfiS0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z47__device_stub__Z16k_csr_mat_vec_mmPiS_PfiS0_S0_PiS_PfiS0_S0_, .-_Z47__device_stub__Z16k_csr_mat_vec_mmPiS_PfiS0_S0_PiS_PfiS0_S0_
.globl _Z16k_csr_mat_vec_mmPiS_PfiS0_S0_
.type _Z16k_csr_mat_vec_mmPiS_PfiS0_S0_, @function
_Z16k_csr_mat_vec_mmPiS_PfiS0_S0_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z16k_csr_mat_vec_mmPiS_PfiS0_S0_PiS_PfiS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z16k_csr_mat_vec_mmPiS_PfiS0_S0_, .-_Z16k_csr_mat_vec_mmPiS_PfiS0_S0_
.globl _Z48__device_stub__Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_PiS_PfiS0_S0_
.type _Z48__device_stub__Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_PiS_PfiS0_S0_, @function
_Z48__device_stub__Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_PiS_PfiS0_S0_:
.LFB2085:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z48__device_stub__Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_PiS_PfiS0_S0_, .-_Z48__device_stub__Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_PiS_PfiS0_S0_
.globl _Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_
.type _Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_, @function
_Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_PiS_PfiS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_, .-_Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_
.globl CSRmatvecmult
.type CSRmatvecmult, @function
CSRmatvecmult:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rdi, %r13
movq %rsi, 8(%rsp)
movq %rdx, 16(%rsp)
movl %ecx, %r12d
movl %r8d, %ebp
movq %r9, 24(%rsp)
movq 176(%rsp), %r14
movl 184(%rsp), %r15d
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leal 1(%rcx), %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L62
.L44:
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L63
.L45:
movslq %ebp, %rbp
salq $2, %rbp
leaq 48(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L64
.L46:
movl $1, %ecx
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L65
.L47:
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L66
.L48:
movl $1, %ecx
movq %rbp, %rdx
movq 16(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L67
.L49:
subq $4, %rbx
leaq 64(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L68
.L50:
movl $1, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L69
.L51:
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L70
.L52:
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L71
.L53:
testb %r15b, %r15b
je .L54
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leal 511(%r12), %esi
testl %r12d, %r12d
cmovns %r12d, %esi
sarl $9, %esi
movl %esi, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $512, 100(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $512, %ecx
movq 80(%rsp), %rdi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L72
.L56:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L73
.L58:
movl $2, %ecx
movq %rbx, %rdx
movq 72(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L74
.L59:
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L75
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L62:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $69, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L44
.L63:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $71, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L45
.L64:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $74, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L46
.L65:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $76, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L47
.L66:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $79, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L48
.L67:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $81, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L49
.L68:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $84, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L50
.L69:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $86, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L51
.L70:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $89, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L52
.L71:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $91, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L53
.L72:
movq 72(%rsp), %r9
movq 64(%rsp), %r8
movl %r12d, %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z48__device_stub__Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_PiS_PfiS0_S0_
jmp .L56
.L54:
leal 510(%r12), %eax
movl %r12d, %edx
subl $1, %edx
cmovns %edx, %eax
sarl $9, %eax
addl $1, %eax
movl %eax, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $512, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L56
movq 72(%rsp), %r9
movq 64(%rsp), %r8
movl %r12d, %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z47__device_stub__Z16k_csr_mat_vec_mmPiS_PfiS0_S0_PiS_PfiS0_S0_
jmp .L56
.L73:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $110, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L58
.L74:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $117, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L59
.L75:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size CSRmatvecmult, .-CSRmatvecmult
.globl _Z46__device_stub__Z16k_ell_mat_vec_mmiiPiPfS0_S0_iiPiPfS0_S0_
.type _Z46__device_stub__Z16k_ell_mat_vec_mmiiPiPfS0_S0_iiPiPfS0_S0_, @function
_Z46__device_stub__Z16k_ell_mat_vec_mmiiPiPfS0_S0_iiPiPfS0_S0_:
.LFB2087:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L80
.L76:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L81
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L80:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16k_ell_mat_vec_mmiiPiPfS0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L76
.L81:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z46__device_stub__Z16k_ell_mat_vec_mmiiPiPfS0_S0_iiPiPfS0_S0_, .-_Z46__device_stub__Z16k_ell_mat_vec_mmiiPiPfS0_S0_iiPiPfS0_S0_
.globl _Z16k_ell_mat_vec_mmiiPiPfS0_S0_
.type _Z16k_ell_mat_vec_mmiiPiPfS0_S0_, @function
_Z16k_ell_mat_vec_mmiiPiPfS0_S0_:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z16k_ell_mat_vec_mmiiPiPfS0_S0_iiPiPfS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z16k_ell_mat_vec_mmiiPiPfS0_S0_, .-_Z16k_ell_mat_vec_mmiiPiPfS0_S0_
.section .rodata.str1.8
.align 8
.LC2:
.string "_Z16k_ell_mat_vec_mmiiPiPfS0_S0_"
.align 8
.LC3:
.string "_Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_"
.align 8
.LC4:
.string "_Z16k_csr_mat_vec_mmPiS_PfiS0_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z16k_ell_mat_vec_mmiiPiPfS0_S0_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z16k_csr_mat_vec_mmPiS_PfiS0_S0_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernels.hip"
.globl _Z31__device_stub__k_csr_mat_vec_mmPiS_PfiS0_S0_ # -- Begin function _Z31__device_stub__k_csr_mat_vec_mmPiS_PfiS0_S0_
.p2align 4, 0x90
.type _Z31__device_stub__k_csr_mat_vec_mmPiS_PfiS0_S0_,@function
_Z31__device_stub__k_csr_mat_vec_mmPiS_PfiS0_S0_: # @_Z31__device_stub__k_csr_mat_vec_mmPiS_PfiS0_S0_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16k_csr_mat_vec_mmPiS_PfiS0_S0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z31__device_stub__k_csr_mat_vec_mmPiS_PfiS0_S0_, .Lfunc_end0-_Z31__device_stub__k_csr_mat_vec_mmPiS_PfiS0_S0_
.cfi_endproc
# -- End function
.globl _Z32__device_stub__k_csr2_mat_vec_mmPiS_PfiS0_S0_ # -- Begin function _Z32__device_stub__k_csr2_mat_vec_mmPiS_PfiS0_S0_
.p2align 4, 0x90
.type _Z32__device_stub__k_csr2_mat_vec_mmPiS_PfiS0_S0_,@function
_Z32__device_stub__k_csr2_mat_vec_mmPiS_PfiS0_S0_: # @_Z32__device_stub__k_csr2_mat_vec_mmPiS_PfiS0_S0_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z32__device_stub__k_csr2_mat_vec_mmPiS_PfiS0_S0_, .Lfunc_end1-_Z32__device_stub__k_csr2_mat_vec_mmPiS_PfiS0_S0_
.cfi_endproc
# -- End function
.globl _Z31__device_stub__k_ell_mat_vec_mmiiPiPfS0_S0_ # -- Begin function _Z31__device_stub__k_ell_mat_vec_mmiiPiPfS0_S0_
.p2align 4, 0x90
.type _Z31__device_stub__k_ell_mat_vec_mmiiPiPfS0_S0_,@function
_Z31__device_stub__k_ell_mat_vec_mmiiPiPfS0_S0_: # @_Z31__device_stub__k_ell_mat_vec_mmiiPiPfS0_S0_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16k_ell_mat_vec_mmiiPiPfS0_S0_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z31__device_stub__k_ell_mat_vec_mmiiPiPfS0_S0_, .Lfunc_end2-_Z31__device_stub__k_ell_mat_vec_mmiiPiPfS0_S0_
.cfi_endproc
# -- End function
.globl CSRmatvecmult # -- Begin function CSRmatvecmult
.p2align 4, 0x90
.type CSRmatvecmult,@function
CSRmatvecmult: # @CSRmatvecmult
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 208(%rsp) # 8-byte Spill
movl %r8d, %ebp
movl %ecx, %r14d
movq %rdx, 200(%rsp) # 8-byte Spill
movq %rsi, %r13
movq %rdi, %r15
movslq %ecx, %rbx
leaq 4(,%rbx,4), %r12
leaq 48(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
je .LBB3_2
# %bb.1:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $69, %esi
xorl %eax, %eax
callq printf
.LBB3_2:
movq 48(%rsp), %rdi
movq %r15, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB3_4
# %bb.3:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $71, %esi
xorl %eax, %eax
callq printf
.LBB3_4:
movslq %ebp, %rbp
shlq $2, %rbp
leaq 40(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
je .LBB3_6
# %bb.5:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $74, %esi
xorl %eax, %eax
callq printf
.LBB3_6:
movq 40(%rsp), %rdi
movq %r13, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB3_8
# %bb.7:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $76, %esi
xorl %eax, %eax
callq printf
.LBB3_8:
leaq 32(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
je .LBB3_10
# %bb.9:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $79, %esi
xorl %eax, %eax
callq printf
.LBB3_10:
movq 32(%rsp), %rdi
movq 200(%rsp), %rsi # 8-byte Reload
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB3_12
# %bb.11:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $81, %esi
xorl %eax, %eax
callq printf
.LBB3_12:
shlq $2, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
je .LBB3_14
# %bb.13:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $84, %esi
xorl %eax, %eax
callq printf
.LBB3_14:
movq 24(%rsp), %rdi
movq 208(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB3_16
# %bb.15:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $86, %esi
xorl %eax, %eax
callq printf
.LBB3_16:
movq 272(%rsp), %r15
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
je .LBB3_18
# %bb.17:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $89, %esi
xorl %eax, %eax
callq printf
.LBB3_18:
movzbl 280(%rsp), %ebp
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB3_20
# %bb.19:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $91, %esi
xorl %eax, %eax
callq printf
.LBB3_20:
movabsq $4294967297, %rdx # imm = 0x100000001
testb %bpl, %bpl
je .LBB3_23
# %bb.21:
leal 511(%r14), %esi
testl %r14d, %r14d
cmovnsl %r14d, %esi
sarl $9, %esi
movq %rdx, %rdi
movl $512, %ecx # imm = 0x200
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_26
# %bb.22:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl %r14d, 12(%rsp)
movq %rsi, 112(%rsp)
movq %rdi, 104(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 112(%rsp), %rax
movq %rax, 176(%rsp)
leaq 104(%rsp), %rax
movq %rax, 184(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_, %edi
jmp .LBB3_25
.LBB3_23:
leal -1(%r14), %eax
leal 510(%r14), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $9, %ecx
incl %ecx
leaq (%rdx,%rcx), %rdi
decq %rdi
addq $511, %rdx # imm = 0x1FF
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_26
# %bb.24:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl %r14d, 12(%rsp)
movq %rsi, 112(%rsp)
movq %rdi, 104(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 112(%rsp), %rax
movq %rax, 176(%rsp)
leaq 104(%rsp), %rax
movq %rax, 184(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z16k_csr_mat_vec_mmPiS_PfiS0_S0_, %edi
.LBB3_25:
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_26:
callq hipGetLastError
testl %eax, %eax
je .LBB3_28
# %bb.27:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $110, %esi
xorl %eax, %eax
callq printf
.LBB3_28:
movq 16(%rsp), %rsi
movq %r15, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB3_30
# %bb.29:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $117, %esi
xorl %eax, %eax
callq printf
.LBB3_30:
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size CSRmatvecmult, .Lfunc_end3-CSRmatvecmult
.cfi_endproc
# -- End function
.globl ELLmatvecmult # -- Begin function ELLmatvecmult
.p2align 4, 0x90
.type ELLmatvecmult,@function
ELLmatvecmult: # @ELLmatvecmult
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, %r14
movq %rcx, %r15
movq %rdx, %r13
movl %edi, %ebp
imull %edi, %esi
movslq %esi, %r12
shlq $2, %r12
leaq 32(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
je .LBB4_2
# %bb.1:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $142, %esi
xorl %eax, %eax
callq printf
.LBB4_2:
movq 32(%rsp), %rdi
movq %r13, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB4_4
# %bb.3:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $144, %esi
xorl %eax, %eax
callq printf
.LBB4_4:
leaq 24(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
je .LBB4_6
# %bb.5:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $147, %esi
xorl %eax, %eax
callq printf
.LBB4_6:
movq 24(%rsp), %rdi
movq %r15, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB4_8
# %bb.7:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $149, %esi
xorl %eax, %eax
callq printf
.LBB4_8:
movslq %ebp, %r15
shlq $2, %r15
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
je .LBB4_10
# %bb.9:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $152, %esi
xorl %eax, %eax
callq printf
.LBB4_10:
movq 16(%rsp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB4_12
# %bb.11:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $154, %esi
xorl %eax, %eax
callq printf
.LBB4_12:
leaq 8(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
je .LBB4_14
# %bb.13:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $157, %esi
xorl %eax, %eax
callq printf
.LBB4_14:
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB4_16
# %bb.15:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $159, %esi
xorl %eax, %eax
callq printf
.LBB4_16:
callq hipGetLastError
testl %eax, %eax
je .LBB4_18
# %bb.17:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $167, %esi
xorl %eax, %eax
callq printf
.LBB4_18:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB4_20
# %bb.19:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $174, %esi
xorl %eax, %eax
callq printf
.LBB4_20:
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size ELLmatvecmult, .Lfunc_end4-ELLmatvecmult
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16k_csr_mat_vec_mmPiS_PfiS0_S0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16k_ell_mat_vec_mmiiPiPfS0_S0_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16k_csr_mat_vec_mmPiS_PfiS0_S0_,@object # @_Z16k_csr_mat_vec_mmPiS_PfiS0_S0_
.section .rodata,"a",@progbits
.globl _Z16k_csr_mat_vec_mmPiS_PfiS0_S0_
.p2align 3, 0x0
_Z16k_csr_mat_vec_mmPiS_PfiS0_S0_:
.quad _Z31__device_stub__k_csr_mat_vec_mmPiS_PfiS0_S0_
.size _Z16k_csr_mat_vec_mmPiS_PfiS0_S0_, 8
.type _Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_,@object # @_Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_
.globl _Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_
.p2align 3, 0x0
_Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_:
.quad _Z32__device_stub__k_csr2_mat_vec_mmPiS_PfiS0_S0_
.size _Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_, 8
.type _Z16k_ell_mat_vec_mmiiPiPfS0_S0_,@object # @_Z16k_ell_mat_vec_mmiiPiPfS0_S0_
.globl _Z16k_ell_mat_vec_mmiiPiPfS0_S0_
.p2align 3, 0x0
_Z16k_ell_mat_vec_mmiiPiPfS0_S0_:
.quad _Z31__device_stub__k_ell_mat_vec_mmiiPiPfS0_S0_
.size _Z16k_ell_mat_vec_mmiiPiPfS0_S0_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "(CUDA) %s"
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " (/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/PCXDME/CUDA/master/kernels.hip:%d)\n"
.size .L.str.1, 95
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16k_csr_mat_vec_mmPiS_PfiS0_S0_"
.size .L__unnamed_1, 34
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_"
.size .L__unnamed_2, 35
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z16k_ell_mat_vec_mmiiPiPfS0_S0_"
.size .L__unnamed_3, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__k_csr_mat_vec_mmPiS_PfiS0_S0_
.addrsig_sym _Z32__device_stub__k_csr2_mat_vec_mmPiS_PfiS0_S0_
.addrsig_sym _Z31__device_stub__k_ell_mat_vec_mmiiPiPfS0_S0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16k_csr_mat_vec_mmPiS_PfiS0_S0_
.addrsig_sym _Z17k_csr2_mat_vec_mmPiS_PfiS0_S0_
.addrsig_sym _Z16k_ell_mat_vec_mmiiPiPfS0_S0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <ctime>
// Includes CUDA
#include <cuda_runtime.h>
#define LINEWIDTH 20
#define NWORDS 32
#define CUDA_STREAMS 1
#define BLOCK_SIZE 32
#define TITLE_SIZE 4
int length;
int len;
int nwords;
int matches[NWORDS];
char *ctext;
char keywords[NWORDS][LINEWIDTH];
unsigned int *text;
unsigned int *words;
float cpuRunTime;
// citation: https://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
#define checkCudaErrors(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
void intialise(char *input)
{
nwords = NWORDS;
printf("-----------\nGoint to read %s\n", input);
char *line;
line = (char*) malloc(sizeof(char)*LINEWIDTH);
memset(matches, 0, sizeof(matches));
// read in text and keywords for processing
FILE *fp, *wfile;
wfile = fopen("./data/keywords.txt","r");
if (!wfile)
{ printf("keywords.txt: File not found.\n"); exit(0);}
int k=0, cnt = nwords;
size_t read, linelen = LINEWIDTH;
while((read = getline(&line, &linelen, wfile)) != -1 && cnt--)
{
strncpy(keywords[k], line, sizeof(line));
keywords[k][4] = '\0';
k++;
}
fclose(wfile);
fp = fopen(input,"r");
if (!fp)
{ printf("Unable to open the file.\n"); exit(0);}
length = 0;
while (getc(fp) != EOF) length++;
ctext = (char *)malloc(length+4);
rewind(fp);
for (int l=0; l<length; l++) ctext[l] = getc(fp);
for (int l=length; l<length+4; l++) ctext[l] = ' ';
fclose(fp);
printf("Length : %d\n", length );
// define number of words of text, and set pointers
len = length/4;
text = (unsigned int *) ctext;
// define words for matching
words = (unsigned int *)malloc(nwords*sizeof(unsigned int));
for (int w=0; w<nwords; w++)
{
words[w] = ((unsigned int) keywords[w][0])
+ ((unsigned int) keywords[w][1])*(1<<8)
+ ((unsigned int) keywords[w][2])*(1<<16)
+ ((unsigned int) keywords[w][3])*(1<<24);
}
}
void deinit(){
free(words);
free(text);
}
void check_matches(int *temp_matches){
bool isRight = true;
for(int i = 0; i<nwords; i++) {
if(matches[i] != temp_matches[i]) {
isRight = false;
printf("WRONG OUTPUT:\t %s\t|\t%d\n", keywords[i], temp_matches[i]);
}
}
if(isRight) {
printf(" - Correct Answer -\n");
}
}
void print_matches(int *temp_matches){
printf("Printing Matches:\n");
printf("Word\t |\tNumber of Matches\n===================================\n");
for (int i = 0; i < nwords; ++i)
printf("%s\t |\t%d\n", keywords[i], temp_matches[i]);
}
void matchPattern_CPU(unsigned int *text, unsigned int *words, int *matches, int nwords, int length)
{
unsigned int word;
for (int l=0; l<length; l++)
{
for (int offset=0; offset<4; offset++)
{
if (offset==0)
word = text[l];
else
word = (text[l]>>(8*offset)) + (text[l+1]<<(32-8*offset));
for (int w=0; w<nwords; w++){
matches[w] += (word==words[w]);
}
}
}
}
void exec_CPU(){
// CPU execution
const clock_t begin_time = clock();
matchPattern_CPU(text, words, matches, nwords, len);
cpuRunTime = (float)( clock() - begin_time ) / CLOCKS_PER_SEC;
printf("CPU exec time: %f s\n\n", cpuRunTime);
}
__global__ void matchPattern_gpu_1(const unsigned int *text, const unsigned int *words, int *matches, int nwords, int length)
{
int tid = threadIdx.x;
int idx = blockIdx.x * blockDim.x + tid;
// for loading text into the shared memory
__shared__ unsigned int text_s[(TITLE_SIZE*NWORDS) + TITLE_SIZE];
#pragma unroll
for(int x = 0; x<TITLE_SIZE; x++){
text_s[tid + (x*NWORDS) + x] = text[idx+(x*blockDim.x*gridDim.x)];
text_s[((x+1)*NWORDS) + x] = text[(x*blockDim.x*gridDim.x) + (blockIdx.x * blockDim.x) + blockDim.x];
}
// loads the keyword for this thread
// each thread in a block is reponsible for one keyword
unsigned int keyword = words[tid];
__syncthreads();
unsigned int word;
int sum = 0;
// go through all the words in the shared memory
#pragma unroll
for(int x = 0; x<TITLE_SIZE; x ++) {
#pragma unroll
for(int w = (x*NWORDS) + x; w < ((x+1)*NWORDS) + (x); w++) {
#pragma unroll
for (int offset=0; offset<4; offset++)
{
word = offset==0 ? text_s[w] : (text_s[w]>>(8*offset)) + (text_s[w+1]<<(32-8*offset));
sum = sum + (word==keyword);
}
}
}
atomicAdd(&matches[tid],sum);
}
void exec_gpu_simple(){
// GPU execution
unsigned int *d_text; unsigned int *d_words; int *d_matches;
int *h_matches;
h_matches = (int *)malloc(nwords*sizeof(int));
checkCudaErrors(cudaMalloc((void**)&d_words, nwords*sizeof(unsigned int)));
checkCudaErrors(cudaMalloc((void**)&d_matches, nwords*sizeof(int)));
checkCudaErrors(cudaMalloc((void**)&d_text, sizeof(char)*strlen(ctext)));
cudaEvent_t start,stop;
float time_H2D,time_D2H,time_kernel;
checkCudaErrors(cudaEventCreate(&start));
checkCudaErrors(cudaEventCreate(&stop));
// MEMCOPY
cudaEventRecord(start, 0);
checkCudaErrors(cudaMemcpy(d_words, words, nwords*sizeof(unsigned int), cudaMemcpyHostToDevice));
checkCudaErrors(cudaMemcpy(d_text, text, sizeof(char)*strlen(ctext), cudaMemcpyHostToDevice));
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time_H2D,start,stop);
printf("HostToDevice memcopy time: %fs\n", time_H2D/1000);
// RUN KERNEL
cudaEventRecord(start, 0);
matchPattern_gpu_1<<< ceil((float)len/(TITLE_SIZE*NWORDS)),NWORDS>>>(d_text, d_words, d_matches, nwords, len);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
checkCudaErrors(cudaPeekAtLastError());
cudaEventElapsedTime(&time_kernel,start,stop);
printf("Kernel execution time: %fs\n", time_kernel/1000);
cudaEventRecord(start, 0);
checkCudaErrors(cudaMemcpy(h_matches, d_matches, nwords*sizeof(int), cudaMemcpyDeviceToHost));
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time_D2H,start,stop);
printf("DeviceToHost memcopy time: %fs\n", time_D2H/1000);
printf("Total memcopy time: %fs\n", (time_D2H+time_H2D)/1000);
printf("Total memcopy+kernel time: %fs\n", (time_D2H+time_H2D+time_kernel)/1000);
printf("Speedup without memory: %f\n", cpuRunTime/((time_kernel)/1000));
printf("Speedup with memory: %f\n", cpuRunTime/((time_D2H + time_H2D + time_kernel)/1000));
check_matches(h_matches);
cudaEventDestroy(start);
cudaEventDestroy(stop);
free(h_matches);
cudaFree(d_words);
cudaFree(d_matches);
cudaFree(d_text);
}
int main(int argc, const char **argv)
{
intialise("./data/small.txt");
exec_CPU();
exec_gpu_simple();
intialise("./data/medium.txt");
exec_CPU();
exec_gpu_simple();
intialise("./data/large.txt");
exec_CPU();
exec_gpu_simple();
deinit();
} | .file "tmpxft_001727cc_00000000-6_pattern_tiling.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2068:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "-----------\nGoint to read %s\n"
.LC1:
.string "r"
.LC2:
.string "./data/keywords.txt"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "keywords.txt: File not found.\n"
.section .rodata.str1.1
.LC4:
.string "Unable to open the file.\n"
.LC5:
.string "Length : %d\n"
.text
.globl _Z9intialisePc
.type _Z9intialisePc, @function
_Z9intialisePc:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r15
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $32, nwords(%rip)
movq %rdi, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $20, %edi
call malloc@PLT
movq %rax, 8(%rsp)
leaq matches(%rip), %rdx
movl $16, %ecx
movl $0, %eax
movq %rdx, %rdi
rep stosq
leaq .LC1(%rip), %rsi
leaq .LC2(%rip), %rdi
call fopen@PLT
testq %rax, %rax
je .L21
movq %rax, %r12
movq $20, 16(%rsp)
leaq keywords(%rip), %rbx
movl nwords(%rip), %eax
leaq (%rax,%rax,4), %rax
leaq (%rbx,%rax,4), %r14
movq %rbx, %rbp
leaq 16(%rsp), %r13
.L6:
leaq 8(%rsp), %rdi
movq %r12, %rcx
movl $10, %edx
movq %r13, %rsi
call __getdelim@PLT
cmpq $-1, %rax
je .L5
cmpq %r14, %rbp
je .L5
movq %rbp, %rcx
subq %rbx, %rcx
movl $640, %eax
cmpq %rax, %rcx
cmovb %rax, %rcx
movq %rbx, %rax
subq %rbp, %rax
addq %rax, %rcx
movl $8, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call __strncpy_chk@PLT
movb $0, 4(%rbp)
addq $20, %rbp
jmp .L6
.L21:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L5:
movq %r12, %rdi
call fclose@PLT
leaq .LC1(%rip), %rsi
movq %r15, %rdi
call fopen@PLT
movq %rax, %r12
testq %rax, %rax
je .L22
movl $0, %eax
jmp .L7
.L22:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L8:
movl length(%rip), %eax
addl $1, %eax
.L7:
movl %eax, length(%rip)
movq %r12, %rdi
call getc@PLT
cmpl $-1, %eax
jne .L8
movl length(%rip), %eax
leal 4(%rax), %edi
movslq %edi, %rdi
call malloc@PLT
movq %rax, ctext(%rip)
movq %r12, %rdi
call rewind@PLT
movl length(%rip), %edx
testl %edx, %edx
jle .L9
movl $0, %ebp
.L10:
movq %r12, %rdi
call getc@PLT
movq ctext(%rip), %rdx
movb %al, (%rdx,%rbp)
movl length(%rip), %edx
addq $1, %rbp
cmpl %ebp, %edx
jg .L10
.L9:
movl length(%rip), %eax
addl $3, %eax
cmpl %edx, %eax
jl .L11
movslq %edx, %rsi
movq %rsi, %rax
subl %esi, %edx
movl %edx, %ecx
.L12:
movq ctext(%rip), %rdx
movb $32, (%rdx,%rax)
addq $1, %rax
movl length(%rip), %esi
leal 3(%rsi), %edx
leal (%rcx,%rax), %esi
cmpl %esi, %edx
jge .L12
.L11:
movq %r12, %rdi
call fclose@PLT
movl length(%rip), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl length(%rip), %edx
leal 3(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $2, %eax
movl %eax, len(%rip)
movq ctext(%rip), %rax
movq %rax, text(%rip)
movl nwords(%rip), %ebp
movslq %ebp, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, words(%rip)
testl %ebp, %ebp
jle .L3
movl $0, %edx
.L14:
movsbl 3(%rbx), %eax
sall $8, %eax
movsbl 2(%rbx), %ecx
addl %ecx, %eax
sall $8, %eax
movsbl 1(%rbx), %ecx
addl %ecx, %eax
sall $8, %eax
movsbl (%rbx), %ecx
addl %ecx, %eax
movq words(%rip), %rcx
movl %eax, (%rcx,%rdx,4)
addq $1, %rdx
addq $20, %rbx
cmpl %edx, nwords(%rip)
jg .L14
.L3:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z9intialisePc, .-_Z9intialisePc
.globl _Z6deinitv
.type _Z6deinitv, @function
_Z6deinitv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq words(%rip), %rdi
call free@PLT
movq text(%rip), %rdi
call free@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z6deinitv, .-_Z6deinitv
.section .rodata.str1.1
.LC6:
.string "WRONG OUTPUT:\t %s\t|\t%d\n"
.LC7:
.string " - Correct Answer -\n"
.text
.globl _Z13check_matchesPi
.type _Z13check_matchesPi, @function
_Z13check_matchesPi:
.LFB2060:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
cmpl $0, nwords(%rip)
jle .L27
movq %rdi, %r12
leaq keywords(%rip), %rbp
movl $0, %ebx
movl $1, %eax
leaq matches(%rip), %r13
leaq .LC6(%rip), %r14
jmp .L29
.L28:
addq $1, %rbx
addq $20, %rbp
cmpl %ebx, nwords(%rip)
jle .L33
.L29:
movl (%r12,%rbx,4), %ecx
cmpl %ecx, 0(%r13,%rbx,4)
je .L28
movq %rbp, %rdx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L28
.L33:
testb %al, %al
jne .L27
.L26:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L26
.cfi_endproc
.LFE2060:
.size _Z13check_matchesPi, .-_Z13check_matchesPi
.section .rodata.str1.1
.LC8:
.string "Printing Matches:\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "Word\t |\tNumber of Matches\n===================================\n"
.section .rodata.str1.1
.LC10:
.string "%s\t |\t%d\n"
.text
.globl _Z13print_matchesPi
.type _Z13print_matchesPi, @function
_Z13print_matchesPi:
.LFB2061:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, nwords(%rip)
jle .L34
movl $0, %ebx
leaq keywords(%rip), %r13
leaq .LC10(%rip), %r12
.L36:
movl 0(%rbp,%rbx,4), %ecx
leaq (%rbx,%rbx,4), %rax
leaq 0(%r13,%rax,4), %rdx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, nwords(%rip)
jg .L36
.L34:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z13print_matchesPi, .-_Z13print_matchesPi
.globl _Z16matchPattern_CPUPjS_Piii
.type _Z16matchPattern_CPUPjS_Piii, @function
_Z16matchPattern_CPUPjS_Piii:
.LFB2062:
.cfi_startproc
endbr64
testl %r8d, %r8d
jle .L52
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rsi, %r9
movl %ecx, %r11d
movq %rdi, %r10
movslq %r8d, %r8
leaq (%rdi,%r8,4), %rbx
movslq %ecx, %rdi
salq $2, %rdi
jmp .L41
.L57:
movl (%r10), %esi
testl %r11d, %r11d
jle .L55
.L43:
movl $0, %eax
.L46:
cmpl %esi, (%r9,%rax)
sete %cl
movzbl %cl, %ecx
addl %ecx, (%rdx,%rax)
addq $4, %rax
cmpq %rdi, %rax
jne .L46
.L45:
addl $1, %r8d
cmpl $4, %r8d
je .L56
.L48:
testl %r8d, %r8d
je .L57
movl %r8d, %eax
negl %eax
leal 32(,%rax,8), %ecx
movl 4(%r10), %esi
sall %cl, %esi
leal 0(,%r8,8), %ecx
movl (%r10), %eax
shrl %cl, %eax
addl %eax, %esi
testl %r11d, %r11d
jg .L43
jmp .L45
.L56:
addq $4, %r10
cmpq %rbx, %r10
je .L39
.L41:
movl $0, %r8d
jmp .L48
.L55:
addl $1, %r8d
jmp .L48
.L39:
popq %rbx
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore 3
ret
.cfi_endproc
.LFE2062:
.size _Z16matchPattern_CPUPjS_Piii, .-_Z16matchPattern_CPUPjS_Piii
.section .rodata.str1.1
.LC12:
.string "CPU exec time: %f s\n\n"
.text
.globl _Z8exec_CPUv
.type _Z8exec_CPUv, @function
_Z8exec_CPUv:
.LFB2063:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
call clock@PLT
movq %rax, %rbx
movl len(%rip), %r8d
movl nwords(%rip), %ecx
leaq matches(%rip), %rdx
movq words(%rip), %rsi
movq text(%rip), %rdi
call _Z16matchPattern_CPUPjS_Piii
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC11(%rip), %xmm0
movss %xmm0, cpuRunTime(%rip)
cvtss2sd %xmm0, %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _Z8exec_CPUv, .-_Z8exec_CPUv
.globl _Z46__device_stub__Z18matchPattern_gpu_1PKjS0_PiiiPKjS0_Piii
.type _Z46__device_stub__Z18matchPattern_gpu_1PKjS0_PiiiPKjS0_Piii, @function
_Z46__device_stub__Z18matchPattern_gpu_1PKjS0_PiiiPKjS0_Piii:
.LFB2090:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L64
.L60:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L65
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L64:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18matchPattern_gpu_1PKjS0_Piii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L60
.L65:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z46__device_stub__Z18matchPattern_gpu_1PKjS0_PiiiPKjS0_Piii, .-_Z46__device_stub__Z18matchPattern_gpu_1PKjS0_PiiiPKjS0_Piii
.globl _Z18matchPattern_gpu_1PKjS0_Piii
.type _Z18matchPattern_gpu_1PKjS0_Piii, @function
_Z18matchPattern_gpu_1PKjS0_Piii:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z18matchPattern_gpu_1PKjS0_PiiiPKjS0_Piii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z18matchPattern_gpu_1PKjS0_Piii, .-_Z18matchPattern_gpu_1PKjS0_Piii
.section .rodata.str1.8
.align 8
.LC13:
.string "/home/ubuntu/Datasets/stackv2/train-structured/sedflix/cuda_pattern_matching/master/pattern_tiling.cu"
.section .rodata.str1.1
.LC14:
.string "GPUassert: %s %s %d\n"
.section .rodata.str1.8
.align 8
.LC16:
.string "HostToDevice memcopy time: %fs\n"
.section .rodata.str1.1
.LC21:
.string "Kernel execution time: %fs\n"
.section .rodata.str1.8
.align 8
.LC22:
.string "DeviceToHost memcopy time: %fs\n"
.section .rodata.str1.1
.LC23:
.string "Total memcopy time: %fs\n"
.section .rodata.str1.8
.align 8
.LC24:
.string "Total memcopy+kernel time: %fs\n"
.section .rodata.str1.1
.LC25:
.string "Speedup without memory: %f\n"
.LC26:
.string "Speedup with memory: %f\n"
.text
.globl _Z15exec_gpu_simplev
.type _Z15exec_gpu_simplev, @function
_Z15exec_gpu_simplev:
.LFB2064:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movslq nwords(%rip), %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L82
movslq nwords(%rip), %rsi
salq $2, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L83
movq ctext(%rip), %rdi
call strlen@PLT
movq %rax, %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L84
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L85
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L86
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movslq nwords(%rip), %rdx
salq $2, %rdx
movl $1, %ecx
movq words(%rip), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L87
movq ctext(%rip), %rdi
call strlen@PLT
movq %rax, %rdx
movl $1, %ecx
movq text(%rip), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L88
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 4(%rsp), %xmm0
divss .LC15(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $32, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl len(%rip), %xmm0
mulss .LC17(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC27(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC18(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L76
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC20(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L76:
cvttss2siq %xmm3, %rax
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L89
.L77:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
call cudaPeekAtLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L90
leaq 60(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 60(%rsp), %xmm0
divss .LC15(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movslq nwords(%rip), %rdx
salq $2, %rdx
movl $2, %ecx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L91
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 48(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 48(%rsp), %xmm0
divss .LC15(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 48(%rsp), %xmm0
addss 4(%rsp), %xmm0
divss .LC15(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 48(%rsp), %xmm0
addss 4(%rsp), %xmm0
addss 60(%rsp), %xmm0
divss .LC15(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 60(%rsp), %xmm1
divss .LC15(%rip), %xmm1
movss cpuRunTime(%rip), %xmm0
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 48(%rsp), %xmm1
addss 4(%rsp), %xmm1
addss 60(%rsp), %xmm1
divss .LC15(%rip), %xmm1
movss cpuRunTime(%rip), %xmm0
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call _Z13check_matchesPi
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq %rbp, %rdi
call free@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L92
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L82:
.cfi_restore_state
movl %eax, %ebx
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $200, %r9d
leaq .LC13(%rip), %r8
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L83:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $201, %r9d
leaq .LC13(%rip), %r8
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L84:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $202, %r9d
leaq .LC13(%rip), %r8
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L85:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $206, %r9d
leaq .LC13(%rip), %r8
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L86:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $207, %r9d
leaq .LC13(%rip), %r8
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L87:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $212, %r9d
leaq .LC13(%rip), %r8
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L88:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $213, %r9d
leaq .LC13(%rip), %r8
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L89:
movl len(%rip), %r8d
movl nwords(%rip), %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z46__device_stub__Z18matchPattern_gpu_1PKjS0_PiiiPKjS0_Piii
jmp .L77
.L90:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $224, %r9d
leaq .LC13(%rip), %r8
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L91:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $229, %r9d
leaq .LC13(%rip), %r8
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L92:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2064:
.size _Z15exec_gpu_simplev, .-_Z15exec_gpu_simplev
.section .rodata.str1.1
.LC28:
.string "./data/small.txt"
.LC29:
.string "./data/medium.txt"
.LC30:
.string "./data/large.txt"
.text
.globl main
.type main, @function
main:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC28(%rip), %rdi
call _Z9intialisePc
call _Z8exec_CPUv
call _Z15exec_gpu_simplev
leaq .LC29(%rip), %rdi
call _Z9intialisePc
call _Z8exec_CPUv
call _Z15exec_gpu_simplev
leaq .LC30(%rip), %rdi
call _Z9intialisePc
call _Z8exec_CPUv
call _Z15exec_gpu_simplev
call _Z6deinitv
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC31:
.string "_Z18matchPattern_gpu_1PKjS0_Piii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC31(%rip), %rdx
movq %rdx, %rcx
leaq _Z18matchPattern_gpu_1PKjS0_Piii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl cpuRunTime
.bss
.align 4
.type cpuRunTime, @object
.size cpuRunTime, 4
cpuRunTime:
.zero 4
.globl words
.align 8
.type words, @object
.size words, 8
words:
.zero 8
.globl text
.align 8
.type text, @object
.size text, 8
text:
.zero 8
.globl keywords
.align 32
.type keywords, @object
.size keywords, 640
keywords:
.zero 640
.globl ctext
.align 8
.type ctext, @object
.size ctext, 8
ctext:
.zero 8
.globl matches
.align 32
.type matches, @object
.size matches, 128
matches:
.zero 128
.globl nwords
.align 4
.type nwords, @object
.size nwords, 4
nwords:
.zero 4
.globl len
.align 4
.type len, @object
.size len, 4
len:
.zero 4
.globl length
.align 4
.type length, @object
.size length, 4
length:
.zero 4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC11:
.long 1232348160
.align 4
.LC15:
.long 1148846080
.align 4
.LC17:
.long 1006632960
.align 4
.LC18:
.long 1258291200
.align 4
.LC20:
.long 1065353216
.align 4
.LC27:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <ctime>
// Includes CUDA
#include <cuda_runtime.h>
#define LINEWIDTH 20
#define NWORDS 32
#define CUDA_STREAMS 1
#define BLOCK_SIZE 32
#define TITLE_SIZE 4
int length;
int len;
int nwords;
int matches[NWORDS];
char *ctext;
char keywords[NWORDS][LINEWIDTH];
unsigned int *text;
unsigned int *words;
float cpuRunTime;
// citation: https://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
#define checkCudaErrors(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
void intialise(char *input)
{
nwords = NWORDS;
printf("-----------\nGoint to read %s\n", input);
char *line;
line = (char*) malloc(sizeof(char)*LINEWIDTH);
memset(matches, 0, sizeof(matches));
// read in text and keywords for processing
FILE *fp, *wfile;
wfile = fopen("./data/keywords.txt","r");
if (!wfile)
{ printf("keywords.txt: File not found.\n"); exit(0);}
int k=0, cnt = nwords;
size_t read, linelen = LINEWIDTH;
while((read = getline(&line, &linelen, wfile)) != -1 && cnt--)
{
strncpy(keywords[k], line, sizeof(line));
keywords[k][4] = '\0';
k++;
}
fclose(wfile);
fp = fopen(input,"r");
if (!fp)
{ printf("Unable to open the file.\n"); exit(0);}
length = 0;
while (getc(fp) != EOF) length++;
ctext = (char *)malloc(length+4);
rewind(fp);
for (int l=0; l<length; l++) ctext[l] = getc(fp);
for (int l=length; l<length+4; l++) ctext[l] = ' ';
fclose(fp);
printf("Length : %d\n", length );
// define number of words of text, and set pointers
len = length/4;
text = (unsigned int *) ctext;
// define words for matching
words = (unsigned int *)malloc(nwords*sizeof(unsigned int));
for (int w=0; w<nwords; w++)
{
words[w] = ((unsigned int) keywords[w][0])
+ ((unsigned int) keywords[w][1])*(1<<8)
+ ((unsigned int) keywords[w][2])*(1<<16)
+ ((unsigned int) keywords[w][3])*(1<<24);
}
}
void deinit(){
free(words);
free(text);
}
void check_matches(int *temp_matches){
bool isRight = true;
for(int i = 0; i<nwords; i++) {
if(matches[i] != temp_matches[i]) {
isRight = false;
printf("WRONG OUTPUT:\t %s\t|\t%d\n", keywords[i], temp_matches[i]);
}
}
if(isRight) {
printf(" - Correct Answer -\n");
}
}
void print_matches(int *temp_matches){
printf("Printing Matches:\n");
printf("Word\t |\tNumber of Matches\n===================================\n");
for (int i = 0; i < nwords; ++i)
printf("%s\t |\t%d\n", keywords[i], temp_matches[i]);
}
void matchPattern_CPU(unsigned int *text, unsigned int *words, int *matches, int nwords, int length)
{
unsigned int word;
for (int l=0; l<length; l++)
{
for (int offset=0; offset<4; offset++)
{
if (offset==0)
word = text[l];
else
word = (text[l]>>(8*offset)) + (text[l+1]<<(32-8*offset));
for (int w=0; w<nwords; w++){
matches[w] += (word==words[w]);
}
}
}
}
void exec_CPU(){
// CPU execution
const clock_t begin_time = clock();
matchPattern_CPU(text, words, matches, nwords, len);
cpuRunTime = (float)( clock() - begin_time ) / CLOCKS_PER_SEC;
printf("CPU exec time: %f s\n\n", cpuRunTime);
}
__global__ void matchPattern_gpu_1(const unsigned int *text, const unsigned int *words, int *matches, int nwords, int length)
{
int tid = threadIdx.x;
int idx = blockIdx.x * blockDim.x + tid;
// for loading text into the shared memory
__shared__ unsigned int text_s[(TITLE_SIZE*NWORDS) + TITLE_SIZE];
#pragma unroll
for(int x = 0; x<TITLE_SIZE; x++){
text_s[tid + (x*NWORDS) + x] = text[idx+(x*blockDim.x*gridDim.x)];
text_s[((x+1)*NWORDS) + x] = text[(x*blockDim.x*gridDim.x) + (blockIdx.x * blockDim.x) + blockDim.x];
}
// loads the keyword for this thread
// each thread in a block is reponsible for one keyword
unsigned int keyword = words[tid];
__syncthreads();
unsigned int word;
int sum = 0;
// go through all the words in the shared memory
#pragma unroll
for(int x = 0; x<TITLE_SIZE; x ++) {
#pragma unroll
for(int w = (x*NWORDS) + x; w < ((x+1)*NWORDS) + (x); w++) {
#pragma unroll
for (int offset=0; offset<4; offset++)
{
word = offset==0 ? text_s[w] : (text_s[w]>>(8*offset)) + (text_s[w+1]<<(32-8*offset));
sum = sum + (word==keyword);
}
}
}
atomicAdd(&matches[tid],sum);
}
void exec_gpu_simple(){
// GPU execution
unsigned int *d_text; unsigned int *d_words; int *d_matches;
int *h_matches;
h_matches = (int *)malloc(nwords*sizeof(int));
checkCudaErrors(cudaMalloc((void**)&d_words, nwords*sizeof(unsigned int)));
checkCudaErrors(cudaMalloc((void**)&d_matches, nwords*sizeof(int)));
checkCudaErrors(cudaMalloc((void**)&d_text, sizeof(char)*strlen(ctext)));
cudaEvent_t start,stop;
float time_H2D,time_D2H,time_kernel;
checkCudaErrors(cudaEventCreate(&start));
checkCudaErrors(cudaEventCreate(&stop));
// MEMCOPY
cudaEventRecord(start, 0);
checkCudaErrors(cudaMemcpy(d_words, words, nwords*sizeof(unsigned int), cudaMemcpyHostToDevice));
checkCudaErrors(cudaMemcpy(d_text, text, sizeof(char)*strlen(ctext), cudaMemcpyHostToDevice));
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time_H2D,start,stop);
printf("HostToDevice memcopy time: %fs\n", time_H2D/1000);
// RUN KERNEL
cudaEventRecord(start, 0);
matchPattern_gpu_1<<< ceil((float)len/(TITLE_SIZE*NWORDS)),NWORDS>>>(d_text, d_words, d_matches, nwords, len);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
checkCudaErrors(cudaPeekAtLastError());
cudaEventElapsedTime(&time_kernel,start,stop);
printf("Kernel execution time: %fs\n", time_kernel/1000);
cudaEventRecord(start, 0);
checkCudaErrors(cudaMemcpy(h_matches, d_matches, nwords*sizeof(int), cudaMemcpyDeviceToHost));
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time_D2H,start,stop);
printf("DeviceToHost memcopy time: %fs\n", time_D2H/1000);
printf("Total memcopy time: %fs\n", (time_D2H+time_H2D)/1000);
printf("Total memcopy+kernel time: %fs\n", (time_D2H+time_H2D+time_kernel)/1000);
printf("Speedup without memory: %f\n", cpuRunTime/((time_kernel)/1000));
printf("Speedup with memory: %f\n", cpuRunTime/((time_D2H + time_H2D + time_kernel)/1000));
check_matches(h_matches);
cudaEventDestroy(start);
cudaEventDestroy(stop);
free(h_matches);
cudaFree(d_words);
cudaFree(d_matches);
cudaFree(d_text);
}
int main(int argc, const char **argv)
{
intialise("./data/small.txt");
exec_CPU();
exec_gpu_simple();
intialise("./data/medium.txt");
exec_CPU();
exec_gpu_simple();
intialise("./data/large.txt");
exec_CPU();
exec_gpu_simple();
deinit();
} | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <ctime>
// Includes CUDA
#include <hip/hip_runtime.h>
#define LINEWIDTH 20
#define NWORDS 32
#define CUDA_STREAMS 1
#define BLOCK_SIZE 32
#define TITLE_SIZE 4
int length;
int len;
int nwords;
int matches[NWORDS];
char *ctext;
char keywords[NWORDS][LINEWIDTH];
unsigned int *text;
unsigned int *words;
float cpuRunTime;
// citation: https://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
#define checkCudaErrors(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
void intialise(char *input)
{
nwords = NWORDS;
printf("-----------\nGoint to read %s\n", input);
char *line;
line = (char*) malloc(sizeof(char)*LINEWIDTH);
memset(matches, 0, sizeof(matches));
// read in text and keywords for processing
FILE *fp, *wfile;
wfile = fopen("./data/keywords.txt","r");
if (!wfile)
{ printf("keywords.txt: File not found.\n"); exit(0);}
int k=0, cnt = nwords;
size_t read, linelen = LINEWIDTH;
while((read = getline(&line, &linelen, wfile)) != -1 && cnt--)
{
strncpy(keywords[k], line, sizeof(line));
keywords[k][4] = '\0';
k++;
}
fclose(wfile);
fp = fopen(input,"r");
if (!fp)
{ printf("Unable to open the file.\n"); exit(0);}
length = 0;
while (getc(fp) != EOF) length++;
ctext = (char *)malloc(length+4);
rewind(fp);
for (int l=0; l<length; l++) ctext[l] = getc(fp);
for (int l=length; l<length+4; l++) ctext[l] = ' ';
fclose(fp);
printf("Length : %d\n", length );
// define number of words of text, and set pointers
len = length/4;
text = (unsigned int *) ctext;
// define words for matching
words = (unsigned int *)malloc(nwords*sizeof(unsigned int));
for (int w=0; w<nwords; w++)
{
words[w] = ((unsigned int) keywords[w][0])
+ ((unsigned int) keywords[w][1])*(1<<8)
+ ((unsigned int) keywords[w][2])*(1<<16)
+ ((unsigned int) keywords[w][3])*(1<<24);
}
}
void deinit(){
free(words);
free(text);
}
void check_matches(int *temp_matches){
bool isRight = true;
for(int i = 0; i<nwords; i++) {
if(matches[i] != temp_matches[i]) {
isRight = false;
printf("WRONG OUTPUT:\t %s\t|\t%d\n", keywords[i], temp_matches[i]);
}
}
if(isRight) {
printf(" - Correct Answer -\n");
}
}
void print_matches(int *temp_matches){
printf("Printing Matches:\n");
printf("Word\t |\tNumber of Matches\n===================================\n");
for (int i = 0; i < nwords; ++i)
printf("%s\t |\t%d\n", keywords[i], temp_matches[i]);
}
void matchPattern_CPU(unsigned int *text, unsigned int *words, int *matches, int nwords, int length)
{
unsigned int word;
for (int l=0; l<length; l++)
{
for (int offset=0; offset<4; offset++)
{
if (offset==0)
word = text[l];
else
word = (text[l]>>(8*offset)) + (text[l+1]<<(32-8*offset));
for (int w=0; w<nwords; w++){
matches[w] += (word==words[w]);
}
}
}
}
void exec_CPU(){
// CPU execution
const clock_t begin_time = clock();
matchPattern_CPU(text, words, matches, nwords, len);
cpuRunTime = (float)( clock() - begin_time ) / CLOCKS_PER_SEC;
printf("CPU exec time: %f s\n\n", cpuRunTime);
}
__global__ void matchPattern_gpu_1(const unsigned int *text, const unsigned int *words, int *matches, int nwords, int length)
{
int tid = threadIdx.x;
int idx = blockIdx.x * blockDim.x + tid;
// for loading text into the shared memory
__shared__ unsigned int text_s[(TITLE_SIZE*NWORDS) + TITLE_SIZE];
#pragma unroll
for(int x = 0; x<TITLE_SIZE; x++){
text_s[tid + (x*NWORDS) + x] = text[idx+(x*blockDim.x*gridDim.x)];
text_s[((x+1)*NWORDS) + x] = text[(x*blockDim.x*gridDim.x) + (blockIdx.x * blockDim.x) + blockDim.x];
}
// loads the keyword for this thread
// each thread in a block is reponsible for one keyword
unsigned int keyword = words[tid];
__syncthreads();
unsigned int word;
int sum = 0;
// go through all the words in the shared memory
#pragma unroll
for(int x = 0; x<TITLE_SIZE; x ++) {
#pragma unroll
for(int w = (x*NWORDS) + x; w < ((x+1)*NWORDS) + (x); w++) {
#pragma unroll
for (int offset=0; offset<4; offset++)
{
word = offset==0 ? text_s[w] : (text_s[w]>>(8*offset)) + (text_s[w+1]<<(32-8*offset));
sum = sum + (word==keyword);
}
}
}
atomicAdd(&matches[tid],sum);
}
void exec_gpu_simple(){
// GPU execution
unsigned int *d_text; unsigned int *d_words; int *d_matches;
int *h_matches;
h_matches = (int *)malloc(nwords*sizeof(int));
checkCudaErrors(hipMalloc((void**)&d_words, nwords*sizeof(unsigned int)));
checkCudaErrors(hipMalloc((void**)&d_matches, nwords*sizeof(int)));
checkCudaErrors(hipMalloc((void**)&d_text, sizeof(char)*strlen(ctext)));
hipEvent_t start,stop;
float time_H2D,time_D2H,time_kernel;
checkCudaErrors(hipEventCreate(&start));
checkCudaErrors(hipEventCreate(&stop));
// MEMCOPY
hipEventRecord(start, 0);
checkCudaErrors(hipMemcpy(d_words, words, nwords*sizeof(unsigned int), hipMemcpyHostToDevice));
checkCudaErrors(hipMemcpy(d_text, text, sizeof(char)*strlen(ctext), hipMemcpyHostToDevice));
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time_H2D,start,stop);
printf("HostToDevice memcopy time: %fs\n", time_H2D/1000);
// RUN KERNEL
hipEventRecord(start, 0);
matchPattern_gpu_1<<< ceil((float)len/(TITLE_SIZE*NWORDS)),NWORDS>>>(d_text, d_words, d_matches, nwords, len);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
checkCudaErrors(hipPeekAtLastError());
hipEventElapsedTime(&time_kernel,start,stop);
printf("Kernel execution time: %fs\n", time_kernel/1000);
hipEventRecord(start, 0);
checkCudaErrors(hipMemcpy(h_matches, d_matches, nwords*sizeof(int), hipMemcpyDeviceToHost));
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time_D2H,start,stop);
printf("DeviceToHost memcopy time: %fs\n", time_D2H/1000);
printf("Total memcopy time: %fs\n", (time_D2H+time_H2D)/1000);
printf("Total memcopy+kernel time: %fs\n", (time_D2H+time_H2D+time_kernel)/1000);
printf("Speedup without memory: %f\n", cpuRunTime/((time_kernel)/1000));
printf("Speedup with memory: %f\n", cpuRunTime/((time_D2H + time_H2D + time_kernel)/1000));
check_matches(h_matches);
hipEventDestroy(start);
hipEventDestroy(stop);
free(h_matches);
hipFree(d_words);
hipFree(d_matches);
hipFree(d_text);
}
int main(int argc, const char **argv)
{
intialise("./data/small.txt");
exec_CPU();
exec_gpu_simple();
intialise("./data/medium.txt");
exec_CPU();
exec_gpu_simple();
intialise("./data/large.txt");
exec_CPU();
exec_gpu_simple();
deinit();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <ctime>
// Includes CUDA
#include <hip/hip_runtime.h>
#define LINEWIDTH 20
#define NWORDS 32
#define CUDA_STREAMS 1
#define BLOCK_SIZE 32
#define TITLE_SIZE 4
int length;
int len;
int nwords;
int matches[NWORDS];
char *ctext;
char keywords[NWORDS][LINEWIDTH];
unsigned int *text;
unsigned int *words;
float cpuRunTime;
// citation: https://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
#define checkCudaErrors(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
void intialise(char *input)
{
nwords = NWORDS;
printf("-----------\nGoint to read %s\n", input);
char *line;
line = (char*) malloc(sizeof(char)*LINEWIDTH);
memset(matches, 0, sizeof(matches));
// read in text and keywords for processing
FILE *fp, *wfile;
wfile = fopen("./data/keywords.txt","r");
if (!wfile)
{ printf("keywords.txt: File not found.\n"); exit(0);}
int k=0, cnt = nwords;
size_t read, linelen = LINEWIDTH;
while((read = getline(&line, &linelen, wfile)) != -1 && cnt--)
{
strncpy(keywords[k], line, sizeof(line));
keywords[k][4] = '\0';
k++;
}
fclose(wfile);
fp = fopen(input,"r");
if (!fp)
{ printf("Unable to open the file.\n"); exit(0);}
length = 0;
while (getc(fp) != EOF) length++;
ctext = (char *)malloc(length+4);
rewind(fp);
for (int l=0; l<length; l++) ctext[l] = getc(fp);
for (int l=length; l<length+4; l++) ctext[l] = ' ';
fclose(fp);
printf("Length : %d\n", length );
// define number of words of text, and set pointers
len = length/4;
text = (unsigned int *) ctext;
// define words for matching
words = (unsigned int *)malloc(nwords*sizeof(unsigned int));
for (int w=0; w<nwords; w++)
{
words[w] = ((unsigned int) keywords[w][0])
+ ((unsigned int) keywords[w][1])*(1<<8)
+ ((unsigned int) keywords[w][2])*(1<<16)
+ ((unsigned int) keywords[w][3])*(1<<24);
}
}
void deinit(){
free(words);
free(text);
}
void check_matches(int *temp_matches){
bool isRight = true;
for(int i = 0; i<nwords; i++) {
if(matches[i] != temp_matches[i]) {
isRight = false;
printf("WRONG OUTPUT:\t %s\t|\t%d\n", keywords[i], temp_matches[i]);
}
}
if(isRight) {
printf(" - Correct Answer -\n");
}
}
void print_matches(int *temp_matches){
printf("Printing Matches:\n");
printf("Word\t |\tNumber of Matches\n===================================\n");
for (int i = 0; i < nwords; ++i)
printf("%s\t |\t%d\n", keywords[i], temp_matches[i]);
}
void matchPattern_CPU(unsigned int *text, unsigned int *words, int *matches, int nwords, int length)
{
unsigned int word;
for (int l=0; l<length; l++)
{
for (int offset=0; offset<4; offset++)
{
if (offset==0)
word = text[l];
else
word = (text[l]>>(8*offset)) + (text[l+1]<<(32-8*offset));
for (int w=0; w<nwords; w++){
matches[w] += (word==words[w]);
}
}
}
}
void exec_CPU(){
// CPU execution
const clock_t begin_time = clock();
matchPattern_CPU(text, words, matches, nwords, len);
cpuRunTime = (float)( clock() - begin_time ) / CLOCKS_PER_SEC;
printf("CPU exec time: %f s\n\n", cpuRunTime);
}
__global__ void matchPattern_gpu_1(const unsigned int *text, const unsigned int *words, int *matches, int nwords, int length)
{
int tid = threadIdx.x;
int idx = blockIdx.x * blockDim.x + tid;
// for loading text into the shared memory
__shared__ unsigned int text_s[(TITLE_SIZE*NWORDS) + TITLE_SIZE];
#pragma unroll
for(int x = 0; x<TITLE_SIZE; x++){
text_s[tid + (x*NWORDS) + x] = text[idx+(x*blockDim.x*gridDim.x)];
text_s[((x+1)*NWORDS) + x] = text[(x*blockDim.x*gridDim.x) + (blockIdx.x * blockDim.x) + blockDim.x];
}
// loads the keyword for this thread
// each thread in a block is reponsible for one keyword
unsigned int keyword = words[tid];
__syncthreads();
unsigned int word;
int sum = 0;
// go through all the words in the shared memory
#pragma unroll
for(int x = 0; x<TITLE_SIZE; x ++) {
#pragma unroll
for(int w = (x*NWORDS) + x; w < ((x+1)*NWORDS) + (x); w++) {
#pragma unroll
for (int offset=0; offset<4; offset++)
{
word = offset==0 ? text_s[w] : (text_s[w]>>(8*offset)) + (text_s[w+1]<<(32-8*offset));
sum = sum + (word==keyword);
}
}
}
atomicAdd(&matches[tid],sum);
}
void exec_gpu_simple(){
// GPU execution
unsigned int *d_text; unsigned int *d_words; int *d_matches;
int *h_matches;
h_matches = (int *)malloc(nwords*sizeof(int));
checkCudaErrors(hipMalloc((void**)&d_words, nwords*sizeof(unsigned int)));
checkCudaErrors(hipMalloc((void**)&d_matches, nwords*sizeof(int)));
checkCudaErrors(hipMalloc((void**)&d_text, sizeof(char)*strlen(ctext)));
hipEvent_t start,stop;
float time_H2D,time_D2H,time_kernel;
checkCudaErrors(hipEventCreate(&start));
checkCudaErrors(hipEventCreate(&stop));
// MEMCOPY
hipEventRecord(start, 0);
checkCudaErrors(hipMemcpy(d_words, words, nwords*sizeof(unsigned int), hipMemcpyHostToDevice));
checkCudaErrors(hipMemcpy(d_text, text, sizeof(char)*strlen(ctext), hipMemcpyHostToDevice));
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time_H2D,start,stop);
printf("HostToDevice memcopy time: %fs\n", time_H2D/1000);
// RUN KERNEL
hipEventRecord(start, 0);
matchPattern_gpu_1<<< ceil((float)len/(TITLE_SIZE*NWORDS)),NWORDS>>>(d_text, d_words, d_matches, nwords, len);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
checkCudaErrors(hipPeekAtLastError());
hipEventElapsedTime(&time_kernel,start,stop);
printf("Kernel execution time: %fs\n", time_kernel/1000);
hipEventRecord(start, 0);
checkCudaErrors(hipMemcpy(h_matches, d_matches, nwords*sizeof(int), hipMemcpyDeviceToHost));
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time_D2H,start,stop);
printf("DeviceToHost memcopy time: %fs\n", time_D2H/1000);
printf("Total memcopy time: %fs\n", (time_D2H+time_H2D)/1000);
printf("Total memcopy+kernel time: %fs\n", (time_D2H+time_H2D+time_kernel)/1000);
printf("Speedup without memory: %f\n", cpuRunTime/((time_kernel)/1000));
printf("Speedup with memory: %f\n", cpuRunTime/((time_D2H + time_H2D + time_kernel)/1000));
check_matches(h_matches);
hipEventDestroy(start);
hipEventDestroy(stop);
free(h_matches);
hipFree(d_words);
hipFree(d_matches);
hipFree(d_text);
}
int main(int argc, const char **argv)
{
intialise("./data/small.txt");
exec_CPU();
exec_gpu_simple();
intialise("./data/medium.txt");
exec_CPU();
exec_gpu_simple();
intialise("./data/large.txt");
exec_CPU();
exec_gpu_simple();
deinit();
} | .text
.file "pattern_tiling.hip"
.globl _Z9intialisePc # -- Begin function _Z9intialisePc
.p2align 4, 0x90
.type _Z9intialisePc,@function
_Z9intialisePc: # @_Z9intialisePc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
movl $32, nwords(%rip)
movl $.L.str, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl $20, %edi
callq malloc
movq %rax, 8(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, matches(%rip)
movaps %xmm0, matches+16(%rip)
movaps %xmm0, matches+32(%rip)
movaps %xmm0, matches+48(%rip)
movaps %xmm0, matches+64(%rip)
movaps %xmm0, matches+80(%rip)
movaps %xmm0, matches+96(%rip)
movaps %xmm0, matches+112(%rip)
movl $.L.str.1, %edi
movl $.L.str.2, %esi
callq fopen
testq %rax, %rax
je .LBB0_1
# %bb.3:
movq %rax, %r14
movl nwords(%rip), %ebp
movq $20, 16(%rsp)
leaq 8(%rsp), %rdi
leaq 16(%rsp), %rsi
movl $10, %edx
movq %rax, %rcx
callq __getdelim
cmpq $-1, %rax
je .LBB0_8
# %bb.4:
testl %ebp, %ebp
je .LBB0_8
# %bb.5: # %.lr.ph.preheader
decl %ebp
movl $keywords, %r15d
leaq 8(%rsp), %r12
leaq 16(%rsp), %r13
.p2align 4, 0x90
.LBB0_6: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rsi
movl $8, %edx
movq %r15, %rdi
callq strncpy
movb $0, 4(%r15)
movq %r12, %rdi
movq %r13, %rsi
movl $10, %edx
movq %r14, %rcx
callq __getdelim
subl $1, %ebp
setb %cl
cmpq $-1, %rax
je .LBB0_8
# %bb.7: # %.lr.ph
# in Loop: Header=BB0_6 Depth=1
addq $20, %r15
testb %cl, %cl
je .LBB0_6
.LBB0_8: # %.critedge
movq %r14, %rdi
callq fclose
movl $.L.str.2, %esi
movq %rbx, %rdi
callq fopen
testq %rax, %rax
je .LBB0_22
# %bb.9: # %.preheader38
movq %rax, %rbx
movl $0, length(%rip)
.p2align 4, 0x90
.LBB0_11: # %.lr.ph45
# =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
callq getc
cmpl $-1, %eax
je .LBB0_12
# %bb.10: # %.lr.ph45
# in Loop: Header=BB0_11 Depth=1
incl length(%rip)
jmp .LBB0_11
.LBB0_12: # %._crit_edge
movslq length(%rip), %rdi
addq $4, %rdi
callq malloc
movq %rax, ctext(%rip)
movq %rbx, %rdi
callq rewind
movl length(%rip), %eax
testl %eax, %eax
jle .LBB0_15
# %bb.13: # %.lr.ph48.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_14: # %.lr.ph48
# =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
callq getc
movq ctext(%rip), %rcx
movb %al, (%rcx,%r14)
incq %r14
movslq length(%rip), %rax
cmpq %rax, %r14
jl .LBB0_14
.LBB0_15: # %.preheader
movl length(%rip), %ecx
addl $4, %ecx
cmpl %ecx, %eax
jge .LBB0_18
# %bb.16: # %.lr.ph50.preheader
cltq
decq %rax
.p2align 4, 0x90
.LBB0_17: # %.lr.ph50
# =>This Inner Loop Header: Depth=1
movq ctext(%rip), %rcx
movb $32, 1(%rcx,%rax)
movslq length(%rip), %rcx
addq $3, %rcx
incq %rax
cmpq %rcx, %rax
jl .LBB0_17
.LBB0_18: # %._crit_edge51
movq %rbx, %rdi
callq fclose
movl length(%rip), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl length(%rip), %eax
leal 3(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $2, %ecx
movl %ecx, len(%rip)
movq ctext(%rip), %rax
movq %rax, text(%rip)
movslq nwords(%rip), %rbx
leaq (,%rbx,4), %rdi
callq malloc
movq %rax, words(%rip)
testq %rbx, %rbx
jle .LBB0_21
# %bb.19: # %.lr.ph54.preheader
movl %ebx, %ecx
shlq $2, %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB0_20: # %.lr.ph54
# =>This Inner Loop Header: Depth=1
movsbl keywords(%rdx,%rdx,4), %esi
movsbl keywords+1(%rdx,%rdx,4), %edi
shll $8, %edi
addl %esi, %edi
movsbl keywords+2(%rdx,%rdx,4), %esi
shll $16, %esi
movzbl keywords+3(%rdx,%rdx,4), %r8d
shll $24, %r8d
addl %esi, %r8d
addl %edi, %r8d
movl %r8d, (%rax,%rdx)
addq $4, %rdx
cmpq %rdx, %rcx
jne .LBB0_20
.LBB0_21: # %._crit_edge55
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_1:
.cfi_def_cfa_offset 80
movl $.Lstr, %edi
jmp .LBB0_2
.LBB0_22:
movl $.Lstr.1, %edi
.LBB0_2:
callq puts@PLT
xorl %edi, %edi
callq exit
.Lfunc_end0:
.size _Z9intialisePc, .Lfunc_end0-_Z9intialisePc
.cfi_endproc
# -- End function
.globl _Z6deinitv # -- Begin function _Z6deinitv
.p2align 4, 0x90
.type _Z6deinitv,@function
_Z6deinitv: # @_Z6deinitv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq words(%rip), %rdi
callq free
movq text(%rip), %rdi
popq %rax
.cfi_def_cfa_offset 8
jmp free # TAILCALL
.Lfunc_end1:
.size _Z6deinitv, .Lfunc_end1-_Z6deinitv
.cfi_endproc
# -- End function
.globl _Z13check_matchesPi # -- Begin function _Z13check_matchesPi
.p2align 4, 0x90
.type _Z13check_matchesPi,@function
_Z13check_matchesPi: # @_Z13check_matchesPi
.cfi_startproc
# %bb.0:
cmpl $0, nwords(%rip)
jle .LBB2_7
# %bb.1: # %.lr.ph.preheader
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
movb $1, %bpl
movl $keywords, %r14d
xorl %r15d, %r15d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_4: # in Loop: Header=BB2_2 Depth=1
incq %r15
movslq nwords(%rip), %rax
addq $20, %r14
cmpq %rax, %r15
jge .LBB2_5
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %edx
cmpl %edx, matches(,%r15,4)
je .LBB2_4
# %bb.3: # in Loop: Header=BB2_2 Depth=1
xorl %ebp, %ebp
movl $.L.str.6, %edi
movq %r14, %rsi
xorl %eax, %eax
callq printf
jmp .LBB2_4
.LBB2_5: # %._crit_edge.loopexit
testb $1, %bpl
leaq 8(%rsp), %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
jne .LBB2_7
# %bb.6:
retq
.LBB2_7: # %.critedge
movl $.Lstr.2, %edi
jmp puts@PLT # TAILCALL
.Lfunc_end2:
.size _Z13check_matchesPi, .Lfunc_end2-_Z13check_matchesPi
.cfi_endproc
# -- End function
.globl _Z13print_matchesPi # -- Begin function _Z13print_matchesPi
.p2align 4, 0x90
.type _Z13print_matchesPi,@function
_Z13print_matchesPi: # @_Z13print_matchesPi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl $.Lstr.3, %edi
callq puts@PLT
movl $.Lstr.4, %edi
callq puts@PLT
cmpl $0, nwords(%rip)
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
movl $keywords, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %edx
movl $.L.str.10, %edi
movq %r14, %rsi
xorl %eax, %eax
callq printf
incq %r15
movslq nwords(%rip), %rax
addq $20, %r14
cmpq %rax, %r15
jl .LBB3_2
.LBB3_3: # %._crit_edge
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z13print_matchesPi, .Lfunc_end3-_Z13print_matchesPi
.cfi_endproc
# -- End function
.globl _Z16matchPattern_CPUPjS_Piii # -- Begin function _Z16matchPattern_CPUPjS_Piii
.p2align 4, 0x90
.type _Z16matchPattern_CPUPjS_Piii,@function
_Z16matchPattern_CPUPjS_Piii: # @_Z16matchPattern_CPUPjS_Piii
.cfi_startproc
# %bb.0:
testl %r8d, %r8d
jle .LBB4_12
# %bb.1: # %.preheader.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl %ecx, %eax
movl %r8d, %r8d
movl %ecx, %r9d
xorl %r10d, %r10d
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_10: # in Loop: Header=BB4_2 Depth=1
incq %r10
cmpq %r8, %r10
je .LBB4_11
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_3 Depth 2
# Child Loop BB4_8 Depth 3
xorl %r11d, %r11d
jmp .LBB4_3
.p2align 4, 0x90
.LBB4_9: # %._crit_edge
# in Loop: Header=BB4_3 Depth=2
incl %r11d
cmpl $4, %r11d
je .LBB4_10
.LBB4_3: # Parent Loop BB4_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_8 Depth 3
testl %r11d, %r11d
je .LBB4_4
# %bb.5: # in Loop: Header=BB4_3 Depth=2
leal (,%r11,8), %ecx
movl (%rdi,%r10,4), %ebp
shrl %cl, %ebp
movl 4(%rdi,%r10,4), %ebx
negb %cl
# kill: def $cl killed $cl killed $ecx
shll %cl, %ebx
addl %ebp, %ebx
testl %eax, %eax
jg .LBB4_7
jmp .LBB4_9
.p2align 4, 0x90
.LBB4_4: # in Loop: Header=BB4_3 Depth=2
movl (%rdi,%r10,4), %ebx
testl %eax, %eax
jle .LBB4_9
.LBB4_7: # %.lr.ph.preheader
# in Loop: Header=BB4_3 Depth=2
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_8: # %.lr.ph
# Parent Loop BB4_2 Depth=1
# Parent Loop BB4_3 Depth=2
# => This Inner Loop Header: Depth=3
xorl %ebp, %ebp
cmpl (%rsi,%rcx,4), %ebx
sete %bpl
addl %ebp, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %r9
jne .LBB4_8
jmp .LBB4_9
.LBB4_11:
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %rbp
.LBB4_12: # %._crit_edge27
retq
.Lfunc_end4:
.size _Z16matchPattern_CPUPjS_Piii, .Lfunc_end4-_Z16matchPattern_CPUPjS_Piii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z8exec_CPUv
.LCPI5_0:
.long 0x49742400 # float 1.0E+6
.text
.globl _Z8exec_CPUv
.p2align 4, 0x90
.type _Z8exec_CPUv,@function
_Z8exec_CPUv: # @_Z8exec_CPUv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
callq clock
movq %rax, %rbx
movl len(%rip), %eax
testl %eax, %eax
jle .LBB5_10
# %bb.1: # %.preheader.lr.ph.i
movq text(%rip), %rdx
movq words(%rip), %rsi
movl nwords(%rip), %edi
movq %rdi, %r8
shlq $2, %r8
xorl %r9d, %r9d
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_9: # in Loop: Header=BB5_2 Depth=1
incq %r9
cmpq %rax, %r9
je .LBB5_10
.LBB5_2: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB5_3 Depth 2
# Child Loop BB5_7 Depth 3
xorl %r10d, %r10d
jmp .LBB5_3
.p2align 4, 0x90
.LBB5_8: # %._crit_edge.i
# in Loop: Header=BB5_3 Depth=2
incl %r10d
cmpl $4, %r10d
je .LBB5_9
.LBB5_3: # Parent Loop BB5_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB5_7 Depth 3
movl (%rdx,%r9,4), %r11d
testl %r10d, %r10d
je .LBB5_5
# %bb.4: # in Loop: Header=BB5_3 Depth=2
leal (,%r10,8), %ecx
shrl %cl, %r11d
movl 4(%rdx,%r9,4), %ebp
negb %cl
# kill: def $cl killed $cl killed $ecx
shll %cl, %ebp
addl %ebp, %r11d
.LBB5_5: # in Loop: Header=BB5_3 Depth=2
testl %edi, %edi
jle .LBB5_8
# %bb.6: # %.lr.ph.i.preheader
# in Loop: Header=BB5_3 Depth=2
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB5_7: # %.lr.ph.i
# Parent Loop BB5_2 Depth=1
# Parent Loop BB5_3 Depth=2
# => This Inner Loop Header: Depth=3
xorl %ebp, %ebp
cmpl (%rsi,%rcx), %r11d
sete %bpl
addl %ebp, matches(%rcx)
addq $4, %rcx
cmpq %rcx, %r8
jne .LBB5_7
jmp .LBB5_8
.LBB5_10: # %_Z16matchPattern_CPUPjS_Piii.exit
callq clock
subq %rbx, %rax
cvtsi2ss %rax, %xmm0
divss .LCPI5_0(%rip), %xmm0
movss %xmm0, cpuRunTime(%rip)
cvtss2sd %xmm0, %xmm0
movl $.L.str.11, %edi
movb $1, %al
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.Lfunc_end5:
.size _Z8exec_CPUv, .Lfunc_end5-_Z8exec_CPUv
.cfi_endproc
# -- End function
.globl _Z33__device_stub__matchPattern_gpu_1PKjS0_Piii # -- Begin function _Z33__device_stub__matchPattern_gpu_1PKjS0_Piii
.p2align 4, 0x90
.type _Z33__device_stub__matchPattern_gpu_1PKjS0_Piii,@function
_Z33__device_stub__matchPattern_gpu_1PKjS0_Piii: # @_Z33__device_stub__matchPattern_gpu_1PKjS0_Piii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18matchPattern_gpu_1PKjS0_Piii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end6:
.size _Z33__device_stub__matchPattern_gpu_1PKjS0_Piii, .Lfunc_end6-_Z33__device_stub__matchPattern_gpu_1PKjS0_Piii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z15exec_gpu_simplev
.LCPI7_0:
.long 0x447a0000 # float 1000
.LCPI7_1:
.long 0x3c000000 # float 0.0078125
.text
.globl _Z15exec_gpu_simplev
.p2align 4, 0x90
.type _Z15exec_gpu_simplev,@function
_Z15exec_gpu_simplev: # @_Z15exec_gpu_simplev
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $184, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movslq nwords(%rip), %r14
shlq $2, %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
leaq 56(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB7_1
# %bb.3: # %_Z9gpuAssert10hipError_tPKcib.exit
movslq nwords(%rip), %rsi
shlq $2, %rsi
leaq 48(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB7_4
# %bb.5: # %_Z9gpuAssert10hipError_tPKcib.exit6
movq ctext(%rip), %rdi
callq strlen
leaq 64(%rsp), %rdi
movq %rax, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB7_6
# %bb.7: # %_Z9gpuAssert10hipError_tPKcib.exit8
leaq 24(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB7_8
# %bb.9: # %_Z9gpuAssert10hipError_tPKcib.exit10
leaq 8(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB7_10
# %bb.11: # %_Z9gpuAssert10hipError_tPKcib.exit12
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 56(%rsp), %rdi
movq words(%rip), %rsi
movslq nwords(%rip), %rdx
shlq $2, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB7_12
# %bb.13: # %_Z9gpuAssert10hipError_tPKcib.exit14
movq 64(%rsp), %r14
movq text(%rip), %r15
movq ctext(%rip), %rdi
callq strlen
movq %r14, %rdi
movq %r15, %rsi
movq %rax, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB7_14
# %bb.15: # %_Z9gpuAssert10hipError_tPKcib.exit16
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 20(%rsp), %rdi
callq hipEventElapsedTime
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI7_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.13, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
xorps %xmm0, %xmm0
cvtsi2ssl len(%rip), %xmm0
mulss .LCPI7_1(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $32, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_17
# %bb.16:
movq 64(%rsp), %rax
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movl nwords(%rip), %esi
movl len(%rip), %edi
movq %rax, 176(%rsp)
movq %rcx, 168(%rsp)
movq %rdx, 160(%rsp)
movl %esi, 76(%rsp)
movl %edi, 72(%rsp)
leaq 176(%rsp), %rax
movq %rax, 80(%rsp)
leaq 168(%rsp), %rax
movq %rax, 88(%rsp)
leaq 160(%rsp), %rax
movq %rax, 96(%rsp)
leaq 76(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rdi
leaq 144(%rsp), %rsi
leaq 136(%rsp), %rdx
leaq 128(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 144(%rsp), %rcx
movl 152(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18matchPattern_gpu_1PKjS0_Piii, %edi
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_17:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB7_18
# %bb.19: # %_Z9gpuAssert10hipError_tPKcib.exit18
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI7_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.14, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 48(%rsp), %rsi
movslq nwords(%rip), %rdx
shlq $2, %rdx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB7_20
# %bb.21: # %_Z9gpuAssert10hipError_tPKcib.exit20
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 80(%rsp), %rdi
callq hipEventElapsedTime
movss 80(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI7_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movb $1, %bpl
movl $.L.str.15, %edi
movb $1, %al
callq printf
movss 80(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss 20(%rsp), %xmm0
divss .LCPI7_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.16, %edi
movb $1, %al
callq printf
movss 80(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss 20(%rsp), %xmm0
addss 32(%rsp), %xmm0
divss .LCPI7_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.17, %edi
movb $1, %al
callq printf
movss cpuRunTime(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss 32(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss .LCPI7_0(%rip), %xmm1
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.18, %edi
movb $1, %al
callq printf
movss 80(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss 20(%rsp), %xmm0
addss 32(%rsp), %xmm0
movss cpuRunTime(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss .LCPI7_0(%rip), %xmm0
divss %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
movl $.L.str.19, %edi
movb $1, %al
callq printf
cmpl $0, nwords(%rip)
jle .LBB7_27
# %bb.22: # %.lr.ph.i.preheader
movl $keywords, %r14d
xorl %r15d, %r15d
jmp .LBB7_23
.p2align 4, 0x90
.LBB7_25: # in Loop: Header=BB7_23 Depth=1
incq %r15
movslq nwords(%rip), %rax
addq $20, %r14
cmpq %rax, %r15
jge .LBB7_26
.LBB7_23: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %edx
cmpl %edx, matches(,%r15,4)
je .LBB7_25
# %bb.24: # in Loop: Header=BB7_23 Depth=1
xorl %ebp, %ebp
movl $.L.str.6, %edi
movq %r14, %rsi
xorl %eax, %eax
callq printf
jmp .LBB7_25
.LBB7_26: # %._crit_edge.loopexit.i
testb $1, %bpl
je .LBB7_28
.LBB7_27: # %.critedge.i
movl $.Lstr.2, %edi
callq puts@PLT
.LBB7_28: # %_Z13check_matchesPi.exit
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq %rbx, %rdi
callq free
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
addq $184, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB7_1:
.cfi_def_cfa_offset 224
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.23, %esi
movl $.L.str.12, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $200, %r8d
jmp .LBB7_2
.LBB7_4:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.23, %esi
movl $.L.str.12, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $201, %r8d
jmp .LBB7_2
.LBB7_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.23, %esi
movl $.L.str.12, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $202, %r8d
jmp .LBB7_2
.LBB7_8:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.23, %esi
movl $.L.str.12, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $206, %r8d
jmp .LBB7_2
.LBB7_10:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.23, %esi
movl $.L.str.12, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $207, %r8d
jmp .LBB7_2
.LBB7_12:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.23, %esi
movl $.L.str.12, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $212, %r8d
jmp .LBB7_2
.LBB7_14:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.23, %esi
movl $.L.str.12, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $213, %r8d
jmp .LBB7_2
.LBB7_18:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.23, %esi
movl $.L.str.12, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $224, %r8d
jmp .LBB7_2
.LBB7_20:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.23, %esi
movl $.L.str.12, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $229, %r8d
.LBB7_2:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end7:
.size _Z15exec_gpu_simplev, .Lfunc_end7-_Z15exec_gpu_simplev
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.L.str.20, %edi
callq _Z9intialisePc
callq _Z8exec_CPUv
callq _Z15exec_gpu_simplev
movl $.L.str.21, %edi
callq _Z9intialisePc
callq _Z8exec_CPUv
callq _Z15exec_gpu_simplev
movl $.L.str.22, %edi
callq _Z9intialisePc
callq _Z8exec_CPUv
callq _Z15exec_gpu_simplev
movq words(%rip), %rdi
callq free
movq text(%rip), %rdi
callq free
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size main, .Lfunc_end8-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB9_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB9_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18matchPattern_gpu_1PKjS0_Piii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end9:
.size __hip_module_ctor, .Lfunc_end9-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB10_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB10_2:
retq
.Lfunc_end10:
.size __hip_module_dtor, .Lfunc_end10-__hip_module_dtor
.cfi_endproc
# -- End function
.type length,@object # @length
.bss
.globl length
.p2align 2, 0x0
length:
.long 0 # 0x0
.size length, 4
.type len,@object # @len
.globl len
.p2align 2, 0x0
len:
.long 0 # 0x0
.size len, 4
.type nwords,@object # @nwords
.globl nwords
.p2align 2, 0x0
nwords:
.long 0 # 0x0
.size nwords, 4
.type matches,@object # @matches
.globl matches
.p2align 4, 0x0
matches:
.zero 128
.size matches, 128
.type ctext,@object # @ctext
.globl ctext
.p2align 3, 0x0
ctext:
.quad 0
.size ctext, 8
.type keywords,@object # @keywords
.globl keywords
.p2align 4, 0x0
keywords:
.zero 640
.size keywords, 640
.type text,@object # @text
.globl text
.p2align 3, 0x0
text:
.quad 0
.size text, 8
.type words,@object # @words
.globl words
.p2align 3, 0x0
words:
.quad 0
.size words, 8
.type cpuRunTime,@object # @cpuRunTime
.globl cpuRunTime
.p2align 2, 0x0
cpuRunTime:
.long 0x00000000 # float 0
.size cpuRunTime, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "-----------\nGoint to read %s\n"
.size .L.str, 30
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "./data/keywords.txt"
.size .L.str.1, 20
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "r"
.size .L.str.2, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Length : %d\n"
.size .L.str.5, 13
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "WRONG OUTPUT:\t %s\t|\t%d\n"
.size .L.str.6, 24
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "%s\t |\t%d\n"
.size .L.str.10, 11
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "CPU exec time: %f s\n\n"
.size .L.str.11, 22
.type _Z18matchPattern_gpu_1PKjS0_Piii,@object # @_Z18matchPattern_gpu_1PKjS0_Piii
.section .rodata,"a",@progbits
.globl _Z18matchPattern_gpu_1PKjS0_Piii
.p2align 3, 0x0
_Z18matchPattern_gpu_1PKjS0_Piii:
.quad _Z33__device_stub__matchPattern_gpu_1PKjS0_Piii
.size _Z18matchPattern_gpu_1PKjS0_Piii, 8
.type .L.str.12,@object # @.str.12
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.12:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/sedflix/cuda_pattern_matching/master/pattern_tiling.hip"
.size .L.str.12, 113
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "HostToDevice memcopy time: %fs\n"
.size .L.str.13, 32
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Kernel execution time: %fs\n"
.size .L.str.14, 28
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "DeviceToHost memcopy time: %fs\n"
.size .L.str.15, 32
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "Total memcopy time: %fs\n"
.size .L.str.16, 25
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "Total memcopy+kernel time: %fs\n"
.size .L.str.17, 32
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "Speedup without memory: %f\n"
.size .L.str.18, 28
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "Speedup with memory: %f\n"
.size .L.str.19, 25
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "./data/small.txt"
.size .L.str.20, 17
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "./data/medium.txt"
.size .L.str.21, 18
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "./data/large.txt"
.size .L.str.22, 17
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.23, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z18matchPattern_gpu_1PKjS0_Piii"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "keywords.txt: File not found."
.size .Lstr, 30
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Unable to open the file."
.size .Lstr.1, 25
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz " - Correct Answer -"
.size .Lstr.2, 20
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Printing Matches:"
.size .Lstr.3, 18
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Word\t |\tNumber of Matches\n==================================="
.size .Lstr.4, 63
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__matchPattern_gpu_1PKjS0_Piii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym keywords
.addrsig_sym _Z18matchPattern_gpu_1PKjS0_Piii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void StarRadKernel2 (double *Qbase2, double *Vrad, double *QStar, double dt, int nrad, int nsec, double *invdiffRmed, double *Rmed, double *dq)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
if (i<nrad && j<nsec){
if (Vrad[i*nsec + j] > 0.0 && i > 0)
QStar[i*nsec + j] = Qbase2[(i-1)*nsec + j] + (Rmed[i]-Rmed[i-1]-Vrad[i*nsec + j]*dt)*0.5*dq[i-1+j*nrad];
else
QStar[i*nsec + j] = Qbase2[i*nsec + j]-(Rmed[i+1]-Rmed[i]+Vrad[i*nsec + j]*dt)*0.5*dq[i+j*nrad];
}
if (i == 0 && j<nsec)
QStar[j] = QStar[j+nsec*nrad] = 0.0;
} | code for sm_80
Function : _Z14StarRadKernel2PdS_S_diiS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x310 ; /* 0x000002d000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0050*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e680000002600 */
/*0060*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0080*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x184], PT ; /* 0x0000610000007a0c */
/* 0x000fe20003f06270 */
/*0090*/ IMAD R9, R9, c[0x0][0x4], R2 ; /* 0x0000010009097a24 */
/* 0x002fca00078e0202 */
/*00a0*/ ISETP.GE.OR P1, PT, R9.reuse, c[0x0][0x180], P0 ; /* 0x0000600009007a0c */
/* 0x040fe40000726670 */
/*00b0*/ ISETP.NE.OR P0, PT, R9, RZ, P0 ; /* 0x000000ff0900720c */
/* 0x000fd60000705670 */
/*00c0*/ @P1 BRA 0x300 ; /* 0x0000023000001947 */
/* 0x000fea0003800000 */
/*00d0*/ HFMA2.MMA R8, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff087435 */
/* 0x000fe200000001ff */
/*00e0*/ IMAD R3, R9, c[0x0][0x184], R0 ; /* 0x0000610009037a24 */
/* 0x000fd200078e0200 */
/*00f0*/ IMAD.WIDE R4, R3, R8, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fcc00078e0208 */
/*0100*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*0110*/ IMAD.WIDE R10, R9, R8, c[0x0][0x190] ; /* 0x00006400090a7625 */
/* 0x000fe200078e0208 */
/*0120*/ SHF.R.S32.HI R2, RZ, 0x1f, R3 ; /* 0x0000001fff027819 */
/* 0x000fc60000011403 */
/*0130*/ IMAD R7, R0, c[0x0][0x180], R9 ; /* 0x0000600000077a24 */
/* 0x000fc800078e0209 */
/*0140*/ IMAD.WIDE R6, R7, R8, c[0x0][0x198] ; /* 0x0000660007067625 */
/* 0x000fe200078e0208 */
/*0150*/ DSETP.GT.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400722a */
/* 0x004e0c0003f24000 */
/*0160*/ ISETP.GT.AND P1, PT, R9, RZ, P1 ; /* 0x000000ff0900720c */
/* 0x001fda0000f24270 */
/*0170*/ @!P1 LDG.E.64 R14, [R10.64] ; /* 0x000000040a0e9981 */
/* 0x000ea8000c1e1b00 */
/*0180*/ @!P1 LDG.E.64 R16, [R10.64+0x8] ; /* 0x000008040a109981 */
/* 0x000ea2000c1e1b00 */
/*0190*/ @!P1 LEA R20, P2, R3, c[0x0][0x160], 0x3 ; /* 0x0000580003149a11 */
/* 0x000fc600078418ff */
/*01a0*/ @!P1 LDG.E.64 R12, [R6.64] ; /* 0x00000004060c9981 */
/* 0x000ee2000c1e1b00 */
/*01b0*/ @!P1 LEA.HI.X R21, R3, c[0x0][0x164], R2, 0x3, P2 ; /* 0x0000590003159a11 */
/* 0x000fca00010f1c02 */
/*01c0*/ @!P1 LDG.E.64 R18, [R20.64] ; /* 0x0000000414129981 */
/* 0x000ee2000c1e1b00 */
/*01d0*/ IMAD.WIDE R2, R3, R8, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fe200078e0208 */
/*01e0*/ @!P1 DADD R14, -R14, R16 ; /* 0x000000000e0e9229 */
/* 0x004e0c0000000110 */
/*01f0*/ @!P1 DFMA R14, R4, c[0x0][0x178], R14 ; /* 0x00005e00040e9a2b */
/* 0x001e0c000000000e */
/*0200*/ @!P1 DMUL R14, R14, -0.5 ; /* 0xbfe000000e0e9828 */
/* 0x001ee20000000000 */
/*0210*/ @P1 MOV R16, c[0x0][0x184] ; /* 0x0000610000101a02 */
/* 0x000fca0000000f00 */
/*0220*/ @!P1 DFMA R18, R14, R12, R18 ; /* 0x0000000c0e12922b */
/* 0x008e220000000012 */
/*0230*/ @P1 IMAD R9, R9, R16, -c[0x0][0x184] ; /* 0x8000610009091624 */
/* 0x000fcc00078e0210 */
/*0240*/ @!P1 STG.E.64 [R2.64], R18 ; /* 0x0000001202009986 */
/* 0x0011e8000c101b04 */
/*0250*/ @P1 LDG.E.64 R12, [R10.64+-0x8] ; /* 0xfffff8040a0c1981 */
/* 0x000ea8000c1e1b00 */
/*0260*/ @P1 LDG.E.64 R14, [R10.64] ; /* 0x000000040a0e1981 */
/* 0x000ea2000c1e1b00 */
/*0270*/ @P1 IADD3 R9, R0, R9, RZ ; /* 0x0000000900091210 */
/* 0x000fc60007ffe0ff */
/*0280*/ @P1 LDG.E.64 R6, [R6.64+-0x8] ; /* 0xfffff80406061981 */
/* 0x000ee4000c1e1b00 */
/*0290*/ @P1 IMAD.WIDE R8, R9, R8, c[0x0][0x160] ; /* 0x0000580009081625 */
/* 0x000fcc00078e0208 */
/*02a0*/ @P1 LDG.E.64 R8, [R8.64] ; /* 0x0000000408081981 */
/* 0x000ee2000c1e1b00 */
/*02b0*/ @P1 DADD R12, -R12, R14 ; /* 0x000000000c0c1229 */
/* 0x004e4c000000010e */
/*02c0*/ @P1 DFMA R12, -R4, c[0x0][0x178], R12 ; /* 0x00005e00040c1a2b */
/* 0x002e4c000000010c */
/*02d0*/ @P1 DMUL R12, R12, 0.5 ; /* 0x3fe000000c0c1828 */
/* 0x002ecc0000000000 */
/*02e0*/ @P1 DFMA R12, R12, R6, R8 ; /* 0x000000060c0c122b */
/* 0x008e4e0000000008 */
/*02f0*/ @P1 STG.E.64 [R2.64], R12 ; /* 0x0000000c02001986 */
/* 0x0021e8000c101b04 */
/*0300*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0310*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0320*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0330*/ MOV R3, c[0x0][0x184] ; /* 0x0000610000037a02 */
/* 0x001fca0000000f00 */
/*0340*/ IMAD R2, R3, c[0x0][0x180], R0 ; /* 0x0000600003027a24 */
/* 0x000fc800078e0200 */
/*0350*/ IMAD.WIDE R2, R2, R5, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fc800078e0205 */
/*0360*/ IMAD.WIDE R4, R0, R5, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fe200078e0205 */
/*0370*/ STG.E.64 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe8000c101b04 */
/*0380*/ STG.E.64 [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe2000c101b04 */
/*0390*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03a0*/ BRA 0x3a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void StarRadKernel2 (double *Qbase2, double *Vrad, double *QStar, double dt, int nrad, int nsec, double *invdiffRmed, double *Rmed, double *dq)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
if (i<nrad && j<nsec){
if (Vrad[i*nsec + j] > 0.0 && i > 0)
QStar[i*nsec + j] = Qbase2[(i-1)*nsec + j] + (Rmed[i]-Rmed[i-1]-Vrad[i*nsec + j]*dt)*0.5*dq[i-1+j*nrad];
else
QStar[i*nsec + j] = Qbase2[i*nsec + j]-(Rmed[i+1]-Rmed[i]+Vrad[i*nsec + j]*dt)*0.5*dq[i+j*nrad];
}
if (i == 0 && j<nsec)
QStar[j] = QStar[j+nsec*nrad] = 0.0;
} | .file "tmpxft_000db82e_00000000-6_StarRadKernel2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z14StarRadKernel2PdS_S_diiS_S_S_PdS_S_diiS_S_S_
.type _Z47__device_stub__Z14StarRadKernel2PdS_S_diiS_S_S_PdS_S_diiS_S_S_, @function
_Z47__device_stub__Z14StarRadKernel2PdS_S_diiS_S_S_PdS_S_diiS_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movsd %xmm0, 32(%rsp)
movl %ecx, 28(%rsp)
movl %r8d, 24(%rsp)
movq %r9, 16(%rsp)
movq 224(%rsp), %rax
movq %rax, 8(%rsp)
movq 232(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 28(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movq %rsp, %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z14StarRadKernel2PdS_S_diiS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z14StarRadKernel2PdS_S_diiS_S_S_PdS_S_diiS_S_S_, .-_Z47__device_stub__Z14StarRadKernel2PdS_S_diiS_S_S_PdS_S_diiS_S_S_
.globl _Z14StarRadKernel2PdS_S_diiS_S_S_
.type _Z14StarRadKernel2PdS_S_diiS_S_S_, @function
_Z14StarRadKernel2PdS_S_diiS_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z47__device_stub__Z14StarRadKernel2PdS_S_diiS_S_S_PdS_S_diiS_S_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14StarRadKernel2PdS_S_diiS_S_S_, .-_Z14StarRadKernel2PdS_S_diiS_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z14StarRadKernel2PdS_S_diiS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14StarRadKernel2PdS_S_diiS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void StarRadKernel2 (double *Qbase2, double *Vrad, double *QStar, double dt, int nrad, int nsec, double *invdiffRmed, double *Rmed, double *dq)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
if (i<nrad && j<nsec){
if (Vrad[i*nsec + j] > 0.0 && i > 0)
QStar[i*nsec + j] = Qbase2[(i-1)*nsec + j] + (Rmed[i]-Rmed[i-1]-Vrad[i*nsec + j]*dt)*0.5*dq[i-1+j*nrad];
else
QStar[i*nsec + j] = Qbase2[i*nsec + j]-(Rmed[i+1]-Rmed[i]+Vrad[i*nsec + j]*dt)*0.5*dq[i+j*nrad];
}
if (i == 0 && j<nsec)
QStar[j] = QStar[j+nsec*nrad] = 0.0;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void StarRadKernel2 (double *Qbase2, double *Vrad, double *QStar, double dt, int nrad, int nsec, double *invdiffRmed, double *Rmed, double *dq)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
if (i<nrad && j<nsec){
if (Vrad[i*nsec + j] > 0.0 && i > 0)
QStar[i*nsec + j] = Qbase2[(i-1)*nsec + j] + (Rmed[i]-Rmed[i-1]-Vrad[i*nsec + j]*dt)*0.5*dq[i-1+j*nrad];
else
QStar[i*nsec + j] = Qbase2[i*nsec + j]-(Rmed[i+1]-Rmed[i]+Vrad[i*nsec + j]*dt)*0.5*dq[i+j*nrad];
}
if (i == 0 && j<nsec)
QStar[j] = QStar[j+nsec*nrad] = 0.0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void StarRadKernel2 (double *Qbase2, double *Vrad, double *QStar, double dt, int nrad, int nsec, double *invdiffRmed, double *Rmed, double *dq)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
if (i<nrad && j<nsec){
if (Vrad[i*nsec + j] > 0.0 && i > 0)
QStar[i*nsec + j] = Qbase2[(i-1)*nsec + j] + (Rmed[i]-Rmed[i-1]-Vrad[i*nsec + j]*dt)*0.5*dq[i-1+j*nrad];
else
QStar[i*nsec + j] = Qbase2[i*nsec + j]-(Rmed[i+1]-Rmed[i]+Vrad[i*nsec + j]*dt)*0.5*dq[i+j*nrad];
}
if (i == 0 && j<nsec)
QStar[j] = QStar[j+nsec*nrad] = 0.0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14StarRadKernel2PdS_S_diiS_S_S_
.globl _Z14StarRadKernel2PdS_S_diiS_S_S_
.p2align 8
.type _Z14StarRadKernel2PdS_S_diiS_S_S_,@function
_Z14StarRadKernel2PdS_S_diiS_S_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x4c
s_load_b64 s[16:17], s[0:1], 0x20
s_load_b64 s[12:13], s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
v_mad_u64_u32 v[0:1], null, s14, s3, v[4:5]
v_cmp_gt_i32_e64 s2, s16, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s17, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[14:15], s[0:1], 0x18
v_mad_u64_u32 v[4:5], null, v2, s17, v[0:1]
s_load_b128 s[8:11], s[0:1], 0x30
v_cmp_gt_i32_e64 s0, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[8:9], 3, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s2, s6, v8
v_add_co_ci_u32_e64 v7, s2, s7, v9, s2
global_load_b64 v[6:7], v[6:7], off
s_waitcnt vmcnt(0)
v_cmp_nlt_f64_e64 s2, 0, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, s0, s2
s_and_saveexec_b32 s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB0_3
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[10:11], 3, v[2:3]
v_mad_u64_u32 v[14:15], null, v0, s16, v[2:3]
v_add_co_u32 v10, s0, s8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v11, s0, s9, v11, s0
v_ashrrev_i32_e32 v15, 31, v14
v_add_co_u32 v8, s0, s4, v8
global_load_b128 v[10:13], v[10:11], off
v_add_co_ci_u32_e64 v9, s0, s5, v9, s0
v_lshlrev_b64 v[14:15], 3, v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v14, s0, s10, v14
v_add_co_ci_u32_e64 v15, s0, s11, v15, s0
global_load_b64 v[8:9], v[8:9], off
global_load_b64 v[14:15], v[14:15], off
s_waitcnt vmcnt(2)
v_add_f64 v[10:11], v[12:13], -v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], s[14:15], v[10:11]
v_mul_f64 v[6:7], v[6:7], -0.5
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[10:11], v[14:15], v[6:7], v[8:9]
.LBB0_3:
s_and_not1_saveexec_b32 s1, s1
s_cbranch_execz .LBB0_5
v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v8, -1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mov_b32_e32 v9, v3
v_lshlrev_b64 v[10:11], 3, v[2:3]
v_lshlrev_b64 v[12:13], 3, v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v9, s0, s8, v10
v_add_co_ci_u32_e64 v10, s0, s9, v11, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v11, s0, s8, v12
v_add_co_ci_u32_e64 v12, s0, s9, v13, s0
v_mad_u64_u32 v[13:14], null, v8, s17, v[0:1]
s_clause 0x1
global_load_b64 v[9:10], v[9:10], off
global_load_b64 v[11:12], v[11:12], off
v_ashrrev_i32_e32 v14, 31, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[13:14], 3, v[13:14]
v_add_co_u32 v13, s0, s4, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v14, s0, s5, v14, s0
s_waitcnt vmcnt(1)
v_mad_u64_u32 v[15:16], null, v0, s16, v[8:9]
s_waitcnt vmcnt(0)
v_add_f64 v[8:9], v[9:10], -v[11:12]
v_ashrrev_i32_e32 v16, 31, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[15:16], 3, v[15:16]
v_add_co_u32 v15, s0, s10, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v16, s0, s11, v16, s0
global_load_b64 v[13:14], v[13:14], off
global_load_b64 v[15:16], v[15:16], off
v_fma_f64 v[6:7], -v[6:7], s[14:15], v[8:9]
v_mul_f64 v[6:7], v[6:7], 0.5
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[10:11], v[15:16], v[6:7], v[13:14]
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s1
v_lshlrev_b64 v[3:4], 3, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s0, s12, v3
v_add_co_ci_u32_e64 v4, s0, s13, v4, s0
global_store_b64 v[3:4], v[10:11], off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s3
v_cmp_eq_u32_e64 s0, 0, v2
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_mad_u64_u32 v[2:3], null, s17, s16, v[0:1]
v_ashrrev_i32_e32 v1, 31, v0
s_mov_b32 s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s12, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s13, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s12, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v1, vcc_lo
s_clause 0x1
global_store_b64 v[2:3], v[4:5], off
global_store_b64 v[0:1], v[4:5], off
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14StarRadKernel2PdS_S_diiS_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14StarRadKernel2PdS_S_diiS_S_S_, .Lfunc_end0-_Z14StarRadKernel2PdS_S_diiS_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14StarRadKernel2PdS_S_diiS_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z14StarRadKernel2PdS_S_diiS_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void StarRadKernel2 (double *Qbase2, double *Vrad, double *QStar, double dt, int nrad, int nsec, double *invdiffRmed, double *Rmed, double *dq)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
if (i<nrad && j<nsec){
if (Vrad[i*nsec + j] > 0.0 && i > 0)
QStar[i*nsec + j] = Qbase2[(i-1)*nsec + j] + (Rmed[i]-Rmed[i-1]-Vrad[i*nsec + j]*dt)*0.5*dq[i-1+j*nrad];
else
QStar[i*nsec + j] = Qbase2[i*nsec + j]-(Rmed[i+1]-Rmed[i]+Vrad[i*nsec + j]*dt)*0.5*dq[i+j*nrad];
}
if (i == 0 && j<nsec)
QStar[j] = QStar[j+nsec*nrad] = 0.0;
} | .text
.file "StarRadKernel2.hip"
.globl _Z29__device_stub__StarRadKernel2PdS_S_diiS_S_S_ # -- Begin function _Z29__device_stub__StarRadKernel2PdS_S_diiS_S_S_
.p2align 4, 0x90
.type _Z29__device_stub__StarRadKernel2PdS_S_diiS_S_S_,@function
_Z29__device_stub__StarRadKernel2PdS_S_diiS_S_S_: # @_Z29__device_stub__StarRadKernel2PdS_S_diiS_S_S_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movsd %xmm0, 64(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %r9, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rax
movq %rax, 144(%rsp)
leaq 176(%rsp), %rax
movq %rax, 152(%rsp)
leaq 184(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14StarRadKernel2PdS_S_diiS_S_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z29__device_stub__StarRadKernel2PdS_S_diiS_S_S_, .Lfunc_end0-_Z29__device_stub__StarRadKernel2PdS_S_diiS_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14StarRadKernel2PdS_S_diiS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14StarRadKernel2PdS_S_diiS_S_S_,@object # @_Z14StarRadKernel2PdS_S_diiS_S_S_
.section .rodata,"a",@progbits
.globl _Z14StarRadKernel2PdS_S_diiS_S_S_
.p2align 3, 0x0
_Z14StarRadKernel2PdS_S_diiS_S_S_:
.quad _Z29__device_stub__StarRadKernel2PdS_S_diiS_S_S_
.size _Z14StarRadKernel2PdS_S_diiS_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14StarRadKernel2PdS_S_diiS_S_S_"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__StarRadKernel2PdS_S_diiS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14StarRadKernel2PdS_S_diiS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14StarRadKernel2PdS_S_diiS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x310 ; /* 0x000002d000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0050*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e680000002600 */
/*0060*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0080*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x184], PT ; /* 0x0000610000007a0c */
/* 0x000fe20003f06270 */
/*0090*/ IMAD R9, R9, c[0x0][0x4], R2 ; /* 0x0000010009097a24 */
/* 0x002fca00078e0202 */
/*00a0*/ ISETP.GE.OR P1, PT, R9.reuse, c[0x0][0x180], P0 ; /* 0x0000600009007a0c */
/* 0x040fe40000726670 */
/*00b0*/ ISETP.NE.OR P0, PT, R9, RZ, P0 ; /* 0x000000ff0900720c */
/* 0x000fd60000705670 */
/*00c0*/ @P1 BRA 0x300 ; /* 0x0000023000001947 */
/* 0x000fea0003800000 */
/*00d0*/ HFMA2.MMA R8, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff087435 */
/* 0x000fe200000001ff */
/*00e0*/ IMAD R3, R9, c[0x0][0x184], R0 ; /* 0x0000610009037a24 */
/* 0x000fd200078e0200 */
/*00f0*/ IMAD.WIDE R4, R3, R8, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fcc00078e0208 */
/*0100*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*0110*/ IMAD.WIDE R10, R9, R8, c[0x0][0x190] ; /* 0x00006400090a7625 */
/* 0x000fe200078e0208 */
/*0120*/ SHF.R.S32.HI R2, RZ, 0x1f, R3 ; /* 0x0000001fff027819 */
/* 0x000fc60000011403 */
/*0130*/ IMAD R7, R0, c[0x0][0x180], R9 ; /* 0x0000600000077a24 */
/* 0x000fc800078e0209 */
/*0140*/ IMAD.WIDE R6, R7, R8, c[0x0][0x198] ; /* 0x0000660007067625 */
/* 0x000fe200078e0208 */
/*0150*/ DSETP.GT.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400722a */
/* 0x004e0c0003f24000 */
/*0160*/ ISETP.GT.AND P1, PT, R9, RZ, P1 ; /* 0x000000ff0900720c */
/* 0x001fda0000f24270 */
/*0170*/ @!P1 LDG.E.64 R14, [R10.64] ; /* 0x000000040a0e9981 */
/* 0x000ea8000c1e1b00 */
/*0180*/ @!P1 LDG.E.64 R16, [R10.64+0x8] ; /* 0x000008040a109981 */
/* 0x000ea2000c1e1b00 */
/*0190*/ @!P1 LEA R20, P2, R3, c[0x0][0x160], 0x3 ; /* 0x0000580003149a11 */
/* 0x000fc600078418ff */
/*01a0*/ @!P1 LDG.E.64 R12, [R6.64] ; /* 0x00000004060c9981 */
/* 0x000ee2000c1e1b00 */
/*01b0*/ @!P1 LEA.HI.X R21, R3, c[0x0][0x164], R2, 0x3, P2 ; /* 0x0000590003159a11 */
/* 0x000fca00010f1c02 */
/*01c0*/ @!P1 LDG.E.64 R18, [R20.64] ; /* 0x0000000414129981 */
/* 0x000ee2000c1e1b00 */
/*01d0*/ IMAD.WIDE R2, R3, R8, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fe200078e0208 */
/*01e0*/ @!P1 DADD R14, -R14, R16 ; /* 0x000000000e0e9229 */
/* 0x004e0c0000000110 */
/*01f0*/ @!P1 DFMA R14, R4, c[0x0][0x178], R14 ; /* 0x00005e00040e9a2b */
/* 0x001e0c000000000e */
/*0200*/ @!P1 DMUL R14, R14, -0.5 ; /* 0xbfe000000e0e9828 */
/* 0x001ee20000000000 */
/*0210*/ @P1 MOV R16, c[0x0][0x184] ; /* 0x0000610000101a02 */
/* 0x000fca0000000f00 */
/*0220*/ @!P1 DFMA R18, R14, R12, R18 ; /* 0x0000000c0e12922b */
/* 0x008e220000000012 */
/*0230*/ @P1 IMAD R9, R9, R16, -c[0x0][0x184] ; /* 0x8000610009091624 */
/* 0x000fcc00078e0210 */
/*0240*/ @!P1 STG.E.64 [R2.64], R18 ; /* 0x0000001202009986 */
/* 0x0011e8000c101b04 */
/*0250*/ @P1 LDG.E.64 R12, [R10.64+-0x8] ; /* 0xfffff8040a0c1981 */
/* 0x000ea8000c1e1b00 */
/*0260*/ @P1 LDG.E.64 R14, [R10.64] ; /* 0x000000040a0e1981 */
/* 0x000ea2000c1e1b00 */
/*0270*/ @P1 IADD3 R9, R0, R9, RZ ; /* 0x0000000900091210 */
/* 0x000fc60007ffe0ff */
/*0280*/ @P1 LDG.E.64 R6, [R6.64+-0x8] ; /* 0xfffff80406061981 */
/* 0x000ee4000c1e1b00 */
/*0290*/ @P1 IMAD.WIDE R8, R9, R8, c[0x0][0x160] ; /* 0x0000580009081625 */
/* 0x000fcc00078e0208 */
/*02a0*/ @P1 LDG.E.64 R8, [R8.64] ; /* 0x0000000408081981 */
/* 0x000ee2000c1e1b00 */
/*02b0*/ @P1 DADD R12, -R12, R14 ; /* 0x000000000c0c1229 */
/* 0x004e4c000000010e */
/*02c0*/ @P1 DFMA R12, -R4, c[0x0][0x178], R12 ; /* 0x00005e00040c1a2b */
/* 0x002e4c000000010c */
/*02d0*/ @P1 DMUL R12, R12, 0.5 ; /* 0x3fe000000c0c1828 */
/* 0x002ecc0000000000 */
/*02e0*/ @P1 DFMA R12, R12, R6, R8 ; /* 0x000000060c0c122b */
/* 0x008e4e0000000008 */
/*02f0*/ @P1 STG.E.64 [R2.64], R12 ; /* 0x0000000c02001986 */
/* 0x0021e8000c101b04 */
/*0300*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0310*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0320*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0330*/ MOV R3, c[0x0][0x184] ; /* 0x0000610000037a02 */
/* 0x001fca0000000f00 */
/*0340*/ IMAD R2, R3, c[0x0][0x180], R0 ; /* 0x0000600003027a24 */
/* 0x000fc800078e0200 */
/*0350*/ IMAD.WIDE R2, R2, R5, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fc800078e0205 */
/*0360*/ IMAD.WIDE R4, R0, R5, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fe200078e0205 */
/*0370*/ STG.E.64 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe8000c101b04 */
/*0380*/ STG.E.64 [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe2000c101b04 */
/*0390*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03a0*/ BRA 0x3a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14StarRadKernel2PdS_S_diiS_S_S_
.globl _Z14StarRadKernel2PdS_S_diiS_S_S_
.p2align 8
.type _Z14StarRadKernel2PdS_S_diiS_S_S_,@function
_Z14StarRadKernel2PdS_S_diiS_S_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x4c
s_load_b64 s[16:17], s[0:1], 0x20
s_load_b64 s[12:13], s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
v_mad_u64_u32 v[0:1], null, s14, s3, v[4:5]
v_cmp_gt_i32_e64 s2, s16, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s17, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[14:15], s[0:1], 0x18
v_mad_u64_u32 v[4:5], null, v2, s17, v[0:1]
s_load_b128 s[8:11], s[0:1], 0x30
v_cmp_gt_i32_e64 s0, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[8:9], 3, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s2, s6, v8
v_add_co_ci_u32_e64 v7, s2, s7, v9, s2
global_load_b64 v[6:7], v[6:7], off
s_waitcnt vmcnt(0)
v_cmp_nlt_f64_e64 s2, 0, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, s0, s2
s_and_saveexec_b32 s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB0_3
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[10:11], 3, v[2:3]
v_mad_u64_u32 v[14:15], null, v0, s16, v[2:3]
v_add_co_u32 v10, s0, s8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v11, s0, s9, v11, s0
v_ashrrev_i32_e32 v15, 31, v14
v_add_co_u32 v8, s0, s4, v8
global_load_b128 v[10:13], v[10:11], off
v_add_co_ci_u32_e64 v9, s0, s5, v9, s0
v_lshlrev_b64 v[14:15], 3, v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v14, s0, s10, v14
v_add_co_ci_u32_e64 v15, s0, s11, v15, s0
global_load_b64 v[8:9], v[8:9], off
global_load_b64 v[14:15], v[14:15], off
s_waitcnt vmcnt(2)
v_add_f64 v[10:11], v[12:13], -v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], s[14:15], v[10:11]
v_mul_f64 v[6:7], v[6:7], -0.5
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[10:11], v[14:15], v[6:7], v[8:9]
.LBB0_3:
s_and_not1_saveexec_b32 s1, s1
s_cbranch_execz .LBB0_5
v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v8, -1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mov_b32_e32 v9, v3
v_lshlrev_b64 v[10:11], 3, v[2:3]
v_lshlrev_b64 v[12:13], 3, v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v9, s0, s8, v10
v_add_co_ci_u32_e64 v10, s0, s9, v11, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v11, s0, s8, v12
v_add_co_ci_u32_e64 v12, s0, s9, v13, s0
v_mad_u64_u32 v[13:14], null, v8, s17, v[0:1]
s_clause 0x1
global_load_b64 v[9:10], v[9:10], off
global_load_b64 v[11:12], v[11:12], off
v_ashrrev_i32_e32 v14, 31, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[13:14], 3, v[13:14]
v_add_co_u32 v13, s0, s4, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v14, s0, s5, v14, s0
s_waitcnt vmcnt(1)
v_mad_u64_u32 v[15:16], null, v0, s16, v[8:9]
s_waitcnt vmcnt(0)
v_add_f64 v[8:9], v[9:10], -v[11:12]
v_ashrrev_i32_e32 v16, 31, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[15:16], 3, v[15:16]
v_add_co_u32 v15, s0, s10, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v16, s0, s11, v16, s0
global_load_b64 v[13:14], v[13:14], off
global_load_b64 v[15:16], v[15:16], off
v_fma_f64 v[6:7], -v[6:7], s[14:15], v[8:9]
v_mul_f64 v[6:7], v[6:7], 0.5
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[10:11], v[15:16], v[6:7], v[13:14]
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s1
v_lshlrev_b64 v[3:4], 3, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s0, s12, v3
v_add_co_ci_u32_e64 v4, s0, s13, v4, s0
global_store_b64 v[3:4], v[10:11], off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s3
v_cmp_eq_u32_e64 s0, 0, v2
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_mad_u64_u32 v[2:3], null, s17, s16, v[0:1]
v_ashrrev_i32_e32 v1, 31, v0
s_mov_b32 s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s12, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s13, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s12, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v1, vcc_lo
s_clause 0x1
global_store_b64 v[2:3], v[4:5], off
global_store_b64 v[0:1], v[4:5], off
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14StarRadKernel2PdS_S_diiS_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14StarRadKernel2PdS_S_diiS_S_S_, .Lfunc_end0-_Z14StarRadKernel2PdS_S_diiS_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14StarRadKernel2PdS_S_diiS_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z14StarRadKernel2PdS_S_diiS_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000db82e_00000000-6_StarRadKernel2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z14StarRadKernel2PdS_S_diiS_S_S_PdS_S_diiS_S_S_
.type _Z47__device_stub__Z14StarRadKernel2PdS_S_diiS_S_S_PdS_S_diiS_S_S_, @function
_Z47__device_stub__Z14StarRadKernel2PdS_S_diiS_S_S_PdS_S_diiS_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movsd %xmm0, 32(%rsp)
movl %ecx, 28(%rsp)
movl %r8d, 24(%rsp)
movq %r9, 16(%rsp)
movq 224(%rsp), %rax
movq %rax, 8(%rsp)
movq 232(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 28(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movq %rsp, %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z14StarRadKernel2PdS_S_diiS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z14StarRadKernel2PdS_S_diiS_S_S_PdS_S_diiS_S_S_, .-_Z47__device_stub__Z14StarRadKernel2PdS_S_diiS_S_S_PdS_S_diiS_S_S_
.globl _Z14StarRadKernel2PdS_S_diiS_S_S_
.type _Z14StarRadKernel2PdS_S_diiS_S_S_, @function
_Z14StarRadKernel2PdS_S_diiS_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z47__device_stub__Z14StarRadKernel2PdS_S_diiS_S_S_PdS_S_diiS_S_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14StarRadKernel2PdS_S_diiS_S_S_, .-_Z14StarRadKernel2PdS_S_diiS_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z14StarRadKernel2PdS_S_diiS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14StarRadKernel2PdS_S_diiS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "StarRadKernel2.hip"
.globl _Z29__device_stub__StarRadKernel2PdS_S_diiS_S_S_ # -- Begin function _Z29__device_stub__StarRadKernel2PdS_S_diiS_S_S_
.p2align 4, 0x90
.type _Z29__device_stub__StarRadKernel2PdS_S_diiS_S_S_,@function
_Z29__device_stub__StarRadKernel2PdS_S_diiS_S_S_: # @_Z29__device_stub__StarRadKernel2PdS_S_diiS_S_S_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movsd %xmm0, 64(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %r9, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rax
movq %rax, 144(%rsp)
leaq 176(%rsp), %rax
movq %rax, 152(%rsp)
leaq 184(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14StarRadKernel2PdS_S_diiS_S_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z29__device_stub__StarRadKernel2PdS_S_diiS_S_S_, .Lfunc_end0-_Z29__device_stub__StarRadKernel2PdS_S_diiS_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14StarRadKernel2PdS_S_diiS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14StarRadKernel2PdS_S_diiS_S_S_,@object # @_Z14StarRadKernel2PdS_S_diiS_S_S_
.section .rodata,"a",@progbits
.globl _Z14StarRadKernel2PdS_S_diiS_S_S_
.p2align 3, 0x0
_Z14StarRadKernel2PdS_S_diiS_S_S_:
.quad _Z29__device_stub__StarRadKernel2PdS_S_diiS_S_S_
.size _Z14StarRadKernel2PdS_S_diiS_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14StarRadKernel2PdS_S_diiS_S_S_"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__StarRadKernel2PdS_S_diiS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14StarRadKernel2PdS_S_diiS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cufft.h>
#include <fstream>
int main(){
// Initializing variables
int n = 1024;
cufftHandle plan1d;
double2 *h_a, *d_a, *h_b;
std::ofstream time_out("time_out.dat"), freq_out("freq_out.dat");
// Allocations / definition
h_a = (double2 *)malloc(sizeof(double2)*n);
h_b = (double2 *)malloc(sizeof(double2)*n);
for (int i = 0; i < n; ++i){
h_a[i].x = sin(20*2*M_PI*i/n);
h_a[i].y = 0;
}
cudaMalloc(&d_a, sizeof(double2)*n);
cudaMemcpy(d_a, h_a, sizeof(double2)*n, cudaMemcpyHostToDevice);
cufftPlan1d(&plan1d, n, CUFFT_Z2Z, 1);
// FFT
cufftExecZ2Z(plan1d, d_a, d_a, CUFFT_FORWARD);
// Copying back
cudaMemcpy(h_b, d_a, sizeof(double2)*n, cudaMemcpyDeviceToHost);
for (int i = 0; i < n; ++i){
time_out << h_a[i].x << '\n';
freq_out << sqrt(h_b[i].x*h_b[i].x + h_b[i].y*h_b[i].y) << '\n';
}
time_out.close();
freq_out.close();
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cufft.h>
#include <fstream>
int main(){
// Initializing variables
int n = 1024;
cufftHandle plan1d;
double2 *h_a, *d_a, *h_b;
std::ofstream time_out("time_out.dat"), freq_out("freq_out.dat");
// Allocations / definition
h_a = (double2 *)malloc(sizeof(double2)*n);
h_b = (double2 *)malloc(sizeof(double2)*n);
for (int i = 0; i < n; ++i){
h_a[i].x = sin(20*2*M_PI*i/n);
h_a[i].y = 0;
}
cudaMalloc(&d_a, sizeof(double2)*n);
cudaMemcpy(d_a, h_a, sizeof(double2)*n, cudaMemcpyHostToDevice);
cufftPlan1d(&plan1d, n, CUFFT_Z2Z, 1);
// FFT
cufftExecZ2Z(plan1d, d_a, d_a, CUFFT_FORWARD);
// Copying back
cudaMemcpy(h_b, d_a, sizeof(double2)*n, cudaMemcpyDeviceToHost);
for (int i = 0; i < n; ++i){
time_out << h_a[i].x << '\n';
freq_out << sqrt(h_b[i].x*h_b[i].x + h_b[i].y*h_b[i].y) << '\n';
}
time_out.close();
freq_out.close();
} | .file "tmpxft_000aa28a_00000000-6_cufft.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3826:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3826:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3849:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3849:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "time_out.dat"
.LC1:
.string "freq_out.dat"
.text
.globl main
.type main, @function
main:
.LFB3823:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3823
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $1064, %rsp
.cfi_def_cfa_offset 1104
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $16, %edx
leaq .LC0(%rip), %rsi
.LEHB0:
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE0:
leaq 528(%rsp), %rdi
movl $16, %edx
leaq .LC1(%rip), %rsi
.LEHB1:
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE1:
movl $16384, %edi
call malloc@PLT
movq %rax, %r12
movl $16384, %edi
call malloc@PLT
movq %rax, %rbp
movq %r12, %r13
movl $0, %ebx
.L6:
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
mulsd .LC2(%rip), %xmm0
mulsd .LC3(%rip), %xmm0
call sin@PLT
movsd %xmm0, 0(%r13)
movq $0x000000000, 8(%r13)
addl $1, %ebx
addq $16, %r13
cmpl $1024, %ebx
jne .L6
leaq 8(%rsp), %rdi
movl $16384, %esi
.LEHB2:
call cudaMalloc@PLT
movl $1, %ecx
movl $16384, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4(%rsp), %rdi
movl $1, %ecx
movl $105, %edx
movl $1024, %esi
call cufftPlan1d@PLT
movq 8(%rsp), %rsi
movl $-1, %ecx
movq %rsi, %rdx
movl 4(%rsp), %edi
call cufftExecZ2Z@PLT
movl $2, %ecx
movl $16384, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq 16(%rsp), %r13
jmp .L11
.L23:
movq %rax, %rdi
movb $10, 2(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L7
leaq 2(%rsp), %rsi
movl $1, %edx
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L8
.L7:
movl $10, %esi
call _ZNSo3putEc@PLT
.L8:
movsd 0(%rbp,%rbx), %xmm0
movsd 8(%rbp,%rbx), %xmm1
mulsd %xmm0, %xmm0
mulsd %xmm1, %xmm1
addsd %xmm1, %xmm0
sqrtsd %xmm0, %xmm0
leaq 528(%rsp), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movb $10, 3(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L9
leaq 3(%rsp), %rsi
movl $1, %edx
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L10
.L9:
movl $10, %esi
call _ZNSo3putEc@PLT
.L10:
addq $16, %rbx
cmpq $16384, %rbx
je .L22
.L11:
movsd (%r12,%rbx), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
jmp .L23
.L22:
leaq 16(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
leaq 528(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
.LEHE2:
leaq 528(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
leaq 16(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 528(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
.L13:
leaq 16(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 1048(%rsp), %rax
subq %fs:40, %rax
je .L14
call __stack_chk_fail@PLT
.L16:
endbr64
movq %rax, %rbx
jmp .L13
.L14:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3823:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3823:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3823-.LLSDACSB3823
.LLSDACSB3823:
.uleb128 .LEHB0-.LFB3823
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3823
.uleb128 .LEHE1-.LEHB1
.uleb128 .L16-.LFB3823
.uleb128 0
.uleb128 .LEHB2-.LFB3823
.uleb128 .LEHE2-.LEHB2
.uleb128 .L17-.LFB3823
.uleb128 0
.uleb128 .LEHB3-.LFB3823
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE3823:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 693450846
.long 1079995002
.align 8
.LC3:
.long 0
.long 1062207488
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cufft.h>
#include <fstream>
int main(){
// Initializing variables
int n = 1024;
cufftHandle plan1d;
double2 *h_a, *d_a, *h_b;
std::ofstream time_out("time_out.dat"), freq_out("freq_out.dat");
// Allocations / definition
h_a = (double2 *)malloc(sizeof(double2)*n);
h_b = (double2 *)malloc(sizeof(double2)*n);
for (int i = 0; i < n; ++i){
h_a[i].x = sin(20*2*M_PI*i/n);
h_a[i].y = 0;
}
cudaMalloc(&d_a, sizeof(double2)*n);
cudaMemcpy(d_a, h_a, sizeof(double2)*n, cudaMemcpyHostToDevice);
cufftPlan1d(&plan1d, n, CUFFT_Z2Z, 1);
// FFT
cufftExecZ2Z(plan1d, d_a, d_a, CUFFT_FORWARD);
// Copying back
cudaMemcpy(h_b, d_a, sizeof(double2)*n, cudaMemcpyDeviceToHost);
for (int i = 0; i < n; ++i){
time_out << h_a[i].x << '\n';
freq_out << sqrt(h_b[i].x*h_b[i].x + h_b[i].y*h_b[i].y) << '\n';
}
time_out.close();
freq_out.close();
} | #include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
#include <fstream>
int main(){
// Initializing variables
int n = 1024;
hipfftHandle plan1d;
double2 *h_a, *d_a, *h_b;
std::ofstream time_out("time_out.dat"), freq_out("freq_out.dat");
// Allocations / definition
h_a = (double2 *)malloc(sizeof(double2)*n);
h_b = (double2 *)malloc(sizeof(double2)*n);
for (int i = 0; i < n; ++i){
h_a[i].x = sin(20*2*M_PI*i/n);
h_a[i].y = 0;
}
hipMalloc(&d_a, sizeof(double2)*n);
hipMemcpy(d_a, h_a, sizeof(double2)*n, hipMemcpyHostToDevice);
hipfftPlan1d(&plan1d, n, HIPFFT_Z2Z, 1);
// FFT
hipfftExecZ2Z(plan1d, d_a, d_a, HIPFFT_FORWARD);
// Copying back
hipMemcpy(h_b, d_a, sizeof(double2)*n, hipMemcpyDeviceToHost);
for (int i = 0; i < n; ++i){
time_out << h_a[i].x << '\n';
freq_out << sqrt(h_b[i].x*h_b[i].x + h_b[i].y*h_b[i].y) << '\n';
}
time_out.close();
freq_out.close();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
#include <fstream>
int main(){
// Initializing variables
int n = 1024;
hipfftHandle plan1d;
double2 *h_a, *d_a, *h_b;
std::ofstream time_out("time_out.dat"), freq_out("freq_out.dat");
// Allocations / definition
h_a = (double2 *)malloc(sizeof(double2)*n);
h_b = (double2 *)malloc(sizeof(double2)*n);
for (int i = 0; i < n; ++i){
h_a[i].x = sin(20*2*M_PI*i/n);
h_a[i].y = 0;
}
hipMalloc(&d_a, sizeof(double2)*n);
hipMemcpy(d_a, h_a, sizeof(double2)*n, hipMemcpyHostToDevice);
hipfftPlan1d(&plan1d, n, HIPFFT_Z2Z, 1);
// FFT
hipfftExecZ2Z(plan1d, d_a, d_a, HIPFFT_FORWARD);
// Copying back
hipMemcpy(h_b, d_a, sizeof(double2)*n, hipMemcpyDeviceToHost);
for (int i = 0; i < n; ++i){
time_out << h_a[i].x << '\n';
freq_out << sqrt(h_b[i].x*h_b[i].x + h_b[i].y*h_b[i].y) << '\n';
}
time_out.close();
freq_out.close();
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
#include <fstream>
int main(){
// Initializing variables
int n = 1024;
hipfftHandle plan1d;
double2 *h_a, *d_a, *h_b;
std::ofstream time_out("time_out.dat"), freq_out("freq_out.dat");
// Allocations / definition
h_a = (double2 *)malloc(sizeof(double2)*n);
h_b = (double2 *)malloc(sizeof(double2)*n);
for (int i = 0; i < n; ++i){
h_a[i].x = sin(20*2*M_PI*i/n);
h_a[i].y = 0;
}
hipMalloc(&d_a, sizeof(double2)*n);
hipMemcpy(d_a, h_a, sizeof(double2)*n, hipMemcpyHostToDevice);
hipfftPlan1d(&plan1d, n, HIPFFT_Z2Z, 1);
// FFT
hipfftExecZ2Z(plan1d, d_a, d_a, HIPFFT_FORWARD);
// Copying back
hipMemcpy(h_b, d_a, sizeof(double2)*n, hipMemcpyDeviceToHost);
for (int i = 0; i < n; ++i){
time_out << h_a[i].x << '\n';
freq_out << sqrt(h_b[i].x*h_b[i].x + h_b[i].y*h_b[i].y) << '\n';
}
time_out.close();
freq_out.close();
} | .text
.file "cufft.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x405f6a7a2955385e # double 125.66370614359172
.LCPI0_1:
.quad 0x3f50000000000000 # double 9.765625E-4
.LCPI0_2:
.quad 0x0000000000000000 # double 0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1048, %rsp # imm = 0x418
.cfi_def_cfa_offset 1104
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 536(%rsp), %rdi
movl $.L.str, %esi
movl $16, %edx
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
.Ltmp0:
leaq 24(%rsp), %rdi
movl $.L.str.1, %esi
movl $16, %edx
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
.Ltmp1:
# %bb.1:
movl $16384, %edi # imm = 0x4000
callq malloc
movq %rax, %rbx
movl $16384, %edi # imm = 0x4000
callq malloc
movq %rax, %r14
movq %rbx, %r15
addq $8, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_2: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %r12d, %xmm0
mulsd .LCPI0_0(%rip), %xmm0
mulsd .LCPI0_1(%rip), %xmm0
callq sin
movsd %xmm0, -8(%r15)
movq $0, (%r15)
incq %r12
addq $16, %r15
cmpq $1024, %r12 # imm = 0x400
jne .LBB0_2
# %bb.3:
.Ltmp3:
leaq 8(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
.Ltmp4:
# %bb.4: # %_ZL9hipMallocI15HIP_vector_typeIdLj2EEE10hipError_tPPT_m.exit
movq 8(%rsp), %rdi
.Ltmp5:
movl $16384, %edx # imm = 0x4000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp6:
# %bb.5:
.Ltmp7:
leaq 16(%rsp), %rdi
movl $1024, %esi # imm = 0x400
movl $105, %edx
movl $1, %ecx
callq hipfftPlan1d
.Ltmp8:
# %bb.6:
movq 16(%rsp), %rdi
movq 8(%rsp), %rdx
.Ltmp9:
movq %rdx, %rsi
movl $-1, %ecx
callq hipfftExecZ2Z
.Ltmp10:
# %bb.7:
movq 8(%rsp), %rsi
.Ltmp11:
movl $16384, %edx # imm = 0x4000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp12:
# %bb.8: # %.preheader.preheader
xorl %ebp, %ebp
leaq 536(%rsp), %r15
leaq 24(%rsp), %r12
leaq 7(%rsp), %r13
jmp .LBB0_9
.p2align 4, 0x90
.LBB0_26: # in Loop: Header=BB0_9 Depth=1
.Ltmp23:
movq %rax, %rdi
movl $10, %esi
callq _ZNSo3putEc
.Ltmp24:
.LBB0_27: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit49
# in Loop: Header=BB0_9 Depth=1
addq $16, %rbp
cmpq $16384, %rbp # imm = 0x4000
je .LBB0_12
.LBB0_9: # %.preheader
# =>This Inner Loop Header: Depth=1
movsd (%rbx,%rbp), %xmm0 # xmm0 = mem[0],zero
.Ltmp13:
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp14:
# %bb.10: # %_ZNSolsEd.exit
# in Loop: Header=BB0_9 Depth=1
movb $10, 7(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB0_19
# %bb.11: # in Loop: Header=BB0_9 Depth=1
.Ltmp15:
movl $1, %edx
movq %rax, %rdi
movq %r13, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp16:
jmp .LBB0_20
.p2align 4, 0x90
.LBB0_19: # in Loop: Header=BB0_9 Depth=1
.Ltmp17:
movq %rax, %rdi
movl $10, %esi
callq _ZNSo3putEc
.Ltmp18:
.LBB0_20: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
# in Loop: Header=BB0_9 Depth=1
movsd (%r14,%rbp), %xmm1 # xmm1 = mem[0],zero
movsd 8(%r14,%rbp), %xmm0 # xmm0 = mem[0],zero
mulsd %xmm1, %xmm1
mulsd %xmm0, %xmm0
addsd %xmm1, %xmm0
ucomisd .LCPI0_2(%rip), %xmm0
jb .LBB0_22
# %bb.21: # in Loop: Header=BB0_9 Depth=1
sqrtsd %xmm0, %xmm0
jmp .LBB0_23
.p2align 4, 0x90
.LBB0_22: # %call.sqrt
# in Loop: Header=BB0_9 Depth=1
callq sqrt
.LBB0_23: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit.split
# in Loop: Header=BB0_9 Depth=1
.Ltmp19:
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp20:
# %bb.24: # %_ZNSolsEd.exit44
# in Loop: Header=BB0_9 Depth=1
movb $10, 7(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB0_26
# %bb.25: # in Loop: Header=BB0_9 Depth=1
.Ltmp21:
movl $1, %edx
movq %rax, %rdi
movq %r13, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp22:
jmp .LBB0_27
.LBB0_12:
leaq 544(%rsp), %rdi
.Ltmp26:
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp27:
# %bb.13: # %.noexc
testq %rax, %rax
jne .LBB0_15
# %bb.14:
movq 536(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $536, %rdi # imm = 0x218
movl 568(%rsp,%rax), %esi
orl $4, %esi
.Ltmp28:
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp29:
.LBB0_15: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv.exit
leaq 32(%rsp), %rdi
.Ltmp30:
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp31:
# %bb.16: # %.noexc51
testq %rax, %rax
jne .LBB0_18
# %bb.17:
movq 24(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $24, %rdi
movl 56(%rsp,%rax), %esi
orl $4, %esi
.Ltmp32:
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp33:
.LBB0_18: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv.exit53
leaq 24(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
leaq 536(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
xorl %eax, %eax
addq $1048, %rsp # imm = 0x418
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_32:
.cfi_def_cfa_offset 1104
.Ltmp2:
movq %rax, %rbx
jmp .LBB0_31
.LBB0_29:
.Ltmp34:
jmp .LBB0_30
.LBB0_28:
.Ltmp25:
.LBB0_30:
movq %rax, %rbx
leaq 24(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
.LBB0_31:
leaq 536(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp12-.Ltmp3 # Call between .Ltmp3 and .Ltmp12
.uleb128 .Ltmp34-.Lfunc_begin0 # jumps to .Ltmp34
.byte 0 # On action: cleanup
.uleb128 .Ltmp23-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp22-.Ltmp23 # Call between .Ltmp23 and .Ltmp22
.uleb128 .Ltmp25-.Lfunc_begin0 # jumps to .Ltmp25
.byte 0 # On action: cleanup
.uleb128 .Ltmp26-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp33-.Ltmp26 # Call between .Ltmp26 and .Ltmp33
.uleb128 .Ltmp34-.Lfunc_begin0 # jumps to .Ltmp34
.byte 0 # On action: cleanup
.uleb128 .Ltmp33-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Lfunc_end0-.Ltmp33 # Call between .Ltmp33 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "time_out.dat"
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "freq_out.dat"
.size .L.str.1, 13
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000aa28a_00000000-6_cufft.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3826:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3826:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3849:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3849:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "time_out.dat"
.LC1:
.string "freq_out.dat"
.text
.globl main
.type main, @function
main:
.LFB3823:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3823
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $1064, %rsp
.cfi_def_cfa_offset 1104
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $16, %edx
leaq .LC0(%rip), %rsi
.LEHB0:
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE0:
leaq 528(%rsp), %rdi
movl $16, %edx
leaq .LC1(%rip), %rsi
.LEHB1:
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE1:
movl $16384, %edi
call malloc@PLT
movq %rax, %r12
movl $16384, %edi
call malloc@PLT
movq %rax, %rbp
movq %r12, %r13
movl $0, %ebx
.L6:
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
mulsd .LC2(%rip), %xmm0
mulsd .LC3(%rip), %xmm0
call sin@PLT
movsd %xmm0, 0(%r13)
movq $0x000000000, 8(%r13)
addl $1, %ebx
addq $16, %r13
cmpl $1024, %ebx
jne .L6
leaq 8(%rsp), %rdi
movl $16384, %esi
.LEHB2:
call cudaMalloc@PLT
movl $1, %ecx
movl $16384, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4(%rsp), %rdi
movl $1, %ecx
movl $105, %edx
movl $1024, %esi
call cufftPlan1d@PLT
movq 8(%rsp), %rsi
movl $-1, %ecx
movq %rsi, %rdx
movl 4(%rsp), %edi
call cufftExecZ2Z@PLT
movl $2, %ecx
movl $16384, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq 16(%rsp), %r13
jmp .L11
.L23:
movq %rax, %rdi
movb $10, 2(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L7
leaq 2(%rsp), %rsi
movl $1, %edx
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L8
.L7:
movl $10, %esi
call _ZNSo3putEc@PLT
.L8:
movsd 0(%rbp,%rbx), %xmm0
movsd 8(%rbp,%rbx), %xmm1
mulsd %xmm0, %xmm0
mulsd %xmm1, %xmm1
addsd %xmm1, %xmm0
sqrtsd %xmm0, %xmm0
leaq 528(%rsp), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movb $10, 3(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L9
leaq 3(%rsp), %rsi
movl $1, %edx
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L10
.L9:
movl $10, %esi
call _ZNSo3putEc@PLT
.L10:
addq $16, %rbx
cmpq $16384, %rbx
je .L22
.L11:
movsd (%r12,%rbx), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
jmp .L23
.L22:
leaq 16(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
leaq 528(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
.LEHE2:
leaq 528(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
leaq 16(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 528(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
.L13:
leaq 16(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 1048(%rsp), %rax
subq %fs:40, %rax
je .L14
call __stack_chk_fail@PLT
.L16:
endbr64
movq %rax, %rbx
jmp .L13
.L14:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3823:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3823:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3823-.LLSDACSB3823
.LLSDACSB3823:
.uleb128 .LEHB0-.LFB3823
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3823
.uleb128 .LEHE1-.LEHB1
.uleb128 .L16-.LFB3823
.uleb128 0
.uleb128 .LEHB2-.LFB3823
.uleb128 .LEHE2-.LEHB2
.uleb128 .L17-.LFB3823
.uleb128 0
.uleb128 .LEHB3-.LFB3823
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE3823:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 693450846
.long 1079995002
.align 8
.LC3:
.long 0
.long 1062207488
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cufft.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x405f6a7a2955385e # double 125.66370614359172
.LCPI0_1:
.quad 0x3f50000000000000 # double 9.765625E-4
.LCPI0_2:
.quad 0x0000000000000000 # double 0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1048, %rsp # imm = 0x418
.cfi_def_cfa_offset 1104
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 536(%rsp), %rdi
movl $.L.str, %esi
movl $16, %edx
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
.Ltmp0:
leaq 24(%rsp), %rdi
movl $.L.str.1, %esi
movl $16, %edx
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
.Ltmp1:
# %bb.1:
movl $16384, %edi # imm = 0x4000
callq malloc
movq %rax, %rbx
movl $16384, %edi # imm = 0x4000
callq malloc
movq %rax, %r14
movq %rbx, %r15
addq $8, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_2: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %r12d, %xmm0
mulsd .LCPI0_0(%rip), %xmm0
mulsd .LCPI0_1(%rip), %xmm0
callq sin
movsd %xmm0, -8(%r15)
movq $0, (%r15)
incq %r12
addq $16, %r15
cmpq $1024, %r12 # imm = 0x400
jne .LBB0_2
# %bb.3:
.Ltmp3:
leaq 8(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
.Ltmp4:
# %bb.4: # %_ZL9hipMallocI15HIP_vector_typeIdLj2EEE10hipError_tPPT_m.exit
movq 8(%rsp), %rdi
.Ltmp5:
movl $16384, %edx # imm = 0x4000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp6:
# %bb.5:
.Ltmp7:
leaq 16(%rsp), %rdi
movl $1024, %esi # imm = 0x400
movl $105, %edx
movl $1, %ecx
callq hipfftPlan1d
.Ltmp8:
# %bb.6:
movq 16(%rsp), %rdi
movq 8(%rsp), %rdx
.Ltmp9:
movq %rdx, %rsi
movl $-1, %ecx
callq hipfftExecZ2Z
.Ltmp10:
# %bb.7:
movq 8(%rsp), %rsi
.Ltmp11:
movl $16384, %edx # imm = 0x4000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp12:
# %bb.8: # %.preheader.preheader
xorl %ebp, %ebp
leaq 536(%rsp), %r15
leaq 24(%rsp), %r12
leaq 7(%rsp), %r13
jmp .LBB0_9
.p2align 4, 0x90
.LBB0_26: # in Loop: Header=BB0_9 Depth=1
.Ltmp23:
movq %rax, %rdi
movl $10, %esi
callq _ZNSo3putEc
.Ltmp24:
.LBB0_27: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit49
# in Loop: Header=BB0_9 Depth=1
addq $16, %rbp
cmpq $16384, %rbp # imm = 0x4000
je .LBB0_12
.LBB0_9: # %.preheader
# =>This Inner Loop Header: Depth=1
movsd (%rbx,%rbp), %xmm0 # xmm0 = mem[0],zero
.Ltmp13:
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp14:
# %bb.10: # %_ZNSolsEd.exit
# in Loop: Header=BB0_9 Depth=1
movb $10, 7(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB0_19
# %bb.11: # in Loop: Header=BB0_9 Depth=1
.Ltmp15:
movl $1, %edx
movq %rax, %rdi
movq %r13, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp16:
jmp .LBB0_20
.p2align 4, 0x90
.LBB0_19: # in Loop: Header=BB0_9 Depth=1
.Ltmp17:
movq %rax, %rdi
movl $10, %esi
callq _ZNSo3putEc
.Ltmp18:
.LBB0_20: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
# in Loop: Header=BB0_9 Depth=1
movsd (%r14,%rbp), %xmm1 # xmm1 = mem[0],zero
movsd 8(%r14,%rbp), %xmm0 # xmm0 = mem[0],zero
mulsd %xmm1, %xmm1
mulsd %xmm0, %xmm0
addsd %xmm1, %xmm0
ucomisd .LCPI0_2(%rip), %xmm0
jb .LBB0_22
# %bb.21: # in Loop: Header=BB0_9 Depth=1
sqrtsd %xmm0, %xmm0
jmp .LBB0_23
.p2align 4, 0x90
.LBB0_22: # %call.sqrt
# in Loop: Header=BB0_9 Depth=1
callq sqrt
.LBB0_23: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit.split
# in Loop: Header=BB0_9 Depth=1
.Ltmp19:
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp20:
# %bb.24: # %_ZNSolsEd.exit44
# in Loop: Header=BB0_9 Depth=1
movb $10, 7(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB0_26
# %bb.25: # in Loop: Header=BB0_9 Depth=1
.Ltmp21:
movl $1, %edx
movq %rax, %rdi
movq %r13, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp22:
jmp .LBB0_27
.LBB0_12:
leaq 544(%rsp), %rdi
.Ltmp26:
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp27:
# %bb.13: # %.noexc
testq %rax, %rax
jne .LBB0_15
# %bb.14:
movq 536(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $536, %rdi # imm = 0x218
movl 568(%rsp,%rax), %esi
orl $4, %esi
.Ltmp28:
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp29:
.LBB0_15: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv.exit
leaq 32(%rsp), %rdi
.Ltmp30:
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp31:
# %bb.16: # %.noexc51
testq %rax, %rax
jne .LBB0_18
# %bb.17:
movq 24(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $24, %rdi
movl 56(%rsp,%rax), %esi
orl $4, %esi
.Ltmp32:
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp33:
.LBB0_18: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv.exit53
leaq 24(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
leaq 536(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
xorl %eax, %eax
addq $1048, %rsp # imm = 0x418
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_32:
.cfi_def_cfa_offset 1104
.Ltmp2:
movq %rax, %rbx
jmp .LBB0_31
.LBB0_29:
.Ltmp34:
jmp .LBB0_30
.LBB0_28:
.Ltmp25:
.LBB0_30:
movq %rax, %rbx
leaq 24(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
.LBB0_31:
leaq 536(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp12-.Ltmp3 # Call between .Ltmp3 and .Ltmp12
.uleb128 .Ltmp34-.Lfunc_begin0 # jumps to .Ltmp34
.byte 0 # On action: cleanup
.uleb128 .Ltmp23-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp22-.Ltmp23 # Call between .Ltmp23 and .Ltmp22
.uleb128 .Ltmp25-.Lfunc_begin0 # jumps to .Ltmp25
.byte 0 # On action: cleanup
.uleb128 .Ltmp26-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp33-.Ltmp26 # Call between .Ltmp26 and .Ltmp33
.uleb128 .Ltmp34-.Lfunc_begin0 # jumps to .Ltmp34
.byte 0 # On action: cleanup
.uleb128 .Ltmp33-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Lfunc_end0-.Ltmp33 # Call between .Ltmp33 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "time_out.dat"
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "freq_out.dat"
.size .L.str.1, 13
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void PyrDown_y_g(u_int8_t *ptGrayIn,u_int8_t *ptGrayOut, int w, int h)
{
int ix = blockIdx.x*blockDim.x + threadIdx.x;
int iy = blockIdx.y*blockDim.y + threadIdx.y;
if(ix<w && iy<h)// && y>2)
{
float p_2 = ptGrayIn[ix*2+(iy*2-2)*w*2]/16.0f;
float p_1 = ptGrayIn[ix*2+(iy*2-1)*w*2]/4.0f;
float p0 = 3.0f*ptGrayIn[ix*2+iy*2*w*2]/8.0f;
float pp1 = ptGrayIn[ix*2+(iy*2+1)*w*2]/4.0f;
float pp2 = ptGrayIn[ix*2+(iy*2+2)*w*2]/16.0f;
int output = p_2 + p_1 + p0 + pp1 + pp2;
ptGrayOut[ix+iy*w] = min(output,255);
}
} | code for sm_80
Function : _Z11PyrDown_y_gPhS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.SHL.U32 R5, R3, 0x2, RZ ; /* 0x0000000203057824 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00c0*/ IMAD R2, R5.reuse, c[0x0][0x170], R0 ; /* 0x00005c0005027a24 */
/* 0x040fe200078e0200 */
/*00d0*/ IADD3 R7, R5, -0x2, RZ ; /* 0xfffffffe05077810 */
/* 0x000fc60007ffe0ff */
/*00e0*/ IMAD.SHL.U32 R9, R2.reuse, 0x2, RZ ; /* 0x0000000202097824 */
/* 0x040fe200078e00ff */
/*00f0*/ IADD3 R2, R2, c[0x0][0x170], RZ ; /* 0x00005c0002027a10 */
/* 0x000fe20007ffe0ff */
/*0100*/ IMAD R7, R7, c[0x0][0x170], R0 ; /* 0x00005c0007077a24 */
/* 0x000fc600078e0200 */
/*0110*/ IADD3 R8, P1, R9, c[0x0][0x160], RZ ; /* 0x0000580009087a10 */
/* 0x000fe20007f3e0ff */
/*0120*/ IMAD.SHL.U32 R6, R7.reuse, 0x2, RZ ; /* 0x0000000207067824 */
/* 0x040fe200078e00ff */
/*0130*/ IADD3 R7, R7, c[0x0][0x170], RZ ; /* 0x00005c0007077a10 */
/* 0x000fc80007ffe0ff */
/*0140*/ IADD3 R4, P0, R6, c[0x0][0x160], RZ ; /* 0x0000580006047a10 */
/* 0x000fe20007f1e0ff */
/*0150*/ IMAD.SHL.U32 R7, R7, 0x2, RZ ; /* 0x0000000207077824 */
/* 0x000fc600078e00ff */
/*0160*/ LEA.HI.X.SX32 R5, R6, c[0x0][0x164], 0x1, P0 ; /* 0x0000590006057a11 */
/* 0x000fe400000f0eff */
/*0170*/ IADD3 R6, P0, R7, c[0x0][0x160], RZ ; /* 0x0000580007067a10 */
/* 0x000fe20007f1e0ff */
/*0180*/ IMAD.SHL.U32 R11, R2.reuse, 0x2, RZ ; /* 0x00000002020b7824 */
/* 0x040fe200078e00ff */
/*0190*/ LEA.HI.X.SX32 R9, R9, c[0x0][0x164], 0x1, P1 ; /* 0x0000590009097a11 */
/* 0x000fe200008f0eff */
/*01a0*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1100 */
/*01b0*/ LEA.HI.X.SX32 R7, R7, c[0x0][0x164], 0x1, P0 ; /* 0x0000590007077a11 */
/* 0x000fe400000f0eff */
/*01c0*/ IADD3 R2, R2, c[0x0][0x170], RZ ; /* 0x00005c0002027a10 */
/* 0x000fe20007ffe0ff */
/*01d0*/ LDG.E.U8 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee2000c1e1100 */
/*01e0*/ IADD3 R10, P0, R11, c[0x0][0x160], RZ ; /* 0x000058000b0a7a10 */
/* 0x000fc60007f1e0ff */
/*01f0*/ LDG.E.U8 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f22000c1e1100 */
/*0200*/ IMAD.SHL.U32 R2, R2, 0x2, RZ ; /* 0x0000000202027824 */
/* 0x000fe200078e00ff */
/*0210*/ LEA.HI.X.SX32 R11, R11, c[0x0][0x164], 0x1, P0 ; /* 0x000059000b0b7a11 */
/* 0x000fc800000f0eff */
/*0220*/ IADD3 R12, P0, R2.reuse, c[0x0][0x160], RZ ; /* 0x00005800020c7a10 */
/* 0x040fe20007f1e0ff */
/*0230*/ LDG.E.U8 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f66000c1e1100 */
/*0240*/ LEA.HI.X.SX32 R13, R2, c[0x0][0x164], 0x1, P0 ; /* 0x00005900020d7a11 */
/* 0x000fca00000f0eff */
/*0250*/ LDG.E.U8 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f62000c1e1100 */
/*0260*/ IMAD R0, R3, c[0x0][0x170], R0 ; /* 0x00005c0003007a24 */
/* 0x000fe200078e0200 */
/*0270*/ I2F.U16 R4, R4 ; /* 0x0000000400047306 */
/* 0x004ff00000101000 */
/*0280*/ I2F.U16 R2, R6 ; /* 0x0000000600027306 */
/* 0x010e300000101000 */
/*0290*/ I2F.U16 R7, R8 ; /* 0x0000000800077306 */
/* 0x008e700000101000 */
/*02a0*/ I2F.U16 R14, R10 ; /* 0x0000000a000e7306 */
/* 0x020ea20000101000 */
/*02b0*/ FMUL R5, R2, 0.25 ; /* 0x3e80000002057820 */
/* 0x001fce0000400000 */
/*02c0*/ I2F.U16 R2, R12 ; /* 0x0000000c00027306 */
/* 0x000e220000101000 */
/*02d0*/ FFMA R16, R4, 0.0625, R5 ; /* 0x3d80000004107823 */
/* 0x000fe40000000005 */
/*02e0*/ FMUL R7, R7, 3 ; /* 0x4040000007077820 */
/* 0x002fc80000400000 */
/*02f0*/ FFMA R7, R7, 0.125, R16 ; /* 0x3e00000007077823 */
/* 0x000fc80000000010 */
/*0300*/ FFMA R7, R14, 0.25, R7 ; /* 0x3e8000000e077823 */
/* 0x004fc80000000007 */
/*0310*/ FFMA R7, R2, 0.0625, R7 ; /* 0x3d80000002077823 */
/* 0x001fcc0000000007 */
/*0320*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e22000020f100 */
/*0330*/ IADD3 R2, P0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000027a10 */
/* 0x000fc80007f1e0ff */
/*0340*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0000037a11 */
/* 0x000fe400000f0eff */
/*0350*/ IMNMX R5, R7, 0xff, PT ; /* 0x000000ff07057817 */
/* 0x001fca0003800200 */
/*0360*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101104 */
/*0370*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0380*/ BRA 0x380; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void PyrDown_y_g(u_int8_t *ptGrayIn,u_int8_t *ptGrayOut, int w, int h)
{
int ix = blockIdx.x*blockDim.x + threadIdx.x;
int iy = blockIdx.y*blockDim.y + threadIdx.y;
if(ix<w && iy<h)// && y>2)
{
float p_2 = ptGrayIn[ix*2+(iy*2-2)*w*2]/16.0f;
float p_1 = ptGrayIn[ix*2+(iy*2-1)*w*2]/4.0f;
float p0 = 3.0f*ptGrayIn[ix*2+iy*2*w*2]/8.0f;
float pp1 = ptGrayIn[ix*2+(iy*2+1)*w*2]/4.0f;
float pp2 = ptGrayIn[ix*2+(iy*2+2)*w*2]/16.0f;
int output = p_2 + p_1 + p0 + pp1 + pp2;
ptGrayOut[ix+iy*w] = min(output,255);
}
} | .file "tmpxft_0004b7af_00000000-6_PyrDown_y_g.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z11PyrDown_y_gPhS_iiPhS_ii
.type _Z35__device_stub__Z11PyrDown_y_gPhS_iiPhS_ii, @function
_Z35__device_stub__Z11PyrDown_y_gPhS_iiPhS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11PyrDown_y_gPhS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z11PyrDown_y_gPhS_iiPhS_ii, .-_Z35__device_stub__Z11PyrDown_y_gPhS_iiPhS_ii
.globl _Z11PyrDown_y_gPhS_ii
.type _Z11PyrDown_y_gPhS_ii, @function
_Z11PyrDown_y_gPhS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11PyrDown_y_gPhS_iiPhS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11PyrDown_y_gPhS_ii, .-_Z11PyrDown_y_gPhS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11PyrDown_y_gPhS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11PyrDown_y_gPhS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void PyrDown_y_g(u_int8_t *ptGrayIn,u_int8_t *ptGrayOut, int w, int h)
{
int ix = blockIdx.x*blockDim.x + threadIdx.x;
int iy = blockIdx.y*blockDim.y + threadIdx.y;
if(ix<w && iy<h)// && y>2)
{
float p_2 = ptGrayIn[ix*2+(iy*2-2)*w*2]/16.0f;
float p_1 = ptGrayIn[ix*2+(iy*2-1)*w*2]/4.0f;
float p0 = 3.0f*ptGrayIn[ix*2+iy*2*w*2]/8.0f;
float pp1 = ptGrayIn[ix*2+(iy*2+1)*w*2]/4.0f;
float pp2 = ptGrayIn[ix*2+(iy*2+2)*w*2]/16.0f;
int output = p_2 + p_1 + p0 + pp1 + pp2;
ptGrayOut[ix+iy*w] = min(output,255);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void PyrDown_y_g(u_int8_t *ptGrayIn,u_int8_t *ptGrayOut, int w, int h)
{
int ix = blockIdx.x*blockDim.x + threadIdx.x;
int iy = blockIdx.y*blockDim.y + threadIdx.y;
if(ix<w && iy<h)// && y>2)
{
float p_2 = ptGrayIn[ix*2+(iy*2-2)*w*2]/16.0f;
float p_1 = ptGrayIn[ix*2+(iy*2-1)*w*2]/4.0f;
float p0 = 3.0f*ptGrayIn[ix*2+iy*2*w*2]/8.0f;
float pp1 = ptGrayIn[ix*2+(iy*2+1)*w*2]/4.0f;
float pp2 = ptGrayIn[ix*2+(iy*2+2)*w*2]/16.0f;
int output = p_2 + p_1 + p0 + pp1 + pp2;
ptGrayOut[ix+iy*w] = min(output,255);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void PyrDown_y_g(u_int8_t *ptGrayIn,u_int8_t *ptGrayOut, int w, int h)
{
int ix = blockIdx.x*blockDim.x + threadIdx.x;
int iy = blockIdx.y*blockDim.y + threadIdx.y;
if(ix<w && iy<h)// && y>2)
{
float p_2 = ptGrayIn[ix*2+(iy*2-2)*w*2]/16.0f;
float p_1 = ptGrayIn[ix*2+(iy*2-1)*w*2]/4.0f;
float p0 = 3.0f*ptGrayIn[ix*2+iy*2*w*2]/8.0f;
float pp1 = ptGrayIn[ix*2+(iy*2+1)*w*2]/4.0f;
float pp2 = ptGrayIn[ix*2+(iy*2+2)*w*2]/16.0f;
int output = p_2 + p_1 + p0 + pp1 + pp2;
ptGrayOut[ix+iy*w] = min(output,255);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11PyrDown_y_gPhS_ii
.globl _Z11PyrDown_y_gPhS_ii
.p2align 8
.type _Z11PyrDown_y_gPhS_ii,@function
_Z11PyrDown_y_gPhS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_lshlrev_b32_e32 v2, 1, v1
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v3, 0x7ffffffe, v2
v_add_nc_u32_e32 v4, -1, v2
v_mul_lo_u32 v5, v2, s4
v_or_b32_e32 v6, 1, v2
v_add_nc_u32_e32 v2, 2, v2
v_mul_lo_u32 v3, v3, s4
v_mul_lo_u32 v4, v4, s4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_lo_u32 v6, v6, s4
v_mul_lo_u32 v2, v2, s4
v_add_lshl_u32 v7, v5, v0, 1
v_add_lshl_u32 v3, v3, v0, 1
v_add_lshl_u32 v4, v4, v0, 1
s_delay_alu instid0(VALU_DEP_3)
v_ashrrev_i32_e32 v8, 31, v7
v_add_lshl_u32 v9, v6, v0, 1
v_add_lshl_u32 v10, v2, v0, 1
v_ashrrev_i32_e32 v5, 31, v3
v_ashrrev_i32_e32 v6, 31, v4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v6, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v8, vcc_lo
s_clause 0x1
global_load_u8 v8, v[4:5], off
global_load_u8 v11, v[2:3], off
v_ashrrev_i32_e32 v3, 31, v9
v_ashrrev_i32_e32 v5, 31, v10
global_load_u8 v6, v[6:7], off
v_add_co_u32 v2, vcc_lo, s0, v9
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v10
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_clause 0x1
global_load_u8 v2, v[2:3], off
global_load_u8 v3, v[4:5], off
s_waitcnt vmcnt(4)
v_cvt_f32_ubyte0_e32 v4, v8
s_waitcnt vmcnt(3)
v_cvt_f32_ubyte0_e32 v5, v11
s_waitcnt vmcnt(2)
v_cvt_f32_ubyte0_e32 v6, v6
v_mul_f32_e32 v4, 0x3e800000, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v6, 0x40400000, v6
v_fmac_f32_e32 v4, 0x3d800000, v5
s_waitcnt vmcnt(1)
v_cvt_f32_ubyte0_e32 v2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fmamk_f32 v4, v6, 0x3e000000, v4
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v3, v3
v_fmac_f32_e32 v4, 0x3e800000, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v4, 0x3d800000, v3
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
v_cvt_i32_f32_e32 v0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v2
v_min_i32_e32 v3, 0xff, v0
v_add_co_u32 v0, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b8 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11PyrDown_y_gPhS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11PyrDown_y_gPhS_ii, .Lfunc_end0-_Z11PyrDown_y_gPhS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11PyrDown_y_gPhS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11PyrDown_y_gPhS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void PyrDown_y_g(u_int8_t *ptGrayIn,u_int8_t *ptGrayOut, int w, int h)
{
int ix = blockIdx.x*blockDim.x + threadIdx.x;
int iy = blockIdx.y*blockDim.y + threadIdx.y;
if(ix<w && iy<h)// && y>2)
{
float p_2 = ptGrayIn[ix*2+(iy*2-2)*w*2]/16.0f;
float p_1 = ptGrayIn[ix*2+(iy*2-1)*w*2]/4.0f;
float p0 = 3.0f*ptGrayIn[ix*2+iy*2*w*2]/8.0f;
float pp1 = ptGrayIn[ix*2+(iy*2+1)*w*2]/4.0f;
float pp2 = ptGrayIn[ix*2+(iy*2+2)*w*2]/16.0f;
int output = p_2 + p_1 + p0 + pp1 + pp2;
ptGrayOut[ix+iy*w] = min(output,255);
}
} | .text
.file "PyrDown_y_g.hip"
.globl _Z26__device_stub__PyrDown_y_gPhS_ii # -- Begin function _Z26__device_stub__PyrDown_y_gPhS_ii
.p2align 4, 0x90
.type _Z26__device_stub__PyrDown_y_gPhS_ii,@function
_Z26__device_stub__PyrDown_y_gPhS_ii: # @_Z26__device_stub__PyrDown_y_gPhS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11PyrDown_y_gPhS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__PyrDown_y_gPhS_ii, .Lfunc_end0-_Z26__device_stub__PyrDown_y_gPhS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11PyrDown_y_gPhS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11PyrDown_y_gPhS_ii,@object # @_Z11PyrDown_y_gPhS_ii
.section .rodata,"a",@progbits
.globl _Z11PyrDown_y_gPhS_ii
.p2align 3, 0x0
_Z11PyrDown_y_gPhS_ii:
.quad _Z26__device_stub__PyrDown_y_gPhS_ii
.size _Z11PyrDown_y_gPhS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11PyrDown_y_gPhS_ii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__PyrDown_y_gPhS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11PyrDown_y_gPhS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11PyrDown_y_gPhS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.SHL.U32 R5, R3, 0x2, RZ ; /* 0x0000000203057824 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00c0*/ IMAD R2, R5.reuse, c[0x0][0x170], R0 ; /* 0x00005c0005027a24 */
/* 0x040fe200078e0200 */
/*00d0*/ IADD3 R7, R5, -0x2, RZ ; /* 0xfffffffe05077810 */
/* 0x000fc60007ffe0ff */
/*00e0*/ IMAD.SHL.U32 R9, R2.reuse, 0x2, RZ ; /* 0x0000000202097824 */
/* 0x040fe200078e00ff */
/*00f0*/ IADD3 R2, R2, c[0x0][0x170], RZ ; /* 0x00005c0002027a10 */
/* 0x000fe20007ffe0ff */
/*0100*/ IMAD R7, R7, c[0x0][0x170], R0 ; /* 0x00005c0007077a24 */
/* 0x000fc600078e0200 */
/*0110*/ IADD3 R8, P1, R9, c[0x0][0x160], RZ ; /* 0x0000580009087a10 */
/* 0x000fe20007f3e0ff */
/*0120*/ IMAD.SHL.U32 R6, R7.reuse, 0x2, RZ ; /* 0x0000000207067824 */
/* 0x040fe200078e00ff */
/*0130*/ IADD3 R7, R7, c[0x0][0x170], RZ ; /* 0x00005c0007077a10 */
/* 0x000fc80007ffe0ff */
/*0140*/ IADD3 R4, P0, R6, c[0x0][0x160], RZ ; /* 0x0000580006047a10 */
/* 0x000fe20007f1e0ff */
/*0150*/ IMAD.SHL.U32 R7, R7, 0x2, RZ ; /* 0x0000000207077824 */
/* 0x000fc600078e00ff */
/*0160*/ LEA.HI.X.SX32 R5, R6, c[0x0][0x164], 0x1, P0 ; /* 0x0000590006057a11 */
/* 0x000fe400000f0eff */
/*0170*/ IADD3 R6, P0, R7, c[0x0][0x160], RZ ; /* 0x0000580007067a10 */
/* 0x000fe20007f1e0ff */
/*0180*/ IMAD.SHL.U32 R11, R2.reuse, 0x2, RZ ; /* 0x00000002020b7824 */
/* 0x040fe200078e00ff */
/*0190*/ LEA.HI.X.SX32 R9, R9, c[0x0][0x164], 0x1, P1 ; /* 0x0000590009097a11 */
/* 0x000fe200008f0eff */
/*01a0*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1100 */
/*01b0*/ LEA.HI.X.SX32 R7, R7, c[0x0][0x164], 0x1, P0 ; /* 0x0000590007077a11 */
/* 0x000fe400000f0eff */
/*01c0*/ IADD3 R2, R2, c[0x0][0x170], RZ ; /* 0x00005c0002027a10 */
/* 0x000fe20007ffe0ff */
/*01d0*/ LDG.E.U8 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee2000c1e1100 */
/*01e0*/ IADD3 R10, P0, R11, c[0x0][0x160], RZ ; /* 0x000058000b0a7a10 */
/* 0x000fc60007f1e0ff */
/*01f0*/ LDG.E.U8 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f22000c1e1100 */
/*0200*/ IMAD.SHL.U32 R2, R2, 0x2, RZ ; /* 0x0000000202027824 */
/* 0x000fe200078e00ff */
/*0210*/ LEA.HI.X.SX32 R11, R11, c[0x0][0x164], 0x1, P0 ; /* 0x000059000b0b7a11 */
/* 0x000fc800000f0eff */
/*0220*/ IADD3 R12, P0, R2.reuse, c[0x0][0x160], RZ ; /* 0x00005800020c7a10 */
/* 0x040fe20007f1e0ff */
/*0230*/ LDG.E.U8 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f66000c1e1100 */
/*0240*/ LEA.HI.X.SX32 R13, R2, c[0x0][0x164], 0x1, P0 ; /* 0x00005900020d7a11 */
/* 0x000fca00000f0eff */
/*0250*/ LDG.E.U8 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f62000c1e1100 */
/*0260*/ IMAD R0, R3, c[0x0][0x170], R0 ; /* 0x00005c0003007a24 */
/* 0x000fe200078e0200 */
/*0270*/ I2F.U16 R4, R4 ; /* 0x0000000400047306 */
/* 0x004ff00000101000 */
/*0280*/ I2F.U16 R2, R6 ; /* 0x0000000600027306 */
/* 0x010e300000101000 */
/*0290*/ I2F.U16 R7, R8 ; /* 0x0000000800077306 */
/* 0x008e700000101000 */
/*02a0*/ I2F.U16 R14, R10 ; /* 0x0000000a000e7306 */
/* 0x020ea20000101000 */
/*02b0*/ FMUL R5, R2, 0.25 ; /* 0x3e80000002057820 */
/* 0x001fce0000400000 */
/*02c0*/ I2F.U16 R2, R12 ; /* 0x0000000c00027306 */
/* 0x000e220000101000 */
/*02d0*/ FFMA R16, R4, 0.0625, R5 ; /* 0x3d80000004107823 */
/* 0x000fe40000000005 */
/*02e0*/ FMUL R7, R7, 3 ; /* 0x4040000007077820 */
/* 0x002fc80000400000 */
/*02f0*/ FFMA R7, R7, 0.125, R16 ; /* 0x3e00000007077823 */
/* 0x000fc80000000010 */
/*0300*/ FFMA R7, R14, 0.25, R7 ; /* 0x3e8000000e077823 */
/* 0x004fc80000000007 */
/*0310*/ FFMA R7, R2, 0.0625, R7 ; /* 0x3d80000002077823 */
/* 0x001fcc0000000007 */
/*0320*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e22000020f100 */
/*0330*/ IADD3 R2, P0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000027a10 */
/* 0x000fc80007f1e0ff */
/*0340*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0000037a11 */
/* 0x000fe400000f0eff */
/*0350*/ IMNMX R5, R7, 0xff, PT ; /* 0x000000ff07057817 */
/* 0x001fca0003800200 */
/*0360*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101104 */
/*0370*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0380*/ BRA 0x380; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11PyrDown_y_gPhS_ii
.globl _Z11PyrDown_y_gPhS_ii
.p2align 8
.type _Z11PyrDown_y_gPhS_ii,@function
_Z11PyrDown_y_gPhS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_lshlrev_b32_e32 v2, 1, v1
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v3, 0x7ffffffe, v2
v_add_nc_u32_e32 v4, -1, v2
v_mul_lo_u32 v5, v2, s4
v_or_b32_e32 v6, 1, v2
v_add_nc_u32_e32 v2, 2, v2
v_mul_lo_u32 v3, v3, s4
v_mul_lo_u32 v4, v4, s4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_lo_u32 v6, v6, s4
v_mul_lo_u32 v2, v2, s4
v_add_lshl_u32 v7, v5, v0, 1
v_add_lshl_u32 v3, v3, v0, 1
v_add_lshl_u32 v4, v4, v0, 1
s_delay_alu instid0(VALU_DEP_3)
v_ashrrev_i32_e32 v8, 31, v7
v_add_lshl_u32 v9, v6, v0, 1
v_add_lshl_u32 v10, v2, v0, 1
v_ashrrev_i32_e32 v5, 31, v3
v_ashrrev_i32_e32 v6, 31, v4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v6, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v8, vcc_lo
s_clause 0x1
global_load_u8 v8, v[4:5], off
global_load_u8 v11, v[2:3], off
v_ashrrev_i32_e32 v3, 31, v9
v_ashrrev_i32_e32 v5, 31, v10
global_load_u8 v6, v[6:7], off
v_add_co_u32 v2, vcc_lo, s0, v9
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v10
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_clause 0x1
global_load_u8 v2, v[2:3], off
global_load_u8 v3, v[4:5], off
s_waitcnt vmcnt(4)
v_cvt_f32_ubyte0_e32 v4, v8
s_waitcnt vmcnt(3)
v_cvt_f32_ubyte0_e32 v5, v11
s_waitcnt vmcnt(2)
v_cvt_f32_ubyte0_e32 v6, v6
v_mul_f32_e32 v4, 0x3e800000, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v6, 0x40400000, v6
v_fmac_f32_e32 v4, 0x3d800000, v5
s_waitcnt vmcnt(1)
v_cvt_f32_ubyte0_e32 v2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fmamk_f32 v4, v6, 0x3e000000, v4
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v3, v3
v_fmac_f32_e32 v4, 0x3e800000, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v4, 0x3d800000, v3
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
v_cvt_i32_f32_e32 v0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v2
v_min_i32_e32 v3, 0xff, v0
v_add_co_u32 v0, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b8 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11PyrDown_y_gPhS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11PyrDown_y_gPhS_ii, .Lfunc_end0-_Z11PyrDown_y_gPhS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11PyrDown_y_gPhS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11PyrDown_y_gPhS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004b7af_00000000-6_PyrDown_y_g.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z11PyrDown_y_gPhS_iiPhS_ii
.type _Z35__device_stub__Z11PyrDown_y_gPhS_iiPhS_ii, @function
_Z35__device_stub__Z11PyrDown_y_gPhS_iiPhS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11PyrDown_y_gPhS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z11PyrDown_y_gPhS_iiPhS_ii, .-_Z35__device_stub__Z11PyrDown_y_gPhS_iiPhS_ii
.globl _Z11PyrDown_y_gPhS_ii
.type _Z11PyrDown_y_gPhS_ii, @function
_Z11PyrDown_y_gPhS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11PyrDown_y_gPhS_iiPhS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11PyrDown_y_gPhS_ii, .-_Z11PyrDown_y_gPhS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11PyrDown_y_gPhS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11PyrDown_y_gPhS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "PyrDown_y_g.hip"
.globl _Z26__device_stub__PyrDown_y_gPhS_ii # -- Begin function _Z26__device_stub__PyrDown_y_gPhS_ii
.p2align 4, 0x90
.type _Z26__device_stub__PyrDown_y_gPhS_ii,@function
_Z26__device_stub__PyrDown_y_gPhS_ii: # @_Z26__device_stub__PyrDown_y_gPhS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11PyrDown_y_gPhS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__PyrDown_y_gPhS_ii, .Lfunc_end0-_Z26__device_stub__PyrDown_y_gPhS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11PyrDown_y_gPhS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11PyrDown_y_gPhS_ii,@object # @_Z11PyrDown_y_gPhS_ii
.section .rodata,"a",@progbits
.globl _Z11PyrDown_y_gPhS_ii
.p2align 3, 0x0
_Z11PyrDown_y_gPhS_ii:
.quad _Z26__device_stub__PyrDown_y_gPhS_ii
.size _Z11PyrDown_y_gPhS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11PyrDown_y_gPhS_ii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__PyrDown_y_gPhS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11PyrDown_y_gPhS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/******************************************************************************
* This program takes an initial estimate of m and c and finds the associated
* rms error. It is then as a base to generate and evaluate 8 new estimates,
* which are steps in different directions in m-c space. The best estimate is
* then used as the base for another iteration of "generate and evaluate". This
* continues until none of the new estimates are better than the base. This is
* a gradient search for a minimum in mc-space.
*
* To compile:
* nvcc -o cuda_linear_regression CUDA_linear_regression.c -lm
*
* To run:
* ./cuda_linear_regression
*
* Dr Kevan Buckley, University of Wolverhampton, 2018
*****************************************************************************/
typedef struct point_t {
double x;
double y;
} point_t;
int n_data = 1000;
__device__ int d_n_data = 1000; //device varialble
//date set
point_t data[] = {
{82.73,128.67},{79.53,133.54},{66.86,124.65},{69.21,135.74},
{82.20,122.07},{84.32,120.46},{71.12,93.14},{85.64,121.42},
{69.22,116.28},{83.12,137.30},{84.31,113.18},{75.60,121.42},
{69.04,91.83},{85.41,131.06},{17.44,58.69},{68.92,119.86},
{69.95,110.05},{ 0.15, 5.39},{73.96,118.70},{27.70,64.64},
{97.97,158.15},{56.21,100.99},{30.27,48.32},{37.47,89.65},
{98.98,144.03},{92.61,133.89},{ 4.72,32.88},{19.51,57.43},
{94.74,145.50},{31.66,71.27},{94.76,134.53},{32.73,59.95},
{32.64,54.53},{38.78,69.06},{91.47,150.49},{77.99,119.35},
{33.38,65.87},{79.28,123.62},{39.69,72.53},{95.47,140.97},
{82.64,137.69},{25.53,51.33},{68.58,85.98},{92.25,132.34},
{74.79,101.30},{ 1.32,18.87},{53.85,95.13},{78.75,128.26},
{ 2.91,21.77},{90.68,128.55},{11.44,35.27},{30.72,56.54},
{49.06,74.08},{49.09,83.45},{62.54,104.58},{38.83,72.26},
{78.43,130.83},{69.49,122.49},{27.27,56.35},{80.06,131.95},
{ 5.73,39.00},{80.21,140.42},{ 8.47,36.12},{86.98,152.43},
{64.26,108.56},{95.74,133.36},{15.06,48.67},{31.96,72.31},
{95.27,141.34},{61.10,89.26},{27.51,68.47},{26.48,60.30},
{92.61,128.38},{ 8.25,47.51},{90.69,118.91},{45.40,79.96},
{23.59,53.12},{46.71,68.27},{21.15,50.29},{27.99,76.29},
{ 7.75,43.57},{13.70,43.56},{74.85,97.83},{50.93,103.11},
{33.80,64.85},{80.99,125.37},{92.41,126.27},{92.61,134.36},
{34.70,55.32},{35.07,55.04},{86.87,157.26},{41.99,90.46},
{16.27,44.43},{36.31,83.84},{22.35,73.11},{89.11,127.19},
{56.11,77.28},{51.90,75.07},{35.74,94.18},{10.66,29.60},
{61.27,114.15},{77.55,117.04},{61.17,99.68},{15.54,55.33},
{91.99,143.18},{12.91,21.82},{48.52,89.94},{54.88,90.86},
{73.59,131.33},{ 5.49,13.95},{92.31,147.29},{48.50,89.49},
{40.02,58.26},{48.22,81.96},{17.08,52.59},{34.27,66.17},
{59.06,94.26},{92.71,134.53},{37.70,65.30},{77.11,111.38},
{43.27,74.12},{79.71,123.45},{ 0.86,38.69},{ 3.00,17.76},
{56.03,80.33},{17.66,43.27},{18.39,47.08},{31.08,83.84},
{32.64,77.85},{51.68,84.57},{78.46,134.18},{ 9.57,40.28},
{68.38,98.26},{30.29,67.59},{86.15,131.86},{16.82,64.91},
{ 3.35,20.88},{65.78,98.73},{50.70,90.92},{38.26,71.11},
{85.52,132.23},{44.06,83.02},{44.09,86.42},{81.86,114.30},
{33.98,69.09},{93.80,147.73},{59.58,103.07},{98.75,154.73},
{88.98,120.59},{78.08,109.00},{82.77,133.94},{76.49,106.31},
{55.38,85.71},{46.56,79.57},{83.92,141.58},{81.38,133.52},
{ 4.88,35.01},{ 4.57,17.99},{57.96,90.07},{33.42,63.80},
{ 9.95,34.53},{47.14,92.75},{63.17,105.19},{95.01,163.93},
{30.36,57.81},{ 2.46,23.97},{69.75,115.88},{64.85,111.01},
{25.18,56.58},{69.84,104.78},{40.43,51.98},{75.61,107.05},
{36.75,69.37},{50.08,100.02},{64.97,103.68},{41.72,86.64},
{ 1.70,47.26},{99.93,141.75},{24.57,64.51},{75.23,116.35},
{ 1.95,18.53},{78.84,102.70},{67.38,97.71},{55.35,82.37},
{58.10,100.09},{53.10,96.07},{41.24,83.81},{68.86,111.98},
{87.36,86.88},{54.06,98.42},{64.12,90.56},{11.77,49.66},
{99.43,134.33},{55.24,99.18},{56.44,74.73},{39.47,62.99},
{ 8.94,48.15},{92.91,130.45},{87.68,138.76},{80.37,116.69},
{56.72,108.65},{ 0.76,24.26},{26.98,75.13},{ 0.39,42.16},
{81.99,138.50},{88.32,117.16},{51.01,87.42},{21.38,55.45},
{72.66,122.82},{18.04,53.56},{11.22,49.73},{36.75,60.26},
{64.81,90.19},{72.72,121.14},{24.03,74.08},{41.38,81.38},
{62.79,98.75},{63.66,109.17},{91.12,143.91},{ 7.41,34.06},
{94.05,131.99},{53.12,90.28},{68.31,114.79},{25.33,67.23},
{42.34,86.91},{94.61,131.38},{43.78,73.28},{50.18,78.10},
{81.64,135.88},{11.27,44.45},{41.03,76.34},{21.25,57.54},
{29.23,57.27},{35.74,75.16},{ 0.91,14.33},{30.08,59.05},
{23.99,56.25},{90.79,120.98},{99.22,152.22},{94.21,143.09},
{19.35,30.03},{82.04,113.25},{79.22,113.69},{83.40,144.06},
{55.82,80.85},{42.49,48.94},{17.60,55.62},{35.65,81.91},
{82.50,135.41},{81.15,114.46},{53.47,78.67},{44.30,73.73},
{32.88,80.28},{99.26,147.55},{76.32,110.24},{78.97,110.27},
{18.08,47.48},{87.01,140.40},{56.25,83.61},{42.62,55.40},
{15.95,16.25},{47.85,106.69},{ 6.61,35.83},{66.38,116.30},
{94.97,122.56},{42.29,73.37},{31.48,67.15},{69.67,105.40},
{30.41,65.31},{ 2.98,19.40},{ 8.12,48.34},{80.41,127.03},
{63.68,112.61},{24.60,78.23},{77.61,123.49},{39.87,38.20},
{77.80,109.59},{58.53,107.63},{23.97,62.36},{ 7.77,27.38},
{ 0.80,41.55},{ 6.45,32.91},{45.32,82.24},{35.56,59.56},
{65.05,97.68},{62.21,96.14},{86.61,121.99},{87.91,125.40},
{48.08,88.87},{ 2.41,40.02},{69.55,119.31},{22.07,61.86},
{61.87,121.40},{82.50,119.46},{26.97,38.40},{31.53,86.30},
{ 1.81,38.57},{72.57,108.34},{88.88,139.23},{63.90,95.79},
{93.29,135.35},{86.26,143.55},{63.62,94.76},{20.24,38.84},
{16.23,48.64},{72.87,108.22},{16.26,51.25},{37.86,66.06},
{57.53,81.37},{61.66,97.20},{49.48,84.98},{95.20,142.45},
{12.10,45.25},{47.79,84.80},{17.29,48.98},{47.11,87.23},
{85.74,119.95},{89.94,142.94},{97.68,155.27},{78.73,123.81},
{51.65,85.91},{52.82,96.05},{50.95,93.50},{16.14,37.21},
{16.73,41.57},{57.25,95.50},{78.47,136.77},{42.35,75.64},
{93.24,135.04},{12.56,38.20},{21.40,62.92},{70.60,136.98},
{44.04,83.57},{ 6.43,36.61},{12.01,50.32},{79.61,119.78},
{43.05,69.07},{14.42,53.01},{51.68,83.82},{25.59,55.77},
{ 9.14,31.58},{37.24,80.94},{15.73,69.21},{71.54,123.11},
{ 1.26,25.72},{ 4.25,38.46},{21.42,39.99},{44.12,79.01},
{31.12,64.63},{85.27,143.62},{43.25,79.30},{77.27,104.30},
{47.34,83.76},{90.57,125.82},{17.35,36.40},{82.01,130.41},
{81.58,124.10},{68.62,117.62},{47.48,79.29},{ 4.30,26.77},
{ 6.94,32.22},{11.71,55.76},{22.62,54.74},{58.43,89.61},
{69.10,111.51},{56.77,101.10},{67.10,102.75},{93.20,144.51},
{83.61,128.56},{71.97,116.09},{75.19,122.16},{48.03,79.67},
{97.95,143.80},{92.27,123.08},{23.88,63.39},{79.15,115.57},
{24.42,51.27},{12.58,34.65},{46.58,78.16},{ 1.29,37.96},
{17.09,45.61},{12.45,40.77},{82.75,107.46},{52.15,75.34},
{39.51,68.51},{31.71,64.23},{39.36,72.00},{12.16,37.99},
{83.13,127.76},{42.25,73.17},{45.32,77.14},{20.52,36.60},
{ 7.99,11.50},{23.34,55.47},{25.87,54.36},{78.73,112.49},
{55.60,94.90},{31.98,73.40},{85.93,137.12},{58.56,97.64},
{88.16,120.43},{78.65,136.60},{25.93,43.32},{84.83,136.32},
{68.09,102.12},{68.36,111.80},{39.80,69.69},{ 0.38,27.89},
{ 4.49,27.85},{32.53,66.32},{54.23,97.63},{19.98,67.32},
{90.62,143.43},{18.31,67.91},{95.66,146.41},{95.41,149.68},
{71.64,111.15},{23.02,44.96},{97.06,154.54},{41.58,75.95},
{79.80,130.01},{74.55,119.44},{72.19,113.27},{70.01,106.48},
{75.24,94.18},{19.82,60.09},{96.31,137.91},{ 2.21,27.44},
{40.52,70.36},{ 2.40,29.12},{35.24,57.25},{26.38,71.34},
{26.02,59.48},{34.73,66.07},{45.15,78.23},{ 9.35,32.58},
{19.37,57.18},{ 9.51,31.70},{15.03,49.81},{85.08,140.35},
{ 3.23,13.46},{58.26,108.47},{ 4.84,31.78},{49.49,83.50},
{35.55,70.67},{26.51,55.44},{20.12,53.39},{72.73,119.37},
{31.04,72.96},{30.66,58.35},{ 2.96,33.18},{18.68,31.50},
{91.41,138.24},{44.67,81.81},{81.57,135.26},{ 0.17,26.66},
{49.03,100.11},{54.47,102.27},{61.78,113.45},{22.67,59.51},
{89.80,143.05},{33.05,78.20},{67.76,108.19},{ 7.64,41.18},
{36.91,87.28},{95.44,147.27},{52.76,94.34},{ 3.52,29.51},
{87.39,118.48},{41.48,64.71},{ 1.44,14.21},{95.04,136.99},
{71.77,115.75},{23.39,47.58},{62.66,115.03},{15.98,34.38},
{29.06,62.77},{ 2.94,28.25},{71.50,119.18},{65.24,119.14},
{30.65,82.39},{16.36,38.82},{ 0.98,48.82},{33.19,56.41},
{27.49,64.34},{53.69,102.47},{28.15,52.58},{40.21,66.07},
{50.56,86.39},{74.71,97.44},{24.72,46.29},{48.05,80.63},
{34.99,52.13},{66.75,115.96},{17.62,49.17},{98.99,157.80},
{37.96,72.18},{56.88,105.06},{48.27,97.04},{71.18,138.90},
{46.35,82.02},{10.43,44.65},{24.14,42.85},{82.21,144.13},
{96.85,148.15},{93.68,126.32},{33.02,61.55},{66.73,108.51},
{83.89,136.35},{80.85,91.16},{79.21,128.88},{84.37,119.84},
{38.41,71.48},{47.49,85.53},{ 1.54,24.44},{68.32,106.44},
{22.82,54.16},{ 2.65,16.35},{19.91,53.53},{12.99,34.98},
{30.87,57.17},{44.10,83.88},{15.84,31.99},{36.46,59.74},
{26.25,79.73},{79.12,132.06},{86.26,132.45},{ 0.61,23.61},
{33.94,59.37},{99.92,145.88},{26.20,53.99},{69.77,115.40},
{69.07,107.00},{ 1.89,17.20},{38.25,81.40},{27.08,62.96},
{23.09,53.98},{55.56,86.93},{ 6.68,50.41},{22.86,49.26},
{17.25,50.25},{19.01,50.16},{35.07,85.09},{59.08,89.15},
{87.02,128.83},{ 1.57,27.68},{97.76,148.25},{70.78,108.00},
{38.01,65.83},{96.41,139.67},{ 2.86,22.44},{27.05,53.00},
{90.99,134.97},{86.60,145.27},{54.66,99.42},{67.61,107.07},
{85.16,137.50},{87.64,144.60},{14.69,36.65},{16.08,49.31},
{14.45,44.07},{65.91,98.39},{50.74,90.72},{ 6.98,31.11},
{52.76,83.96},{ 8.03,43.93},{17.58,52.58},{33.63,59.04},
{87.65,137.34},{77.97,142.54},{30.56,69.47},{59.61,114.61},
{14.05,53.07},{87.65,116.66},{33.19,75.96},{31.87,66.95},
{25.89,57.59},{48.60,75.67},{80.25,109.89},{ 6.61,24.27},
{ 4.56,44.00},{40.17,62.33},{92.32,117.73},{75.07,112.71},
{17.10,35.12},{39.06,66.60},{ 4.26,34.01},{52.95,102.49},
{45.73,76.57},{ 4.72,29.94},{ 2.01,17.54},{39.08,88.44},
{82.94,141.75},{44.51,90.97},{27.27,63.14},{60.16,95.38},
{41.26,72.59},{66.50,104.49},{58.37,110.13},{62.11,96.01},
{70.30,90.15},{18.47,47.61},{24.80,51.82},{79.02,133.40},
{96.61,147.92},{18.14,33.27},{ 0.83,51.20},{99.67,143.65},
{34.07,67.38},{57.28,110.02},{35.92,59.90},{66.15,124.45},
{81.82,135.08},{ 2.97,28.49},{95.97,135.79},{51.17,80.95},
{91.47,142.00},{94.09,121.08},{57.70,82.98},{67.96,100.92},
{81.91,132.34},{11.55,39.74},{86.59,126.05},{ 5.36,41.72},
{90.86,144.15},{81.02,137.56},{35.87,81.76},{63.73,105.92},
{78.29,129.54},{96.72,150.04},{14.97,61.93},{45.76,77.17},
{82.69,123.95},{85.82,132.89},{85.95,127.24},{15.04,36.92},
{89.91,112.87},{30.86,58.13},{ 5.77,42.22},{75.24,108.41},
{ 8.43,32.09},{90.70,147.99},{80.16,112.57},{42.81,73.54},
{82.47,123.41},{48.23,98.48},{77.48,143.96},{ 0.48,14.50},
{29.75,63.12},{88.76,137.72},{33.59,70.61},{22.74,43.51},
{82.15,116.11},{89.10,120.65},{26.56,68.17},{40.72,74.98},
{68.46,99.23},{34.82,66.71},{36.56,67.33},{72.32,114.23},
{29.65,65.99},{44.39,64.83},{82.08,116.35},{99.73,139.12},
{79.04,118.48},{20.78,42.05},{72.39,96.47},{90.62,147.11},
{35.99,59.11},{50.65,83.23},{59.04,100.47},{87.01,145.78},
{43.71,76.56},{95.61,151.81},{50.25,88.96},{69.64,122.07},
{40.07,79.38},{82.61,133.63},{20.84,39.75},{10.28,42.50},
{47.43,70.82},{30.47,67.19},{69.16,100.10},{46.06,74.00},
{93.78,152.76},{19.93,67.46},{79.61,130.88},{81.11,120.11},
{76.16,123.94},{75.84,111.70},{50.97,85.30},{47.35,90.59},
{93.21,115.44},{19.22,39.30},{11.67,29.58},{52.48,95.64},
{38.76,59.62},{ 2.74,-2.03},{18.99,63.67},{82.38,128.08},
{15.68,32.34},{39.19,83.38},{31.06,65.92},{28.91,73.05},
{19.01,59.69},{76.62,117.74},{36.82,91.33},{86.28,121.19},
{39.26,50.72},{41.45,70.26},{65.81,111.41},{77.09,117.88},
{78.96,128.48},{16.41,56.61},{39.54,64.11},{72.45,110.54},
{48.83,77.35},{27.61,51.82},{26.53,47.44},{83.06,111.09},
{97.06,127.57},{89.01,146.82},{89.44,141.17},{69.18,100.25},
{ 1.11,11.60},{71.63,123.66},{92.93,151.73},{99.46,165.34},
{36.49,71.56},{95.48,153.13},{65.33,102.37},{15.28,35.93},
{ 5.52,36.67},{ 0.78,42.47},{10.09,36.68},{ 5.75,37.39},
{52.34,89.11},{14.55,47.37},{67.92,113.35},{36.66,77.34},
{99.76,143.75},{26.67,58.72},{ 3.21,39.37},{87.70,124.12},
{90.03,131.24},{51.54,91.39},{62.86,98.04},{52.75,90.87},
{34.17,84.31},{62.00,89.08},{82.47,111.89},{61.38,123.48},
{47.17,84.64},{20.91,53.51},{96.96,131.54},{46.06,85.14},
{26.85,71.44},{91.67,138.51},{54.07,85.26},{51.63,89.63},
{94.04,140.80},{67.75,107.07},{29.24,76.71},{38.29,75.78},
{28.49,72.87},{60.51,102.28},{77.22,107.79},{99.25,145.86},
{33.11,52.32},{72.47,125.80},{21.97,59.23},{14.25,61.11},
{23.79,63.11},{77.78,109.13},{23.51,81.38},{66.92,110.89},
{79.81,109.80},{56.72,94.63},{59.60,110.57},{57.68,104.54},
{27.83,42.43},{47.80,87.68},{58.79,76.51},{78.33,126.71},
{85.14,128.99},{71.61,116.42},{58.09,96.85},{44.89,71.34},
{33.12,80.19},{98.79,130.09},{44.57,82.03},{88.63,142.61},
{61.96,98.55},{58.54,106.80},{19.17,61.00},{13.51,26.68},
{76.68,124.52},{82.62,138.53},{78.13,122.09},{37.10,60.33},
{ 8.82,48.63},{71.64,105.27},{68.44,115.07},{ 7.66,61.91},
{64.37,96.58},{54.90,88.28},{78.35,133.29},{79.84,129.58},
{ 3.09,28.37},{48.62,76.00},{38.26,63.99},{42.05,102.17},
{48.89,73.66},{54.38,100.05},{11.16,55.43},{63.24,110.69},
{68.17,114.15},{68.68,109.15},{53.43,90.23},{67.45,106.67},
{10.60,34.41},{56.81,90.86},{11.42,27.08},{36.93,93.13},
{41.64,89.77},{69.74,103.98},{23.07,55.12},{44.98,83.65},
{35.75,72.65},{14.80,56.15},{72.19,115.53},{51.10,80.69},
{96.54,140.10},{15.04,62.30},{21.17,56.15},{46.42,79.63},
{22.35,52.01},{35.47,54.95},{ 4.27,21.33},{84.37,139.55},
{43.95,93.24},{86.56,132.82},{44.35,83.36},{76.81,114.79},
{ 1.05,31.66},{32.76,76.15},{83.66,120.90},{12.14,42.52},
{25.85,55.83},{82.12,140.05},{75.33,126.93},{32.92,75.90},
{ 7.52,24.51},{25.42,41.55},{42.57,67.15},{87.36,150.38},
{ 0.51,17.68},{45.70,84.75},{58.74,88.68},{28.62,74.38},
{73.22,113.45},{78.64,114.25},{42.40,92.03},{84.22,132.25},
{54.24,73.34},{ 2.71,30.27},{54.11,84.97},{66.74,112.66},
{28.80,57.88},{87.02,146.20},{32.02,63.03},{59.57,94.41},
{40.46,79.73},{23.74,49.78},{87.58,140.94},{84.15,113.32},
{32.48,63.48},{ 4.59,25.85},{98.00,128.35},{12.23,37.43},
{66.17,102.97},{50.73,93.82},{74.68,137.79},{43.72,92.85},
{53.95,91.99},{54.47,105.25},{56.70,104.89},{16.59,46.52},
{71.56,115.18},{80.62,99.79},{71.29,101.42},{16.81,56.15},
{48.88,84.93},{ 8.41,40.02},{93.98,147.39},{39.20,86.04},
{61.75,90.80},{ 1.06,32.69},{21.40,33.33},{ 8.60,28.69},
{38.80,61.88},{14.41,38.37},{40.14,70.01},{69.45,105.44},
{14.41,43.93},{51.20,93.11},{39.10,57.10},{21.04,39.51},
{10.12,30.43},{70.13,93.88},{ 1.74,20.56},{12.23,34.33},
{98.81,151.87},{50.48,92.07},{ 6.98, 9.52},{24.08,69.94},
{15.72,40.89},{83.99,127.44},{47.21,90.46},{88.31,138.70},
{91.05,132.13},{45.22,62.24},{87.76,128.67},{99.37,168.24},
{94.38,140.24},{31.30,67.65},{40.85,84.03},{40.91,79.56},
{77.14,135.74},{50.92,80.52},{17.81,49.14},{90.30,135.15},
{28.44,64.60},{49.23,85.12},{81.63,141.58},{83.04,111.19},
{28.39,63.30},{ 8.61,44.11},{25.36,50.79},{51.35,93.32},
{64.49,80.42},{96.17,134.31},{96.10,144.32},{47.58,83.36},
{94.38,131.03},{41.97,69.05},{37.86,62.21},{26.97,65.30},
{37.57,88.95},{65.08,108.58},{17.68,39.80},{63.75,103.14},
{91.86,132.07},{76.35,121.19},{22.98,34.87},{96.46,140.54},
{ 9.38,31.40},{42.97,82.09},{20.56,49.02},{13.73,41.31},
{37.35,63.18},{69.54,105.57},{38.17,83.30},{47.04,80.34},
{48.79,98.00},{39.34,61.59},{82.57,125.55},{40.77,82.18},
{13.62,53.38},{35.33,95.17},{95.36,148.79},{20.25,62.00},
{47.48,86.54},{30.22,61.07},{83.90,120.30},{85.81,123.25},
{84.29,130.44},{52.84,95.43},{96.72,140.32},{ 3.29,45.68},
{71.77,98.66},{ 8.52,42.40},{22.55,54.27},{15.08,47.10},
{91.29,130.23},{16.48,40.04},{44.84,72.14},{34.44,73.42},
{36.26,78.30},{58.45,115.51},{96.59,150.22},{63.80,98.30},
{85.92,120.14},{93.68,129.88},{74.09,119.30},{99.44,136.93},
{88.39,131.55},{64.40,117.89},{13.87,47.30},{81.17,106.77}
};
__device__ double d_residual_error(double x, double y, double m, double c) {
double e = (m * x) + c - y;
return e * e;
}
__global__ void d_rms_error(double *m, double *c, double *error_sum_arr, point_t *d_data) {
/*
Using the current index calculation:
- The thread id
- The block id
- The number of threads per block
*/
int i = threadIdx.x + blockIdx.x * blockDim.x;
//Error of sum stored in the array
error_sum_arr[i] = d_residual_error(d_data[i].x, d_data[i].y, *m, *c);
} | code for sm_80
Function : _Z11d_rms_errorPdS_S_P7point_t
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff057435 */
/* 0x000fe200000001ff */
/*0030*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff087624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R9, c[0x0][0x164] ; /* 0x0000590000097a02 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0060*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0a7624 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R11, c[0x0][0x16c] ; /* 0x00005b00000b7a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0090*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1b00 */
/*00a0*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea2000c1e1b00 */
/*00b0*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc800078e0200 */
/*00c0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fca00078e0205 */
/*00d0*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1b00 */
/*00e0*/ LDG.E.64 R6, [R2.64+0x8] ; /* 0x0000080402067981 */
/* 0x000ee2000c1e1b00 */
/*00f0*/ DFMA R4, R4, R8, R10 ; /* 0x000000080404722b */
/* 0x004ecc000000000a */
/*0100*/ DADD R4, -R6, R4 ; /* 0x0000000006047229 */
/* 0x0080640000000104 */
/*0110*/ MOV R7, 0x8 ; /* 0x0000000800077802 */
/* 0x001fc80000000f00 */
/*0120*/ DMUL R4, R4, R4 ; /* 0x0000000404047228 */
/* 0x002e220000000000 */
/*0130*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fcc00078e0207 */
/*0140*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x001fe2000c101b04 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/******************************************************************************
* This program takes an initial estimate of m and c and finds the associated
* rms error. It is then as a base to generate and evaluate 8 new estimates,
* which are steps in different directions in m-c space. The best estimate is
* then used as the base for another iteration of "generate and evaluate". This
* continues until none of the new estimates are better than the base. This is
* a gradient search for a minimum in mc-space.
*
* To compile:
* nvcc -o cuda_linear_regression CUDA_linear_regression.c -lm
*
* To run:
* ./cuda_linear_regression
*
* Dr Kevan Buckley, University of Wolverhampton, 2018
*****************************************************************************/
typedef struct point_t {
double x;
double y;
} point_t;
int n_data = 1000;
__device__ int d_n_data = 1000; //device varialble
//date set
point_t data[] = {
{82.73,128.67},{79.53,133.54},{66.86,124.65},{69.21,135.74},
{82.20,122.07},{84.32,120.46},{71.12,93.14},{85.64,121.42},
{69.22,116.28},{83.12,137.30},{84.31,113.18},{75.60,121.42},
{69.04,91.83},{85.41,131.06},{17.44,58.69},{68.92,119.86},
{69.95,110.05},{ 0.15, 5.39},{73.96,118.70},{27.70,64.64},
{97.97,158.15},{56.21,100.99},{30.27,48.32},{37.47,89.65},
{98.98,144.03},{92.61,133.89},{ 4.72,32.88},{19.51,57.43},
{94.74,145.50},{31.66,71.27},{94.76,134.53},{32.73,59.95},
{32.64,54.53},{38.78,69.06},{91.47,150.49},{77.99,119.35},
{33.38,65.87},{79.28,123.62},{39.69,72.53},{95.47,140.97},
{82.64,137.69},{25.53,51.33},{68.58,85.98},{92.25,132.34},
{74.79,101.30},{ 1.32,18.87},{53.85,95.13},{78.75,128.26},
{ 2.91,21.77},{90.68,128.55},{11.44,35.27},{30.72,56.54},
{49.06,74.08},{49.09,83.45},{62.54,104.58},{38.83,72.26},
{78.43,130.83},{69.49,122.49},{27.27,56.35},{80.06,131.95},
{ 5.73,39.00},{80.21,140.42},{ 8.47,36.12},{86.98,152.43},
{64.26,108.56},{95.74,133.36},{15.06,48.67},{31.96,72.31},
{95.27,141.34},{61.10,89.26},{27.51,68.47},{26.48,60.30},
{92.61,128.38},{ 8.25,47.51},{90.69,118.91},{45.40,79.96},
{23.59,53.12},{46.71,68.27},{21.15,50.29},{27.99,76.29},
{ 7.75,43.57},{13.70,43.56},{74.85,97.83},{50.93,103.11},
{33.80,64.85},{80.99,125.37},{92.41,126.27},{92.61,134.36},
{34.70,55.32},{35.07,55.04},{86.87,157.26},{41.99,90.46},
{16.27,44.43},{36.31,83.84},{22.35,73.11},{89.11,127.19},
{56.11,77.28},{51.90,75.07},{35.74,94.18},{10.66,29.60},
{61.27,114.15},{77.55,117.04},{61.17,99.68},{15.54,55.33},
{91.99,143.18},{12.91,21.82},{48.52,89.94},{54.88,90.86},
{73.59,131.33},{ 5.49,13.95},{92.31,147.29},{48.50,89.49},
{40.02,58.26},{48.22,81.96},{17.08,52.59},{34.27,66.17},
{59.06,94.26},{92.71,134.53},{37.70,65.30},{77.11,111.38},
{43.27,74.12},{79.71,123.45},{ 0.86,38.69},{ 3.00,17.76},
{56.03,80.33},{17.66,43.27},{18.39,47.08},{31.08,83.84},
{32.64,77.85},{51.68,84.57},{78.46,134.18},{ 9.57,40.28},
{68.38,98.26},{30.29,67.59},{86.15,131.86},{16.82,64.91},
{ 3.35,20.88},{65.78,98.73},{50.70,90.92},{38.26,71.11},
{85.52,132.23},{44.06,83.02},{44.09,86.42},{81.86,114.30},
{33.98,69.09},{93.80,147.73},{59.58,103.07},{98.75,154.73},
{88.98,120.59},{78.08,109.00},{82.77,133.94},{76.49,106.31},
{55.38,85.71},{46.56,79.57},{83.92,141.58},{81.38,133.52},
{ 4.88,35.01},{ 4.57,17.99},{57.96,90.07},{33.42,63.80},
{ 9.95,34.53},{47.14,92.75},{63.17,105.19},{95.01,163.93},
{30.36,57.81},{ 2.46,23.97},{69.75,115.88},{64.85,111.01},
{25.18,56.58},{69.84,104.78},{40.43,51.98},{75.61,107.05},
{36.75,69.37},{50.08,100.02},{64.97,103.68},{41.72,86.64},
{ 1.70,47.26},{99.93,141.75},{24.57,64.51},{75.23,116.35},
{ 1.95,18.53},{78.84,102.70},{67.38,97.71},{55.35,82.37},
{58.10,100.09},{53.10,96.07},{41.24,83.81},{68.86,111.98},
{87.36,86.88},{54.06,98.42},{64.12,90.56},{11.77,49.66},
{99.43,134.33},{55.24,99.18},{56.44,74.73},{39.47,62.99},
{ 8.94,48.15},{92.91,130.45},{87.68,138.76},{80.37,116.69},
{56.72,108.65},{ 0.76,24.26},{26.98,75.13},{ 0.39,42.16},
{81.99,138.50},{88.32,117.16},{51.01,87.42},{21.38,55.45},
{72.66,122.82},{18.04,53.56},{11.22,49.73},{36.75,60.26},
{64.81,90.19},{72.72,121.14},{24.03,74.08},{41.38,81.38},
{62.79,98.75},{63.66,109.17},{91.12,143.91},{ 7.41,34.06},
{94.05,131.99},{53.12,90.28},{68.31,114.79},{25.33,67.23},
{42.34,86.91},{94.61,131.38},{43.78,73.28},{50.18,78.10},
{81.64,135.88},{11.27,44.45},{41.03,76.34},{21.25,57.54},
{29.23,57.27},{35.74,75.16},{ 0.91,14.33},{30.08,59.05},
{23.99,56.25},{90.79,120.98},{99.22,152.22},{94.21,143.09},
{19.35,30.03},{82.04,113.25},{79.22,113.69},{83.40,144.06},
{55.82,80.85},{42.49,48.94},{17.60,55.62},{35.65,81.91},
{82.50,135.41},{81.15,114.46},{53.47,78.67},{44.30,73.73},
{32.88,80.28},{99.26,147.55},{76.32,110.24},{78.97,110.27},
{18.08,47.48},{87.01,140.40},{56.25,83.61},{42.62,55.40},
{15.95,16.25},{47.85,106.69},{ 6.61,35.83},{66.38,116.30},
{94.97,122.56},{42.29,73.37},{31.48,67.15},{69.67,105.40},
{30.41,65.31},{ 2.98,19.40},{ 8.12,48.34},{80.41,127.03},
{63.68,112.61},{24.60,78.23},{77.61,123.49},{39.87,38.20},
{77.80,109.59},{58.53,107.63},{23.97,62.36},{ 7.77,27.38},
{ 0.80,41.55},{ 6.45,32.91},{45.32,82.24},{35.56,59.56},
{65.05,97.68},{62.21,96.14},{86.61,121.99},{87.91,125.40},
{48.08,88.87},{ 2.41,40.02},{69.55,119.31},{22.07,61.86},
{61.87,121.40},{82.50,119.46},{26.97,38.40},{31.53,86.30},
{ 1.81,38.57},{72.57,108.34},{88.88,139.23},{63.90,95.79},
{93.29,135.35},{86.26,143.55},{63.62,94.76},{20.24,38.84},
{16.23,48.64},{72.87,108.22},{16.26,51.25},{37.86,66.06},
{57.53,81.37},{61.66,97.20},{49.48,84.98},{95.20,142.45},
{12.10,45.25},{47.79,84.80},{17.29,48.98},{47.11,87.23},
{85.74,119.95},{89.94,142.94},{97.68,155.27},{78.73,123.81},
{51.65,85.91},{52.82,96.05},{50.95,93.50},{16.14,37.21},
{16.73,41.57},{57.25,95.50},{78.47,136.77},{42.35,75.64},
{93.24,135.04},{12.56,38.20},{21.40,62.92},{70.60,136.98},
{44.04,83.57},{ 6.43,36.61},{12.01,50.32},{79.61,119.78},
{43.05,69.07},{14.42,53.01},{51.68,83.82},{25.59,55.77},
{ 9.14,31.58},{37.24,80.94},{15.73,69.21},{71.54,123.11},
{ 1.26,25.72},{ 4.25,38.46},{21.42,39.99},{44.12,79.01},
{31.12,64.63},{85.27,143.62},{43.25,79.30},{77.27,104.30},
{47.34,83.76},{90.57,125.82},{17.35,36.40},{82.01,130.41},
{81.58,124.10},{68.62,117.62},{47.48,79.29},{ 4.30,26.77},
{ 6.94,32.22},{11.71,55.76},{22.62,54.74},{58.43,89.61},
{69.10,111.51},{56.77,101.10},{67.10,102.75},{93.20,144.51},
{83.61,128.56},{71.97,116.09},{75.19,122.16},{48.03,79.67},
{97.95,143.80},{92.27,123.08},{23.88,63.39},{79.15,115.57},
{24.42,51.27},{12.58,34.65},{46.58,78.16},{ 1.29,37.96},
{17.09,45.61},{12.45,40.77},{82.75,107.46},{52.15,75.34},
{39.51,68.51},{31.71,64.23},{39.36,72.00},{12.16,37.99},
{83.13,127.76},{42.25,73.17},{45.32,77.14},{20.52,36.60},
{ 7.99,11.50},{23.34,55.47},{25.87,54.36},{78.73,112.49},
{55.60,94.90},{31.98,73.40},{85.93,137.12},{58.56,97.64},
{88.16,120.43},{78.65,136.60},{25.93,43.32},{84.83,136.32},
{68.09,102.12},{68.36,111.80},{39.80,69.69},{ 0.38,27.89},
{ 4.49,27.85},{32.53,66.32},{54.23,97.63},{19.98,67.32},
{90.62,143.43},{18.31,67.91},{95.66,146.41},{95.41,149.68},
{71.64,111.15},{23.02,44.96},{97.06,154.54},{41.58,75.95},
{79.80,130.01},{74.55,119.44},{72.19,113.27},{70.01,106.48},
{75.24,94.18},{19.82,60.09},{96.31,137.91},{ 2.21,27.44},
{40.52,70.36},{ 2.40,29.12},{35.24,57.25},{26.38,71.34},
{26.02,59.48},{34.73,66.07},{45.15,78.23},{ 9.35,32.58},
{19.37,57.18},{ 9.51,31.70},{15.03,49.81},{85.08,140.35},
{ 3.23,13.46},{58.26,108.47},{ 4.84,31.78},{49.49,83.50},
{35.55,70.67},{26.51,55.44},{20.12,53.39},{72.73,119.37},
{31.04,72.96},{30.66,58.35},{ 2.96,33.18},{18.68,31.50},
{91.41,138.24},{44.67,81.81},{81.57,135.26},{ 0.17,26.66},
{49.03,100.11},{54.47,102.27},{61.78,113.45},{22.67,59.51},
{89.80,143.05},{33.05,78.20},{67.76,108.19},{ 7.64,41.18},
{36.91,87.28},{95.44,147.27},{52.76,94.34},{ 3.52,29.51},
{87.39,118.48},{41.48,64.71},{ 1.44,14.21},{95.04,136.99},
{71.77,115.75},{23.39,47.58},{62.66,115.03},{15.98,34.38},
{29.06,62.77},{ 2.94,28.25},{71.50,119.18},{65.24,119.14},
{30.65,82.39},{16.36,38.82},{ 0.98,48.82},{33.19,56.41},
{27.49,64.34},{53.69,102.47},{28.15,52.58},{40.21,66.07},
{50.56,86.39},{74.71,97.44},{24.72,46.29},{48.05,80.63},
{34.99,52.13},{66.75,115.96},{17.62,49.17},{98.99,157.80},
{37.96,72.18},{56.88,105.06},{48.27,97.04},{71.18,138.90},
{46.35,82.02},{10.43,44.65},{24.14,42.85},{82.21,144.13},
{96.85,148.15},{93.68,126.32},{33.02,61.55},{66.73,108.51},
{83.89,136.35},{80.85,91.16},{79.21,128.88},{84.37,119.84},
{38.41,71.48},{47.49,85.53},{ 1.54,24.44},{68.32,106.44},
{22.82,54.16},{ 2.65,16.35},{19.91,53.53},{12.99,34.98},
{30.87,57.17},{44.10,83.88},{15.84,31.99},{36.46,59.74},
{26.25,79.73},{79.12,132.06},{86.26,132.45},{ 0.61,23.61},
{33.94,59.37},{99.92,145.88},{26.20,53.99},{69.77,115.40},
{69.07,107.00},{ 1.89,17.20},{38.25,81.40},{27.08,62.96},
{23.09,53.98},{55.56,86.93},{ 6.68,50.41},{22.86,49.26},
{17.25,50.25},{19.01,50.16},{35.07,85.09},{59.08,89.15},
{87.02,128.83},{ 1.57,27.68},{97.76,148.25},{70.78,108.00},
{38.01,65.83},{96.41,139.67},{ 2.86,22.44},{27.05,53.00},
{90.99,134.97},{86.60,145.27},{54.66,99.42},{67.61,107.07},
{85.16,137.50},{87.64,144.60},{14.69,36.65},{16.08,49.31},
{14.45,44.07},{65.91,98.39},{50.74,90.72},{ 6.98,31.11},
{52.76,83.96},{ 8.03,43.93},{17.58,52.58},{33.63,59.04},
{87.65,137.34},{77.97,142.54},{30.56,69.47},{59.61,114.61},
{14.05,53.07},{87.65,116.66},{33.19,75.96},{31.87,66.95},
{25.89,57.59},{48.60,75.67},{80.25,109.89},{ 6.61,24.27},
{ 4.56,44.00},{40.17,62.33},{92.32,117.73},{75.07,112.71},
{17.10,35.12},{39.06,66.60},{ 4.26,34.01},{52.95,102.49},
{45.73,76.57},{ 4.72,29.94},{ 2.01,17.54},{39.08,88.44},
{82.94,141.75},{44.51,90.97},{27.27,63.14},{60.16,95.38},
{41.26,72.59},{66.50,104.49},{58.37,110.13},{62.11,96.01},
{70.30,90.15},{18.47,47.61},{24.80,51.82},{79.02,133.40},
{96.61,147.92},{18.14,33.27},{ 0.83,51.20},{99.67,143.65},
{34.07,67.38},{57.28,110.02},{35.92,59.90},{66.15,124.45},
{81.82,135.08},{ 2.97,28.49},{95.97,135.79},{51.17,80.95},
{91.47,142.00},{94.09,121.08},{57.70,82.98},{67.96,100.92},
{81.91,132.34},{11.55,39.74},{86.59,126.05},{ 5.36,41.72},
{90.86,144.15},{81.02,137.56},{35.87,81.76},{63.73,105.92},
{78.29,129.54},{96.72,150.04},{14.97,61.93},{45.76,77.17},
{82.69,123.95},{85.82,132.89},{85.95,127.24},{15.04,36.92},
{89.91,112.87},{30.86,58.13},{ 5.77,42.22},{75.24,108.41},
{ 8.43,32.09},{90.70,147.99},{80.16,112.57},{42.81,73.54},
{82.47,123.41},{48.23,98.48},{77.48,143.96},{ 0.48,14.50},
{29.75,63.12},{88.76,137.72},{33.59,70.61},{22.74,43.51},
{82.15,116.11},{89.10,120.65},{26.56,68.17},{40.72,74.98},
{68.46,99.23},{34.82,66.71},{36.56,67.33},{72.32,114.23},
{29.65,65.99},{44.39,64.83},{82.08,116.35},{99.73,139.12},
{79.04,118.48},{20.78,42.05},{72.39,96.47},{90.62,147.11},
{35.99,59.11},{50.65,83.23},{59.04,100.47},{87.01,145.78},
{43.71,76.56},{95.61,151.81},{50.25,88.96},{69.64,122.07},
{40.07,79.38},{82.61,133.63},{20.84,39.75},{10.28,42.50},
{47.43,70.82},{30.47,67.19},{69.16,100.10},{46.06,74.00},
{93.78,152.76},{19.93,67.46},{79.61,130.88},{81.11,120.11},
{76.16,123.94},{75.84,111.70},{50.97,85.30},{47.35,90.59},
{93.21,115.44},{19.22,39.30},{11.67,29.58},{52.48,95.64},
{38.76,59.62},{ 2.74,-2.03},{18.99,63.67},{82.38,128.08},
{15.68,32.34},{39.19,83.38},{31.06,65.92},{28.91,73.05},
{19.01,59.69},{76.62,117.74},{36.82,91.33},{86.28,121.19},
{39.26,50.72},{41.45,70.26},{65.81,111.41},{77.09,117.88},
{78.96,128.48},{16.41,56.61},{39.54,64.11},{72.45,110.54},
{48.83,77.35},{27.61,51.82},{26.53,47.44},{83.06,111.09},
{97.06,127.57},{89.01,146.82},{89.44,141.17},{69.18,100.25},
{ 1.11,11.60},{71.63,123.66},{92.93,151.73},{99.46,165.34},
{36.49,71.56},{95.48,153.13},{65.33,102.37},{15.28,35.93},
{ 5.52,36.67},{ 0.78,42.47},{10.09,36.68},{ 5.75,37.39},
{52.34,89.11},{14.55,47.37},{67.92,113.35},{36.66,77.34},
{99.76,143.75},{26.67,58.72},{ 3.21,39.37},{87.70,124.12},
{90.03,131.24},{51.54,91.39},{62.86,98.04},{52.75,90.87},
{34.17,84.31},{62.00,89.08},{82.47,111.89},{61.38,123.48},
{47.17,84.64},{20.91,53.51},{96.96,131.54},{46.06,85.14},
{26.85,71.44},{91.67,138.51},{54.07,85.26},{51.63,89.63},
{94.04,140.80},{67.75,107.07},{29.24,76.71},{38.29,75.78},
{28.49,72.87},{60.51,102.28},{77.22,107.79},{99.25,145.86},
{33.11,52.32},{72.47,125.80},{21.97,59.23},{14.25,61.11},
{23.79,63.11},{77.78,109.13},{23.51,81.38},{66.92,110.89},
{79.81,109.80},{56.72,94.63},{59.60,110.57},{57.68,104.54},
{27.83,42.43},{47.80,87.68},{58.79,76.51},{78.33,126.71},
{85.14,128.99},{71.61,116.42},{58.09,96.85},{44.89,71.34},
{33.12,80.19},{98.79,130.09},{44.57,82.03},{88.63,142.61},
{61.96,98.55},{58.54,106.80},{19.17,61.00},{13.51,26.68},
{76.68,124.52},{82.62,138.53},{78.13,122.09},{37.10,60.33},
{ 8.82,48.63},{71.64,105.27},{68.44,115.07},{ 7.66,61.91},
{64.37,96.58},{54.90,88.28},{78.35,133.29},{79.84,129.58},
{ 3.09,28.37},{48.62,76.00},{38.26,63.99},{42.05,102.17},
{48.89,73.66},{54.38,100.05},{11.16,55.43},{63.24,110.69},
{68.17,114.15},{68.68,109.15},{53.43,90.23},{67.45,106.67},
{10.60,34.41},{56.81,90.86},{11.42,27.08},{36.93,93.13},
{41.64,89.77},{69.74,103.98},{23.07,55.12},{44.98,83.65},
{35.75,72.65},{14.80,56.15},{72.19,115.53},{51.10,80.69},
{96.54,140.10},{15.04,62.30},{21.17,56.15},{46.42,79.63},
{22.35,52.01},{35.47,54.95},{ 4.27,21.33},{84.37,139.55},
{43.95,93.24},{86.56,132.82},{44.35,83.36},{76.81,114.79},
{ 1.05,31.66},{32.76,76.15},{83.66,120.90},{12.14,42.52},
{25.85,55.83},{82.12,140.05},{75.33,126.93},{32.92,75.90},
{ 7.52,24.51},{25.42,41.55},{42.57,67.15},{87.36,150.38},
{ 0.51,17.68},{45.70,84.75},{58.74,88.68},{28.62,74.38},
{73.22,113.45},{78.64,114.25},{42.40,92.03},{84.22,132.25},
{54.24,73.34},{ 2.71,30.27},{54.11,84.97},{66.74,112.66},
{28.80,57.88},{87.02,146.20},{32.02,63.03},{59.57,94.41},
{40.46,79.73},{23.74,49.78},{87.58,140.94},{84.15,113.32},
{32.48,63.48},{ 4.59,25.85},{98.00,128.35},{12.23,37.43},
{66.17,102.97},{50.73,93.82},{74.68,137.79},{43.72,92.85},
{53.95,91.99},{54.47,105.25},{56.70,104.89},{16.59,46.52},
{71.56,115.18},{80.62,99.79},{71.29,101.42},{16.81,56.15},
{48.88,84.93},{ 8.41,40.02},{93.98,147.39},{39.20,86.04},
{61.75,90.80},{ 1.06,32.69},{21.40,33.33},{ 8.60,28.69},
{38.80,61.88},{14.41,38.37},{40.14,70.01},{69.45,105.44},
{14.41,43.93},{51.20,93.11},{39.10,57.10},{21.04,39.51},
{10.12,30.43},{70.13,93.88},{ 1.74,20.56},{12.23,34.33},
{98.81,151.87},{50.48,92.07},{ 6.98, 9.52},{24.08,69.94},
{15.72,40.89},{83.99,127.44},{47.21,90.46},{88.31,138.70},
{91.05,132.13},{45.22,62.24},{87.76,128.67},{99.37,168.24},
{94.38,140.24},{31.30,67.65},{40.85,84.03},{40.91,79.56},
{77.14,135.74},{50.92,80.52},{17.81,49.14},{90.30,135.15},
{28.44,64.60},{49.23,85.12},{81.63,141.58},{83.04,111.19},
{28.39,63.30},{ 8.61,44.11},{25.36,50.79},{51.35,93.32},
{64.49,80.42},{96.17,134.31},{96.10,144.32},{47.58,83.36},
{94.38,131.03},{41.97,69.05},{37.86,62.21},{26.97,65.30},
{37.57,88.95},{65.08,108.58},{17.68,39.80},{63.75,103.14},
{91.86,132.07},{76.35,121.19},{22.98,34.87},{96.46,140.54},
{ 9.38,31.40},{42.97,82.09},{20.56,49.02},{13.73,41.31},
{37.35,63.18},{69.54,105.57},{38.17,83.30},{47.04,80.34},
{48.79,98.00},{39.34,61.59},{82.57,125.55},{40.77,82.18},
{13.62,53.38},{35.33,95.17},{95.36,148.79},{20.25,62.00},
{47.48,86.54},{30.22,61.07},{83.90,120.30},{85.81,123.25},
{84.29,130.44},{52.84,95.43},{96.72,140.32},{ 3.29,45.68},
{71.77,98.66},{ 8.52,42.40},{22.55,54.27},{15.08,47.10},
{91.29,130.23},{16.48,40.04},{44.84,72.14},{34.44,73.42},
{36.26,78.30},{58.45,115.51},{96.59,150.22},{63.80,98.30},
{85.92,120.14},{93.68,129.88},{74.09,119.30},{99.44,136.93},
{88.39,131.55},{64.40,117.89},{13.87,47.30},{81.17,106.77}
};
__device__ double d_residual_error(double x, double y, double m, double c) {
double e = (m * x) + c - y;
return e * e;
}
__global__ void d_rms_error(double *m, double *c, double *error_sum_arr, point_t *d_data) {
/*
Using the current index calculation:
- The thread id
- The block id
- The number of threads per block
*/
int i = threadIdx.x + blockIdx.x * blockDim.x;
//Error of sum stored in the array
error_sum_arr[i] = d_residual_error(d_data[i].x, d_data[i].y, *m, *c);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11d_rms_errorPdS_S_P7point_t
.globl _Z11d_rms_errorPdS_S_P7point_t
.p2align 8
.type _Z11d_rms_errorPdS_S_P7point_t,@function
_Z11d_rms_errorPdS_S_P7point_t:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x2c
s_load_b256 s[0:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s8, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, s15, s8, v[0:1]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 4, v[4:5]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b128 v[0:3], v[0:1], off
s_load_b64 s[0:1], s[0:1], 0x0
s_load_b64 s[2:3], s[2:3], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f64 v[0:1], v[0:1], s[0:1], s[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[0:1], -v[2:3]
v_lshlrev_b64 v[2:3], 3, v[4:5]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
v_mul_f64 v[0:1], v[0:1], v[0:1]
global_store_b64 v[2:3], v[0:1], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11d_rms_errorPdS_S_P7point_t
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11d_rms_errorPdS_S_P7point_t, .Lfunc_end0-_Z11d_rms_errorPdS_S_P7point_t
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected d_n_data
.type d_n_data,@object
.data
.globl d_n_data
.p2align 2, 0x0
d_n_data:
.long 1000
.size d_n_data, 4
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11d_rms_errorPdS_S_P7point_t
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11d_rms_errorPdS_S_P7point_t.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11d_rms_errorPdS_S_P7point_t
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff057435 */
/* 0x000fe200000001ff */
/*0030*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff087624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R9, c[0x0][0x164] ; /* 0x0000590000097a02 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0060*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0a7624 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R11, c[0x0][0x16c] ; /* 0x00005b00000b7a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0090*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1b00 */
/*00a0*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea2000c1e1b00 */
/*00b0*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc800078e0200 */
/*00c0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fca00078e0205 */
/*00d0*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1b00 */
/*00e0*/ LDG.E.64 R6, [R2.64+0x8] ; /* 0x0000080402067981 */
/* 0x000ee2000c1e1b00 */
/*00f0*/ DFMA R4, R4, R8, R10 ; /* 0x000000080404722b */
/* 0x004ecc000000000a */
/*0100*/ DADD R4, -R6, R4 ; /* 0x0000000006047229 */
/* 0x0080640000000104 */
/*0110*/ MOV R7, 0x8 ; /* 0x0000000800077802 */
/* 0x001fc80000000f00 */
/*0120*/ DMUL R4, R4, R4 ; /* 0x0000000404047228 */
/* 0x002e220000000000 */
/*0130*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fcc00078e0207 */
/*0140*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x001fe2000c101b04 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11d_rms_errorPdS_S_P7point_t
.globl _Z11d_rms_errorPdS_S_P7point_t
.p2align 8
.type _Z11d_rms_errorPdS_S_P7point_t,@function
_Z11d_rms_errorPdS_S_P7point_t:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x2c
s_load_b256 s[0:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s8, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, s15, s8, v[0:1]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 4, v[4:5]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b128 v[0:3], v[0:1], off
s_load_b64 s[0:1], s[0:1], 0x0
s_load_b64 s[2:3], s[2:3], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f64 v[0:1], v[0:1], s[0:1], s[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[0:1], -v[2:3]
v_lshlrev_b64 v[2:3], 3, v[4:5]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
v_mul_f64 v[0:1], v[0:1], v[0:1]
global_store_b64 v[2:3], v[0:1], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11d_rms_errorPdS_S_P7point_t
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11d_rms_errorPdS_S_P7point_t, .Lfunc_end0-_Z11d_rms_errorPdS_S_P7point_t
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected d_n_data
.type d_n_data,@object
.data
.globl d_n_data
.p2align 2, 0x0
d_n_data:
.long 1000
.size d_n_data, 4
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11d_rms_errorPdS_S_P7point_t
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11d_rms_errorPdS_S_P7point_t.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <math.h>
#include <time.h>
#include <stdlib.h>
#include <random>
#include <vector>
#include <chrono>
#include <deque>
#include <algorithm>
#include <iterator>
#include <set>
#define BLOCK_SIZE 1024
struct bstree {
int *left_child;
int *right_child;
int *parent;
bool *flag;
};
__global__ void populate_child_parent(float *arr, int *i_left_child, int *i_right_child, int *i_parent, int *o_left_child, int *o_right_child, int *o_parent, bool *flag, const int n) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) {
int y = i_parent[i];
if (i_left_child[i] == -1 && i_right_child[i] == -1 && i != y) {
flag[0] = true;
int x, p;
if (arr[i] <= arr[y]) {
p = i_left_child[y];
x = (p != -1) ? p:y;
o_parent[i] = x;
}
else {
p = i_right_child[y];
x = (p != -1) ? p:y;
o_parent[i] = x;
}
if (i != x) {
if (arr[i] <= arr[x]) {
if (o_left_child[x] == -1) {
o_left_child[x] = i;
}
}
else {
if (o_right_child[x] == -1) {
o_right_child[x] = i;
}
}
}
}
}
}
__global__ void copy_arr(int *in_arr, int *out_arr, const int n) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) {
out_arr[i] = in_arr[i];
}
}
void copy_array(int *arr1, int *arr2, const int n) {
cudaStream_t stream;
cudaStreamCreate(&stream);
copy_arr<<<(n + BLOCK_SIZE - 1)/BLOCK_SIZE, BLOCK_SIZE, 0, stream>>>(arr1, arr2, n);
cudaDeviceSynchronize();
cudaStreamDestroy(stream);
}
void random_vector(float *arr, const int n, const float min_val=0.0, const float max_val=1000.0) {
static std::random_device rd;
static std::mt19937 mte(rd());
std::uniform_real_distribution<float> dist(min_val, max_val);
for (int i = 0; i < n; i++) {
arr[i] = dist(mte);
}
}
bstree construct_binary_tree(float *arr, bstree g, bstree g1, const int n) {
copy_array(g.left_child, g1.left_child, n);
copy_array(g.right_child, g1.right_child, n);
copy_array(g.parent, g1.parent, n);
g1.flag[0] = false;
populate_child_parent<<<(n + BLOCK_SIZE - 1)/BLOCK_SIZE, BLOCK_SIZE>>>(arr, g.left_child, g.right_child, g.parent, g1.left_child, g1.right_child, g1.parent, g1.flag, n);
cudaDeviceSynchronize();
return g1;
}
bstree bs_tree(float *arr, int root_index, bstree g, bstree g1, const int n) {
g.flag[0] = true;
while (g.flag[0]) {
g = construct_binary_tree(arr, g, g1, n);
}
return g;
}
float *traversal(float *arr, int *left_child, int *right_child, int root_index, const int n) {
int *stack = new int[n];
float *out = new float[n];
stack[0] = root_index;
int p = 1;
int i = 0;
std::set<int> visited;
while (p > 0) {
int curr_root = stack[p-1];
if (left_child[curr_root] != -1 && visited.find(left_child[curr_root]) == visited.end()) {
stack[p++] = left_child[curr_root];
}
else {
if (visited.find(curr_root) == visited.end()) {
out[i++] = arr[curr_root];
visited.insert(curr_root);
}
if (right_child[curr_root] != -1 && visited.find(right_child[curr_root]) == visited.end()) {
stack[p++] = right_child[curr_root];
}
else {
p -= 1;
}
}
}
return out;
}
float *inorder_traversal(float *arr, bstree g, bstree g1, const int n) {
int root_index = rand() % static_cast<int>(n);
std::fill(g.parent, g.parent+n, root_index);
auto t1 = std::chrono::high_resolution_clock::now();
g = bs_tree(arr, root_index, g, g1, n);
auto t2 = std::chrono::high_resolution_clock::now();
auto duration = std::chrono::duration_cast<std::chrono::milliseconds>( t2 - t1 ).count();
std::cout << duration << std::endl;
return traversal(arr, g.left_child, g.right_child, root_index, n);
}
bool check_correctness(float *arr, float *pred_arr, const int n) {
std::sort(arr, arr+n);
for (int i = 0; i < n ; i++) {
if (arr[i] != pred_arr[i]) {
return false;
}
}
return true;
}
int main(void) {
int n = 1 << 25;
float *arr, *temp;
cudaMallocManaged(&arr, n*sizeof(float));
random_vector(arr, n, 0, 10000);
temp = new float[n];
std::copy(arr, arr+n, temp);
bstree g, g1;
cudaMallocManaged(&g.left_child, n*sizeof(int));
cudaMallocManaged(&g.right_child, n*sizeof(int));
cudaMallocManaged(&g.parent, n*sizeof(int));
cudaMallocManaged(&g.flag, sizeof(bool));
cudaMallocManaged(&g1.left_child, n*sizeof(int));
cudaMallocManaged(&g1.right_child, n*sizeof(int));
cudaMallocManaged(&g1.parent, n*sizeof(int));
cudaMallocManaged(&g1.flag, sizeof(bool));
std::fill(g.left_child, g.left_child+n, -1);
std::fill(g.right_child, g.right_child+n, -1);
auto t1 = std::chrono::high_resolution_clock::now();
float *pred = inorder_traversal(arr, g, g1, n);
auto t2 = std::chrono::high_resolution_clock::now();
auto duration = std::chrono::duration_cast<std::chrono::milliseconds>( t2 - t1 ).count();
std::cout << duration << std::endl;
t1 = std::chrono::high_resolution_clock::now();
std::cout << check_correctness(temp, pred, n) << std::endl;
t2 = std::chrono::high_resolution_clock::now();
duration = std::chrono::duration_cast<std::chrono::milliseconds>( t2 - t1 ).count();
std::cout << duration << std::endl;
cudaFree(arr);
cudaFree(g.left_child);
cudaFree(g.right_child);
cudaFree(g.parent);
cudaFree(g.flag);
cudaFree(g1.left_child);
cudaFree(g1.right_child);
cudaFree(g1.parent);
cudaFree(g1.flag);
return 0;
} | code for sm_80
Function : _Z8copy_arrPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0205 */
/*00b0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z21populate_child_parentPfPiS0_S0_S0_S0_S0_Pbi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x1a0], PT ; /* 0x0000680000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R6, R0, R5, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ SHF.R.S32.HI R11, RZ, 0x1f, R0 ; /* 0x0000001fff0b7819 */
/* 0x000fe20000011400 */
/*00b0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fca00078e0205 */
/*00c0*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000ee2000c1e1900 */
/*00d0*/ ISETP.NE.AND P0, PT, R6, -0x1, PT ; /* 0xffffffff0600780c */
/* 0x004fda0003f05270 */
/*00e0*/ @!P0 LEA R8, P1, R0, c[0x0][0x170], 0x2 ; /* 0x00005c0000088a11 */
/* 0x000fc800078210ff */
/*00f0*/ @!P0 LEA.HI.X R9, R0, c[0x0][0x174], R11, 0x2, P1 ; /* 0x00005d0000098a11 */
/* 0x000fca00008f140b */
/*0100*/ @!P0 LDG.E R8, [R8.64] ; /* 0x0000000408088981 */
/* 0x000ea4000c1e1900 */
/*0110*/ ISETP.EQ.AND P0, PT, R8, -0x1, !P0 ; /* 0xffffffff0800780c */
/* 0x004fc80004702270 */
/*0120*/ ISETP.EQ.OR P0, PT, R0, R13, !P0 ; /* 0x0000000d0000720c */
/* 0x008fda0004702670 */
/*0130*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0140*/ SHF.R.S32.HI R2, RZ, 0x1f, R13 ; /* 0x0000001fff027819 */
/* 0x000fe2000001140d */
/*0150*/ IMAD.SHL.U32 R15, R13.reuse, 0x4, RZ ; /* 0x000000040d0f7824 */
/* 0x040fe200078e00ff */
/*0160*/ SHF.L.U64.HI R14, R0.reuse, 0x2, R11 ; /* 0x00000002000e7819 */
/* 0x040fe2000001020b */
/*0170*/ IMAD.SHL.U32 R12, R0, 0x4, RZ ; /* 0x00000004000c7824 */
/* 0x000fe200078e00ff */
/*0180*/ SHF.L.U64.HI R17, R13, 0x2, R2 ; /* 0x000000020d117819 */
/* 0x000fe20000010202 */
/*0190*/ IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; /* 0x00000001ff107424 */
/* 0x000fe200078e00ff */
/*01a0*/ IADD3 R8, P0, R15, c[0x0][0x160], RZ ; /* 0x000058000f087a10 */
/* 0x000fe20007f1e0ff */
/*01b0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x198] ; /* 0x00006600ff067624 */
/* 0x000fe200078e00ff */
/*01c0*/ IADD3 R2, P1, R12, c[0x0][0x160], RZ ; /* 0x000058000c027a10 */
/* 0x000fe20007f3e0ff */
/*01d0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x19c] ; /* 0x00006700ff077624 */
/* 0x000fe200078e00ff */
/*01e0*/ IADD3.X R9, R17, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590011097a10 */
/* 0x000fc400007fe4ff */
/*01f0*/ IADD3.X R3, R14, c[0x0][0x164], RZ, P1, !PT ; /* 0x000059000e037a10 */
/* 0x000fe40000ffe4ff */
/*0200*/ STG.E.U8 [R6.64], R16 ; /* 0x0000001006007986 */
/* 0x0001e8000c101104 */
/*0210*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1900 */
/*0220*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea2000c1e1900 */
/*0230*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0a7624 */
/* 0x000fc400078e00ff */
/*0240*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff047624 */
/* 0x000fe200078e00ff */
/*0250*/ FSETP.GTU.AND P0, PT, R11, R8, PT ; /* 0x000000080b00720b */
/* 0x004fc80003f0c000 */
/*0260*/ SEL R10, R10, c[0x0][0x168], P0 ; /* 0x00005a000a0a7a07 */
/* 0x000fe40000000000 */
/*0270*/ SEL R4, R4, c[0x0][0x16c], P0 ; /* 0x00005b0004047a07 */
/* 0x000fe40000000000 */
/*0280*/ IADD3 R10, P0, R10, R15, RZ ; /* 0x0000000f0a0a7210 */
/* 0x000fca0007f1e0ff */
/*0290*/ IMAD.X R11, R4, 0x1, R17, P0 ; /* 0x00000001040b7824 */
/* 0x000fca00000e0611 */
/*02a0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea2000c1e1900 */
/*02b0*/ IADD3 R6, P1, R12, c[0x0][0x190], RZ ; /* 0x000064000c067a10 */
/* 0x001fc80007f3e0ff */
/*02c0*/ IADD3.X R7, R14, c[0x0][0x194], RZ, P1, !PT ; /* 0x000065000e077a10 */
/* 0x000fe40000ffe4ff */
/*02d0*/ ISETP.NE.AND P0, PT, R10, -0x1, PT ; /* 0xffffffff0a00780c */
/* 0x004fc80003f05270 */
/*02e0*/ SEL R13, R13, R10, !P0 ; /* 0x0000000a0d0d7207 */
/* 0x000fc80004000000 */
/*02f0*/ ISETP.NE.AND P0, PT, R0, R13, PT ; /* 0x0000000d0000720c */
/* 0x000fe20003f05270 */
/*0300*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0001d8000c101904 */
/*0310*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0320*/ IMAD.WIDE R4, R13, R5, c[0x0][0x160] ; /* 0x000058000d047625 */
/* 0x001fe200078e0205 */
/*0330*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000eaa000c1e1900 */
/*0340*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0350*/ SHF.R.S32.HI R6, RZ, 0x1f, R13 ; /* 0x0000001fff067819 */
/* 0x000fe4000001140d */
/*0360*/ FSETP.GTU.AND P0, PT, R2, R5, PT ; /* 0x000000050200720b */
/* 0x004fda0003f0c000 */
/*0370*/ @P0 BRA 0x3f0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0380*/ LEA R2, P0, R13, c[0x0][0x180], 0x2 ; /* 0x000060000d027a11 */
/* 0x000fc800078010ff */
/*0390*/ LEA.HI.X R3, R13, c[0x0][0x184], R6, 0x2, P0 ; /* 0x000061000d037a11 */
/* 0x000fca00000f1406 */
/*03a0*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1900 */
/*03b0*/ ISETP.NE.AND P0, PT, R4, -0x1, PT ; /* 0xffffffff0400780c */
/* 0x004fda0003f05270 */
/*03c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*03d0*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101904 */
/*03e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03f0*/ LEA R2, P0, R13, c[0x0][0x188], 0x2 ; /* 0x000062000d027a11 */
/* 0x000fc800078010ff */
/*0400*/ LEA.HI.X R3, R13, c[0x0][0x18c], R6, 0x2, P0 ; /* 0x000063000d037a11 */
/* 0x000fca00000f1406 */
/*0410*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1900 */
/*0420*/ ISETP.NE.AND P0, PT, R4, -0x1, PT ; /* 0xffffffff0400780c */
/* 0x004fda0003f05270 */
/*0430*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0440*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101904 */
/*0450*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0460*/ BRA 0x460; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <math.h>
#include <time.h>
#include <stdlib.h>
#include <random>
#include <vector>
#include <chrono>
#include <deque>
#include <algorithm>
#include <iterator>
#include <set>
#define BLOCK_SIZE 1024
struct bstree {
int *left_child;
int *right_child;
int *parent;
bool *flag;
};
__global__ void populate_child_parent(float *arr, int *i_left_child, int *i_right_child, int *i_parent, int *o_left_child, int *o_right_child, int *o_parent, bool *flag, const int n) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) {
int y = i_parent[i];
if (i_left_child[i] == -1 && i_right_child[i] == -1 && i != y) {
flag[0] = true;
int x, p;
if (arr[i] <= arr[y]) {
p = i_left_child[y];
x = (p != -1) ? p:y;
o_parent[i] = x;
}
else {
p = i_right_child[y];
x = (p != -1) ? p:y;
o_parent[i] = x;
}
if (i != x) {
if (arr[i] <= arr[x]) {
if (o_left_child[x] == -1) {
o_left_child[x] = i;
}
}
else {
if (o_right_child[x] == -1) {
o_right_child[x] = i;
}
}
}
}
}
}
__global__ void copy_arr(int *in_arr, int *out_arr, const int n) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) {
out_arr[i] = in_arr[i];
}
}
void copy_array(int *arr1, int *arr2, const int n) {
cudaStream_t stream;
cudaStreamCreate(&stream);
copy_arr<<<(n + BLOCK_SIZE - 1)/BLOCK_SIZE, BLOCK_SIZE, 0, stream>>>(arr1, arr2, n);
cudaDeviceSynchronize();
cudaStreamDestroy(stream);
}
void random_vector(float *arr, const int n, const float min_val=0.0, const float max_val=1000.0) {
static std::random_device rd;
static std::mt19937 mte(rd());
std::uniform_real_distribution<float> dist(min_val, max_val);
for (int i = 0; i < n; i++) {
arr[i] = dist(mte);
}
}
bstree construct_binary_tree(float *arr, bstree g, bstree g1, const int n) {
copy_array(g.left_child, g1.left_child, n);
copy_array(g.right_child, g1.right_child, n);
copy_array(g.parent, g1.parent, n);
g1.flag[0] = false;
populate_child_parent<<<(n + BLOCK_SIZE - 1)/BLOCK_SIZE, BLOCK_SIZE>>>(arr, g.left_child, g.right_child, g.parent, g1.left_child, g1.right_child, g1.parent, g1.flag, n);
cudaDeviceSynchronize();
return g1;
}
bstree bs_tree(float *arr, int root_index, bstree g, bstree g1, const int n) {
g.flag[0] = true;
while (g.flag[0]) {
g = construct_binary_tree(arr, g, g1, n);
}
return g;
}
float *traversal(float *arr, int *left_child, int *right_child, int root_index, const int n) {
int *stack = new int[n];
float *out = new float[n];
stack[0] = root_index;
int p = 1;
int i = 0;
std::set<int> visited;
while (p > 0) {
int curr_root = stack[p-1];
if (left_child[curr_root] != -1 && visited.find(left_child[curr_root]) == visited.end()) {
stack[p++] = left_child[curr_root];
}
else {
if (visited.find(curr_root) == visited.end()) {
out[i++] = arr[curr_root];
visited.insert(curr_root);
}
if (right_child[curr_root] != -1 && visited.find(right_child[curr_root]) == visited.end()) {
stack[p++] = right_child[curr_root];
}
else {
p -= 1;
}
}
}
return out;
}
float *inorder_traversal(float *arr, bstree g, bstree g1, const int n) {
int root_index = rand() % static_cast<int>(n);
std::fill(g.parent, g.parent+n, root_index);
auto t1 = std::chrono::high_resolution_clock::now();
g = bs_tree(arr, root_index, g, g1, n);
auto t2 = std::chrono::high_resolution_clock::now();
auto duration = std::chrono::duration_cast<std::chrono::milliseconds>( t2 - t1 ).count();
std::cout << duration << std::endl;
return traversal(arr, g.left_child, g.right_child, root_index, n);
}
bool check_correctness(float *arr, float *pred_arr, const int n) {
std::sort(arr, arr+n);
for (int i = 0; i < n ; i++) {
if (arr[i] != pred_arr[i]) {
return false;
}
}
return true;
}
int main(void) {
int n = 1 << 25;
float *arr, *temp;
cudaMallocManaged(&arr, n*sizeof(float));
random_vector(arr, n, 0, 10000);
temp = new float[n];
std::copy(arr, arr+n, temp);
bstree g, g1;
cudaMallocManaged(&g.left_child, n*sizeof(int));
cudaMallocManaged(&g.right_child, n*sizeof(int));
cudaMallocManaged(&g.parent, n*sizeof(int));
cudaMallocManaged(&g.flag, sizeof(bool));
cudaMallocManaged(&g1.left_child, n*sizeof(int));
cudaMallocManaged(&g1.right_child, n*sizeof(int));
cudaMallocManaged(&g1.parent, n*sizeof(int));
cudaMallocManaged(&g1.flag, sizeof(bool));
std::fill(g.left_child, g.left_child+n, -1);
std::fill(g.right_child, g.right_child+n, -1);
auto t1 = std::chrono::high_resolution_clock::now();
float *pred = inorder_traversal(arr, g, g1, n);
auto t2 = std::chrono::high_resolution_clock::now();
auto duration = std::chrono::duration_cast<std::chrono::milliseconds>( t2 - t1 ).count();
std::cout << duration << std::endl;
t1 = std::chrono::high_resolution_clock::now();
std::cout << check_correctness(temp, pred, n) << std::endl;
t2 = std::chrono::high_resolution_clock::now();
duration = std::chrono::duration_cast<std::chrono::milliseconds>( t2 - t1 ).count();
std::cout << duration << std::endl;
cudaFree(arr);
cudaFree(g.left_child);
cudaFree(g.right_child);
cudaFree(g.parent);
cudaFree(g.flag);
cudaFree(g1.left_child);
cudaFree(g1.right_child);
cudaFree(g1.parent);
cudaFree(g1.flag);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <time.h>
#include <stdlib.h>
#include <random>
#include <vector>
#include <chrono>
#include <deque>
#include <algorithm>
#include <iterator>
#include <set>
#define BLOCK_SIZE 1024
struct bstree {
int *left_child;
int *right_child;
int *parent;
bool *flag;
};
__global__ void populate_child_parent(float *arr, int *i_left_child, int *i_right_child, int *i_parent, int *o_left_child, int *o_right_child, int *o_parent, bool *flag, const int n) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) {
int y = i_parent[i];
if (i_left_child[i] == -1 && i_right_child[i] == -1 && i != y) {
flag[0] = true;
int x, p;
if (arr[i] <= arr[y]) {
p = i_left_child[y];
x = (p != -1) ? p:y;
o_parent[i] = x;
}
else {
p = i_right_child[y];
x = (p != -1) ? p:y;
o_parent[i] = x;
}
if (i != x) {
if (arr[i] <= arr[x]) {
if (o_left_child[x] == -1) {
o_left_child[x] = i;
}
}
else {
if (o_right_child[x] == -1) {
o_right_child[x] = i;
}
}
}
}
}
}
__global__ void copy_arr(int *in_arr, int *out_arr, const int n) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) {
out_arr[i] = in_arr[i];
}
}
void copy_array(int *arr1, int *arr2, const int n) {
hipStream_t stream;
hipStreamCreate(&stream);
copy_arr<<<(n + BLOCK_SIZE - 1)/BLOCK_SIZE, BLOCK_SIZE, 0, stream>>>(arr1, arr2, n);
hipDeviceSynchronize();
hipStreamDestroy(stream);
}
void random_vector(float *arr, const int n, const float min_val=0.0, const float max_val=1000.0) {
static std::random_device rd;
static std::mt19937 mte(rd());
std::uniform_real_distribution<float> dist(min_val, max_val);
for (int i = 0; i < n; i++) {
arr[i] = dist(mte);
}
}
bstree construct_binary_tree(float *arr, bstree g, bstree g1, const int n) {
copy_array(g.left_child, g1.left_child, n);
copy_array(g.right_child, g1.right_child, n);
copy_array(g.parent, g1.parent, n);
g1.flag[0] = false;
populate_child_parent<<<(n + BLOCK_SIZE - 1)/BLOCK_SIZE, BLOCK_SIZE>>>(arr, g.left_child, g.right_child, g.parent, g1.left_child, g1.right_child, g1.parent, g1.flag, n);
hipDeviceSynchronize();
return g1;
}
bstree bs_tree(float *arr, int root_index, bstree g, bstree g1, const int n) {
g.flag[0] = true;
while (g.flag[0]) {
g = construct_binary_tree(arr, g, g1, n);
}
return g;
}
float *traversal(float *arr, int *left_child, int *right_child, int root_index, const int n) {
int *stack = new int[n];
float *out = new float[n];
stack[0] = root_index;
int p = 1;
int i = 0;
std::set<int> visited;
while (p > 0) {
int curr_root = stack[p-1];
if (left_child[curr_root] != -1 && visited.find(left_child[curr_root]) == visited.end()) {
stack[p++] = left_child[curr_root];
}
else {
if (visited.find(curr_root) == visited.end()) {
out[i++] = arr[curr_root];
visited.insert(curr_root);
}
if (right_child[curr_root] != -1 && visited.find(right_child[curr_root]) == visited.end()) {
stack[p++] = right_child[curr_root];
}
else {
p -= 1;
}
}
}
return out;
}
float *inorder_traversal(float *arr, bstree g, bstree g1, const int n) {
int root_index = rand() % static_cast<int>(n);
std::fill(g.parent, g.parent+n, root_index);
auto t1 = std::chrono::high_resolution_clock::now();
g = bs_tree(arr, root_index, g, g1, n);
auto t2 = std::chrono::high_resolution_clock::now();
auto duration = std::chrono::duration_cast<std::chrono::milliseconds>( t2 - t1 ).count();
std::cout << duration << std::endl;
return traversal(arr, g.left_child, g.right_child, root_index, n);
}
bool check_correctness(float *arr, float *pred_arr, const int n) {
std::sort(arr, arr+n);
for (int i = 0; i < n ; i++) {
if (arr[i] != pred_arr[i]) {
return false;
}
}
return true;
}
int main(void) {
int n = 1 << 25;
float *arr, *temp;
hipMallocManaged(&arr, n*sizeof(float));
random_vector(arr, n, 0, 10000);
temp = new float[n];
std::copy(arr, arr+n, temp);
bstree g, g1;
hipMallocManaged(&g.left_child, n*sizeof(int));
hipMallocManaged(&g.right_child, n*sizeof(int));
hipMallocManaged(&g.parent, n*sizeof(int));
hipMallocManaged(&g.flag, sizeof(bool));
hipMallocManaged(&g1.left_child, n*sizeof(int));
hipMallocManaged(&g1.right_child, n*sizeof(int));
hipMallocManaged(&g1.parent, n*sizeof(int));
hipMallocManaged(&g1.flag, sizeof(bool));
std::fill(g.left_child, g.left_child+n, -1);
std::fill(g.right_child, g.right_child+n, -1);
auto t1 = std::chrono::high_resolution_clock::now();
float *pred = inorder_traversal(arr, g, g1, n);
auto t2 = std::chrono::high_resolution_clock::now();
auto duration = std::chrono::duration_cast<std::chrono::milliseconds>( t2 - t1 ).count();
std::cout << duration << std::endl;
t1 = std::chrono::high_resolution_clock::now();
std::cout << check_correctness(temp, pred, n) << std::endl;
t2 = std::chrono::high_resolution_clock::now();
duration = std::chrono::duration_cast<std::chrono::milliseconds>( t2 - t1 ).count();
std::cout << duration << std::endl;
hipFree(arr);
hipFree(g.left_child);
hipFree(g.right_child);
hipFree(g.parent);
hipFree(g.flag);
hipFree(g1.left_child);
hipFree(g1.right_child);
hipFree(g1.parent);
hipFree(g1.flag);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <time.h>
#include <stdlib.h>
#include <random>
#include <vector>
#include <chrono>
#include <deque>
#include <algorithm>
#include <iterator>
#include <set>
#define BLOCK_SIZE 1024
struct bstree {
int *left_child;
int *right_child;
int *parent;
bool *flag;
};
__global__ void populate_child_parent(float *arr, int *i_left_child, int *i_right_child, int *i_parent, int *o_left_child, int *o_right_child, int *o_parent, bool *flag, const int n) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) {
int y = i_parent[i];
if (i_left_child[i] == -1 && i_right_child[i] == -1 && i != y) {
flag[0] = true;
int x, p;
if (arr[i] <= arr[y]) {
p = i_left_child[y];
x = (p != -1) ? p:y;
o_parent[i] = x;
}
else {
p = i_right_child[y];
x = (p != -1) ? p:y;
o_parent[i] = x;
}
if (i != x) {
if (arr[i] <= arr[x]) {
if (o_left_child[x] == -1) {
o_left_child[x] = i;
}
}
else {
if (o_right_child[x] == -1) {
o_right_child[x] = i;
}
}
}
}
}
}
__global__ void copy_arr(int *in_arr, int *out_arr, const int n) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) {
out_arr[i] = in_arr[i];
}
}
void copy_array(int *arr1, int *arr2, const int n) {
hipStream_t stream;
hipStreamCreate(&stream);
copy_arr<<<(n + BLOCK_SIZE - 1)/BLOCK_SIZE, BLOCK_SIZE, 0, stream>>>(arr1, arr2, n);
hipDeviceSynchronize();
hipStreamDestroy(stream);
}
void random_vector(float *arr, const int n, const float min_val=0.0, const float max_val=1000.0) {
static std::random_device rd;
static std::mt19937 mte(rd());
std::uniform_real_distribution<float> dist(min_val, max_val);
for (int i = 0; i < n; i++) {
arr[i] = dist(mte);
}
}
bstree construct_binary_tree(float *arr, bstree g, bstree g1, const int n) {
copy_array(g.left_child, g1.left_child, n);
copy_array(g.right_child, g1.right_child, n);
copy_array(g.parent, g1.parent, n);
g1.flag[0] = false;
populate_child_parent<<<(n + BLOCK_SIZE - 1)/BLOCK_SIZE, BLOCK_SIZE>>>(arr, g.left_child, g.right_child, g.parent, g1.left_child, g1.right_child, g1.parent, g1.flag, n);
hipDeviceSynchronize();
return g1;
}
bstree bs_tree(float *arr, int root_index, bstree g, bstree g1, const int n) {
g.flag[0] = true;
while (g.flag[0]) {
g = construct_binary_tree(arr, g, g1, n);
}
return g;
}
float *traversal(float *arr, int *left_child, int *right_child, int root_index, const int n) {
int *stack = new int[n];
float *out = new float[n];
stack[0] = root_index;
int p = 1;
int i = 0;
std::set<int> visited;
while (p > 0) {
int curr_root = stack[p-1];
if (left_child[curr_root] != -1 && visited.find(left_child[curr_root]) == visited.end()) {
stack[p++] = left_child[curr_root];
}
else {
if (visited.find(curr_root) == visited.end()) {
out[i++] = arr[curr_root];
visited.insert(curr_root);
}
if (right_child[curr_root] != -1 && visited.find(right_child[curr_root]) == visited.end()) {
stack[p++] = right_child[curr_root];
}
else {
p -= 1;
}
}
}
return out;
}
float *inorder_traversal(float *arr, bstree g, bstree g1, const int n) {
int root_index = rand() % static_cast<int>(n);
std::fill(g.parent, g.parent+n, root_index);
auto t1 = std::chrono::high_resolution_clock::now();
g = bs_tree(arr, root_index, g, g1, n);
auto t2 = std::chrono::high_resolution_clock::now();
auto duration = std::chrono::duration_cast<std::chrono::milliseconds>( t2 - t1 ).count();
std::cout << duration << std::endl;
return traversal(arr, g.left_child, g.right_child, root_index, n);
}
bool check_correctness(float *arr, float *pred_arr, const int n) {
std::sort(arr, arr+n);
for (int i = 0; i < n ; i++) {
if (arr[i] != pred_arr[i]) {
return false;
}
}
return true;
}
int main(void) {
int n = 1 << 25;
float *arr, *temp;
hipMallocManaged(&arr, n*sizeof(float));
random_vector(arr, n, 0, 10000);
temp = new float[n];
std::copy(arr, arr+n, temp);
bstree g, g1;
hipMallocManaged(&g.left_child, n*sizeof(int));
hipMallocManaged(&g.right_child, n*sizeof(int));
hipMallocManaged(&g.parent, n*sizeof(int));
hipMallocManaged(&g.flag, sizeof(bool));
hipMallocManaged(&g1.left_child, n*sizeof(int));
hipMallocManaged(&g1.right_child, n*sizeof(int));
hipMallocManaged(&g1.parent, n*sizeof(int));
hipMallocManaged(&g1.flag, sizeof(bool));
std::fill(g.left_child, g.left_child+n, -1);
std::fill(g.right_child, g.right_child+n, -1);
auto t1 = std::chrono::high_resolution_clock::now();
float *pred = inorder_traversal(arr, g, g1, n);
auto t2 = std::chrono::high_resolution_clock::now();
auto duration = std::chrono::duration_cast<std::chrono::milliseconds>( t2 - t1 ).count();
std::cout << duration << std::endl;
t1 = std::chrono::high_resolution_clock::now();
std::cout << check_correctness(temp, pred, n) << std::endl;
t2 = std::chrono::high_resolution_clock::now();
duration = std::chrono::duration_cast<std::chrono::milliseconds>( t2 - t1 ).count();
std::cout << duration << std::endl;
hipFree(arr);
hipFree(g.left_child);
hipFree(g.right_child);
hipFree(g.parent);
hipFree(g.flag);
hipFree(g1.left_child);
hipFree(g1.right_child);
hipFree(g1.parent);
hipFree(g1.flag);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21populate_child_parentPfPiS0_S0_S0_S0_S0_Pbi
.globl _Z21populate_child_parentPfPiS0_S0_S0_S0_S0_Pbi
.p2align 8
.type _Z21populate_child_parentPfPiS0_S0_S0_S0_S0_Pbi,@function
_Z21populate_child_parentPfPiS0_S0_S0_S0_S0_Pbi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x54
s_load_b32 s3, s[0:1], 0x40
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_14
s_load_b64 s[8:9], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s8, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v4, vcc_lo
global_load_b32 v0, v[5:6], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, -1, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_14
s_load_b128 s[4:7], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v0, v[5:6], off
global_load_b32 v4, v[3:4], off
s_waitcnt vmcnt(1)
v_cmp_eq_u32_e32 vcc_lo, -1, v0
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e64 s2, v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_14
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[6:7], s[0:1], 0x38
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[8:9], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, vcc_lo, s2, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
v_add_co_u32 v10, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v11, vcc_lo, s3, v7, vcc_lo
s_clause 0x1
global_load_b32 v0, v[8:9], off
global_load_b32 v3, v[10:11], off
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, 1
global_store_b8 v8, v9, s[6:7]
s_waitcnt vmcnt(0)
v_cmp_le_f32_e32 vcc_lo, v0, v3
s_and_saveexec_b32 s6, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s6, exec_lo, s6
s_cbranch_execz .LBB0_5
v_add_co_u32 v5, vcc_lo, s8, v6
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v7, vcc_lo
global_load_b32 v3, v[5:6], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, -1, v3
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
.LBB0_5:
s_and_not1_saveexec_b32 s6, s6
s_cbranch_execz .LBB0_7
v_lshlrev_b64 v[5:6], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b32 v3, v[5:6], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, -1, v3
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s6
s_load_b64 s[4:5], s[0:1], 0x30
v_lshlrev_b64 v[4:5], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, v1, v3
global_store_b32 v[4:5], v3, off
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_14
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[3:4]
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_mov_b32 s2, 0
s_mov_b32 s3, exec_lo
global_load_b32 v2, v[5:6], off
s_waitcnt vmcnt(0)
v_cmpx_le_f32_e32 v0, v2
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_10
s_load_b64 s[4:5], s[0:1], 0x20
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
global_load_b32 v0, v[5:6], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, -1, v0
s_and_b32 s2, vcc_lo, exec_lo
.LBB0_10:
s_and_not1_saveexec_b32 s3, s3
s_cbranch_execz .LBB0_12
s_load_b64 s[0:1], s[0:1], 0x28
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v3, vcc_lo
s_and_not1_b32 s0, s2, exec_lo
global_load_b32 v0, v[5:6], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, -1, v0
s_and_b32 s1, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s2, s0, s1
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_14
global_store_b32 v[5:6], v1, off
.LBB0_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21populate_child_parentPfPiS0_S0_S0_S0_S0_Pbi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 328
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21populate_child_parentPfPiS0_S0_S0_S0_S0_Pbi, .Lfunc_end0-_Z21populate_child_parentPfPiS0_S0_S0_S0_S0_Pbi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8copy_arrPiS_i
.globl _Z8copy_arrPiS_i
.p2align 8
.type _Z8copy_arrPiS_i,@function
_Z8copy_arrPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8copy_arrPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z8copy_arrPiS_i, .Lfunc_end1-_Z8copy_arrPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .offset: 64
.size: 4
.value_kind: by_value
- .offset: 72
.size: 4
.value_kind: hidden_block_count_x
- .offset: 76
.size: 4
.value_kind: hidden_block_count_y
- .offset: 80
.size: 4
.value_kind: hidden_block_count_z
- .offset: 84
.size: 2
.value_kind: hidden_group_size_x
- .offset: 86
.size: 2
.value_kind: hidden_group_size_y
- .offset: 88
.size: 2
.value_kind: hidden_group_size_z
- .offset: 90
.size: 2
.value_kind: hidden_remainder_x
- .offset: 92
.size: 2
.value_kind: hidden_remainder_y
- .offset: 94
.size: 2
.value_kind: hidden_remainder_z
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 136
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 328
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21populate_child_parentPfPiS0_S0_S0_S0_S0_Pbi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21populate_child_parentPfPiS0_S0_S0_S0_S0_Pbi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8copy_arrPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8copy_arrPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8copy_arrPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0205 */
/*00b0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z21populate_child_parentPfPiS0_S0_S0_S0_S0_Pbi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x1a0], PT ; /* 0x0000680000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R6, R0, R5, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ SHF.R.S32.HI R11, RZ, 0x1f, R0 ; /* 0x0000001fff0b7819 */
/* 0x000fe20000011400 */
/*00b0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fca00078e0205 */
/*00c0*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000ee2000c1e1900 */
/*00d0*/ ISETP.NE.AND P0, PT, R6, -0x1, PT ; /* 0xffffffff0600780c */
/* 0x004fda0003f05270 */
/*00e0*/ @!P0 LEA R8, P1, R0, c[0x0][0x170], 0x2 ; /* 0x00005c0000088a11 */
/* 0x000fc800078210ff */
/*00f0*/ @!P0 LEA.HI.X R9, R0, c[0x0][0x174], R11, 0x2, P1 ; /* 0x00005d0000098a11 */
/* 0x000fca00008f140b */
/*0100*/ @!P0 LDG.E R8, [R8.64] ; /* 0x0000000408088981 */
/* 0x000ea4000c1e1900 */
/*0110*/ ISETP.EQ.AND P0, PT, R8, -0x1, !P0 ; /* 0xffffffff0800780c */
/* 0x004fc80004702270 */
/*0120*/ ISETP.EQ.OR P0, PT, R0, R13, !P0 ; /* 0x0000000d0000720c */
/* 0x008fda0004702670 */
/*0130*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0140*/ SHF.R.S32.HI R2, RZ, 0x1f, R13 ; /* 0x0000001fff027819 */
/* 0x000fe2000001140d */
/*0150*/ IMAD.SHL.U32 R15, R13.reuse, 0x4, RZ ; /* 0x000000040d0f7824 */
/* 0x040fe200078e00ff */
/*0160*/ SHF.L.U64.HI R14, R0.reuse, 0x2, R11 ; /* 0x00000002000e7819 */
/* 0x040fe2000001020b */
/*0170*/ IMAD.SHL.U32 R12, R0, 0x4, RZ ; /* 0x00000004000c7824 */
/* 0x000fe200078e00ff */
/*0180*/ SHF.L.U64.HI R17, R13, 0x2, R2 ; /* 0x000000020d117819 */
/* 0x000fe20000010202 */
/*0190*/ IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; /* 0x00000001ff107424 */
/* 0x000fe200078e00ff */
/*01a0*/ IADD3 R8, P0, R15, c[0x0][0x160], RZ ; /* 0x000058000f087a10 */
/* 0x000fe20007f1e0ff */
/*01b0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x198] ; /* 0x00006600ff067624 */
/* 0x000fe200078e00ff */
/*01c0*/ IADD3 R2, P1, R12, c[0x0][0x160], RZ ; /* 0x000058000c027a10 */
/* 0x000fe20007f3e0ff */
/*01d0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x19c] ; /* 0x00006700ff077624 */
/* 0x000fe200078e00ff */
/*01e0*/ IADD3.X R9, R17, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590011097a10 */
/* 0x000fc400007fe4ff */
/*01f0*/ IADD3.X R3, R14, c[0x0][0x164], RZ, P1, !PT ; /* 0x000059000e037a10 */
/* 0x000fe40000ffe4ff */
/*0200*/ STG.E.U8 [R6.64], R16 ; /* 0x0000001006007986 */
/* 0x0001e8000c101104 */
/*0210*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1900 */
/*0220*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea2000c1e1900 */
/*0230*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0a7624 */
/* 0x000fc400078e00ff */
/*0240*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff047624 */
/* 0x000fe200078e00ff */
/*0250*/ FSETP.GTU.AND P0, PT, R11, R8, PT ; /* 0x000000080b00720b */
/* 0x004fc80003f0c000 */
/*0260*/ SEL R10, R10, c[0x0][0x168], P0 ; /* 0x00005a000a0a7a07 */
/* 0x000fe40000000000 */
/*0270*/ SEL R4, R4, c[0x0][0x16c], P0 ; /* 0x00005b0004047a07 */
/* 0x000fe40000000000 */
/*0280*/ IADD3 R10, P0, R10, R15, RZ ; /* 0x0000000f0a0a7210 */
/* 0x000fca0007f1e0ff */
/*0290*/ IMAD.X R11, R4, 0x1, R17, P0 ; /* 0x00000001040b7824 */
/* 0x000fca00000e0611 */
/*02a0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea2000c1e1900 */
/*02b0*/ IADD3 R6, P1, R12, c[0x0][0x190], RZ ; /* 0x000064000c067a10 */
/* 0x001fc80007f3e0ff */
/*02c0*/ IADD3.X R7, R14, c[0x0][0x194], RZ, P1, !PT ; /* 0x000065000e077a10 */
/* 0x000fe40000ffe4ff */
/*02d0*/ ISETP.NE.AND P0, PT, R10, -0x1, PT ; /* 0xffffffff0a00780c */
/* 0x004fc80003f05270 */
/*02e0*/ SEL R13, R13, R10, !P0 ; /* 0x0000000a0d0d7207 */
/* 0x000fc80004000000 */
/*02f0*/ ISETP.NE.AND P0, PT, R0, R13, PT ; /* 0x0000000d0000720c */
/* 0x000fe20003f05270 */
/*0300*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0001d8000c101904 */
/*0310*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0320*/ IMAD.WIDE R4, R13, R5, c[0x0][0x160] ; /* 0x000058000d047625 */
/* 0x001fe200078e0205 */
/*0330*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000eaa000c1e1900 */
/*0340*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0350*/ SHF.R.S32.HI R6, RZ, 0x1f, R13 ; /* 0x0000001fff067819 */
/* 0x000fe4000001140d */
/*0360*/ FSETP.GTU.AND P0, PT, R2, R5, PT ; /* 0x000000050200720b */
/* 0x004fda0003f0c000 */
/*0370*/ @P0 BRA 0x3f0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0380*/ LEA R2, P0, R13, c[0x0][0x180], 0x2 ; /* 0x000060000d027a11 */
/* 0x000fc800078010ff */
/*0390*/ LEA.HI.X R3, R13, c[0x0][0x184], R6, 0x2, P0 ; /* 0x000061000d037a11 */
/* 0x000fca00000f1406 */
/*03a0*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1900 */
/*03b0*/ ISETP.NE.AND P0, PT, R4, -0x1, PT ; /* 0xffffffff0400780c */
/* 0x004fda0003f05270 */
/*03c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*03d0*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101904 */
/*03e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03f0*/ LEA R2, P0, R13, c[0x0][0x188], 0x2 ; /* 0x000062000d027a11 */
/* 0x000fc800078010ff */
/*0400*/ LEA.HI.X R3, R13, c[0x0][0x18c], R6, 0x2, P0 ; /* 0x000063000d037a11 */
/* 0x000fca00000f1406 */
/*0410*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1900 */
/*0420*/ ISETP.NE.AND P0, PT, R4, -0x1, PT ; /* 0xffffffff0400780c */
/* 0x004fda0003f05270 */
/*0430*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0440*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101904 */
/*0450*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0460*/ BRA 0x460; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21populate_child_parentPfPiS0_S0_S0_S0_S0_Pbi
.globl _Z21populate_child_parentPfPiS0_S0_S0_S0_S0_Pbi
.p2align 8
.type _Z21populate_child_parentPfPiS0_S0_S0_S0_S0_Pbi,@function
_Z21populate_child_parentPfPiS0_S0_S0_S0_S0_Pbi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x54
s_load_b32 s3, s[0:1], 0x40
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_14
s_load_b64 s[8:9], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s8, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v4, vcc_lo
global_load_b32 v0, v[5:6], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, -1, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_14
s_load_b128 s[4:7], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v0, v[5:6], off
global_load_b32 v4, v[3:4], off
s_waitcnt vmcnt(1)
v_cmp_eq_u32_e32 vcc_lo, -1, v0
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e64 s2, v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_14
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[6:7], s[0:1], 0x38
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[8:9], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, vcc_lo, s2, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
v_add_co_u32 v10, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v11, vcc_lo, s3, v7, vcc_lo
s_clause 0x1
global_load_b32 v0, v[8:9], off
global_load_b32 v3, v[10:11], off
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, 1
global_store_b8 v8, v9, s[6:7]
s_waitcnt vmcnt(0)
v_cmp_le_f32_e32 vcc_lo, v0, v3
s_and_saveexec_b32 s6, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s6, exec_lo, s6
s_cbranch_execz .LBB0_5
v_add_co_u32 v5, vcc_lo, s8, v6
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v7, vcc_lo
global_load_b32 v3, v[5:6], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, -1, v3
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
.LBB0_5:
s_and_not1_saveexec_b32 s6, s6
s_cbranch_execz .LBB0_7
v_lshlrev_b64 v[5:6], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b32 v3, v[5:6], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, -1, v3
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s6
s_load_b64 s[4:5], s[0:1], 0x30
v_lshlrev_b64 v[4:5], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, v1, v3
global_store_b32 v[4:5], v3, off
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_14
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[3:4]
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_mov_b32 s2, 0
s_mov_b32 s3, exec_lo
global_load_b32 v2, v[5:6], off
s_waitcnt vmcnt(0)
v_cmpx_le_f32_e32 v0, v2
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_10
s_load_b64 s[4:5], s[0:1], 0x20
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
global_load_b32 v0, v[5:6], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, -1, v0
s_and_b32 s2, vcc_lo, exec_lo
.LBB0_10:
s_and_not1_saveexec_b32 s3, s3
s_cbranch_execz .LBB0_12
s_load_b64 s[0:1], s[0:1], 0x28
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v3, vcc_lo
s_and_not1_b32 s0, s2, exec_lo
global_load_b32 v0, v[5:6], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, -1, v0
s_and_b32 s1, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s2, s0, s1
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_14
global_store_b32 v[5:6], v1, off
.LBB0_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21populate_child_parentPfPiS0_S0_S0_S0_S0_Pbi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 328
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21populate_child_parentPfPiS0_S0_S0_S0_S0_Pbi, .Lfunc_end0-_Z21populate_child_parentPfPiS0_S0_S0_S0_S0_Pbi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8copy_arrPiS_i
.globl _Z8copy_arrPiS_i
.p2align 8
.type _Z8copy_arrPiS_i,@function
_Z8copy_arrPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8copy_arrPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z8copy_arrPiS_i, .Lfunc_end1-_Z8copy_arrPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .offset: 64
.size: 4
.value_kind: by_value
- .offset: 72
.size: 4
.value_kind: hidden_block_count_x
- .offset: 76
.size: 4
.value_kind: hidden_block_count_y
- .offset: 80
.size: 4
.value_kind: hidden_block_count_z
- .offset: 84
.size: 2
.value_kind: hidden_group_size_x
- .offset: 86
.size: 2
.value_kind: hidden_group_size_y
- .offset: 88
.size: 2
.value_kind: hidden_group_size_z
- .offset: 90
.size: 2
.value_kind: hidden_remainder_x
- .offset: 92
.size: 2
.value_kind: hidden_remainder_y
- .offset: 94
.size: 2
.value_kind: hidden_remainder_z
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 136
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 328
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21populate_child_parentPfPiS0_S0_S0_S0_S0_Pbi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21populate_child_parentPfPiS0_S0_S0_S0_S0_Pbi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8copy_arrPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8copy_arrPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <cuda_runtime.h>
#include <time.h>
#define C10_WARP_SIZE 32
#define N 32*1024*1024
constexpr int kCUDABlockReduceNumThreads = 512;
// Algorithmic limitation: BlockReduce does two WarpReduce calls, each
// of which reduces C10_WARP_SIZE elements. So, at most
// C10_WARP_SIZE**2 elements can be reduced at a time.
// NOTE: This is >= the max block size on current hardware anyway (1024).
constexpr int kCUDABlockReduceMaxThreads = C10_WARP_SIZE * C10_WARP_SIZE;
// Sums `val` accross all threads in a warp.
//
// Assumptions:
// - The size of each block should be a multiple of `C10_WARP_SIZE`
// 实际上 WARP_SHFL_DOWN 的实现如下：
// template <typename T>
// __device__ __forceinline__ T WARP_SHFL_DOWN(T value, unsigned int delta, int width = warpSize, unsigned int mask = 0xffffffff)
// {
// #if !defined(USE_ROCM)
// return __shfl_down_sync(mask, value, delta, width);
// #else
// return __shfl_down(value, delta, width);
// #endif
// }
// 可以看到这里使用了warp原语__shfl_down_sync来对一个warp内的val进行规约求和。
// __shfl_down_sync的相关介绍：https://docs.nvidia.com/cuda/cuda-c-programming-guide/#warp-shuffle-functions
// && https://developer.nvidia.com/zh-cn/blog/using-cuda-warp-level-primitives/
// 示意图如：https://developer.nvidia.com/blog/wp-content/uploads/2018/01/reduce_shfl_down-625x275.png 所示
// 函数原型：T __shfl_down_sync(unsigned mask, T var, unsigned int delta, int width=warpSize);
// mask表示一个warp中thread的激活表;
// var表示规约求和的变量；
// delta表示当前线程与另一个线程求和时跨越的线程偏移;
// width表示求和的宽度（个数）
// 根据循环体for (int offset = (C10_WARP_SIZE >> 1); offset > 0; offset >>= 1)，
// 第一次循环时 delta 是 16，即 Lane0（Lane0表示一个warp中的lane_index）与 Lane16 求和，Lane1 与 Lane17 求和，***，
// 依此类推，一个 warp 内的 32 个 thread 的 val 规约成 16 个val。第二次循环时 delta 是 8 ，即 Lane0 与 Lane4 求和，Lane1 与 Lane5，
// 与上图的第一次行为相同。依次类推，最终不同 warp 中的 val 规约求和到了 Lane0 所持有的 val 中。
// 至此执行完 val = WarpReduceSum(val); 后，所有 warp 的和都规约到了每个 warp 中的 lane0 的线程中了，即 lid == 0 的线程，
// wid 则代表了不同的 lane（或不同的 warp ）。
template <typename T>
__inline__ __device__ T WarpReduceSum(T val) {
#pragma unroll
for (int offset = (C10_WARP_SIZE >> 1); offset > 0; offset >>= 1) {
val += WARP_SHFL_DOWN(val, offset);
// 或者：val += __shfl_down_sync(0xffffffff， val, offset, warpSize);//warpSize为内置数据，值为32
}
return val;
}
struct Block1D {
static __forceinline__ __device__ int Tid() { return threadIdx.x; }
static __forceinline__ __device__ int Warps() {
return blockDim.x / C10_WARP_SIZE;
}
};
struct Block2D {
static __forceinline__ __device__ int Tid() {
return threadIdx.x + threadIdx.y * blockDim.x;
}
static __forceinline__ __device__ int Warps() {
return blockDim.x * blockDim.y / C10_WARP_SIZE;
}
};
// Sums `val` across all threads in a block.
//
// Warning: the return value is only valid for thread 0.
// Assumptions:
// - The size of each block should be a multiple of `C10_WARP_SIZE`
// - `shared` should be a pointer to shared memory with size of, at least,
// `sizeof(T) * number_of_warps`
// lane的中文翻译为车道（路宽），lane表示一个warp中的thread个数，
// 在 Block1D中在一个 lane 中的索引 lane_index 为 [0, warpSize - 1] 。
// 在一个 block 中会有多个 lane，lane_id = threadIdx.x / C10_WARP_SIZE ，最多有 1024 / C10_WARP_SIZE = 32 个lane。
template <typename T, typename B = Block1D>
__inline__ __device__ T BlockReduceSum(T val, T* shared) {
const int tid = B::Tid(); // 获取 block 中的线程 id
const int lid = tid % C10_WARP_SIZE; // lane id，表示当前 thread 在当前 lane 中的索引
const int wid = tid / C10_WARP_SIZE; // wid表示当前 thread 在第多少个 lane
// 每个 thread 对应寄存器中都有一个 val 值，WarpReduceSum 函数便是对 warp 中的所有 thread 所持有的 val 进行求和
val = WarpReduceSum(val);
// 下面要将各个 warp 规约求和的值进行一次规约，需要通过 shared-memory 将数据保存到同一个 warp 中的不同线程中，
// 在数据保存前需要__syncthreads(); 同步一下
__syncthreads(); // prevent races when BlockReduces are called in a row.
if (lid == 0) {
shared[wid] = val;
}
__syncthreads();
// 默认申请 32 大小的 shared-memory（32其实也是一个 Block 最大的 lane 个数），
// 当 Block 内线程束较少时，无法刷新 shared-memory 上全部的 32 个值，需要对未使用到的内存进行初始化；
val = (tid < B::Warps()) ? shared[lid] : T(0);
// 再次使用 WarpReduceSum 对这 32 个 thread 的值进行求和，最终一个 Block 内的值便全部规约求和到了 threadIdx.x == 0 的线程所持有的 val 值了。
// 这也就是说对于调用 BlockReduceSum 函数的代码来说，在使用规约求和后的值时需要通过 threadIdx.x == 0 的线程获取。
if (wid == 0) {
val = WarpReduceSum(val);
}
return val;
}
template <typename T, class ReduceOp>
__inline__ __device__ T WarpReduce(T val, const ReduceOp& op) {
#pragma unroll
for (int offset = (C10_WARP_SIZE >> 1); offset > 0; offset >>= 1) {
val = op.combine(val, op.warp_shfl_down(val, offset));
}
return val;
}
template <typename T, class ReduceOp, typename B = Block1D>
__inline__ __device__ T
BlockReduce(T val, const ReduceOp& op, const T& identity_element, T* shared) {
const int tid = B::Tid();
const int lid = tid % C10_WARP_SIZE;
const int wid = tid / C10_WARP_SIZE;
val = WarpReduce(val, op);
__syncthreads(); // prevent races when BlockReduces are called in a row.
if (lid == 0) {
shared[wid] = val;
}
__syncthreads();
val = (tid < B::Warps()) ? shared[lid] : identity_element;
if (wid == 0) {
val = WarpReduce(val, op);
}
return val;
}
int main(){
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cuda_runtime.h>
#include <time.h>
#define C10_WARP_SIZE 32
#define N 32*1024*1024
constexpr int kCUDABlockReduceNumThreads = 512;
// Algorithmic limitation: BlockReduce does two WarpReduce calls, each
// of which reduces C10_WARP_SIZE elements. So, at most
// C10_WARP_SIZE**2 elements can be reduced at a time.
// NOTE: This is >= the max block size on current hardware anyway (1024).
constexpr int kCUDABlockReduceMaxThreads = C10_WARP_SIZE * C10_WARP_SIZE;
// Sums `val` accross all threads in a warp.
//
// Assumptions:
// - The size of each block should be a multiple of `C10_WARP_SIZE`
// 实际上 WARP_SHFL_DOWN 的实现如下：
// template <typename T>
// __device__ __forceinline__ T WARP_SHFL_DOWN(T value, unsigned int delta, int width = warpSize, unsigned int mask = 0xffffffff)
// {
// #if !defined(USE_ROCM)
// return __shfl_down_sync(mask, value, delta, width);
// #else
// return __shfl_down(value, delta, width);
// #endif
// }
// 可以看到这里使用了warp原语__shfl_down_sync来对一个warp内的val进行规约求和。
// __shfl_down_sync的相关介绍：https://docs.nvidia.com/cuda/cuda-c-programming-guide/#warp-shuffle-functions
// && https://developer.nvidia.com/zh-cn/blog/using-cuda-warp-level-primitives/
// 示意图如：https://developer.nvidia.com/blog/wp-content/uploads/2018/01/reduce_shfl_down-625x275.png 所示
// 函数原型：T __shfl_down_sync(unsigned mask, T var, unsigned int delta, int width=warpSize);
// mask表示一个warp中thread的激活表;
// var表示规约求和的变量；
// delta表示当前线程与另一个线程求和时跨越的线程偏移;
// width表示求和的宽度（个数）
// 根据循环体for (int offset = (C10_WARP_SIZE >> 1); offset > 0; offset >>= 1)，
// 第一次循环时 delta 是 16，即 Lane0（Lane0表示一个warp中的lane_index）与 Lane16 求和，Lane1 与 Lane17 求和，***，
// 依此类推，一个 warp 内的 32 个 thread 的 val 规约成 16 个val。第二次循环时 delta 是 8 ，即 Lane0 与 Lane4 求和，Lane1 与 Lane5，
// 与上图的第一次行为相同。依次类推，最终不同 warp 中的 val 规约求和到了 Lane0 所持有的 val 中。
// 至此执行完 val = WarpReduceSum(val); 后，所有 warp 的和都规约到了每个 warp 中的 lane0 的线程中了，即 lid == 0 的线程，
// wid 则代表了不同的 lane（或不同的 warp ）。
template <typename T>
__inline__ __device__ T WarpReduceSum(T val) {
#pragma unroll
for (int offset = (C10_WARP_SIZE >> 1); offset > 0; offset >>= 1) {
val += WARP_SHFL_DOWN(val, offset);
// 或者：val += __shfl_down_sync(0xffffffff， val, offset, warpSize);//warpSize为内置数据，值为32
}
return val;
}
struct Block1D {
static __forceinline__ __device__ int Tid() { return threadIdx.x; }
static __forceinline__ __device__ int Warps() {
return blockDim.x / C10_WARP_SIZE;
}
};
struct Block2D {
static __forceinline__ __device__ int Tid() {
return threadIdx.x + threadIdx.y * blockDim.x;
}
static __forceinline__ __device__ int Warps() {
return blockDim.x * blockDim.y / C10_WARP_SIZE;
}
};
// Sums `val` across all threads in a block.
//
// Warning: the return value is only valid for thread 0.
// Assumptions:
// - The size of each block should be a multiple of `C10_WARP_SIZE`
// - `shared` should be a pointer to shared memory with size of, at least,
// `sizeof(T) * number_of_warps`
// lane的中文翻译为车道（路宽），lane表示一个warp中的thread个数，
// 在 Block1D中在一个 lane 中的索引 lane_index 为 [0, warpSize - 1] 。
// 在一个 block 中会有多个 lane，lane_id = threadIdx.x / C10_WARP_SIZE ，最多有 1024 / C10_WARP_SIZE = 32 个lane。
template <typename T, typename B = Block1D>
__inline__ __device__ T BlockReduceSum(T val, T* shared) {
const int tid = B::Tid(); // 获取 block 中的线程 id
const int lid = tid % C10_WARP_SIZE; // lane id，表示当前 thread 在当前 lane 中的索引
const int wid = tid / C10_WARP_SIZE; // wid表示当前 thread 在第多少个 lane
// 每个 thread 对应寄存器中都有一个 val 值，WarpReduceSum 函数便是对 warp 中的所有 thread 所持有的 val 进行求和
val = WarpReduceSum(val);
// 下面要将各个 warp 规约求和的值进行一次规约，需要通过 shared-memory 将数据保存到同一个 warp 中的不同线程中，
// 在数据保存前需要__syncthreads(); 同步一下
__syncthreads(); // prevent races when BlockReduces are called in a row.
if (lid == 0) {
shared[wid] = val;
}
__syncthreads();
// 默认申请 32 大小的 shared-memory（32其实也是一个 Block 最大的 lane 个数），
// 当 Block 内线程束较少时，无法刷新 shared-memory 上全部的 32 个值，需要对未使用到的内存进行初始化；
val = (tid < B::Warps()) ? shared[lid] : T(0);
// 再次使用 WarpReduceSum 对这 32 个 thread 的值进行求和，最终一个 Block 内的值便全部规约求和到了 threadIdx.x == 0 的线程所持有的 val 值了。
// 这也就是说对于调用 BlockReduceSum 函数的代码来说，在使用规约求和后的值时需要通过 threadIdx.x == 0 的线程获取。
if (wid == 0) {
val = WarpReduceSum(val);
}
return val;
}
template <typename T, class ReduceOp>
__inline__ __device__ T WarpReduce(T val, const ReduceOp& op) {
#pragma unroll
for (int offset = (C10_WARP_SIZE >> 1); offset > 0; offset >>= 1) {
val = op.combine(val, op.warp_shfl_down(val, offset));
}
return val;
}
template <typename T, class ReduceOp, typename B = Block1D>
__inline__ __device__ T
BlockReduce(T val, const ReduceOp& op, const T& identity_element, T* shared) {
const int tid = B::Tid();
const int lid = tid % C10_WARP_SIZE;
const int wid = tid / C10_WARP_SIZE;
val = WarpReduce(val, op);
__syncthreads(); // prevent races when BlockReduces are called in a row.
if (lid == 0) {
shared[wid] = val;
}
__syncthreads();
val = (tid < B::Warps()) ? shared[lid] : identity_element;
if (wid == 0) {
val = WarpReduce(val, op);
}
return val;
}
int main(){
return 0;
} | .file "tmpxft_00065bc9_00000000-6_pytorch_block_reduce.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2038:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2038:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl main
.type main, @function
main:
.LFB2035:
.cfi_startproc
endbr64
movl $0, %eax
ret
.cfi_endproc
.LFE2035:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cuda_runtime.h>
#include <time.h>
#define C10_WARP_SIZE 32
#define N 32*1024*1024
constexpr int kCUDABlockReduceNumThreads = 512;
// Algorithmic limitation: BlockReduce does two WarpReduce calls, each
// of which reduces C10_WARP_SIZE elements. So, at most
// C10_WARP_SIZE**2 elements can be reduced at a time.
// NOTE: This is >= the max block size on current hardware anyway (1024).
constexpr int kCUDABlockReduceMaxThreads = C10_WARP_SIZE * C10_WARP_SIZE;
// Sums `val` accross all threads in a warp.
//
// Assumptions:
// - The size of each block should be a multiple of `C10_WARP_SIZE`
// 实际上 WARP_SHFL_DOWN 的实现如下：
// template <typename T>
// __device__ __forceinline__ T WARP_SHFL_DOWN(T value, unsigned int delta, int width = warpSize, unsigned int mask = 0xffffffff)
// {
// #if !defined(USE_ROCM)
// return __shfl_down_sync(mask, value, delta, width);
// #else
// return __shfl_down(value, delta, width);
// #endif
// }
// 可以看到这里使用了warp原语__shfl_down_sync来对一个warp内的val进行规约求和。
// __shfl_down_sync的相关介绍：https://docs.nvidia.com/cuda/cuda-c-programming-guide/#warp-shuffle-functions
// && https://developer.nvidia.com/zh-cn/blog/using-cuda-warp-level-primitives/
// 示意图如：https://developer.nvidia.com/blog/wp-content/uploads/2018/01/reduce_shfl_down-625x275.png 所示
// 函数原型：T __shfl_down_sync(unsigned mask, T var, unsigned int delta, int width=warpSize);
// mask表示一个warp中thread的激活表;
// var表示规约求和的变量；
// delta表示当前线程与另一个线程求和时跨越的线程偏移;
// width表示求和的宽度（个数）
// 根据循环体for (int offset = (C10_WARP_SIZE >> 1); offset > 0; offset >>= 1)，
// 第一次循环时 delta 是 16，即 Lane0（Lane0表示一个warp中的lane_index）与 Lane16 求和，Lane1 与 Lane17 求和，***，
// 依此类推，一个 warp 内的 32 个 thread 的 val 规约成 16 个val。第二次循环时 delta 是 8 ，即 Lane0 与 Lane4 求和，Lane1 与 Lane5，
// 与上图的第一次行为相同。依次类推，最终不同 warp 中的 val 规约求和到了 Lane0 所持有的 val 中。
// 至此执行完 val = WarpReduceSum(val); 后，所有 warp 的和都规约到了每个 warp 中的 lane0 的线程中了，即 lid == 0 的线程，
// wid 则代表了不同的 lane（或不同的 warp ）。
template <typename T>
__inline__ __device__ T WarpReduceSum(T val) {
#pragma unroll
for (int offset = (C10_WARP_SIZE >> 1); offset > 0; offset >>= 1) {
val += WARP_SHFL_DOWN(val, offset);
// 或者：val += __shfl_down_sync(0xffffffff， val, offset, warpSize);//warpSize为内置数据，值为32
}
return val;
}
struct Block1D {
static __forceinline__ __device__ int Tid() { return threadIdx.x; }
static __forceinline__ __device__ int Warps() {
return blockDim.x / C10_WARP_SIZE;
}
};
struct Block2D {
static __forceinline__ __device__ int Tid() {
return threadIdx.x + threadIdx.y * blockDim.x;
}
static __forceinline__ __device__ int Warps() {
return blockDim.x * blockDim.y / C10_WARP_SIZE;
}
};
// Sums `val` across all threads in a block.
//
// Warning: the return value is only valid for thread 0.
// Assumptions:
// - The size of each block should be a multiple of `C10_WARP_SIZE`
// - `shared` should be a pointer to shared memory with size of, at least,
// `sizeof(T) * number_of_warps`
// lane的中文翻译为车道（路宽），lane表示一个warp中的thread个数，
// 在 Block1D中在一个 lane 中的索引 lane_index 为 [0, warpSize - 1] 。
// 在一个 block 中会有多个 lane，lane_id = threadIdx.x / C10_WARP_SIZE ，最多有 1024 / C10_WARP_SIZE = 32 个lane。
template <typename T, typename B = Block1D>
__inline__ __device__ T BlockReduceSum(T val, T* shared) {
const int tid = B::Tid(); // 获取 block 中的线程 id
const int lid = tid % C10_WARP_SIZE; // lane id，表示当前 thread 在当前 lane 中的索引
const int wid = tid / C10_WARP_SIZE; // wid表示当前 thread 在第多少个 lane
// 每个 thread 对应寄存器中都有一个 val 值，WarpReduceSum 函数便是对 warp 中的所有 thread 所持有的 val 进行求和
val = WarpReduceSum(val);
// 下面要将各个 warp 规约求和的值进行一次规约，需要通过 shared-memory 将数据保存到同一个 warp 中的不同线程中，
// 在数据保存前需要__syncthreads(); 同步一下
__syncthreads(); // prevent races when BlockReduces are called in a row.
if (lid == 0) {
shared[wid] = val;
}
__syncthreads();
// 默认申请 32 大小的 shared-memory（32其实也是一个 Block 最大的 lane 个数），
// 当 Block 内线程束较少时，无法刷新 shared-memory 上全部的 32 个值，需要对未使用到的内存进行初始化；
val = (tid < B::Warps()) ? shared[lid] : T(0);
// 再次使用 WarpReduceSum 对这 32 个 thread 的值进行求和，最终一个 Block 内的值便全部规约求和到了 threadIdx.x == 0 的线程所持有的 val 值了。
// 这也就是说对于调用 BlockReduceSum 函数的代码来说，在使用规约求和后的值时需要通过 threadIdx.x == 0 的线程获取。
if (wid == 0) {
val = WarpReduceSum(val);
}
return val;
}
template <typename T, class ReduceOp>
__inline__ __device__ T WarpReduce(T val, const ReduceOp& op) {
#pragma unroll
for (int offset = (C10_WARP_SIZE >> 1); offset > 0; offset >>= 1) {
val = op.combine(val, op.warp_shfl_down(val, offset));
}
return val;
}
template <typename T, class ReduceOp, typename B = Block1D>
__inline__ __device__ T
BlockReduce(T val, const ReduceOp& op, const T& identity_element, T* shared) {
const int tid = B::Tid();
const int lid = tid % C10_WARP_SIZE;
const int wid = tid / C10_WARP_SIZE;
val = WarpReduce(val, op);
__syncthreads(); // prevent races when BlockReduces are called in a row.
if (lid == 0) {
shared[wid] = val;
}
__syncthreads();
val = (tid < B::Warps()) ? shared[lid] : identity_element;
if (wid == 0) {
val = WarpReduce(val, op);
}
return val;
}
int main(){
return 0;
} | #include <hip/hip_runtime.h>
#include <time.h>
#define C10_WARP_SIZE 32
#define N 32*1024*1024
constexpr int kCUDABlockReduceNumThreads = 512;
// Algorithmic limitation: BlockReduce does two WarpReduce calls, each
// of which reduces C10_WARP_SIZE elements. So, at most
// C10_WARP_SIZE**2 elements can be reduced at a time.
// NOTE: This is >= the max block size on current hardware anyway (1024).
constexpr int kCUDABlockReduceMaxThreads = C10_WARP_SIZE * C10_WARP_SIZE;
// Sums `val` accross all threads in a warp.
//
// Assumptions:
// - The size of each block should be a multiple of `C10_WARP_SIZE`
// 实际上 WARP_SHFL_DOWN 的实现如下：
// template <typename T>
// __device__ __forceinline__ T WARP_SHFL_DOWN(T value, unsigned int delta, int width = warpSize, unsigned int mask = 0xffffffff)
// {
// #if !defined(USE_ROCM)
// return __shfl_down_sync(mask, value, delta, width);
// #else
// return __shfl_down(value, delta, width);
// #endif
// }
// 可以看到这里使用了warp原语__shfl_down_sync来对一个warp内的val进行规约求和。
// __shfl_down_sync的相关介绍：https://docs.nvidia.com/cuda/cuda-c-programming-guide/#warp-shuffle-functions
// && https://developer.nvidia.com/zh-cn/blog/using-cuda-warp-level-primitives/
// 示意图如：https://developer.nvidia.com/blog/wp-content/uploads/2018/01/reduce_shfl_down-625x275.png 所示
// 函数原型：T __shfl_down_sync(unsigned mask, T var, unsigned int delta, int width=warpSize);
// mask表示一个warp中thread的激活表;
// var表示规约求和的变量；
// delta表示当前线程与另一个线程求和时跨越的线程偏移;
// width表示求和的宽度（个数）
// 根据循环体for (int offset = (C10_WARP_SIZE >> 1); offset > 0; offset >>= 1)，
// 第一次循环时 delta 是 16，即 Lane0（Lane0表示一个warp中的lane_index）与 Lane16 求和，Lane1 与 Lane17 求和，***，
// 依此类推，一个 warp 内的 32 个 thread 的 val 规约成 16 个val。第二次循环时 delta 是 8 ，即 Lane0 与 Lane4 求和，Lane1 与 Lane5，
// 与上图的第一次行为相同。依次类推，最终不同 warp 中的 val 规约求和到了 Lane0 所持有的 val 中。
// 至此执行完 val = WarpReduceSum(val); 后，所有 warp 的和都规约到了每个 warp 中的 lane0 的线程中了，即 lid == 0 的线程，
// wid 则代表了不同的 lane（或不同的 warp ）。
template <typename T>
__inline__ __device__ T WarpReduceSum(T val) {
#pragma unroll
for (int offset = (C10_WARP_SIZE >> 1); offset > 0; offset >>= 1) {
val += WARP_SHFL_DOWN(val, offset);
// 或者：val += __shfl_down_sync(0xffffffff， val, offset, warpSize);//warpSize为内置数据，值为32
}
return val;
}
struct Block1D {
static __forceinline__ __device__ int Tid() { return threadIdx.x; }
static __forceinline__ __device__ int Warps() {
return blockDim.x / C10_WARP_SIZE;
}
};
struct Block2D {
static __forceinline__ __device__ int Tid() {
return threadIdx.x + threadIdx.y * blockDim.x;
}
static __forceinline__ __device__ int Warps() {
return blockDim.x * blockDim.y / C10_WARP_SIZE;
}
};
// Sums `val` across all threads in a block.
//
// Warning: the return value is only valid for thread 0.
// Assumptions:
// - The size of each block should be a multiple of `C10_WARP_SIZE`
// - `shared` should be a pointer to shared memory with size of, at least,
// `sizeof(T) * number_of_warps`
// lane的中文翻译为车道（路宽），lane表示一个warp中的thread个数，
// 在 Block1D中在一个 lane 中的索引 lane_index 为 [0, warpSize - 1] 。
// 在一个 block 中会有多个 lane，lane_id = threadIdx.x / C10_WARP_SIZE ，最多有 1024 / C10_WARP_SIZE = 32 个lane。
template <typename T, typename B = Block1D>
__inline__ __device__ T BlockReduceSum(T val, T* shared) {
const int tid = B::Tid(); // 获取 block 中的线程 id
const int lid = tid % C10_WARP_SIZE; // lane id，表示当前 thread 在当前 lane 中的索引
const int wid = tid / C10_WARP_SIZE; // wid表示当前 thread 在第多少个 lane
// 每个 thread 对应寄存器中都有一个 val 值，WarpReduceSum 函数便是对 warp 中的所有 thread 所持有的 val 进行求和
val = WarpReduceSum(val);
// 下面要将各个 warp 规约求和的值进行一次规约，需要通过 shared-memory 将数据保存到同一个 warp 中的不同线程中，
// 在数据保存前需要__syncthreads(); 同步一下
__syncthreads(); // prevent races when BlockReduces are called in a row.
if (lid == 0) {
shared[wid] = val;
}
__syncthreads();
// 默认申请 32 大小的 shared-memory（32其实也是一个 Block 最大的 lane 个数），
// 当 Block 内线程束较少时，无法刷新 shared-memory 上全部的 32 个值，需要对未使用到的内存进行初始化；
val = (tid < B::Warps()) ? shared[lid] : T(0);
// 再次使用 WarpReduceSum 对这 32 个 thread 的值进行求和，最终一个 Block 内的值便全部规约求和到了 threadIdx.x == 0 的线程所持有的 val 值了。
// 这也就是说对于调用 BlockReduceSum 函数的代码来说，在使用规约求和后的值时需要通过 threadIdx.x == 0 的线程获取。
if (wid == 0) {
val = WarpReduceSum(val);
}
return val;
}
template <typename T, class ReduceOp>
__inline__ __device__ T WarpReduce(T val, const ReduceOp& op) {
#pragma unroll
for (int offset = (C10_WARP_SIZE >> 1); offset > 0; offset >>= 1) {
val = op.combine(val, op.warp_shfl_down(val, offset));
}
return val;
}
template <typename T, class ReduceOp, typename B = Block1D>
__inline__ __device__ T
BlockReduce(T val, const ReduceOp& op, const T& identity_element, T* shared) {
const int tid = B::Tid();
const int lid = tid % C10_WARP_SIZE;
const int wid = tid / C10_WARP_SIZE;
val = WarpReduce(val, op);
__syncthreads(); // prevent races when BlockReduces are called in a row.
if (lid == 0) {
shared[wid] = val;
}
__syncthreads();
val = (tid < B::Warps()) ? shared[lid] : identity_element;
if (wid == 0) {
val = WarpReduce(val, op);
}
return val;
}
int main(){
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <time.h>
#define C10_WARP_SIZE 32
#define N 32*1024*1024
constexpr int kCUDABlockReduceNumThreads = 512;
// Algorithmic limitation: BlockReduce does two WarpReduce calls, each
// of which reduces C10_WARP_SIZE elements. So, at most
// C10_WARP_SIZE**2 elements can be reduced at a time.
// NOTE: This is >= the max block size on current hardware anyway (1024).
constexpr int kCUDABlockReduceMaxThreads = C10_WARP_SIZE * C10_WARP_SIZE;
// Sums `val` accross all threads in a warp.
//
// Assumptions:
// - The size of each block should be a multiple of `C10_WARP_SIZE`
// 实际上 WARP_SHFL_DOWN 的实现如下：
// template <typename T>
// __device__ __forceinline__ T WARP_SHFL_DOWN(T value, unsigned int delta, int width = warpSize, unsigned int mask = 0xffffffff)
// {
// #if !defined(USE_ROCM)
// return __shfl_down_sync(mask, value, delta, width);
// #else
// return __shfl_down(value, delta, width);
// #endif
// }
// 可以看到这里使用了warp原语__shfl_down_sync来对一个warp内的val进行规约求和。
// __shfl_down_sync的相关介绍：https://docs.nvidia.com/cuda/cuda-c-programming-guide/#warp-shuffle-functions
// && https://developer.nvidia.com/zh-cn/blog/using-cuda-warp-level-primitives/
// 示意图如：https://developer.nvidia.com/blog/wp-content/uploads/2018/01/reduce_shfl_down-625x275.png 所示
// 函数原型：T __shfl_down_sync(unsigned mask, T var, unsigned int delta, int width=warpSize);
// mask表示一个warp中thread的激活表;
// var表示规约求和的变量；
// delta表示当前线程与另一个线程求和时跨越的线程偏移;
// width表示求和的宽度（个数）
// 根据循环体for (int offset = (C10_WARP_SIZE >> 1); offset > 0; offset >>= 1)，
// 第一次循环时 delta 是 16，即 Lane0（Lane0表示一个warp中的lane_index）与 Lane16 求和，Lane1 与 Lane17 求和，***，
// 依此类推，一个 warp 内的 32 个 thread 的 val 规约成 16 个val。第二次循环时 delta 是 8 ，即 Lane0 与 Lane4 求和，Lane1 与 Lane5，
// 与上图的第一次行为相同。依次类推，最终不同 warp 中的 val 规约求和到了 Lane0 所持有的 val 中。
// 至此执行完 val = WarpReduceSum(val); 后，所有 warp 的和都规约到了每个 warp 中的 lane0 的线程中了，即 lid == 0 的线程，
// wid 则代表了不同的 lane（或不同的 warp ）。
template <typename T>
__inline__ __device__ T WarpReduceSum(T val) {
#pragma unroll
for (int offset = (C10_WARP_SIZE >> 1); offset > 0; offset >>= 1) {
val += WARP_SHFL_DOWN(val, offset);
// 或者：val += __shfl_down_sync(0xffffffff， val, offset, warpSize);//warpSize为内置数据，值为32
}
return val;
}
struct Block1D {
static __forceinline__ __device__ int Tid() { return threadIdx.x; }
static __forceinline__ __device__ int Warps() {
return blockDim.x / C10_WARP_SIZE;
}
};
struct Block2D {
static __forceinline__ __device__ int Tid() {
return threadIdx.x + threadIdx.y * blockDim.x;
}
static __forceinline__ __device__ int Warps() {
return blockDim.x * blockDim.y / C10_WARP_SIZE;
}
};
// Sums `val` across all threads in a block.
//
// Warning: the return value is only valid for thread 0.
// Assumptions:
// - The size of each block should be a multiple of `C10_WARP_SIZE`
// - `shared` should be a pointer to shared memory with size of, at least,
// `sizeof(T) * number_of_warps`
// lane的中文翻译为车道（路宽），lane表示一个warp中的thread个数，
// 在 Block1D中在一个 lane 中的索引 lane_index 为 [0, warpSize - 1] 。
// 在一个 block 中会有多个 lane，lane_id = threadIdx.x / C10_WARP_SIZE ，最多有 1024 / C10_WARP_SIZE = 32 个lane。
template <typename T, typename B = Block1D>
__inline__ __device__ T BlockReduceSum(T val, T* shared) {
const int tid = B::Tid(); // 获取 block 中的线程 id
const int lid = tid % C10_WARP_SIZE; // lane id，表示当前 thread 在当前 lane 中的索引
const int wid = tid / C10_WARP_SIZE; // wid表示当前 thread 在第多少个 lane
// 每个 thread 对应寄存器中都有一个 val 值，WarpReduceSum 函数便是对 warp 中的所有 thread 所持有的 val 进行求和
val = WarpReduceSum(val);
// 下面要将各个 warp 规约求和的值进行一次规约，需要通过 shared-memory 将数据保存到同一个 warp 中的不同线程中，
// 在数据保存前需要__syncthreads(); 同步一下
__syncthreads(); // prevent races when BlockReduces are called in a row.
if (lid == 0) {
shared[wid] = val;
}
__syncthreads();
// 默认申请 32 大小的 shared-memory（32其实也是一个 Block 最大的 lane 个数），
// 当 Block 内线程束较少时，无法刷新 shared-memory 上全部的 32 个值，需要对未使用到的内存进行初始化；
val = (tid < B::Warps()) ? shared[lid] : T(0);
// 再次使用 WarpReduceSum 对这 32 个 thread 的值进行求和，最终一个 Block 内的值便全部规约求和到了 threadIdx.x == 0 的线程所持有的 val 值了。
// 这也就是说对于调用 BlockReduceSum 函数的代码来说，在使用规约求和后的值时需要通过 threadIdx.x == 0 的线程获取。
if (wid == 0) {
val = WarpReduceSum(val);
}
return val;
}
template <typename T, class ReduceOp>
__inline__ __device__ T WarpReduce(T val, const ReduceOp& op) {
#pragma unroll
for (int offset = (C10_WARP_SIZE >> 1); offset > 0; offset >>= 1) {
val = op.combine(val, op.warp_shfl_down(val, offset));
}
return val;
}
template <typename T, class ReduceOp, typename B = Block1D>
__inline__ __device__ T
BlockReduce(T val, const ReduceOp& op, const T& identity_element, T* shared) {
const int tid = B::Tid();
const int lid = tid % C10_WARP_SIZE;
const int wid = tid / C10_WARP_SIZE;
val = WarpReduce(val, op);
__syncthreads(); // prevent races when BlockReduces are called in a row.
if (lid == 0) {
shared[wid] = val;
}
__syncthreads();
val = (tid < B::Warps()) ? shared[lid] : identity_element;
if (wid == 0) {
val = WarpReduce(val, op);
}
return val;
}
int main(){
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <time.h>
#define C10_WARP_SIZE 32
#define N 32*1024*1024
constexpr int kCUDABlockReduceNumThreads = 512;
// Algorithmic limitation: BlockReduce does two WarpReduce calls, each
// of which reduces C10_WARP_SIZE elements. So, at most
// C10_WARP_SIZE**2 elements can be reduced at a time.
// NOTE: This is >= the max block size on current hardware anyway (1024).
constexpr int kCUDABlockReduceMaxThreads = C10_WARP_SIZE * C10_WARP_SIZE;
// Sums `val` accross all threads in a warp.
//
// Assumptions:
// - The size of each block should be a multiple of `C10_WARP_SIZE`
// 实际上 WARP_SHFL_DOWN 的实现如下：
// template <typename T>
// __device__ __forceinline__ T WARP_SHFL_DOWN(T value, unsigned int delta, int width = warpSize, unsigned int mask = 0xffffffff)
// {
// #if !defined(USE_ROCM)
// return __shfl_down_sync(mask, value, delta, width);
// #else
// return __shfl_down(value, delta, width);
// #endif
// }
// 可以看到这里使用了warp原语__shfl_down_sync来对一个warp内的val进行规约求和。
// __shfl_down_sync的相关介绍：https://docs.nvidia.com/cuda/cuda-c-programming-guide/#warp-shuffle-functions
// && https://developer.nvidia.com/zh-cn/blog/using-cuda-warp-level-primitives/
// 示意图如：https://developer.nvidia.com/blog/wp-content/uploads/2018/01/reduce_shfl_down-625x275.png 所示
// 函数原型：T __shfl_down_sync(unsigned mask, T var, unsigned int delta, int width=warpSize);
// mask表示一个warp中thread的激活表;
// var表示规约求和的变量；
// delta表示当前线程与另一个线程求和时跨越的线程偏移;
// width表示求和的宽度（个数）
// 根据循环体for (int offset = (C10_WARP_SIZE >> 1); offset > 0; offset >>= 1)，
// 第一次循环时 delta 是 16，即 Lane0（Lane0表示一个warp中的lane_index）与 Lane16 求和，Lane1 与 Lane17 求和，***，
// 依此类推，一个 warp 内的 32 个 thread 的 val 规约成 16 个val。第二次循环时 delta 是 8 ，即 Lane0 与 Lane4 求和，Lane1 与 Lane5，
// 与上图的第一次行为相同。依次类推，最终不同 warp 中的 val 规约求和到了 Lane0 所持有的 val 中。
// 至此执行完 val = WarpReduceSum(val); 后，所有 warp 的和都规约到了每个 warp 中的 lane0 的线程中了，即 lid == 0 的线程，
// wid 则代表了不同的 lane（或不同的 warp ）。
template <typename T>
__inline__ __device__ T WarpReduceSum(T val) {
#pragma unroll
for (int offset = (C10_WARP_SIZE >> 1); offset > 0; offset >>= 1) {
val += WARP_SHFL_DOWN(val, offset);
// 或者：val += __shfl_down_sync(0xffffffff， val, offset, warpSize);//warpSize为内置数据，值为32
}
return val;
}
struct Block1D {
static __forceinline__ __device__ int Tid() { return threadIdx.x; }
static __forceinline__ __device__ int Warps() {
return blockDim.x / C10_WARP_SIZE;
}
};
struct Block2D {
static __forceinline__ __device__ int Tid() {
return threadIdx.x + threadIdx.y * blockDim.x;
}
static __forceinline__ __device__ int Warps() {
return blockDim.x * blockDim.y / C10_WARP_SIZE;
}
};
// Sums `val` across all threads in a block.
//
// Warning: the return value is only valid for thread 0.
// Assumptions:
// - The size of each block should be a multiple of `C10_WARP_SIZE`
// - `shared` should be a pointer to shared memory with size of, at least,
// `sizeof(T) * number_of_warps`
// lane的中文翻译为车道（路宽），lane表示一个warp中的thread个数，
// 在 Block1D中在一个 lane 中的索引 lane_index 为 [0, warpSize - 1] 。
// 在一个 block 中会有多个 lane，lane_id = threadIdx.x / C10_WARP_SIZE ，最多有 1024 / C10_WARP_SIZE = 32 个lane。
template <typename T, typename B = Block1D>
__inline__ __device__ T BlockReduceSum(T val, T* shared) {
const int tid = B::Tid(); // 获取 block 中的线程 id
const int lid = tid % C10_WARP_SIZE; // lane id，表示当前 thread 在当前 lane 中的索引
const int wid = tid / C10_WARP_SIZE; // wid表示当前 thread 在第多少个 lane
// 每个 thread 对应寄存器中都有一个 val 值，WarpReduceSum 函数便是对 warp 中的所有 thread 所持有的 val 进行求和
val = WarpReduceSum(val);
// 下面要将各个 warp 规约求和的值进行一次规约，需要通过 shared-memory 将数据保存到同一个 warp 中的不同线程中，
// 在数据保存前需要__syncthreads(); 同步一下
__syncthreads(); // prevent races when BlockReduces are called in a row.
if (lid == 0) {
shared[wid] = val;
}
__syncthreads();
// 默认申请 32 大小的 shared-memory（32其实也是一个 Block 最大的 lane 个数），
// 当 Block 内线程束较少时，无法刷新 shared-memory 上全部的 32 个值，需要对未使用到的内存进行初始化；
val = (tid < B::Warps()) ? shared[lid] : T(0);
// 再次使用 WarpReduceSum 对这 32 个 thread 的值进行求和，最终一个 Block 内的值便全部规约求和到了 threadIdx.x == 0 的线程所持有的 val 值了。
// 这也就是说对于调用 BlockReduceSum 函数的代码来说，在使用规约求和后的值时需要通过 threadIdx.x == 0 的线程获取。
if (wid == 0) {
val = WarpReduceSum(val);
}
return val;
}
template <typename T, class ReduceOp>
__inline__ __device__ T WarpReduce(T val, const ReduceOp& op) {
#pragma unroll
for (int offset = (C10_WARP_SIZE >> 1); offset > 0; offset >>= 1) {
val = op.combine(val, op.warp_shfl_down(val, offset));
}
return val;
}
template <typename T, class ReduceOp, typename B = Block1D>
__inline__ __device__ T
BlockReduce(T val, const ReduceOp& op, const T& identity_element, T* shared) {
const int tid = B::Tid();
const int lid = tid % C10_WARP_SIZE;
const int wid = tid / C10_WARP_SIZE;
val = WarpReduce(val, op);
__syncthreads(); // prevent races when BlockReduces are called in a row.
if (lid == 0) {
shared[wid] = val;
}
__syncthreads();
val = (tid < B::Warps()) ? shared[lid] : identity_element;
if (wid == 0) {
val = WarpReduce(val, op);
}
return val;
}
int main(){
return 0;
} | .text
.file "pytorch_block_reduce.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
xorl %eax, %eax
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00065bc9_00000000-6_pytorch_block_reduce.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2038:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2038:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl main
.type main, @function
main:
.LFB2035:
.cfi_startproc
endbr64
movl $0, %eax
ret
.cfi_endproc
.LFE2035:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "pytorch_block_reduce.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
xorl %eax, %eax
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include "cuda_runtime.h"
//#include "cuda_profiler_api.h"
#define THREADS 32 //In each block THREADS*THREADS threads
struct matrix {
int ncols;
int nrows;
double* mat;
};
void readMatrix(struct matrix* m, FILE* file);
void printMatrix(struct matrix* m, FILE* file);
__global__ void matrixMul(double *d_m1, double *d_m2, double *d_m3, int row1, int row2, int col1, int col2);
/*
* The file which contains a matrix has in its first row the dimensions
* then using fscanf each element of the matrix is stored on the memory allocated dynamically
*/
void readMatrix(struct matrix* m, FILE* file) {
int i, j;
m->mat = (double*)malloc(m->ncols * m->nrows * sizeof(double));
for (i = 0; i < m->nrows; i++) {
for (j = 0; j < m->ncols; j++) {
fscanf(file, "%lf", &m->mat[i * m->ncols + j]);
}
}
}
/* The opposite operation of readMatrix. Stores a matrix into a file, element by element */
void printMatrix(struct matrix* m, FILE* file) {
int i, j;
for (i = 0; i < m->nrows; i++) {
for (j = 0; j < m->ncols; j++) {
fprintf(file, "%lf ", m->mat[i * m->ncols + j]);
}
fprintf(file, "\n");
}
}
/*
* Performs the multiplication operation between the matrices m1 and m2.
* The result will be stored in the matrix m3.
* The algorithm is practically the one that can be found here: https://en.wikipedia.org/wiki/Matrix_multiplication#Definition
* The grid is sized in a 2D way as each blocks whose dimension is THREADSxTHREADS, this helps in associating to a single thread and element of the result matrix to which calcutate a summation exploiting the numerous core of a GPU.
*/
__global__ void matrixMul(double *d_m1, double *d_m2, double *d_m3, int row1, int row2, int col1, int col2){
//coordinates of each thread inside the grind and so inside a block
int i = blockIdx.y*blockDim.y+threadIdx.y;
int j = blockIdx.x*blockDim.x+threadIdx.x;
double sum = 0;
int k;
//the two previous for cycle are substituted by the matrix of threads
if ((i < row1) && (j < col2)){
for(k = 0; k<col1; k++){
sum += d_m1[i*col1+k]*d_m2[k*col2+j];
}
d_m3[i*col2+j]=sum;
}
}
int main(int argc, char* argv[]) {
if(argc != 3){ //1- exe name, 2- mat1.txt, 3- mat2.txt
printf("Parameter error.\n");
exit(1);
}
FILE *mat1, *mat2, *resultFile;
clock_t t;
struct matrix m1, m2, m3;
mat1 = fopen(argv[1], "r");
mat2 = fopen(argv[2], "r");
fscanf(mat1, "%d %d", &m1.nrows, &m1.ncols);
fscanf(mat2, "%d %d", &m2.nrows, &m2.ncols);
/* Multiplication is permitted if m1 is m x n and m2 is n x p, m1 must have the same number of column of the rows of m2 matrix */
if(m1.ncols != m2.nrows){
printf("It is not possible to do matrix multiplication. Check matrices number of rows and cols.\n");
fclose(mat1);
fclose(mat2);
exit(1);
}
readMatrix(&m1, mat1);
readMatrix(&m2, mat2);
//M3 initilization
m3.nrows=m1.nrows;
m3.ncols=m2.ncols;
m3.mat = (double*)malloc(m3.ncols * m3.nrows * sizeof(double));
//cudaProfilerStart();
/* Device variable, allocations, and transfers */
double *d_m1, *d_m2, *d_m3;
cudaMalloc((void**)&d_m1, m1.nrows*m1.ncols*sizeof(double));
cudaMalloc((void**)&d_m2, m2.nrows*m2.ncols*sizeof(double));
cudaMalloc((void**)&d_m3, m3.nrows*m3.ncols*sizeof(double));
cudaMemcpy(d_m1, m1.mat, m1.nrows*m1.ncols * sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(d_m2, m2.mat, m2.nrows*m2.ncols * sizeof(double), cudaMemcpyHostToDevice);
cudaMemset(d_m3, 0, m3.nrows*m3.ncols*sizeof(double));
dim3 dimBlock(THREADS, THREADS); //each block is THREADxTHREAD
dim3 dimGrid((m2.ncols+dimBlock.x-1)/dimBlock.x, (m1.nrows+dimBlock.y-1)/dimBlock.y); //the grid is allocated so the necessary amount of blocks are initialized
t = clock();
matrixMul <<<dimGrid, dimBlock>>>(d_m1, d_m2, d_m3, m1.nrows, m2.nrows, m1.ncols, m2.ncols);
cudaDeviceSynchronize();
t = clock() - t; //total time spent in matrixMul (wall clock time)
cudaMemcpy(m3.mat, d_m3, m3.nrows*m3.ncols * sizeof(double), cudaMemcpyDeviceToHost);
//cudaProfilerStop();
resultFile = fopen("result.txt", "w");
printMatrix(&m3, resultFile);
printf("Elapsed time: %.5lf seconds\n", ((double)t)/CLOCKS_PER_SEC);
fclose(mat1);
fclose(mat2);
fclose(resultFile);
cudaFree(d_m1);
cudaFree(d_m2);
cudaFree(d_m3);
free(m1.mat);
free(m2.mat);
free(m3.mat);
return 0;
} | code for sm_80
Function : _Z9matrixMulPdS_S_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x184], PT ; /* 0x0000610000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x180] ; /* 0x0000600000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe4000001ff00 */
/*00d0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0xc80 ; /* 0x00000b9000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe20007ffe0ff */
/*0100*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*0110*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fe200078ec0ff */
/*0120*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe2000001ff00 */
/*0130*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fda0003f06070 */
/*0140*/ @!P0 BRA 0xb30 ; /* 0x000009e000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R4, -R2, c[0x0][0x180], RZ ; /* 0x0000600002047a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0170*/ MOV R29, 0x8 ; /* 0x00000008001d7802 */
/* 0x000fe20000000f00 */
/*0180*/ IMAD R26, R3, c[0x0][0x180], RZ ; /* 0x00006000031a7a24 */
/* 0x000fe200078e02ff */
/*0190*/ ISETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f04270 */
/*01a0*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe2000001ff00 */
/*01b0*/ MOV R5, RZ ; /* 0x000000ff00057202 */
/* 0x000fe20000000f00 */
/*01c0*/ IMAD.WIDE R28, R0, R29, c[0x0][0x168] ; /* 0x00005a00001c7625 */
/* 0x000fd400078e021d */
/*01d0*/ @!P0 BRA 0x990 ; /* 0x000007b000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6c0 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*0230*/ IMAD.U32 R7, RZ, RZ, UR7 ; /* 0x00000007ff077e24 */
/* 0x000fe2000f8e00ff */
/*0240*/ LDG.E.64 R20, [R28.64] ; /* 0x000000041c147981 */
/* 0x0010a6000c1e1b00 */
/*0250*/ IMAD.WIDE R6, R26, 0x8, R6 ; /* 0x000000081a067825 */
/* 0x000fca00078e0206 */
/*0260*/ LDG.E.64 R12, [R6.64] ; /* 0x00000004060c7981 */
/* 0x000ea2000c1e1b00 */
/*0270*/ MOV R27, c[0x0][0x184] ; /* 0x00006100001b7a02 */
/* 0x000fc60000000f00 */
/*0280*/ LDG.E.64 R10, [R6.64+0x8] ; /* 0x00000804060a7981 */
/* 0x000ee4000c1e1b00 */
/*0290*/ IMAD.WIDE R24, R27.reuse, 0x8, R28 ; /* 0x000000081b187825 */
/* 0x040fe400078e021c */
/*02a0*/ LDG.E.64 R8, [R6.64+0x10] ; /* 0x0000100406087981 */
/* 0x000f28000c1e1b00 */
/*02b0*/ LDG.E.64 R16, [R24.64] ; /* 0x0000000418107981 */
/* 0x000ee2000c1e1b00 */
/*02c0*/ IMAD.WIDE R22, R27, 0x8, R24 ; /* 0x000000081b167825 */
/* 0x000fca00078e0218 */
/*02d0*/ LDG.E.64 R14, [R22.64] ; /* 0x00000004160e7981 */
/* 0x002322000c1e1b00 */
/*02e0*/ IMAD.WIDE R28, R27, 0x8, R22 ; /* 0x000000081b1c7825 */
/* 0x001fc600078e0216 */
/*02f0*/ LDG.E.64 R22, [R6.64+0x18] ; /* 0x0000180406167981 */
/* 0x002f62000c1e1b00 */
/*0300*/ DFMA R18, R20, R12, R18 ; /* 0x0000000c1412722b */
/* 0x0040c60000000012 */
/*0310*/ LDG.E.64 R12, [R28.64] ; /* 0x000000041c0c7981 */
/* 0x001164000c1e1b00 */
/*0320*/ IMAD.WIDE R28, R27.reuse, 0x8, R28 ; /* 0x000000081b1c7825 */
/* 0x041fe200078e021c */
/*0330*/ DFMA R18, R16, R10, R18 ; /* 0x0000000a1012722b */
/* 0x0081240000000012 */
/*0340*/ LDG.E.64 R16, [R6.64+0x20] ; /* 0x0000200406107981 */
/* 0x001ea8000c1e1b00 */
/*0350*/ LDG.E.64 R10, [R28.64] ; /* 0x000000041c0a7981 */
/* 0x000ea2000c1e1b00 */
/*0360*/ IMAD.WIDE R24, R27, 0x8, R28 ; /* 0x000000081b187825 */
/* 0x000fe200078e021c */
/*0370*/ DFMA R18, R14, R8, R18 ; /* 0x000000080e12722b */
/* 0x0101440000000012 */
/*0380*/ LDG.E.64 R14, [R6.64+0x28] ; /* 0x00002804060e7981 */
/* 0x001ee8000c1e1b00 */
/*0390*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x000ee2000c1e1b00 */
/*03a0*/ IMAD.WIDE R20, R27.reuse, 0x8, R24 ; /* 0x000000081b147825 */
/* 0x040fe200078e0218 */
/*03b0*/ DFMA R22, R12, R22, R18 ; /* 0x000000160c16722b */
/* 0x0200a40000000012 */
/*03c0*/ LDG.E.64 R18, [R6.64+0x30] ; /* 0x0000300406127981 */
/* 0x001f28000c1e1b00 */
/*03d0*/ LDG.E.64 R12, [R20.64] ; /* 0x00000004140c7981 */
/* 0x000124000c1e1b00 */
/*03e0*/ IMAD.WIDE R20, R27, 0x8, R20 ; /* 0x000000081b147825 */
/* 0x001fe200078e0214 */
/*03f0*/ DFMA R16, R10, R16, R22 ; /* 0x000000100a10722b */
/* 0x0040c40000000016 */
/*0400*/ LDG.E.64 R22, [R6.64+0x38] ; /* 0x0000380406167981 */
/* 0x001ea8000c1e1b00 */
/*0410*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000ea2000c1e1b00 */
/*0420*/ IMAD.WIDE R28, R27.reuse, 0x8, R20 ; /* 0x000000081b1c7825 */
/* 0x040fe200078e0214 */
/*0430*/ DFMA R14, R8, R14, R16 ; /* 0x0000000e080e722b */
/* 0x0081240000000010 */
/*0440*/ LDG.E.64 R16, [R6.64+0x40] ; /* 0x0000400406107981 */
/* 0x001ee8000c1e1b00 */
/*0450*/ LDG.E.64 R8, [R28.64] ; /* 0x000000041c087981 */
/* 0x000ee2000c1e1b00 */
/*0460*/ IMAD.WIDE R24, R27, 0x8, R28 ; /* 0x000000081b187825 */
/* 0x000fe200078e021c */
/*0470*/ DFMA R18, R12, R18, R14 ; /* 0x000000120c12722b */
/* 0x010084000000000e */
/*0480*/ LDG.E.64 R14, [R6.64+0x48] ; /* 0x00004804060e7981 */
/* 0x001f28000c1e1b00 */
/*0490*/ LDG.E.64 R12, [R24.64] ; /* 0x00000004180c7981 */
/* 0x000124000c1e1b00 */
/*04a0*/ IMAD.WIDE R24, R27.reuse, 0x8, R24 ; /* 0x000000081b187825 */
/* 0x041fe200078e0218 */
/*04b0*/ DFMA R22, R10, R22, R18 ; /* 0x000000160a16722b */
/* 0x0040e40000000012 */
/*04c0*/ LDG.E.64 R18, [R6.64+0x50] ; /* 0x0000500406127981 */
/* 0x001ea6000c1e1b00 */
/*04d0*/ IMAD.WIDE R20, R27, 0x8, R24 ; /* 0x000000081b147825 */
/* 0x000fe200078e0218 */
/*04e0*/ LDG.E.64 R10, [R24.64] ; /* 0x00000004180a7981 */
/* 0x000ea2000c1e1b00 */
/*04f0*/ DFMA R16, R8, R16, R22 ; /* 0x000000100810722b */
/* 0x0081060000000016 */
/*0500*/ LDG.E.64 R22, [R6.64+0x58] ; /* 0x0000580406167981 */
/* 0x001ee8000c1e1b00 */
/*0510*/ LDG.E.64 R8, [R20.64] ; /* 0x0000000414087981 */
/* 0x000ee2000c1e1b00 */
/*0520*/ IMAD.WIDE R28, R27.reuse, 0x8, R20 ; /* 0x000000081b1c7825 */
/* 0x040fe200078e0214 */
/*0530*/ DFMA R14, R12, R14, R16 ; /* 0x0000000e0c0e722b */
/* 0x0100a40000000010 */
/*0540*/ LDG.E.64 R12, [R6.64+0x60] ; /* 0x00006004060c7981 */
/* 0x001f28000c1e1b00 */
/*0550*/ LDG.E.64 R16, [R28.64] ; /* 0x000000041c107981 */
/* 0x000124000c1e1b00 */
/*0560*/ IMAD.WIDE R28, R27, 0x8, R28 ; /* 0x000000081b1c7825 */
/* 0x001fe200078e021c */
/*0570*/ DFMA R18, R10, R18, R14 ; /* 0x000000120a12722b */
/* 0x0040c4000000000e */
/*0580*/ LDG.E.64 R10, [R6.64+0x68] ; /* 0x00006804060a7981 */
/* 0x001ea6000c1e1b00 */
/*0590*/ IMAD.WIDE R24, R27, 0x8, R28 ; /* 0x000000081b187825 */
/* 0x000fe200078e021c */
/*05a0*/ LDG.E.64 R14, [R28.64] ; /* 0x000000041c0e7981 */
/* 0x000ea2000c1e1b00 */
/*05b0*/ DFMA R22, R8, R22, R18 ; /* 0x000000160816722b */
/* 0x0081060000000012 */
/*05c0*/ LDG.E.64 R18, [R6.64+0x70] ; /* 0x0000700406127981 */
/* 0x001ee2000c1e1b00 */
/*05d0*/ IMAD.WIDE R8, R27, 0x8, R24 ; /* 0x000000081b087825 */
/* 0x000fc600078e0218 */
/*05e0*/ LDG.E.64 R20, [R24.64] ; /* 0x0000000418147981 */
/* 0x000ee2000c1e1b00 */
/*05f0*/ DFMA R12, R16, R12, R22 ; /* 0x0000000c100c722b */
/* 0x0100860000000016 */
/*0600*/ LDG.E.64 R16, [R6.64+0x78] ; /* 0x0000780406107981 */
/* 0x001f28000c1e1b00 */
/*0610*/ LDG.E.64 R22, [R8.64] ; /* 0x0000000408167981 */
/* 0x000f22000c1e1b00 */
/*0620*/ IADD3 R4, R4, -0x10, RZ ; /* 0xfffffff004047810 */
/* 0x000fc80007ffe0ff */
/*0630*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe20003f24270 */
/*0640*/ DFMA R10, R14, R10, R12 ; /* 0x0000000a0e0a722b */
/* 0x004ee2000000000c */
/*0650*/ UIADD3 UR6, UP0, UR6, 0x80, URZ ; /* 0x0000008006067890 */
/* 0x000fca000ff1e03f */
/*0660*/ DFMA R18, R20, R18, R10 ; /* 0x000000121412722b */
/* 0x008f22000000000a */
/*0670*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0680*/ IMAD.WIDE R28, R27, 0x8, R8 ; /* 0x000000081b1c7825 */
/* 0x000fe200078e0208 */
/*0690*/ IADD3 R5, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x000fc60007ffe0ff */
/*06a0*/ DFMA R18, R22, R16, R18 ; /* 0x000000101612722b */
/* 0x0100620000000012 */
/*06b0*/ @P1 BRA 0x220 ; /* 0xfffffb6000001947 */
/* 0x000fea000383ffff */
/*06c0*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*06d0*/ @!P1 BRA 0x970 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*06e0*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*06f0*/ LDG.E.64 R20, [R28.64] ; /* 0x000000041c147981 */
/* 0x0004e2000c1e1b00 */
/*0700*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fe40008000f00 */
/*0710*/ MOV R27, c[0x0][0x184] ; /* 0x00006100001b7a02 */
/* 0x000fc60000000f00 */
/*0720*/ IMAD.WIDE R6, R26, 0x8, R6 ; /* 0x000000081a067825 */
/* 0x000fca00078e0206 */
/*0730*/ LDG.E.64 R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x000ee2000c1e1b00 */
/*0740*/ IMAD.WIDE R22, R27, 0x8, R28 ; /* 0x000000081b167825 */
/* 0x001fc600078e021c */
/*0750*/ LDG.E.64 R14, [R6.64+0x8] ; /* 0x00000804060e7981 */
/* 0x000f28000c1e1b00 */
/*0760*/ LDG.E.64 R16, [R22.64] ; /* 0x0000000416107981 */
/* 0x000128000c1e1b00 */
/*0770*/ LDG.E.64 R12, [R6.64+0x10] ; /* 0x00001004060c7981 */
/* 0x000f62000c1e1b00 */
/*0780*/ IMAD.WIDE R22, R27, 0x8, R22 ; /* 0x000000081b167825 */
/* 0x001fca00078e0216 */
/*0790*/ LDG.E.64 R8, [R22.64] ; /* 0x0000000416087981 */
/* 0x000f62000c1e1b00 */
/*07a0*/ IMAD.WIDE R24, R27, 0x8, R22 ; /* 0x000000081b187825 */
/* 0x000fcc00078e0216 */
/*07b0*/ IMAD.WIDE R28, R27, 0x8, R24 ; /* 0x000000081b1c7825 */
/* 0x004fe200078e0218 */
/*07c0*/ DFMA R18, R20, R10, R18 ; /* 0x0000000a1412722b */
/* 0x00a1240000000012 */
/*07d0*/ LDG.E.64 R20, [R6.64+0x18] ; /* 0x0000180406147981 */
/* 0x001ea8000c1e1b00 */
/*07e0*/ LDG.E.64 R10, [R24.64] ; /* 0x00000004180a7981 */
/* 0x0000a2000c1e1b00 */
/*07f0*/ DFMA R14, R16, R14, R18 ; /* 0x0000000e100e722b */
/* 0x0103460000000012 */
/*0800*/ LDG.E.64 R18, [R6.64+0x20] ; /* 0x0000200406127981 */
/* 0x002ee8000c1e1b00 */
/*0810*/ LDG.E.64 R16, [R28.64] ; /* 0x000000041c107981 */
/* 0x0002e2000c1e1b00 */
/*0820*/ DFMA R12, R8, R12, R14 ; /* 0x0000000c080c722b */
/* 0x0208a2000000000e */
/*0830*/ IMAD.WIDE R28, R27.reuse, 0x8, R28 ; /* 0x000000081b1c7825 */
/* 0x042fe400078e021c */
/*0840*/ LDG.E.64 R8, [R6.64+0x28] ; /* 0x0000280406087981 */
/* 0x010f28000c1e1b00 */
/*0850*/ LDG.E.64 R14, [R28.64] ; /* 0x000000041c0e7981 */
/* 0x000f22000c1e1b00 */
/*0860*/ IMAD.WIDE R22, R27, 0x8, R28 ; /* 0x000000081b167825 */
/* 0x000fcc00078e021c */
/*0870*/ IMAD.WIDE R24, R27, 0x8, R22 ; /* 0x000000081b187825 */
/* 0x001fe200078e0216 */
/*0880*/ DFMA R20, R10, R20, R12 ; /* 0x000000140a14722b */
/* 0x0040e4000000000c */
/*0890*/ LDG.E.64 R12, [R6.64+0x30] ; /* 0x00003004060c7981 */
/* 0x001ea8000c1e1b00 */
/*08a0*/ LDG.E.64 R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000ea2000c1e1b00 */
/*08b0*/ DFMA R16, R16, R18, R20 ; /* 0x000000121010722b */
/* 0x0081060000000014 */
/*08c0*/ LDG.E.64 R18, [R6.64+0x38] ; /* 0x0000380406127981 */
/* 0x001ee8000c1e1b00 */
/*08d0*/ LDG.E.64 R20, [R24.64] ; /* 0x0000000418147981 */
/* 0x000ee2000c1e1b00 */
/*08e0*/ DFMA R8, R14, R8, R16 ; /* 0x000000080e08722b */
/* 0x010ea20000000010 */
/*08f0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0900*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0910*/ IMAD.WIDE R28, R27, 0x8, R24 ; /* 0x000000081b1c7825 */
/* 0x000fe200078e0218 */
/*0920*/ IADD3 R5, R5, 0x8, RZ ; /* 0x0000000805057810 */
/* 0x000fe40007ffe0ff */
/*0930*/ IADD3 R4, R4, -0x8, RZ ; /* 0xfffffff804047810 */
/* 0x000fe20007ffe0ff */
/*0940*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0950*/ DFMA R8, R10, R12, R8 ; /* 0x0000000c0a08722b */
/* 0x004ecc0000000008 */
/*0960*/ DFMA R18, R20, R18, R8 ; /* 0x000000121412722b */
/* 0x0080480000000008 */
/*0970*/ ISETP.NE.OR P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0000705670 */
/*0980*/ @!P0 BRA 0xb30 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0990*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fe20008000f00 */
/*09a0*/ IMAD.U32 R6, RZ, RZ, UR6 ; /* 0x00000006ff067e24 */
/* 0x000fe2000f8e00ff */
/*09b0*/ LDG.E.64 R8, [R28.64] ; /* 0x000000041c087981 */
/* 0x001ea6000c1e1b00 */
/*09c0*/ IMAD.WIDE R6, R26, 0x8, R6 ; /* 0x000000081a067825 */
/* 0x000fca00078e0206 */
/*09d0*/ LDG.E.64 R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x000ea2000c1e1b00 */
/*09e0*/ MOV R27, c[0x0][0x184] ; /* 0x00006100001b7a02 */
/* 0x000fc60000000f00 */
/*09f0*/ LDG.E.64 R12, [R6.64+0x8] ; /* 0x00000804060c7981 */
/* 0x000ee4000c1e1b00 */
/*0a00*/ IMAD.WIDE R24, R27.reuse, 0x8, R28 ; /* 0x000000081b187825 */
/* 0x040fe400078e021c */
/*0a10*/ LDG.E.64 R16, [R6.64+0x10] ; /* 0x0000100406107981 */
/* 0x000f28000c1e1b00 */
/*0a20*/ LDG.E.64 R22, [R24.64] ; /* 0x0000000418167981 */
/* 0x0000e4000c1e1b00 */
/*0a30*/ IMAD.WIDE R24, R27, 0x8, R24 ; /* 0x000000081b187825 */
/* 0x001fca00078e0218 */
/*0a40*/ LDG.E.64 R14, [R24.64] ; /* 0x00000004180e7981 */
/* 0x000f22000c1e1b00 */
/*0a50*/ IMAD.WIDE R20, R27, 0x8, R24 ; /* 0x000000081b147825 */
/* 0x000fe200078e0218 */
/*0a60*/ DFMA R8, R8, R10, R18 ; /* 0x0000000a0808722b */
/* 0x0060e40000000012 */
/*0a70*/ LDG.E.64 R18, [R6.64+0x18] ; /* 0x0000180406127981 */
/* 0x001ea8000c1e1b00 */
/*0a80*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000ea2000c1e1b00 */
/*0a90*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fc80007ffe0ff */
/*0aa0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0ab0*/ DFMA R8, R22, R12, R8 ; /* 0x0000000c1608722b */
/* 0x008f220000000008 */
/*0ac0*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0ad0*/ IMAD.WIDE R28, R27, 0x8, R20 ; /* 0x000000081b1c7825 */
/* 0x000fc600078e0214 */
/*0ae0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0af0*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fe20007ffe0ff */
/*0b00*/ DFMA R8, R14, R16, R8 ; /* 0x000000100e08722b */
/* 0x010e8c0000000008 */
/*0b10*/ DFMA R18, R10, R18, R8 ; /* 0x000000120a12722b */
/* 0x0040640000000008 */
/*0b20*/ @P0 BRA 0x990 ; /* 0xfffffe6000000947 */
/* 0x003fea000383ffff */
/*0b30*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*0b40*/ @!P0 BRA 0xc80 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0b50*/ MOV R7, 0x8 ; /* 0x0000000800077802 */
/* 0x000fe20000000f00 */
/*0b60*/ IMAD R4, R3, c[0x0][0x180], R5 ; /* 0x0000600003047a24 */
/* 0x000fe400078e0205 */
/*0b70*/ IMAD R6, R5, c[0x0][0x184], R0 ; /* 0x0000610005067a24 */
/* 0x000fe400078e0200 */
/*0b80*/ IMAD.WIDE R4, R4, R7, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0207 */
/*0b90*/ IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fe200078e0207 */
/*0ba0*/ MOV R10, R4 ; /* 0x00000004000a7202 */
/* 0x000fc60000000f00 */
/*0bb0*/ IMAD.MOV.U32 R11, RZ, RZ, R5 ; /* 0x000000ffff0b7224 */
/* 0x000fc600078e0005 */
/*0bc0*/ MOV R8, R10 ; /* 0x0000000a00087202 */
/* 0x001fe20000000f00 */
/*0bd0*/ LDG.E.64 R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0000a2000c1e1b00 */
/*0be0*/ MOV R9, R11 ; /* 0x0000000b00097202 */
/* 0x000fcc0000000f00 */
/*0bf0*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1b00 */
/*0c00*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fc80007ffe0ff */
/*0c10*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f05270 */
/*0c20*/ MOV R13, c[0x0][0x184] ; /* 0x00006100000d7a02 */
/* 0x000fe40000000f00 */
/*0c30*/ IADD3 R10, P1, R10, 0x8, RZ ; /* 0x000000080a0a7810 */
/* 0x000fc60007f3e0ff */
/*0c40*/ IMAD.WIDE R6, R13, 0x8, R6 ; /* 0x000000080d067825 */
/* 0x001fe200078e0206 */
/*0c50*/ IADD3.X R11, RZ, R11, RZ, P1, !PT ; /* 0x0000000bff0b7210 */
/* 0x000fe20000ffe4ff */
/*0c60*/ DFMA R18, R4, R8, R18 ; /* 0x000000080412722b */
/* 0x0060480000000012 */
/*0c70*/ @P0 BRA 0xbc0 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*0c80*/ MOV R2, 0x8 ; /* 0x0000000800027802 */
/* 0x000fe20000000f00 */
/*0c90*/ IMAD R3, R3, c[0x0][0x184], R0 ; /* 0x0000610003037a24 */
/* 0x000fc800078e0200 */
/*0ca0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0cb0*/ STG.E.64 [R2.64], R18 ; /* 0x0000001202007986 */
/* 0x002fe2000c101b04 */
/*0cc0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0cd0*/ BRA 0xcd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include "cuda_runtime.h"
//#include "cuda_profiler_api.h"
#define THREADS 32 //In each block THREADS*THREADS threads
struct matrix {
int ncols;
int nrows;
double* mat;
};
void readMatrix(struct matrix* m, FILE* file);
void printMatrix(struct matrix* m, FILE* file);
__global__ void matrixMul(double *d_m1, double *d_m2, double *d_m3, int row1, int row2, int col1, int col2);
/*
* The file which contains a matrix has in its first row the dimensions
* then using fscanf each element of the matrix is stored on the memory allocated dynamically
*/
void readMatrix(struct matrix* m, FILE* file) {
int i, j;
m->mat = (double*)malloc(m->ncols * m->nrows * sizeof(double));
for (i = 0; i < m->nrows; i++) {
for (j = 0; j < m->ncols; j++) {
fscanf(file, "%lf", &m->mat[i * m->ncols + j]);
}
}
}
/* The opposite operation of readMatrix. Stores a matrix into a file, element by element */
void printMatrix(struct matrix* m, FILE* file) {
int i, j;
for (i = 0; i < m->nrows; i++) {
for (j = 0; j < m->ncols; j++) {
fprintf(file, "%lf ", m->mat[i * m->ncols + j]);
}
fprintf(file, "\n");
}
}
/*
* Performs the multiplication operation between the matrices m1 and m2.
* The result will be stored in the matrix m3.
* The algorithm is practically the one that can be found here: https://en.wikipedia.org/wiki/Matrix_multiplication#Definition
* The grid is sized in a 2D way as each blocks whose dimension is THREADSxTHREADS, this helps in associating to a single thread and element of the result matrix to which calcutate a summation exploiting the numerous core of a GPU.
*/
__global__ void matrixMul(double *d_m1, double *d_m2, double *d_m3, int row1, int row2, int col1, int col2){
//coordinates of each thread inside the grind and so inside a block
int i = blockIdx.y*blockDim.y+threadIdx.y;
int j = blockIdx.x*blockDim.x+threadIdx.x;
double sum = 0;
int k;
//the two previous for cycle are substituted by the matrix of threads
if ((i < row1) && (j < col2)){
for(k = 0; k<col1; k++){
sum += d_m1[i*col1+k]*d_m2[k*col2+j];
}
d_m3[i*col2+j]=sum;
}
}
int main(int argc, char* argv[]) {
if(argc != 3){ //1- exe name, 2- mat1.txt, 3- mat2.txt
printf("Parameter error.\n");
exit(1);
}
FILE *mat1, *mat2, *resultFile;
clock_t t;
struct matrix m1, m2, m3;
mat1 = fopen(argv[1], "r");
mat2 = fopen(argv[2], "r");
fscanf(mat1, "%d %d", &m1.nrows, &m1.ncols);
fscanf(mat2, "%d %d", &m2.nrows, &m2.ncols);
/* Multiplication is permitted if m1 is m x n and m2 is n x p, m1 must have the same number of column of the rows of m2 matrix */
if(m1.ncols != m2.nrows){
printf("It is not possible to do matrix multiplication. Check matrices number of rows and cols.\n");
fclose(mat1);
fclose(mat2);
exit(1);
}
readMatrix(&m1, mat1);
readMatrix(&m2, mat2);
//M3 initilization
m3.nrows=m1.nrows;
m3.ncols=m2.ncols;
m3.mat = (double*)malloc(m3.ncols * m3.nrows * sizeof(double));
//cudaProfilerStart();
/* Device variable, allocations, and transfers */
double *d_m1, *d_m2, *d_m3;
cudaMalloc((void**)&d_m1, m1.nrows*m1.ncols*sizeof(double));
cudaMalloc((void**)&d_m2, m2.nrows*m2.ncols*sizeof(double));
cudaMalloc((void**)&d_m3, m3.nrows*m3.ncols*sizeof(double));
cudaMemcpy(d_m1, m1.mat, m1.nrows*m1.ncols * sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(d_m2, m2.mat, m2.nrows*m2.ncols * sizeof(double), cudaMemcpyHostToDevice);
cudaMemset(d_m3, 0, m3.nrows*m3.ncols*sizeof(double));
dim3 dimBlock(THREADS, THREADS); //each block is THREADxTHREAD
dim3 dimGrid((m2.ncols+dimBlock.x-1)/dimBlock.x, (m1.nrows+dimBlock.y-1)/dimBlock.y); //the grid is allocated so the necessary amount of blocks are initialized
t = clock();
matrixMul <<<dimGrid, dimBlock>>>(d_m1, d_m2, d_m3, m1.nrows, m2.nrows, m1.ncols, m2.ncols);
cudaDeviceSynchronize();
t = clock() - t; //total time spent in matrixMul (wall clock time)
cudaMemcpy(m3.mat, d_m3, m3.nrows*m3.ncols * sizeof(double), cudaMemcpyDeviceToHost);
//cudaProfilerStop();
resultFile = fopen("result.txt", "w");
printMatrix(&m3, resultFile);
printf("Elapsed time: %.5lf seconds\n", ((double)t)/CLOCKS_PER_SEC);
fclose(mat1);
fclose(mat2);
fclose(resultFile);
cudaFree(d_m1);
cudaFree(d_m2);
cudaFree(d_m3);
free(m1.mat);
free(m2.mat);
free(m3.mat);
return 0;
} | .file "tmpxft_00043dab_00000000-6_mat_mul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%lf"
.text
.globl _Z10readMatrixP6matrixP8_IO_FILE
.type _Z10readMatrixP6matrixP8_IO_FILE, @function
_Z10readMatrixP6matrixP8_IO_FILE:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %rbp
movq %rsi, %r13
movl 4(%rdi), %ebx
movl %ebx, %edi
imull 0(%rbp), %edi
movslq %edi, %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, 8(%rbp)
movl $0, %r12d
leaq .LC0(%rip), %r14
testl %ebx, %ebx
jg .L4
.L3:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
imull %r12d, %eax
addl %ebx, %eax
cltq
movq 8(%rbp), %rdx
leaq (%rdx,%rax,8), %rdx
movq %r14, %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addl $1, %ebx
movl 0(%rbp), %eax
cmpl %ebx, %eax
jg .L6
.L7:
addl $1, %r12d
cmpl %r12d, 4(%rbp)
jle .L3
.L4:
movl 0(%rbp), %eax
movl $0, %ebx
testl %eax, %eax
jg .L6
jmp .L7
.cfi_endproc
.LFE2057:
.size _Z10readMatrixP6matrixP8_IO_FILE, .-_Z10readMatrixP6matrixP8_IO_FILE
.section .rodata.str1.1
.LC1:
.string "%lf "
.LC2:
.string "\n"
.text
.globl _Z11printMatrixP6matrixP8_IO_FILE
.type _Z11printMatrixP6matrixP8_IO_FILE, @function
_Z11printMatrixP6matrixP8_IO_FILE:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movq %rsi, %r13
movl $0, %r12d
leaq .LC1(%rip), %r14
leaq .LC2(%rip), %r15
cmpl $0, 4(%rdi)
jg .L15
.L14:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
imull %r12d, %eax
addl %ebx, %eax
cltq
movq 8(%rbp), %rdx
movsd (%rdx,%rax,8), %xmm0
movq %r14, %rdx
movl $2, %esi
movq %r13, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addl $1, %ebx
movl 0(%rbp), %eax
cmpl %ebx, %eax
jg .L17
.L18:
movq %r15, %rdx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, %r12d
cmpl %r12d, 4(%rbp)
jle .L14
.L15:
movl 0(%rbp), %eax
movl $0, %ebx
testl %eax, %eax
jg .L17
jmp .L18
.cfi_endproc
.LFE2058:
.size _Z11printMatrixP6matrixP8_IO_FILE, .-_Z11printMatrixP6matrixP8_IO_FILE
.globl _Z36__device_stub__Z9matrixMulPdS_S_iiiiPdS_S_iiii
.type _Z36__device_stub__Z9matrixMulPdS_S_iiiiPdS_S_iiii, @function
_Z36__device_stub__Z9matrixMulPdS_S_iiiiPdS_S_iiii:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9matrixMulPdS_S_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z36__device_stub__Z9matrixMulPdS_S_iiiiPdS_S_iiii, .-_Z36__device_stub__Z9matrixMulPdS_S_iiiiPdS_S_iiii
.globl _Z9matrixMulPdS_S_iiii
.type _Z9matrixMulPdS_S_iiii, @function
_Z9matrixMulPdS_S_iiii:
.LFB2085:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z36__device_stub__Z9matrixMulPdS_S_iiiiPdS_S_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z9matrixMulPdS_S_iiii, .-_Z9matrixMulPdS_S_iiii
.section .rodata.str1.1
.LC3:
.string "Parameter error.\n"
.LC4:
.string "r"
.LC5:
.string "%d %d"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "It is not possible to do matrix multiplication. Check matrices number of rows and cols.\n"
.section .rodata.str1.1
.LC7:
.string "w"
.LC8:
.string "result.txt"
.LC10:
.string "Elapsed time: %.5lf seconds\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
cmpl $3, %edi
jne .L39
movq %rsi, %rbx
movq 8(%rsi), %rdi
leaq .LC4(%rip), %rbp
movq %rbp, %rsi
call fopen@PLT
movq %rax, %r13
movq 16(%rbx), %rdi
movq %rbp, %rsi
call fopen@PLT
movq %rax, %r12
leaq 48(%rsp), %rcx
leaq 52(%rsp), %rdx
leaq .LC5(%rip), %rbx
movq %rbx, %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
leaq 64(%rsp), %rcx
leaq 68(%rsp), %rdx
movq %rbx, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 68(%rsp), %eax
cmpl %eax, 48(%rsp)
jne .L40
leaq 48(%rsp), %rdi
movq %r13, %rsi
call _Z10readMatrixP6matrixP8_IO_FILE
leaq 64(%rsp), %rdi
movq %r12, %rsi
call _Z10readMatrixP6matrixP8_IO_FILE
movl 52(%rsp), %ebp
movl %ebp, 84(%rsp)
movl 64(%rsp), %ebx
movl %ebx, 80(%rsp)
imull %ebp, %ebx
movslq %ebx, %rbx
salq $3, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rax, 88(%rsp)
imull 48(%rsp), %ebp
movslq %ebp, %rsi
salq $3, %rsi
movq %rsp, %rdi
call cudaMalloc@PLT
movl 68(%rsp), %esi
imull 64(%rsp), %esi
movslq %esi, %rsi
salq $3, %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl 52(%rsp), %edx
imull 48(%rsp), %edx
movslq %edx, %rdx
salq $3, %rdx
movl $1, %ecx
movq 56(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl 68(%rsp), %edx
imull 64(%rsp), %edx
movslq %edx, %rdx
salq $3, %rdx
movl $1, %ecx
movq 72(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movq %rbx, %rdx
movl $0, %esi
movq 16(%rsp), %rdi
call cudaMemset@PLT
movl $1, 32(%rsp)
movl 52(%rsp), %eax
addl $31, %eax
shrl $5, %eax
movl 64(%rsp), %ecx
leal 31(%rcx), %edx
shrl $5, %edx
movl %edx, 36(%rsp)
movl %eax, 40(%rsp)
movl $1, 44(%rsp)
call clock@PLT
movq %rax, %r15
movl $32, 24(%rsp)
movl $32, 28(%rsp)
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L36:
call cudaDeviceSynchronize@PLT
call clock@PLT
subq %r15, %rax
movq %rax, %rbp
movl $2, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq .LC7(%rip), %rsi
leaq .LC8(%rip), %rdi
call fopen@PLT
movq %rax, %rbx
leaq 80(%rsp), %rdi
movq %rax, %rsi
call _Z11printMatrixP6matrixP8_IO_FILE
pxor %xmm0, %xmm0
cvtsi2sdq %rbp, %xmm0
divsd .LC9(%rip), %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r13, %rdi
call fclose@PLT
movq %r12, %rdi
call fclose@PLT
movq %rbx, %rdi
call fclose@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call free@PLT
movq 72(%rsp), %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L42
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L40:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call fclose@PLT
movq %r12, %rdi
call fclose@PLT
movl $1, %edi
call exit@PLT
.L41:
subq $8, %rsp
.cfi_def_cfa_offset 184
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 192
movl 64(%rsp), %r9d
movl 84(%rsp), %r8d
movl 68(%rsp), %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z36__device_stub__Z9matrixMulPdS_S_iiiiPdS_S_iiii
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L36
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z9matrixMulPdS_S_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z9matrixMulPdS_S_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC9:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include "cuda_runtime.h"
//#include "cuda_profiler_api.h"
#define THREADS 32 //In each block THREADS*THREADS threads
struct matrix {
int ncols;
int nrows;
double* mat;
};
void readMatrix(struct matrix* m, FILE* file);
void printMatrix(struct matrix* m, FILE* file);
__global__ void matrixMul(double *d_m1, double *d_m2, double *d_m3, int row1, int row2, int col1, int col2);
/*
* The file which contains a matrix has in its first row the dimensions
* then using fscanf each element of the matrix is stored on the memory allocated dynamically
*/
void readMatrix(struct matrix* m, FILE* file) {
int i, j;
m->mat = (double*)malloc(m->ncols * m->nrows * sizeof(double));
for (i = 0; i < m->nrows; i++) {
for (j = 0; j < m->ncols; j++) {
fscanf(file, "%lf", &m->mat[i * m->ncols + j]);
}
}
}
/* The opposite operation of readMatrix. Stores a matrix into a file, element by element */
void printMatrix(struct matrix* m, FILE* file) {
int i, j;
for (i = 0; i < m->nrows; i++) {
for (j = 0; j < m->ncols; j++) {
fprintf(file, "%lf ", m->mat[i * m->ncols + j]);
}
fprintf(file, "\n");
}
}
/*
* Performs the multiplication operation between the matrices m1 and m2.
* The result will be stored in the matrix m3.
* The algorithm is practically the one that can be found here: https://en.wikipedia.org/wiki/Matrix_multiplication#Definition
* The grid is sized in a 2D way as each blocks whose dimension is THREADSxTHREADS, this helps in associating to a single thread and element of the result matrix to which calcutate a summation exploiting the numerous core of a GPU.
*/
__global__ void matrixMul(double *d_m1, double *d_m2, double *d_m3, int row1, int row2, int col1, int col2){
//coordinates of each thread inside the grind and so inside a block
int i = blockIdx.y*blockDim.y+threadIdx.y;
int j = blockIdx.x*blockDim.x+threadIdx.x;
double sum = 0;
int k;
//the two previous for cycle are substituted by the matrix of threads
if ((i < row1) && (j < col2)){
for(k = 0; k<col1; k++){
sum += d_m1[i*col1+k]*d_m2[k*col2+j];
}
d_m3[i*col2+j]=sum;
}
}
int main(int argc, char* argv[]) {
if(argc != 3){ //1- exe name, 2- mat1.txt, 3- mat2.txt
printf("Parameter error.\n");
exit(1);
}
FILE *mat1, *mat2, *resultFile;
clock_t t;
struct matrix m1, m2, m3;
mat1 = fopen(argv[1], "r");
mat2 = fopen(argv[2], "r");
fscanf(mat1, "%d %d", &m1.nrows, &m1.ncols);
fscanf(mat2, "%d %d", &m2.nrows, &m2.ncols);
/* Multiplication is permitted if m1 is m x n and m2 is n x p, m1 must have the same number of column of the rows of m2 matrix */
if(m1.ncols != m2.nrows){
printf("It is not possible to do matrix multiplication. Check matrices number of rows and cols.\n");
fclose(mat1);
fclose(mat2);
exit(1);
}
readMatrix(&m1, mat1);
readMatrix(&m2, mat2);
//M3 initilization
m3.nrows=m1.nrows;
m3.ncols=m2.ncols;
m3.mat = (double*)malloc(m3.ncols * m3.nrows * sizeof(double));
//cudaProfilerStart();
/* Device variable, allocations, and transfers */
double *d_m1, *d_m2, *d_m3;
cudaMalloc((void**)&d_m1, m1.nrows*m1.ncols*sizeof(double));
cudaMalloc((void**)&d_m2, m2.nrows*m2.ncols*sizeof(double));
cudaMalloc((void**)&d_m3, m3.nrows*m3.ncols*sizeof(double));
cudaMemcpy(d_m1, m1.mat, m1.nrows*m1.ncols * sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(d_m2, m2.mat, m2.nrows*m2.ncols * sizeof(double), cudaMemcpyHostToDevice);
cudaMemset(d_m3, 0, m3.nrows*m3.ncols*sizeof(double));
dim3 dimBlock(THREADS, THREADS); //each block is THREADxTHREAD
dim3 dimGrid((m2.ncols+dimBlock.x-1)/dimBlock.x, (m1.nrows+dimBlock.y-1)/dimBlock.y); //the grid is allocated so the necessary amount of blocks are initialized
t = clock();
matrixMul <<<dimGrid, dimBlock>>>(d_m1, d_m2, d_m3, m1.nrows, m2.nrows, m1.ncols, m2.ncols);
cudaDeviceSynchronize();
t = clock() - t; //total time spent in matrixMul (wall clock time)
cudaMemcpy(m3.mat, d_m3, m3.nrows*m3.ncols * sizeof(double), cudaMemcpyDeviceToHost);
//cudaProfilerStop();
resultFile = fopen("result.txt", "w");
printMatrix(&m3, resultFile);
printf("Elapsed time: %.5lf seconds\n", ((double)t)/CLOCKS_PER_SEC);
fclose(mat1);
fclose(mat2);
fclose(resultFile);
cudaFree(d_m1);
cudaFree(d_m2);
cudaFree(d_m3);
free(m1.mat);
free(m2.mat);
free(m3.mat);
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include "hip/hip_runtime.h"
//#include "cuda_profiler_api.h"
#define THREADS 32 //In each block THREADS*THREADS threads
struct matrix {
int ncols;
int nrows;
double* mat;
};
void readMatrix(struct matrix* m, FILE* file);
void printMatrix(struct matrix* m, FILE* file);
__global__ void matrixMul(double *d_m1, double *d_m2, double *d_m3, int row1, int row2, int col1, int col2);
/*
* The file which contains a matrix has in its first row the dimensions
* then using fscanf each element of the matrix is stored on the memory allocated dynamically
*/
void readMatrix(struct matrix* m, FILE* file) {
int i, j;
m->mat = (double*)malloc(m->ncols * m->nrows * sizeof(double));
for (i = 0; i < m->nrows; i++) {
for (j = 0; j < m->ncols; j++) {
fscanf(file, "%lf", &m->mat[i * m->ncols + j]);
}
}
}
/* The opposite operation of readMatrix. Stores a matrix into a file, element by element */
void printMatrix(struct matrix* m, FILE* file) {
int i, j;
for (i = 0; i < m->nrows; i++) {
for (j = 0; j < m->ncols; j++) {
fprintf(file, "%lf ", m->mat[i * m->ncols + j]);
}
fprintf(file, "\n");
}
}
/*
* Performs the multiplication operation between the matrices m1 and m2.
* The result will be stored in the matrix m3.
* The algorithm is practically the one that can be found here: https://en.wikipedia.org/wiki/Matrix_multiplication#Definition
* The grid is sized in a 2D way as each blocks whose dimension is THREADSxTHREADS, this helps in associating to a single thread and element of the result matrix to which calcutate a summation exploiting the numerous core of a GPU.
*/
__global__ void matrixMul(double *d_m1, double *d_m2, double *d_m3, int row1, int row2, int col1, int col2){
//coordinates of each thread inside the grind and so inside a block
int i = blockIdx.y*blockDim.y+threadIdx.y;
int j = blockIdx.x*blockDim.x+threadIdx.x;
double sum = 0;
int k;
//the two previous for cycle are substituted by the matrix of threads
if ((i < row1) && (j < col2)){
for(k = 0; k<col1; k++){
sum += d_m1[i*col1+k]*d_m2[k*col2+j];
}
d_m3[i*col2+j]=sum;
}
}
int main(int argc, char* argv[]) {
if(argc != 3){ //1- exe name, 2- mat1.txt, 3- mat2.txt
printf("Parameter error.\n");
exit(1);
}
FILE *mat1, *mat2, *resultFile;
clock_t t;
struct matrix m1, m2, m3;
mat1 = fopen(argv[1], "r");
mat2 = fopen(argv[2], "r");
fscanf(mat1, "%d %d", &m1.nrows, &m1.ncols);
fscanf(mat2, "%d %d", &m2.nrows, &m2.ncols);
/* Multiplication is permitted if m1 is m x n and m2 is n x p, m1 must have the same number of column of the rows of m2 matrix */
if(m1.ncols != m2.nrows){
printf("It is not possible to do matrix multiplication. Check matrices number of rows and cols.\n");
fclose(mat1);
fclose(mat2);
exit(1);
}
readMatrix(&m1, mat1);
readMatrix(&m2, mat2);
//M3 initilization
m3.nrows=m1.nrows;
m3.ncols=m2.ncols;
m3.mat = (double*)malloc(m3.ncols * m3.nrows * sizeof(double));
//cudaProfilerStart();
/* Device variable, allocations, and transfers */
double *d_m1, *d_m2, *d_m3;
hipMalloc((void**)&d_m1, m1.nrows*m1.ncols*sizeof(double));
hipMalloc((void**)&d_m2, m2.nrows*m2.ncols*sizeof(double));
hipMalloc((void**)&d_m3, m3.nrows*m3.ncols*sizeof(double));
hipMemcpy(d_m1, m1.mat, m1.nrows*m1.ncols * sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(d_m2, m2.mat, m2.nrows*m2.ncols * sizeof(double), hipMemcpyHostToDevice);
hipMemset(d_m3, 0, m3.nrows*m3.ncols*sizeof(double));
dim3 dimBlock(THREADS, THREADS); //each block is THREADxTHREAD
dim3 dimGrid((m2.ncols+dimBlock.x-1)/dimBlock.x, (m1.nrows+dimBlock.y-1)/dimBlock.y); //the grid is allocated so the necessary amount of blocks are initialized
t = clock();
matrixMul <<<dimGrid, dimBlock>>>(d_m1, d_m2, d_m3, m1.nrows, m2.nrows, m1.ncols, m2.ncols);
hipDeviceSynchronize();
t = clock() - t; //total time spent in matrixMul (wall clock time)
hipMemcpy(m3.mat, d_m3, m3.nrows*m3.ncols * sizeof(double), hipMemcpyDeviceToHost);
//cudaProfilerStop();
resultFile = fopen("result.txt", "w");
printMatrix(&m3, resultFile);
printf("Elapsed time: %.5lf seconds\n", ((double)t)/CLOCKS_PER_SEC);
fclose(mat1);
fclose(mat2);
fclose(resultFile);
hipFree(d_m1);
hipFree(d_m2);
hipFree(d_m3);
free(m1.mat);
free(m2.mat);
free(m3.mat);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include "hip/hip_runtime.h"
//#include "cuda_profiler_api.h"
#define THREADS 32 //In each block THREADS*THREADS threads
struct matrix {
int ncols;
int nrows;
double* mat;
};
void readMatrix(struct matrix* m, FILE* file);
void printMatrix(struct matrix* m, FILE* file);
__global__ void matrixMul(double *d_m1, double *d_m2, double *d_m3, int row1, int row2, int col1, int col2);
/*
* The file which contains a matrix has in its first row the dimensions
* then using fscanf each element of the matrix is stored on the memory allocated dynamically
*/
void readMatrix(struct matrix* m, FILE* file) {
int i, j;
m->mat = (double*)malloc(m->ncols * m->nrows * sizeof(double));
for (i = 0; i < m->nrows; i++) {
for (j = 0; j < m->ncols; j++) {
fscanf(file, "%lf", &m->mat[i * m->ncols + j]);
}
}
}
/* The opposite operation of readMatrix. Stores a matrix into a file, element by element */
void printMatrix(struct matrix* m, FILE* file) {
int i, j;
for (i = 0; i < m->nrows; i++) {
for (j = 0; j < m->ncols; j++) {
fprintf(file, "%lf ", m->mat[i * m->ncols + j]);
}
fprintf(file, "\n");
}
}
/*
* Performs the multiplication operation between the matrices m1 and m2.
* The result will be stored in the matrix m3.
* The algorithm is practically the one that can be found here: https://en.wikipedia.org/wiki/Matrix_multiplication#Definition
* The grid is sized in a 2D way as each blocks whose dimension is THREADSxTHREADS, this helps in associating to a single thread and element of the result matrix to which calcutate a summation exploiting the numerous core of a GPU.
*/
__global__ void matrixMul(double *d_m1, double *d_m2, double *d_m3, int row1, int row2, int col1, int col2){
//coordinates of each thread inside the grind and so inside a block
int i = blockIdx.y*blockDim.y+threadIdx.y;
int j = blockIdx.x*blockDim.x+threadIdx.x;
double sum = 0;
int k;
//the two previous for cycle are substituted by the matrix of threads
if ((i < row1) && (j < col2)){
for(k = 0; k<col1; k++){
sum += d_m1[i*col1+k]*d_m2[k*col2+j];
}
d_m3[i*col2+j]=sum;
}
}
int main(int argc, char* argv[]) {
if(argc != 3){ //1- exe name, 2- mat1.txt, 3- mat2.txt
printf("Parameter error.\n");
exit(1);
}
FILE *mat1, *mat2, *resultFile;
clock_t t;
struct matrix m1, m2, m3;
mat1 = fopen(argv[1], "r");
mat2 = fopen(argv[2], "r");
fscanf(mat1, "%d %d", &m1.nrows, &m1.ncols);
fscanf(mat2, "%d %d", &m2.nrows, &m2.ncols);
/* Multiplication is permitted if m1 is m x n and m2 is n x p, m1 must have the same number of column of the rows of m2 matrix */
if(m1.ncols != m2.nrows){
printf("It is not possible to do matrix multiplication. Check matrices number of rows and cols.\n");
fclose(mat1);
fclose(mat2);
exit(1);
}
readMatrix(&m1, mat1);
readMatrix(&m2, mat2);
//M3 initilization
m3.nrows=m1.nrows;
m3.ncols=m2.ncols;
m3.mat = (double*)malloc(m3.ncols * m3.nrows * sizeof(double));
//cudaProfilerStart();
/* Device variable, allocations, and transfers */
double *d_m1, *d_m2, *d_m3;
hipMalloc((void**)&d_m1, m1.nrows*m1.ncols*sizeof(double));
hipMalloc((void**)&d_m2, m2.nrows*m2.ncols*sizeof(double));
hipMalloc((void**)&d_m3, m3.nrows*m3.ncols*sizeof(double));
hipMemcpy(d_m1, m1.mat, m1.nrows*m1.ncols * sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(d_m2, m2.mat, m2.nrows*m2.ncols * sizeof(double), hipMemcpyHostToDevice);
hipMemset(d_m3, 0, m3.nrows*m3.ncols*sizeof(double));
dim3 dimBlock(THREADS, THREADS); //each block is THREADxTHREAD
dim3 dimGrid((m2.ncols+dimBlock.x-1)/dimBlock.x, (m1.nrows+dimBlock.y-1)/dimBlock.y); //the grid is allocated so the necessary amount of blocks are initialized
t = clock();
matrixMul <<<dimGrid, dimBlock>>>(d_m1, d_m2, d_m3, m1.nrows, m2.nrows, m1.ncols, m2.ncols);
hipDeviceSynchronize();
t = clock() - t; //total time spent in matrixMul (wall clock time)
hipMemcpy(m3.mat, d_m3, m3.nrows*m3.ncols * sizeof(double), hipMemcpyDeviceToHost);
//cudaProfilerStop();
resultFile = fopen("result.txt", "w");
printMatrix(&m3, resultFile);
printf("Elapsed time: %.5lf seconds\n", ((double)t)/CLOCKS_PER_SEC);
fclose(mat1);
fclose(mat2);
fclose(resultFile);
hipFree(d_m1);
hipFree(d_m2);
hipFree(d_m3);
free(m1.mat);
free(m2.mat);
free(m3.mat);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9matrixMulPdS_S_iiii
.globl _Z9matrixMulPdS_S_iiii
.p2align 8
.type _Z9matrixMulPdS_S_iiii,@function
_Z9matrixMulPdS_S_iiii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s4, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x24
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v6, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 3, v[2:3]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v7, 31, v6
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s2, 0
v_lshlrev_b64 v[7:8], 3, v[6:7]
v_add_nc_u32_e32 v6, s3, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b64 v[9:10], v[4:5], off
global_load_b64 v[7:8], v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 8
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[9:10], v[7:8], v[2:3]
s_cbranch_scc1 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v0, s3, v[1:2]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9matrixMulPdS_S_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9matrixMulPdS_S_iiii, .Lfunc_end0-_Z9matrixMulPdS_S_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9matrixMulPdS_S_iiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9matrixMulPdS_S_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include "hip/hip_runtime.h"
//#include "cuda_profiler_api.h"
#define THREADS 32 //In each block THREADS*THREADS threads
struct matrix {
int ncols;
int nrows;
double* mat;
};
void readMatrix(struct matrix* m, FILE* file);
void printMatrix(struct matrix* m, FILE* file);
__global__ void matrixMul(double *d_m1, double *d_m2, double *d_m3, int row1, int row2, int col1, int col2);
/*
* The file which contains a matrix has in its first row the dimensions
* then using fscanf each element of the matrix is stored on the memory allocated dynamically
*/
void readMatrix(struct matrix* m, FILE* file) {
int i, j;
m->mat = (double*)malloc(m->ncols * m->nrows * sizeof(double));
for (i = 0; i < m->nrows; i++) {
for (j = 0; j < m->ncols; j++) {
fscanf(file, "%lf", &m->mat[i * m->ncols + j]);
}
}
}
/* The opposite operation of readMatrix. Stores a matrix into a file, element by element */
void printMatrix(struct matrix* m, FILE* file) {
int i, j;
for (i = 0; i < m->nrows; i++) {
for (j = 0; j < m->ncols; j++) {
fprintf(file, "%lf ", m->mat[i * m->ncols + j]);
}
fprintf(file, "\n");
}
}
/*
* Performs the multiplication operation between the matrices m1 and m2.
* The result will be stored in the matrix m3.
* The algorithm is practically the one that can be found here: https://en.wikipedia.org/wiki/Matrix_multiplication#Definition
* The grid is sized in a 2D way as each blocks whose dimension is THREADSxTHREADS, this helps in associating to a single thread and element of the result matrix to which calcutate a summation exploiting the numerous core of a GPU.
*/
__global__ void matrixMul(double *d_m1, double *d_m2, double *d_m3, int row1, int row2, int col1, int col2){
//coordinates of each thread inside the grind and so inside a block
int i = blockIdx.y*blockDim.y+threadIdx.y;
int j = blockIdx.x*blockDim.x+threadIdx.x;
double sum = 0;
int k;
//the two previous for cycle are substituted by the matrix of threads
if ((i < row1) && (j < col2)){
for(k = 0; k<col1; k++){
sum += d_m1[i*col1+k]*d_m2[k*col2+j];
}
d_m3[i*col2+j]=sum;
}
}
int main(int argc, char* argv[]) {
if(argc != 3){ //1- exe name, 2- mat1.txt, 3- mat2.txt
printf("Parameter error.\n");
exit(1);
}
FILE *mat1, *mat2, *resultFile;
clock_t t;
struct matrix m1, m2, m3;
mat1 = fopen(argv[1], "r");
mat2 = fopen(argv[2], "r");
fscanf(mat1, "%d %d", &m1.nrows, &m1.ncols);
fscanf(mat2, "%d %d", &m2.nrows, &m2.ncols);
/* Multiplication is permitted if m1 is m x n and m2 is n x p, m1 must have the same number of column of the rows of m2 matrix */
if(m1.ncols != m2.nrows){
printf("It is not possible to do matrix multiplication. Check matrices number of rows and cols.\n");
fclose(mat1);
fclose(mat2);
exit(1);
}
readMatrix(&m1, mat1);
readMatrix(&m2, mat2);
//M3 initilization
m3.nrows=m1.nrows;
m3.ncols=m2.ncols;
m3.mat = (double*)malloc(m3.ncols * m3.nrows * sizeof(double));
//cudaProfilerStart();
/* Device variable, allocations, and transfers */
double *d_m1, *d_m2, *d_m3;
hipMalloc((void**)&d_m1, m1.nrows*m1.ncols*sizeof(double));
hipMalloc((void**)&d_m2, m2.nrows*m2.ncols*sizeof(double));
hipMalloc((void**)&d_m3, m3.nrows*m3.ncols*sizeof(double));
hipMemcpy(d_m1, m1.mat, m1.nrows*m1.ncols * sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(d_m2, m2.mat, m2.nrows*m2.ncols * sizeof(double), hipMemcpyHostToDevice);
hipMemset(d_m3, 0, m3.nrows*m3.ncols*sizeof(double));
dim3 dimBlock(THREADS, THREADS); //each block is THREADxTHREAD
dim3 dimGrid((m2.ncols+dimBlock.x-1)/dimBlock.x, (m1.nrows+dimBlock.y-1)/dimBlock.y); //the grid is allocated so the necessary amount of blocks are initialized
t = clock();
matrixMul <<<dimGrid, dimBlock>>>(d_m1, d_m2, d_m3, m1.nrows, m2.nrows, m1.ncols, m2.ncols);
hipDeviceSynchronize();
t = clock() - t; //total time spent in matrixMul (wall clock time)
hipMemcpy(m3.mat, d_m3, m3.nrows*m3.ncols * sizeof(double), hipMemcpyDeviceToHost);
//cudaProfilerStop();
resultFile = fopen("result.txt", "w");
printMatrix(&m3, resultFile);
printf("Elapsed time: %.5lf seconds\n", ((double)t)/CLOCKS_PER_SEC);
fclose(mat1);
fclose(mat2);
fclose(resultFile);
hipFree(d_m1);
hipFree(d_m2);
hipFree(d_m3);
free(m1.mat);
free(m2.mat);
free(m3.mat);
return 0;
} | .text
.file "mat_mul.hip"
.globl _Z10readMatrixP6matrixP8_IO_FILE # -- Begin function _Z10readMatrixP6matrixP8_IO_FILE
.p2align 4, 0x90
.type _Z10readMatrixP6matrixP8_IO_FILE,@function
_Z10readMatrixP6matrixP8_IO_FILE: # @_Z10readMatrixP6matrixP8_IO_FILE
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq %rdi, %r14
movslq (%rdi), %rax
movslq 4(%rdi), %rdi
imulq %rax, %rdi
shlq $3, %rdi
callq malloc
movq %rax, 8(%r14)
cmpl $0, 4(%r14)
jle .LBB0_6
# %bb.1: # %.preheader.preheader
xorl %ebp, %ebp
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
incl %ebp
cmpl 4(%r14), %ebp
jge .LBB0_6
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
movl (%r14), %eax
testl %eax, %eax
jle .LBB0_5
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB0_2 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_4: # %.lr.ph
# Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebp, %eax
movslq %eax, %rdx
addq %r15, %rdx
shlq $3, %rdx
addq 8(%r14), %rdx
movl $.L.str, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl (%r14), %eax
incq %r15
cmpl %eax, %r15d
jl .LBB0_4
jmp .LBB0_5
.LBB0_6: # %._crit_edge17
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z10readMatrixP6matrixP8_IO_FILE, .Lfunc_end0-_Z10readMatrixP6matrixP8_IO_FILE
.cfi_endproc
# -- End function
.globl _Z11printMatrixP6matrixP8_IO_FILE # -- Begin function _Z11printMatrixP6matrixP8_IO_FILE
.p2align 4, 0x90
.type _Z11printMatrixP6matrixP8_IO_FILE,@function
_Z11printMatrixP6matrixP8_IO_FILE: # @_Z11printMatrixP6matrixP8_IO_FILE
.cfi_startproc
# %bb.0:
cmpl $0, 4(%rdi)
jle .LBB1_7
# %bb.1: # %.preheader.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
xorl %r15d, %r15d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movl $10, %edi
movq %rbx, %rsi
callq fputc@PLT
incl %r15d
cmpl 4(%r14), %r15d
jge .LBB1_6
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
movl (%r14), %eax
testl %eax, %eax
jle .LBB1_5
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB1_2 Depth=1
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movq 8(%r14), %rcx
imull %r15d, %eax
cltq
addq %r12, %rax
movsd (%rcx,%rax,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.1, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
movl (%r14), %eax
incq %r12
cmpl %eax, %r12d
jl .LBB1_4
jmp .LBB1_5
.LBB1_6:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB1_7: # %._crit_edge15
retq
.Lfunc_end1:
.size _Z11printMatrixP6matrixP8_IO_FILE, .Lfunc_end1-_Z11printMatrixP6matrixP8_IO_FILE
.cfi_endproc
# -- End function
.globl _Z24__device_stub__matrixMulPdS_S_iiii # -- Begin function _Z24__device_stub__matrixMulPdS_S_iiii
.p2align 4, 0x90
.type _Z24__device_stub__matrixMulPdS_S_iiii,@function
_Z24__device_stub__matrixMulPdS_S_iiii: # @_Z24__device_stub__matrixMulPdS_S_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9matrixMulPdS_S_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z24__device_stub__matrixMulPdS_S_iiii, .Lfunc_end2-_Z24__device_stub__matrixMulPdS_S_iiii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $3, %edi
jne .LBB3_23
# %bb.1:
movq %rsi, %r14
movq 8(%rsi), %rdi
movl $.L.str.4, %esi
callq fopen
movq %rax, %r12
movq 16(%r14), %rdi
movl $.L.str.4, %esi
callq fopen
movq %rax, %r14
leaq 20(%rsp), %rdx
leaq 16(%rsp), %rcx
movl $.L.str.5, %esi
movq %r12, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
leaq 4(%rsp), %rdx
movq %rsp, %rcx
movl $.L.str.5, %esi
movq %r14, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl 16(%rsp), %eax
cmpl 4(%rsp), %eax
jne .LBB3_24
# %bb.2:
movl 20(%rsp), %ebx
imull %ebx, %eax
movslq %eax, %rdi
shlq $3, %rdi
callq malloc
movq %rax, 24(%rsp)
testl %ebx, %ebx
jle .LBB3_8
# %bb.3: # %.preheader.i.preheader
xorl %ebp, %ebp
jmp .LBB3_4
.p2align 4, 0x90
.LBB3_7: # %._crit_edge.i
# in Loop: Header=BB3_4 Depth=1
incl %ebp
cmpl 20(%rsp), %ebp
jge .LBB3_8
.LBB3_4: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
movl 16(%rsp), %eax
testl %eax, %eax
jle .LBB3_7
# %bb.5: # %.lr.ph.i.preheader
# in Loop: Header=BB3_4 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_6: # %.lr.ph.i
# Parent Loop BB3_4 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebp, %eax
movslq %eax, %rdx
addq %r15, %rdx
shlq $3, %rdx
addq 24(%rsp), %rdx
movl $.L.str, %esi
movq %r12, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl 16(%rsp), %eax
incq %r15
cmpl %eax, %r15d
jl .LBB3_6
jmp .LBB3_7
.LBB3_8: # %_Z10readMatrixP6matrixP8_IO_FILE.exit
movslq (%rsp), %rdi
movslq 4(%rsp), %rbx
imulq %rbx, %rdi
shlq $3, %rdi
callq malloc
movq %rax, 8(%rsp)
testq %rbx, %rbx
jle .LBB3_14
# %bb.9: # %.preheader.i23.preheader
xorl %ebp, %ebp
jmp .LBB3_10
.p2align 4, 0x90
.LBB3_13: # %._crit_edge.i25
# in Loop: Header=BB3_10 Depth=1
incl %ebp
cmpl 4(%rsp), %ebp
jge .LBB3_14
.LBB3_10: # %.preheader.i23
# =>This Loop Header: Depth=1
# Child Loop BB3_12 Depth 2
movl (%rsp), %eax
testl %eax, %eax
jle .LBB3_13
# %bb.11: # %.lr.ph.i26.preheader
# in Loop: Header=BB3_10 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_12: # %.lr.ph.i26
# Parent Loop BB3_10 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebp, %eax
movslq %eax, %rdx
addq %r15, %rdx
shlq $3, %rdx
addq 8(%rsp), %rdx
movl $.L.str, %esi
movq %r14, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl (%rsp), %eax
incq %r15
cmpl %eax, %r15d
jl .LBB3_12
jmp .LBB3_13
.LBB3_14: # %_Z10readMatrixP6matrixP8_IO_FILE.exit28
movq %r14, 96(%rsp) # 8-byte Spill
movq %r12, 104(%rsp) # 8-byte Spill
movslq 20(%rsp), %rbx
movl %ebx, %r13d
movl (%rsp), %r15d
movl %r15d, %eax
imull %ebx, %eax
movslq %eax, %r12
shlq $3, %r12
movq %r12, %rdi
callq malloc
movq %rax, %r14
movslq 16(%rsp), %rsi
imulq %rbx, %rsi
shlq $3, %rsi
leaq 48(%rsp), %rdi
callq hipMalloc
movslq 4(%rsp), %rax
movslq (%rsp), %rsi
imulq %rax, %rsi
shlq $3, %rsi
leaq 40(%rsp), %rdi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 48(%rsp), %rdi
movq 24(%rsp), %rsi
movslq 20(%rsp), %rax
movslq 16(%rsp), %rdx
imulq %rax, %rdx
shlq $3, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq 8(%rsp), %rsi
movslq 4(%rsp), %rax
movslq (%rsp), %rdx
imulq %rax, %rdx
shlq $3, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
xorl %esi, %esi
movq %r12, %rdx
callq hipMemset
movl (%rsp), %eax
addl $31, %eax
shrl $5, %eax
movl 20(%rsp), %ebp
addl $31, %ebp
shrl $5, %ebp
shlq $32, %rbp
orq %rax, %rbp
callq clock
movq %rax, 88(%rsp) # 8-byte Spill
movabsq $137438953504, %rdx # imm = 0x2000000020
movq %rbp, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_16
# %bb.15:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movl 16(%rsp), %esi
movl 20(%rsp), %edi
movl (%rsp), %r8d
movl 4(%rsp), %r9d
movq %rax, 184(%rsp)
movq %rcx, 176(%rsp)
movq %rdx, 168(%rsp)
movl %edi, 68(%rsp)
movl %r9d, 64(%rsp)
movl %esi, 60(%rsp)
movl %r8d, 56(%rsp)
leaq 184(%rsp), %rax
movq %rax, 192(%rsp)
leaq 176(%rsp), %rax
movq %rax, 200(%rsp)
leaq 168(%rsp), %rax
movq %rax, 208(%rsp)
leaq 68(%rsp), %rax
movq %rax, 216(%rsp)
leaq 64(%rsp), %rax
movq %rax, 224(%rsp)
leaq 60(%rsp), %rax
movq %rax, 232(%rsp)
leaq 56(%rsp), %rax
movq %rax, 240(%rsp)
leaq 152(%rsp), %rdi
leaq 136(%rsp), %rsi
leaq 128(%rsp), %rdx
leaq 120(%rsp), %rcx
callq __hipPopCallConfiguration
movq 152(%rsp), %rsi
movl 160(%rsp), %edx
movq 136(%rsp), %rcx
movl 144(%rsp), %r8d
leaq 192(%rsp), %r9
movl $_Z9matrixMulPdS_S_iiii, %edi
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_16:
callq hipDeviceSynchronize
callq clock
movq %rax, 80(%rsp) # 8-byte Spill
movq 32(%rsp), %rsi
movq %r14, 72(%rsp) # 8-byte Spill
movq %r14, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.L.str.7, %edi
movl $.L.str.8, %esi
callq fopen
movq %rax, %r12
movq %r13, 112(%rsp) # 8-byte Spill
testl %r13d, %r13d
jle .LBB3_22
# %bb.17: # %.preheader.i29.preheader
xorl %ebp, %ebp
xorl %r13d, %r13d
jmp .LBB3_18
.p2align 4, 0x90
.LBB3_21: # %._crit_edge.i30
# in Loop: Header=BB3_18 Depth=1
movl $10, %edi
movq %r12, %rsi
callq fputc@PLT
incq %r13
addl %r15d, %ebp
cmpq 112(%rsp), %r13 # 8-byte Folded Reload
je .LBB3_22
.LBB3_18: # %.preheader.i29
# =>This Loop Header: Depth=1
# Child Loop BB3_20 Depth 2
testl %r15d, %r15d
jle .LBB3_21
# %bb.19: # %.lr.ph.i31.preheader
# in Loop: Header=BB3_18 Depth=1
movl %ebp, %eax
movq 72(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_20: # %.lr.ph.i31
# Parent Loop BB3_18 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rbx,%r14,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.1, %esi
movq %r12, %rdi
movb $1, %al
callq fprintf
incq %r14
cmpq %r14, %r15
jne .LBB3_20
jmp .LBB3_21
.LBB3_22: # %_Z11printMatrixP6matrixP8_IO_FILE.exit
movq 80(%rsp), %rax # 8-byte Reload
subq 88(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI3_0(%rip), %xmm0
movl $.L.str.9, %edi
movb $1, %al
callq printf
movq 104(%rsp), %rdi # 8-byte Reload
callq fclose
movq 96(%rsp), %rdi # 8-byte Reload
callq fclose
movq %r12, %rdi
callq fclose
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq free
movq 8(%rsp), %rdi
callq free
movq 72(%rsp), %rdi # 8-byte Reload
callq free
xorl %eax, %eax
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_23:
.cfi_def_cfa_offset 304
movl $.Lstr.1, %edi
callq puts@PLT
movl $1, %edi
callq exit
.LBB3_24:
movl $.Lstr, %edi
callq puts@PLT
movq %r12, %rdi
callq fclose
movq %r14, %rdi
callq fclose
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9matrixMulPdS_S_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%lf"
.size .L.str, 4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%lf "
.size .L.str.1, 5
.type _Z9matrixMulPdS_S_iiii,@object # @_Z9matrixMulPdS_S_iiii
.section .rodata,"a",@progbits
.globl _Z9matrixMulPdS_S_iiii
.p2align 3, 0x0
_Z9matrixMulPdS_S_iiii:
.quad _Z24__device_stub__matrixMulPdS_S_iiii
.size _Z9matrixMulPdS_S_iiii, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "r"
.size .L.str.4, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d %d"
.size .L.str.5, 6
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "result.txt"
.size .L.str.7, 11
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "w"
.size .L.str.8, 2
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Elapsed time: %.5lf seconds\n"
.size .L.str.9, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9matrixMulPdS_S_iiii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "It is not possible to do matrix multiplication. Check matrices number of rows and cols."
.size .Lstr, 88
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Parameter error."
.size .Lstr.1, 17
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__matrixMulPdS_S_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9matrixMulPdS_S_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9matrixMulPdS_S_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x184], PT ; /* 0x0000610000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x180] ; /* 0x0000600000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe4000001ff00 */
/*00d0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0xc80 ; /* 0x00000b9000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe20007ffe0ff */
/*0100*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*0110*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fe200078ec0ff */
/*0120*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe2000001ff00 */
/*0130*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fda0003f06070 */
/*0140*/ @!P0 BRA 0xb30 ; /* 0x000009e000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R4, -R2, c[0x0][0x180], RZ ; /* 0x0000600002047a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0170*/ MOV R29, 0x8 ; /* 0x00000008001d7802 */
/* 0x000fe20000000f00 */
/*0180*/ IMAD R26, R3, c[0x0][0x180], RZ ; /* 0x00006000031a7a24 */
/* 0x000fe200078e02ff */
/*0190*/ ISETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f04270 */
/*01a0*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe2000001ff00 */
/*01b0*/ MOV R5, RZ ; /* 0x000000ff00057202 */
/* 0x000fe20000000f00 */
/*01c0*/ IMAD.WIDE R28, R0, R29, c[0x0][0x168] ; /* 0x00005a00001c7625 */
/* 0x000fd400078e021d */
/*01d0*/ @!P0 BRA 0x990 ; /* 0x000007b000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6c0 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*0230*/ IMAD.U32 R7, RZ, RZ, UR7 ; /* 0x00000007ff077e24 */
/* 0x000fe2000f8e00ff */
/*0240*/ LDG.E.64 R20, [R28.64] ; /* 0x000000041c147981 */
/* 0x0010a6000c1e1b00 */
/*0250*/ IMAD.WIDE R6, R26, 0x8, R6 ; /* 0x000000081a067825 */
/* 0x000fca00078e0206 */
/*0260*/ LDG.E.64 R12, [R6.64] ; /* 0x00000004060c7981 */
/* 0x000ea2000c1e1b00 */
/*0270*/ MOV R27, c[0x0][0x184] ; /* 0x00006100001b7a02 */
/* 0x000fc60000000f00 */
/*0280*/ LDG.E.64 R10, [R6.64+0x8] ; /* 0x00000804060a7981 */
/* 0x000ee4000c1e1b00 */
/*0290*/ IMAD.WIDE R24, R27.reuse, 0x8, R28 ; /* 0x000000081b187825 */
/* 0x040fe400078e021c */
/*02a0*/ LDG.E.64 R8, [R6.64+0x10] ; /* 0x0000100406087981 */
/* 0x000f28000c1e1b00 */
/*02b0*/ LDG.E.64 R16, [R24.64] ; /* 0x0000000418107981 */
/* 0x000ee2000c1e1b00 */
/*02c0*/ IMAD.WIDE R22, R27, 0x8, R24 ; /* 0x000000081b167825 */
/* 0x000fca00078e0218 */
/*02d0*/ LDG.E.64 R14, [R22.64] ; /* 0x00000004160e7981 */
/* 0x002322000c1e1b00 */
/*02e0*/ IMAD.WIDE R28, R27, 0x8, R22 ; /* 0x000000081b1c7825 */
/* 0x001fc600078e0216 */
/*02f0*/ LDG.E.64 R22, [R6.64+0x18] ; /* 0x0000180406167981 */
/* 0x002f62000c1e1b00 */
/*0300*/ DFMA R18, R20, R12, R18 ; /* 0x0000000c1412722b */
/* 0x0040c60000000012 */
/*0310*/ LDG.E.64 R12, [R28.64] ; /* 0x000000041c0c7981 */
/* 0x001164000c1e1b00 */
/*0320*/ IMAD.WIDE R28, R27.reuse, 0x8, R28 ; /* 0x000000081b1c7825 */
/* 0x041fe200078e021c */
/*0330*/ DFMA R18, R16, R10, R18 ; /* 0x0000000a1012722b */
/* 0x0081240000000012 */
/*0340*/ LDG.E.64 R16, [R6.64+0x20] ; /* 0x0000200406107981 */
/* 0x001ea8000c1e1b00 */
/*0350*/ LDG.E.64 R10, [R28.64] ; /* 0x000000041c0a7981 */
/* 0x000ea2000c1e1b00 */
/*0360*/ IMAD.WIDE R24, R27, 0x8, R28 ; /* 0x000000081b187825 */
/* 0x000fe200078e021c */
/*0370*/ DFMA R18, R14, R8, R18 ; /* 0x000000080e12722b */
/* 0x0101440000000012 */
/*0380*/ LDG.E.64 R14, [R6.64+0x28] ; /* 0x00002804060e7981 */
/* 0x001ee8000c1e1b00 */
/*0390*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x000ee2000c1e1b00 */
/*03a0*/ IMAD.WIDE R20, R27.reuse, 0x8, R24 ; /* 0x000000081b147825 */
/* 0x040fe200078e0218 */
/*03b0*/ DFMA R22, R12, R22, R18 ; /* 0x000000160c16722b */
/* 0x0200a40000000012 */
/*03c0*/ LDG.E.64 R18, [R6.64+0x30] ; /* 0x0000300406127981 */
/* 0x001f28000c1e1b00 */
/*03d0*/ LDG.E.64 R12, [R20.64] ; /* 0x00000004140c7981 */
/* 0x000124000c1e1b00 */
/*03e0*/ IMAD.WIDE R20, R27, 0x8, R20 ; /* 0x000000081b147825 */
/* 0x001fe200078e0214 */
/*03f0*/ DFMA R16, R10, R16, R22 ; /* 0x000000100a10722b */
/* 0x0040c40000000016 */
/*0400*/ LDG.E.64 R22, [R6.64+0x38] ; /* 0x0000380406167981 */
/* 0x001ea8000c1e1b00 */
/*0410*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000ea2000c1e1b00 */
/*0420*/ IMAD.WIDE R28, R27.reuse, 0x8, R20 ; /* 0x000000081b1c7825 */
/* 0x040fe200078e0214 */
/*0430*/ DFMA R14, R8, R14, R16 ; /* 0x0000000e080e722b */
/* 0x0081240000000010 */
/*0440*/ LDG.E.64 R16, [R6.64+0x40] ; /* 0x0000400406107981 */
/* 0x001ee8000c1e1b00 */
/*0450*/ LDG.E.64 R8, [R28.64] ; /* 0x000000041c087981 */
/* 0x000ee2000c1e1b00 */
/*0460*/ IMAD.WIDE R24, R27, 0x8, R28 ; /* 0x000000081b187825 */
/* 0x000fe200078e021c */
/*0470*/ DFMA R18, R12, R18, R14 ; /* 0x000000120c12722b */
/* 0x010084000000000e */
/*0480*/ LDG.E.64 R14, [R6.64+0x48] ; /* 0x00004804060e7981 */
/* 0x001f28000c1e1b00 */
/*0490*/ LDG.E.64 R12, [R24.64] ; /* 0x00000004180c7981 */
/* 0x000124000c1e1b00 */
/*04a0*/ IMAD.WIDE R24, R27.reuse, 0x8, R24 ; /* 0x000000081b187825 */
/* 0x041fe200078e0218 */
/*04b0*/ DFMA R22, R10, R22, R18 ; /* 0x000000160a16722b */
/* 0x0040e40000000012 */
/*04c0*/ LDG.E.64 R18, [R6.64+0x50] ; /* 0x0000500406127981 */
/* 0x001ea6000c1e1b00 */
/*04d0*/ IMAD.WIDE R20, R27, 0x8, R24 ; /* 0x000000081b147825 */
/* 0x000fe200078e0218 */
/*04e0*/ LDG.E.64 R10, [R24.64] ; /* 0x00000004180a7981 */
/* 0x000ea2000c1e1b00 */
/*04f0*/ DFMA R16, R8, R16, R22 ; /* 0x000000100810722b */
/* 0x0081060000000016 */
/*0500*/ LDG.E.64 R22, [R6.64+0x58] ; /* 0x0000580406167981 */
/* 0x001ee8000c1e1b00 */
/*0510*/ LDG.E.64 R8, [R20.64] ; /* 0x0000000414087981 */
/* 0x000ee2000c1e1b00 */
/*0520*/ IMAD.WIDE R28, R27.reuse, 0x8, R20 ; /* 0x000000081b1c7825 */
/* 0x040fe200078e0214 */
/*0530*/ DFMA R14, R12, R14, R16 ; /* 0x0000000e0c0e722b */
/* 0x0100a40000000010 */
/*0540*/ LDG.E.64 R12, [R6.64+0x60] ; /* 0x00006004060c7981 */
/* 0x001f28000c1e1b00 */
/*0550*/ LDG.E.64 R16, [R28.64] ; /* 0x000000041c107981 */
/* 0x000124000c1e1b00 */
/*0560*/ IMAD.WIDE R28, R27, 0x8, R28 ; /* 0x000000081b1c7825 */
/* 0x001fe200078e021c */
/*0570*/ DFMA R18, R10, R18, R14 ; /* 0x000000120a12722b */
/* 0x0040c4000000000e */
/*0580*/ LDG.E.64 R10, [R6.64+0x68] ; /* 0x00006804060a7981 */
/* 0x001ea6000c1e1b00 */
/*0590*/ IMAD.WIDE R24, R27, 0x8, R28 ; /* 0x000000081b187825 */
/* 0x000fe200078e021c */
/*05a0*/ LDG.E.64 R14, [R28.64] ; /* 0x000000041c0e7981 */
/* 0x000ea2000c1e1b00 */
/*05b0*/ DFMA R22, R8, R22, R18 ; /* 0x000000160816722b */
/* 0x0081060000000012 */
/*05c0*/ LDG.E.64 R18, [R6.64+0x70] ; /* 0x0000700406127981 */
/* 0x001ee2000c1e1b00 */
/*05d0*/ IMAD.WIDE R8, R27, 0x8, R24 ; /* 0x000000081b087825 */
/* 0x000fc600078e0218 */
/*05e0*/ LDG.E.64 R20, [R24.64] ; /* 0x0000000418147981 */
/* 0x000ee2000c1e1b00 */
/*05f0*/ DFMA R12, R16, R12, R22 ; /* 0x0000000c100c722b */
/* 0x0100860000000016 */
/*0600*/ LDG.E.64 R16, [R6.64+0x78] ; /* 0x0000780406107981 */
/* 0x001f28000c1e1b00 */
/*0610*/ LDG.E.64 R22, [R8.64] ; /* 0x0000000408167981 */
/* 0x000f22000c1e1b00 */
/*0620*/ IADD3 R4, R4, -0x10, RZ ; /* 0xfffffff004047810 */
/* 0x000fc80007ffe0ff */
/*0630*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe20003f24270 */
/*0640*/ DFMA R10, R14, R10, R12 ; /* 0x0000000a0e0a722b */
/* 0x004ee2000000000c */
/*0650*/ UIADD3 UR6, UP0, UR6, 0x80, URZ ; /* 0x0000008006067890 */
/* 0x000fca000ff1e03f */
/*0660*/ DFMA R18, R20, R18, R10 ; /* 0x000000121412722b */
/* 0x008f22000000000a */
/*0670*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0680*/ IMAD.WIDE R28, R27, 0x8, R8 ; /* 0x000000081b1c7825 */
/* 0x000fe200078e0208 */
/*0690*/ IADD3 R5, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x000fc60007ffe0ff */
/*06a0*/ DFMA R18, R22, R16, R18 ; /* 0x000000101612722b */
/* 0x0100620000000012 */
/*06b0*/ @P1 BRA 0x220 ; /* 0xfffffb6000001947 */
/* 0x000fea000383ffff */
/*06c0*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*06d0*/ @!P1 BRA 0x970 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*06e0*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*06f0*/ LDG.E.64 R20, [R28.64] ; /* 0x000000041c147981 */
/* 0x0004e2000c1e1b00 */
/*0700*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fe40008000f00 */
/*0710*/ MOV R27, c[0x0][0x184] ; /* 0x00006100001b7a02 */
/* 0x000fc60000000f00 */
/*0720*/ IMAD.WIDE R6, R26, 0x8, R6 ; /* 0x000000081a067825 */
/* 0x000fca00078e0206 */
/*0730*/ LDG.E.64 R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x000ee2000c1e1b00 */
/*0740*/ IMAD.WIDE R22, R27, 0x8, R28 ; /* 0x000000081b167825 */
/* 0x001fc600078e021c */
/*0750*/ LDG.E.64 R14, [R6.64+0x8] ; /* 0x00000804060e7981 */
/* 0x000f28000c1e1b00 */
/*0760*/ LDG.E.64 R16, [R22.64] ; /* 0x0000000416107981 */
/* 0x000128000c1e1b00 */
/*0770*/ LDG.E.64 R12, [R6.64+0x10] ; /* 0x00001004060c7981 */
/* 0x000f62000c1e1b00 */
/*0780*/ IMAD.WIDE R22, R27, 0x8, R22 ; /* 0x000000081b167825 */
/* 0x001fca00078e0216 */
/*0790*/ LDG.E.64 R8, [R22.64] ; /* 0x0000000416087981 */
/* 0x000f62000c1e1b00 */
/*07a0*/ IMAD.WIDE R24, R27, 0x8, R22 ; /* 0x000000081b187825 */
/* 0x000fcc00078e0216 */
/*07b0*/ IMAD.WIDE R28, R27, 0x8, R24 ; /* 0x000000081b1c7825 */
/* 0x004fe200078e0218 */
/*07c0*/ DFMA R18, R20, R10, R18 ; /* 0x0000000a1412722b */
/* 0x00a1240000000012 */
/*07d0*/ LDG.E.64 R20, [R6.64+0x18] ; /* 0x0000180406147981 */
/* 0x001ea8000c1e1b00 */
/*07e0*/ LDG.E.64 R10, [R24.64] ; /* 0x00000004180a7981 */
/* 0x0000a2000c1e1b00 */
/*07f0*/ DFMA R14, R16, R14, R18 ; /* 0x0000000e100e722b */
/* 0x0103460000000012 */
/*0800*/ LDG.E.64 R18, [R6.64+0x20] ; /* 0x0000200406127981 */
/* 0x002ee8000c1e1b00 */
/*0810*/ LDG.E.64 R16, [R28.64] ; /* 0x000000041c107981 */
/* 0x0002e2000c1e1b00 */
/*0820*/ DFMA R12, R8, R12, R14 ; /* 0x0000000c080c722b */
/* 0x0208a2000000000e */
/*0830*/ IMAD.WIDE R28, R27.reuse, 0x8, R28 ; /* 0x000000081b1c7825 */
/* 0x042fe400078e021c */
/*0840*/ LDG.E.64 R8, [R6.64+0x28] ; /* 0x0000280406087981 */
/* 0x010f28000c1e1b00 */
/*0850*/ LDG.E.64 R14, [R28.64] ; /* 0x000000041c0e7981 */
/* 0x000f22000c1e1b00 */
/*0860*/ IMAD.WIDE R22, R27, 0x8, R28 ; /* 0x000000081b167825 */
/* 0x000fcc00078e021c */
/*0870*/ IMAD.WIDE R24, R27, 0x8, R22 ; /* 0x000000081b187825 */
/* 0x001fe200078e0216 */
/*0880*/ DFMA R20, R10, R20, R12 ; /* 0x000000140a14722b */
/* 0x0040e4000000000c */
/*0890*/ LDG.E.64 R12, [R6.64+0x30] ; /* 0x00003004060c7981 */
/* 0x001ea8000c1e1b00 */
/*08a0*/ LDG.E.64 R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000ea2000c1e1b00 */
/*08b0*/ DFMA R16, R16, R18, R20 ; /* 0x000000121010722b */
/* 0x0081060000000014 */
/*08c0*/ LDG.E.64 R18, [R6.64+0x38] ; /* 0x0000380406127981 */
/* 0x001ee8000c1e1b00 */
/*08d0*/ LDG.E.64 R20, [R24.64] ; /* 0x0000000418147981 */
/* 0x000ee2000c1e1b00 */
/*08e0*/ DFMA R8, R14, R8, R16 ; /* 0x000000080e08722b */
/* 0x010ea20000000010 */
/*08f0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0900*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0910*/ IMAD.WIDE R28, R27, 0x8, R24 ; /* 0x000000081b1c7825 */
/* 0x000fe200078e0218 */
/*0920*/ IADD3 R5, R5, 0x8, RZ ; /* 0x0000000805057810 */
/* 0x000fe40007ffe0ff */
/*0930*/ IADD3 R4, R4, -0x8, RZ ; /* 0xfffffff804047810 */
/* 0x000fe20007ffe0ff */
/*0940*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0950*/ DFMA R8, R10, R12, R8 ; /* 0x0000000c0a08722b */
/* 0x004ecc0000000008 */
/*0960*/ DFMA R18, R20, R18, R8 ; /* 0x000000121412722b */
/* 0x0080480000000008 */
/*0970*/ ISETP.NE.OR P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0000705670 */
/*0980*/ @!P0 BRA 0xb30 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0990*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fe20008000f00 */
/*09a0*/ IMAD.U32 R6, RZ, RZ, UR6 ; /* 0x00000006ff067e24 */
/* 0x000fe2000f8e00ff */
/*09b0*/ LDG.E.64 R8, [R28.64] ; /* 0x000000041c087981 */
/* 0x001ea6000c1e1b00 */
/*09c0*/ IMAD.WIDE R6, R26, 0x8, R6 ; /* 0x000000081a067825 */
/* 0x000fca00078e0206 */
/*09d0*/ LDG.E.64 R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x000ea2000c1e1b00 */
/*09e0*/ MOV R27, c[0x0][0x184] ; /* 0x00006100001b7a02 */
/* 0x000fc60000000f00 */
/*09f0*/ LDG.E.64 R12, [R6.64+0x8] ; /* 0x00000804060c7981 */
/* 0x000ee4000c1e1b00 */
/*0a00*/ IMAD.WIDE R24, R27.reuse, 0x8, R28 ; /* 0x000000081b187825 */
/* 0x040fe400078e021c */
/*0a10*/ LDG.E.64 R16, [R6.64+0x10] ; /* 0x0000100406107981 */
/* 0x000f28000c1e1b00 */
/*0a20*/ LDG.E.64 R22, [R24.64] ; /* 0x0000000418167981 */
/* 0x0000e4000c1e1b00 */
/*0a30*/ IMAD.WIDE R24, R27, 0x8, R24 ; /* 0x000000081b187825 */
/* 0x001fca00078e0218 */
/*0a40*/ LDG.E.64 R14, [R24.64] ; /* 0x00000004180e7981 */
/* 0x000f22000c1e1b00 */
/*0a50*/ IMAD.WIDE R20, R27, 0x8, R24 ; /* 0x000000081b147825 */
/* 0x000fe200078e0218 */
/*0a60*/ DFMA R8, R8, R10, R18 ; /* 0x0000000a0808722b */
/* 0x0060e40000000012 */
/*0a70*/ LDG.E.64 R18, [R6.64+0x18] ; /* 0x0000180406127981 */
/* 0x001ea8000c1e1b00 */
/*0a80*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000ea2000c1e1b00 */
/*0a90*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fc80007ffe0ff */
/*0aa0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0ab0*/ DFMA R8, R22, R12, R8 ; /* 0x0000000c1608722b */
/* 0x008f220000000008 */
/*0ac0*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0ad0*/ IMAD.WIDE R28, R27, 0x8, R20 ; /* 0x000000081b1c7825 */
/* 0x000fc600078e0214 */
/*0ae0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0af0*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fe20007ffe0ff */
/*0b00*/ DFMA R8, R14, R16, R8 ; /* 0x000000100e08722b */
/* 0x010e8c0000000008 */
/*0b10*/ DFMA R18, R10, R18, R8 ; /* 0x000000120a12722b */
/* 0x0040640000000008 */
/*0b20*/ @P0 BRA 0x990 ; /* 0xfffffe6000000947 */
/* 0x003fea000383ffff */
/*0b30*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*0b40*/ @!P0 BRA 0xc80 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0b50*/ MOV R7, 0x8 ; /* 0x0000000800077802 */
/* 0x000fe20000000f00 */
/*0b60*/ IMAD R4, R3, c[0x0][0x180], R5 ; /* 0x0000600003047a24 */
/* 0x000fe400078e0205 */
/*0b70*/ IMAD R6, R5, c[0x0][0x184], R0 ; /* 0x0000610005067a24 */
/* 0x000fe400078e0200 */
/*0b80*/ IMAD.WIDE R4, R4, R7, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0207 */
/*0b90*/ IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fe200078e0207 */
/*0ba0*/ MOV R10, R4 ; /* 0x00000004000a7202 */
/* 0x000fc60000000f00 */
/*0bb0*/ IMAD.MOV.U32 R11, RZ, RZ, R5 ; /* 0x000000ffff0b7224 */
/* 0x000fc600078e0005 */
/*0bc0*/ MOV R8, R10 ; /* 0x0000000a00087202 */
/* 0x001fe20000000f00 */
/*0bd0*/ LDG.E.64 R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0000a2000c1e1b00 */
/*0be0*/ MOV R9, R11 ; /* 0x0000000b00097202 */
/* 0x000fcc0000000f00 */
/*0bf0*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1b00 */
/*0c00*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fc80007ffe0ff */
/*0c10*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f05270 */
/*0c20*/ MOV R13, c[0x0][0x184] ; /* 0x00006100000d7a02 */
/* 0x000fe40000000f00 */
/*0c30*/ IADD3 R10, P1, R10, 0x8, RZ ; /* 0x000000080a0a7810 */
/* 0x000fc60007f3e0ff */
/*0c40*/ IMAD.WIDE R6, R13, 0x8, R6 ; /* 0x000000080d067825 */
/* 0x001fe200078e0206 */
/*0c50*/ IADD3.X R11, RZ, R11, RZ, P1, !PT ; /* 0x0000000bff0b7210 */
/* 0x000fe20000ffe4ff */
/*0c60*/ DFMA R18, R4, R8, R18 ; /* 0x000000080412722b */
/* 0x0060480000000012 */
/*0c70*/ @P0 BRA 0xbc0 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*0c80*/ MOV R2, 0x8 ; /* 0x0000000800027802 */
/* 0x000fe20000000f00 */
/*0c90*/ IMAD R3, R3, c[0x0][0x184], R0 ; /* 0x0000610003037a24 */
/* 0x000fc800078e0200 */
/*0ca0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0cb0*/ STG.E.64 [R2.64], R18 ; /* 0x0000001202007986 */
/* 0x002fe2000c101b04 */
/*0cc0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0cd0*/ BRA 0xcd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9matrixMulPdS_S_iiii
.globl _Z9matrixMulPdS_S_iiii
.p2align 8
.type _Z9matrixMulPdS_S_iiii,@function
_Z9matrixMulPdS_S_iiii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s4, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x24
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v6, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 3, v[2:3]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v7, 31, v6
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s2, 0
v_lshlrev_b64 v[7:8], 3, v[6:7]
v_add_nc_u32_e32 v6, s3, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b64 v[9:10], v[4:5], off
global_load_b64 v[7:8], v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 8
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[9:10], v[7:8], v[2:3]
s_cbranch_scc1 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v0, s3, v[1:2]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9matrixMulPdS_S_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9matrixMulPdS_S_iiii, .Lfunc_end0-_Z9matrixMulPdS_S_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9matrixMulPdS_S_iiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9matrixMulPdS_S_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00043dab_00000000-6_mat_mul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%lf"
.text
.globl _Z10readMatrixP6matrixP8_IO_FILE
.type _Z10readMatrixP6matrixP8_IO_FILE, @function
_Z10readMatrixP6matrixP8_IO_FILE:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %rbp
movq %rsi, %r13
movl 4(%rdi), %ebx
movl %ebx, %edi
imull 0(%rbp), %edi
movslq %edi, %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, 8(%rbp)
movl $0, %r12d
leaq .LC0(%rip), %r14
testl %ebx, %ebx
jg .L4
.L3:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
imull %r12d, %eax
addl %ebx, %eax
cltq
movq 8(%rbp), %rdx
leaq (%rdx,%rax,8), %rdx
movq %r14, %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addl $1, %ebx
movl 0(%rbp), %eax
cmpl %ebx, %eax
jg .L6
.L7:
addl $1, %r12d
cmpl %r12d, 4(%rbp)
jle .L3
.L4:
movl 0(%rbp), %eax
movl $0, %ebx
testl %eax, %eax
jg .L6
jmp .L7
.cfi_endproc
.LFE2057:
.size _Z10readMatrixP6matrixP8_IO_FILE, .-_Z10readMatrixP6matrixP8_IO_FILE
.section .rodata.str1.1
.LC1:
.string "%lf "
.LC2:
.string "\n"
.text
.globl _Z11printMatrixP6matrixP8_IO_FILE
.type _Z11printMatrixP6matrixP8_IO_FILE, @function
_Z11printMatrixP6matrixP8_IO_FILE:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movq %rsi, %r13
movl $0, %r12d
leaq .LC1(%rip), %r14
leaq .LC2(%rip), %r15
cmpl $0, 4(%rdi)
jg .L15
.L14:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
imull %r12d, %eax
addl %ebx, %eax
cltq
movq 8(%rbp), %rdx
movsd (%rdx,%rax,8), %xmm0
movq %r14, %rdx
movl $2, %esi
movq %r13, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addl $1, %ebx
movl 0(%rbp), %eax
cmpl %ebx, %eax
jg .L17
.L18:
movq %r15, %rdx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, %r12d
cmpl %r12d, 4(%rbp)
jle .L14
.L15:
movl 0(%rbp), %eax
movl $0, %ebx
testl %eax, %eax
jg .L17
jmp .L18
.cfi_endproc
.LFE2058:
.size _Z11printMatrixP6matrixP8_IO_FILE, .-_Z11printMatrixP6matrixP8_IO_FILE
.globl _Z36__device_stub__Z9matrixMulPdS_S_iiiiPdS_S_iiii
.type _Z36__device_stub__Z9matrixMulPdS_S_iiiiPdS_S_iiii, @function
_Z36__device_stub__Z9matrixMulPdS_S_iiiiPdS_S_iiii:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9matrixMulPdS_S_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z36__device_stub__Z9matrixMulPdS_S_iiiiPdS_S_iiii, .-_Z36__device_stub__Z9matrixMulPdS_S_iiiiPdS_S_iiii
.globl _Z9matrixMulPdS_S_iiii
.type _Z9matrixMulPdS_S_iiii, @function
_Z9matrixMulPdS_S_iiii:
.LFB2085:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z36__device_stub__Z9matrixMulPdS_S_iiiiPdS_S_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z9matrixMulPdS_S_iiii, .-_Z9matrixMulPdS_S_iiii
.section .rodata.str1.1
.LC3:
.string "Parameter error.\n"
.LC4:
.string "r"
.LC5:
.string "%d %d"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "It is not possible to do matrix multiplication. Check matrices number of rows and cols.\n"
.section .rodata.str1.1
.LC7:
.string "w"
.LC8:
.string "result.txt"
.LC10:
.string "Elapsed time: %.5lf seconds\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
cmpl $3, %edi
jne .L39
movq %rsi, %rbx
movq 8(%rsi), %rdi
leaq .LC4(%rip), %rbp
movq %rbp, %rsi
call fopen@PLT
movq %rax, %r13
movq 16(%rbx), %rdi
movq %rbp, %rsi
call fopen@PLT
movq %rax, %r12
leaq 48(%rsp), %rcx
leaq 52(%rsp), %rdx
leaq .LC5(%rip), %rbx
movq %rbx, %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
leaq 64(%rsp), %rcx
leaq 68(%rsp), %rdx
movq %rbx, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 68(%rsp), %eax
cmpl %eax, 48(%rsp)
jne .L40
leaq 48(%rsp), %rdi
movq %r13, %rsi
call _Z10readMatrixP6matrixP8_IO_FILE
leaq 64(%rsp), %rdi
movq %r12, %rsi
call _Z10readMatrixP6matrixP8_IO_FILE
movl 52(%rsp), %ebp
movl %ebp, 84(%rsp)
movl 64(%rsp), %ebx
movl %ebx, 80(%rsp)
imull %ebp, %ebx
movslq %ebx, %rbx
salq $3, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rax, 88(%rsp)
imull 48(%rsp), %ebp
movslq %ebp, %rsi
salq $3, %rsi
movq %rsp, %rdi
call cudaMalloc@PLT
movl 68(%rsp), %esi
imull 64(%rsp), %esi
movslq %esi, %rsi
salq $3, %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl 52(%rsp), %edx
imull 48(%rsp), %edx
movslq %edx, %rdx
salq $3, %rdx
movl $1, %ecx
movq 56(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl 68(%rsp), %edx
imull 64(%rsp), %edx
movslq %edx, %rdx
salq $3, %rdx
movl $1, %ecx
movq 72(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movq %rbx, %rdx
movl $0, %esi
movq 16(%rsp), %rdi
call cudaMemset@PLT
movl $1, 32(%rsp)
movl 52(%rsp), %eax
addl $31, %eax
shrl $5, %eax
movl 64(%rsp), %ecx
leal 31(%rcx), %edx
shrl $5, %edx
movl %edx, 36(%rsp)
movl %eax, 40(%rsp)
movl $1, 44(%rsp)
call clock@PLT
movq %rax, %r15
movl $32, 24(%rsp)
movl $32, 28(%rsp)
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L36:
call cudaDeviceSynchronize@PLT
call clock@PLT
subq %r15, %rax
movq %rax, %rbp
movl $2, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq .LC7(%rip), %rsi
leaq .LC8(%rip), %rdi
call fopen@PLT
movq %rax, %rbx
leaq 80(%rsp), %rdi
movq %rax, %rsi
call _Z11printMatrixP6matrixP8_IO_FILE
pxor %xmm0, %xmm0
cvtsi2sdq %rbp, %xmm0
divsd .LC9(%rip), %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r13, %rdi
call fclose@PLT
movq %r12, %rdi
call fclose@PLT
movq %rbx, %rdi
call fclose@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call free@PLT
movq 72(%rsp), %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L42
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L40:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call fclose@PLT
movq %r12, %rdi
call fclose@PLT
movl $1, %edi
call exit@PLT
.L41:
subq $8, %rsp
.cfi_def_cfa_offset 184
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 192
movl 64(%rsp), %r9d
movl 84(%rsp), %r8d
movl 68(%rsp), %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z36__device_stub__Z9matrixMulPdS_S_iiiiPdS_S_iiii
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L36
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z9matrixMulPdS_S_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z9matrixMulPdS_S_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC9:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mat_mul.hip"
.globl _Z10readMatrixP6matrixP8_IO_FILE # -- Begin function _Z10readMatrixP6matrixP8_IO_FILE
.p2align 4, 0x90
.type _Z10readMatrixP6matrixP8_IO_FILE,@function
_Z10readMatrixP6matrixP8_IO_FILE: # @_Z10readMatrixP6matrixP8_IO_FILE
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq %rdi, %r14
movslq (%rdi), %rax
movslq 4(%rdi), %rdi
imulq %rax, %rdi
shlq $3, %rdi
callq malloc
movq %rax, 8(%r14)
cmpl $0, 4(%r14)
jle .LBB0_6
# %bb.1: # %.preheader.preheader
xorl %ebp, %ebp
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
incl %ebp
cmpl 4(%r14), %ebp
jge .LBB0_6
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
movl (%r14), %eax
testl %eax, %eax
jle .LBB0_5
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB0_2 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_4: # %.lr.ph
# Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebp, %eax
movslq %eax, %rdx
addq %r15, %rdx
shlq $3, %rdx
addq 8(%r14), %rdx
movl $.L.str, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl (%r14), %eax
incq %r15
cmpl %eax, %r15d
jl .LBB0_4
jmp .LBB0_5
.LBB0_6: # %._crit_edge17
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z10readMatrixP6matrixP8_IO_FILE, .Lfunc_end0-_Z10readMatrixP6matrixP8_IO_FILE
.cfi_endproc
# -- End function
.globl _Z11printMatrixP6matrixP8_IO_FILE # -- Begin function _Z11printMatrixP6matrixP8_IO_FILE
.p2align 4, 0x90
.type _Z11printMatrixP6matrixP8_IO_FILE,@function
_Z11printMatrixP6matrixP8_IO_FILE: # @_Z11printMatrixP6matrixP8_IO_FILE
.cfi_startproc
# %bb.0:
cmpl $0, 4(%rdi)
jle .LBB1_7
# %bb.1: # %.preheader.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
xorl %r15d, %r15d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movl $10, %edi
movq %rbx, %rsi
callq fputc@PLT
incl %r15d
cmpl 4(%r14), %r15d
jge .LBB1_6
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
movl (%r14), %eax
testl %eax, %eax
jle .LBB1_5
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB1_2 Depth=1
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movq 8(%r14), %rcx
imull %r15d, %eax
cltq
addq %r12, %rax
movsd (%rcx,%rax,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.1, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
movl (%r14), %eax
incq %r12
cmpl %eax, %r12d
jl .LBB1_4
jmp .LBB1_5
.LBB1_6:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB1_7: # %._crit_edge15
retq
.Lfunc_end1:
.size _Z11printMatrixP6matrixP8_IO_FILE, .Lfunc_end1-_Z11printMatrixP6matrixP8_IO_FILE
.cfi_endproc
# -- End function
.globl _Z24__device_stub__matrixMulPdS_S_iiii # -- Begin function _Z24__device_stub__matrixMulPdS_S_iiii
.p2align 4, 0x90
.type _Z24__device_stub__matrixMulPdS_S_iiii,@function
_Z24__device_stub__matrixMulPdS_S_iiii: # @_Z24__device_stub__matrixMulPdS_S_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9matrixMulPdS_S_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z24__device_stub__matrixMulPdS_S_iiii, .Lfunc_end2-_Z24__device_stub__matrixMulPdS_S_iiii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $3, %edi
jne .LBB3_23
# %bb.1:
movq %rsi, %r14
movq 8(%rsi), %rdi
movl $.L.str.4, %esi
callq fopen
movq %rax, %r12
movq 16(%r14), %rdi
movl $.L.str.4, %esi
callq fopen
movq %rax, %r14
leaq 20(%rsp), %rdx
leaq 16(%rsp), %rcx
movl $.L.str.5, %esi
movq %r12, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
leaq 4(%rsp), %rdx
movq %rsp, %rcx
movl $.L.str.5, %esi
movq %r14, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl 16(%rsp), %eax
cmpl 4(%rsp), %eax
jne .LBB3_24
# %bb.2:
movl 20(%rsp), %ebx
imull %ebx, %eax
movslq %eax, %rdi
shlq $3, %rdi
callq malloc
movq %rax, 24(%rsp)
testl %ebx, %ebx
jle .LBB3_8
# %bb.3: # %.preheader.i.preheader
xorl %ebp, %ebp
jmp .LBB3_4
.p2align 4, 0x90
.LBB3_7: # %._crit_edge.i
# in Loop: Header=BB3_4 Depth=1
incl %ebp
cmpl 20(%rsp), %ebp
jge .LBB3_8
.LBB3_4: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
movl 16(%rsp), %eax
testl %eax, %eax
jle .LBB3_7
# %bb.5: # %.lr.ph.i.preheader
# in Loop: Header=BB3_4 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_6: # %.lr.ph.i
# Parent Loop BB3_4 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebp, %eax
movslq %eax, %rdx
addq %r15, %rdx
shlq $3, %rdx
addq 24(%rsp), %rdx
movl $.L.str, %esi
movq %r12, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl 16(%rsp), %eax
incq %r15
cmpl %eax, %r15d
jl .LBB3_6
jmp .LBB3_7
.LBB3_8: # %_Z10readMatrixP6matrixP8_IO_FILE.exit
movslq (%rsp), %rdi
movslq 4(%rsp), %rbx
imulq %rbx, %rdi
shlq $3, %rdi
callq malloc
movq %rax, 8(%rsp)
testq %rbx, %rbx
jle .LBB3_14
# %bb.9: # %.preheader.i23.preheader
xorl %ebp, %ebp
jmp .LBB3_10
.p2align 4, 0x90
.LBB3_13: # %._crit_edge.i25
# in Loop: Header=BB3_10 Depth=1
incl %ebp
cmpl 4(%rsp), %ebp
jge .LBB3_14
.LBB3_10: # %.preheader.i23
# =>This Loop Header: Depth=1
# Child Loop BB3_12 Depth 2
movl (%rsp), %eax
testl %eax, %eax
jle .LBB3_13
# %bb.11: # %.lr.ph.i26.preheader
# in Loop: Header=BB3_10 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_12: # %.lr.ph.i26
# Parent Loop BB3_10 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebp, %eax
movslq %eax, %rdx
addq %r15, %rdx
shlq $3, %rdx
addq 8(%rsp), %rdx
movl $.L.str, %esi
movq %r14, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl (%rsp), %eax
incq %r15
cmpl %eax, %r15d
jl .LBB3_12
jmp .LBB3_13
.LBB3_14: # %_Z10readMatrixP6matrixP8_IO_FILE.exit28
movq %r14, 96(%rsp) # 8-byte Spill
movq %r12, 104(%rsp) # 8-byte Spill
movslq 20(%rsp), %rbx
movl %ebx, %r13d
movl (%rsp), %r15d
movl %r15d, %eax
imull %ebx, %eax
movslq %eax, %r12
shlq $3, %r12
movq %r12, %rdi
callq malloc
movq %rax, %r14
movslq 16(%rsp), %rsi
imulq %rbx, %rsi
shlq $3, %rsi
leaq 48(%rsp), %rdi
callq hipMalloc
movslq 4(%rsp), %rax
movslq (%rsp), %rsi
imulq %rax, %rsi
shlq $3, %rsi
leaq 40(%rsp), %rdi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 48(%rsp), %rdi
movq 24(%rsp), %rsi
movslq 20(%rsp), %rax
movslq 16(%rsp), %rdx
imulq %rax, %rdx
shlq $3, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq 8(%rsp), %rsi
movslq 4(%rsp), %rax
movslq (%rsp), %rdx
imulq %rax, %rdx
shlq $3, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
xorl %esi, %esi
movq %r12, %rdx
callq hipMemset
movl (%rsp), %eax
addl $31, %eax
shrl $5, %eax
movl 20(%rsp), %ebp
addl $31, %ebp
shrl $5, %ebp
shlq $32, %rbp
orq %rax, %rbp
callq clock
movq %rax, 88(%rsp) # 8-byte Spill
movabsq $137438953504, %rdx # imm = 0x2000000020
movq %rbp, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_16
# %bb.15:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movl 16(%rsp), %esi
movl 20(%rsp), %edi
movl (%rsp), %r8d
movl 4(%rsp), %r9d
movq %rax, 184(%rsp)
movq %rcx, 176(%rsp)
movq %rdx, 168(%rsp)
movl %edi, 68(%rsp)
movl %r9d, 64(%rsp)
movl %esi, 60(%rsp)
movl %r8d, 56(%rsp)
leaq 184(%rsp), %rax
movq %rax, 192(%rsp)
leaq 176(%rsp), %rax
movq %rax, 200(%rsp)
leaq 168(%rsp), %rax
movq %rax, 208(%rsp)
leaq 68(%rsp), %rax
movq %rax, 216(%rsp)
leaq 64(%rsp), %rax
movq %rax, 224(%rsp)
leaq 60(%rsp), %rax
movq %rax, 232(%rsp)
leaq 56(%rsp), %rax
movq %rax, 240(%rsp)
leaq 152(%rsp), %rdi
leaq 136(%rsp), %rsi
leaq 128(%rsp), %rdx
leaq 120(%rsp), %rcx
callq __hipPopCallConfiguration
movq 152(%rsp), %rsi
movl 160(%rsp), %edx
movq 136(%rsp), %rcx
movl 144(%rsp), %r8d
leaq 192(%rsp), %r9
movl $_Z9matrixMulPdS_S_iiii, %edi
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_16:
callq hipDeviceSynchronize
callq clock
movq %rax, 80(%rsp) # 8-byte Spill
movq 32(%rsp), %rsi
movq %r14, 72(%rsp) # 8-byte Spill
movq %r14, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.L.str.7, %edi
movl $.L.str.8, %esi
callq fopen
movq %rax, %r12
movq %r13, 112(%rsp) # 8-byte Spill
testl %r13d, %r13d
jle .LBB3_22
# %bb.17: # %.preheader.i29.preheader
xorl %ebp, %ebp
xorl %r13d, %r13d
jmp .LBB3_18
.p2align 4, 0x90
.LBB3_21: # %._crit_edge.i30
# in Loop: Header=BB3_18 Depth=1
movl $10, %edi
movq %r12, %rsi
callq fputc@PLT
incq %r13
addl %r15d, %ebp
cmpq 112(%rsp), %r13 # 8-byte Folded Reload
je .LBB3_22
.LBB3_18: # %.preheader.i29
# =>This Loop Header: Depth=1
# Child Loop BB3_20 Depth 2
testl %r15d, %r15d
jle .LBB3_21
# %bb.19: # %.lr.ph.i31.preheader
# in Loop: Header=BB3_18 Depth=1
movl %ebp, %eax
movq 72(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_20: # %.lr.ph.i31
# Parent Loop BB3_18 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rbx,%r14,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.1, %esi
movq %r12, %rdi
movb $1, %al
callq fprintf
incq %r14
cmpq %r14, %r15
jne .LBB3_20
jmp .LBB3_21
.LBB3_22: # %_Z11printMatrixP6matrixP8_IO_FILE.exit
movq 80(%rsp), %rax # 8-byte Reload
subq 88(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI3_0(%rip), %xmm0
movl $.L.str.9, %edi
movb $1, %al
callq printf
movq 104(%rsp), %rdi # 8-byte Reload
callq fclose
movq 96(%rsp), %rdi # 8-byte Reload
callq fclose
movq %r12, %rdi
callq fclose
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq free
movq 8(%rsp), %rdi
callq free
movq 72(%rsp), %rdi # 8-byte Reload
callq free
xorl %eax, %eax
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_23:
.cfi_def_cfa_offset 304
movl $.Lstr.1, %edi
callq puts@PLT
movl $1, %edi
callq exit
.LBB3_24:
movl $.Lstr, %edi
callq puts@PLT
movq %r12, %rdi
callq fclose
movq %r14, %rdi
callq fclose
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9matrixMulPdS_S_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%lf"
.size .L.str, 4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%lf "
.size .L.str.1, 5
.type _Z9matrixMulPdS_S_iiii,@object # @_Z9matrixMulPdS_S_iiii
.section .rodata,"a",@progbits
.globl _Z9matrixMulPdS_S_iiii
.p2align 3, 0x0
_Z9matrixMulPdS_S_iiii:
.quad _Z24__device_stub__matrixMulPdS_S_iiii
.size _Z9matrixMulPdS_S_iiii, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "r"
.size .L.str.4, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d %d"
.size .L.str.5, 6
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "result.txt"
.size .L.str.7, 11
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "w"
.size .L.str.8, 2
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Elapsed time: %.5lf seconds\n"
.size .L.str.9, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9matrixMulPdS_S_iiii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "It is not possible to do matrix multiplication. Check matrices number of rows and cols."
.size .Lstr, 88
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Parameter error."
.size .Lstr.1, 17
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__matrixMulPdS_S_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9matrixMulPdS_S_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,float var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20) {
comp += var_2 - (var_3 + +1.4889E-43f);
if (comp <= (+1.5026E25f + atanf(var_4 * expf(var_5 / var_6 / -1.8817E35f)))) {
float tmp_1 = +1.8395E9f;
float tmp_2 = -0.0f;
comp += tmp_2 * tmp_1 * var_7 + (var_8 / asinf(var_9 / fabsf(-1.3023E-42f)));
comp = (var_10 - sqrtf(-1.1907E35f));
}
if (comp < +1.3739E-41f - var_11) {
comp = (var_12 * (+1.6612E34f / -1.7853E8f / +1.4702E-43f));
comp += var_13 / var_14;
comp += var_15 * -0.0f * (var_16 * var_17 / asinf(floorf((var_18 - +1.4509E-36f - -1.6745E2f))));
}
for (int i=0; i < var_1; ++i) {
comp += (+1.2415E20f - asinf(+0.0f / (var_19 - var_20 * -1.2148E-35f)));
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
float tmp_3 = atof(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21);
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_0005624d_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z45__device_stub__Z7computefiffffffffffffffffffffifffffffffffffffffff
.type _Z45__device_stub__Z7computefiffffffffffffffffffffifffffffffffffffffff, @function
_Z45__device_stub__Z7computefiffffffffffffffffffffifffffffffffffffffff:
.LFB2083:
.cfi_startproc
endbr64
subq $296, %rsp
.cfi_def_cfa_offset 304
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movss %xmm1, 36(%rsp)
movss %xmm2, 32(%rsp)
movss %xmm3, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 20(%rsp)
movss %xmm6, 16(%rsp)
movss %xmm7, 12(%rsp)
movq %fs:40, %rax
movq %rax, 280(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 304(%rsp), %rax
movq %rax, 184(%rsp)
leaq 312(%rsp), %rax
movq %rax, 192(%rsp)
leaq 320(%rsp), %rax
movq %rax, 200(%rsp)
leaq 328(%rsp), %rax
movq %rax, 208(%rsp)
leaq 336(%rsp), %rax
movq %rax, 216(%rsp)
leaq 344(%rsp), %rax
movq %rax, 224(%rsp)
leaq 352(%rsp), %rax
movq %rax, 232(%rsp)
leaq 360(%rsp), %rax
movq %rax, 240(%rsp)
leaq 368(%rsp), %rax
movq %rax, 248(%rsp)
leaq 376(%rsp), %rax
movq %rax, 256(%rsp)
leaq 384(%rsp), %rax
movq %rax, 264(%rsp)
leaq 392(%rsp), %rax
movq %rax, 272(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $296, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 312
pushq 56(%rsp)
.cfi_def_cfa_offset 320
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7computefifffffffffffffffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 304
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z45__device_stub__Z7computefiffffffffffffffffffffifffffffffffffffffff, .-_Z45__device_stub__Z7computefiffffffffffffffffffffifffffffffffffffffff
.globl _Z7computefifffffffffffffffffff
.type _Z7computefifffffffffffffffffff, @function
_Z7computefifffffffffffffffffff:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movss 200(%rsp), %xmm8
movss %xmm8, 88(%rsp)
movss 192(%rsp), %xmm8
movss %xmm8, 80(%rsp)
movss 184(%rsp), %xmm8
movss %xmm8, 72(%rsp)
movss 176(%rsp), %xmm8
movss %xmm8, 64(%rsp)
movss 168(%rsp), %xmm8
movss %xmm8, 56(%rsp)
movss 160(%rsp), %xmm8
movss %xmm8, 48(%rsp)
movss 152(%rsp), %xmm8
movss %xmm8, 40(%rsp)
movss 144(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 136(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 128(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 120(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 112(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z45__device_stub__Z7computefiffffffffffffffffffffifffffffffffffffffff
addq $104, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefifffffffffffffffffff, .-_Z7computefifffffffffffffffffff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $200, %rsp
.cfi_def_cfa_offset 224
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 152(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 24(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 144(%rsp)
movq 32(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 136(%rsp)
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 128(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 120(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 112(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 104(%rsp)
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 96(%rsp)
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 120(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 128(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 136(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 144(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 152(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 160(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movq 168(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, (%rsp)
movl $1, 180(%rsp)
movl $1, 184(%rsp)
movl $1, 168(%rsp)
movl $1, 172(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 180(%rsp), %rdx
movl $1, %ecx
movq 168(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 152(%rsp), %xmm0
pxor %xmm1, %xmm1
cvtsd2ss (%rsp), %xmm1
leaq -96(%rsp), %rsp
.cfi_def_cfa_offset 320
movss %xmm1, 88(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 104(%rsp), %xmm1
movss %xmm1, 80(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 112(%rsp), %xmm1
movss %xmm1, 72(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 120(%rsp), %xmm1
movss %xmm1, 64(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 128(%rsp), %xmm1
movss %xmm1, 56(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 136(%rsp), %xmm1
movss %xmm1, 48(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 144(%rsp), %xmm1
movss %xmm1, 40(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 152(%rsp), %xmm1
movss %xmm1, 32(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 160(%rsp), %xmm1
movss %xmm1, 24(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 168(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 176(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 184(%rsp), %xmm1
movss %xmm1, (%rsp)
pxor %xmm7, %xmm7
cvtsd2ss 192(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 200(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtsd2ss 208(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 216(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 224(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 232(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 240(%rsp), %xmm1
movl %ebp, %edi
call _Z45__device_stub__Z7computefiffffffffffffffffffffifffffffffffffffffff
addq $96, %rsp
.cfi_def_cfa_offset 224
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z7computefifffffffffffffffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefifffffffffffffffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,float var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20) {
comp += var_2 - (var_3 + +1.4889E-43f);
if (comp <= (+1.5026E25f + atanf(var_4 * expf(var_5 / var_6 / -1.8817E35f)))) {
float tmp_1 = +1.8395E9f;
float tmp_2 = -0.0f;
comp += tmp_2 * tmp_1 * var_7 + (var_8 / asinf(var_9 / fabsf(-1.3023E-42f)));
comp = (var_10 - sqrtf(-1.1907E35f));
}
if (comp < +1.3739E-41f - var_11) {
comp = (var_12 * (+1.6612E34f / -1.7853E8f / +1.4702E-43f));
comp += var_13 / var_14;
comp += var_15 * -0.0f * (var_16 * var_17 / asinf(floorf((var_18 - +1.4509E-36f - -1.6745E2f))));
}
for (int i=0; i < var_1; ++i) {
comp += (+1.2415E20f - asinf(+0.0f / (var_19 - var_20 * -1.2148E-35f)));
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
float tmp_3 = atof(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21);
cudaDeviceSynchronize();
return 0;
} | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,float var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20) {
comp += var_2 - (var_3 + +1.4889E-43f);
if (comp <= (+1.5026E25f + atanf(var_4 * expf(var_5 / var_6 / -1.8817E35f)))) {
float tmp_1 = +1.8395E9f;
float tmp_2 = -0.0f;
comp += tmp_2 * tmp_1 * var_7 + (var_8 / asinf(var_9 / fabsf(-1.3023E-42f)));
comp = (var_10 - sqrtf(-1.1907E35f));
}
if (comp < +1.3739E-41f - var_11) {
comp = (var_12 * (+1.6612E34f / -1.7853E8f / +1.4702E-43f));
comp += var_13 / var_14;
comp += var_15 * -0.0f * (var_16 * var_17 / asinf(floorf((var_18 - +1.4509E-36f - -1.6745E2f))));
}
for (int i=0; i < var_1; ++i) {
comp += (+1.2415E20f - asinf(+0.0f / (var_19 - var_20 * -1.2148E-35f)));
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
float tmp_3 = atof(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21);
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,float var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20) {
comp += var_2 - (var_3 + +1.4889E-43f);
if (comp <= (+1.5026E25f + atanf(var_4 * expf(var_5 / var_6 / -1.8817E35f)))) {
float tmp_1 = +1.8395E9f;
float tmp_2 = -0.0f;
comp += tmp_2 * tmp_1 * var_7 + (var_8 / asinf(var_9 / fabsf(-1.3023E-42f)));
comp = (var_10 - sqrtf(-1.1907E35f));
}
if (comp < +1.3739E-41f - var_11) {
comp = (var_12 * (+1.6612E34f / -1.7853E8f / +1.4702E-43f));
comp += var_13 / var_14;
comp += var_15 * -0.0f * (var_16 * var_17 / asinf(floorf((var_18 - +1.4509E-36f - -1.6745E2f))));
}
for (int i=0; i < var_1; ++i) {
comp += (+1.2415E20f - asinf(+0.0f / (var_19 - var_20 * -1.2148E-35f)));
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
float tmp_3 = atof(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21);
hipDeviceSynchronize();
return 0;
} | .text
.file "test.hip"
.globl _Z22__device_stub__computefifffffffffffffffffff # -- Begin function _Z22__device_stub__computefifffffffffffffffffff
.p2align 4, 0x90
.type _Z22__device_stub__computefifffffffffffffffffff,@function
_Z22__device_stub__computefifffffffffffffffffff: # @_Z22__device_stub__computefifffffffffffffffffff
.cfi_startproc
# %bb.0:
subq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 272
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movss %xmm1, 36(%rsp)
movss %xmm2, 32(%rsp)
movss %xmm3, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 20(%rsp)
movss %xmm6, 16(%rsp)
movss %xmm7, 12(%rsp)
leaq 44(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rax
movq %rax, 104(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 272(%rsp), %rax
movq %rax, 168(%rsp)
leaq 280(%rsp), %rax
movq %rax, 176(%rsp)
leaq 288(%rsp), %rax
movq %rax, 184(%rsp)
leaq 296(%rsp), %rax
movq %rax, 192(%rsp)
leaq 304(%rsp), %rax
movq %rax, 200(%rsp)
leaq 312(%rsp), %rax
movq %rax, 208(%rsp)
leaq 320(%rsp), %rax
movq %rax, 216(%rsp)
leaq 328(%rsp), %rax
movq %rax, 224(%rsp)
leaq 336(%rsp), %rax
movq %rax, 232(%rsp)
leaq 344(%rsp), %rax
movq %rax, 240(%rsp)
leaq 352(%rsp), %rax
movq %rax, 248(%rsp)
leaq 360(%rsp), %rax
movq %rax, 256(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7computefifffffffffffffffffff, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $280, %rsp # imm = 0x118
.cfi_adjust_cfa_offset -280
retq
.Lfunc_end0:
.size _Z22__device_stub__computefifffffffffffffffffff, .Lfunc_end0-_Z22__device_stub__computefifffffffffffffffffff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 256(%rsp) # 8-byte Spill
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 24(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 248(%rsp) # 8-byte Spill
movq 32(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 240(%rsp) # 8-byte Spill
movq 40(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 232(%rsp) # 8-byte Spill
movq 48(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 128(%rsp) # 8-byte Spill
movq 56(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 120(%rsp) # 8-byte Spill
movq 64(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 112(%rsp) # 8-byte Spill
movq 72(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 104(%rsp) # 8-byte Spill
movq 80(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 224(%rsp) # 8-byte Spill
movq 88(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 216(%rsp) # 8-byte Spill
movq 96(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 208(%rsp) # 8-byte Spill
movq 104(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 200(%rsp) # 8-byte Spill
movq 112(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 192(%rsp) # 8-byte Spill
movq 120(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 184(%rsp) # 8-byte Spill
movq 128(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 176(%rsp) # 8-byte Spill
movq 136(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 168(%rsp) # 8-byte Spill
movq 144(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 160(%rsp) # 8-byte Spill
movq 152(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 152(%rsp) # 8-byte Spill
movq 160(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 144(%rsp) # 8-byte Spill
movq 168(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 136(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movsd 136(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm8
movsd 144(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm9
movsd 152(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm10
movsd 160(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm11
movsd 168(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm12
movsd 176(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm13
movsd 184(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm14
movsd 192(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm15
movsd 200(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm4
movsd 208(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm5
movsd 216(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm6
movsd 224(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm7
movsd 104(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 104(%rsp) # 4-byte Spill
movsd 112(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 112(%rsp) # 4-byte Spill
movsd 120(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 120(%rsp) # 4-byte Spill
movsd 128(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 128(%rsp) # 4-byte Spill
movsd 232(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm3
movsd 240(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm2
movsd 248(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm1
movsd 256(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm8, 88(%rsp)
movss %xmm9, 80(%rsp)
movss %xmm10, 72(%rsp)
movss %xmm11, 64(%rsp)
movss %xmm12, 56(%rsp)
movss %xmm13, 48(%rsp)
movss %xmm14, 40(%rsp)
movss %xmm15, 32(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 16(%rsp)
movss %xmm6, 8(%rsp)
movss %xmm7, (%rsp)
movl %ebx, %edi
movss 128(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss 120(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
movss 112(%rsp), %xmm6 # 4-byte Reload
# xmm6 = mem[0],zero,zero,zero
movss 104(%rsp), %xmm7 # 4-byte Reload
# xmm7 = mem[0],zero,zero,zero
callq _Z22__device_stub__computefifffffffffffffffffff
.LBB2_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefifffffffffffffffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefifffffffffffffffffff,@object # @_Z7computefifffffffffffffffffff
.section .rodata,"a",@progbits
.globl _Z7computefifffffffffffffffffff
.p2align 3, 0x0
_Z7computefifffffffffffffffffff:
.quad _Z22__device_stub__computefifffffffffffffffffff
.size _Z7computefifffffffffffffffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefifffffffffffffffffff"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefifffffffffffffffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefifffffffffffffffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005624d_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z45__device_stub__Z7computefiffffffffffffffffffffifffffffffffffffffff
.type _Z45__device_stub__Z7computefiffffffffffffffffffffifffffffffffffffffff, @function
_Z45__device_stub__Z7computefiffffffffffffffffffffifffffffffffffffffff:
.LFB2083:
.cfi_startproc
endbr64
subq $296, %rsp
.cfi_def_cfa_offset 304
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movss %xmm1, 36(%rsp)
movss %xmm2, 32(%rsp)
movss %xmm3, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 20(%rsp)
movss %xmm6, 16(%rsp)
movss %xmm7, 12(%rsp)
movq %fs:40, %rax
movq %rax, 280(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 304(%rsp), %rax
movq %rax, 184(%rsp)
leaq 312(%rsp), %rax
movq %rax, 192(%rsp)
leaq 320(%rsp), %rax
movq %rax, 200(%rsp)
leaq 328(%rsp), %rax
movq %rax, 208(%rsp)
leaq 336(%rsp), %rax
movq %rax, 216(%rsp)
leaq 344(%rsp), %rax
movq %rax, 224(%rsp)
leaq 352(%rsp), %rax
movq %rax, 232(%rsp)
leaq 360(%rsp), %rax
movq %rax, 240(%rsp)
leaq 368(%rsp), %rax
movq %rax, 248(%rsp)
leaq 376(%rsp), %rax
movq %rax, 256(%rsp)
leaq 384(%rsp), %rax
movq %rax, 264(%rsp)
leaq 392(%rsp), %rax
movq %rax, 272(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $296, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 312
pushq 56(%rsp)
.cfi_def_cfa_offset 320
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7computefifffffffffffffffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 304
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z45__device_stub__Z7computefiffffffffffffffffffffifffffffffffffffffff, .-_Z45__device_stub__Z7computefiffffffffffffffffffffifffffffffffffffffff
.globl _Z7computefifffffffffffffffffff
.type _Z7computefifffffffffffffffffff, @function
_Z7computefifffffffffffffffffff:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movss 200(%rsp), %xmm8
movss %xmm8, 88(%rsp)
movss 192(%rsp), %xmm8
movss %xmm8, 80(%rsp)
movss 184(%rsp), %xmm8
movss %xmm8, 72(%rsp)
movss 176(%rsp), %xmm8
movss %xmm8, 64(%rsp)
movss 168(%rsp), %xmm8
movss %xmm8, 56(%rsp)
movss 160(%rsp), %xmm8
movss %xmm8, 48(%rsp)
movss 152(%rsp), %xmm8
movss %xmm8, 40(%rsp)
movss 144(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 136(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 128(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 120(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 112(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z45__device_stub__Z7computefiffffffffffffffffffffifffffffffffffffffff
addq $104, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefifffffffffffffffffff, .-_Z7computefifffffffffffffffffff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $200, %rsp
.cfi_def_cfa_offset 224
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 152(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 24(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 144(%rsp)
movq 32(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 136(%rsp)
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 128(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 120(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 112(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 104(%rsp)
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 96(%rsp)
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 120(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 128(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 136(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 144(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 152(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 160(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movq 168(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, (%rsp)
movl $1, 180(%rsp)
movl $1, 184(%rsp)
movl $1, 168(%rsp)
movl $1, 172(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 180(%rsp), %rdx
movl $1, %ecx
movq 168(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 152(%rsp), %xmm0
pxor %xmm1, %xmm1
cvtsd2ss (%rsp), %xmm1
leaq -96(%rsp), %rsp
.cfi_def_cfa_offset 320
movss %xmm1, 88(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 104(%rsp), %xmm1
movss %xmm1, 80(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 112(%rsp), %xmm1
movss %xmm1, 72(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 120(%rsp), %xmm1
movss %xmm1, 64(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 128(%rsp), %xmm1
movss %xmm1, 56(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 136(%rsp), %xmm1
movss %xmm1, 48(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 144(%rsp), %xmm1
movss %xmm1, 40(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 152(%rsp), %xmm1
movss %xmm1, 32(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 160(%rsp), %xmm1
movss %xmm1, 24(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 168(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 176(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 184(%rsp), %xmm1
movss %xmm1, (%rsp)
pxor %xmm7, %xmm7
cvtsd2ss 192(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 200(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtsd2ss 208(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 216(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 224(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 232(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 240(%rsp), %xmm1
movl %ebp, %edi
call _Z45__device_stub__Z7computefiffffffffffffffffffffifffffffffffffffffff
addq $96, %rsp
.cfi_def_cfa_offset 224
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z7computefifffffffffffffffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefifffffffffffffffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl _Z22__device_stub__computefifffffffffffffffffff # -- Begin function _Z22__device_stub__computefifffffffffffffffffff
.p2align 4, 0x90
.type _Z22__device_stub__computefifffffffffffffffffff,@function
_Z22__device_stub__computefifffffffffffffffffff: # @_Z22__device_stub__computefifffffffffffffffffff
.cfi_startproc
# %bb.0:
subq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 272
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movss %xmm1, 36(%rsp)
movss %xmm2, 32(%rsp)
movss %xmm3, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 20(%rsp)
movss %xmm6, 16(%rsp)
movss %xmm7, 12(%rsp)
leaq 44(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rax
movq %rax, 104(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 272(%rsp), %rax
movq %rax, 168(%rsp)
leaq 280(%rsp), %rax
movq %rax, 176(%rsp)
leaq 288(%rsp), %rax
movq %rax, 184(%rsp)
leaq 296(%rsp), %rax
movq %rax, 192(%rsp)
leaq 304(%rsp), %rax
movq %rax, 200(%rsp)
leaq 312(%rsp), %rax
movq %rax, 208(%rsp)
leaq 320(%rsp), %rax
movq %rax, 216(%rsp)
leaq 328(%rsp), %rax
movq %rax, 224(%rsp)
leaq 336(%rsp), %rax
movq %rax, 232(%rsp)
leaq 344(%rsp), %rax
movq %rax, 240(%rsp)
leaq 352(%rsp), %rax
movq %rax, 248(%rsp)
leaq 360(%rsp), %rax
movq %rax, 256(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7computefifffffffffffffffffff, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $280, %rsp # imm = 0x118
.cfi_adjust_cfa_offset -280
retq
.Lfunc_end0:
.size _Z22__device_stub__computefifffffffffffffffffff, .Lfunc_end0-_Z22__device_stub__computefifffffffffffffffffff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 256(%rsp) # 8-byte Spill
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 24(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 248(%rsp) # 8-byte Spill
movq 32(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 240(%rsp) # 8-byte Spill
movq 40(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 232(%rsp) # 8-byte Spill
movq 48(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 128(%rsp) # 8-byte Spill
movq 56(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 120(%rsp) # 8-byte Spill
movq 64(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 112(%rsp) # 8-byte Spill
movq 72(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 104(%rsp) # 8-byte Spill
movq 80(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 224(%rsp) # 8-byte Spill
movq 88(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 216(%rsp) # 8-byte Spill
movq 96(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 208(%rsp) # 8-byte Spill
movq 104(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 200(%rsp) # 8-byte Spill
movq 112(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 192(%rsp) # 8-byte Spill
movq 120(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 184(%rsp) # 8-byte Spill
movq 128(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 176(%rsp) # 8-byte Spill
movq 136(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 168(%rsp) # 8-byte Spill
movq 144(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 160(%rsp) # 8-byte Spill
movq 152(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 152(%rsp) # 8-byte Spill
movq 160(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 144(%rsp) # 8-byte Spill
movq 168(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 136(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movsd 136(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm8
movsd 144(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm9
movsd 152(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm10
movsd 160(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm11
movsd 168(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm12
movsd 176(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm13
movsd 184(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm14
movsd 192(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm15
movsd 200(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm4
movsd 208(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm5
movsd 216(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm6
movsd 224(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm7
movsd 104(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 104(%rsp) # 4-byte Spill
movsd 112(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 112(%rsp) # 4-byte Spill
movsd 120(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 120(%rsp) # 4-byte Spill
movsd 128(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 128(%rsp) # 4-byte Spill
movsd 232(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm3
movsd 240(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm2
movsd 248(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm1
movsd 256(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm8, 88(%rsp)
movss %xmm9, 80(%rsp)
movss %xmm10, 72(%rsp)
movss %xmm11, 64(%rsp)
movss %xmm12, 56(%rsp)
movss %xmm13, 48(%rsp)
movss %xmm14, 40(%rsp)
movss %xmm15, 32(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 16(%rsp)
movss %xmm6, 8(%rsp)
movss %xmm7, (%rsp)
movl %ebx, %edi
movss 128(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss 120(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
movss 112(%rsp), %xmm6 # 4-byte Reload
# xmm6 = mem[0],zero,zero,zero
movss 104(%rsp), %xmm7 # 4-byte Reload
# xmm7 = mem[0],zero,zero,zero
callq _Z22__device_stub__computefifffffffffffffffffff
.LBB2_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefifffffffffffffffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefifffffffffffffffffff,@object # @_Z7computefifffffffffffffffffff
.section .rodata,"a",@progbits
.globl _Z7computefifffffffffffffffffff
.p2align 3, 0x0
_Z7computefifffffffffffffffffff:
.quad _Z22__device_stub__computefifffffffffffffffffff
.size _Z7computefifffffffffffffffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefifffffffffffffffffff"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefifffffffffffffffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefifffffffffffffffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //
// Created by bruno on 2021/7/2.
//
#include <stdio.h>
int main(void)
{
printf("Hello World from cpu \n");
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //
// Created by bruno on 2021/7/2.
//
#include <stdio.h>
int main(void)
{
printf("Hello World from cpu \n");
} | .file "tmpxft_0013a953_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World from cpu \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //
// Created by bruno on 2021/7/2.
//
#include <stdio.h>
int main(void)
{
printf("Hello World from cpu \n");
} | //
// Created by bruno on 2021/7/2.
//
#include <hip/hip_runtime.h>
#include <stdio.h>
int main(void)
{
printf("Hello World from cpu \n");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //
// Created by bruno on 2021/7/2.
//
#include <hip/hip_runtime.h>
#include <stdio.h>
int main(void)
{
printf("Hello World from cpu \n");
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //
// Created by bruno on 2021/7/2.
//
#include <hip/hip_runtime.h>
#include <stdio.h>
int main(void)
{
printf("Hello World from cpu \n");
} | .text
.file "hello.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World from cpu "
.size .Lstr, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013a953_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World from cpu \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hello.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World from cpu "
.size .Lstr, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // add two vectors
#include <stdio.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <curand_kernel.h>
#define N (2048*2048)
const int THREADS_PER_BLOCK = 512;
__global__ void add(int npts,int *a,int *b,int *c){
int i = threadIdx.x + blockIdx.x*blockDim.x; // combining blocks and threads; this gives an absolute index
if(i<npts){
c[i] = a[i] + b[i];
}
}
int main(void){
const int SIZE = N*sizeof(int);
int *a = (int *)malloc(SIZE);
int *b = (int *)malloc(SIZE);
int *c = (int *)malloc(SIZE);
int *a_dev,*b_dev,*c_dev;
int i=0;
for(i=0;i<N;i++){
a[i] = -1*i;
b[i] = 2*i;
}
cudaMalloc( (void**)&a_dev,SIZE);
cudaMalloc( (void**)&b_dev,SIZE);
cudaMalloc( (void**)&c_dev,SIZE);
cudaMemcpy(a_dev,a,SIZE,cudaMemcpyHostToDevice);
cudaMemcpy(b_dev,b,SIZE,cudaMemcpyHostToDevice);
add<<<(N+THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(N,a_dev,b_dev,c_dev);
cudaMemcpy(c,c_dev,SIZE,cudaMemcpyDeviceToHost);
for(i=0;i<N;i++){
printf("i = %d, %d + %d = %d \n",i,a[i],b[i],c[i]);
}
free(a);
free(b);
free(c);
cudaFree(a_dev);
cudaFree(b_dev);
cudaFree(c_dev);
return 0;
} | code for sm_80
Function : _Z3addiPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // add two vectors
#include <stdio.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <curand_kernel.h>
#define N (2048*2048)
const int THREADS_PER_BLOCK = 512;
__global__ void add(int npts,int *a,int *b,int *c){
int i = threadIdx.x + blockIdx.x*blockDim.x; // combining blocks and threads; this gives an absolute index
if(i<npts){
c[i] = a[i] + b[i];
}
}
int main(void){
const int SIZE = N*sizeof(int);
int *a = (int *)malloc(SIZE);
int *b = (int *)malloc(SIZE);
int *c = (int *)malloc(SIZE);
int *a_dev,*b_dev,*c_dev;
int i=0;
for(i=0;i<N;i++){
a[i] = -1*i;
b[i] = 2*i;
}
cudaMalloc( (void**)&a_dev,SIZE);
cudaMalloc( (void**)&b_dev,SIZE);
cudaMalloc( (void**)&c_dev,SIZE);
cudaMemcpy(a_dev,a,SIZE,cudaMemcpyHostToDevice);
cudaMemcpy(b_dev,b,SIZE,cudaMemcpyHostToDevice);
add<<<(N+THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(N,a_dev,b_dev,c_dev);
cudaMemcpy(c,c_dev,SIZE,cudaMemcpyDeviceToHost);
for(i=0;i<N;i++){
printf("i = %d, %d + %d = %d \n",i,a[i],b[i],c[i]);
}
free(a);
free(b);
free(c);
cudaFree(a_dev);
cudaFree(b_dev);
cudaFree(c_dev);
return 0;
} | .file "tmpxft_000900b4_00000000-6_add_vectors.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2274:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2274:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3addiPiS_S_iPiS_S_
.type _Z27__device_stub__Z3addiPiS_S_iPiS_S_, @function
_Z27__device_stub__Z3addiPiS_S_iPiS_S_:
.LFB2296:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addiPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2296:
.size _Z27__device_stub__Z3addiPiS_S_iPiS_S_, .-_Z27__device_stub__Z3addiPiS_S_iPiS_S_
.globl _Z3addiPiS_S_
.type _Z3addiPiS_S_, @function
_Z3addiPiS_S_:
.LFB2297:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3addiPiS_S_iPiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2297:
.size _Z3addiPiS_S_, .-_Z3addiPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "i = %d, %d + %d = %d \n"
.text
.globl main
.type main, @function
main:
.LFB2271:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $16777216, %edi
call malloc@PLT
movq %rax, %r12
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbp
movl $16777216, %edi
call malloc@PLT
movq %rax, %r13
movl $0, %eax
.L12:
movl %eax, %edx
negl %edx
movl %edx, (%r12,%rax,4)
leal (%rax,%rax), %edx
movl %edx, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $4194304, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $16777216, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16777216, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl $8192, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $16777216, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %r14
.L14:
movl (%r12,%rbx,4), %ecx
movl 0(%r13,%rbx,4), %r9d
movl 0(%rbp,%rbx,4), %r8d
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $4194304, %rbx
jne .L14
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movl $4194304, %edi
call _Z27__device_stub__Z3addiPiS_S_iPiS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2271:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addiPiS_S_"
.LC2:
.string "precalc_xorwow_matrix"
.LC3:
.string "precalc_xorwow_offset_matrix"
.LC4:
.string "mrg32k3aM1"
.LC5:
.string "mrg32k3aM2"
.LC6:
.string "mrg32k3aM1SubSeq"
.LC7:
.string "mrg32k3aM2SubSeq"
.LC8:
.string "mrg32k3aM1Seq"
.LC9:
.string "mrg32k3aM2Seq"
.LC10:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2299:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiPiS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2299:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // add two vectors
#include <stdio.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <curand_kernel.h>
#define N (2048*2048)
const int THREADS_PER_BLOCK = 512;
__global__ void add(int npts,int *a,int *b,int *c){
int i = threadIdx.x + blockIdx.x*blockDim.x; // combining blocks and threads; this gives an absolute index
if(i<npts){
c[i] = a[i] + b[i];
}
}
int main(void){
const int SIZE = N*sizeof(int);
int *a = (int *)malloc(SIZE);
int *b = (int *)malloc(SIZE);
int *c = (int *)malloc(SIZE);
int *a_dev,*b_dev,*c_dev;
int i=0;
for(i=0;i<N;i++){
a[i] = -1*i;
b[i] = 2*i;
}
cudaMalloc( (void**)&a_dev,SIZE);
cudaMalloc( (void**)&b_dev,SIZE);
cudaMalloc( (void**)&c_dev,SIZE);
cudaMemcpy(a_dev,a,SIZE,cudaMemcpyHostToDevice);
cudaMemcpy(b_dev,b,SIZE,cudaMemcpyHostToDevice);
add<<<(N+THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(N,a_dev,b_dev,c_dev);
cudaMemcpy(c,c_dev,SIZE,cudaMemcpyDeviceToHost);
for(i=0;i<N;i++){
printf("i = %d, %d + %d = %d \n",i,a[i],b[i],c[i]);
}
free(a);
free(b);
free(c);
cudaFree(a_dev);
cudaFree(b_dev);
cudaFree(c_dev);
return 0;
} | // add two vectors
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
#define N (2048*2048)
const int THREADS_PER_BLOCK = 512;
__global__ void add(int npts,int *a,int *b,int *c){
int i = threadIdx.x + blockIdx.x*blockDim.x; // combining blocks and threads; this gives an absolute index
if(i<npts){
c[i] = a[i] + b[i];
}
}
int main(void){
const int SIZE = N*sizeof(int);
int *a = (int *)malloc(SIZE);
int *b = (int *)malloc(SIZE);
int *c = (int *)malloc(SIZE);
int *a_dev,*b_dev,*c_dev;
int i=0;
for(i=0;i<N;i++){
a[i] = -1*i;
b[i] = 2*i;
}
hipMalloc( (void**)&a_dev,SIZE);
hipMalloc( (void**)&b_dev,SIZE);
hipMalloc( (void**)&c_dev,SIZE);
hipMemcpy(a_dev,a,SIZE,hipMemcpyHostToDevice);
hipMemcpy(b_dev,b,SIZE,hipMemcpyHostToDevice);
add<<<(N+THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(N,a_dev,b_dev,c_dev);
hipMemcpy(c,c_dev,SIZE,hipMemcpyDeviceToHost);
for(i=0;i<N;i++){
printf("i = %d, %d + %d = %d \n",i,a[i],b[i],c[i]);
}
free(a);
free(b);
free(c);
hipFree(a_dev);
hipFree(b_dev);
hipFree(c_dev);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // add two vectors
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
#define N (2048*2048)
const int THREADS_PER_BLOCK = 512;
__global__ void add(int npts,int *a,int *b,int *c){
int i = threadIdx.x + blockIdx.x*blockDim.x; // combining blocks and threads; this gives an absolute index
if(i<npts){
c[i] = a[i] + b[i];
}
}
int main(void){
const int SIZE = N*sizeof(int);
int *a = (int *)malloc(SIZE);
int *b = (int *)malloc(SIZE);
int *c = (int *)malloc(SIZE);
int *a_dev,*b_dev,*c_dev;
int i=0;
for(i=0;i<N;i++){
a[i] = -1*i;
b[i] = 2*i;
}
hipMalloc( (void**)&a_dev,SIZE);
hipMalloc( (void**)&b_dev,SIZE);
hipMalloc( (void**)&c_dev,SIZE);
hipMemcpy(a_dev,a,SIZE,hipMemcpyHostToDevice);
hipMemcpy(b_dev,b,SIZE,hipMemcpyHostToDevice);
add<<<(N+THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(N,a_dev,b_dev,c_dev);
hipMemcpy(c,c_dev,SIZE,hipMemcpyDeviceToHost);
for(i=0;i<N;i++){
printf("i = %d, %d + %d = %d \n",i,a[i],b[i],c[i]);
}
free(a);
free(b);
free(c);
hipFree(a_dev);
hipFree(b_dev);
hipFree(c_dev);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiPiS_S_
.globl _Z3addiPiS_S_
.p2align 8
.type _Z3addiPiS_S_,@function
_Z3addiPiS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiPiS_S_, .Lfunc_end0-_Z3addiPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addiPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // add two vectors
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
#define N (2048*2048)
const int THREADS_PER_BLOCK = 512;
__global__ void add(int npts,int *a,int *b,int *c){
int i = threadIdx.x + blockIdx.x*blockDim.x; // combining blocks and threads; this gives an absolute index
if(i<npts){
c[i] = a[i] + b[i];
}
}
int main(void){
const int SIZE = N*sizeof(int);
int *a = (int *)malloc(SIZE);
int *b = (int *)malloc(SIZE);
int *c = (int *)malloc(SIZE);
int *a_dev,*b_dev,*c_dev;
int i=0;
for(i=0;i<N;i++){
a[i] = -1*i;
b[i] = 2*i;
}
hipMalloc( (void**)&a_dev,SIZE);
hipMalloc( (void**)&b_dev,SIZE);
hipMalloc( (void**)&c_dev,SIZE);
hipMemcpy(a_dev,a,SIZE,hipMemcpyHostToDevice);
hipMemcpy(b_dev,b,SIZE,hipMemcpyHostToDevice);
add<<<(N+THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(N,a_dev,b_dev,c_dev);
hipMemcpy(c,c_dev,SIZE,hipMemcpyDeviceToHost);
for(i=0;i<N;i++){
printf("i = %d, %d + %d = %d \n",i,a[i],b[i],c[i]);
}
free(a);
free(b);
free(c);
hipFree(a_dev);
hipFree(b_dev);
hipFree(c_dev);
return 0;
} | .text
.file "add_vectors.hip"
.globl _Z18__device_stub__addiPiS_S_ # -- Begin function _Z18__device_stub__addiPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addiPiS_S_,@function
_Z18__device_stub__addiPiS_S_: # @_Z18__device_stub__addiPiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addiPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addiPiS_S_, .Lfunc_end0-_Z18__device_stub__addiPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %rbx
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r14
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r15
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rcx,2)
movl %ecx, (%r14,%rcx,2)
addq $2, %rcx
decl %eax
cmpq $8388608, %rcx # imm = 0x800000
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movq 24(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967808, %rdx # imm = 0x100000200
leaq 7680(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl $4194304, 36(%rsp) # imm = 0x400000
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 104(%rsp), %rax
movq %rax, 120(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3addiPiS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $16777216, %edx # imm = 0x1000000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r12,4), %edx
movl (%r14,%r12,4), %ecx
movl (%r15,%r12,4), %r8d
movl $.L.str, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
incq %r12
cmpq $4194304, %r12 # imm = 0x400000
jne .LBB1_5
# %bb.6:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiPiS_S_,@object # @_Z3addiPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addiPiS_S_
.p2align 3, 0x0
_Z3addiPiS_S_:
.quad _Z18__device_stub__addiPiS_S_
.size _Z3addiPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "i = %d, %d + %d = %d \n"
.size .L.str, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addiPiS_S_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addiPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiPiS_S_
.globl _Z3addiPiS_S_
.p2align 8
.type _Z3addiPiS_S_,@function
_Z3addiPiS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiPiS_S_, .Lfunc_end0-_Z3addiPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addiPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000900b4_00000000-6_add_vectors.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2274:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2274:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3addiPiS_S_iPiS_S_
.type _Z27__device_stub__Z3addiPiS_S_iPiS_S_, @function
_Z27__device_stub__Z3addiPiS_S_iPiS_S_:
.LFB2296:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addiPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2296:
.size _Z27__device_stub__Z3addiPiS_S_iPiS_S_, .-_Z27__device_stub__Z3addiPiS_S_iPiS_S_
.globl _Z3addiPiS_S_
.type _Z3addiPiS_S_, @function
_Z3addiPiS_S_:
.LFB2297:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3addiPiS_S_iPiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2297:
.size _Z3addiPiS_S_, .-_Z3addiPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "i = %d, %d + %d = %d \n"
.text
.globl main
.type main, @function
main:
.LFB2271:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $16777216, %edi
call malloc@PLT
movq %rax, %r12
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbp
movl $16777216, %edi
call malloc@PLT
movq %rax, %r13
movl $0, %eax
.L12:
movl %eax, %edx
negl %edx
movl %edx, (%r12,%rax,4)
leal (%rax,%rax), %edx
movl %edx, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $4194304, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $16777216, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16777216, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl $8192, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $16777216, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %r14
.L14:
movl (%r12,%rbx,4), %ecx
movl 0(%r13,%rbx,4), %r9d
movl 0(%rbp,%rbx,4), %r8d
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $4194304, %rbx
jne .L14
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movl $4194304, %edi
call _Z27__device_stub__Z3addiPiS_S_iPiS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2271:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addiPiS_S_"
.LC2:
.string "precalc_xorwow_matrix"
.LC3:
.string "precalc_xorwow_offset_matrix"
.LC4:
.string "mrg32k3aM1"
.LC5:
.string "mrg32k3aM2"
.LC6:
.string "mrg32k3aM1SubSeq"
.LC7:
.string "mrg32k3aM2SubSeq"
.LC8:
.string "mrg32k3aM1Seq"
.LC9:
.string "mrg32k3aM2Seq"
.LC10:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2299:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiPiS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2299:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add_vectors.hip"
.globl _Z18__device_stub__addiPiS_S_ # -- Begin function _Z18__device_stub__addiPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addiPiS_S_,@function
_Z18__device_stub__addiPiS_S_: # @_Z18__device_stub__addiPiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addiPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addiPiS_S_, .Lfunc_end0-_Z18__device_stub__addiPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %rbx
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r14
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r15
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rcx,2)
movl %ecx, (%r14,%rcx,2)
addq $2, %rcx
decl %eax
cmpq $8388608, %rcx # imm = 0x800000
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movq 24(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967808, %rdx # imm = 0x100000200
leaq 7680(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl $4194304, 36(%rsp) # imm = 0x400000
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 104(%rsp), %rax
movq %rax, 120(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3addiPiS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $16777216, %edx # imm = 0x1000000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r12,4), %edx
movl (%r14,%r12,4), %ecx
movl (%r15,%r12,4), %r8d
movl $.L.str, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
incq %r12
cmpq $4194304, %r12 # imm = 0x400000
jne .LBB1_5
# %bb.6:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiPiS_S_,@object # @_Z3addiPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addiPiS_S_
.p2align 3, 0x0
_Z3addiPiS_S_:
.quad _Z18__device_stub__addiPiS_S_
.size _Z3addiPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "i = %d, %d + %d = %d \n"
.size .L.str, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addiPiS_S_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
const int MAX_THREAD_NUMBER = 1000000;
__device__ long long counterArray[MAX_THREAD_NUMBER] = {0};
extern "C" __device__ void bambooProfile(long bambooIndex)
{
int blockId = blockIdx.x
+ blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
long long index = blockId * (blockDim.x * blockDim.y * blockDim.z)
+ (threadIdx.z * (blockDim.x * blockDim.y))
+ (threadIdx.y * blockDim.x)
+ threadIdx.x;
counterArray[index]++;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
const int MAX_THREAD_NUMBER = 1000000;
__device__ long long counterArray[MAX_THREAD_NUMBER] = {0};
extern "C" __device__ void bambooProfile(long bambooIndex)
{
int blockId = blockIdx.x
+ blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
long long index = blockId * (blockDim.x * blockDim.y * blockDim.z)
+ (threadIdx.z * (blockDim.x * blockDim.y))
+ (threadIdx.y * blockDim.x)
+ threadIdx.x;
counterArray[index]++;
} | .file "tmpxft_00057451_00000000-6_profiling_runtime.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl bambooProfile
.type bambooProfile, @function
bambooProfile:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size bambooProfile, .-bambooProfile
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "counterArray"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8000000, %r9d
movl $0, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL12counterArray(%rip), %rsi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL12counterArray
.comm _ZL12counterArray,8000000,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
const int MAX_THREAD_NUMBER = 1000000;
__device__ long long counterArray[MAX_THREAD_NUMBER] = {0};
extern "C" __device__ void bambooProfile(long bambooIndex)
{
int blockId = blockIdx.x
+ blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
long long index = blockId * (blockDim.x * blockDim.y * blockDim.z)
+ (threadIdx.z * (blockDim.x * blockDim.y))
+ (threadIdx.y * blockDim.x)
+ threadIdx.x;
counterArray[index]++;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
const int MAX_THREAD_NUMBER = 1000000;
__device__ long long counterArray[MAX_THREAD_NUMBER] = {0};
extern "C" __device__ void bambooProfile(long bambooIndex)
{
int blockId = blockIdx.x
+ blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
long long index = blockId * (blockDim.x * blockDim.y * blockDim.z)
+ (threadIdx.z * (blockDim.x * blockDim.y))
+ (threadIdx.y * blockDim.x)
+ threadIdx.x;
counterArray[index]++;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
const int MAX_THREAD_NUMBER = 1000000;
__device__ long long counterArray[MAX_THREAD_NUMBER] = {0};
extern "C" __device__ void bambooProfile(long bambooIndex)
{
int blockId = blockIdx.x
+ blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
long long index = blockId * (blockDim.x * blockDim.y * blockDim.z)
+ (threadIdx.z * (blockDim.x * blockDim.y))
+ (threadIdx.y * blockDim.x)
+ threadIdx.x;
counterArray[index]++;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected counterArray
.type counterArray,@object
.section .bss,"aw",@nobits
.globl counterArray
.p2align 4, 0x0
counterArray:
.zero 8000000
.size counterArray, 8000000
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym counterArray
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
const int MAX_THREAD_NUMBER = 1000000;
__device__ long long counterArray[MAX_THREAD_NUMBER] = {0};
extern "C" __device__ void bambooProfile(long bambooIndex)
{
int blockId = blockIdx.x
+ blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
long long index = blockId * (blockDim.x * blockDim.y * blockDim.z)
+ (threadIdx.z * (blockDim.x * blockDim.y))
+ (threadIdx.y * blockDim.x)
+ threadIdx.x;
counterArray[index]++;
} | .text
.file "profiling_runtime.hip"
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB0_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB0_2:
movq __hip_gpubin_handle(%rip), %rdi
movl $counterArray, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $8000000, %r9d # imm = 0x7A1200
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end0:
.size __hip_module_ctor, .Lfunc_end0-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB1_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB1_2:
retq
.Lfunc_end1:
.size __hip_module_dtor, .Lfunc_end1-__hip_module_dtor
.cfi_endproc
# -- End function
.type counterArray,@object # @counterArray
.local counterArray
.comm counterArray,8000000,16
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "counterArray"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym counterArray
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected counterArray
.type counterArray,@object
.section .bss,"aw",@nobits
.globl counterArray
.p2align 4, 0x0
counterArray:
.zero 8000000
.size counterArray, 8000000
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym counterArray
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00057451_00000000-6_profiling_runtime.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl bambooProfile
.type bambooProfile, @function
bambooProfile:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size bambooProfile, .-bambooProfile
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "counterArray"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8000000, %r9d
movl $0, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL12counterArray(%rip), %rsi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL12counterArray
.comm _ZL12counterArray,8000000,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "profiling_runtime.hip"
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB0_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB0_2:
movq __hip_gpubin_handle(%rip), %rdi
movl $counterArray, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $8000000, %r9d # imm = 0x7A1200
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end0:
.size __hip_module_ctor, .Lfunc_end0-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB1_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB1_2:
retq
.Lfunc_end1:
.size __hip_module_dtor, .Lfunc_end1-__hip_module_dtor
.cfi_endproc
# -- End function
.type counterArray,@object # @counterArray
.local counterArray
.comm counterArray,8000000,16
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "counterArray"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym counterArray
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cufft.h"
#ifndef pi
#define pi 4.0f*atanf(1.0f)
#endif
#ifndef threads_num
#define threads_num 256
#endif
/* functions for dst and dct transforms */
static __global__ void DataExtSetRedft00_1d(float *d_in, cufftComplex *d_out, int n);
static __global__ void DataSubGetRedft00_1d(cufftComplex *d_in, float *d_out, int n);
static __global__ void DataExtSetRedft10_1d(float *d_in, cufftComplex *d_out, int n);
static __global__ void DataSubGetRedft10_1d(cufftComplex *d_in, float *d_out, int n);
static __global__ void DataExtSetRedft01_1d(float *d_in, cufftComplex *d_out, int n);
static __global__ void DataSubGetRedft01_1d(cufftComplex *d_in, float *d_out, int n);
static __global__ void DataExtSetRodft00_1d(float *d_in, cufftComplex *d_out, int n);
static __global__ void DataSubGetRodft00_1d(cufftComplex *d_in, float *d_out, int n);
static __global__ void DataExtSetIRodft00_1d(float *d_in, cufftComplex *d_out, int n);
static __global__ void DataSubGetIRodft00_1d(cufftComplex *d_in, float *d_out, int n);
static __global__ void DataExtSetRodft10_1d(float *d_in, cufftComplex *d_out, int n);
static __global__ void DataSubGetRodft10_1d(cufftComplex *d_in, float *d_out, int n);
static __global__ void DataExtSetRodft01_1d(float *d_in, cufftComplex *d_out, int n);
static __global__ void DataSubGetRodft01_1d(cufftComplex *d_in, float *d_out, int n);
static __global__ void PhaseShiftForw_1d(cufftComplex *d_in, cufftComplex *d_out, int n);
static __global__ void PhaseShiftBack_1d(cufftComplex *d_in, cufftComplex *d_out, int n);
/* various dst and dct transforms */
void cufft_redft00_1d(float *d_in, float *d_out, int n);
void cufft_iredft00_1d(float *d_in, float *d_out, int n);
void cufft_redft10_1d(float *d_in, float *d_out, int n);
void cufft_redft01_1d(float *d_in, float *d_out, int n);
void cufft_rodft00_1d(float *d_in, float *d_out, int n);
void cufft_irodft00_1d(float *d_in, float *d_out, int n);
void cufft_rodft10_1d(float *d_in, float *d_out, int n);
void cufft_rodft01_1d(float *d_in, float *d_out, int n);
/* functions for first-order derivatives computed by dst and dct */
static __global__ void dst1_idct2_1d_pre(float *d_in, float *d_out, float dx, int n);
static __global__ void dst1_idct2_1d_post(float *d_in, float *d_out, int n);
static __global__ void dct1_idst2_1d_pre(float *d_in, float *d_out, float dx, int n);
static __global__ void dct1_idst2_1d_post(float *d_in, float *d_out, int n);
static __global__ void dst2_idct1_1d_pre(float *d_in, float *d_out, float dx, int n);
static __global__ void dst2_idct1_1d_post(float *d_in, float *d_out, int n);
static __global__ void dct2_idst1_1d_pre(float *d_in, float *d_out, float dx, int n);
static __global__ void dct2_idst1_1d_post(float *d_in, float *d_out, int n);
void cufft_dct2_idst1_1d(float *d_in, float *d_out, float dx, int nn)
{
int n = nn-1;
float *d_in_dst;
cudaMalloc((void **)&d_in_dst, n*sizeof(float));
/* Sine transform */
cufft_redft10_1d(d_in, d_in_dst, n);
float *d_in_tmp;
cudaMalloc((void **)&d_in_tmp, (n-1)*sizeof(float));
/* Multiplied by wavenumber */
dct2_idst1_1d_pre<<<(n+threads_num-1)/threads_num, threads_num>>>(d_in_dst, d_in_tmp, dx, n);
float *d_out_tmp;
cudaMalloc((void **)&d_out_tmp, (n-1)*sizeof(float));
/* Inverse cosine transform */
cufft_irodft00_1d(d_in_tmp, d_out_tmp, n-1);
/* Get the result */
dct2_idst1_1d_post<<<(n+threads_num-1)/threads_num, threads_num>>>(d_out_tmp, d_out, n);
cudaFree(d_in_dst);
cudaFree(d_in_tmp);
cudaFree(d_out_tmp);
}
static __global__ void dct2_idst1_1d_pre(float *d_in, float *d_out, float dx, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
d_out[0] = 0.0f;
//for (int ix=tid; ix<n-1; ix+=threads_num)
if (ix < n-1)
d_out[ix] = -(float)(ix+1)*pi/((float)n*dx)*d_in[ix+1];
}
static __global__ void dct2_idst1_1d_post(float *d_in, float *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
//for (int ix=tid; ix<n-1; ix+=threads_num)
if (ix < n-1)
d_out[ix+1] = d_in[ix]/(2.0f*(float)(n));
d_out[n] = 0.0f;
}
void cufft_dst2_idct1_1d(float *d_in, float *d_out, float dx, int nn)
{
int n = nn-1;
float *d_in_dst;
cudaMalloc((void **)&d_in_dst, n*sizeof(float));
/* Sine transform */
cufft_rodft10_1d(d_in, d_in_dst, n);
float *d_in_tmp;
cudaMalloc((void **)&d_in_tmp, (n+1)*sizeof(float));
/* Multiplied by wavenumber */
dst2_idct1_1d_pre<<<(n+threads_num-1)/threads_num, threads_num>>>(d_in_dst, d_in_tmp, dx, n);
float *d_out_tmp;
cudaMalloc((void **)&d_out_tmp, (n+1)*sizeof(float));
/* Inverse cosine transform */
cufft_redft00_1d(d_in_tmp, d_out_tmp, n+1);
/* Get the result */
dst2_idct1_1d_post<<<(n+threads_num-1)/threads_num, threads_num>>>(d_out_tmp, d_out, n);
cudaFree(d_in_dst);
cudaFree(d_in_tmp);
cudaFree(d_out_tmp);
}
static __global__ void dst2_idct1_1d_pre(float *d_in, float *d_out, float dx, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
d_out[0] = 0.0f;
//for (int ix=tid; ix<n; ix+=threads_num)
if (ix < n)
d_out[ix+1] = (float)(ix+1)*pi/((float)n*dx)*d_in[ix];
}
static __global__ void dst2_idct1_1d_post(float *d_in, float *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
//for (int ix=tid; ix<n+1; ix+=threads_num)
if (ix < n+1)
d_out[ix] = d_in[ix]/(2.0f*(float)(n));
}
void cufft_dct1_idst2_1d(float *d_in, float *d_out, float dx, int n)
{
float *d_in_dst;
cudaMalloc((void **)&d_in_dst, n*sizeof(float));
/* Sine transform */
cudaMemset((void *)&d_in[n-1], 0, sizeof(int));
cufft_redft00_1d(d_in, d_in_dst, n);
float *d_in_tmp;
cudaMalloc((void **)&d_in_tmp, (n-1)*sizeof(float));
/* Multiplied by wavenumber */
dct1_idst2_1d_pre<<<(n+threads_num-1)/threads_num, threads_num>>>(d_in_dst, d_in_tmp, dx, n);
float *d_out_tmp;
cudaMalloc((void **)&d_out_tmp, (n-1)*sizeof(float));
/* Inverse cosine transform */
cufft_rodft01_1d(d_in_tmp, d_out_tmp, n-1);
/* Get the result */
dct1_idst2_1d_post<<<(n+threads_num-1)/threads_num, threads_num>>>(d_out_tmp, d_out, n);
cudaFree(d_in_dst);
cudaFree(d_in_tmp);
cudaFree(d_out_tmp);
}
static __global__ void dct1_idst2_1d_pre(float *d_in, float *d_out, float dx, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
d_out[0] = 0.0f;
//for (int ix=tid; ix<n-1; ix+=threads_num)
if (ix < n-1)
d_out[ix] = -(float)(ix+1)*pi/(float(n-1)*dx)*d_in[ix+1];
}
static __global__ void dct1_idst2_1d_post(float *d_in, float *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
//for (int ix=tid; ix<n-1; ix+=threads_num)
if (ix < n-1)
d_out[ix] = d_in[ix]/(2.0f*(float)(n-1));
d_out[n-1] = 0.0f;
}
void cufft_dst1_idct2_1d(float *d_in, float *d_out, float dx, int n)
{
float *d_in_dst;
cudaMalloc((void **)&d_in_dst, n*sizeof(float));
/* Sine transform */
cufft_rodft00_1d(d_in, d_in_dst, n);
float *d_in_tmp;
cudaMalloc((void **)&d_in_tmp, (n+1)*sizeof(float));
/* Multiplied by wavenumber */
dst1_idct2_1d_pre<<<(n+threads_num-1)/threads_num, threads_num>>>(d_in_dst, d_in_tmp, dx, n);
float *d_out_tmp;
cudaMalloc((void **)&d_out_tmp, (n+1)*sizeof(float));
/* Inverse cosine transform */
cufft_redft01_1d(d_in_tmp, d_out_tmp, n+1);
/* Get the result */
dst1_idct2_1d_post<<<(n+threads_num-1)/threads_num, threads_num>>>(d_out_tmp, d_out, n);
cudaFree(d_in_dst);
cudaFree(d_in_tmp);
cudaFree(d_out_tmp);
}
static __global__ void dst1_idct2_1d_pre(float *d_in, float *d_out, float dx, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
//for (int ix=tid; ix<n; ix+=threads_num)
if (ix < n)
d_out[ix+1] = (float)(ix+1)*pi/(float(n+1)*dx)*d_in[ix];
d_out[0] = 0.0f;
}
static __global__ void dst1_idct2_1d_post(float *d_in, float *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
//for (int ix=tid; ix<n-1; ix+=threads_num)
if (ix < n-1)
d_out[ix] = d_in[ix+1]/(2.0f*(float)(n+1));
d_out[n-1] = 0.0f;
}
void cufft_redft00_1d(float *d_in, float *d_out, int n)
{
/* Allocate memory for extended complex data */
cufftComplex *d_in_ext;
cudaMalloc((void **)&d_in_ext, (2*n-2)*sizeof(cufftComplex));
/* Extend and convert the data from float to cufftComplex */
DataExtSetRedft00_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_in, d_in_ext, n);
/* Create a 1D FFT plan */
cufftHandle plan;
cufftPlan1d(&plan, 2*n-2, CUFFT_C2C, 1);
/* Allocate memory for transformed data */
cufftComplex *d_out_ext;
cudaMalloc((void **)&d_out_ext, (2*n-2)*sizeof(cufftComplex));
/* Use the CUFFT plan to transform the signal out of place */
cufftExecC2C(plan, d_in_ext, d_out_ext, CUFFT_FORWARD);
/* Subtract the transformed data */
DataSubGetRedft00_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_out_ext, d_out, n);
cufftDestroy(plan);
cudaFree(d_in_ext);
cudaFree(d_out_ext);
}
void cufft_iredft00_1d(float *d_in, float *d_out, int n)
{
cufft_redft00_1d(d_in, d_out, n);
}
void cufft_redft10_1d(float *d_in, float *d_out, int n)
{
/* Allocate meory for extended complex data */
cufftComplex *d_in_ext;
cudaMalloc((void **)&d_in_ext, 2*n*sizeof(cufftComplex));
/* Extend and convert the data from float to cufftComplex */
DataExtSetRedft10_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_in, d_in_ext, n);
/* Create a 1D FFT plan */
cufftHandle plan;
cufftPlan1d(&plan, 2*n, CUFFT_C2C, 1);
/* Allocate memory for transformed data */
cufftComplex *d_out_ext;
cudaMalloc((void **)&d_out_ext, 2*n*sizeof(cufftComplex));
/* Use the CUFFT plan to transform the signal out of place */
cufftExecC2C(plan, d_in_ext, d_out_ext, CUFFT_FORWARD);
/* Allocate memory for shifted data */
cufftComplex *d_out_ext_shift;
cudaMalloc((void **)&d_out_ext_shift, 2*n*sizeof(cufftComplex));
/* 1/2 phase shift */
PhaseShiftForw_1d<<<(2*n+threads_num-1)/threads_num, threads_num>>>(d_out_ext, d_out_ext_shift, 2*n);
/* Subtract the transformed data */
DataSubGetRedft10_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_out_ext_shift, d_out, n);
cufftDestroy(plan);
cudaFree(d_in_ext);
cudaFree(d_out_ext);
cudaFree(d_out_ext_shift);
}
void cufft_redft01_1d(float *d_in, float *d_out, int n)
{
/* Allocate meory for extended complex data */
cufftComplex *d_in_ext;
cudaMalloc((void **)&d_in_ext, 2*n*sizeof(cufftComplex));
/* Extend and convert the data from float to cufftComplex */
DataExtSetRedft01_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_in, d_in_ext, n);
/* Allocate memory for shifted data */
cufftComplex *d_in_ext_shift;
cudaMalloc((void **)&d_in_ext_shift, 2*n*sizeof(cufftComplex));
/* -1/2 phase shift */
PhaseShiftBack_1d<<<(2*n+threads_num-1)/threads_num, threads_num>>>(d_in_ext, d_in_ext_shift, 2*n);
/* Create a 1D FFT plan */
cufftHandle plan;
cufftPlan1d(&plan, 2*n, CUFFT_C2C, 1);
/* Allocate memory for transformed data */
cufftComplex *d_out_ext;
cudaMalloc((void **)&d_out_ext, 2*n*sizeof(cufftComplex));
/* Use the CUFFT plan to transform the signal out of place */
cufftExecC2C(plan, d_in_ext_shift, d_out_ext, CUFFT_INVERSE);
/* Subtract the transformed data */
DataSubGetRedft01_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_out_ext, d_out, n);
cufftDestroy(plan);
cudaFree(d_in_ext);
cudaFree(d_in_ext_shift);
cudaFree(d_out_ext);
}
void cufft_rodft00_1d(float *d_in, float *d_out, int n)
{
/* Allocate memory for extended complex data */
cufftComplex *d_in_ext;
cudaMalloc((void **)&d_in_ext, (2*n+2)*sizeof(cufftComplex));
/* Extend and convert the data from float to cufftComplex */
DataExtSetRodft00_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_in, d_in_ext, n);
/* Create a 1D FFT plan */
cufftHandle plan;
cufftPlan1d(&plan, 2*n+2, CUFFT_C2C, 1);
/* Allocate memory for transformed data */
cufftComplex *d_out_ext;
cudaMalloc((void **)&d_out_ext, (2*n+2)*sizeof(cufftComplex));
/* Use the CUFFT plan to transform the signal out of place */
cufftExecC2C(plan, d_in_ext, d_out_ext, CUFFT_FORWARD);
/* Subtract the transformed data */
DataSubGetRodft00_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_out_ext, d_out, n);
cufftDestroy(plan);
cudaFree(d_in_ext);
cudaFree(d_out_ext);
}
void cufft_irodft00_1d(float *d_in, float *d_out, int n)
{
/* Allocate memory for extended complex data */
cufftComplex *d_in_ext;
cudaMalloc((void **)&d_in_ext, (2*n+2)*sizeof(cufftComplex));
/* Extend and convert the data from float to cufftComplex */
DataExtSetIRodft00_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_in, d_in_ext, n);
/* Create a 1D FFT plan */
cufftHandle plan;
cufftPlan1d(&plan, 2*n+2, CUFFT_C2C, 1);
/* Allocate memory for transformed data */
cufftComplex *d_out_ext;
cudaMalloc((void **)&d_out_ext, (2*n+2)*sizeof(cufftComplex));
/* Use the CUFFT plan to transform the signal out of place */
cufftExecC2C(plan, d_in_ext, d_out_ext, CUFFT_INVERSE);
/* Subtract the transformed data */
DataSubGetIRodft00_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_out_ext, d_out, n);
cufftDestroy(plan);
cudaFree(d_in_ext);
cudaFree(d_out_ext);
}
void cufft_rodft10_1d(float *d_in, float *d_out, int n)
{
/* Allocate meory for extended complex data */
cufftComplex *d_in_ext;
cudaMalloc((void **)&d_in_ext, 2*n*sizeof(cufftComplex));
/* Extend and convert the data from float to cufftComplex */
DataExtSetRodft10_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_in, d_in_ext, n);
/* Create a 1D FFT plan */
cufftHandle plan;
cufftPlan1d(&plan, 2*n, CUFFT_C2C, 1);
/* Allocate memory for transformed data */
cufftComplex *d_out_ext;
cudaMalloc((void **)&d_out_ext, 2*n*sizeof(cufftComplex));
/* Use the CUFFT plan to transform the signal out of place */
cufftExecC2C(plan, d_in_ext, d_out_ext, CUFFT_FORWARD);
/* Allocate memory for shifted data */
cufftComplex *d_out_ext_shift;
cudaMalloc((void **)&d_out_ext_shift, 2*n*sizeof(cufftComplex));
/* 1/2 phase shift */
PhaseShiftForw_1d<<<(2*n+threads_num-1)/threads_num, threads_num>>>(d_out_ext, d_out_ext_shift, 2*n);
/* Subtract the transformed data */
DataSubGetRodft10_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_out_ext_shift, d_out, n);
cufftDestroy(plan);
cudaFree(d_in_ext);
cudaFree(d_out_ext);
cudaFree(d_out_ext_shift);
}
void cufft_rodft01_1d(float *d_in, float *d_out, int n)
{
/* Allocate meory for extended complex data */
cufftComplex *d_in_ext;
cudaMalloc((void **)&d_in_ext, 2*n*sizeof(cufftComplex));
/* Extend and convert the data from float to cufftComplex */
DataExtSetRodft01_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_in, d_in_ext, n);
/* Allocate memory for shifted data */
cufftComplex *d_in_ext_shift;
cudaMalloc((void **)&d_in_ext_shift, 2*n*sizeof(cufftComplex));
/* -1/2 phase shift */
PhaseShiftBack_1d<<<(2*n+threads_num-1)/threads_num, threads_num>>>(d_in_ext, d_in_ext_shift, 2*n);
/* Create a 1D FFT plan */
cufftHandle plan;
cufftPlan1d(&plan, 2*n, CUFFT_C2C, 1);
/* Allocate memory for transformed data */
cufftComplex *d_out_ext;
cudaMalloc((void **)&d_out_ext, 2*n*sizeof(cufftComplex));
/* Use the CUFFT plan to transform the signal out of place */
cufftExecC2C(plan, d_in_ext_shift, d_out_ext, CUFFT_INVERSE);
/* Subtract the transformed data */
DataSubGetRodft01_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_out_ext, d_out, n);
cufftDestroy(plan);
cudaFree(d_in_ext);
cudaFree(d_in_ext_shift);
cudaFree(d_out_ext);
}
static __global__ void DataExtSetRedft00_1d(float *d_in, cufftComplex *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
//for (int ix=tid; ix<n; ix+=threads_num)
if (ix < n)
{
d_out[ix].x = d_in[ix];
d_out[ix].y = 0.0f;
if (ix<n-2)
{
d_out[2*n-3-ix].x = d_in[ix+1];
d_out[2*n-3-ix].y = 0.0f;
}
}
}
static __global__ void DataSubGetRedft00_1d(cufftComplex *d_in, float *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
//for (int ix=tid; ix<n; ix+=threads_num)
if (ix < n)
d_out[ix] = d_in[ix].x;
}
static __global__ void DataExtSetRedft10_1d(float *d_in, cufftComplex *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
//for (int ix=tid; ix<n; ix+=threads_num)
if (ix < n)
{
d_out[ix].x = d_in[ix];
d_out[ix].y = 0.0f;
d_out[2*n-1-ix].x = d_in[ix];
d_out[2*n-1-ix].y = 0.0f;
}
}
static __global__ void DataSubGetRedft10_1d(cufftComplex *d_in, float *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
//for (int ix=tid; ix<n; ix+=threads_num)
if (ix < n)
d_out[ix] = d_in[ix].x;
}
static __global__ void DataExtSetRedft01_1d(float *d_in, cufftComplex *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
//for (int ix=tid; ix<n; ix+=threads_num)
if (ix < n)
{
d_out[ix].x = d_in[ix];
d_out[ix].y = 0.0f;
if (ix<n-1)
{
d_out[2*n-1-ix].x = d_in[ix+1];
d_out[2*n-1-ix].y = 0.0f;
}
}
}
static __global__ void DataSubGetRedft01_1d(cufftComplex *d_in, float *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
//for (int ix=tid; ix<n; ix+=threads_num)
if (ix < n)
d_out[ix] = d_in[ix].x;
}
static __global__ void DataExtSetRodft00_1d(float *d_in, cufftComplex *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
//for (int ix=tid; ix<n; ix+=threads_num)
if (ix < n)
{
d_out[ix+1].x = d_in[ix];
d_out[ix+1].y = 0.0f;
d_out[2*n+1-ix].x = -d_in[ix];
d_out[2*n+1-ix].y = 0.0f;
}
d_out[0].x = d_out[0].y = 0.0f;
d_out[n+1].x = d_out[n+1].y = 0.0f;
}
static __global__ void DataSubGetRodft00_1d(cufftComplex *d_in, float *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
//for (int ix=tid; ix<n; ix+=threads_num)
if (ix < n)
d_out[ix] = -d_in[ix+1].y;
}
static __global__ void DataExtSetIRodft00_1d(float *d_in, cufftComplex *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
//for (int ix=tid; ix<n; ix+=threads_num)
if (ix < n)
{
d_out[ix+1].y = -d_in[ix];
d_out[ix+1].x = 0.0f;
d_out[2*n+1-ix].y = d_in[ix];
d_out[2*n+1-ix].x = 0.0f;
}
d_out[0].x = d_out[0].y = 0.0f;
d_out[n+1].x = d_out[n+1].y = 0.0f;
}
static __global__ void DataSubGetIRodft00_1d(cufftComplex *d_in, float *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
//for (int ix=tid; ix<n; ix+=threads_num)
if (ix < n)
d_out[ix] = d_in[ix+1].x;
}
static __global__ void DataExtSetRodft10_1d(float *d_in, cufftComplex *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
//for (int ix=tid; ix<n; ix+=threads_num)
if (ix < n)
{
d_out[ix].x = d_in[ix];
d_out[ix].y = 0.0f;
d_out[2*n-1-ix].x = -d_in[ix];
d_out[2*n-1-ix].y = 0.0f;
}
}
static __global__ void DataSubGetRodft10_1d(cufftComplex *d_in, float *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
//for (int ix=tid; ix<n; ix+=threads_num)
if (ix < n)
d_out[ix] = -d_in[ix+1].y;
}
static __global__ void DataExtSetRodft01_1d(float *d_in, cufftComplex *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
//for (int ix=tid; ix<n; ix+=threads_num)
if (ix < n)
{
d_out[ix+1].y = -d_in[ix];
d_out[ix+1].x = 0.0f;
if (ix<n-1)
{
d_out[2*n-1-ix].y = d_in[ix];
d_out[2*n-1-ix].x = 0.0f;
}
}
d_out[0].x = d_out[0].y = 0.0f;
}
static __global__ void DataSubGetRodft01_1d(cufftComplex *d_in, float *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
//for (int ix=tid; ix<n; ix+=threads_num)
if (ix < n)
d_out[ix] = d_in[ix].x;
}
static __global__ void PhaseShiftForw_1d(cufftComplex *d_in, cufftComplex *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
float d_k;
//for (int ix=tid; ix<n; ix+=threads_num)
if (ix < n)
{
if (ix<n/2)
d_k = (float)ix*pi/(float)(n/2);
else
d_k = -pi+(float)(ix-n/2)*pi/(float)(n/2);
d_out[ix].x = d_in[ix].x*cosf(d_k/2.0f)+d_in[ix].y*sinf(d_k/2.0f);
d_out[ix].y = -d_in[ix].x*sinf(d_k/2.0f)+d_in[ix].y*cosf(d_k/2.0f);
}
}
static __global__ void PhaseShiftBack_1d(cufftComplex *d_in, cufftComplex *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
float d_k;
//for (int ix=tid; ix<n; ix+=threads_num)
if (ix < n)
{
if (ix<n/2)
d_k = (float)ix*pi/(float)(n/2);
else
d_k = -pi+(float)(ix-n/2)*pi/(float)(n/2);
d_out[ix].x = d_in[ix].x*cosf(d_k/2.0f)-d_in[ix].y*sinf(d_k/2.0f);
d_out[ix].y = d_in[ix].x*sinf(d_k/2.0f)+d_in[ix].y*cosf(d_k/2.0f);
}
}
void data_test_forw_1d(float *h_in, float *h_out, int n)
{
float *d_in;
cudaMalloc((void **)&d_in, n*sizeof(float));
cudaMemcpy(d_in, h_in, n*sizeof(float), cudaMemcpyHostToDevice);
float *d_out;
cudaMalloc((void **)&d_out, n*sizeof(float));
cufft_rodft00_1d(d_in, d_out, n);
cudaMemcpy(h_out, d_out, n*sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(d_in);
cudaFree(d_out);
}
void data_test_back_1d(float *h_in, float *h_out, int n)
{
float *d_in;
cudaMalloc((void **)&d_in, n*sizeof(float));
cudaMemcpy(d_in, h_in, n*sizeof(float), cudaMemcpyHostToDevice);
float *d_out;
cudaMalloc((void **)&d_out, n*sizeof(float));
cufft_rodft01_1d(d_in, d_out, n);
cudaMemcpy(h_out, d_out, n*sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(d_in);
cudaFree(d_out);
}
void data_test_derv_1d(float *h_in, float *h_out, float dx, int n)
{
float *d_in;
cudaMalloc((void **)&d_in, n*sizeof(float));
cudaMemcpy(d_in, h_in, n*sizeof(float), cudaMemcpyHostToDevice);
float *d_out;
cudaMalloc((void **)&d_out, n*sizeof(float));
cufft_dct2_idst1_1d(d_in, d_out, dx, n);
cudaMemcpy(h_out, d_out, n*sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(d_in);
cudaFree(d_out);
} | #include <hip/hip_runtime.h>
#include "hipfft/hipfft.h"
#ifndef pi
#define pi 4.0f*atanf(1.0f)
#endif
#ifndef threads_num
#define threads_num 256
#endif
/* functions for dst and dct transforms */
static __global__ void DataExtSetRedft00_1d(float *d_in, hipfftComplex *d_out, int n);
static __global__ void DataSubGetRedft00_1d(hipfftComplex *d_in, float *d_out, int n);
static __global__ void DataExtSetRedft10_1d(float *d_in, hipfftComplex *d_out, int n);
static __global__ void DataSubGetRedft10_1d(hipfftComplex *d_in, float *d_out, int n);
static __global__ void DataExtSetRedft01_1d(float *d_in, hipfftComplex *d_out, int n);
static __global__ void DataSubGetRedft01_1d(hipfftComplex *d_in, float *d_out, int n);
static __global__ void DataExtSetRodft00_1d(float *d_in, hipfftComplex *d_out, int n);
static __global__ void DataSubGetRodft00_1d(hipfftComplex *d_in, float *d_out, int n);
static __global__ void DataExtSetIRodft00_1d(float *d_in, hipfftComplex *d_out, int n);
static __global__ void DataSubGetIRodft00_1d(hipfftComplex *d_in, float *d_out, int n);
static __global__ void DataExtSetRodft10_1d(float *d_in, hipfftComplex *d_out, int n);
static __global__ void DataSubGetRodft10_1d(hipfftComplex *d_in, float *d_out, int n);
static __global__ void DataExtSetRodft01_1d(float *d_in, hipfftComplex *d_out, int n);
static __global__ void DataSubGetRodft01_1d(hipfftComplex *d_in, float *d_out, int n);
static __global__ void PhaseShiftForw_1d(hipfftComplex *d_in, hipfftComplex *d_out, int n);
static __global__ void PhaseShiftBack_1d(hipfftComplex *d_in, hipfftComplex *d_out, int n);
/* various dst and dct transforms */
void cufft_redft00_1d(float *d_in, float *d_out, int n);
void cufft_iredft00_1d(float *d_in, float *d_out, int n);
void cufft_redft10_1d(float *d_in, float *d_out, int n);
void cufft_redft01_1d(float *d_in, float *d_out, int n);
void cufft_rodft00_1d(float *d_in, float *d_out, int n);
void cufft_irodft00_1d(float *d_in, float *d_out, int n);
void cufft_rodft10_1d(float *d_in, float *d_out, int n);
void cufft_rodft01_1d(float *d_in, float *d_out, int n);
/* functions for first-order derivatives computed by dst and dct */
static __global__ void dst1_idct2_1d_pre(float *d_in, float *d_out, float dx, int n);
static __global__ void dst1_idct2_1d_post(float *d_in, float *d_out, int n);
static __global__ void dct1_idst2_1d_pre(float *d_in, float *d_out, float dx, int n);
static __global__ void dct1_idst2_1d_post(float *d_in, float *d_out, int n);
static __global__ void dst2_idct1_1d_pre(float *d_in, float *d_out, float dx, int n);
static __global__ void dst2_idct1_1d_post(float *d_in, float *d_out, int n);
static __global__ void dct2_idst1_1d_pre(float *d_in, float *d_out, float dx, int n);
static __global__ void dct2_idst1_1d_post(float *d_in, float *d_out, int n);
void cufft_dct2_idst1_1d(float *d_in, float *d_out, float dx, int nn)
{
int n = nn-1;
float *d_in_dst;
hipMalloc((void **)&d_in_dst, n*sizeof(float));
/* Sine transform */
cufft_redft10_1d(d_in, d_in_dst, n);
float *d_in_tmp;
hipMalloc((void **)&d_in_tmp, (n-1)*sizeof(float));
/* Multiplied by wavenumber */
dct2_idst1_1d_pre<<<(n+threads_num-1)/threads_num, threads_num>>>(d_in_dst, d_in_tmp, dx, n);
float *d_out_tmp;
hipMalloc((void **)&d_out_tmp, (n-1)*sizeof(float));
/* Inverse cosine transform */
cufft_irodft00_1d(d_in_tmp, d_out_tmp, n-1);
/* Get the result */
dct2_idst1_1d_post<<<(n+threads_num-1)/threads_num, threads_num>>>(d_out_tmp, d_out, n);
hipFree(d_in_dst);
hipFree(d_in_tmp);
hipFree(d_out_tmp);
}
static __global__ void dct2_idst1_1d_pre(float *d_in, float *d_out, float dx, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
d_out[0] = 0.0f;
//for (int ix=tid; ix<n-1; ix+=threads_num)
if (ix < n-1)
d_out[ix] = -(float)(ix+1)*pi/((float)n*dx)*d_in[ix+1];
}
static __global__ void dct2_idst1_1d_post(float *d_in, float *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
//for (int ix=tid; ix<n-1; ix+=threads_num)
if (ix < n-1)
d_out[ix+1] = d_in[ix]/(2.0f*(float)(n));
d_out[n] = 0.0f;
}
void cufft_dst2_idct1_1d(float *d_in, float *d_out, float dx, int nn)
{
int n = nn-1;
float *d_in_dst;
hipMalloc((void **)&d_in_dst, n*sizeof(float));
/* Sine transform */
cufft_rodft10_1d(d_in, d_in_dst, n);
float *d_in_tmp;
hipMalloc((void **)&d_in_tmp, (n+1)*sizeof(float));
/* Multiplied by wavenumber */
dst2_idct1_1d_pre<<<(n+threads_num-1)/threads_num, threads_num>>>(d_in_dst, d_in_tmp, dx, n);
float *d_out_tmp;
hipMalloc((void **)&d_out_tmp, (n+1)*sizeof(float));
/* Inverse cosine transform */
cufft_redft00_1d(d_in_tmp, d_out_tmp, n+1);
/* Get the result */
dst2_idct1_1d_post<<<(n+threads_num-1)/threads_num, threads_num>>>(d_out_tmp, d_out, n);
hipFree(d_in_dst);
hipFree(d_in_tmp);
hipFree(d_out_tmp);
}
static __global__ void dst2_idct1_1d_pre(float *d_in, float *d_out, float dx, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
d_out[0] = 0.0f;
//for (int ix=tid; ix<n; ix+=threads_num)
if (ix < n)
d_out[ix+1] = (float)(ix+1)*pi/((float)n*dx)*d_in[ix];
}
static __global__ void dst2_idct1_1d_post(float *d_in, float *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
//for (int ix=tid; ix<n+1; ix+=threads_num)
if (ix < n+1)
d_out[ix] = d_in[ix]/(2.0f*(float)(n));
}
void cufft_dct1_idst2_1d(float *d_in, float *d_out, float dx, int n)
{
float *d_in_dst;
hipMalloc((void **)&d_in_dst, n*sizeof(float));
/* Sine transform */
hipMemset((void *)&d_in[n-1], 0, sizeof(int));
cufft_redft00_1d(d_in, d_in_dst, n);
float *d_in_tmp;
hipMalloc((void **)&d_in_tmp, (n-1)*sizeof(float));
/* Multiplied by wavenumber */
dct1_idst2_1d_pre<<<(n+threads_num-1)/threads_num, threads_num>>>(d_in_dst, d_in_tmp, dx, n);
float *d_out_tmp;
hipMalloc((void **)&d_out_tmp, (n-1)*sizeof(float));
/* Inverse cosine transform */
cufft_rodft01_1d(d_in_tmp, d_out_tmp, n-1);
/* Get the result */
dct1_idst2_1d_post<<<(n+threads_num-1)/threads_num, threads_num>>>(d_out_tmp, d_out, n);
hipFree(d_in_dst);
hipFree(d_in_tmp);
hipFree(d_out_tmp);
}
static __global__ void dct1_idst2_1d_pre(float *d_in, float *d_out, float dx, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
d_out[0] = 0.0f;
//for (int ix=tid; ix<n-1; ix+=threads_num)
if (ix < n-1)
d_out[ix] = -(float)(ix+1)*pi/(float(n-1)*dx)*d_in[ix+1];
}
static __global__ void dct1_idst2_1d_post(float *d_in, float *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
//for (int ix=tid; ix<n-1; ix+=threads_num)
if (ix < n-1)
d_out[ix] = d_in[ix]/(2.0f*(float)(n-1));
d_out[n-1] = 0.0f;
}
void cufft_dst1_idct2_1d(float *d_in, float *d_out, float dx, int n)
{
float *d_in_dst;
hipMalloc((void **)&d_in_dst, n*sizeof(float));
/* Sine transform */
cufft_rodft00_1d(d_in, d_in_dst, n);
float *d_in_tmp;
hipMalloc((void **)&d_in_tmp, (n+1)*sizeof(float));
/* Multiplied by wavenumber */
dst1_idct2_1d_pre<<<(n+threads_num-1)/threads_num, threads_num>>>(d_in_dst, d_in_tmp, dx, n);
float *d_out_tmp;
hipMalloc((void **)&d_out_tmp, (n+1)*sizeof(float));
/* Inverse cosine transform */
cufft_redft01_1d(d_in_tmp, d_out_tmp, n+1);
/* Get the result */
dst1_idct2_1d_post<<<(n+threads_num-1)/threads_num, threads_num>>>(d_out_tmp, d_out, n);
hipFree(d_in_dst);
hipFree(d_in_tmp);
hipFree(d_out_tmp);
}
static __global__ void dst1_idct2_1d_pre(float *d_in, float *d_out, float dx, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
//for (int ix=tid; ix<n; ix+=threads_num)
if (ix < n)
d_out[ix+1] = (float)(ix+1)*pi/(float(n+1)*dx)*d_in[ix];
d_out[0] = 0.0f;
}
static __global__ void dst1_idct2_1d_post(float *d_in, float *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
//for (int ix=tid; ix<n-1; ix+=threads_num)
if (ix < n-1)
d_out[ix] = d_in[ix+1]/(2.0f*(float)(n+1));
d_out[n-1] = 0.0f;
}
void cufft_redft00_1d(float *d_in, float *d_out, int n)
{
/* Allocate memory for extended complex data */
hipfftComplex *d_in_ext;
hipMalloc((void **)&d_in_ext, (2*n-2)*sizeof(hipfftComplex));
/* Extend and convert the data from float to cufftComplex */
DataExtSetRedft00_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_in, d_in_ext, n);
/* Create a 1D FFT plan */
hipfftHandle plan;
hipfftPlan1d(&plan, 2*n-2, HIPFFT_C2C, 1);
/* Allocate memory for transformed data */
hipfftComplex *d_out_ext;
hipMalloc((void **)&d_out_ext, (2*n-2)*sizeof(hipfftComplex));
/* Use the CUFFT plan to transform the signal out of place */
hipfftExecC2C(plan, d_in_ext, d_out_ext, HIPFFT_FORWARD);
/* Subtract the transformed data */
DataSubGetRedft00_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_out_ext, d_out, n);
hipfftDestroy(plan);
hipFree(d_in_ext);
hipFree(d_out_ext);
}
void cufft_iredft00_1d(float *d_in, float *d_out, int n)
{
cufft_redft00_1d(d_in, d_out, n);
}
void cufft_redft10_1d(float *d_in, float *d_out, int n)
{
/* Allocate meory for extended complex data */
hipfftComplex *d_in_ext;
hipMalloc((void **)&d_in_ext, 2*n*sizeof(hipfftComplex));
/* Extend and convert the data from float to cufftComplex */
DataExtSetRedft10_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_in, d_in_ext, n);
/* Create a 1D FFT plan */
hipfftHandle plan;
hipfftPlan1d(&plan, 2*n, HIPFFT_C2C, 1);
/* Allocate memory for transformed data */
hipfftComplex *d_out_ext;
hipMalloc((void **)&d_out_ext, 2*n*sizeof(hipfftComplex));
/* Use the CUFFT plan to transform the signal out of place */
hipfftExecC2C(plan, d_in_ext, d_out_ext, HIPFFT_FORWARD);
/* Allocate memory for shifted data */
hipfftComplex *d_out_ext_shift;
hipMalloc((void **)&d_out_ext_shift, 2*n*sizeof(hipfftComplex));
/* 1/2 phase shift */
PhaseShiftForw_1d<<<(2*n+threads_num-1)/threads_num, threads_num>>>(d_out_ext, d_out_ext_shift, 2*n);
/* Subtract the transformed data */
DataSubGetRedft10_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_out_ext_shift, d_out, n);
hipfftDestroy(plan);
hipFree(d_in_ext);
hipFree(d_out_ext);
hipFree(d_out_ext_shift);
}
void cufft_redft01_1d(float *d_in, float *d_out, int n)
{
/* Allocate meory for extended complex data */
hipfftComplex *d_in_ext;
hipMalloc((void **)&d_in_ext, 2*n*sizeof(hipfftComplex));
/* Extend and convert the data from float to cufftComplex */
DataExtSetRedft01_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_in, d_in_ext, n);
/* Allocate memory for shifted data */
hipfftComplex *d_in_ext_shift;
hipMalloc((void **)&d_in_ext_shift, 2*n*sizeof(hipfftComplex));
/* -1/2 phase shift */
PhaseShiftBack_1d<<<(2*n+threads_num-1)/threads_num, threads_num>>>(d_in_ext, d_in_ext_shift, 2*n);
/* Create a 1D FFT plan */
hipfftHandle plan;
hipfftPlan1d(&plan, 2*n, HIPFFT_C2C, 1);
/* Allocate memory for transformed data */
hipfftComplex *d_out_ext;
hipMalloc((void **)&d_out_ext, 2*n*sizeof(hipfftComplex));
/* Use the CUFFT plan to transform the signal out of place */
hipfftExecC2C(plan, d_in_ext_shift, d_out_ext, HIPFFT_BACKWARD);
/* Subtract the transformed data */
DataSubGetRedft01_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_out_ext, d_out, n);
hipfftDestroy(plan);
hipFree(d_in_ext);
hipFree(d_in_ext_shift);
hipFree(d_out_ext);
}
void cufft_rodft00_1d(float *d_in, float *d_out, int n)
{
/* Allocate memory for extended complex data */
hipfftComplex *d_in_ext;
hipMalloc((void **)&d_in_ext, (2*n+2)*sizeof(hipfftComplex));
/* Extend and convert the data from float to cufftComplex */
DataExtSetRodft00_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_in, d_in_ext, n);
/* Create a 1D FFT plan */
hipfftHandle plan;
hipfftPlan1d(&plan, 2*n+2, HIPFFT_C2C, 1);
/* Allocate memory for transformed data */
hipfftComplex *d_out_ext;
hipMalloc((void **)&d_out_ext, (2*n+2)*sizeof(hipfftComplex));
/* Use the CUFFT plan to transform the signal out of place */
hipfftExecC2C(plan, d_in_ext, d_out_ext, HIPFFT_FORWARD);
/* Subtract the transformed data */
DataSubGetRodft00_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_out_ext, d_out, n);
hipfftDestroy(plan);
hipFree(d_in_ext);
hipFree(d_out_ext);
}
void cufft_irodft00_1d(float *d_in, float *d_out, int n)
{
/* Allocate memory for extended complex data */
hipfftComplex *d_in_ext;
hipMalloc((void **)&d_in_ext, (2*n+2)*sizeof(hipfftComplex));
/* Extend and convert the data from float to cufftComplex */
DataExtSetIRodft00_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_in, d_in_ext, n);
/* Create a 1D FFT plan */
hipfftHandle plan;
hipfftPlan1d(&plan, 2*n+2, HIPFFT_C2C, 1);
/* Allocate memory for transformed data */
hipfftComplex *d_out_ext;
hipMalloc((void **)&d_out_ext, (2*n+2)*sizeof(hipfftComplex));
/* Use the CUFFT plan to transform the signal out of place */
hipfftExecC2C(plan, d_in_ext, d_out_ext, HIPFFT_BACKWARD);
/* Subtract the transformed data */
DataSubGetIRodft00_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_out_ext, d_out, n);
hipfftDestroy(plan);
hipFree(d_in_ext);
hipFree(d_out_ext);
}
void cufft_rodft10_1d(float *d_in, float *d_out, int n)
{
/* Allocate meory for extended complex data */
hipfftComplex *d_in_ext;
hipMalloc((void **)&d_in_ext, 2*n*sizeof(hipfftComplex));
/* Extend and convert the data from float to cufftComplex */
DataExtSetRodft10_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_in, d_in_ext, n);
/* Create a 1D FFT plan */
hipfftHandle plan;
hipfftPlan1d(&plan, 2*n, HIPFFT_C2C, 1);
/* Allocate memory for transformed data */
hipfftComplex *d_out_ext;
hipMalloc((void **)&d_out_ext, 2*n*sizeof(hipfftComplex));
/* Use the CUFFT plan to transform the signal out of place */
hipfftExecC2C(plan, d_in_ext, d_out_ext, HIPFFT_FORWARD);
/* Allocate memory for shifted data */
hipfftComplex *d_out_ext_shift;
hipMalloc((void **)&d_out_ext_shift, 2*n*sizeof(hipfftComplex));
/* 1/2 phase shift */
PhaseShiftForw_1d<<<(2*n+threads_num-1)/threads_num, threads_num>>>(d_out_ext, d_out_ext_shift, 2*n);
/* Subtract the transformed data */
DataSubGetRodft10_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_out_ext_shift, d_out, n);
hipfftDestroy(plan);
hipFree(d_in_ext);
hipFree(d_out_ext);
hipFree(d_out_ext_shift);
}
void cufft_rodft01_1d(float *d_in, float *d_out, int n)
{
/* Allocate meory for extended complex data */
hipfftComplex *d_in_ext;
hipMalloc((void **)&d_in_ext, 2*n*sizeof(hipfftComplex));
/* Extend and convert the data from float to cufftComplex */
DataExtSetRodft01_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_in, d_in_ext, n);
/* Allocate memory for shifted data */
hipfftComplex *d_in_ext_shift;
hipMalloc((void **)&d_in_ext_shift, 2*n*sizeof(hipfftComplex));
/* -1/2 phase shift */
PhaseShiftBack_1d<<<(2*n+threads_num-1)/threads_num, threads_num>>>(d_in_ext, d_in_ext_shift, 2*n);
/* Create a 1D FFT plan */
hipfftHandle plan;
hipfftPlan1d(&plan, 2*n, HIPFFT_C2C, 1);
/* Allocate memory for transformed data */
hipfftComplex *d_out_ext;
hipMalloc((void **)&d_out_ext, 2*n*sizeof(hipfftComplex));
/* Use the CUFFT plan to transform the signal out of place */
hipfftExecC2C(plan, d_in_ext_shift, d_out_ext, HIPFFT_BACKWARD);
/* Subtract the transformed data */
DataSubGetRodft01_1d<<<(n+threads_num-1)/threads_num, threads_num>>>(d_out_ext, d_out, n);
hipfftDestroy(plan);
hipFree(d_in_ext);
hipFree(d_in_ext_shift);
hipFree(d_out_ext);
}
static __global__ void DataExtSetRedft00_1d(float *d_in, hipfftComplex *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
//for (int ix=tid; ix<n; ix+=threads_num)
if (ix < n)
{
d_out[ix].x = d_in[ix];
d_out[ix].y = 0.0f;
if (ix<n-2)
{
d_out[2*n-3-ix].x = d_in[ix+1];
d_out[2*n-3-ix].y = 0.0f;
}
}
}
static __global__ void DataSubGetRedft00_1d(hipfftComplex *d_in, float *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
//for (int ix=tid; ix<n; ix+=threads_num)
if (ix < n)
d_out[ix] = d_in[ix].x;
}
static __global__ void DataExtSetRedft10_1d(float *d_in, hipfftComplex *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
//for (int ix=tid; ix<n; ix+=threads_num)
if (ix < n)
{
d_out[ix].x = d_in[ix];
d_out[ix].y = 0.0f;
d_out[2*n-1-ix].x = d_in[ix];
d_out[2*n-1-ix].y = 0.0f;
}
}
static __global__ void DataSubGetRedft10_1d(hipfftComplex *d_in, float *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
//for (int ix=tid; ix<n; ix+=threads_num)
if (ix < n)
d_out[ix] = d_in[ix].x;
}
static __global__ void DataExtSetRedft01_1d(float *d_in, hipfftComplex *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
//for (int ix=tid; ix<n; ix+=threads_num)
if (ix < n)
{
d_out[ix].x = d_in[ix];
d_out[ix].y = 0.0f;
if (ix<n-1)
{
d_out[2*n-1-ix].x = d_in[ix+1];
d_out[2*n-1-ix].y = 0.0f;
}
}
}
static __global__ void DataSubGetRedft01_1d(hipfftComplex *d_in, float *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
//for (int ix=tid; ix<n; ix+=threads_num)
if (ix < n)
d_out[ix] = d_in[ix].x;
}
static __global__ void DataExtSetRodft00_1d(float *d_in, hipfftComplex *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
//for (int ix=tid; ix<n; ix+=threads_num)
if (ix < n)
{
d_out[ix+1].x = d_in[ix];
d_out[ix+1].y = 0.0f;
d_out[2*n+1-ix].x = -d_in[ix];
d_out[2*n+1-ix].y = 0.0f;
}
d_out[0].x = d_out[0].y = 0.0f;
d_out[n+1].x = d_out[n+1].y = 0.0f;
}
static __global__ void DataSubGetRodft00_1d(hipfftComplex *d_in, float *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
//for (int ix=tid; ix<n; ix+=threads_num)
if (ix < n)
d_out[ix] = -d_in[ix+1].y;
}
static __global__ void DataExtSetIRodft00_1d(float *d_in, hipfftComplex *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
//for (int ix=tid; ix<n; ix+=threads_num)
if (ix < n)
{
d_out[ix+1].y = -d_in[ix];
d_out[ix+1].x = 0.0f;
d_out[2*n+1-ix].y = d_in[ix];
d_out[2*n+1-ix].x = 0.0f;
}
d_out[0].x = d_out[0].y = 0.0f;
d_out[n+1].x = d_out[n+1].y = 0.0f;
}
static __global__ void DataSubGetIRodft00_1d(hipfftComplex *d_in, float *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
//for (int ix=tid; ix<n; ix+=threads_num)
if (ix < n)
d_out[ix] = d_in[ix+1].x;
}
static __global__ void DataExtSetRodft10_1d(float *d_in, hipfftComplex *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
//for (int ix=tid; ix<n; ix+=threads_num)
if (ix < n)
{
d_out[ix].x = d_in[ix];
d_out[ix].y = 0.0f;
d_out[2*n-1-ix].x = -d_in[ix];
d_out[2*n-1-ix].y = 0.0f;
}
}
static __global__ void DataSubGetRodft10_1d(hipfftComplex *d_in, float *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
//for (int ix=tid; ix<n; ix+=threads_num)
if (ix < n)
d_out[ix] = -d_in[ix+1].y;
}
static __global__ void DataExtSetRodft01_1d(float *d_in, hipfftComplex *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
//for (int ix=tid; ix<n; ix+=threads_num)
if (ix < n)
{
d_out[ix+1].y = -d_in[ix];
d_out[ix+1].x = 0.0f;
if (ix<n-1)
{
d_out[2*n-1-ix].y = d_in[ix];
d_out[2*n-1-ix].x = 0.0f;
}
}
d_out[0].x = d_out[0].y = 0.0f;
}
static __global__ void DataSubGetRodft01_1d(hipfftComplex *d_in, float *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
//for (int ix=tid; ix<n; ix+=threads_num)
if (ix < n)
d_out[ix] = d_in[ix].x;
}
static __global__ void PhaseShiftForw_1d(hipfftComplex *d_in, hipfftComplex *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
float d_k;
//for (int ix=tid; ix<n; ix+=threads_num)
if (ix < n)
{
if (ix<n/2)
d_k = (float)ix*pi/(float)(n/2);
else
d_k = -pi+(float)(ix-n/2)*pi/(float)(n/2);
d_out[ix].x = d_in[ix].x*cosf(d_k/2.0f)+d_in[ix].y*sinf(d_k/2.0f);
d_out[ix].y = -d_in[ix].x*sinf(d_k/2.0f)+d_in[ix].y*cosf(d_k/2.0f);
}
}
static __global__ void PhaseShiftBack_1d(hipfftComplex *d_in, hipfftComplex *d_out, int n)
{
//int tid = threadIdx.x;
int ix = blockIdx.x * blockDim.x + threadIdx.x;
float d_k;
//for (int ix=tid; ix<n; ix+=threads_num)
if (ix < n)
{
if (ix<n/2)
d_k = (float)ix*pi/(float)(n/2);
else
d_k = -pi+(float)(ix-n/2)*pi/(float)(n/2);
d_out[ix].x = d_in[ix].x*cosf(d_k/2.0f)-d_in[ix].y*sinf(d_k/2.0f);
d_out[ix].y = d_in[ix].x*sinf(d_k/2.0f)+d_in[ix].y*cosf(d_k/2.0f);
}
}
void data_test_forw_1d(float *h_in, float *h_out, int n)
{
float *d_in;
hipMalloc((void **)&d_in, n*sizeof(float));
hipMemcpy(d_in, h_in, n*sizeof(float), hipMemcpyHostToDevice);
float *d_out;
hipMalloc((void **)&d_out, n*sizeof(float));
cufft_rodft00_1d(d_in, d_out, n);
hipMemcpy(h_out, d_out, n*sizeof(float), hipMemcpyDeviceToHost);
hipFree(d_in);
hipFree(d_out);
}
void data_test_back_1d(float *h_in, float *h_out, int n)
{
float *d_in;
hipMalloc((void **)&d_in, n*sizeof(float));
hipMemcpy(d_in, h_in, n*sizeof(float), hipMemcpyHostToDevice);
float *d_out;
hipMalloc((void **)&d_out, n*sizeof(float));
cufft_rodft01_1d(d_in, d_out, n);
hipMemcpy(h_out, d_out, n*sizeof(float), hipMemcpyDeviceToHost);
hipFree(d_in);
hipFree(d_out);
}
void data_test_derv_1d(float *h_in, float *h_out, float dx, int n)
{
float *d_in;
hipMalloc((void **)&d_in, n*sizeof(float));
hipMemcpy(d_in, h_in, n*sizeof(float), hipMemcpyHostToDevice);
float *d_out;
hipMalloc((void **)&d_out, n*sizeof(float));
cufft_dct2_idst1_1d(d_in, d_out, dx, n);
hipMemcpy(h_out, d_out, n*sizeof(float), hipMemcpyDeviceToHost);
hipFree(d_in);
hipFree(d_out);
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define ROUND_OFF 50000
#define CUDA_NUM_THREADS 1024
#define WARPS_PER_BLOCK 1
#define THREADS_PER_WARP 32
#define CUDA_KERNEL_LOOP(i, n) for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < (n); i += blockDim.x * gridDim.x)
#define GET_BLOCKS(n, t) (n+t-1) / t
// == Dimension rearrangement Kernel
__global__ void CorrelateData_1d(const int nthreads, int num, int topwidth, int topheight, int topchannels, int topcount, int max_displacement, int x_shift, int neighborhood_grid_width, int kernel_radius, int kernel_size, int stride1, int stride2, int bottomwidth, int bottomheight, int bottomchannels, const float *bottom0, const float *bottom1, float *top)
{
extern __shared__ char patch_data_char[];
float *patch_data = (float *)patch_data_char;
// First (upper left) position of kernel upper-left corner in current center position of neighborhood in image 1
int x1 = blockIdx.x*stride1 + max_displacement;
int y1 = blockIdx.y*stride1;
int item = blockIdx.z;
int ch_off = threadIdx.x;
// Load 3D patch into shared shared memory
for(int j = 0; j < kernel_size; j++) { // HEIGHT
for(int i = 0; i < kernel_size; i++) { // WIDTH
int ji_off = ((j * kernel_size) + i) * bottomchannels;
for(int ch = ch_off; ch < bottomchannels; ch += (WARPS_PER_BLOCK*THREADS_PER_WARP)) { // CHANNELS
int idx1 = ((item * bottomheight + y1+j) * bottomwidth + x1+i) * bottomchannels + ch;
int idxPatchData = ji_off + ch;
patch_data[idxPatchData] = bottom0[idx1];
}
}
}
__syncthreads();
__shared__ float sum[WARPS_PER_BLOCK*THREADS_PER_WARP];
// Compute correlation
for(int top_channel = 0; top_channel < topchannels; top_channel++) {
sum[ch_off] = 0;
int s2o = (top_channel % neighborhood_grid_width + x_shift) * stride2;
for(int j = 0; j < kernel_size; j++) { // HEIGHT
for(int i = 0; i < kernel_size; i++) { // WIDTH
int ji_off = ((j * kernel_size) + i) * bottomchannels;
for(int ch = ch_off; ch < bottomchannels; ch += (WARPS_PER_BLOCK*THREADS_PER_WARP)) { // CHANNELS
int x2 = x1 + s2o;
int idxPatchData = ji_off + ch;
int idx2 = ((item * bottomheight + y1+j) * bottomwidth + x2+i) * bottomchannels + ch;
//int idx2 = ((item * bottomheight + y1+j) * bottomwidth + x1+i) * bottomchannels + ch;
//printf("x1 %d x2 %d bh %d bw %d bc %d i %d ch %d y1 %d idx2 %d\n", x1, x2, bottomheight, bottomwidth, bottomchannels, item, ch, y1, idx2);
sum[ch_off] += patch_data[idxPatchData] * bottom1[idx2];
}
}
}
__syncthreads();
if(ch_off == 0) {
float total_sum = 0;
for(int idx = 0; idx < WARPS_PER_BLOCK*THREADS_PER_WARP; idx++) {
total_sum += sum[idx];
}
//printf("ch_off %d sum %f\n", ch_off, total_sum);
const int sumelems = kernel_size*kernel_size*bottomchannels;
const int index = ((top_channel*topheight + blockIdx.y)*topwidth)+blockIdx.x;
top[index + item*topcount] = total_sum / (float)sumelems;
}
}
// Aggregate
} | .file "tmpxft_0018abd1_00000000-6_CorrelateData_1d.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z58__device_stub__Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_PfiiiiiiiiiiiiiiiiPKfS0_Pf
.type _Z58__device_stub__Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_PfiiiiiiiiiiiiiiiiPKfS0_Pf, @function
_Z58__device_stub__Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_PfiiiiiiiiiiiiiiiiPKfS0_Pf:
.LFB2051:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movl %ecx, 32(%rsp)
movl %r8d, 28(%rsp)
movl %r9d, 24(%rsp)
movq 368(%rsp), %rax
movq %rax, 16(%rsp)
movq 376(%rsp), %rax
movq %rax, 8(%rsp)
movq 384(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 288(%rsp), %rax
movq %rax, 160(%rsp)
leaq 296(%rsp), %rax
movq %rax, 168(%rsp)
leaq 304(%rsp), %rax
movq %rax, 176(%rsp)
leaq 312(%rsp), %rax
movq %rax, 184(%rsp)
leaq 320(%rsp), %rax
movq %rax, 192(%rsp)
leaq 328(%rsp), %rax
movq %rax, 200(%rsp)
leaq 336(%rsp), %rax
movq %rax, 208(%rsp)
leaq 344(%rsp), %rax
movq %rax, 216(%rsp)
leaq 352(%rsp), %rax
movq %rax, 224(%rsp)
leaq 360(%rsp), %rax
movq %rax, 232(%rsp)
leaq 16(%rsp), %rax
movq %rax, 240(%rsp)
leaq 8(%rsp), %rax
movq %rax, 248(%rsp)
movq %rsp, %rax
movq %rax, 256(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 296
pushq 56(%rsp)
.cfi_def_cfa_offset 304
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z58__device_stub__Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_PfiiiiiiiiiiiiiiiiPKfS0_Pf, .-_Z58__device_stub__Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_PfiiiiiiiiiiiiiiiiPKfS0_Pf
.globl _Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf
.type _Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf, @function
_Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 120(%rsp)
.cfi_def_cfa_offset 32
pushq 120(%rsp)
.cfi_def_cfa_offset 40
pushq 120(%rsp)
.cfi_def_cfa_offset 48
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 72
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 80
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 88
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 96
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 104
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 112
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 120
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 128
call _Z58__device_stub__Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_PfiiiiiiiiiiiiiiiiPKfS0_Pf
addq $120, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf, .-_Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define ROUND_OFF 50000
#define CUDA_NUM_THREADS 1024
#define WARPS_PER_BLOCK 1
#define THREADS_PER_WARP 32
#define CUDA_KERNEL_LOOP(i, n) for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < (n); i += blockDim.x * gridDim.x)
#define GET_BLOCKS(n, t) (n+t-1) / t
// == Dimension rearrangement Kernel
__global__ void CorrelateData_1d(const int nthreads, int num, int topwidth, int topheight, int topchannels, int topcount, int max_displacement, int x_shift, int neighborhood_grid_width, int kernel_radius, int kernel_size, int stride1, int stride2, int bottomwidth, int bottomheight, int bottomchannels, const float *bottom0, const float *bottom1, float *top)
{
extern __shared__ char patch_data_char[];
float *patch_data = (float *)patch_data_char;
// First (upper left) position of kernel upper-left corner in current center position of neighborhood in image 1
int x1 = blockIdx.x*stride1 + max_displacement;
int y1 = blockIdx.y*stride1;
int item = blockIdx.z;
int ch_off = threadIdx.x;
// Load 3D patch into shared shared memory
for(int j = 0; j < kernel_size; j++) { // HEIGHT
for(int i = 0; i < kernel_size; i++) { // WIDTH
int ji_off = ((j * kernel_size) + i) * bottomchannels;
for(int ch = ch_off; ch < bottomchannels; ch += (WARPS_PER_BLOCK*THREADS_PER_WARP)) { // CHANNELS
int idx1 = ((item * bottomheight + y1+j) * bottomwidth + x1+i) * bottomchannels + ch;
int idxPatchData = ji_off + ch;
patch_data[idxPatchData] = bottom0[idx1];
}
}
}
__syncthreads();
__shared__ float sum[WARPS_PER_BLOCK*THREADS_PER_WARP];
// Compute correlation
for(int top_channel = 0; top_channel < topchannels; top_channel++) {
sum[ch_off] = 0;
int s2o = (top_channel % neighborhood_grid_width + x_shift) * stride2;
for(int j = 0; j < kernel_size; j++) { // HEIGHT
for(int i = 0; i < kernel_size; i++) { // WIDTH
int ji_off = ((j * kernel_size) + i) * bottomchannels;
for(int ch = ch_off; ch < bottomchannels; ch += (WARPS_PER_BLOCK*THREADS_PER_WARP)) { // CHANNELS
int x2 = x1 + s2o;
int idxPatchData = ji_off + ch;
int idx2 = ((item * bottomheight + y1+j) * bottomwidth + x2+i) * bottomchannels + ch;
//int idx2 = ((item * bottomheight + y1+j) * bottomwidth + x1+i) * bottomchannels + ch;
//printf("x1 %d x2 %d bh %d bw %d bc %d i %d ch %d y1 %d idx2 %d\n", x1, x2, bottomheight, bottomwidth, bottomchannels, item, ch, y1, idx2);
sum[ch_off] += patch_data[idxPatchData] * bottom1[idx2];
}
}
}
__syncthreads();
if(ch_off == 0) {
float total_sum = 0;
for(int idx = 0; idx < WARPS_PER_BLOCK*THREADS_PER_WARP; idx++) {
total_sum += sum[idx];
}
//printf("ch_off %d sum %f\n", ch_off, total_sum);
const int sumelems = kernel_size*kernel_size*bottomchannels;
const int index = ((top_channel*topheight + blockIdx.y)*topwidth)+blockIdx.x;
top[index + item*topcount] = total_sum / (float)sumelems;
}
}
// Aggregate
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define ROUND_OFF 50000
#define CUDA_NUM_THREADS 1024
#define WARPS_PER_BLOCK 1
#define THREADS_PER_WARP 32
#define CUDA_KERNEL_LOOP(i, n) for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < (n); i += blockDim.x * gridDim.x)
#define GET_BLOCKS(n, t) (n+t-1) / t
// == Dimension rearrangement Kernel
__global__ void CorrelateData_1d(const int nthreads, int num, int topwidth, int topheight, int topchannels, int topcount, int max_displacement, int x_shift, int neighborhood_grid_width, int kernel_radius, int kernel_size, int stride1, int stride2, int bottomwidth, int bottomheight, int bottomchannels, const float *bottom0, const float *bottom1, float *top)
{
extern __shared__ char patch_data_char[];
float *patch_data = (float *)patch_data_char;
// First (upper left) position of kernel upper-left corner in current center position of neighborhood in image 1
int x1 = blockIdx.x*stride1 + max_displacement;
int y1 = blockIdx.y*stride1;
int item = blockIdx.z;
int ch_off = threadIdx.x;
// Load 3D patch into shared shared memory
for(int j = 0; j < kernel_size; j++) { // HEIGHT
for(int i = 0; i < kernel_size; i++) { // WIDTH
int ji_off = ((j * kernel_size) + i) * bottomchannels;
for(int ch = ch_off; ch < bottomchannels; ch += (WARPS_PER_BLOCK*THREADS_PER_WARP)) { // CHANNELS
int idx1 = ((item * bottomheight + y1+j) * bottomwidth + x1+i) * bottomchannels + ch;
int idxPatchData = ji_off + ch;
patch_data[idxPatchData] = bottom0[idx1];
}
}
}
__syncthreads();
__shared__ float sum[WARPS_PER_BLOCK*THREADS_PER_WARP];
// Compute correlation
for(int top_channel = 0; top_channel < topchannels; top_channel++) {
sum[ch_off] = 0;
int s2o = (top_channel % neighborhood_grid_width + x_shift) * stride2;
for(int j = 0; j < kernel_size; j++) { // HEIGHT
for(int i = 0; i < kernel_size; i++) { // WIDTH
int ji_off = ((j * kernel_size) + i) * bottomchannels;
for(int ch = ch_off; ch < bottomchannels; ch += (WARPS_PER_BLOCK*THREADS_PER_WARP)) { // CHANNELS
int x2 = x1 + s2o;
int idxPatchData = ji_off + ch;
int idx2 = ((item * bottomheight + y1+j) * bottomwidth + x2+i) * bottomchannels + ch;
//int idx2 = ((item * bottomheight + y1+j) * bottomwidth + x1+i) * bottomchannels + ch;
//printf("x1 %d x2 %d bh %d bw %d bc %d i %d ch %d y1 %d idx2 %d\n", x1, x2, bottomheight, bottomwidth, bottomchannels, item, ch, y1, idx2);
sum[ch_off] += patch_data[idxPatchData] * bottom1[idx2];
}
}
}
__syncthreads();
if(ch_off == 0) {
float total_sum = 0;
for(int idx = 0; idx < WARPS_PER_BLOCK*THREADS_PER_WARP; idx++) {
total_sum += sum[idx];
}
//printf("ch_off %d sum %f\n", ch_off, total_sum);
const int sumelems = kernel_size*kernel_size*bottomchannels;
const int index = ((top_channel*topheight + blockIdx.y)*topwidth)+blockIdx.x;
top[index + item*topcount] = total_sum / (float)sumelems;
}
}
// Aggregate
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define ROUND_OFF 50000
#define CUDA_NUM_THREADS 1024
#define WARPS_PER_BLOCK 1
#define THREADS_PER_WARP 32
#define CUDA_KERNEL_LOOP(i, n) for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < (n); i += blockDim.x * gridDim.x)
#define GET_BLOCKS(n, t) (n+t-1) / t
// == Dimension rearrangement Kernel
__global__ void CorrelateData_1d(const int nthreads, int num, int topwidth, int topheight, int topchannels, int topcount, int max_displacement, int x_shift, int neighborhood_grid_width, int kernel_radius, int kernel_size, int stride1, int stride2, int bottomwidth, int bottomheight, int bottomchannels, const float *bottom0, const float *bottom1, float *top)
{
extern __shared__ char patch_data_char[];
float *patch_data = (float *)patch_data_char;
// First (upper left) position of kernel upper-left corner in current center position of neighborhood in image 1
int x1 = blockIdx.x*stride1 + max_displacement;
int y1 = blockIdx.y*stride1;
int item = blockIdx.z;
int ch_off = threadIdx.x;
// Load 3D patch into shared shared memory
for(int j = 0; j < kernel_size; j++) { // HEIGHT
for(int i = 0; i < kernel_size; i++) { // WIDTH
int ji_off = ((j * kernel_size) + i) * bottomchannels;
for(int ch = ch_off; ch < bottomchannels; ch += (WARPS_PER_BLOCK*THREADS_PER_WARP)) { // CHANNELS
int idx1 = ((item * bottomheight + y1+j) * bottomwidth + x1+i) * bottomchannels + ch;
int idxPatchData = ji_off + ch;
patch_data[idxPatchData] = bottom0[idx1];
}
}
}
__syncthreads();
__shared__ float sum[WARPS_PER_BLOCK*THREADS_PER_WARP];
// Compute correlation
for(int top_channel = 0; top_channel < topchannels; top_channel++) {
sum[ch_off] = 0;
int s2o = (top_channel % neighborhood_grid_width + x_shift) * stride2;
for(int j = 0; j < kernel_size; j++) { // HEIGHT
for(int i = 0; i < kernel_size; i++) { // WIDTH
int ji_off = ((j * kernel_size) + i) * bottomchannels;
for(int ch = ch_off; ch < bottomchannels; ch += (WARPS_PER_BLOCK*THREADS_PER_WARP)) { // CHANNELS
int x2 = x1 + s2o;
int idxPatchData = ji_off + ch;
int idx2 = ((item * bottomheight + y1+j) * bottomwidth + x2+i) * bottomchannels + ch;
//int idx2 = ((item * bottomheight + y1+j) * bottomwidth + x1+i) * bottomchannels + ch;
//printf("x1 %d x2 %d bh %d bw %d bc %d i %d ch %d y1 %d idx2 %d\n", x1, x2, bottomheight, bottomwidth, bottomchannels, item, ch, y1, idx2);
sum[ch_off] += patch_data[idxPatchData] * bottom1[idx2];
}
}
}
__syncthreads();
if(ch_off == 0) {
float total_sum = 0;
for(int idx = 0; idx < WARPS_PER_BLOCK*THREADS_PER_WARP; idx++) {
total_sum += sum[idx];
}
//printf("ch_off %d sum %f\n", ch_off, total_sum);
const int sumelems = kernel_size*kernel_size*bottomchannels;
const int index = ((top_channel*topheight + blockIdx.y)*topwidth)+blockIdx.x;
top[index + item*topcount] = total_sum / (float)sumelems;
}
}
// Aggregate
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf
.globl _Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf
.p2align 8
.type _Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf,@function
_Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf:
s_clause 0x3
s_load_b64 s[8:9], s[0:1], 0x28
s_load_b32 s12, s[0:1], 0x3c
s_load_b64 s[18:19], s[0:1], 0x34
s_load_b32 s23, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s24, s13, s9
v_cmp_gt_i32_e32 vcc_lo, s12, v0
s_mul_i32 s25, s14, s9
s_cmp_lt_i32 s8, 1
s_mul_i32 s26, s15, s19
s_mul_i32 s9, s12, s18
s_mul_i32 s22, s12, s8
s_cbranch_scc1 .LBB0_8
s_load_b64 s[4:5], s[0:1], 0x40
s_add_i32 s2, s26, s25
s_add_i32 s3, s23, s24
s_mul_i32 s2, s18, s2
v_lshl_add_u32 v5, v0, 2, 0x80
s_add_i32 s3, s3, s2
s_lshl_b32 s6, s22, 2
v_mad_u64_u32 v[1:2], null, s12, s3, v[0:1]
s_lshl_b32 s7, s12, 2
s_mov_b32 s10, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v1, s9, v1
v_add_nc_u32_e32 v5, s6, v5
s_add_i32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s10, s8
s_cbranch_scc1 .LBB0_8
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v6, v5
v_mov_b32_e32 v2, v1
s_mov_b32 s11, 0
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s16
v_add_nc_u32_e32 v2, s12, v2
v_add_nc_u32_e32 v6, s7, v6
s_add_i32 s11, s11, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s11, s8
s_cbranch_scc1 .LBB0_2
.LBB0_5:
s_and_saveexec_b32 s16, vcc_lo
s_cbranch_execz .LBB0_4
v_ashrrev_i32_e32 v3, 31, v2
v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v8, v0
s_mov_b32 s17, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, s2, s4, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s2, s5, v4, s2
.p2align 6
.LBB0_7:
global_load_b32 v9, v[3:4], off
v_add_nc_u32_e32 v8, 32, v8
v_add_co_u32 v3, s2, v3, 0x80
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v4, s2, 0, v4, s2
v_cmp_le_i32_e64 s3, s12, v8
s_delay_alu instid0(VALU_DEP_1)
s_or_b32 s17, s3, s17
s_waitcnt vmcnt(0)
ds_store_b32 v7, v9
v_add_nc_u32_e32 v7, 0x80, v7
s_and_not1_b32 exec_lo, exec_lo, s17
s_cbranch_execnz .LBB0_7
s_branch .LBB0_4
.LBB0_8:
s_set_inst_prefetch_distance 0x2
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_24
s_clause 0x1
s_load_b64 s[10:11], s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x14
s_cmp_gt_i32 s8, 0
s_load_b32 s19, s[0:1], 0x30
s_cselect_b32 s20, -1, 0
v_dual_mov_b32 v8, 0 :: v_dual_lshlrev_b32 v5, 2, v0
s_mul_i32 s27, s8, s8
s_add_i32 s26, s26, s25
s_mul_i32 s27, s27, s12
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v7, 0x80, v5
v_cvt_f32_i32_e32 v6, s27
s_mov_b32 s21, 0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s11, 31
s_mul_i32 s2, s15, s2
s_add_i32 s5, s11, s4
s_add_i32 s13, s2, s13
s_xor_b32 s11, s5, s4
s_clause 0x1
s_load_b64 s[16:17], s[0:1], 0x8
s_load_b128 s[4:7], s[0:1], 0x48
v_cvt_f32_u32_e32 v1, s11
v_cmp_gt_i32_e64 s0, s12, v0
v_cmp_eq_u32_e64 s1, 0, v0
s_add_i32 s15, s23, s24
s_mul_i32 s2, s18, s26
v_rcp_iflag_f32_e32 v1, v1
s_add_i32 s15, s15, s2
s_lshl_b32 s18, s22, 2
s_lshl_b32 s22, s12, 2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1)
v_cvt_u32_f32_e32 v9, v1
s_branch .LBB0_11
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s2
s_add_i32 s21, s21, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s21, s3
s_cbranch_scc1 .LBB0_24
.LBB0_11:
s_and_not1_b32 vcc_lo, exec_lo, s20
ds_store_b32 v5, v8
s_cbranch_vccnz .LBB0_20
v_readfirstlane_b32 s2, v9
s_sub_i32 s23, 0, s11
v_mov_b32_e32 v10, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s23, s23, s2
s_mul_hi_u32 s23, s2, s23
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s23
s_mul_hi_u32 s2, s21, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s2, s2, s11
s_sub_i32 s2, s21, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_sub_i32 s23, s2, s11
s_cmp_ge_u32 s2, s11
s_cselect_b32 s2, s23, s2
s_sub_i32 s23, s2, s11
s_cmp_ge_u32 s2, s11
s_cselect_b32 s2, s23, s2
s_mov_b32 s23, 0
s_add_i32 s2, s2, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s2, s2, s19
s_add_i32 s2, s15, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s12, s2, v[0:1]
s_branch .LBB0_14
.LBB0_13:
s_set_inst_prefetch_distance 0x2
v_add_nc_u32_e32 v1, s9, v1
v_add_nc_u32_e32 v10, s18, v10
s_add_i32 s23, s23, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s23, s8
s_cbranch_scc1 .LBB0_20
.LBB0_14:
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v11, v10 :: v_dual_mov_b32 v2, v1
s_mov_b32 s24, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_16
.p2align 6
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s25
v_add_nc_u32_e32 v2, s12, v2
v_add_nc_u32_e32 v11, s22, v11
s_add_i32 s24, s24, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s24, s8
s_cbranch_scc1 .LBB0_13
.LBB0_16:
s_and_saveexec_b32 s25, s0
s_cbranch_execz .LBB0_15
ds_load_b32 v12, v5
v_ashrrev_i32_e32 v3, 31, v2
v_dual_mov_b32 v13, v11 :: v_dual_mov_b32 v14, v0
s_mov_b32 s26, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.p2align 6
.LBB0_18:
global_load_b32 v15, v[3:4], off
ds_load_b32 v16, v13
v_add_nc_u32_e32 v14, 32, v14
v_add_co_u32 v3, vcc_lo, v3, 0x80
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_le_i32_e64 s2, s12, v14
v_add_nc_u32_e32 v13, 0x80, v13
s_or_b32 s26, s2, s26
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v12, v16, v15
s_and_not1_b32 exec_lo, exec_lo, s26
s_cbranch_execnz .LBB0_18
s_or_b32 exec_lo, exec_lo, s26
ds_store_b32 v5, v12
s_branch .LBB0_15
.LBB0_20:
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, s1
s_cbranch_execz .LBB0_10
v_mov_b32_e32 v1, 0
s_mov_b32 s23, 0
.LBB0_22:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v2, s23
s_add_i32 s23, s23, 4
s_cmpk_eq_i32 s23, 0x80
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v1, v2
s_cbranch_scc0 .LBB0_22
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_scale_f32 v2, null, v6, v6, v1
v_div_scale_f32 v10, vcc_lo, v1, v6, v1
s_mul_i32 s23, s21, s17
v_rcp_f32_e32 v3, v2
s_add_i32 s23, s23, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s23, s23, s16
s_add_i32 s24, s13, s23
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s25, s24, 31
s_lshl_b64 s[24:25], s[24:25], 2
s_waitcnt_depctr 0xfff
v_fma_f32 v4, -v2, v3, 1.0
s_add_u32 s24, s6, s24
s_addc_u32 s25, s7, s25
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v4, v3
v_mul_f32_e32 v4, v10, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v11, -v2, v4, v10
v_fmac_f32_e32 v4, v11, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v2, -v2, v4, v10
v_div_fmas_f32 v2, v2, v3, v4
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v1, v2, v6, v1
global_store_b32 v8, v1, s[24:25]
s_branch .LBB0_10
.LBB0_24:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf
.amdhsa_group_segment_fixed_size 128
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 88
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 28
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf, .Lfunc_end0-_Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 60
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 80
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 128
.kernarg_segment_align: 8
.kernarg_segment_size: 88
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf
.private_segment_fixed_size: 0
.sgpr_count: 30
.sgpr_spill_count: 0
.symbol: _Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define ROUND_OFF 50000
#define CUDA_NUM_THREADS 1024
#define WARPS_PER_BLOCK 1
#define THREADS_PER_WARP 32
#define CUDA_KERNEL_LOOP(i, n) for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < (n); i += blockDim.x * gridDim.x)
#define GET_BLOCKS(n, t) (n+t-1) / t
// == Dimension rearrangement Kernel
__global__ void CorrelateData_1d(const int nthreads, int num, int topwidth, int topheight, int topchannels, int topcount, int max_displacement, int x_shift, int neighborhood_grid_width, int kernel_radius, int kernel_size, int stride1, int stride2, int bottomwidth, int bottomheight, int bottomchannels, const float *bottom0, const float *bottom1, float *top)
{
extern __shared__ char patch_data_char[];
float *patch_data = (float *)patch_data_char;
// First (upper left) position of kernel upper-left corner in current center position of neighborhood in image 1
int x1 = blockIdx.x*stride1 + max_displacement;
int y1 = blockIdx.y*stride1;
int item = blockIdx.z;
int ch_off = threadIdx.x;
// Load 3D patch into shared shared memory
for(int j = 0; j < kernel_size; j++) { // HEIGHT
for(int i = 0; i < kernel_size; i++) { // WIDTH
int ji_off = ((j * kernel_size) + i) * bottomchannels;
for(int ch = ch_off; ch < bottomchannels; ch += (WARPS_PER_BLOCK*THREADS_PER_WARP)) { // CHANNELS
int idx1 = ((item * bottomheight + y1+j) * bottomwidth + x1+i) * bottomchannels + ch;
int idxPatchData = ji_off + ch;
patch_data[idxPatchData] = bottom0[idx1];
}
}
}
__syncthreads();
__shared__ float sum[WARPS_PER_BLOCK*THREADS_PER_WARP];
// Compute correlation
for(int top_channel = 0; top_channel < topchannels; top_channel++) {
sum[ch_off] = 0;
int s2o = (top_channel % neighborhood_grid_width + x_shift) * stride2;
for(int j = 0; j < kernel_size; j++) { // HEIGHT
for(int i = 0; i < kernel_size; i++) { // WIDTH
int ji_off = ((j * kernel_size) + i) * bottomchannels;
for(int ch = ch_off; ch < bottomchannels; ch += (WARPS_PER_BLOCK*THREADS_PER_WARP)) { // CHANNELS
int x2 = x1 + s2o;
int idxPatchData = ji_off + ch;
int idx2 = ((item * bottomheight + y1+j) * bottomwidth + x2+i) * bottomchannels + ch;
//int idx2 = ((item * bottomheight + y1+j) * bottomwidth + x1+i) * bottomchannels + ch;
//printf("x1 %d x2 %d bh %d bw %d bc %d i %d ch %d y1 %d idx2 %d\n", x1, x2, bottomheight, bottomwidth, bottomchannels, item, ch, y1, idx2);
sum[ch_off] += patch_data[idxPatchData] * bottom1[idx2];
}
}
}
__syncthreads();
if(ch_off == 0) {
float total_sum = 0;
for(int idx = 0; idx < WARPS_PER_BLOCK*THREADS_PER_WARP; idx++) {
total_sum += sum[idx];
}
//printf("ch_off %d sum %f\n", ch_off, total_sum);
const int sumelems = kernel_size*kernel_size*bottomchannels;
const int index = ((top_channel*topheight + blockIdx.y)*topwidth)+blockIdx.x;
top[index + item*topcount] = total_sum / (float)sumelems;
}
}
// Aggregate
} | .text
.file "CorrelateData_1d.hip"
.globl _Z31__device_stub__CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf # -- Begin function _Z31__device_stub__CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf
.p2align 4, 0x90
.type _Z31__device_stub__CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf,@function
_Z31__device_stub__CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf: # @_Z31__device_stub__CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf
.cfi_startproc
# %bb.0:
subq $232, %rsp
.cfi_def_cfa_offset 240
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 28(%rsp), %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rax
movq %rax, 88(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 240(%rsp), %rax
movq %rax, 128(%rsp)
leaq 248(%rsp), %rax
movq %rax, 136(%rsp)
leaq 256(%rsp), %rax
movq %rax, 144(%rsp)
leaq 264(%rsp), %rax
movq %rax, 152(%rsp)
leaq 272(%rsp), %rax
movq %rax, 160(%rsp)
leaq 280(%rsp), %rax
movq %rax, 168(%rsp)
leaq 288(%rsp), %rax
movq %rax, 176(%rsp)
leaq 296(%rsp), %rax
movq %rax, 184(%rsp)
leaq 304(%rsp), %rax
movq %rax, 192(%rsp)
leaq 312(%rsp), %rax
movq %rax, 200(%rsp)
leaq 320(%rsp), %rax
movq %rax, 208(%rsp)
leaq 328(%rsp), %rax
movq %rax, 216(%rsp)
leaq 336(%rsp), %rax
movq %rax, 224(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $248, %rsp
.cfi_adjust_cfa_offset -248
retq
.Lfunc_end0:
.size _Z31__device_stub__CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf, .Lfunc_end0-_Z31__device_stub__CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf,@object # @_Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf
.section .rodata,"a",@progbits
.globl _Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf
.p2align 3, 0x0
_Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf:
.quad _Z31__device_stub__CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf
.size _Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf"
.size .L__unnamed_1, 45
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018abd1_00000000-6_CorrelateData_1d.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z58__device_stub__Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_PfiiiiiiiiiiiiiiiiPKfS0_Pf
.type _Z58__device_stub__Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_PfiiiiiiiiiiiiiiiiPKfS0_Pf, @function
_Z58__device_stub__Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_PfiiiiiiiiiiiiiiiiPKfS0_Pf:
.LFB2051:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movl %ecx, 32(%rsp)
movl %r8d, 28(%rsp)
movl %r9d, 24(%rsp)
movq 368(%rsp), %rax
movq %rax, 16(%rsp)
movq 376(%rsp), %rax
movq %rax, 8(%rsp)
movq 384(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 288(%rsp), %rax
movq %rax, 160(%rsp)
leaq 296(%rsp), %rax
movq %rax, 168(%rsp)
leaq 304(%rsp), %rax
movq %rax, 176(%rsp)
leaq 312(%rsp), %rax
movq %rax, 184(%rsp)
leaq 320(%rsp), %rax
movq %rax, 192(%rsp)
leaq 328(%rsp), %rax
movq %rax, 200(%rsp)
leaq 336(%rsp), %rax
movq %rax, 208(%rsp)
leaq 344(%rsp), %rax
movq %rax, 216(%rsp)
leaq 352(%rsp), %rax
movq %rax, 224(%rsp)
leaq 360(%rsp), %rax
movq %rax, 232(%rsp)
leaq 16(%rsp), %rax
movq %rax, 240(%rsp)
leaq 8(%rsp), %rax
movq %rax, 248(%rsp)
movq %rsp, %rax
movq %rax, 256(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 296
pushq 56(%rsp)
.cfi_def_cfa_offset 304
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z58__device_stub__Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_PfiiiiiiiiiiiiiiiiPKfS0_Pf, .-_Z58__device_stub__Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_PfiiiiiiiiiiiiiiiiPKfS0_Pf
.globl _Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf
.type _Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf, @function
_Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 120(%rsp)
.cfi_def_cfa_offset 32
pushq 120(%rsp)
.cfi_def_cfa_offset 40
pushq 120(%rsp)
.cfi_def_cfa_offset 48
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 72
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 80
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 88
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 96
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 104
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 112
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 120
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 128
call _Z58__device_stub__Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_PfiiiiiiiiiiiiiiiiPKfS0_Pf
addq $120, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf, .-_Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "CorrelateData_1d.hip"
.globl _Z31__device_stub__CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf # -- Begin function _Z31__device_stub__CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf
.p2align 4, 0x90
.type _Z31__device_stub__CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf,@function
_Z31__device_stub__CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf: # @_Z31__device_stub__CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf
.cfi_startproc
# %bb.0:
subq $232, %rsp
.cfi_def_cfa_offset 240
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 28(%rsp), %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rax
movq %rax, 88(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 240(%rsp), %rax
movq %rax, 128(%rsp)
leaq 248(%rsp), %rax
movq %rax, 136(%rsp)
leaq 256(%rsp), %rax
movq %rax, 144(%rsp)
leaq 264(%rsp), %rax
movq %rax, 152(%rsp)
leaq 272(%rsp), %rax
movq %rax, 160(%rsp)
leaq 280(%rsp), %rax
movq %rax, 168(%rsp)
leaq 288(%rsp), %rax
movq %rax, 176(%rsp)
leaq 296(%rsp), %rax
movq %rax, 184(%rsp)
leaq 304(%rsp), %rax
movq %rax, 192(%rsp)
leaq 312(%rsp), %rax
movq %rax, 200(%rsp)
leaq 320(%rsp), %rax
movq %rax, 208(%rsp)
leaq 328(%rsp), %rax
movq %rax, 216(%rsp)
leaq 336(%rsp), %rax
movq %rax, 224(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $248, %rsp
.cfi_adjust_cfa_offset -248
retq
.Lfunc_end0:
.size _Z31__device_stub__CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf, .Lfunc_end0-_Z31__device_stub__CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf,@object # @_Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf
.section .rodata,"a",@progbits
.globl _Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf
.p2align 3, 0x0
_Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf:
.quad _Z31__device_stub__CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf
.size _Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf"
.size .L__unnamed_1, 45
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16CorrelateData_1diiiiiiiiiiiiiiiiPKfS0_Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void CopyConnectionsCoordinatesKernel( int *connectionMatrix, float *pointsCoordinates, float *vertexData, int *connectionCount, int maxCells )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < maxCells * maxCells)
{
if(connectionMatrix[threadId] == 1)
{
int from = threadId / maxCells;
int to = threadId % maxCells;
if(to > from)
{
//int vertexDataOffset = maxCells * 3;
int vertexDataOffset = 0;
int connIdx = atomicAdd( &connectionCount[0], 1);
vertexData[vertexDataOffset + connIdx * 6] = pointsCoordinates[from * 3];
vertexData[vertexDataOffset + connIdx * 6 + 1] = pointsCoordinates[from * 3 + 1];
vertexData[vertexDataOffset + connIdx * 6 + 2] = pointsCoordinates[from * 3 + 2];
vertexData[vertexDataOffset + connIdx * 6 + 3] = pointsCoordinates[to * 3];
vertexData[vertexDataOffset + connIdx * 6 + 4] = pointsCoordinates[to * 3 + 1];
vertexData[vertexDataOffset + connIdx * 6 + 5] = pointsCoordinates[to * 3 + 2];
}
}
}
} | code for sm_80
Function : _Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ULDC UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIMAD UR4, UR4, UR4, URZ ; /* 0x00000004040472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0070*/ IMAD R5, R0, c[0x0][0x0], R5 ; /* 0x0000000000057a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.AND P0, PT, R5, UR4, PT ; /* 0x0000000405007c0c */
/* 0x000fda000bf06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00c0*/ IMAD.WIDE R2, R5, R0, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fcc00078e0200 */
/*00d0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00e0*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x004fda0003f05270 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ IABS R7, c[0x0][0x180] ; /* 0x0000600000077a13 */
/* 0x000fc80000000000 */
/*0110*/ I2F.RP R4, R7 ; /* 0x0000000700047306 */
/* 0x000e300000209400 */
/*0120*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0130*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0140*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0150*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe200078e00ff */
/*0160*/ IADD3 R6, RZ, -R3, RZ ; /* 0x80000003ff067210 */
/* 0x002fca0007ffe0ff */
/*0170*/ IMAD R9, R6, R7, RZ ; /* 0x0000000706097224 */
/* 0x000fe200078e02ff */
/*0180*/ IABS R6, R5 ; /* 0x0000000500067213 */
/* 0x000fc60000000000 */
/*0190*/ IMAD.HI.U32 R3, R3, R9, R2 ; /* 0x0000000903037227 */
/* 0x000fe200078e0002 */
/*01a0*/ LOP3.LUT R2, R5, c[0x0][0x180], RZ, 0x3c, !PT ; /* 0x0000600005027a12 */
/* 0x000fc800078e3cff */
/*01b0*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f26270 */
/*01c0*/ IMAD.HI.U32 R3, R3, R6, RZ ; /* 0x0000000603037227 */
/* 0x000fca00078e00ff */
/*01d0*/ IADD3 R4, -R3, RZ, RZ ; /* 0x000000ff03047210 */
/* 0x000fca0007ffe1ff */
/*01e0*/ IMAD R4, R7, R4, R6 ; /* 0x0000000407047224 */
/* 0x000fca00078e0206 */
/*01f0*/ ISETP.GT.U32.AND P2, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x000fda0003f44070 */
/*0200*/ @!P2 IMAD.IADD R4, R4, 0x1, -R7 ; /* 0x000000010404a824 */
/* 0x000fe200078e0a07 */
/*0210*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*0220*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fe40003f45270 */
/*0230*/ ISETP.GE.U32.AND P0, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x000fda0003f06070 */
/*0240*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fc80007ffe0ff */
/*0250*/ MOV R4, R3 ; /* 0x0000000300047202 */
/* 0x000fca0000000f00 */
/*0260*/ @!P1 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff049224 */
/* 0x000fe200078e0a04 */
/*0270*/ @!P2 LOP3.LUT R4, RZ, c[0x0][0x180], RZ, 0x33, !PT ; /* 0x00006000ff04aa12 */
/* 0x000fc800078e33ff */
/*0280*/ IADD3 R2, -R4, RZ, RZ ; /* 0x000000ff04027210 */
/* 0x000fca0007ffe1ff */
/*0290*/ IMAD R17, R2, c[0x0][0x180], R5 ; /* 0x0000600002117a24 */
/* 0x000fca00078e0205 */
/*02a0*/ ISETP.GT.AND P0, PT, R17, R4, PT ; /* 0x000000041100720c */
/* 0x000fda0003f04270 */
/*02b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*02c0*/ S2R R3, SR_LANEID ; /* 0x0000000000037919 */
/* 0x000e220000000000 */
/*02d0*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe200038e0100 */
/*02e0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fe200078e00ff */
/*02f0*/ FLO.U32 R8, UR6 ; /* 0x0000000600087d00 */
/* 0x000e3000080e0000 */
/*0300*/ POPC R11, UR6 ; /* 0x00000006000b7d09 */
/* 0x000e620008000000 */
/*0310*/ ISETP.EQ.U32.AND P0, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x001fc40003f02070 */
/*0320*/ MOV R3, c[0x0][0x17c] ; /* 0x00005f0000037a02 */
/* 0x000fd60000000f00 */
/*0330*/ @P0 ATOMG.E.ADD.STRONG.GPU PT, R15, [R2.64], R11 ; /* 0x0000000b020f09a8 */
/* 0x002ea200081ee1c4 */
/*0340*/ IMAD R5, R4, 0x3, RZ ; /* 0x0000000304057824 */
/* 0x000fc800078e02ff */
/*0350*/ IMAD.WIDE R4, R5, R0, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0200 */
/*0360*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ee8000c1e1900 */
/*0370*/ S2R R7, SR_LTMASK ; /* 0x0000000000077919 */
/* 0x000e240000003900 */
/*0380*/ LOP3.LUT R10, R7, UR6, RZ, 0xc0, !PT ; /* 0x00000006070a7c12 */
/* 0x001fc8000f8ec0ff */
/*0390*/ POPC R7, R10 ; /* 0x0000000a00077309 */
/* 0x000e220000000000 */
/*03a0*/ SHFL.IDX PT, R6, R15, R8, 0x1f ; /* 0x00001f080f067589 */
/* 0x004e2400000e0000 */
/*03b0*/ IMAD.IADD R6, R6, 0x1, R7 ; /* 0x0000000106067824 */
/* 0x001fc800078e0207 */
/*03c0*/ IMAD R7, R6, 0x6, RZ ; /* 0x0000000606077824 */
/* 0x000fc800078e02ff */
/*03d0*/ IMAD.WIDE R6, R7, R0, c[0x0][0x170] ; /* 0x00005c0007067625 */
/* 0x000fca00078e0200 */
/*03e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0081e8000c101904 */
/*03f0*/ LDG.E R11, [R4.64+0x4] ; /* 0x00000404040b7981 */
/* 0x000ea2000c1e1900 */
/*0400*/ IMAD R3, R17, 0x3, RZ ; /* 0x0000000311037824 */
/* 0x000fc600078e02ff */
/*0410*/ STG.E [R6.64+0x4], R11 ; /* 0x0000040b06007986 */
/* 0x004fe8000c101904 */
/*0420*/ LDG.E R13, [R4.64+0x8] ; /* 0x00000804040d7981 */
/* 0x000ea2000c1e1900 */
/*0430*/ IMAD.WIDE R2, R3, R0, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fc600078e0200 */
/*0440*/ STG.E [R6.64+0x8], R13 ; /* 0x0000080d06007986 */
/* 0x004fe8000c101904 */
/*0450*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ea8000c1e1900 */
/*0460*/ STG.E [R6.64+0xc], R15 ; /* 0x00000c0f06007986 */
/* 0x004fe8000c101904 */
/*0470*/ LDG.E R17, [R2.64+0x4] ; /* 0x0000040402117981 */
/* 0x000ea8000c1e1900 */
/*0480*/ STG.E [R6.64+0x10], R17 ; /* 0x0000101106007986 */
/* 0x004fe8000c101904 */
/*0490*/ LDG.E R9, [R2.64+0x8] ; /* 0x0000080402097981 */
/* 0x001ea8000c1e1900 */
/*04a0*/ STG.E [R6.64+0x14], R9 ; /* 0x0000140906007986 */
/* 0x004fe2000c101904 */
/*04b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04c0*/ BRA 0x4c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void CopyConnectionsCoordinatesKernel( int *connectionMatrix, float *pointsCoordinates, float *vertexData, int *connectionCount, int maxCells )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < maxCells * maxCells)
{
if(connectionMatrix[threadId] == 1)
{
int from = threadId / maxCells;
int to = threadId % maxCells;
if(to > from)
{
//int vertexDataOffset = maxCells * 3;
int vertexDataOffset = 0;
int connIdx = atomicAdd( &connectionCount[0], 1);
vertexData[vertexDataOffset + connIdx * 6] = pointsCoordinates[from * 3];
vertexData[vertexDataOffset + connIdx * 6 + 1] = pointsCoordinates[from * 3 + 1];
vertexData[vertexDataOffset + connIdx * 6 + 2] = pointsCoordinates[from * 3 + 2];
vertexData[vertexDataOffset + connIdx * 6 + 3] = pointsCoordinates[to * 3];
vertexData[vertexDataOffset + connIdx * 6 + 4] = pointsCoordinates[to * 3 + 1];
vertexData[vertexDataOffset + connIdx * 6 + 5] = pointsCoordinates[to * 3 + 2];
}
}
}
} | .file "tmpxft_0002ec72_00000000-6_CopyConnectionsCoordinatesKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z60__device_stub__Z32CopyConnectionsCoordinatesKernelPiPfS0_S_iPiPfS0_S_i
.type _Z60__device_stub__Z32CopyConnectionsCoordinatesKernelPiPfS0_S_iPiPfS0_S_i, @function
_Z60__device_stub__Z32CopyConnectionsCoordinatesKernelPiPfS0_S_iPiPfS0_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z60__device_stub__Z32CopyConnectionsCoordinatesKernelPiPfS0_S_iPiPfS0_S_i, .-_Z60__device_stub__Z32CopyConnectionsCoordinatesKernelPiPfS0_S_iPiPfS0_S_i
.globl _Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i
.type _Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i, @function
_Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z60__device_stub__Z32CopyConnectionsCoordinatesKernelPiPfS0_S_iPiPfS0_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i, .-_Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void CopyConnectionsCoordinatesKernel( int *connectionMatrix, float *pointsCoordinates, float *vertexData, int *connectionCount, int maxCells )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < maxCells * maxCells)
{
if(connectionMatrix[threadId] == 1)
{
int from = threadId / maxCells;
int to = threadId % maxCells;
if(to > from)
{
//int vertexDataOffset = maxCells * 3;
int vertexDataOffset = 0;
int connIdx = atomicAdd( &connectionCount[0], 1);
vertexData[vertexDataOffset + connIdx * 6] = pointsCoordinates[from * 3];
vertexData[vertexDataOffset + connIdx * 6 + 1] = pointsCoordinates[from * 3 + 1];
vertexData[vertexDataOffset + connIdx * 6 + 2] = pointsCoordinates[from * 3 + 2];
vertexData[vertexDataOffset + connIdx * 6 + 3] = pointsCoordinates[to * 3];
vertexData[vertexDataOffset + connIdx * 6 + 4] = pointsCoordinates[to * 3 + 1];
vertexData[vertexDataOffset + connIdx * 6 + 5] = pointsCoordinates[to * 3 + 2];
}
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void CopyConnectionsCoordinatesKernel( int *connectionMatrix, float *pointsCoordinates, float *vertexData, int *connectionCount, int maxCells )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < maxCells * maxCells)
{
if(connectionMatrix[threadId] == 1)
{
int from = threadId / maxCells;
int to = threadId % maxCells;
if(to > from)
{
//int vertexDataOffset = maxCells * 3;
int vertexDataOffset = 0;
int connIdx = atomicAdd( &connectionCount[0], 1);
vertexData[vertexDataOffset + connIdx * 6] = pointsCoordinates[from * 3];
vertexData[vertexDataOffset + connIdx * 6 + 1] = pointsCoordinates[from * 3 + 1];
vertexData[vertexDataOffset + connIdx * 6 + 2] = pointsCoordinates[from * 3 + 2];
vertexData[vertexDataOffset + connIdx * 6 + 3] = pointsCoordinates[to * 3];
vertexData[vertexDataOffset + connIdx * 6 + 4] = pointsCoordinates[to * 3 + 1];
vertexData[vertexDataOffset + connIdx * 6 + 5] = pointsCoordinates[to * 3 + 2];
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void CopyConnectionsCoordinatesKernel( int *connectionMatrix, float *pointsCoordinates, float *vertexData, int *connectionCount, int maxCells )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < maxCells * maxCells)
{
if(connectionMatrix[threadId] == 1)
{
int from = threadId / maxCells;
int to = threadId % maxCells;
if(to > from)
{
//int vertexDataOffset = maxCells * 3;
int vertexDataOffset = 0;
int connIdx = atomicAdd( &connectionCount[0], 1);
vertexData[vertexDataOffset + connIdx * 6] = pointsCoordinates[from * 3];
vertexData[vertexDataOffset + connIdx * 6 + 1] = pointsCoordinates[from * 3 + 1];
vertexData[vertexDataOffset + connIdx * 6 + 2] = pointsCoordinates[from * 3 + 2];
vertexData[vertexDataOffset + connIdx * 6 + 3] = pointsCoordinates[to * 3];
vertexData[vertexDataOffset + connIdx * 6 + 4] = pointsCoordinates[to * 3 + 1];
vertexData[vertexDataOffset + connIdx * 6 + 5] = pointsCoordinates[to * 3 + 2];
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i
.globl _Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i
.p2align 8
.type _Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i,@function
_Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x28
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s2, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_and_b32 s4, s4, 0xffff
s_add_i32 s3, s3, s14
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s3, s4, v[0:1]
s_mul_i32 s3, s2, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_6
s_load_b64 s[4:5], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 1, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_6
s_ashr_i32 s3, s2, 31
v_ashrrev_i32_e32 v3, 31, v1
s_add_i32 s4, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s4, s4, s3
v_add_nc_u32_e32 v4, v1, v3
v_cvt_f32_u32_e32 v0, s4
s_sub_i32 s5, 0, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v4, v3
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v3, s3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v4, v0
v_mul_lo_u32 v2, v0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v0
v_subrev_nc_u32_e32 v5, s4, v2
v_cmp_le_u32_e32 vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 1, v0
v_cmp_le_u32_e32 vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v0, v3
v_mul_lo_u32 v0, v2, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v1, v0
v_cmp_gt_i32_e32 vcc_lo, v0, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_6
s_mov_b32 s3, exec_lo
s_mov_b32 s2, exec_lo
v_mbcnt_lo_u32_b32 v1, s3, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v1
s_cbranch_execz .LBB0_5
s_load_b64 s[4:5], s[0:1], 0x18
s_bcnt1_i32_b32 s3, s3
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, s3
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v3, v3, v4, s[4:5] glc
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s2
s_load_b128 s[0:3], s[0:1], 0x8
v_lshl_add_u32 v4, v2, 1, v2
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s4, v3
v_lshl_add_u32 v0, v0, 1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v5, 31, v4
v_add_nc_u32_e32 v1, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_mul_lo_u32 v1, v1, 6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
v_lshlrev_b64 v[2:3], 2, v[1:2]
global_load_b32 v6, v[4:5], off
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v6, off
global_load_b32 v8, v[4:5], off offset:4
v_or_b32_e32 v6, 1, v1
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[6:7], v8, off
global_load_b32 v4, v[4:5], off offset:8
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v4, off offset:8
global_load_b32 v4, v[0:1], off
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v4, off offset:12
global_load_b32 v4, v[0:1], off offset:4
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v4, off offset:16
global_load_b32 v0, v[0:1], off offset:8
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v0, off offset:20
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i, .Lfunc_end0-_Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void CopyConnectionsCoordinatesKernel( int *connectionMatrix, float *pointsCoordinates, float *vertexData, int *connectionCount, int maxCells )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < maxCells * maxCells)
{
if(connectionMatrix[threadId] == 1)
{
int from = threadId / maxCells;
int to = threadId % maxCells;
if(to > from)
{
//int vertexDataOffset = maxCells * 3;
int vertexDataOffset = 0;
int connIdx = atomicAdd( &connectionCount[0], 1);
vertexData[vertexDataOffset + connIdx * 6] = pointsCoordinates[from * 3];
vertexData[vertexDataOffset + connIdx * 6 + 1] = pointsCoordinates[from * 3 + 1];
vertexData[vertexDataOffset + connIdx * 6 + 2] = pointsCoordinates[from * 3 + 2];
vertexData[vertexDataOffset + connIdx * 6 + 3] = pointsCoordinates[to * 3];
vertexData[vertexDataOffset + connIdx * 6 + 4] = pointsCoordinates[to * 3 + 1];
vertexData[vertexDataOffset + connIdx * 6 + 5] = pointsCoordinates[to * 3 + 2];
}
}
}
} | .text
.file "CopyConnectionsCoordinatesKernel.hip"
.globl _Z47__device_stub__CopyConnectionsCoordinatesKernelPiPfS0_S_i # -- Begin function _Z47__device_stub__CopyConnectionsCoordinatesKernelPiPfS0_S_i
.p2align 4, 0x90
.type _Z47__device_stub__CopyConnectionsCoordinatesKernelPiPfS0_S_i,@function
_Z47__device_stub__CopyConnectionsCoordinatesKernelPiPfS0_S_i: # @_Z47__device_stub__CopyConnectionsCoordinatesKernelPiPfS0_S_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z47__device_stub__CopyConnectionsCoordinatesKernelPiPfS0_S_i, .Lfunc_end0-_Z47__device_stub__CopyConnectionsCoordinatesKernelPiPfS0_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i,@object # @_Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i
.section .rodata,"a",@progbits
.globl _Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i
.p2align 3, 0x0
_Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i:
.quad _Z47__device_stub__CopyConnectionsCoordinatesKernelPiPfS0_S_i
.size _Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i"
.size .L__unnamed_1, 47
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z47__device_stub__CopyConnectionsCoordinatesKernelPiPfS0_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ULDC UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIMAD UR4, UR4, UR4, URZ ; /* 0x00000004040472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0070*/ IMAD R5, R0, c[0x0][0x0], R5 ; /* 0x0000000000057a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.AND P0, PT, R5, UR4, PT ; /* 0x0000000405007c0c */
/* 0x000fda000bf06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00c0*/ IMAD.WIDE R2, R5, R0, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fcc00078e0200 */
/*00d0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00e0*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x004fda0003f05270 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ IABS R7, c[0x0][0x180] ; /* 0x0000600000077a13 */
/* 0x000fc80000000000 */
/*0110*/ I2F.RP R4, R7 ; /* 0x0000000700047306 */
/* 0x000e300000209400 */
/*0120*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0130*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0140*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0150*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe200078e00ff */
/*0160*/ IADD3 R6, RZ, -R3, RZ ; /* 0x80000003ff067210 */
/* 0x002fca0007ffe0ff */
/*0170*/ IMAD R9, R6, R7, RZ ; /* 0x0000000706097224 */
/* 0x000fe200078e02ff */
/*0180*/ IABS R6, R5 ; /* 0x0000000500067213 */
/* 0x000fc60000000000 */
/*0190*/ IMAD.HI.U32 R3, R3, R9, R2 ; /* 0x0000000903037227 */
/* 0x000fe200078e0002 */
/*01a0*/ LOP3.LUT R2, R5, c[0x0][0x180], RZ, 0x3c, !PT ; /* 0x0000600005027a12 */
/* 0x000fc800078e3cff */
/*01b0*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f26270 */
/*01c0*/ IMAD.HI.U32 R3, R3, R6, RZ ; /* 0x0000000603037227 */
/* 0x000fca00078e00ff */
/*01d0*/ IADD3 R4, -R3, RZ, RZ ; /* 0x000000ff03047210 */
/* 0x000fca0007ffe1ff */
/*01e0*/ IMAD R4, R7, R4, R6 ; /* 0x0000000407047224 */
/* 0x000fca00078e0206 */
/*01f0*/ ISETP.GT.U32.AND P2, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x000fda0003f44070 */
/*0200*/ @!P2 IMAD.IADD R4, R4, 0x1, -R7 ; /* 0x000000010404a824 */
/* 0x000fe200078e0a07 */
/*0210*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*0220*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fe40003f45270 */
/*0230*/ ISETP.GE.U32.AND P0, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x000fda0003f06070 */
/*0240*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fc80007ffe0ff */
/*0250*/ MOV R4, R3 ; /* 0x0000000300047202 */
/* 0x000fca0000000f00 */
/*0260*/ @!P1 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff049224 */
/* 0x000fe200078e0a04 */
/*0270*/ @!P2 LOP3.LUT R4, RZ, c[0x0][0x180], RZ, 0x33, !PT ; /* 0x00006000ff04aa12 */
/* 0x000fc800078e33ff */
/*0280*/ IADD3 R2, -R4, RZ, RZ ; /* 0x000000ff04027210 */
/* 0x000fca0007ffe1ff */
/*0290*/ IMAD R17, R2, c[0x0][0x180], R5 ; /* 0x0000600002117a24 */
/* 0x000fca00078e0205 */
/*02a0*/ ISETP.GT.AND P0, PT, R17, R4, PT ; /* 0x000000041100720c */
/* 0x000fda0003f04270 */
/*02b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*02c0*/ S2R R3, SR_LANEID ; /* 0x0000000000037919 */
/* 0x000e220000000000 */
/*02d0*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe200038e0100 */
/*02e0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fe200078e00ff */
/*02f0*/ FLO.U32 R8, UR6 ; /* 0x0000000600087d00 */
/* 0x000e3000080e0000 */
/*0300*/ POPC R11, UR6 ; /* 0x00000006000b7d09 */
/* 0x000e620008000000 */
/*0310*/ ISETP.EQ.U32.AND P0, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x001fc40003f02070 */
/*0320*/ MOV R3, c[0x0][0x17c] ; /* 0x00005f0000037a02 */
/* 0x000fd60000000f00 */
/*0330*/ @P0 ATOMG.E.ADD.STRONG.GPU PT, R15, [R2.64], R11 ; /* 0x0000000b020f09a8 */
/* 0x002ea200081ee1c4 */
/*0340*/ IMAD R5, R4, 0x3, RZ ; /* 0x0000000304057824 */
/* 0x000fc800078e02ff */
/*0350*/ IMAD.WIDE R4, R5, R0, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0200 */
/*0360*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ee8000c1e1900 */
/*0370*/ S2R R7, SR_LTMASK ; /* 0x0000000000077919 */
/* 0x000e240000003900 */
/*0380*/ LOP3.LUT R10, R7, UR6, RZ, 0xc0, !PT ; /* 0x00000006070a7c12 */
/* 0x001fc8000f8ec0ff */
/*0390*/ POPC R7, R10 ; /* 0x0000000a00077309 */
/* 0x000e220000000000 */
/*03a0*/ SHFL.IDX PT, R6, R15, R8, 0x1f ; /* 0x00001f080f067589 */
/* 0x004e2400000e0000 */
/*03b0*/ IMAD.IADD R6, R6, 0x1, R7 ; /* 0x0000000106067824 */
/* 0x001fc800078e0207 */
/*03c0*/ IMAD R7, R6, 0x6, RZ ; /* 0x0000000606077824 */
/* 0x000fc800078e02ff */
/*03d0*/ IMAD.WIDE R6, R7, R0, c[0x0][0x170] ; /* 0x00005c0007067625 */
/* 0x000fca00078e0200 */
/*03e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0081e8000c101904 */
/*03f0*/ LDG.E R11, [R4.64+0x4] ; /* 0x00000404040b7981 */
/* 0x000ea2000c1e1900 */
/*0400*/ IMAD R3, R17, 0x3, RZ ; /* 0x0000000311037824 */
/* 0x000fc600078e02ff */
/*0410*/ STG.E [R6.64+0x4], R11 ; /* 0x0000040b06007986 */
/* 0x004fe8000c101904 */
/*0420*/ LDG.E R13, [R4.64+0x8] ; /* 0x00000804040d7981 */
/* 0x000ea2000c1e1900 */
/*0430*/ IMAD.WIDE R2, R3, R0, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fc600078e0200 */
/*0440*/ STG.E [R6.64+0x8], R13 ; /* 0x0000080d06007986 */
/* 0x004fe8000c101904 */
/*0450*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ea8000c1e1900 */
/*0460*/ STG.E [R6.64+0xc], R15 ; /* 0x00000c0f06007986 */
/* 0x004fe8000c101904 */
/*0470*/ LDG.E R17, [R2.64+0x4] ; /* 0x0000040402117981 */
/* 0x000ea8000c1e1900 */
/*0480*/ STG.E [R6.64+0x10], R17 ; /* 0x0000101106007986 */
/* 0x004fe8000c101904 */
/*0490*/ LDG.E R9, [R2.64+0x8] ; /* 0x0000080402097981 */
/* 0x001ea8000c1e1900 */
/*04a0*/ STG.E [R6.64+0x14], R9 ; /* 0x0000140906007986 */
/* 0x004fe2000c101904 */
/*04b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04c0*/ BRA 0x4c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i
.globl _Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i
.p2align 8
.type _Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i,@function
_Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x28
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s2, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_and_b32 s4, s4, 0xffff
s_add_i32 s3, s3, s14
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s3, s4, v[0:1]
s_mul_i32 s3, s2, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_6
s_load_b64 s[4:5], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 1, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_6
s_ashr_i32 s3, s2, 31
v_ashrrev_i32_e32 v3, 31, v1
s_add_i32 s4, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s4, s4, s3
v_add_nc_u32_e32 v4, v1, v3
v_cvt_f32_u32_e32 v0, s4
s_sub_i32 s5, 0, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v4, v3
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v3, s3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v4, v0
v_mul_lo_u32 v2, v0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v0
v_subrev_nc_u32_e32 v5, s4, v2
v_cmp_le_u32_e32 vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 1, v0
v_cmp_le_u32_e32 vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v0, v3
v_mul_lo_u32 v0, v2, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v1, v0
v_cmp_gt_i32_e32 vcc_lo, v0, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_6
s_mov_b32 s3, exec_lo
s_mov_b32 s2, exec_lo
v_mbcnt_lo_u32_b32 v1, s3, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v1
s_cbranch_execz .LBB0_5
s_load_b64 s[4:5], s[0:1], 0x18
s_bcnt1_i32_b32 s3, s3
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, s3
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v3, v3, v4, s[4:5] glc
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s2
s_load_b128 s[0:3], s[0:1], 0x8
v_lshl_add_u32 v4, v2, 1, v2
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s4, v3
v_lshl_add_u32 v0, v0, 1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v5, 31, v4
v_add_nc_u32_e32 v1, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_mul_lo_u32 v1, v1, 6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
v_lshlrev_b64 v[2:3], 2, v[1:2]
global_load_b32 v6, v[4:5], off
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v6, off
global_load_b32 v8, v[4:5], off offset:4
v_or_b32_e32 v6, 1, v1
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[6:7], v8, off
global_load_b32 v4, v[4:5], off offset:8
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v4, off offset:8
global_load_b32 v4, v[0:1], off
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v4, off offset:12
global_load_b32 v4, v[0:1], off offset:4
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v4, off offset:16
global_load_b32 v0, v[0:1], off offset:8
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v0, off offset:20
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i, .Lfunc_end0-_Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002ec72_00000000-6_CopyConnectionsCoordinatesKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z60__device_stub__Z32CopyConnectionsCoordinatesKernelPiPfS0_S_iPiPfS0_S_i
.type _Z60__device_stub__Z32CopyConnectionsCoordinatesKernelPiPfS0_S_iPiPfS0_S_i, @function
_Z60__device_stub__Z32CopyConnectionsCoordinatesKernelPiPfS0_S_iPiPfS0_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z60__device_stub__Z32CopyConnectionsCoordinatesKernelPiPfS0_S_iPiPfS0_S_i, .-_Z60__device_stub__Z32CopyConnectionsCoordinatesKernelPiPfS0_S_iPiPfS0_S_i
.globl _Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i
.type _Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i, @function
_Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z60__device_stub__Z32CopyConnectionsCoordinatesKernelPiPfS0_S_iPiPfS0_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i, .-_Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "CopyConnectionsCoordinatesKernel.hip"
.globl _Z47__device_stub__CopyConnectionsCoordinatesKernelPiPfS0_S_i # -- Begin function _Z47__device_stub__CopyConnectionsCoordinatesKernelPiPfS0_S_i
.p2align 4, 0x90
.type _Z47__device_stub__CopyConnectionsCoordinatesKernelPiPfS0_S_i,@function
_Z47__device_stub__CopyConnectionsCoordinatesKernelPiPfS0_S_i: # @_Z47__device_stub__CopyConnectionsCoordinatesKernelPiPfS0_S_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z47__device_stub__CopyConnectionsCoordinatesKernelPiPfS0_S_i, .Lfunc_end0-_Z47__device_stub__CopyConnectionsCoordinatesKernelPiPfS0_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i,@object # @_Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i
.section .rodata,"a",@progbits
.globl _Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i
.p2align 3, 0x0
_Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i:
.quad _Z47__device_stub__CopyConnectionsCoordinatesKernelPiPfS0_S_i
.size _Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i"
.size .L__unnamed_1, 47
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z47__device_stub__CopyConnectionsCoordinatesKernelPiPfS0_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z32CopyConnectionsCoordinatesKernelPiPfS0_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,float var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14) {
comp = (-1.4149E17f / -1.2899E-8f);
for (int i=0; i < var_1; ++i) {
float tmp_1 = (var_2 - (var_3 / -1.9107E-14f + +0.0f - (var_4 + +1.8370E-25f)));
comp += tmp_1 - logf(log10f((-1.7442E36f / var_5 * (var_6 * var_7))));
comp += (-1.5960E-43f - (-1.7254E35f * -1.0943E35f + var_8));
}
if (comp <= (+1.4929E10f + var_9)) {
float tmp_2 = +1.3666E-36f;
float tmp_3 = +1.7855E-11f;
comp += tmp_3 - tmp_2 * var_10 / floorf((var_11 / sqrtf(var_12 * +1.2344E34f / var_13 - var_14)));
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
float tmp_3 = atof(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15);
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_00074fc3_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z39__device_stub__Z7computefiffffffffffffffifffffffffffff
.type _Z39__device_stub__Z7computefiffffffffffffffifffffffffffff, @function
_Z39__device_stub__Z7computefiffffffffffffffifffffffffffff:
.LFB2083:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movss %xmm1, 36(%rsp)
movss %xmm2, 32(%rsp)
movss %xmm3, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 20(%rsp)
movss %xmm6, 16(%rsp)
movss %xmm7, 12(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 256(%rsp), %rax
movq %rax, 184(%rsp)
leaq 264(%rsp), %rax
movq %rax, 192(%rsp)
leaq 272(%rsp), %rax
movq %rax, 200(%rsp)
leaq 280(%rsp), %rax
movq %rax, 208(%rsp)
leaq 288(%rsp), %rax
movq %rax, 216(%rsp)
leaq 296(%rsp), %rax
movq %rax, 224(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 264
pushq 56(%rsp)
.cfi_def_cfa_offset 272
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7computefifffffffffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z39__device_stub__Z7computefiffffffffffffffifffffffffffff, .-_Z39__device_stub__Z7computefiffffffffffffffifffffffffffff
.globl _Z7computefifffffffffffff
.type _Z7computefifffffffffffff, @function
_Z7computefifffffffffffff:
.LFB2084:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movss 104(%rsp), %xmm8
movss %xmm8, 40(%rsp)
movss 96(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 88(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 80(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 72(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 64(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z39__device_stub__Z7computefiffffffffffffffifffffffffffff
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefifffffffffffff, .-_Z7computefifffffffffffff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $152, %rsp
.cfi_def_cfa_offset 176
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 104(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 24(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 96(%rsp)
movq 32(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movq 120(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, (%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 132(%rsp), %rdx
movl $1, %ecx
movq 120(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 104(%rsp), %xmm0
pxor %xmm1, %xmm1
cvtsd2ss (%rsp), %xmm1
leaq -48(%rsp), %rsp
.cfi_def_cfa_offset 224
movss %xmm1, 40(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 56(%rsp), %xmm1
movss %xmm1, 32(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 64(%rsp), %xmm1
movss %xmm1, 24(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 72(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 80(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 88(%rsp), %xmm1
movss %xmm1, (%rsp)
pxor %xmm7, %xmm7
cvtsd2ss 96(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 104(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtsd2ss 112(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 120(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 128(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 136(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 144(%rsp), %xmm1
movl %ebp, %edi
call _Z39__device_stub__Z7computefiffffffffffffffifffffffffffff
addq $48, %rsp
.cfi_def_cfa_offset 176
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7computefifffffffffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefifffffffffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,float var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14) {
comp = (-1.4149E17f / -1.2899E-8f);
for (int i=0; i < var_1; ++i) {
float tmp_1 = (var_2 - (var_3 / -1.9107E-14f + +0.0f - (var_4 + +1.8370E-25f)));
comp += tmp_1 - logf(log10f((-1.7442E36f / var_5 * (var_6 * var_7))));
comp += (-1.5960E-43f - (-1.7254E35f * -1.0943E35f + var_8));
}
if (comp <= (+1.4929E10f + var_9)) {
float tmp_2 = +1.3666E-36f;
float tmp_3 = +1.7855E-11f;
comp += tmp_3 - tmp_2 * var_10 / floorf((var_11 / sqrtf(var_12 * +1.2344E34f / var_13 - var_14)));
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
float tmp_3 = atof(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15);
cudaDeviceSynchronize();
return 0;
} | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,float var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14) {
comp = (-1.4149E17f / -1.2899E-8f);
for (int i=0; i < var_1; ++i) {
float tmp_1 = (var_2 - (var_3 / -1.9107E-14f + +0.0f - (var_4 + +1.8370E-25f)));
comp += tmp_1 - logf(log10f((-1.7442E36f / var_5 * (var_6 * var_7))));
comp += (-1.5960E-43f - (-1.7254E35f * -1.0943E35f + var_8));
}
if (comp <= (+1.4929E10f + var_9)) {
float tmp_2 = +1.3666E-36f;
float tmp_3 = +1.7855E-11f;
comp += tmp_3 - tmp_2 * var_10 / floorf((var_11 / sqrtf(var_12 * +1.2344E34f / var_13 - var_14)));
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
float tmp_3 = atof(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15);
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,float var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14) {
comp = (-1.4149E17f / -1.2899E-8f);
for (int i=0; i < var_1; ++i) {
float tmp_1 = (var_2 - (var_3 / -1.9107E-14f + +0.0f - (var_4 + +1.8370E-25f)));
comp += tmp_1 - logf(log10f((-1.7442E36f / var_5 * (var_6 * var_7))));
comp += (-1.5960E-43f - (-1.7254E35f * -1.0943E35f + var_8));
}
if (comp <= (+1.4929E10f + var_9)) {
float tmp_2 = +1.3666E-36f;
float tmp_3 = +1.7855E-11f;
comp += tmp_3 - tmp_2 * var_10 / floorf((var_11 / sqrtf(var_12 * +1.2344E34f / var_13 - var_14)));
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
float tmp_3 = atof(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15);
hipDeviceSynchronize();
return 0;
} | .text
.file "test.hip"
.globl _Z22__device_stub__computefifffffffffffff # -- Begin function _Z22__device_stub__computefifffffffffffff
.p2align 4, 0x90
.type _Z22__device_stub__computefifffffffffffff,@function
_Z22__device_stub__computefifffffffffffff: # @_Z22__device_stub__computefifffffffffffff
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movss %xmm1, 36(%rsp)
movss %xmm2, 32(%rsp)
movss %xmm3, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 20(%rsp)
movss %xmm6, 16(%rsp)
movss %xmm7, 12(%rsp)
leaq 44(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rax
movq %rax, 104(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 224(%rsp), %rax
movq %rax, 168(%rsp)
leaq 232(%rsp), %rax
movq %rax, 176(%rsp)
leaq 240(%rsp), %rax
movq %rax, 184(%rsp)
leaq 248(%rsp), %rax
movq %rax, 192(%rsp)
leaq 256(%rsp), %rax
movq %rax, 200(%rsp)
leaq 264(%rsp), %rax
movq %rax, 208(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7computefifffffffffffff, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size _Z22__device_stub__computefifffffffffffff, .Lfunc_end0-_Z22__device_stub__computefifffffffffffff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $344, %rsp # imm = 0x158
.cfi_def_cfa_offset 368
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 168(%rsp) # 8-byte Spill
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 24(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 160(%rsp) # 8-byte Spill
movq 32(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 152(%rsp) # 8-byte Spill
movq 40(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 144(%rsp) # 8-byte Spill
movq 48(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 136(%rsp) # 8-byte Spill
movq 56(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 128(%rsp) # 8-byte Spill
movq 64(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 120(%rsp) # 8-byte Spill
movq 72(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 112(%rsp) # 8-byte Spill
movq 80(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 104(%rsp) # 8-byte Spill
movq 88(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 96(%rsp) # 8-byte Spill
movq 96(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 88(%rsp) # 8-byte Spill
movq 104(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 80(%rsp) # 8-byte Spill
movq 112(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 72(%rsp) # 8-byte Spill
movq 120(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 64(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movsd 64(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movsd 72(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
cvtsd2ss %xmm1, %xmm1
movsd 80(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
cvtsd2ss %xmm2, %xmm2
movsd 88(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
cvtsd2ss %xmm3, %xmm3
movsd 96(%rsp), %xmm4 # 8-byte Reload
# xmm4 = mem[0],zero
cvtsd2ss %xmm4, %xmm4
movsd 104(%rsp), %xmm5 # 8-byte Reload
# xmm5 = mem[0],zero
cvtsd2ss %xmm5, %xmm5
movsd 112(%rsp), %xmm6 # 8-byte Reload
# xmm6 = mem[0],zero
cvtsd2ss %xmm6, %xmm6
movsd 120(%rsp), %xmm7 # 8-byte Reload
# xmm7 = mem[0],zero
cvtsd2ss %xmm7, %xmm7
movsd 128(%rsp), %xmm8 # 8-byte Reload
# xmm8 = mem[0],zero
cvtsd2ss %xmm8, %xmm8
movsd 136(%rsp), %xmm9 # 8-byte Reload
# xmm9 = mem[0],zero
cvtsd2ss %xmm9, %xmm9
movsd 144(%rsp), %xmm10 # 8-byte Reload
# xmm10 = mem[0],zero
cvtsd2ss %xmm10, %xmm10
movsd 152(%rsp), %xmm11 # 8-byte Reload
# xmm11 = mem[0],zero
cvtsd2ss %xmm11, %xmm11
movsd 160(%rsp), %xmm12 # 8-byte Reload
# xmm12 = mem[0],zero
cvtsd2ss %xmm12, %xmm12
movsd 168(%rsp), %xmm13 # 8-byte Reload
# xmm13 = mem[0],zero
cvtsd2ss %xmm13, %xmm13
movss %xmm13, 60(%rsp)
movl %ebx, 56(%rsp)
movss %xmm12, 52(%rsp)
movss %xmm11, 48(%rsp)
movss %xmm10, 44(%rsp)
movss %xmm9, 40(%rsp)
movss %xmm8, 36(%rsp)
movss %xmm7, 32(%rsp)
movss %xmm6, 28(%rsp)
movss %xmm5, 24(%rsp)
movss %xmm4, 20(%rsp)
movss %xmm3, 16(%rsp)
movss %xmm2, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm0, 4(%rsp)
leaq 60(%rsp), %rax
movq %rax, 224(%rsp)
leaq 56(%rsp), %rax
movq %rax, 232(%rsp)
leaq 52(%rsp), %rax
movq %rax, 240(%rsp)
leaq 48(%rsp), %rax
movq %rax, 248(%rsp)
leaq 44(%rsp), %rax
movq %rax, 256(%rsp)
leaq 40(%rsp), %rax
movq %rax, 264(%rsp)
leaq 36(%rsp), %rax
movq %rax, 272(%rsp)
leaq 32(%rsp), %rax
movq %rax, 280(%rsp)
leaq 28(%rsp), %rax
movq %rax, 288(%rsp)
leaq 24(%rsp), %rax
movq %rax, 296(%rsp)
leaq 20(%rsp), %rax
movq %rax, 304(%rsp)
leaq 16(%rsp), %rax
movq %rax, 312(%rsp)
leaq 12(%rsp), %rax
movq %rax, 320(%rsp)
leaq 8(%rsp), %rax
movq %rax, 328(%rsp)
leaq 4(%rsp), %rax
movq %rax, 336(%rsp)
leaq 208(%rsp), %rdi
leaq 192(%rsp), %rsi
leaq 184(%rsp), %rdx
leaq 176(%rsp), %rcx
callq __hipPopCallConfiguration
movq 208(%rsp), %rsi
movl 216(%rsp), %edx
movq 192(%rsp), %rcx
movl 200(%rsp), %r8d
leaq 224(%rsp), %r9
movl $_Z7computefifffffffffffff, %edi
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
pushq 192(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $344, %rsp # imm = 0x158
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefifffffffffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefifffffffffffff,@object # @_Z7computefifffffffffffff
.section .rodata,"a",@progbits
.globl _Z7computefifffffffffffff
.p2align 3, 0x0
_Z7computefifffffffffffff:
.quad _Z22__device_stub__computefifffffffffffff
.size _Z7computefifffffffffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefifffffffffffff"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefifffffffffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefifffffffffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00074fc3_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z39__device_stub__Z7computefiffffffffffffffifffffffffffff
.type _Z39__device_stub__Z7computefiffffffffffffffifffffffffffff, @function
_Z39__device_stub__Z7computefiffffffffffffffifffffffffffff:
.LFB2083:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movss %xmm1, 36(%rsp)
movss %xmm2, 32(%rsp)
movss %xmm3, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 20(%rsp)
movss %xmm6, 16(%rsp)
movss %xmm7, 12(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 256(%rsp), %rax
movq %rax, 184(%rsp)
leaq 264(%rsp), %rax
movq %rax, 192(%rsp)
leaq 272(%rsp), %rax
movq %rax, 200(%rsp)
leaq 280(%rsp), %rax
movq %rax, 208(%rsp)
leaq 288(%rsp), %rax
movq %rax, 216(%rsp)
leaq 296(%rsp), %rax
movq %rax, 224(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 264
pushq 56(%rsp)
.cfi_def_cfa_offset 272
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7computefifffffffffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z39__device_stub__Z7computefiffffffffffffffifffffffffffff, .-_Z39__device_stub__Z7computefiffffffffffffffifffffffffffff
.globl _Z7computefifffffffffffff
.type _Z7computefifffffffffffff, @function
_Z7computefifffffffffffff:
.LFB2084:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movss 104(%rsp), %xmm8
movss %xmm8, 40(%rsp)
movss 96(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 88(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 80(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 72(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 64(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z39__device_stub__Z7computefiffffffffffffffifffffffffffff
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefifffffffffffff, .-_Z7computefifffffffffffff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $152, %rsp
.cfi_def_cfa_offset 176
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 104(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 24(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 96(%rsp)
movq 32(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movq 120(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, (%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 132(%rsp), %rdx
movl $1, %ecx
movq 120(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 104(%rsp), %xmm0
pxor %xmm1, %xmm1
cvtsd2ss (%rsp), %xmm1
leaq -48(%rsp), %rsp
.cfi_def_cfa_offset 224
movss %xmm1, 40(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 56(%rsp), %xmm1
movss %xmm1, 32(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 64(%rsp), %xmm1
movss %xmm1, 24(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 72(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 80(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 88(%rsp), %xmm1
movss %xmm1, (%rsp)
pxor %xmm7, %xmm7
cvtsd2ss 96(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 104(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtsd2ss 112(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 120(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 128(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 136(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 144(%rsp), %xmm1
movl %ebp, %edi
call _Z39__device_stub__Z7computefiffffffffffffffifffffffffffff
addq $48, %rsp
.cfi_def_cfa_offset 176
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7computefifffffffffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefifffffffffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl _Z22__device_stub__computefifffffffffffff # -- Begin function _Z22__device_stub__computefifffffffffffff
.p2align 4, 0x90
.type _Z22__device_stub__computefifffffffffffff,@function
_Z22__device_stub__computefifffffffffffff: # @_Z22__device_stub__computefifffffffffffff
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movss %xmm1, 36(%rsp)
movss %xmm2, 32(%rsp)
movss %xmm3, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 20(%rsp)
movss %xmm6, 16(%rsp)
movss %xmm7, 12(%rsp)
leaq 44(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rax
movq %rax, 104(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 224(%rsp), %rax
movq %rax, 168(%rsp)
leaq 232(%rsp), %rax
movq %rax, 176(%rsp)
leaq 240(%rsp), %rax
movq %rax, 184(%rsp)
leaq 248(%rsp), %rax
movq %rax, 192(%rsp)
leaq 256(%rsp), %rax
movq %rax, 200(%rsp)
leaq 264(%rsp), %rax
movq %rax, 208(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7computefifffffffffffff, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size _Z22__device_stub__computefifffffffffffff, .Lfunc_end0-_Z22__device_stub__computefifffffffffffff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $344, %rsp # imm = 0x158
.cfi_def_cfa_offset 368
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 168(%rsp) # 8-byte Spill
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 24(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 160(%rsp) # 8-byte Spill
movq 32(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 152(%rsp) # 8-byte Spill
movq 40(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 144(%rsp) # 8-byte Spill
movq 48(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 136(%rsp) # 8-byte Spill
movq 56(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 128(%rsp) # 8-byte Spill
movq 64(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 120(%rsp) # 8-byte Spill
movq 72(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 112(%rsp) # 8-byte Spill
movq 80(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 104(%rsp) # 8-byte Spill
movq 88(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 96(%rsp) # 8-byte Spill
movq 96(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 88(%rsp) # 8-byte Spill
movq 104(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 80(%rsp) # 8-byte Spill
movq 112(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 72(%rsp) # 8-byte Spill
movq 120(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 64(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movsd 64(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movsd 72(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
cvtsd2ss %xmm1, %xmm1
movsd 80(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
cvtsd2ss %xmm2, %xmm2
movsd 88(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
cvtsd2ss %xmm3, %xmm3
movsd 96(%rsp), %xmm4 # 8-byte Reload
# xmm4 = mem[0],zero
cvtsd2ss %xmm4, %xmm4
movsd 104(%rsp), %xmm5 # 8-byte Reload
# xmm5 = mem[0],zero
cvtsd2ss %xmm5, %xmm5
movsd 112(%rsp), %xmm6 # 8-byte Reload
# xmm6 = mem[0],zero
cvtsd2ss %xmm6, %xmm6
movsd 120(%rsp), %xmm7 # 8-byte Reload
# xmm7 = mem[0],zero
cvtsd2ss %xmm7, %xmm7
movsd 128(%rsp), %xmm8 # 8-byte Reload
# xmm8 = mem[0],zero
cvtsd2ss %xmm8, %xmm8
movsd 136(%rsp), %xmm9 # 8-byte Reload
# xmm9 = mem[0],zero
cvtsd2ss %xmm9, %xmm9
movsd 144(%rsp), %xmm10 # 8-byte Reload
# xmm10 = mem[0],zero
cvtsd2ss %xmm10, %xmm10
movsd 152(%rsp), %xmm11 # 8-byte Reload
# xmm11 = mem[0],zero
cvtsd2ss %xmm11, %xmm11
movsd 160(%rsp), %xmm12 # 8-byte Reload
# xmm12 = mem[0],zero
cvtsd2ss %xmm12, %xmm12
movsd 168(%rsp), %xmm13 # 8-byte Reload
# xmm13 = mem[0],zero
cvtsd2ss %xmm13, %xmm13
movss %xmm13, 60(%rsp)
movl %ebx, 56(%rsp)
movss %xmm12, 52(%rsp)
movss %xmm11, 48(%rsp)
movss %xmm10, 44(%rsp)
movss %xmm9, 40(%rsp)
movss %xmm8, 36(%rsp)
movss %xmm7, 32(%rsp)
movss %xmm6, 28(%rsp)
movss %xmm5, 24(%rsp)
movss %xmm4, 20(%rsp)
movss %xmm3, 16(%rsp)
movss %xmm2, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm0, 4(%rsp)
leaq 60(%rsp), %rax
movq %rax, 224(%rsp)
leaq 56(%rsp), %rax
movq %rax, 232(%rsp)
leaq 52(%rsp), %rax
movq %rax, 240(%rsp)
leaq 48(%rsp), %rax
movq %rax, 248(%rsp)
leaq 44(%rsp), %rax
movq %rax, 256(%rsp)
leaq 40(%rsp), %rax
movq %rax, 264(%rsp)
leaq 36(%rsp), %rax
movq %rax, 272(%rsp)
leaq 32(%rsp), %rax
movq %rax, 280(%rsp)
leaq 28(%rsp), %rax
movq %rax, 288(%rsp)
leaq 24(%rsp), %rax
movq %rax, 296(%rsp)
leaq 20(%rsp), %rax
movq %rax, 304(%rsp)
leaq 16(%rsp), %rax
movq %rax, 312(%rsp)
leaq 12(%rsp), %rax
movq %rax, 320(%rsp)
leaq 8(%rsp), %rax
movq %rax, 328(%rsp)
leaq 4(%rsp), %rax
movq %rax, 336(%rsp)
leaq 208(%rsp), %rdi
leaq 192(%rsp), %rsi
leaq 184(%rsp), %rdx
leaq 176(%rsp), %rcx
callq __hipPopCallConfiguration
movq 208(%rsp), %rsi
movl 216(%rsp), %edx
movq 192(%rsp), %rcx
movl 200(%rsp), %r8d
leaq 224(%rsp), %r9
movl $_Z7computefifffffffffffff, %edi
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
pushq 192(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $344, %rsp # imm = 0x158
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefifffffffffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefifffffffffffff,@object # @_Z7computefifffffffffffff
.section .rodata,"a",@progbits
.globl _Z7computefifffffffffffff
.p2align 3, 0x0
_Z7computefifffffffffffff:
.quad _Z22__device_stub__computefifffffffffffff
.size _Z7computefifffffffffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefifffffffffffff"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefifffffffffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefifffffffffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda_runtime.h>
__global__ void add (int a, int b, int *c) {
*c = a + b;
printf("into add");
}
int main(int argv, char** argc ) {
printf( "Hello, World!\n" );
int c;
int *device_c;
cudaMalloc((void**)&device_c, sizeof(int));
add<<<1, 1>>>(2, 7, device_c);
cudaMemcpy(&c, device_c, sizeof(int),
cudaMemcpyDeviceToHost);
printf("2 + 7 = %d\n", c);
cudaFree(device_c);
return 0;
} | code for sm_80
Function : _Z3addiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff007624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R8, 0x0 ; /* 0x0000000000087802 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe200078e00ff */
/*0060*/ IADD3 R0, R0, c[0x0][0x160], RZ ; /* 0x0000580000007a10 */
/* 0x000fe20007ffe0ff */
/*0070*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0080*/ LDC.64 R8, c[0x4][R8] ; /* 0x0100000008087b82 */
/* 0x000e220000000a00 */
/*0090*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*00a0*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*00b0*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x0003ea000c101904 */
/*00c0*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x002fe40000000000 */
/*00d0*/ MOV R11, 0x140 ; /* 0x00000140000b7802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R20, 0xc0 ; /* 0x000000c000147802 */
/* 0x000fc40000000f00 */
/*00f0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0110*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*0120*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0130*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x001fea0003c00000 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime.h>
__global__ void add (int a, int b, int *c) {
*c = a + b;
printf("into add");
}
int main(int argv, char** argc ) {
printf( "Hello, World!\n" );
int c;
int *device_c;
cudaMalloc((void**)&device_c, sizeof(int));
add<<<1, 1>>>(2, 7, device_c);
cudaMemcpy(&c, device_c, sizeof(int),
cudaMemcpyDeviceToHost);
printf("2 + 7 = %d\n", c);
cudaFree(device_c);
return 0;
} | .file "tmpxft_000eb82c_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3addiiPiiiPi
.type _Z24__device_stub__Z3addiiPiiiPi, @function
_Z24__device_stub__Z3addiiPiiiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z3addiiPiiiPi, .-_Z24__device_stub__Z3addiiPiiiPi
.globl _Z3addiiPi
.type _Z3addiiPi, @function
_Z3addiiPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3addiiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addiiPi, .-_Z3addiiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello, World!\n"
.LC1:
.string "2 + 7 = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
movl 28(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rdx
movl $7, %esi
movl $2, %edi
call _Z24__device_stub__Z3addiiPiiiPi
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z3addiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime.h>
__global__ void add (int a, int b, int *c) {
*c = a + b;
printf("into add");
}
int main(int argv, char** argc ) {
printf( "Hello, World!\n" );
int c;
int *device_c;
cudaMalloc((void**)&device_c, sizeof(int));
add<<<1, 1>>>(2, 7, device_c);
cudaMemcpy(&c, device_c, sizeof(int),
cudaMemcpyDeviceToHost);
printf("2 + 7 = %d\n", c);
cudaFree(device_c);
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void add (int a, int b, int *c) {
*c = a + b;
printf("into add");
}
int main(int argv, char** argc ) {
printf( "Hello, World!\n" );
int c;
int *device_c;
hipMalloc((void**)&device_c, sizeof(int));
add<<<1, 1>>>(2, 7, device_c);
hipMemcpy(&c, device_c, sizeof(int),
hipMemcpyDeviceToHost);
printf("2 + 7 = %d\n", c);
hipFree(device_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void add (int a, int b, int *c) {
*c = a + b;
printf("into add");
}
int main(int argv, char** argc ) {
printf( "Hello, World!\n" );
int c;
int *device_c;
hipMalloc((void**)&device_c, sizeof(int));
add<<<1, 1>>>(2, 7, device_c);
hipMemcpy(&c, device_c, sizeof(int),
hipMemcpyDeviceToHost);
printf("2 + 7 = %d\n", c);
hipFree(device_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiiPi
.globl _Z3addiiPi
.p2align 8
.type _Z3addiiPi,@function
_Z3addiiPi:
s_load_b128 s[4:7], s[0:1], 0x0
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v4, v20
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s5, s4
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[6:7]
s_load_b64 s[2:3], s[0:1], 0x60
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
s_waitcnt lgkmcnt(0)
global_load_b64 v[7:8], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_mov_b32 s4, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v2, v2, v8
v_and_b32_e32 v1, v1, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v2, 24
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[5:6], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[5:6], v0, v[5:8], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[5:6], v[7:8]
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v1, 0
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[2:3], v1, s[2:3] offset:40
global_load_b64 v[9:10], v1, s[2:3]
v_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v7, v5
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v2, v2, v7
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[5:6], null, v2, 24, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v2, v6 :: v_dual_and_b32 v3, v3, v8
v_mad_u64_u32 v[9:10], null, v3, 24, v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v6, v9
global_load_b64 v[5:6], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[5:6], v1, v[5:8], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[5:6], v[7:8]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[7:8], v0, s[2:3] offset:40
global_load_b128 v[0:3], v0, s[2:3]
v_readfirstlane_b32 s4, v5
v_readfirstlane_b32 s5, v6
s_mov_b32 s8, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v7
v_readfirstlane_b32 s7, v8
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v5, s8 :: v_dual_mov_b32 v6, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v7, 2 :: v_dual_mov_b32 v8, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v9, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v10, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[9:10], v[5:8], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v8, 33
s_lshl_b64 s[8:9], s[6:7], 12
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 6, v[4:5]
s_mov_b32 s8, 0
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_mov_b32_e32 v9, 0
v_add_co_u32 v6, vcc_lo, v2, v6
v_dual_mov_b32 v15, s11 :: v_dual_mov_b32 v14, s10
v_add_co_ci_u32_e32 v7, vcc_lo, v3, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_dual_mov_b32 v10, v9 :: v_dual_mov_b32 v13, s9
v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v12, s8
s_clause 0x3
global_store_b128 v[6:7], v[8:11], off
global_store_b128 v[6:7], v[12:15], off offset:16
global_store_b128 v[6:7], v[12:15], off offset:32
global_store_b128 v[6:7], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
s_clause 0x1
global_load_b64 v[12:13], v5, s[2:3] offset:32 glc
global_load_b64 v[2:3], v5, s[2:3] offset:40
v_dual_mov_b32 v10, s4 :: v_dual_mov_b32 v11, s5
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[12:13], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v5, v[10:13], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[12:13]
s_cbranch_execz .LBB0_12
v_mov_b32_e32 v10, 0
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 9
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiiPi, .Lfunc_end0-_Z3addiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "into add"
.size .str, 9
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 96
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiiPi
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z3addiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void add (int a, int b, int *c) {
*c = a + b;
printf("into add");
}
int main(int argv, char** argc ) {
printf( "Hello, World!\n" );
int c;
int *device_c;
hipMalloc((void**)&device_c, sizeof(int));
add<<<1, 1>>>(2, 7, device_c);
hipMemcpy(&c, device_c, sizeof(int),
hipMemcpyDeviceToHost);
printf("2 + 7 = %d\n", c);
hipFree(device_c);
return 0;
} | .text
.file "main.hip"
.globl _Z18__device_stub__addiiPi # -- Begin function _Z18__device_stub__addiiPi
.p2align 4, 0x90
.type _Z18__device_stub__addiiPi,@function
_Z18__device_stub__addiiPi: # @_Z18__device_stub__addiiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3addiiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__addiiPi, .Lfunc_end0-_Z18__device_stub__addiiPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl $.Lstr, %edi
callq puts@PLT
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq (%rsp), %rax
movl $2, 12(%rsp)
movl $7, 8(%rsp)
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 8(%rsp), %rax
movq %rax, 24(%rsp)
leaq 96(%rsp), %rax
movq %rax, 32(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z3addiiPi, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
leaq 16(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 16(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiiPi,@object # @_Z3addiiPi
.section .rodata,"a",@progbits
.globl _Z3addiiPi
.p2align 3, 0x0
_Z3addiiPi:
.quad _Z18__device_stub__addiiPi
.size _Z3addiiPi, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "2 + 7 = %d\n"
.size .L.str.1, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addiiPi"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello, World!"
.size .Lstr, 14
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff007624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R8, 0x0 ; /* 0x0000000000087802 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe200078e00ff */
/*0060*/ IADD3 R0, R0, c[0x0][0x160], RZ ; /* 0x0000580000007a10 */
/* 0x000fe20007ffe0ff */
/*0070*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0080*/ LDC.64 R8, c[0x4][R8] ; /* 0x0100000008087b82 */
/* 0x000e220000000a00 */
/*0090*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*00a0*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*00b0*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x0003ea000c101904 */
/*00c0*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x002fe40000000000 */
/*00d0*/ MOV R11, 0x140 ; /* 0x00000140000b7802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R20, 0xc0 ; /* 0x000000c000147802 */
/* 0x000fc40000000f00 */
/*00f0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0110*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*0120*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0130*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x001fea0003c00000 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiiPi
.globl _Z3addiiPi
.p2align 8
.type _Z3addiiPi,@function
_Z3addiiPi:
s_load_b128 s[4:7], s[0:1], 0x0
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v4, v20
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s5, s4
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[6:7]
s_load_b64 s[2:3], s[0:1], 0x60
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
s_waitcnt lgkmcnt(0)
global_load_b64 v[7:8], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_mov_b32 s4, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v2, v2, v8
v_and_b32_e32 v1, v1, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v2, 24
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[5:6], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[5:6], v0, v[5:8], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[5:6], v[7:8]
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v1, 0
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[2:3], v1, s[2:3] offset:40
global_load_b64 v[9:10], v1, s[2:3]
v_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v7, v5
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v2, v2, v7
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[5:6], null, v2, 24, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v2, v6 :: v_dual_and_b32 v3, v3, v8
v_mad_u64_u32 v[9:10], null, v3, 24, v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v6, v9
global_load_b64 v[5:6], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[5:6], v1, v[5:8], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[5:6], v[7:8]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[7:8], v0, s[2:3] offset:40
global_load_b128 v[0:3], v0, s[2:3]
v_readfirstlane_b32 s4, v5
v_readfirstlane_b32 s5, v6
s_mov_b32 s8, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v7
v_readfirstlane_b32 s7, v8
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v5, s8 :: v_dual_mov_b32 v6, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v7, 2 :: v_dual_mov_b32 v8, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v9, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v10, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[9:10], v[5:8], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v8, 33
s_lshl_b64 s[8:9], s[6:7], 12
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 6, v[4:5]
s_mov_b32 s8, 0
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_mov_b32_e32 v9, 0
v_add_co_u32 v6, vcc_lo, v2, v6
v_dual_mov_b32 v15, s11 :: v_dual_mov_b32 v14, s10
v_add_co_ci_u32_e32 v7, vcc_lo, v3, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_dual_mov_b32 v10, v9 :: v_dual_mov_b32 v13, s9
v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v12, s8
s_clause 0x3
global_store_b128 v[6:7], v[8:11], off
global_store_b128 v[6:7], v[12:15], off offset:16
global_store_b128 v[6:7], v[12:15], off offset:32
global_store_b128 v[6:7], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
s_clause 0x1
global_load_b64 v[12:13], v5, s[2:3] offset:32 glc
global_load_b64 v[2:3], v5, s[2:3] offset:40
v_dual_mov_b32 v10, s4 :: v_dual_mov_b32 v11, s5
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[12:13], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v5, v[10:13], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[12:13]
s_cbranch_execz .LBB0_12
v_mov_b32_e32 v10, 0
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 9
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiiPi, .Lfunc_end0-_Z3addiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "into add"
.size .str, 9
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 96
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiiPi
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z3addiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000eb82c_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3addiiPiiiPi
.type _Z24__device_stub__Z3addiiPiiiPi, @function
_Z24__device_stub__Z3addiiPiiiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z3addiiPiiiPi, .-_Z24__device_stub__Z3addiiPiiiPi
.globl _Z3addiiPi
.type _Z3addiiPi, @function
_Z3addiiPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3addiiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addiiPi, .-_Z3addiiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello, World!\n"
.LC1:
.string "2 + 7 = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
movl 28(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rdx
movl $7, %esi
movl $2, %edi
call _Z24__device_stub__Z3addiiPiiiPi
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z3addiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z18__device_stub__addiiPi # -- Begin function _Z18__device_stub__addiiPi
.p2align 4, 0x90
.type _Z18__device_stub__addiiPi,@function
_Z18__device_stub__addiiPi: # @_Z18__device_stub__addiiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3addiiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__addiiPi, .Lfunc_end0-_Z18__device_stub__addiiPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl $.Lstr, %edi
callq puts@PLT
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq (%rsp), %rax
movl $2, 12(%rsp)
movl $7, 8(%rsp)
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 8(%rsp), %rax
movq %rax, 24(%rsp)
leaq 96(%rsp), %rax
movq %rax, 32(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z3addiiPi, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
leaq 16(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 16(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiiPi,@object # @_Z3addiiPi
.section .rodata,"a",@progbits
.globl _Z3addiiPi
.p2align 3, 0x0
_Z3addiiPi:
.quad _Z18__device_stub__addiiPi
.size _Z3addiiPi, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "2 + 7 = %d\n"
.size .L.str.1, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addiiPi"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello, World!"
.size .Lstr, 14
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "error.h"
#include <cuda.h>
#include <curand_kernel.h>
#include <cassert>
#include <iostream>
#include <string>
namespace
{
const char* curandGetErrorString(const curandStatus_t error)
{
switch (error)
{
case CURAND_STATUS_SUCCESS:
return "CURAND_STATUS_SUCCESS";
case CURAND_STATUS_VERSION_MISMATCH:
return "CURAND_STATUS_VERSION_MISMATCH";
case CURAND_STATUS_NOT_INITIALIZED:
return "CURAND_STATUS_NOT_INITIALIZED";
case CURAND_STATUS_ALLOCATION_FAILED:
return "CURAND_STATUS_ALLOCATION_FAILED";
case CURAND_STATUS_TYPE_ERROR:
return "CURAND_STATUS_TYPE_ERROR";
case CURAND_STATUS_OUT_OF_RANGE:
return "CURAND_STATUS_OUT_OF_RANGE";
case CURAND_STATUS_LENGTH_NOT_MULTIPLE:
return "CURAND_STATUS_LENGTH_NOT_MULTIPLE";
case CURAND_STATUS_DOUBLE_PRECISION_REQUIRED:
return "CURAND_STATUS_DOUBLE_PRECISION_REQUIRED";
case CURAND_STATUS_LAUNCH_FAILURE:
return "CURAND_STATUS_LAUNCH_FAILURE";
case CURAND_STATUS_PREEXISTING_FAILURE:
return "CURAND_STATUS_PREEXISTING_FAILURE";
case CURAND_STATUS_INITIALIZATION_FAILED:
return "CURAND_STATUS_INITIALIZATION_FAILED";
case CURAND_STATUS_ARCH_MISMATCH:
return "CURAND_STATUS_ARCH_MISMATCH";
case CURAND_STATUS_INTERNAL_ERROR:
return "CURAND_STATUS_INTERNAL_ERROR";
}
return "<unknown>";
}
}
namespace cutw
{
void
cuassert(const int code,
const char* const file,
const int line,
const bool abort)
{
if (code != cudaSuccess)
{
std::string msg = "cutw: cuassert: ";
msg += cudaGetErrorString(static_cast<cudaError_t>(code));
msg += " @ ";
msg += file;
msg += ":";
msg += std::to_string(line);
std::cerr << msg << std::endl;
if (abort)
{
assert(false);
std::terminate();
}
}
}
void
curandassert(const int code,
const char* const file,
const int line,
const bool abort)
{
if (code != CURAND_STATUS_SUCCESS)
{
std::string msg = "cutw: curandassert: ";
msg += curandGetErrorString(static_cast<curandStatus_t>(code));
msg += " @ ";
msg += file;
msg += ":";
msg += std::to_string(line);
std::cerr << msg << std::endl;
if (abort)
{
assert(false);
std::terminate();
}
}
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "error.h"
#include <cuda.h>
#include <curand_kernel.h>
#include <cassert>
#include <iostream>
#include <string>
namespace
{
const char* curandGetErrorString(const curandStatus_t error)
{
switch (error)
{
case CURAND_STATUS_SUCCESS:
return "CURAND_STATUS_SUCCESS";
case CURAND_STATUS_VERSION_MISMATCH:
return "CURAND_STATUS_VERSION_MISMATCH";
case CURAND_STATUS_NOT_INITIALIZED:
return "CURAND_STATUS_NOT_INITIALIZED";
case CURAND_STATUS_ALLOCATION_FAILED:
return "CURAND_STATUS_ALLOCATION_FAILED";
case CURAND_STATUS_TYPE_ERROR:
return "CURAND_STATUS_TYPE_ERROR";
case CURAND_STATUS_OUT_OF_RANGE:
return "CURAND_STATUS_OUT_OF_RANGE";
case CURAND_STATUS_LENGTH_NOT_MULTIPLE:
return "CURAND_STATUS_LENGTH_NOT_MULTIPLE";
case CURAND_STATUS_DOUBLE_PRECISION_REQUIRED:
return "CURAND_STATUS_DOUBLE_PRECISION_REQUIRED";
case CURAND_STATUS_LAUNCH_FAILURE:
return "CURAND_STATUS_LAUNCH_FAILURE";
case CURAND_STATUS_PREEXISTING_FAILURE:
return "CURAND_STATUS_PREEXISTING_FAILURE";
case CURAND_STATUS_INITIALIZATION_FAILED:
return "CURAND_STATUS_INITIALIZATION_FAILED";
case CURAND_STATUS_ARCH_MISMATCH:
return "CURAND_STATUS_ARCH_MISMATCH";
case CURAND_STATUS_INTERNAL_ERROR:
return "CURAND_STATUS_INTERNAL_ERROR";
}
return "<unknown>";
}
}
namespace cutw
{
void
cuassert(const int code,
const char* const file,
const int line,
const bool abort)
{
if (code != cudaSuccess)
{
std::string msg = "cutw: cuassert: ";
msg += cudaGetErrorString(static_cast<cudaError_t>(code));
msg += " @ ";
msg += file;
msg += ":";
msg += std::to_string(line);
std::cerr << msg << std::endl;
if (abort)
{
assert(false);
std::terminate();
}
}
}
void
curandassert(const int code,
const char* const file,
const int line,
const bool abort)
{
if (code != CURAND_STATUS_SUCCESS)
{
std::string msg = "cutw: curandassert: ";
msg += curandGetErrorString(static_cast<curandStatus_t>(code));
msg += " @ ";
msg += file;
msg += ":";
msg += std::to_string(line);
std::cerr << msg << std::endl;
if (abort)
{
assert(false);
std::terminate();
}
}
}
} | .file "tmpxft_000d595e_00000000-6_error.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3890:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3890:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CURAND_STATUS_SUCCESS"
.LC1:
.string "<unknown>"
.LC2:
.string "CURAND_STATUS_NOT_INITIALIZED"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "CURAND_STATUS_ALLOCATION_FAILED"
.section .rodata.str1.1
.LC4:
.string "CURAND_STATUS_TYPE_ERROR"
.LC5:
.string "CURAND_STATUS_OUT_OF_RANGE"
.section .rodata.str1.8
.align 8
.LC6:
.string "CURAND_STATUS_LENGTH_NOT_MULTIPLE"
.align 8
.LC7:
.string "CURAND_STATUS_DOUBLE_PRECISION_REQUIRED"
.section .rodata.str1.1
.LC8:
.string "CURAND_STATUS_LAUNCH_FAILURE"
.section .rodata.str1.8
.align 8
.LC9:
.string "CURAND_STATUS_PREEXISTING_FAILURE"
.align 8
.LC10:
.string "CURAND_STATUS_INITIALIZATION_FAILED"
.section .rodata.str1.1
.LC11:
.string "CURAND_STATUS_ARCH_MISMATCH"
.LC12:
.string "CURAND_STATUS_INTERNAL_ERROR"
.section .rodata.str1.8
.align 8
.LC13:
.string "CURAND_STATUS_VERSION_MISMATCH"
.text
.globl _ZN40_GLOBAL__N__7a962cdd_8_error_cu_f67a015120curandGetErrorStringE12curandStatus
.hidden _ZN40_GLOBAL__N__7a962cdd_8_error_cu_f67a015120curandGetErrorStringE12curandStatus
.type _ZN40_GLOBAL__N__7a962cdd_8_error_cu_f67a015120curandGetErrorStringE12curandStatus, @function
_ZN40_GLOBAL__N__7a962cdd_8_error_cu_f67a015120curandGetErrorStringE12curandStatus:
.LFB3885:
.cfi_startproc
endbr64
cmpl $106, %edi
ja .L4
cmpl $99, %edi
jbe .L23
subl $100, %edi
cmpl $6, %edi
ja .L7
movl %edi, %edi
leaq .L9(%rip), %rdx
movslq (%rdx,%rdi,4), %rax
addq %rdx, %rax
notrack jmp *%rax
.section .rodata
.align 4
.align 4
.L9:
.long .L17-.L9
.long .L14-.L9
.long .L13-.L9
.long .L12-.L9
.long .L11-.L9
.long .L10-.L9
.long .L8-.L9
.text
.L23:
testl %edi, %edi
leaq .LC0(%rip), %rax
leaq .LC1(%rip), %rdx
cmovne %rdx, %rax
ret
.L14:
leaq .LC2(%rip), %rax
ret
.L7:
leaq .LC1(%rip), %rax
ret
.L4:
leaq .LC10(%rip), %rax
cmpl $203, %edi
je .L3
jbe .L24
leaq .LC11(%rip), %rax
cmpl $204, %edi
je .L3
cmpl $999, %edi
leaq .LC12(%rip), %rax
leaq .LC1(%rip), %rdx
cmovne %rdx, %rax
ret
.L24:
leaq .LC8(%rip), %rax
cmpl $201, %edi
je .L3
cmpl $202, %edi
leaq .LC9(%rip), %rax
leaq .LC1(%rip), %rdx
cmovne %rdx, %rax
ret
.L13:
leaq .LC3(%rip), %rax
ret
.L12:
leaq .LC4(%rip), %rax
ret
.L11:
leaq .LC5(%rip), %rax
ret
.L10:
leaq .LC6(%rip), %rax
ret
.L8:
leaq .LC7(%rip), %rax
ret
.L17:
leaq .LC13(%rip), %rax
.L3:
ret
.cfi_endproc
.LFE3885:
.size _ZN40_GLOBAL__N__7a962cdd_8_error_cu_f67a015120curandGetErrorStringE12curandStatus, .-_ZN40_GLOBAL__N__7a962cdd_8_error_cu_f67a015120curandGetErrorStringE12curandStatus
.section .rodata.str1.1
.LC14:
.string "precalc_xorwow_matrix"
.LC15:
.string "precalc_xorwow_offset_matrix"
.LC16:
.string "mrg32k3aM1"
.LC17:
.string "mrg32k3aM2"
.LC18:
.string "mrg32k3aM1SubSeq"
.LC19:
.string "mrg32k3aM2SubSeq"
.LC20:
.string "mrg32k3aM1Seq"
.LC21:
.string "mrg32k3aM2Seq"
.LC22:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3913:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3913:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_,"axG",@progbits,_ZNSt8__detail18__to_chars_10_implIjEEvPcjT_,comdat
.weak _ZNSt8__detail18__to_chars_10_implIjEEvPcjT_
.type _ZNSt8__detail18__to_chars_10_implIjEEvPcjT_, @function
_ZNSt8__detail18__to_chars_10_implIjEEvPcjT_:
.LFB4076:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movl %edx, %ecx
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
movabsq $3688503277381496880, %rax
movabsq $3976738051646829616, %rdx
movq %rax, (%rsp)
movq %rdx, 8(%rsp)
movabsq $3544667369688283184, %rax
movabsq $3832902143785906737, %rdx
movq %rax, 16(%rsp)
movq %rdx, 24(%rsp)
movabsq $4121136918051239473, %rax
movabsq $3689066235924983858, %rdx
movq %rax, 32(%rsp)
movq %rdx, 40(%rsp)
movabsq $3977301010190316594, %rax
movabsq $3545230328231770162, %rdx
movq %rax, 48(%rsp)
movq %rdx, 56(%rsp)
movabsq $3833465102329393715, %rax
movabsq $4121699876594726451, %rdx
movq %rax, 64(%rsp)
movq %rdx, 72(%rsp)
movabsq $3689629194468470836, %rax
movabsq $3977863968733803572, %rdx
movq %rax, 80(%rsp)
movq %rdx, 88(%rsp)
movabsq $3545793286775257140, %rax
movabsq $3834028060872880693, %rdx
movq %rax, 96(%rsp)
movq %rdx, 104(%rsp)
movabsq $4122262835138213429, %rax
movabsq $3690192153011957814, %rdx
movq %rax, 112(%rsp)
movq %rdx, 120(%rsp)
movabsq $3978426927277290550, %rax
movabsq $3546356245318744118, %rdx
movq %rax, 128(%rsp)
movq %rdx, 136(%rsp)
movabsq $3834591019416367671, %rax
movabsq $4122825793681700407, %rdx
movq %rax, 144(%rsp)
movq %rdx, 152(%rsp)
movabsq $3690755111555444792, %rax
movabsq $3978989885820777528, %rdx
movq %rax, 160(%rsp)
movq %rdx, 168(%rsp)
movabsq $3546919203862231096, %rax
movabsq $3835153977959854649, %rdx
movq %rax, 176(%rsp)
movq %rdx, 184(%rsp)
movabsq $4122263930388298034, %rax
movabsq $16106987313379638, %rdx
movq %rax, 185(%rsp)
movq %rdx, 193(%rsp)
subl $1, %esi
cmpl $99, %ecx
jbe .L28
.L29:
movl %ecx, %edx
imulq $1374389535, %rdx, %rdx
shrq $37, %rdx
imull $100, %edx, %r8d
movl %ecx, %eax
subl %r8d, %eax
addl %eax, %eax
movl %ecx, %r8d
movl %edx, %ecx
movl %esi, %edx
leal 1(%rax), %r9d
movzbl (%rsp,%r9), %r9d
movb %r9b, (%rdi,%rdx)
leal -1(%rsi), %edx
movl %eax, %eax
movzbl (%rsp,%rax), %eax
movb %al, (%rdi,%rdx)
subl $2, %esi
cmpl $9999, %r8d
ja .L29
.L28:
leal 48(%rcx), %eax
cmpl $9, %ecx
jbe .L31
addl %ecx, %ecx
leal 1(%rcx), %eax
movzbl (%rsp,%rax), %eax
movb %al, 1(%rdi)
movl %ecx, %ecx
movzbl (%rsp,%rcx), %eax
.L31:
movb %al, (%rdi)
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4076:
.size _ZNSt8__detail18__to_chars_10_implIjEEvPcjT_, .-_ZNSt8__detail18__to_chars_10_implIjEEvPcjT_
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag:
.LFB4297:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
subq %rsi, %rdx
movq %rdx, %rbp
movq %rdx, (%rsp)
cmpq $15, %rdx
ja .L43
movq (%rdi), %rdi
cmpq $1, %rdx
jne .L39
movzbl (%rsi), %eax
movb %al, (%rdi)
.L40:
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L44
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
movq %rsp, %rsi
movl $0, %edx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %rdi
movq %rax, (%rbx)
movq (%rsp), %rax
movq %rax, 16(%rbx)
.L38:
movq %rbp, %rdx
movq %r12, %rsi
call memcpy@PLT
jmp .L40
.L39:
testq %rdx, %rdx
je .L40
jmp .L38
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4297:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.section .rodata.str1.1
.LC23:
.string "cutw: curandassert: "
.LC24:
.string "basic_string::append"
.LC25:
.string " @ "
.LC26:
.string ":"
.text
.globl _ZN4cutw12curandassertEiPKcib
.type _ZN4cutw12curandassertEiPKcib, @function
_ZN4cutw12curandassertEiPKcib:
.LFB3887:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3887
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
testl %edi, %edi
jne .L86
.L45:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L87
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L86:
.cfi_restore_state
movl %edi, %ebx
movq %rsi, %r12
movl %edx, %r14d
movl %ecx, %ebp
movq %rsp, %rdi
leaq 16(%rsp), %rax
movq %rax, (%rsp)
leaq 20+.LC23(%rip), %rdx
leaq -20(%rdx), %rsi
.LEHB0:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.LEHE0:
movl %ebx, %edi
call _ZN40_GLOBAL__N__7a962cdd_8_error_cu_f67a015120curandGetErrorStringE12curandStatus
movq %rax, %rbx
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movabsq $4611686018427387903, %rax
subq 8(%rsp), %rax
cmpq %rdx, %rax
jb .L88
movq %rsp, %rdi
movq %rbx, %rsi
.LEHB1:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm@PLT
jmp .L89
.L88:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L90
leaq .LC24(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L82:
endbr64
movq %rax, %rbx
jmp .L75
.L90:
call __stack_chk_fail@PLT
.L89:
movabsq $4611686018427387903, %rax
subq 8(%rsp), %rax
cmpq $2, %rax
jbe .L91
movq %rsp, %rdi
movl $3, %edx
leaq .LC25(%rip), %rsi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm@PLT
jmp .L92
.L91:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L93
leaq .LC24(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L93:
call __stack_chk_fail@PLT
.L92:
movq %r12, %rdi
call strlen@PLT
movq %rax, %rdx
movabsq $4611686018427387903, %rax
subq 8(%rsp), %rax
cmpq %rdx, %rax
jb .L94
movq %rsp, %rdi
movq %r12, %rsi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm@PLT
jmp .L95
.L94:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L96
leaq .LC24(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L96:
call __stack_chk_fail@PLT
.L95:
movabsq $4611686018427387903, %rax
cmpq %rax, 8(%rsp)
je .L97
movq %rsp, %rdi
movl $1, %edx
leaq .LC26(%rip), %rsi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm@PLT
jmp .L98
.L97:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L99
leaq .LC24(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.LEHE1:
.L99:
call __stack_chk_fail@PLT
.L98:
movl %r14d, %r13d
shrl $31, %r13d
movl %r14d, %r12d
negl %r12d
cmovs %r14d, %r12d
cmpl $9, %r12d
jbe .L78
cmpl $99, %r12d
jbe .L79
cmpl $999, %r12d
jbe .L80
cmpl $9999, %r12d
jbe .L81
movl %r12d, %eax
movl $1, %ebx
movabsq $3777893186295716171, %rcx
.L61:
movl %eax, %eax
mulq %rcx
shrq $11, %rdx
movl %edx, %eax
addl $4, %ebx
cmpl $9, %edx
jbe .L57
cmpl $99, %edx
jbe .L58
cmpl $999, %edx
jbe .L59
cmpl $9999, %edx
ja .L61
.L60:
addl $3, %ebx
jmp .L57
.L79:
movl $1, %ebx
.L58:
addl $1, %ebx
.L57:
leaq 32(%rsp), %rdi
leaq 48(%rsp), %rax
movq %rax, 32(%rsp)
leal 0(%r13,%rbx), %esi
movl $45, %edx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructEmc@PLT
movzbl %r13b, %edi
addq 32(%rsp), %rdi
movl %r12d, %edx
movl %ebx, %esi
call _ZNSt8__detail18__to_chars_10_implIjEEvPcjT_
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movabsq $4611686018427387903, %rax
subq 8(%rsp), %rax
cmpq %rdx, %rax
jb .L100
movq %rsp, %rdi
.LEHB2:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm@PLT
jmp .L101
.L80:
movl $1, %ebx
.L59:
addl $2, %ebx
jmp .L57
.L81:
movl $1, %ebx
jmp .L60
.L78:
movl $1, %ebx
jmp .L57
.L100:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L102
leaq .LC24(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.LEHE2:
.L83:
endbr64
movq %rax, %rbx
leaq 32(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L75:
movq %rsp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
je .L76
call __stack_chk_fail@PLT
.L102:
call __stack_chk_fail@PLT
.L101:
movq 32(%rsp), %rdi
leaq 48(%rsp), %rax
cmpq %rax, %rdi
je .L67
movq 48(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L67:
movq 8(%rsp), %rdx
movq (%rsp), %rsi
leaq _ZSt4cerr(%rip), %rdi
.LEHB3:
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L103
cmpb $0, 56(%r12)
je .L70
movzbl 67(%r12), %esi
.L71:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L104
.L103:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L105
call _ZSt16__throw_bad_castv@PLT
.L105:
call __stack_chk_fail@PLT
.L70:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L71
.L104:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.LEHE3:
testb %bpl, %bpl
jne .L106
movq (%rsp), %rdi
leaq 16(%rsp), %rax
cmpq %rax, %rdi
je .L45
movq 16(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
jmp .L45
.L106:
call _ZSt9terminatev@PLT
.L76:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L87:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3887:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3887:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3887-.LLSDACSB3887
.LLSDACSB3887:
.uleb128 .LEHB0-.LFB3887
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3887
.uleb128 .LEHE1-.LEHB1
.uleb128 .L82-.LFB3887
.uleb128 0
.uleb128 .LEHB2-.LFB3887
.uleb128 .LEHE2-.LEHB2
.uleb128 .L83-.LFB3887
.uleb128 0
.uleb128 .LEHB3-.LFB3887
.uleb128 .LEHE3-.LEHB3
.uleb128 .L82-.LFB3887
.uleb128 0
.uleb128 .LEHB4-.LFB3887
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE3887:
.text
.size _ZN4cutw12curandassertEiPKcib, .-_ZN4cutw12curandassertEiPKcib
.section .rodata.str1.1
.LC27:
.string "cutw: cuassert: "
.text
.globl _ZN4cutw8cuassertEiPKcib
.type _ZN4cutw8cuassertEiPKcib, @function
_ZN4cutw8cuassertEiPKcib:
.LFB3886:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3886
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
testl %edi, %edi
jne .L148
.L107:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L149
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L148:
.cfi_restore_state
movl %edi, %ebx
movq %rsi, %r12
movl %edx, %r14d
movl %ecx, %ebp
movq %rsp, %rdi
leaq 16(%rsp), %rax
movq %rax, (%rsp)
leaq 16+.LC27(%rip), %rdx
leaq -16(%rdx), %rsi
.LEHB5:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.LEHE5:
movl %ebx, %edi
.LEHB6:
call cudaGetErrorString@PLT
movq %rax, %rbx
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movabsq $4611686018427387903, %rax
subq 8(%rsp), %rax
cmpq %rdx, %rax
jb .L150
movq %rsp, %rdi
movq %rbx, %rsi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm@PLT
jmp .L151
.L150:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L152
leaq .LC24(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L144:
endbr64
movq %rax, %rbx
jmp .L137
.L152:
call __stack_chk_fail@PLT
.L151:
movabsq $4611686018427387903, %rax
subq 8(%rsp), %rax
cmpq $2, %rax
jbe .L153
movq %rsp, %rdi
movl $3, %edx
leaq .LC25(%rip), %rsi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm@PLT
jmp .L154
.L153:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L155
leaq .LC24(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L155:
call __stack_chk_fail@PLT
.L154:
movq %r12, %rdi
call strlen@PLT
movq %rax, %rdx
movabsq $4611686018427387903, %rax
subq 8(%rsp), %rax
cmpq %rdx, %rax
jb .L156
movq %rsp, %rdi
movq %r12, %rsi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm@PLT
jmp .L157
.L156:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L158
leaq .LC24(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L158:
call __stack_chk_fail@PLT
.L157:
movabsq $4611686018427387903, %rax
cmpq %rax, 8(%rsp)
je .L159
movq %rsp, %rdi
movl $1, %edx
leaq .LC26(%rip), %rsi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm@PLT
jmp .L160
.L159:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L161
leaq .LC24(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.LEHE6:
.L161:
call __stack_chk_fail@PLT
.L160:
movl %r14d, %r13d
shrl $31, %r13d
movl %r14d, %r12d
negl %r12d
cmovs %r14d, %r12d
cmpl $9, %r12d
jbe .L140
cmpl $99, %r12d
jbe .L141
cmpl $999, %r12d
jbe .L142
cmpl $9999, %r12d
jbe .L143
movl %r12d, %eax
movl $1, %ebx
movabsq $3777893186295716171, %rcx
.L123:
movl %eax, %eax
mulq %rcx
shrq $11, %rdx
movl %edx, %eax
addl $4, %ebx
cmpl $9, %edx
jbe .L119
cmpl $99, %edx
jbe .L120
cmpl $999, %edx
jbe .L121
cmpl $9999, %edx
ja .L123
.L122:
addl $3, %ebx
jmp .L119
.L141:
movl $1, %ebx
.L120:
addl $1, %ebx
.L119:
leaq 32(%rsp), %rdi
leaq 48(%rsp), %rax
movq %rax, 32(%rsp)
leal 0(%r13,%rbx), %esi
movl $45, %edx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructEmc@PLT
movzbl %r13b, %edi
addq 32(%rsp), %rdi
movl %r12d, %edx
movl %ebx, %esi
call _ZNSt8__detail18__to_chars_10_implIjEEvPcjT_
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movabsq $4611686018427387903, %rax
subq 8(%rsp), %rax
cmpq %rdx, %rax
jb .L162
movq %rsp, %rdi
.LEHB7:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm@PLT
jmp .L163
.L142:
movl $1, %ebx
.L121:
addl $2, %ebx
jmp .L119
.L143:
movl $1, %ebx
jmp .L122
.L140:
movl $1, %ebx
jmp .L119
.L162:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L164
leaq .LC24(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.LEHE7:
.L145:
endbr64
movq %rax, %rbx
leaq 32(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L137:
movq %rsp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
je .L138
call __stack_chk_fail@PLT
.L164:
call __stack_chk_fail@PLT
.L163:
movq 32(%rsp), %rdi
leaq 48(%rsp), %rax
cmpq %rax, %rdi
je .L129
movq 48(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L129:
movq 8(%rsp), %rdx
movq (%rsp), %rsi
leaq _ZSt4cerr(%rip), %rdi
.LEHB8:
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L165
cmpb $0, 56(%r12)
je .L132
movzbl 67(%r12), %esi
.L133:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L166
.L165:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L167
call _ZSt16__throw_bad_castv@PLT
.L167:
call __stack_chk_fail@PLT
.L132:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L133
.L166:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.LEHE8:
testb %bpl, %bpl
jne .L168
movq (%rsp), %rdi
leaq 16(%rsp), %rax
cmpq %rax, %rdi
je .L107
movq 16(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
jmp .L107
.L168:
call _ZSt9terminatev@PLT
.L138:
movq %rbx, %rdi
.LEHB9:
call _Unwind_Resume@PLT
.LEHE9:
.L149:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3886:
.section .gcc_except_table
.LLSDA3886:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3886-.LLSDACSB3886
.LLSDACSB3886:
.uleb128 .LEHB5-.LFB3886
.uleb128 .LEHE5-.LEHB5
.uleb128 0
.uleb128 0
.uleb128 .LEHB6-.LFB3886
.uleb128 .LEHE6-.LEHB6
.uleb128 .L144-.LFB3886
.uleb128 0
.uleb128 .LEHB7-.LFB3886
.uleb128 .LEHE7-.LEHB7
.uleb128 .L145-.LFB3886
.uleb128 0
.uleb128 .LEHB8-.LFB3886
.uleb128 .LEHE8-.LEHB8
.uleb128 .L144-.LFB3886
.uleb128 0
.uleb128 .LEHB9-.LFB3886
.uleb128 .LEHE9-.LEHB9
.uleb128 0
.uleb128 0
.LLSDACSE3886:
.text
.size _ZN4cutw8cuassertEiPKcib, .-_ZN4cutw8cuassertEiPKcib
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.